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| author | Luka Perkov <luka@openwrt.org> | 2014-08-08 13:38:31 +0000 |
|---|---|---|
| committer | Luka Perkov <luka@openwrt.org> | 2014-08-08 13:38:31 +0000 |
| commit | 1e00993cd8087ca0d27232be91fd470cd958083e (patch) | |
| tree | 02a9dcf85003ca8dc045dc0244d3378648ff3788 /target/linux/imx6/patches-3.10/0010-ARM-imx6q-Add-PCIe-bits-to-GPR-syscon-definition.patch | |
| parent | 9fd45ba9a76d1db66890bce6af6411e54780b9d4 (diff) | |
| download | upstream-1e00993cd8087ca0d27232be91fd470cd958083e.tar.gz upstream-1e00993cd8087ca0d27232be91fd470cd958083e.tar.bz2 upstream-1e00993cd8087ca0d27232be91fd470cd958083e.zip | |
imx6: drop 3.10 support
Signed-off-by: Luka Perkov <luka@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@42075 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/imx6/patches-3.10/0010-ARM-imx6q-Add-PCIe-bits-to-GPR-syscon-definition.patch')
| -rw-r--r-- | target/linux/imx6/patches-3.10/0010-ARM-imx6q-Add-PCIe-bits-to-GPR-syscon-definition.patch | 37 |
1 files changed, 0 insertions, 37 deletions
diff --git a/target/linux/imx6/patches-3.10/0010-ARM-imx6q-Add-PCIe-bits-to-GPR-syscon-definition.patch b/target/linux/imx6/patches-3.10/0010-ARM-imx6q-Add-PCIe-bits-to-GPR-syscon-definition.patch deleted file mode 100644 index 19ca079dc9..0000000000 --- a/target/linux/imx6/patches-3.10/0010-ARM-imx6q-Add-PCIe-bits-to-GPR-syscon-definition.patch +++ /dev/null @@ -1,37 +0,0 @@ -From: Sean Cross <xobs@kosagi.com> -Subject: [PATCH 1/2] ARM: imx6q: Add PCIe bits to GPR syscon definition - -PCIe requires additional bits be defined for GPR8 and GPR12. - -Signed-off-by: Sean Cross <xobs@kosagi.com> -Signed-off-by: Shawn Guo <shawn.guo@linaro.org> -Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> ---- - include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 8 ++++++++ - 1 file changed, 8 insertions(+) - ---- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h -+++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h -@@ -241,6 +241,12 @@ - - #define IMX6Q_GPR5_L2_CLK_STOP BIT(8) - -+#define IMX6Q_GPR8_TX_SWING_LOW (0x7f << 25) -+#define IMX6Q_GPR8_TX_SWING_FULL (0x7f << 18) -+#define IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB (0x3f << 12) -+#define IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB (0x3f << 6) -+#define IMX6Q_GPR8_TX_DEEMPH_GEN1 (0x3f << 0) -+ - #define IMX6Q_GPR9_TZASC2_BYP BIT(1) - #define IMX6Q_GPR9_TZASC1_BYP BIT(0) - -@@ -273,7 +279,9 @@ - #define IMX6Q_GPR12_ARMP_AHB_CLK_EN BIT(26) - #define IMX6Q_GPR12_ARMP_ATB_CLK_EN BIT(25) - #define IMX6Q_GPR12_ARMP_APB_CLK_EN BIT(24) -+#define IMX6Q_GPR12_DEVICE_TYPE (0xf << 12) - #define IMX6Q_GPR12_PCIE_CTL_2 BIT(10) -+#define IMX6Q_GPR12_LOS_LEVEL (0x1f << 4) - - #define IMX6Q_GPR13_SDMA_STOP_REQ BIT(30) - #define IMX6Q_GPR13_CAN2_STOP_REQ BIT(29) |