oxnas: add experimental support for Linux 5.10

PCIe still reports link-down for some reason, RAID fails to assemble
despite SATA looking good (maybe a generic problem with RAID?)

Signed-off-by: Daniel Golle <daniel@makrotopia.org>

11 files changed, 998 insertions, 0 deletions

diff --git a/target/linux/oxnas/patches-5.10/010-pogoplug-series-3.patch b/target/linux/oxnas/patches-5.10/010-pogoplug-series-3.patch
new file mode 100644
index 0000000000..44102352af
--- /dev/null
+++ b/target/linux/oxnas/patches-5.10/010-pogoplug-series-3.patch
@@ -0,0 +1,82 @@
+- add compatible string
+- add console to bootargs
+- add led aliases
+- adjust nand partition table
+---
+--- a/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts
++++ b/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts
+@@ -11,10 +11,10 @@
+ / {
+ 	model = "Cloud Engines PogoPlug Series 3";
+ 
+-	compatible = "cloudengines,pogoplugv3", "oxsemi,ox820";
++	compatible = "cloudengines,pogoplug-series-3", "cloudengines,pogoplugv3", "oxsemi,ox820";
+ 
+ 	chosen {
+-		bootargs = "earlyprintk";
++		bootargs = "earlyprintk console=ttyS0,115200";
+ 		stdout-path = "serial0:115200n8";
+ 	};
+ 
+@@ -27,24 +27,28 @@
+ 		serial0 = &uart0;
+ 		gpio0 = &gpio0;
+ 		gpio1 = &gpio1;
++		led-boot = &led_status;
++		led-failsafe = &led_warn;
++		led-running = &led_act;
++		led-upgrade = &led_warn;
+ 	};
+ 
+ 	leds {
+ 		compatible = "gpio-leds";
+ 
+-		blue {
++		led_status: blue {
+ 			label = "pogoplug:blue";
+ 			gpios = <&gpio0 2 0>;
+ 			default-state = "keep";
+ 		};
+ 
+-		orange {
++		led_warn: orange {
+ 			label = "pogoplug:orange";
+ 			gpios = <&gpio1 16 1>;
+ 			default-state = "keep";
+ 		};
+ 
+-		green {
++		led_act: green {
+ 			label = "pogoplug:green";
+ 			gpios = <&gpio1 17 1>;
+ 			default-state = "keep";
+@@ -73,11 +77,27 @@
+ 		nand-ecc-algo = "hamming";
+ 
+ 		partition@0 {
+-			label = "boot";
+-			reg = <0x00000000 0x00e00000>;
++			label = "stage1";
++			reg = <0x00000000 0x00040000>;
+ 			read-only;
+ 		};
+ 
++		partition@40000 {
++			label = "u-boot";
++			reg = <0x00040000 0x00380000>;
++			read-only;
++		};
++
++		partition@3c0000 {
++			label = "u-boot-env";
++			reg = <0x003c0000 0x00080000>;
++		};
++
++		partition@440000 {
++			label = "kernel";
++			reg = <0x00440000 0x009c0000>;
++		};
++
+ 		partition@e00000 {
+ 			label = "ubi";
+ 			reg = <0x00e00000 0x07200000>;
diff --git a/target/linux/oxnas/patches-5.10/050-ox820-remove-left-overs.patch b/target/linux/oxnas/patches-5.10/050-ox820-remove-left-overs.patch
new file mode 100644
index 0000000000..e30f328792
--- /dev/null
+++ b/target/linux/oxnas/patches-5.10/050-ox820-remove-left-overs.patch
@@ -0,0 +1,63 @@
+From 552ed4955c1fee1109bf5ba137dc35a411a1448c Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Fri, 1 Jun 2018 02:41:15 +0200
+Subject: [PATCH] arm: ox820: remove left-overs
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/clk/clk-oxnas.c                  |  2 --
+ include/dt-bindings/clock/oxsemi,ox820.h | 32 +++++++++++-------------
+ 2 files changed, 14 insertions(+), 20 deletions(-)
+
+--- a/drivers/clk/clk-oxnas.c
++++ b/drivers/clk/clk-oxnas.c
+@@ -29,8 +29,6 @@ struct oxnas_stdclk_data {
+ 	struct clk_hw_onecell_data *onecell_data;
+ 	struct clk_oxnas_gate **gates;
+ 	unsigned int ngates;
+-	struct clk_oxnas_pll **plls;
+-	unsigned int nplls;
+ };
+ 
+ /* Regmap offsets */
+--- a/include/dt-bindings/clock/oxsemi,ox820.h
++++ b/include/dt-bindings/clock/oxsemi,ox820.h
+@@ -6,24 +6,20 @@
+ #ifndef DT_CLOCK_OXSEMI_OX820_H
+ #define DT_CLOCK_OXSEMI_OX820_H
+ 
+-/* PLLs */
+-#define CLK_820_PLLA		0
+-#define CLK_820_PLLB		1
+-
+ /* Gate Clocks */
+-#define CLK_820_LEON		2
+-#define CLK_820_DMA_SGDMA	3
+-#define CLK_820_CIPHER		4
+-#define CLK_820_SD		5
+-#define CLK_820_SATA		6
+-#define CLK_820_AUDIO		7
+-#define CLK_820_USBMPH		8
+-#define CLK_820_ETHA		9
+-#define CLK_820_PCIEA		10
+-#define CLK_820_NAND		11
+-#define CLK_820_PCIEB		12
+-#define CLK_820_ETHB		13
+-#define CLK_820_REF600		14
+-#define CLK_820_USBDEV		15
++#define CLK_820_LEON		0
++#define CLK_820_DMA_SGDMA	1
++#define CLK_820_CIPHER		2
++#define CLK_820_SD		3
++#define CLK_820_SATA		4
++#define CLK_820_AUDIO		5
++#define CLK_820_USBMPH		6
++#define CLK_820_ETHA		7
++#define CLK_820_PCIEA		8
++#define CLK_820_NAND		9
++#define CLK_820_PCIEB		10
++#define CLK_820_ETHB		11
++#define CLK_820_REF600		12
++#define CLK_820_USBDEV		13
+ 
+ #endif /* DT_CLOCK_OXSEMI_OX820_H */
diff --git a/target/linux/oxnas/patches-5.10/100-oxnas-clk-plla-pllb.patch b/target/linux/oxnas/patches-5.10/100-oxnas-clk-plla-pllb.patch
new file mode 100644
index 0000000000..29a9036498
--- /dev/null
+++ b/target/linux/oxnas/patches-5.10/100-oxnas-clk-plla-pllb.patch
@@ -0,0 +1,273 @@
+--- a/drivers/clk/clk-oxnas.c
++++ b/drivers/clk/clk-oxnas.c
+@@ -5,19 +5,42 @@
+  * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
+  */
+ 
++#include <linux/clk.h>
++#include <linux/clkdev.h>
+ #include <linux/clk-provider.h>
+ #include <linux/kernel.h>
+ #include <linux/init.h>
++#include <linux/delay.h>
+ #include <linux/of.h>
+ #include <linux/of_device.h>
+ #include <linux/platform_device.h>
+ #include <linux/stringify.h>
+ #include <linux/regmap.h>
+ #include <linux/mfd/syscon.h>
++#include <linux/reset.h>
+ 
+ #include <dt-bindings/clock/oxsemi,ox810se.h>
+ #include <dt-bindings/clock/oxsemi,ox820.h>
+ 
++#define REF300_DIV_INT_SHIFT		8
++#define REF300_DIV_FRAC_SHIFT		0
++#define REF300_DIV_INT(val)		((val) << REF300_DIV_INT_SHIFT)
++#define REF300_DIV_FRAC(val)		((val) << REF300_DIV_FRAC_SHIFT)
++
++#define PLLB_BYPASS			1
++#define PLLB_ENSAT			3
++#define PLLB_OUTDIV			4
++#define PLLB_REFDIV			8
++#define PLLB_DIV_INT_SHIFT		8
++#define PLLB_DIV_FRAC_SHIFT		0
++#define PLLB_DIV_INT(val)		((val) << PLLB_DIV_INT_SHIFT)
++#define PLLB_DIV_FRAC(val)		((val) << PLLB_DIV_FRAC_SHIFT)
++
++#define PLLA_REFDIV_MASK		0x3F
++#define PLLA_REFDIV_SHIFT		8
++#define PLLA_OUTDIV_MASK		0x7
++#define PLLA_OUTDIV_SHIFT		4
++
+ /* Standard regmap gate clocks */
+ struct clk_oxnas_gate {
+ 	struct clk_hw hw;
+@@ -36,6 +59,135 @@ struct oxnas_stdclk_data {
+ #define CLK_SET_REGOFFSET	0x2c
+ #define CLK_CLR_REGOFFSET	0x30
+ 
++#define PLLA_CTRL0_REGOFFSET	0x1f0
++#define PLLA_CTRL1_REGOFFSET	0x1f4
++#define PLLB_CTRL0_REGOFFSET	0x1001f0
++#define MHZ (1000 * 1000)
++
++struct clk_oxnas_pll {
++	struct clk_hw hw;
++	struct device_node *devnode;
++	struct reset_control *rstc;
++	struct regmap *syscon;
++};
++
++#define to_clk_oxnas_pll(_hw) container_of(_hw, struct clk_oxnas_pll, hw)
++
++static unsigned long plla_clk_recalc_rate(struct clk_hw *hw,
++	unsigned long parent_rate)
++{
++	struct clk_oxnas_pll *plla = to_clk_oxnas_pll(hw);
++	unsigned long fin = parent_rate;
++	unsigned long refdiv, outdiv;
++	unsigned int pll0, fbdiv;
++
++	BUG_ON(regmap_read(plla->syscon, PLLA_CTRL0_REGOFFSET, &pll0));
++
++	refdiv = (pll0 >> PLLA_REFDIV_SHIFT) & PLLA_REFDIV_MASK;
++	refdiv += 1;
++	outdiv = (pll0 >> PLLA_OUTDIV_SHIFT) & PLLA_OUTDIV_MASK;
++	outdiv += 1;
++
++	BUG_ON(regmap_read(plla->syscon, PLLA_CTRL1_REGOFFSET, &fbdiv));
++	/* seems we will not be here when pll is bypassed, so ignore this
++	 * case */
++
++	return fin / MHZ * fbdiv / (refdiv * outdiv) / 32768 * MHZ;
++}
++
++static const char *pll_clk_parents[] = {
++	"oscillator",
++};
++
++static struct clk_ops plla_ops = {
++	.recalc_rate = plla_clk_recalc_rate,
++};
++
++static struct clk_init_data clk_plla_init = {
++	.name = "plla",
++	.ops = &plla_ops,
++	.parent_names = pll_clk_parents,
++	.num_parents = ARRAY_SIZE(pll_clk_parents),
++};
++
++static int pllb_clk_is_prepared(struct clk_hw *hw)
++{
++	struct clk_oxnas_pll *pllb = to_clk_oxnas_pll(hw);
++
++	return !!pllb->rstc;
++}
++
++static int pllb_clk_prepare(struct clk_hw *hw)
++{
++	struct clk_oxnas_pll *pllb = to_clk_oxnas_pll(hw);
++
++	pllb->rstc = of_reset_control_get(pllb->devnode, NULL);
++
++	return IS_ERR(pllb->rstc) ? PTR_ERR(pllb->rstc) : 0;
++}
++
++static void pllb_clk_unprepare(struct clk_hw *hw)
++{
++	struct clk_oxnas_pll *pllb = to_clk_oxnas_pll(hw);
++
++	BUG_ON(IS_ERR(pllb->rstc));
++
++	reset_control_put(pllb->rstc);
++	pllb->rstc = NULL;
++}
++
++static int pllb_clk_enable(struct clk_hw *hw)
++{
++	struct clk_oxnas_pll *pllb = to_clk_oxnas_pll(hw);
++
++	BUG_ON(IS_ERR(pllb->rstc));
++
++	/* put PLL into bypass */
++	regmap_update_bits(pllb->syscon, PLLB_CTRL0_REGOFFSET, BIT(PLLB_BYPASS), BIT(PLLB_BYPASS));
++	wmb();
++	udelay(10);
++	reset_control_assert(pllb->rstc);
++	udelay(10);
++	/* set PLL B control information */
++	regmap_write_bits(pllb->syscon, PLLB_CTRL0_REGOFFSET, 0xffff,
++			  (1 << PLLB_ENSAT) | (1 << PLLB_OUTDIV) | (2 << PLLB_REFDIV));
++	reset_control_deassert(pllb->rstc);
++	udelay(100);
++	regmap_update_bits(pllb->syscon, PLLB_CTRL0_REGOFFSET, BIT(PLLB_BYPASS), 0);
++
++	return 0;
++}
++
++static void pllb_clk_disable(struct clk_hw *hw)
++{
++	struct clk_oxnas_pll *pllb = to_clk_oxnas_pll(hw);
++
++	BUG_ON(IS_ERR(pllb->rstc));
++
++	/* put PLL into bypass */
++	regmap_update_bits(pllb->syscon, PLLB_CTRL0_REGOFFSET, BIT(PLLB_BYPASS), BIT(PLLB_BYPASS));
++
++	wmb();
++	udelay(10);
++
++	reset_control_assert(pllb->rstc);
++}
++
++static struct clk_ops pllb_ops = {
++	.prepare = pllb_clk_prepare,
++	.unprepare = pllb_clk_unprepare,
++	.is_prepared = pllb_clk_is_prepared,
++	.enable = pllb_clk_enable,
++	.disable = pllb_clk_disable,
++};
++
++static struct clk_init_data clk_pllb_init = {
++	.name = "pllb",
++	.ops = &pllb_ops,
++	.parent_names = pll_clk_parents,
++	.num_parents = ARRAY_SIZE(pll_clk_parents),
++};
++
+ static inline struct clk_oxnas_gate *to_clk_oxnas_gate(struct clk_hw *hw)
+ {
+ 	return container_of(hw, struct clk_oxnas_gate, hw);
+@@ -249,3 +401,42 @@ static struct platform_driver oxnas_stdc
+ 	},
+ };
+ builtin_platform_driver(oxnas_stdclk_driver);
++
++void __init oxnas_init_plla(struct device_node *np)
++{
++	struct clk *clk;
++	struct clk_oxnas_pll *plla;
++
++	plla = kmalloc(sizeof(*plla), GFP_KERNEL);
++	BUG_ON(!plla);
++
++	plla->syscon = syscon_node_to_regmap(of_get_parent(np));
++	plla->hw.init = &clk_plla_init;
++	plla->devnode = np;
++	plla->rstc = NULL;
++	clk = clk_register(NULL, &plla->hw);
++	BUG_ON(IS_ERR(clk));
++	/* mark it as enabled */
++	clk_prepare_enable(clk);
++	of_clk_add_provider(np, of_clk_src_simple_get, clk);
++}
++CLK_OF_DECLARE(oxnas_plla, "plxtech,nas782x-plla", oxnas_init_plla);
++
++void __init oxnas_init_pllb(struct device_node *np)
++{
++	struct clk *clk;
++	struct clk_oxnas_pll *pllb;
++
++	pllb = kmalloc(sizeof(*pllb), GFP_KERNEL);
++	BUG_ON(!pllb);
++
++	pllb->syscon = syscon_node_to_regmap(of_get_parent(np));
++	pllb->hw.init = &clk_pllb_init;
++	pllb->devnode = np;
++	pllb->rstc = NULL;
++
++	clk = clk_register(NULL, &pllb->hw);
++	BUG_ON(IS_ERR(clk));
++	of_clk_add_provider(np, of_clk_src_simple_get, clk);
++}
++CLK_OF_DECLARE(oxnas_pllb, "plxtech,nas782x-pllb", oxnas_init_pllb);
+--- a/arch/arm/boot/dts/ox820.dtsi
++++ b/arch/arm/boot/dts/ox820.dtsi
+@@ -61,12 +61,6 @@
+ 			clocks = <&osc>;
+ 		};
+ 
+-		plla: plla {
+-			compatible = "fixed-clock";
+-			#clock-cells = <0>;
+-			clock-frequency = <850000000>;
+-		};
+-
+ 		armclk: armclk {
+ 			compatible = "fixed-factor-clock";
+ 			#clock-cells = <0>;
+@@ -266,6 +260,19 @@
+ 					compatible = "oxsemi,ox820-stdclk", "oxsemi,ox810se-stdclk";
+ 					#clock-cells = <1>;
+ 				};
++
++				plla: plla {
++					compatible = "plxtech,nas782x-plla";
++					#clock-cells = <0>;
++					clocks = <&osc>;
++				};
++
++				pllb: pllb {
++					compatible = "plxtech,nas782x-pllb";
++					#clock-cells = <0>;
++					clocks = <&osc>;
++					resets = <&reset RESET_PLLB>;
++				};
+ 			};
+ 		};
+ 
+@@ -287,6 +294,13 @@
+ 				clocks = <&armclk>;
+ 			};
+ 
++			watchdog@620 {
++				compatible = "mpcore_wdt";
++				reg = <0x620 0x20>;
++				interrupts = <GIC_PPI 14 (GIC_CPU_MASK_RAW(3)|IRQ_TYPE_LEVEL_HIGH)>;
++				clocks = <&armclk>;
++			};
++
+ 			gic: gic@1000 {
+ 				compatible = "arm,arm11mp-gic";
+ 				interrupt-controller;
diff --git a/target/linux/oxnas/patches-5.10/150-oxnas-restart.patch b/target/linux/oxnas/patches-5.10/150-oxnas-restart.patch
new file mode 100644
index 0000000000..c5b07fd5a7
--- /dev/null
+++ b/target/linux/oxnas/patches-5.10/150-oxnas-restart.patch
@@ -0,0 +1,25 @@
+--- a/drivers/power/reset/Kconfig
++++ b/drivers/power/reset/Kconfig
+@@ -141,6 +141,12 @@ config POWER_RESET_OXNAS
+ 	help
+ 	  Restart support for OXNAS/PLXTECH OX820 SoC.
+ 
++config POWER_RESET_OXNAS
++	bool "OXNAS SoC restart driver"
++	depends on ARCH_OXNAS
++	help
++	  Restart support for OXNAS boards.
++
+ config POWER_RESET_PIIX4_POWEROFF
+ 	tristate "Intel PIIX4 power-off driver"
+ 	depends on PCI
+--- a/drivers/power/reset/Makefile
++++ b/drivers/power/reset/Makefile
+@@ -18,6 +18,7 @@ obj-$(CONFIG_POWER_RESET_QCOM_PON) += qc
+ obj-$(CONFIG_POWER_RESET_OCELOT_RESET) += ocelot-reset.o
+ obj-$(CONFIG_POWER_RESET_PIIX4_POWEROFF) += piix4-poweroff.o
+ obj-$(CONFIG_POWER_RESET_LTC2952) += ltc2952-poweroff.o
++obj-$(CONFIG_POWER_RESET_OXNAS) += oxnas-restart.o
+ obj-$(CONFIG_POWER_RESET_QNAP) += qnap-poweroff.o
+ obj-$(CONFIG_POWER_RESET_RESTART) += restart-poweroff.o
+ obj-$(CONFIG_POWER_RESET_ST) += st-poweroff.o
diff --git a/target/linux/oxnas/patches-5.10/320-oxnas-phy-pcie.patch b/target/linux/oxnas/patches-5.10/320-oxnas-phy-pcie.patch
new file mode 100644
index 0000000000..a590151e5c
--- /dev/null
+++ b/target/linux/oxnas/patches-5.10/320-oxnas-phy-pcie.patch
@@ -0,0 +1,44 @@
+--- a/arch/arm/boot/dts/ox820.dtsi
++++ b/arch/arm/boot/dts/ox820.dtsi
+@@ -247,6 +247,15 @@
+ 				};
+ 			};
+ 
++			pcie_phy: pcie-phy@a00000 {
++				compatible = "oxsemi,ox820-pcie-phy";
++				reg = <0xa00000 0x10>;
++				#phy-cells = <0>;
++				resets = <&reset RESET_PCIEPHY>;
++				reset-names = "phy";
++				status = "disabled";
++			};
++
+ 			sys: sys-ctrl@e00000 {
+ 				compatible = "oxsemi,ox820-sys-ctrl", "syscon", "simple-mfd";
+ 				reg = <0xe00000 0x200000>;
+--- a/drivers/phy/Kconfig
++++ b/drivers/phy/Kconfig
+@@ -35,6 +35,13 @@ config PHY_LPC18XX_USB_OTG
+ 	  This driver is need for USB0 support on LPC18xx/43xx and takes
+ 	  care of enabling and clock setup.
+ 
++config PHY_OXNAS
++	tristate "Oxford Semi. OX820 PCI-E PHY support"
++	depends on HAS_IOMEM && OF && (ARM || COMPILE_TEST)
++	select GENERIC_PHY
++	help
++	  This option enables support for OXNAS OX820 SoC PCIE PHY.
++
+ config PHY_PISTACHIO_USB
+ 	tristate "IMG Pistachio USB2.0 PHY driver"
+ 	depends on MACH_PISTACHIO
+--- a/drivers/phy/Makefile
++++ b/drivers/phy/Makefile
+@@ -6,6 +6,7 @@
+ obj-$(CONFIG_GENERIC_PHY)		+= phy-core.o
+ obj-$(CONFIG_GENERIC_PHY_MIPI_DPHY)	+= phy-core-mipi-dphy.o
+ obj-$(CONFIG_PHY_LPC18XX_USB_OTG)	+= phy-lpc18xx-usb-otg.o
++obj-$(CONFIG_PHY_OXNAS)			+= phy-oxnas-pcie.o
+ obj-$(CONFIG_PHY_XGENE)			+= phy-xgene.o
+ obj-$(CONFIG_PHY_PISTACHIO_USB)		+= phy-pistachio-usb.o
+ obj-$(CONFIG_USB_LGM_PHY)		+= phy-lgm-usb.o
diff --git a/target/linux/oxnas/patches-5.10/340-oxnas-pcie.patch b/target/linux/oxnas/patches-5.10/340-oxnas-pcie.patch
new file mode 100644
index 0000000000..01b5a188c3
--- /dev/null
+++ b/target/linux/oxnas/patches-5.10/340-oxnas-pcie.patch
@@ -0,0 +1,122 @@
+--- a/drivers/pci/controller/Kconfig
++++ b/drivers/pci/controller/Kconfig
+@@ -305,6 +305,11 @@ config PCIE_HISI_ERR
+ 	  Say Y here if you want error handling support
+ 	  for the PCIe controller's errors on HiSilicon HIP SoCs
+ 
++config PCIE_OXNAS
++	bool "PLX Oxnas PCIe controller"
++	depends on ARCH_OXNAS
++	select PCIEPORTBUS
++
+ source "drivers/pci/controller/dwc/Kconfig"
+ source "drivers/pci/controller/mobiveil/Kconfig"
+ source "drivers/pci/controller/cadence/Kconfig"
+--- a/drivers/pci/controller/Makefile
++++ b/drivers/pci/controller/Makefile
+@@ -27,6 +27,7 @@ obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rock
+ obj-$(CONFIG_PCIE_ROCKCHIP_EP) += pcie-rockchip-ep.o
+ obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie-rockchip-host.o
+ obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
++obj-$(CONFIG_PCIE_OXNAS) += pcie-oxnas.o
+ obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
+ obj-$(CONFIG_VMD) += vmd.o
+ obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
+--- a/arch/arm/boot/dts/ox820.dtsi
++++ b/arch/arm/boot/dts/ox820.dtsi
+@@ -289,7 +289,7 @@
+ 			#address-cells = <1>;
+ 			#size-cells = <1>;
+ 			compatible = "simple-bus";
+-			ranges = <0 0x47000000 0x1000000>;
++			ranges = <0 0x47000000 0x2000>;
+ 
+ 			scu: scu@0 {
+ 				compatible = "arm,arm11mp-scu";
+@@ -318,5 +318,86 @@
+ 				      <0x100 0x500>;
+ 			};
+ 		};
++
++		pcie0: pcie-controller@47c00000 {
++			compatible = "plxtech,nas782x-pcie";
++			device_type = "pci";
++			#address-cells = <3>;
++			#size-cells = <2>;
++
++			/*		flag & space	bus address	host address	size */
++			ranges = <	0x82000000	0 0x48000000	0x48000000	0 0x2000000
++					0xC2000000	0 0x4A000000	0x4A000000	0 0x1E00000
++					0x81000000	0 0x4BE00000	0x4BE00000	0 0x0100000
++					0x80000000	0 0x4BF00000	0x4BF00000	0 0x0100000>;
++
++			bus-range = <0x00 0x7f>;
++
++			/*	cfg			inbound translator	*/
++			reg =	<0x47c00000 0x1000>,	<0x47d00000 0x100>;
++
++			phys = <&pcie_phy>;
++			phy-names = "pcie-phy";
++
++			#interrupt-cells = <1>;
++			/* wild card mask, match all bus address & interrupt specifier */
++			/* format: bus address mask, interrupt specifier mask */
++			/* each bit 1 means need match, 0 means ignored when match */
++			interrupt-map-mask = <0 0 0 0>;
++			/* format: a list of: bus address, interrupt specifier,
++			 * parent interrupt controller & specifier */
++			interrupt-map = <0 0 0 0 &gic 0 19 0x304>;
++			gpios = <&gpio1 12 0>;
++			clocks = <&stdclk CLK_820_PCIEA>, <&pllb>;
++			clock-names = "pcie", "busclk";
++			resets = <&reset RESET_PCIEA>;
++			reset-names = "pcie";
++
++			plxtech,pcie-hcsl-bit = <2>;
++			plxtech,pcie-ctrl-offset = <0x120>;
++			plxtech,pcie-outbound-offset = <0x138>;
++			status = "disabled";
++		};
++
++		pcie1: pcie-controller@47e00000 {
++			compatible = "plxtech,nas782x-pcie";
++			device_type = "pci";
++			#address-cells = <3>;
++			#size-cells = <2>;
++
++			/*		flag & space	bus address	host address	size */
++			ranges = <	0x82000000	0 0x4C000000	0x4C000000	0 0x2000000
++					0xC2000000	0 0x4E000000	0x4E000000	0 0x1E00000
++					0x81000000	0 0x4FE00000	0x4FE00000	0 0x0100000
++					0x80000000	0 0x4FF00000	0x4FF00000	0 0x0100000>;
++
++			bus-range = <0x80 0xff>;
++
++			/*	cfg			inbound translator	*/
++			reg =	<0x47e00000 0x1000>,	<0x47f00000 0x100>;
++
++			phys = <&pcie_phy>;
++			phy-names = "pcie-phy";
++
++			#interrupt-cells = <1>;
++			/* wild card mask, match all bus address & interrupt specifier */
++			/* format: bus address mask, interrupt specifier mask */
++			/* each bit 1 means need match, 0 means ignored when match */
++			interrupt-map-mask = <0 0 0 0>;
++			/* format: a list of: bus address, interrupt specifier,
++			 * parent interrupt controller & specifier */
++			interrupt-map = <0 0 0 0 &gic 0 20 0x304>;
++
++			/* gpios = <&gpio1 12 0>; */
++			clocks = <&stdclk CLK_820_PCIEB>, <&pllb>;
++			clock-names = "pcie", "busclk";
++			resets = <&reset RESET_PCIEB>;
++			reset-names = "pcie";
++
++			plxtech,pcie-hcsl-bit = <3>;
++			plxtech,pcie-ctrl-offset = <0x124>;
++			plxtech,pcie-outbound-offset = <0x174>;
++			status = "disabled";
++		};
+ 	};
+ };
diff --git a/target/linux/oxnas/patches-5.10/500-oxnas-sata.patch b/target/linux/oxnas/patches-5.10/500-oxnas-sata.patch
new file mode 100644
index 0000000000..d3ec2e2d48
--- /dev/null
+++ b/target/linux/oxnas/patches-5.10/500-oxnas-sata.patch
@@ -0,0 +1,60 @@
+--- a/drivers/ata/Kconfig
++++ b/drivers/ata/Kconfig
+@@ -568,6 +568,14 @@ config SATA_VITESSE
+ 
+ 	  If unsure, say N.
+ 
++config SATA_OXNAS
++	tristate "PLXTECH NAS782X SATA support"
++	select SATA_HOST
++	help
++	  This option enables support for Nas782x Serial ATA controller.
++
++	  If unsure, say N.
++
+ comment "PATA SFF controllers with BMDMA"
+ 
+ config PATA_ALI
+--- a/drivers/ata/Makefile
++++ b/drivers/ata/Makefile
+@@ -46,6 +46,7 @@ obj-$(CONFIG_SATA_SVW)		+= sata_svw.o
+ obj-$(CONFIG_SATA_ULI)		+= sata_uli.o
+ obj-$(CONFIG_SATA_VIA)		+= sata_via.o
+ obj-$(CONFIG_SATA_VITESSE)	+= sata_vsc.o
++obj-$(CONFIG_SATA_OXNAS)	+= sata_oxnas.o
+ 
+ # SFF PATA w/ BMDMA
+ obj-$(CONFIG_PATA_ALI)		+= pata_ali.o
+--- a/arch/arm/boot/dts/ox820.dtsi
++++ b/arch/arm/boot/dts/ox820.dtsi
+@@ -399,5 +399,20 @@
+ 			plxtech,pcie-outbound-offset = <0x174>;
+ 			status = "disabled";
+ 		};
++
++		sata: sata@45900000 {
++			compatible = "plxtech,nas782x-sata";
++				/*	ports		dmactl		sgdma	*/
++			reg = <0x45900000 0x20000>, <0x459A0000 0x40>, <0x459B0000 0x20>,
++				/*	core		phy		descriptors (optional)	*/
++				<0x459E0000 0x2000>, <0x44900000 0x0C>, <0x50000000 0x1000>;
++			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&stdclk CLK_820_SATA>;
++			resets = <&reset RESET_SATA>, <&reset RESET_SATA_LINK>, <&reset RESET_SATA_PHY>;
++			reset-names = "sata", "link", "phy";
++			nr-ports = <1>;
++			status = "disabled";
++		};
++
+ 	};
+ };
+--- a/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts
++++ b/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts
+@@ -111,3 +111,7 @@
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&pinctrl_etha_mdio>;
+ };
++
++&sata {
++	status = "okay";
++};
diff --git a/target/linux/oxnas/patches-5.10/510-ox820-libata-leds.patch b/target/linux/oxnas/patches-5.10/510-ox820-libata-leds.patch
new file mode 100644
index 0000000000..05ae9ba44b
--- /dev/null
+++ b/target/linux/oxnas/patches-5.10/510-ox820-libata-leds.patch
@@ -0,0 +1,10 @@
+--- a/arch/arm/mach-oxnas/Kconfig
++++ b/arch/arm/mach-oxnas/Kconfig
+@@ -2,6 +2,7 @@
+ menuconfig ARCH_OXNAS
+ 	bool "Oxford Semiconductor OXNAS Family SoCs"
+ 	select ARCH_HAS_RESET_CONTROLLER
++	select ARCH_WANT_LIBATA_LEDS
+ 	select COMMON_CLK_OXNAS
+ 	select GPIOLIB
+ 	select MFD_SYSCON
diff --git a/target/linux/oxnas/patches-5.10/800-oxnas-ehci.patch b/target/linux/oxnas/patches-5.10/800-oxnas-ehci.patch
new file mode 100644
index 0000000000..8b4d943810
--- /dev/null
+++ b/target/linux/oxnas/patches-5.10/800-oxnas-ehci.patch
@@ -0,0 +1,73 @@
+--- a/drivers/usb/host/Kconfig
++++ b/drivers/usb/host/Kconfig
+@@ -350,6 +350,13 @@ config USB_OCTEON_EHCI
+ 	  USB 2.0 device support.  All CN6XXX based chips with USB are
+ 	  supported.
+ 
++config USB_EHCI_OXNAS
++	tristate "OXNAS EHCI Module"
++	depends on USB_EHCI_HCD && ARCH_OXNAS
++	select USB_EHCI_ROOT_HUB_TT
++	help
++	  Enable support for the OX820 SOC's on-chip EHCI controller.
++
+ endif # USB_EHCI_HCD
+ 
+ config USB_OXU210HP_HCD
+--- a/drivers/usb/host/Makefile
++++ b/drivers/usb/host/Makefile
+@@ -48,6 +48,7 @@ obj-$(CONFIG_USB_EHCI_HCD_SPEAR)	+= ehci
+ obj-$(CONFIG_USB_EHCI_HCD_STI)	+= ehci-st.o
+ obj-$(CONFIG_USB_EHCI_EXYNOS)	+= ehci-exynos.o
+ obj-$(CONFIG_USB_EHCI_HCD_AT91) += ehci-atmel.o
++obj-$(CONFIG_USB_EHCI_OXNAS)	+= ehci-oxnas.o
+ obj-$(CONFIG_USB_EHCI_TEGRA)	+= ehci-tegra.o
+ obj-$(CONFIG_USB_EHCI_BRCMSTB)	+= ehci-brcm.o
+ 
+--- a/arch/arm/boot/dts/ox820.dtsi
++++ b/arch/arm/boot/dts/ox820.dtsi
+@@ -106,6 +106,31 @@
+ 			status = "disabled";
+ 		};
+ 
++		ehci: ehci@40200100 {
++			compatible = "plxtech,nas782x-ehci";
++			reg = <0x40200100 0xf00>;
++			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&stdclk CLK_820_USBMPH>, <&pllb>, <&stdclk CLK_820_REF600>;
++			clock-names = "usb", "refsrc", "phyref";
++			resets = <&reset RESET_USBHS>, <&reset RESET_USBPHYA>, <&reset RESET_USBPHYB>;
++			reset-names = "host", "phya", "phyb";
++			oxsemi,sys-ctrl = <&sys>;
++			/* Otherwise ref300 is used, which is derived from sata phy
++			 * in that case, usb depends on sata initialization */
++			/* FIXME: how to make this dependency explicit ? */
++			oxsemi,ehci_use_pllb;
++			status = "disabled";
++
++			ehci_port1: port@1 {
++				reg = <1>;
++				#trigger-source-cells = <0>;
++			};
++			ehci_port2: port@2 {
++				reg = <2>;
++				#trigger-source-cells = <0>;
++			};
++		};
++
+ 		apb-bridge@44000000 {
+ 			#address-cells = <1>;
+ 			#size-cells = <1>;
+--- a/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts
++++ b/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts
+@@ -105,6 +105,10 @@
+ 	};
+ };
+ 
++&ehci {
++	status = "okay";
++};
++
+ &etha {
+ 	status = "okay";
+ 
diff --git a/target/linux/oxnas/patches-5.10/996-generic-Mangle-bootloader-s-kernel-arguments.patch b/target/linux/oxnas/patches-5.10/996-generic-Mangle-bootloader-s-kernel-arguments.patch
new file mode 100644
index 0000000000..07abd0c648
--- /dev/null
+++ b/target/linux/oxnas/patches-5.10/996-generic-Mangle-bootloader-s-kernel-arguments.patch
@@ -0,0 +1,189 @@
+From 71270226b14733a4b1f2cde58ea9265caa50b38d Mon Sep 17 00:00:00 2001
+From: Adrian Panella <ianchi74@outlook.com>
+Date: Thu, 9 Mar 2017 09:37:17 +0100
+Subject: [PATCH 67/69] generic: Mangle bootloader's kernel arguments
+
+The command-line arguments provided by the boot loader will be
+appended to a new device tree property: bootloader-args.
+If there is a property "append-rootblock" in DT under /chosen
+and a root= option in bootloaders command line it will be parsed
+and added to DT bootargs with the form: <append-rootblock>XX.
+Only command line ATAG will be processed, the rest of the ATAGs
+sent by bootloader will be ignored.
+This is usefull in dual boot systems, to get the current root partition
+without afecting the rest of the system.
+
+Signed-off-by: Adrian Panella <ianchi74@outlook.com>
+---
+ arch/arm/Kconfig                        | 11 +++++
+ arch/arm/boot/compressed/atags_to_fdt.c | 72 ++++++++++++++++++++++++++++++++-
+ init/main.c                             | 16 ++++++++
+ 3 files changed, 98 insertions(+), 1 deletion(-)
+
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -1780,6 +1780,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
+ 	  The command-line arguments provided by the boot loader will be
+ 	  appended to the the device tree bootargs property.
+ 
++config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
++	bool "Append rootblock parsing bootloader's kernel arguments"
++	help
++	  The command-line arguments provided by the boot loader will be
++	  appended to a new device tree property: bootloader-args.
++	  If there is a property "append-rootblock" in DT under /chosen 
++	  and a root= option in bootloaders command line it will be parsed 
++	  and added to DT bootargs with the form: <append-rootblock>XX.
++	  Only command line ATAG will be processed, the rest of the ATAGs
++	  sent by bootloader will be ignored.
++
+ endchoice
+ 
+ config CMDLINE
+--- a/arch/arm/boot/compressed/atags_to_fdt.c
++++ b/arch/arm/boot/compressed/atags_to_fdt.c
+@@ -5,6 +5,8 @@
+ 
+ #if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND)
+ #define do_extend_cmdline 1
++#elif defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
++#define do_extend_cmdline 1
+ #else
+ #define do_extend_cmdline 0
+ #endif
+@@ -69,6 +71,59 @@ static uint32_t get_cell_size(const void
+ 	return cell_size;
+ }
+ 
++#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
++
++static char *append_rootblock(char *dest, const char *str, int len, void *fdt)
++{
++	char *ptr, *end;
++	char *root="root=";
++	int i, l;
++	const char *rootblock;
++
++	//ARM doesn't have __HAVE_ARCH_STRSTR, so search manually
++	ptr = str - 1;
++
++	do {
++		//first find an 'r' at the begining or after a space
++		do {
++			ptr++;
++			ptr = strchr(ptr, 'r');
++			if(!ptr) return dest;
++
++		} while (ptr != str && *(ptr-1) != ' ');
++
++		//then check for the rest
++		for(i = 1; i <= 4; i++)
++			if(*(ptr+i) != *(root+i)) break;
++
++	} while (i != 5);
++
++	end = strchr(ptr, ' ');
++	end = end ? (end - 1) : (strchr(ptr, 0) - 1);
++
++	//find partition number (assumes format root=/dev/mtdXX | /dev/mtdblockXX | yy:XX )
++	for( i = 0; end >= ptr && *end >= '0' && *end <= '9'; end--, i++);
++	ptr = end + 1;
++
++	/* if append-rootblock property is set use it to append to command line */
++	rootblock = getprop(fdt, "/chosen", "append-rootblock", &l);
++	if(rootblock != NULL) {
++		if(*dest != ' ') {
++			*dest = ' ';
++			dest++;
++			len++;
++		}
++		if (len + l + i <= COMMAND_LINE_SIZE) {
++			memcpy(dest, rootblock, l);
++			dest += l - 1;
++			memcpy(dest, ptr, i);
++			dest += i;
++		}
++	}
++	return dest;
++}
++#endif
++
+ static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline)
+ {
+ 	char cmdline[COMMAND_LINE_SIZE];
+@@ -88,12 +143,21 @@ static void merge_fdt_bootargs(void *fdt
+ 
+ 	/* and append the ATAG_CMDLINE */
+ 	if (fdt_cmdline) {
++
++#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
++		//save original bootloader args
++		//and append ubi.mtd with root partition number to current cmdline
++		setprop_string(fdt, "/chosen", "bootloader-args", fdt_cmdline);
++		ptr = append_rootblock(ptr, fdt_cmdline, len, fdt);
++
++#else
+ 		len = strlen(fdt_cmdline);
+ 		if (ptr - cmdline + len + 2 < COMMAND_LINE_SIZE) {
+ 			*ptr++ = ' ';
+ 			memcpy(ptr, fdt_cmdline, len);
+ 			ptr += len;
+ 		}
++#endif
+ 	}
+ 	*ptr = '\0';
+ 
+@@ -168,7 +232,9 @@ int atags_to_fdt(void *atag_list, void *
+ 			else
+ 				setprop_string(fdt, "/chosen", "bootargs",
+ 					       atag->u.cmdline.cmdline);
+-		} else if (atag->hdr.tag == ATAG_MEM) {
++		}
++#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
++		else if (atag->hdr.tag == ATAG_MEM) {
+ 			if (memcount >= sizeof(mem_reg_property)/4)
+ 				continue;
+ 			if (!atag->u.mem.size)
+@@ -212,6 +278,10 @@ int atags_to_fdt(void *atag_list, void *
+ 		setprop(fdt, "/memory", "reg", mem_reg_property,
+ 			4 * memcount * memsize);
+ 	}
++#else
++
++	}
++#endif
+ 
+ 	return fdt_pack(fdt);
+ }
+--- a/init/main.c
++++ b/init/main.c
+@@ -110,6 +110,10 @@
+ 
+ #include <kunit/test.h>
+ 
++#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
++#include <linux/of.h>
++#endif
++
+ static int kernel_init(void *);
+ 
+ extern void init_IRQ(void);
+@@ -903,6 +907,18 @@ asmlinkage __visible void __init __no_sa
+ 	page_alloc_init();
+ 
+ 	pr_notice("Kernel command line: %s\n", saved_command_line);
++
++#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
++	//Show bootloader's original command line for reference
++	if(of_chosen) {
++		const char *prop = of_get_property(of_chosen, "bootloader-args", NULL);
++		if(prop)
++			pr_notice("Bootloader command line (ignored): %s\n", prop);
++		else
++			pr_notice("Bootloader command line not present\n");
++	}
++#endif
++
+ 	/* parameters may set static keys */
+ 	jump_label_init();
+ 	parse_early_param();
diff --git a/target/linux/oxnas/patches-5.10/999-libata-hacks.patch b/target/linux/oxnas/patches-5.10/999-libata-hacks.patch
new file mode 100644
index 0000000000..b02c506e9f
--- /dev/null
+++ b/target/linux/oxnas/patches-5.10/999-libata-hacks.patch
@@ -0,0 +1,57 @@
+--- a/drivers/ata/libata-core.c
++++ b/drivers/ata/libata-core.c
+@@ -1528,6 +1528,14 @@ unsigned ata_exec_internal_sg(struct ata
+ 		return AC_ERR_SYSTEM;
+ 	}
+ 
++	if (ap->ops->acquire_hw && !ap->ops->acquire_hw(ap, 0, 0)) {
++		spin_unlock_irqrestore(ap->lock, flags);
++		if (!ap->ops->acquire_hw(ap, 1, (2*HZ))) {
++			return AC_ERR_TIMEOUT;
++		}
++		spin_lock_irqsave(ap->lock, flags);
++	}
++
+ 	/* initialize internal qc */
+ 	qc = __ata_qc_from_tag(ap, ATA_TAG_INTERNAL);
+ 
+@@ -4520,6 +4528,9 @@ struct ata_queued_cmd *ata_qc_new_init(s
+ 	if (unlikely(ap->pflags & ATA_PFLAG_FROZEN))
+ 		return NULL;
+ 
++	if (ap->ops->qc_new && ap->ops->qc_new(ap))
++		return NULL;
++
+ 	/* libsas case */
+ 	if (ap->flags & ATA_FLAG_SAS_HOST) {
+ 		tag = ata_sas_allocate_tag(ap);
+@@ -4565,6 +4576,8 @@ void ata_qc_free(struct ata_queued_cmd *
+ 		qc->tag = ATA_TAG_POISON;
+ 		if (ap->flags & ATA_FLAG_SAS_HOST)
+ 			ata_sas_free_tag(tag, ap);
++		if (ap->ops->qc_free)
++			ap->ops->qc_free(qc);
+ 	}
+ }
+ 
+--- a/include/linux/libata.h
++++ b/include/linux/libata.h
+@@ -911,6 +911,8 @@ struct ata_port_operations {
+ 	enum ata_completion_errors (*qc_prep)(struct ata_queued_cmd *qc);
+ 	unsigned int (*qc_issue)(struct ata_queued_cmd *qc);
+ 	bool (*qc_fill_rtf)(struct ata_queued_cmd *qc);
++	int (*qc_new)(struct ata_port *ap);
++	void (*qc_free)(struct ata_queued_cmd *qc);
+ 
+ 	/*
+ 	 * Configuration and exception handling
+@@ -1001,6 +1003,9 @@ struct ata_port_operations {
+ 	void (*phy_reset)(struct ata_port *ap);
+ 	void (*eng_timeout)(struct ata_port *ap);
+ 
++	int (*acquire_hw)(struct ata_port *ap, int may_sleep,
++			  int timeout_jiffies);
++
+ 	/*
+ 	 * ->inherits must be the last field and all the preceding
+ 	 * fields must be pointers.