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| author | Gabor Juhos <juhosg@openwrt.org> | 2014-01-26 11:30:34 +0000 |
|---|---|---|
| committer | Gabor Juhos <juhosg@openwrt.org> | 2014-01-26 11:30:34 +0000 |
| commit | a2543d72d8a0b4a9efcee26c8af36d618de4c863 (patch) | |
| tree | e8655a579d54b55e648ec1750bb282fc1c5d7b61 /target/linux/ramips/patches-3.10/0511-MIPS-GIC-Send-IPIs-using-the-GIC.patch | |
| parent | e41e531e3b6a5fa99db8b682c00e47fc15d3d401 (diff) | |
| download | upstream-a2543d72d8a0b4a9efcee26c8af36d618de4c863.tar.gz upstream-a2543d72d8a0b4a9efcee26c8af36d618de4c863.tar.bz2 upstream-a2543d72d8a0b4a9efcee26c8af36d618de4c863.zip | |
kernel: update 3.10 to 3.10.28
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
SVN-Revision: 39399
Diffstat (limited to 'target/linux/ramips/patches-3.10/0511-MIPS-GIC-Send-IPIs-using-the-GIC.patch')
| -rw-r--r-- | target/linux/ramips/patches-3.10/0511-MIPS-GIC-Send-IPIs-using-the-GIC.patch | 13 |
1 files changed, 4 insertions, 9 deletions
diff --git a/target/linux/ramips/patches-3.10/0511-MIPS-GIC-Send-IPIs-using-the-GIC.patch b/target/linux/ramips/patches-3.10/0511-MIPS-GIC-Send-IPIs-using-the-GIC.patch index 6e4cfc7d4b..366fdb2aff 100644 --- a/target/linux/ramips/patches-3.10/0511-MIPS-GIC-Send-IPIs-using-the-GIC.patch +++ b/target/linux/ramips/patches-3.10/0511-MIPS-GIC-Send-IPIs-using-the-GIC.patch @@ -10,11 +10,9 @@ Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> arch/mips/kernel/smp-mt.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) -diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c -index 2f8c468..d057c84 100644 --- a/arch/mips/kernel/smp-mt.c +++ b/arch/mips/kernel/smp-mt.c -@@ -71,6 +71,7 @@ static unsigned int __init smvp_vpe_init(unsigned int tc, unsigned int mvpconf0, +@@ -71,6 +71,7 @@ static unsigned int __init smvp_vpe_init /* Record this as available CPU */ set_cpu_possible(tc, true); @@ -22,7 +20,7 @@ index 2f8c468..d057c84 100644 __cpu_number_map[tc] = ++ncpu; __cpu_logical_map[ncpu] = tc; } -@@ -112,12 +113,35 @@ static void __init smvp_tc_init(unsigned int tc, unsigned int mvpconf0) +@@ -112,12 +113,35 @@ static void __init smvp_tc_init(unsigned write_tc_c0_tchalt(TCHALT_H); } @@ -58,7 +56,7 @@ index 2f8c468..d057c84 100644 local_irq_save(flags); vpflags = dvpe(); /* can't access the other CPU's registers whilst MVPE enabled */ -@@ -164,6 +188,8 @@ static void __cpuinit vsmp_init_secondary(void) +@@ -164,6 +188,8 @@ static void __cpuinit vsmp_init_secondar static void __cpuinit vsmp_smp_finish(void) { @@ -67,7 +65,7 @@ index 2f8c468..d057c84 100644 /* CDFIXME: remove this? */ write_c0_compare(read_c0_count() + (8* mips_hpt_frequency/HZ)); -@@ -178,6 +204,7 @@ static void __cpuinit vsmp_smp_finish(void) +@@ -178,6 +204,7 @@ static void __cpuinit vsmp_smp_finish(vo static void vsmp_cpus_done(void) { @@ -101,6 +99,3 @@ index 2f8c468..d057c84 100644 mips_mt_set_cpuoptions(); } --- -1.7.10.4 - |