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authorJohn Crispin <john@phrozen.org>2016-06-29 15:09:09 +0200
committerJohn Crispin <john@phrozen.org>2016-07-03 08:00:26 +0200
commitd09f0045ea2f7fb142e23d8f5cdd45e48a3dcc26 (patch)
tree289551e88ed176e420e75d9c180705bb6ce38b0b /target/linux/ramips/patches-4.4/0520-esw-gmac.patch
parente892472b1eb1dc5529c2c1b14173446be9704508 (diff)
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ramips: fix up switch settings for Sitecom WL-351 v1 002
Pinmux for rgmii needs to be set to rgmii, not gpio. Hide the ESW switch on boot (using new rgmii esw devicetree attribute). Also add a Sitecom-specific profile, since the image needs to include the rtl8366 kernel driver. Signed-off-by: Tobias Diedrich <ranma+openwrt@tdiedrich.de>
Diffstat (limited to 'target/linux/ramips/patches-4.4/0520-esw-gmac.patch')
-rw-r--r--target/linux/ramips/patches-4.4/0520-esw-gmac.patch69
1 files changed, 69 insertions, 0 deletions
diff --git a/target/linux/ramips/patches-4.4/0520-esw-gmac.patch b/target/linux/ramips/patches-4.4/0520-esw-gmac.patch
new file mode 100644
index 0000000000..9d4cd3f4c1
--- /dev/null
+++ b/target/linux/ramips/patches-4.4/0520-esw-gmac.patch
@@ -0,0 +1,69 @@
+--- a/drivers/net/ethernet/mediatek/esw_rt3050.c
++++ b/drivers/net/ethernet/mediatek/esw_rt3050.c
+@@ -221,6 +221,8 @@
+
+ unsigned char port_map;
+ unsigned char port_disable;
++ unsigned int reg_initval_fct2;
++ unsigned int reg_initval_fpa2;
+ unsigned int reg_led_polarity;
+
+ struct switch_dev swdev;
+@@ -452,7 +454,10 @@
+ (RT305X_ESW_PORTS_NOCPU << RT305X_ESW_POC2_UNTAG_EN_S)),
+ RT305X_ESW_REG_POC2);
+
+- esw_w32(esw, 0x0002500c, RT305X_ESW_REG_FCT2);
++ if (esw->reg_initval_fct2)
++ esw_w32(esw, esw->reg_initval_fct2, RT305X_ESW_REG_FCT2);
++ else
++ esw_w32(esw, 0x0002500c, RT305X_ESW_REG_FCT2);
+
+ /* 300s aging timer, max packet len 1536, broadcast storm prevention
+ * disabled, disable collision abort, mac xor48 hash, 10 packet back
+@@ -475,7 +480,10 @@
+ * port5: disabled
+ * port6: enabled, gige, full-duplex, rx/tx-flow-control
+ */
+- esw_w32(esw, 0x3f502b28, RT305X_ESW_REG_FPA2);
++ if (esw->reg_initval_fpa2)
++ esw_w32(esw, esw->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
++ else
++ esw_w32(esw, 0x3f502b28, RT305X_ESW_REG_FPA2);
+ esw_w32(esw, 0x00000000, RT305X_ESW_REG_FPA);
+
+ /* Force Link/Activity on ports */
+@@ -1361,6 +1369,14 @@
+ if (port_disable)
+ esw->port_disable = be32_to_cpu(*port_disable);
+
++ reg_init = of_get_property(np, "ralink,fct2", NULL);
++ if (reg_init)
++ esw->reg_initval_fct2 = be32_to_cpu(*reg_init);
++
++ reg_init = of_get_property(np, "ralink,fpa2", NULL);
++ if (reg_init)
++ esw->reg_initval_fpa2 = be32_to_cpu(*reg_init);
++
+ reg_init = of_get_property(np, "mediatek,led_polarity", NULL);
+ if (reg_init)
+ esw->reg_led_polarity = be32_to_cpu(*reg_init);
+@@ -1386,6 +1402,18 @@
+
+ esw_hw_init(esw);
+
++ reg_init = of_get_property(np, "ralink,rgmii", NULL);
++ if (reg_init && be32_to_cpu(*reg_init) == 1) {
++ /*
++ * External switch connected to RGMII interface.
++ * Unregister the switch device after initialization.
++ */
++ dev_err(&pdev->dev, "RGMII mode, not exporting switch device.\n");
++ unregister_switch(&esw->swdev);
++ platform_set_drvdata(pdev, NULL);
++ return -ENODEV;
++ }
++
+ ret = devm_request_irq(&pdev->dev, esw->irq, esw_interrupt, 0, "esw",
+ esw);
+