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| author | Daniel González Cabanelas <dgcbueu@gmail.com> | 2021-04-27 10:58:15 +0200 |
|---|---|---|
| committer | Hauke Mehrtens <hauke@hauke-m.de> | 2021-05-01 00:37:15 +0200 |
| commit | 26a5aea9bc76ff17c2dae03f01ab39e7630da3cc (patch) | |
| tree | 39facaa1cde35f9c5603479db4f450f825a08be5 /toolchain/binutils/Makefile | |
| parent | d7956c57284624f4bc7b905d192c81e1d34576fe (diff) | |
| download | upstream-26a5aea9bc76ff17c2dae03f01ab39e7630da3cc.tar.gz upstream-26a5aea9bc76ff17c2dae03f01ab39e7630da3cc.tar.bz2 upstream-26a5aea9bc76ff17c2dae03f01ab39e7630da3cc.zip | |
mvebu: LS421DE: improve pin configuration
The CLK125 output pin at the ethernet PHY is connected via capacitor to
GND and nowhere else. Disable it. Also tune the LED masks.
The MPP56 and MPP60 pins at the SoC are conected to the μPD720202 USB3.0
chip:
- MPP56: wired to PCIe CLKREQ# (out)
- MPP60: wired to PCIe RESET# (in)
Configure the pcie pinmux for these pins.
Signed-off-by: Daniel González Cabanelas <dgcbueu@gmail.com>
Diffstat (limited to 'toolchain/binutils/Makefile')
0 files changed, 0 insertions, 0 deletions