diff options
4 files changed, 266 insertions, 224 deletions
diff --git a/target/linux/realtek/files-5.10/arch/mips/kernel/cevt-rtl9300.c b/target/linux/realtek/files-5.10/arch/mips/kernel/cevt-rtl9300.c new file mode 100644 index 0000000000..cf3a4fe437 --- /dev/null +++ b/target/linux/realtek/files-5.10/arch/mips/kernel/cevt-rtl9300.c @@ -0,0 +1,212 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <linux/clockchips.h> +#include <linux/init.h> +#include <asm/time.h> +#include <asm/idle.h> +#include <linux/interrupt.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> +#include <linux/sched_clock.h> + +#include <mach-rtl83xx.h> + +/* + * Timer registers + * the RTL9300/9310 SoCs have 6 timers, each register block 0x10 apart + */ +#define RTL9300_TC_DATA 0x0 +#define RTL9300_TC_CNT 0x4 +#define RTL9300_TC_CTRL 0x8 +#define RTL9300_TC_CTRL_MODE BIT(24) +#define RTL9300_TC_CTRL_EN BIT(28) +#define RTL9300_TC_INT 0xc +#define RTL9300_TC_INT_IP BIT(16) +#define RTL9300_TC_INT_IE BIT(20) + +// Clocksource is using timer 0, clock event uses timer 1 +#define TIMER_CLK_SRC 0 +#define TIMER_CLK_EVT 0 +#define TIMER_BLK_EVT (TIMER_CLK_EVT << 4) + +// Timer modes +#define TIMER_MODE_REPEAT 1 +#define TIMER_MODE_ONCE 0 + +// Minimum divider is 2 +#define DIVISOR_RTL9300 2 + +#define N_BITS 28 + +#define RTL9300_TC1_IRQ 8 +#define RTL9300_CLOCK_RATE 87500000 +#define RTL9300_TC0_BASE (void *)0xb8003200 + +int irq_tc0 = 7; + +static void __iomem *rtl9300_tc_base(struct clock_event_device *clk) +{ + struct irq_desc *desc = irq_to_desc(clk->irq); + int tc = desc->irq_data.hwirq - irq_tc0; + + return RTL9300_TC0_BASE + (tc << 4); +} + +static irqreturn_t rtl9300_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *clk = dev_id; +// int cpu = smp_processor_id(); + struct irq_desc *desc = irq_to_desc(irq); + int tc = desc->irq_data.hwirq - irq_tc0; + void __iomem *base = RTL9300_TC0_BASE + (tc << 4); + static atomic_t count = ATOMIC_INIT(0); + unsigned int c; + u32 v = readl(base + RTL9300_TC_INT); + + c = (unsigned int)atomic_inc_return(&count); + + // Acknowledge the IRQ + v |= RTL9300_TC_INT_IP; + writel(v, base + RTL9300_TC_INT); + if (readl(base + RTL9300_TC_INT) & RTL9300_TC_INT_IP) + dump_stack(); + + clk->event_handler(clk); + return IRQ_HANDLED; +} + +static void rtl9300_clock_stop(void __iomem *base) +{ + u32 v; + + writel(0, base + RTL9300_TC_CTRL); + + // Acknowledge possibly pending IRQ + v = readl(base + RTL9300_TC_INT); +// if (v & RTL9300_TC_INT_IP) + writel(v | RTL9300_TC_INT_IP, base + RTL9300_TC_INT); + if (readl(base + RTL9300_TC_INT) & RTL9300_TC_INT_IP) + dump_stack(); +} + +static void rtl9300_timer_start(void __iomem *base, bool periodic) +{ + u32 v = (periodic ? RTL9300_TC_CTRL_MODE : 0) | RTL9300_TC_CTRL_EN | DIVISOR_RTL9300; + + writel(0, base + RTL9300_TC_CNT); + pr_debug("------------- starting timer base %08x\n", (u32)base); + writel(v, base + RTL9300_TC_CTRL); +} + +static int rtl9300_next_event(unsigned long delta, struct clock_event_device *clk) +{ + void __iomem *base = rtl9300_tc_base(clk); + + rtl9300_clock_stop(base); + writel(delta, base + RTL9300_TC_DATA); + rtl9300_timer_start(base, TIMER_MODE_ONCE); + + return 0; +} + +static int rtl9300_state_periodic(struct clock_event_device *clk) +{ + void __iomem *base = rtl9300_tc_base(clk); + + pr_debug("------------- rtl9300_state_periodic %08x\n", (u32)base); + rtl9300_clock_stop(base); + writel(RTL9300_CLOCK_RATE / HZ, base + RTL9300_TC_DATA); + rtl9300_timer_start(base, TIMER_MODE_REPEAT); + return 0; +} + +static int rtl9300_state_oneshot(struct clock_event_device *clk) +{ + void __iomem *base = rtl9300_tc_base(clk); + + pr_debug("------------- rtl9300_state_oneshot %08x\n", (u32)base); + rtl9300_clock_stop(base); + writel(RTL9300_CLOCK_RATE / HZ, base + RTL9300_TC_DATA); + rtl9300_timer_start(base, TIMER_MODE_ONCE); + return 0; +} + +static int rtl9300_shutdown(struct clock_event_device *clk) +{ + void __iomem *base = rtl9300_tc_base(clk); + + pr_debug("------------- rtl9300_shutdown %08x\n", (u32)base); + rtl9300_clock_stop(base); + return 0; +} + +static void rtl9300_clock_setup(void __iomem *base) +{ + u32 v; + + // Disable timer + writel(0, base + RTL9300_TC_CTRL); + + // Acknowledge possibly pending IRQ + v = readl(base + RTL9300_TC_INT); +// if (v & RTL9300_TC_INT_IP) + writel(v | RTL9300_TC_INT_IP, base + RTL9300_TC_INT); + if (readl(base + RTL9300_TC_INT) & RTL9300_TC_INT_IP) + dump_stack(); + + // Setup maximum period (for use as clock-source) + writel(0x0fffffff, base + RTL9300_TC_DATA); +} + +static DEFINE_PER_CPU(struct clock_event_device, rtl9300_clockevent); +static DEFINE_PER_CPU(char [18], rtl9300_clock_name); + +void rtl9300_clockevent_init(void) +{ + int cpu = smp_processor_id(); + int irq; + struct clock_event_device *cd = &per_cpu(rtl9300_clockevent, cpu); + unsigned char *name = per_cpu(rtl9300_clock_name, cpu); + unsigned long flags = IRQF_PERCPU | IRQF_TIMER; + struct device_node *node; + + pr_info("%s called for cpu%d\n", __func__, cpu); + BUG_ON(cpu > 3); /* Only have 4 general purpose timers */ + + node = of_find_compatible_node(NULL, NULL, "realtek,rtl9300clock"); + if (!node) { + pr_err("No DT entry found for realtek,rtl9300clock\n"); + return; + } + + irq = irq_of_parse_and_map(node, cpu); + pr_info("%s using IRQ %d\n", __func__, irq); + + rtl9300_clock_setup(RTL9300_TC0_BASE + TIMER_BLK_EVT + (cpu << 4)); + + sprintf(name, "rtl9300-counter-%d", cpu); + cd->name = name; + cd->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; + + clockevent_set_clock(cd, RTL9300_CLOCK_RATE); + + cd->max_delta_ns = clockevent_delta2ns(0x0fffffff, cd); + cd->max_delta_ticks = 0x0fffffff; + cd->min_delta_ns = clockevent_delta2ns(0x20, cd); + cd->min_delta_ticks = 0x20; + cd->rating = 300; + cd->irq = irq; + cd->cpumask = cpumask_of(cpu); + cd->set_next_event = rtl9300_next_event; + cd->set_state_shutdown = rtl9300_shutdown; + cd->set_state_periodic = rtl9300_state_periodic; + cd->set_state_oneshot = rtl9300_state_oneshot; + clockevents_register_device(cd); + + irq_set_affinity(irq, cd->cpumask); + + if (request_irq(irq, rtl9300_timer_interrupt, flags, name, cd)) + pr_err("Failed to request irq %d (%s)\n", irq, name); + + writel(RTL9300_TC_INT_IE, RTL9300_TC0_BASE + TIMER_BLK_EVT + (cpu << 4) + RTL9300_TC_INT); +} diff --git a/target/linux/realtek/files-5.10/drivers/clocksource/timer-rtl9300.c b/target/linux/realtek/files-5.10/drivers/clocksource/timer-rtl9300.c deleted file mode 100644 index 9ab1733fe3..0000000000 --- a/target/linux/realtek/files-5.10/drivers/clocksource/timer-rtl9300.c +++ /dev/null @@ -1,196 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include <linux/clockchips.h> -#include <linux/init.h> -#include <asm/time.h> -#include <linux/interrupt.h> -#include <linux/of_address.h> -#include <linux/of_irq.h> -#include <linux/sched_clock.h> -#include "timer-of.h" - -#include <mach-rtl83xx.h> - -/* - * Timer registers - * the RTL9300/9310 SoCs have 6 timers, each register block 0x10 apart - */ -#define RTL9300_TC_DATA 0x0 -#define RTL9300_TC_CNT 0x4 -#define RTL9300_TC_CTRL 0x8 -#define RTL9300_TC_CTRL_MODE BIT(24) -#define RTL9300_TC_CTRL_EN BIT(28) -#define RTL9300_TC_INT 0xc -#define RTL9300_TC_INT_IP BIT(16) -#define RTL9300_TC_INT_IE BIT(20) - -// Clocksource is using timer 0, clock event uses timer 1 -#define TIMER_CLK_SRC 0 -#define TIMER_CLK_EVT 1 -#define TIMER_BLK_EVT (TIMER_CLK_EVT << 4) - -// Timer modes -#define TIMER_MODE_REPEAT 1 -#define TIMER_MODE_ONCE 0 - -// Minimum divider is 2 -#define DIVISOR_RTL9300 2 - -#define N_BITS 28 - -static void __iomem *rtl9300_sched_reg __read_mostly; - -static u64 notrace rtl9300_sched_clock_read(void) -{ -/* pr_info("In %s: %x\n", __func__, readl_relaxed(rtl9300_sched_reg)); - dump_stack();*/ - return readl_relaxed(rtl9300_sched_reg); -} - -static irqreturn_t rtl9300_timer_interrupt(int irq, void *dev_id) -{ - struct clock_event_device *clk = dev_id; - struct timer_of *to = to_timer_of(clk); - u32 v = readl(timer_of_base(to) + TIMER_BLK_EVT + RTL9300_TC_INT); - - // Acknowledge the IRQ - v |= RTL9300_TC_INT_IP; - writel(v, timer_of_base(to) + TIMER_BLK_EVT + RTL9300_TC_INT); - - clk->event_handler(clk); - return IRQ_HANDLED; -} - -static void rtl9300_timer_stop(struct timer_of *to) -{ - u32 v; - - writel(0, timer_of_base(to) + TIMER_BLK_EVT + RTL9300_TC_CTRL); - - // Acknowledge possibly pending IRQ - v = readl(timer_of_base(to) + TIMER_BLK_EVT + RTL9300_TC_INT); - if (v & RTL9300_TC_INT_IP) - writel(v, timer_of_base(to) + TIMER_BLK_EVT + RTL9300_TC_INT); -} - -static void rtl9300_timer_start(struct timer_of *to, int timer, bool periodic) -{ - u32 v = (periodic ? RTL9300_TC_CTRL_MODE : 0) | RTL9300_TC_CTRL_EN | DIVISOR_RTL9300; - writel(v, timer_of_base(to) + timer * 0x10 + RTL9300_TC_CTRL); -} - -static int rtl9300_set_next_event(unsigned long delta, struct clock_event_device *clk) -{ - struct timer_of *to = to_timer_of(clk); - - rtl9300_timer_stop(to); - writel(delta, timer_of_base(to) + TIMER_BLK_EVT + RTL9300_TC_DATA); - rtl9300_timer_start(to, TIMER_CLK_EVT, TIMER_MODE_ONCE); - return 0; -} - -static int rtl9300_set_state_periodic(struct clock_event_device *clk) -{ - struct timer_of *to = to_timer_of(clk); - - rtl9300_timer_stop(to); - writel(to->of_clk.period, timer_of_base(to) + TIMER_BLK_EVT + RTL9300_TC_DATA); - rtl9300_timer_start(to, TIMER_CLK_EVT, TIMER_MODE_REPEAT); - return 0; -} - -static int rtl9300_set_state_oneshot(struct clock_event_device *clk) -{ - struct timer_of *to = to_timer_of(clk); - - rtl9300_timer_stop(to); - writel(to->of_clk.period, timer_of_base(to) + TIMER_BLK_EVT + RTL9300_TC_DATA); - rtl9300_timer_start(to, TIMER_CLK_EVT, TIMER_MODE_ONCE); - return 0; -} - -static int rtl9300_set_state_shutdown(struct clock_event_device *clk) -{ - struct timer_of *to = to_timer_of(clk); - - rtl9300_timer_stop(to); - return 0; -} - -static struct timer_of t_of = { - .flags = TIMER_OF_BASE | TIMER_OF_IRQ | TIMER_OF_CLOCK, - - .clkevt = { - .name = "rtl9300_timer", - .rating = 350, - .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, - .set_next_event = rtl9300_set_next_event, - .set_state_oneshot = rtl9300_set_state_oneshot, - .set_state_periodic = rtl9300_set_state_periodic, - .set_state_shutdown = rtl9300_set_state_shutdown, - }, - - .of_irq = { - .name = "ostimer", - .handler = rtl9300_timer_interrupt, - .flags = IRQF_TIMER, - }, -}; - -static void __init rtl9300_timer_setup(u8 timer) -{ - u32 v; - - // Disable timer - writel(0, timer_of_base(&t_of) + 0x10 * timer + RTL9300_TC_CTRL); - - // Acknowledge possibly pending IRQ - v = readl(timer_of_base(&t_of) + 0x10 * timer + RTL9300_TC_INT); - if (v & RTL9300_TC_INT_IP) - writel(v, timer_of_base(&t_of) + 0x10 * timer + RTL9300_TC_INT); - - // Setup maximum period (for use as clock-source) - writel(0x0fffffff, timer_of_base(&t_of) + 0x10 * timer + RTL9300_TC_DATA); -} - - -static int __init rtl9300_timer_init(struct device_node *node) -{ - int err = 0; - unsigned long rate; - - pr_info("%s: setting up timer\n", __func__); - - err = timer_of_init(node, &t_of); - if (err) - return err; - - rate = timer_of_rate(&t_of) / DIVISOR_RTL9300; - pr_info("Frequency in dts: %ld, my rate is %ld, period %ld\n", - timer_of_rate(&t_of), rate, timer_of_period(&t_of)); - pr_info("With base %08x IRQ: %d\n", (u32)timer_of_base(&t_of), timer_of_irq(&t_of)); - - // Configure clock source and register it for scheduling - rtl9300_timer_setup(TIMER_CLK_SRC); - rtl9300_timer_start(&t_of, TIMER_CLK_SRC, TIMER_MODE_REPEAT); - - rtl9300_sched_reg = timer_of_base(&t_of) + TIMER_CLK_SRC * 0x10 + RTL9300_TC_CNT; - - err = clocksource_mmio_init(rtl9300_sched_reg, node->name, rate , 100, N_BITS, - clocksource_mmio_readl_up); - if (err) - return err; - - sched_clock_register(rtl9300_sched_clock_read, N_BITS, rate); - - // Configure clock event source - rtl9300_timer_setup(TIMER_CLK_EVT); - clockevents_config_and_register(&t_of.clkevt, rate, 100, 0x0fffffff); - - // Enable interrupt - writel(RTL9300_TC_INT_IE, timer_of_base(&t_of) + TIMER_BLK_EVT + RTL9300_TC_INT); - - return err; -} - -TIMER_OF_DECLARE(rtl9300_timer, "realtek,rtl9300-timer", rtl9300_timer_init); diff --git a/target/linux/realtek/patches-5.10/302-clocksource-add-rtl9300-driver.patch b/target/linux/realtek/patches-5.10/302-clocksource-add-rtl9300-driver.patch deleted file mode 100644 index 365a62bf30..0000000000 --- a/target/linux/realtek/patches-5.10/302-clocksource-add-rtl9300-driver.patch +++ /dev/null @@ -1,28 +0,0 @@ ---- a/drivers/clocksource/Kconfig -+++ b/drivers/clocksource/Kconfig -@@ -127,6 +127,15 @@ config RDA_TIMER - help - Enables the support for the RDA Micro timer driver. - -+config RTL9300_TIMER -+ bool "Clocksource/timer for the Realtek RTL9300 family of SoCs" -+ depends on MIPS -+ select COMMON_CLK -+ select TIMER_OF -+ select CLKSRC_MMIO -+ help -+ Enables support for the Realtek RTL9300 timer driver. -+ - config SUN4I_TIMER - bool "Sun4i timer driver" if COMPILE_TEST - depends on HAS_IOMEM ---- a/drivers/clocksource/Makefile -+++ b/drivers/clocksource/Makefile -@@ -63,6 +63,7 @@ obj-$(CONFIG_MILBEAUT_TIMER) += timer-mi - obj-$(CONFIG_SPRD_TIMER) += timer-sprd.o - obj-$(CONFIG_NPCM7XX_TIMER) += timer-npcm7xx.o - obj-$(CONFIG_RDA_TIMER) += timer-rda.o -+obj-$(CONFIG_RTL9300_TIMER) += timer-rtl9300.o - - obj-$(CONFIG_ARC_TIMERS) += arc_timer.o - obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o diff --git a/target/linux/realtek/patches-5.10/309-cevt-rtl9300-support.patch b/target/linux/realtek/patches-5.10/309-cevt-rtl9300-support.patch new file mode 100644 index 0000000000..6a0038d86b --- /dev/null +++ b/target/linux/realtek/patches-5.10/309-cevt-rtl9300-support.patch @@ -0,0 +1,54 @@ +--- a/arch/mips/kernel/Makefile ++++ b/arch/mips/kernel/Makefile +@@ -27,6 +27,7 @@ obj-$(CONFIG_CEVT_BCM1480) += cevt-bcm14 + obj-$(CONFIG_CEVT_R4K) += cevt-r4k.o + obj-$(CONFIG_CEVT_DS1287) += cevt-ds1287.o + obj-$(CONFIG_CEVT_GT641XX) += cevt-gt641xx.o ++obj-$(CONFIG_CEVT_RTL9300) += cevt-rtl9300.o + obj-$(CONFIG_CEVT_SB1250) += cevt-sb1250.o + obj-$(CONFIG_CEVT_TXX9) += cevt-txx9.o + obj-$(CONFIG_CSRC_BCM1480) += csrc-bcm1480.o +--- a/arch/mips/include/asm/time.h ++++ b/arch/mips/include/asm/time.h +@@ -15,6 +15,8 @@ + #include <linux/clockchips.h> + #include <linux/clocksource.h> + ++extern void rtl9300_clockevent_init(void); ++ + extern spinlock_t rtc_lock; + + /* +@@ -43,6 +45,11 @@ extern int r4k_clockevent_init(void); + + static inline int mips_clockevent_init(void) + { ++#ifdef CONFIG_CEVT_RTL9300 ++ rtl9300_clockevent_init(); ++ return 0; ++#endif ++ + #ifdef CONFIG_CEVT_R4K + return r4k_clockevent_init(); + #else +--- a/arch/mips/kernel/smp-mt.c ++++ b/arch/mips/kernel/smp-mt.c +@@ -108,12 +108,18 @@ static void __init smvp_tc_init(unsigned + static void vsmp_init_secondary(void) + { + /* This is Malta specific: IPI,performance and timer interrupts */ ++ ++ /* RTL9300 Clear internal timer interrupt */ ++ write_c0_compare(0); ++ + if (mips_gic_present()) + change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 | + STATUSF_IP4 | STATUSF_IP5 | + STATUSF_IP6 | STATUSF_IP7); + else + change_c0_status(ST0_IM, STATUSF_IP0 | STATUSF_IP1 | ++ STATUSF_IP2 | STATUSF_IP3 | ++ STATUSF_IP4 | STATUSF_IP5 | + STATUSF_IP6 | STATUSF_IP7); + } + |