aboutsummaryrefslogtreecommitdiffstats
path: root/package/kernel/mac80211/patches/344-0011-brcmfmac-remove-pcie-gen1-support.patch
diff options
context:
space:
mode:
Diffstat (limited to 'package/kernel/mac80211/patches/344-0011-brcmfmac-remove-pcie-gen1-support.patch')
-rw-r--r--package/kernel/mac80211/patches/344-0011-brcmfmac-remove-pcie-gen1-support.patch221
1 files changed, 0 insertions, 221 deletions
diff --git a/package/kernel/mac80211/patches/344-0011-brcmfmac-remove-pcie-gen1-support.patch b/package/kernel/mac80211/patches/344-0011-brcmfmac-remove-pcie-gen1-support.patch
deleted file mode 100644
index f99f6dbf07..0000000000
--- a/package/kernel/mac80211/patches/344-0011-brcmfmac-remove-pcie-gen1-support.patch
+++ /dev/null
@@ -1,221 +0,0 @@
-From: Hante Meuleman <meuleman@broadcom.com>
-Date: Wed, 17 Feb 2016 11:27:00 +0100
-Subject: [PATCH] brcmfmac: remove pcie gen1 support
-
-The PCIE bus driver supports older gen1 (v1) chips, but there is no
-actual device which is using this older pcie core which is supported
-by brcmfmac. Remove all gen1 related code.
-
-Reviewed-by: Arend Van Spriel <arend@broadcom.com>
-Reviewed-by: Franky (Zhenhui) Lin <frankyl@broadcom.com>
-Reviewed-by: Pieter-Paul Giesberts <pieterpg@broadcom.com>
-Signed-off-by: Hante Meuleman <meuleman@broadcom.com>
-Signed-off-by: Arend van Spriel <arend@broadcom.com>
-Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
----
-
---- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c
-+++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c
-@@ -100,9 +100,6 @@ static struct brcmf_firmware_mapping brc
- #define BRCMF_PCIE_PCIE2REG_CONFIGDATA 0x124
- #define BRCMF_PCIE_PCIE2REG_H2D_MAILBOX 0x140
-
--#define BRCMF_PCIE_GENREV1 1
--#define BRCMF_PCIE_GENREV2 2
--
- #define BRCMF_PCIE2_INTA 0x01
- #define BRCMF_PCIE2_INTB 0x02
-
-@@ -257,9 +254,7 @@ struct brcmf_pciedev_info {
- u32 ram_size;
- struct brcmf_chip *ci;
- u32 coreid;
-- u32 generic_corerev;
- struct brcmf_pcie_shared_info shared;
-- void (*ringbell)(struct brcmf_pciedev_info *devinfo);
- wait_queue_head_t mbdata_resp_wait;
- bool mbdata_completed;
- bool irq_allocated;
-@@ -746,68 +741,22 @@ static void brcmf_pcie_bus_console_read(
- }
-
-
--static __used void brcmf_pcie_ringbell_v1(struct brcmf_pciedev_info *devinfo)
--{
-- u32 reg_value;
--
-- brcmf_dbg(PCIE, "RING !\n");
-- reg_value = brcmf_pcie_read_reg32(devinfo,
-- BRCMF_PCIE_PCIE2REG_MAILBOXINT);
-- reg_value |= BRCMF_PCIE2_INTB;
-- brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
-- reg_value);
--}
--
--
--static void brcmf_pcie_ringbell_v2(struct brcmf_pciedev_info *devinfo)
--{
-- brcmf_dbg(PCIE, "RING !\n");
-- /* Any arbitrary value will do, lets use 1 */
-- brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_H2D_MAILBOX, 1);
--}
--
--
- static void brcmf_pcie_intr_disable(struct brcmf_pciedev_info *devinfo)
- {
-- if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1)
-- pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_INTMASK,
-- 0);
-- else
-- brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK,
-- 0);
-+ brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK, 0);
- }
-
-
- static void brcmf_pcie_intr_enable(struct brcmf_pciedev_info *devinfo)
- {
-- if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1)
-- pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_INTMASK,
-- BRCMF_PCIE_INT_DEF);
-- else
-- brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK,
-- BRCMF_PCIE_MB_INT_D2H_DB |
-- BRCMF_PCIE_MB_INT_FN0_0 |
-- BRCMF_PCIE_MB_INT_FN0_1);
-+ brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK,
-+ BRCMF_PCIE_MB_INT_D2H_DB |
-+ BRCMF_PCIE_MB_INT_FN0_0 |
-+ BRCMF_PCIE_MB_INT_FN0_1);
- }
-
-
--static irqreturn_t brcmf_pcie_quick_check_isr_v1(int irq, void *arg)
--{
-- struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
-- u32 status;
--
-- status = 0;
-- pci_read_config_dword(devinfo->pdev, BRCMF_PCIE_REG_INTSTATUS, &status);
-- if (status) {
-- brcmf_pcie_intr_disable(devinfo);
-- brcmf_dbg(PCIE, "Enter\n");
-- return IRQ_WAKE_THREAD;
-- }
-- return IRQ_NONE;
--}
--
--
--static irqreturn_t brcmf_pcie_quick_check_isr_v2(int irq, void *arg)
-+static irqreturn_t brcmf_pcie_quick_check_isr(int irq, void *arg)
- {
- struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
-
-@@ -820,29 +769,7 @@ static irqreturn_t brcmf_pcie_quick_chec
- }
-
-
--static irqreturn_t brcmf_pcie_isr_thread_v1(int irq, void *arg)
--{
-- struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
-- const struct pci_dev *pdev = devinfo->pdev;
-- u32 status;
--
-- devinfo->in_irq = true;
-- status = 0;
-- pci_read_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, &status);
-- brcmf_dbg(PCIE, "Enter %x\n", status);
-- if (status) {
-- pci_write_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, status);
-- if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
-- brcmf_proto_msgbuf_rx_trigger(&devinfo->pdev->dev);
-- }
-- if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
-- brcmf_pcie_intr_enable(devinfo);
-- devinfo->in_irq = false;
-- return IRQ_HANDLED;
--}
--
--
--static irqreturn_t brcmf_pcie_isr_thread_v2(int irq, void *arg)
-+static irqreturn_t brcmf_pcie_isr_thread(int irq, void *arg)
- {
- struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
- u32 status;
-@@ -879,28 +806,14 @@ static int brcmf_pcie_request_irq(struct
- brcmf_pcie_intr_disable(devinfo);
-
- brcmf_dbg(PCIE, "Enter\n");
-- /* is it a v1 or v2 implementation */
-+
- pci_enable_msi(pdev);
-- if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1) {
-- if (request_threaded_irq(pdev->irq,
-- brcmf_pcie_quick_check_isr_v1,
-- brcmf_pcie_isr_thread_v1,
-- IRQF_SHARED, "brcmf_pcie_intr",
-- devinfo)) {
-- pci_disable_msi(pdev);
-- brcmf_err("Failed to request IRQ %d\n", pdev->irq);
-- return -EIO;
-- }
-- } else {
-- if (request_threaded_irq(pdev->irq,
-- brcmf_pcie_quick_check_isr_v2,
-- brcmf_pcie_isr_thread_v2,
-- IRQF_SHARED, "brcmf_pcie_intr",
-- devinfo)) {
-- pci_disable_msi(pdev);
-- brcmf_err("Failed to request IRQ %d\n", pdev->irq);
-- return -EIO;
-- }
-+ if (request_threaded_irq(pdev->irq, brcmf_pcie_quick_check_isr,
-+ brcmf_pcie_isr_thread, IRQF_SHARED,
-+ "brcmf_pcie_intr", devinfo)) {
-+ pci_disable_msi(pdev);
-+ brcmf_err("Failed to request IRQ %d\n", pdev->irq);
-+ return -EIO;
- }
- devinfo->irq_allocated = true;
- return 0;
-@@ -931,16 +844,9 @@ static void brcmf_pcie_release_irq(struc
- if (devinfo->in_irq)
- brcmf_err("Still in IRQ (processing) !!!\n");
-
-- if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1) {
-- status = 0;
-- pci_read_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, &status);
-- pci_write_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, status);
-- } else {
-- status = brcmf_pcie_read_reg32(devinfo,
-- BRCMF_PCIE_PCIE2REG_MAILBOXINT);
-- brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
-- status);
-- }
-+ status = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT);
-+ brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT, status);
-+
- devinfo->irq_allocated = false;
- }
-
-@@ -989,7 +895,9 @@ static int brcmf_pcie_ring_mb_ring_bell(
- if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
- return -EIO;
-
-- devinfo->ringbell(devinfo);
-+ brcmf_dbg(PCIE, "RING !\n");
-+ /* Any arbitrary value will do, lets use 1 */
-+ brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_H2D_MAILBOX, 1);
-
- return 0;
- }
-@@ -1503,9 +1411,6 @@ static int brcmf_pcie_download_fw_nvram(
- u32 address;
- u32 resetintr;
-
-- devinfo->ringbell = brcmf_pcie_ringbell_v2;
-- devinfo->generic_corerev = BRCMF_PCIE_GENREV2;
--
- brcmf_dbg(PCIE, "Halt ARM.\n");
- err = brcmf_pcie_enter_download_state(devinfo);
- if (err)
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-07 19:57:26 +0000