diff options
Diffstat (limited to 'package/kernel/mac80211/patches/651-0011-rtl8xxxu-Add-interrupt-bit-definitions-for-gen2-part.patch')
| -rw-r--r-- | package/kernel/mac80211/patches/651-0011-rtl8xxxu-Add-interrupt-bit-definitions-for-gen2-part.patch | 82 |
1 files changed, 82 insertions, 0 deletions
diff --git a/package/kernel/mac80211/patches/651-0011-rtl8xxxu-Add-interrupt-bit-definitions-for-gen2-part.patch b/package/kernel/mac80211/patches/651-0011-rtl8xxxu-Add-interrupt-bit-definitions-for-gen2-part.patch new file mode 100644 index 0000000000..d8ca286678 --- /dev/null +++ b/package/kernel/mac80211/patches/651-0011-rtl8xxxu-Add-interrupt-bit-definitions-for-gen2-part.patch @@ -0,0 +1,82 @@ +From b11b4053e28ebcd35fca0b81448ee91ef88a6fed Mon Sep 17 00:00:00 2001 +From: Jes Sorensen <Jes.Sorensen@redhat.com> +Date: Wed, 20 Jul 2016 16:52:13 -0400 +Subject: [PATCH] rtl8xxxu: Add interrupt bit definitions for gen2 parts + +These are primarily needed for SDIO/PCI parts, but the vendor driver +still sets them for some USB devices. + +Signed-off-by: Jes Sorensen <Jes.Sorensen@redhat.com> +--- + .../net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h | 56 ++++++++++++++++++++++ + 1 file changed, 56 insertions(+) + +--- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h ++++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h +@@ -213,10 +213,66 @@ + #define REG_HMBOX_EXT_1 0x008a + #define REG_HMBOX_EXT_2 0x008c + #define REG_HMBOX_EXT_3 0x008e ++ + /* Interrupt registers for 8192e/8723bu/8812 */ + #define REG_HIMR0 0x00b0 ++#define IMR0_TXCCK BIT(30) /* TXRPT interrupt when CCX bit ++ of the packet is set */ ++#define IMR0_PSTIMEOUT BIT(29) /* Power Save Time Out Int */ ++#define IMR0_GTINT4 BIT(28) /* Set when GTIMER4 expires */ ++#define IMR0_GTINT3 BIT(27) /* Set when GTIMER3 expires */ ++#define IMR0_TBDER BIT(26) /* Transmit Beacon0 Error */ ++#define IMR0_TBDOK BIT(25) /* Transmit Beacon0 OK */ ++#define IMR0_TSF_BIT32_TOGGLE BIT(24) /* TSF Timer BIT32 toggle ++ indication interrupt */ ++#define IMR0_BCNDMAINT0 BIT(20) /* Beacon DMA Interrupt 0 */ ++#define IMR0_BCNDERR0 BIT(16) /* Beacon Queue DMA Error 0 */ ++#define IMR0_HSISR_IND_ON_INT BIT(15) /* HSISR Indicator (HSIMR & ++ HSISR is true) */ ++#define IMR0_BCNDMAINT_E BIT(14) /* Beacon DMA Interrupt ++ Extension for Win7 */ ++#define IMR0_ATIMEND BIT(12) /* CTWidnow End or ++ ATIM Window End */ ++#define IMR0_HISR1_IND_INT BIT(11) /* HISR1 Indicator ++ (HISR1 & HIMR1 is true) */ ++#define IMR0_C2HCMD BIT(10) /* CPU to Host Command INT ++ Status, Write 1 to clear */ ++#define IMR0_CPWM2 BIT(9) /* CPU power Mode exchange INT ++ Status, Write 1 to clear */ ++#define IMR0_CPWM BIT(8) /* CPU power Mode exchange INT ++ Status, Write 1 to clear */ ++#define IMR0_HIGHDOK BIT(7) /* High Queue DMA OK */ ++#define IMR0_MGNTDOK BIT(6) /* Management Queue DMA OK */ ++#define IMR0_BKDOK BIT(5) /* AC_BK DMA OK */ ++#define IMR0_BEDOK BIT(4) /* AC_BE DMA OK */ ++#define IMR0_VIDOK BIT(3) /* AC_VI DMA OK */ ++#define IMR0_VODOK BIT(2) /* AC_VO DMA OK */ ++#define IMR0_RDU BIT(1) /* Rx Descriptor Unavailable */ ++#define IMR0_ROK BIT(0) /* Receive DMA OK */ + #define REG_HISR0 0x00b4 + #define REG_HIMR1 0x00b8 ++#define IMR1_BCNDMAINT7 BIT(27) /* Beacon DMA Interrupt 7 */ ++#define IMR1_BCNDMAINT6 BIT(26) /* Beacon DMA Interrupt 6 */ ++#define IMR1_BCNDMAINT5 BIT(25) /* Beacon DMA Interrupt 5 */ ++#define IMR1_BCNDMAINT4 BIT(24) /* Beacon DMA Interrupt 4 */ ++#define IMR1_BCNDMAINT3 BIT(23) /* Beacon DMA Interrupt 3 */ ++#define IMR1_BCNDMAINT2 BIT(22) /* Beacon DMA Interrupt 2 */ ++#define IMR1_BCNDMAINT1 BIT(21) /* Beacon DMA Interrupt 1 */ ++#define IMR1_BCNDERR7 BIT(20) /* Beacon Queue DMA Err Int 7 */ ++#define IMR1_BCNDERR6 BIT(19) /* Beacon Queue DMA Err Int 6 */ ++#define IMR1_BCNDERR5 BIT(18) /* Beacon Queue DMA Err Int 5 */ ++#define IMR1_BCNDERR4 BIT(17) /* Beacon Queue DMA Err Int 4 */ ++#define IMR1_BCNDERR3 BIT(16) /* Beacon Queue DMA Err Int 3 */ ++#define IMR1_BCNDERR2 BIT(15) /* Beacon Queue DMA Err Int 2 */ ++#define IMR1_BCNDERR1 BIT(14) /* Beacon Queue DMA Err Int 1 */ ++#define IMR1_ATIMEND_E BIT(13) /* ATIM Window End Extension ++ for Win7 */ ++#define IMR1_TXERR BIT(11) /* Tx Error Flag Int Status, ++ write 1 to clear */ ++#define IMR1_RXERR BIT(10) /* Rx Error Flag Int Status, ++ write 1 to clear */ ++#define IMR1_TXFOVW BIT(9) /* Transmit FIFO Overflow */ ++#define IMR1_RXFOVW BIT(8) /* Receive FIFO Overflow */ + #define REG_HISR1 0x00bc + + /* Host suspend counter on FPGA platform */ |