diff options
Diffstat (limited to 'target/linux/bmips/patches-5.10/004-v5.11-mips-bmips-dts-add-BCM6328-reset-controller-support.patch')
| -rw-r--r-- | target/linux/bmips/patches-5.10/004-v5.11-mips-bmips-dts-add-BCM6328-reset-controller-support.patch | 56 |
1 files changed, 0 insertions, 56 deletions
diff --git a/target/linux/bmips/patches-5.10/004-v5.11-mips-bmips-dts-add-BCM6328-reset-controller-support.patch b/target/linux/bmips/patches-5.10/004-v5.11-mips-bmips-dts-add-BCM6328-reset-controller-support.patch deleted file mode 100644 index 85c63f6bd1..0000000000 --- a/target/linux/bmips/patches-5.10/004-v5.11-mips-bmips-dts-add-BCM6328-reset-controller-support.patch +++ /dev/null @@ -1,56 +0,0 @@ -From 83f865d7e32e40b4903b1f83537c63fc5cdf1eb8 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com> -Date: Wed, 17 Jun 2020 12:50:36 +0200 -Subject: [PATCH 4/9] mips: bmips: dts: add BCM6328 reset controller support -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -BCM6328 SoCs have a reset controller for certain components. - -Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> -Acked-by: Florian Fainelli <f.fainelli@gmail.com> -Reviewed-by: Rob Herring <robh@kernel.org> -Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> ---- - arch/mips/boot/dts/brcm/bcm6328.dtsi | 6 ++++++ - include/dt-bindings/reset/bcm6328-reset.h | 18 ++++++++++++++++++ - 2 files changed, 24 insertions(+) - create mode 100644 include/dt-bindings/reset/bcm6328-reset.h - ---- a/arch/mips/boot/dts/brcm/bcm6328.dtsi -+++ b/arch/mips/boot/dts/brcm/bcm6328.dtsi -@@ -57,6 +57,12 @@ - #clock-cells = <1>; - }; - -+ periph_rst: reset-controller@10000010 { -+ compatible = "brcm,bcm6345-reset"; -+ reg = <0x10000010 0x4>; -+ #reset-cells = <1>; -+ }; -+ - periph_intc: interrupt-controller@10000020 { - compatible = "brcm,bcm6345-l1-intc"; - reg = <0x10000020 0x10>, ---- /dev/null -+++ b/include/dt-bindings/reset/bcm6328-reset.h -@@ -0,0 +1,18 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+ -+#ifndef __DT_BINDINGS_RESET_BCM6328_H -+#define __DT_BINDINGS_RESET_BCM6328_H -+ -+#define BCM6328_RST_SPI 0 -+#define BCM6328_RST_EPHY 1 -+#define BCM6328_RST_SAR 2 -+#define BCM6328_RST_ENETSW 3 -+#define BCM6328_RST_USBS 4 -+#define BCM6328_RST_USBH 5 -+#define BCM6328_RST_PCM 6 -+#define BCM6328_RST_PCIE_CORE 7 -+#define BCM6328_RST_PCIE 8 -+#define BCM6328_RST_PCIE_EXT 9 -+#define BCM6328_RST_PCIE_HARD 10 -+ -+#endif /* __DT_BINDINGS_RESET_BCM6328_H */ |