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* download.pl: Change OpenWrt mirrors to HTTPS.Rosen Penev2018-05-011-4/+4
| | | | | | These have supported HTTPS for quite a while. I have not seen any obvious breakage. Signed-off-by: Rosen Penev <rosenp@gmail.com>
* download.pl: Change SourceForge address to HTTPS.Rosen Penev2018-05-011-1/+1
| | | | | | | | SourceForge has supported HTTPS for its downloads for a long time now. I have not been able to see any failures resulting from this change. Signed-off-by: Rosen Penev <rosenp@gmail.com>
* mtd-utils: add back macOS compatibility code that was dropped during the updateFelix Fietkau2018-04-301-0/+12
| | | | Signed-off-by: Felix Fietkau <nbd@nbd.name>
* kernel: Restrict dmesg output to root.Rosen Penev2018-04-304-4/+4
| | | | | | | | In typical OpenWrt setups, there are no other users that have a shell spawned for them by default. This can be overriden by the kernel.dmesg_output syssctl. Signed-off-by: Rosen Penev <rosenp@gmail.com>
* libnl: Disable debug supportHauke Mehrtens2018-04-301-0/+3
| | | | | | | | | | | | | | | | | | | This dereses the size of the libnl pakcage a little bit old: 857 bin/packages/mips_24kc/base/libnl_3.4.0-1_mips_24kc.ipk 41195 bin/packages/mips_24kc/base/libnl-core_3.4.0-1_mips_24kc.ipk 7818 bin/packages/mips_24kc/base/libnl-genl_3.4.0-1_mips_24kc.ipk 24322 bin/packages/mips_24kc/base/libnl-nf_3.4.0-1_mips_24kc.ipk 136075 bin/packages/mips_24kc/base/libnl-route_3.4.0-1_mips_24kc.ipk new: 852 bin/packages/mips_24kc/base/libnl_3.4.0-1_mips_24kc.ipk 35020 bin/packages/mips_24kc/base/libnl-core_3.4.0-1_mips_24kc.ipk 7615 bin/packages/mips_24kc/base/libnl-genl_3.4.0-1_mips_24kc.ipk 24114 bin/packages/mips_24kc/base/libnl-nf_3.4.0-1_mips_24kc.ipk 131134 bin/packages/mips_24kc/base/libnl-route_3.4.0-1_mips_24kc.ipk Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
* at91: sama5: remove neon and VFPv4 supportSandeep Sheriker Mallikarjun2018-04-301-3/+1
| | | | | | | | | sama5d2 & samad4 have neon feature and sama5d3 does not have neon feature due to which sama5d3 boot fails with error message Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000004. removing neon & VFPv4 support to fix this Signed-off-by: Sandeep Sheriker Mallikarjun <sandeepsheriker.mallikarjun@microchip.com>
* at91: fix build error for wb50n.Sandeep Sheriker Mallikarjun2018-04-301-10/+14
| | | | | | | when external kernel is selected from menuconfig, device wb50n is not avaliable and build fails. As a fix adding checks for external kernel. Signed-off-by: Sandeep Sheriker Mallikarjun <sandeepsheriker.mallikarjun@microchip.com>
* libusb: Update to 1.0.22Rosen Penev2018-04-301-4/+4
| | | | | | | | | | Switched download from SourceForge to GitHub. It seems the author migrated to that. Also fixed the website URL as the SourceForge link is dead. Compile tested on ar71xx and mvebu. Small size decrease on ar71xx: 30444 vs. 30099 bytes. Signed-off-by: Rosen Penev <rosenp@gmail.com>
* ar71xx: Add userspace support for Mikrotik rb-2011iLSSimon Paterson2018-04-306-0/+10
| | | | | | | | | | Kernel support already present. Patch adds userspace for the 'iLS' suffix model of the RB2011 family. Enables correct initial switch settings, sysupgrade, etc. https://mikrotik.com/product/RB2011iLS-IN Signed-off-by: Simon Paterson <simon.paterson.nz@gmail.com>
* kernel: bump 4.14 to 4.14.37Koen Vandeputte2018-04-303-4/+4
| | | | | | | | | | | | Refreshed all patches Compile-tested on: cns3xxx, imx6, octeon, ramips/mt7621, x86/64 Runtime-tested on: cns3xxx, imx6, octeon, ramips/mt7621, x86/64 Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com> Tested-by: Stijn Segers <foss@volatilesystems.org> [add extra tested targets to commit msg] Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
* odhcp6c: update to latest git HEADHans Dedecker2018-04-291-3/+3
| | | | | | | 5316d7f ra: always trigger update in case of RA parameter change 327f73d dhcpv6: fix strncpy bounds Signed-off-by: Hans Dedecker <dedeckeh@gmail.com>
* toolchain/binutils: Use xz tarballs where possibleDaniel Engberg2018-04-291-3/+4
| | | | | | | Switch to xz for 2.29.1 and 2.30 These tarballs are about 10Mbyte smaller than bz2. Signed-off-by: Daniel Engberg <daniel.engberg.lists@pyret.net>
* glibc: switch from git to httpsJohann Neuhauser2018-04-291-1/+1
| | | | | | This is needed for working behind a http proxy. Signed-off-by: Johann Neuhauser <jneuhauser@dh-electronics.de>
* uboot-mvebu: Fix build with libressl 2.7.2Hauke Mehrtens2018-04-291-0/+14
| | | | | | | When libressl was linked the libpthread was missing, add it in addition. Fixes: 2c192b69163f ("tools/libressl: update to version 2.7.2") Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
* uboot-mxs: Fix build with libressl 2.7.2Hauke Mehrtens2018-04-292-16/+31
| | | | | | | | | When libressl was linked the libpthread was missing, add it in addition. Also make the mxsimage tool to use the OpenSSL 1.1 API for the recent libressl version. Fixes: 2c192b69163f ("tools/libressl: update to version 2.7.2") Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
* uboot-zynq: Fix build with libressl 2.7.2Hauke Mehrtens2018-04-291-0/+14
| | | | | | | When libressl was linked the libpthread was missing, add it in addition. Fixes: 2c192b69163f ("tools/libressl: update to version 2.7.2") Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
* tools/make-ext4fs: Fix build on MacOSXHauke Mehrtens2018-04-291-2/+0
| | | | | | | | | | | MacOSX does not support "-Wl,-Bstatic" so do not force the static linking. We only copy the static libz library into the staging libraries directories, the linker will anyway only find the static version and link against that on all systems. Fixes: 8dcd941d8b9 ("tools/zlib: move zlib build to tools") Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
* tools/libressl: update to version 2.7.2Hauke Mehrtens2018-04-284-3/+112
| | | | | | | Libressl version 2.7.0 and later implement more of the OpenSSL 1.1 API and this needs some modifications of the code using it. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
* mtd-utils: activate --gc-sectionsHauke Mehrtens2018-04-281-0/+3
| | | | | | | | | | | | | | | This reduces the size of the binary a bit: old: 37556 bin/targets/lantiq/xrx200/packages/nand-utils_2.0.1-1_mips_24kc.ipk 81697 bin/targets/lantiq/xrx200/packages/ubi-utils_2.0.1-1_mips_24kc.ipk new: 27450 bin/targets/lantiq/xrx200/packages/nand-utils_2.0.1-1_mips_24kc.ipk 71796 bin/targets/lantiq/xrx200/packages/ubi-utils_2.0.1-1_mips_24kc.ipk Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Tested-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
* mtd-utils: update to 2.0.2Syrone Wong2018-04-284-62/+47
| | | | | | | | | | | | 010-fix-rpmatch.patch is upstream, removed from our patchset The file structure is changed, modify patch accordingly use CONFIGURE_ARGS to disable tests, xattr and lzo Compile and run tested on mvebu and x86_64 Signed-off-by: Syrone Wong <wong.syrone@gmail.com> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Tested-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
* tools/mtd-utils: update to version 2.0.2Hauke Mehrtens2018-04-2811-303/+101
| | | | | | | | This version now uses autotools to configure the build system. They are also using the newly added zlib package. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Tested-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
* tools/mtd-utils: Mark some lzma functions as staticHauke Mehrtens2018-04-281-37/+37
| | | | | | | | | | | | | | | These functions are not declared in any header file and only used in same compile unit, mark them as static to remove one gcc warning and make it easier for the compiler to optimize them out. This also fixes some style problems to make this patch match the version in the packages folder. This is copied from this commit to the mtd-utils we pack into the image: 56d0dd56e9c6efa79 ("mtd-utils: Mark some lzma functions as static") Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Tested-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
* tools/zlib: move zlib build to toolsHauke Mehrtens2018-04-289-20/+76
| | | | | | | | | | | | | This allows us to link the other tools against our libz and we do not need the system zlib any more. Only the static linked library is copied to the staging directory so we have a statically linked library on all systems and not only on Linux. This also adds the new dependencies of the packages which are depending on zlib. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Tested-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
* netifd: update to latest git HEAD (Coverity fixes)Hans Dedecker2018-04-271-3/+3
| | | | | | | 56ceced interface-ip: remove superfluous iface check in interface_ip_set_enabled() 4f4a8c0 system-linux: fix strncpy bounds Signed-off-by: Hans Dedecker <dedeckeh@gmail.com>
* arm64: enable harden branch predictorMathias Kresin2018-04-276-2/+10
| | | | | | Enable the harden branch predictor for arm64 as it is recommend. Signed-off-by: Mathias Kresin <dev@kresin.me>
* kernel: add missing config symbolsMathias Kresin2018-04-272-6/+4
| | | | | | | | The harden branch predictor was backported for arm64 with 4.9.92-96. Fixes: 9aa196e0f260 ("kernel: bump 4.9 to bump 4.9.96") Signed-off-by: Mathias Kresin <dev@kresin.me>
* build: add support for git submodules with CONFIG_SRC_TREE_OVERRIDEFelix Fietkau2018-04-271-1/+6
| | | | | | | Also work around an issue where git would store the modified workdir in the submodule git config files Signed-off-by: Felix Fietkau <nbd@nbd.name>
* scripts/feeds: add support for git feeds with submodulesFelix Fietkau2018-04-271-0/+6
| | | | Signed-off-by: Felix Fietkau <nbd@nbd.name>
* brcm47xx: remove linux 4.4 supportFelix Fietkau2018-04-2725-2935/+0
| | | | Signed-off-by: Felix Fietkau <nbd@nbd.name>
* brcm63xx: remove linux 4.4 supportFelix Fietkau2018-04-27233-29054/+0
| | | | Signed-off-by: Felix Fietkau <nbd@nbd.name>
* bcm53xx: drop linux 4.4 and 4.9 supportFelix Fietkau2018-04-27179-21831/+0
| | | | Signed-off-by: Felix Fietkau <nbd@nbd.name>
* brcm2708: Add support for raspberry pi 3 b+.Christo Nedev2018-04-276-7/+309
| | | | Signed-off-by: Christo Nedev <christo.nedev@me.com>
* kernel: Fix data corruption on some mips devices.Rosen Penev2018-04-271-0/+92
| | | | | | | | | | This is mainly a bug fix for multi-core MIPS systems where L1 caches besides the primary do not get flushed. The most obvious problem is data corruption on SATA and USB devices where read requests are typically larger than the cacheline size. This may also fix ar71xx systems that suffer from similar data corruption but I have not tested if it does. Signed-off-by: Rosen Penev <rosenp@gmail.com>
* iftop: bump to latestKevin Darbyshire-Bryant2018-04-271-3/+3
| | | | | | | | | | | | The sender domain has a DMARC Reject/Quarantine policy which disallows sending mailing list messages using the original "From" header. To mitigate this problem, the original message has been wrapped automatically by the mailing list software. Choose first running interface, rather than first "up" interface (Redhat #1403025) Signed-off-by: Kevin Darbyshire-Bryant <ldir@darbyshire-bryant.me.uk> Tested-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
* ar71xx: Ubiquiti Airmax M: add relocate-kernel to invalidate cacheMatthias Schiffer2018-04-261-0/+1
| | | | | | | | | | | | | | Some Ubiquiti U-boot versions, in particular the "U-Boot 1.1.4.2-s956 (Jun 10 2015 - 10:54:50)" found with AirOS 5.6, do not correctly flush the caches for the whole kernel address range after decompressing the kernel image, leading to hard to debug boot failures, depending on kernel version and configuration. As a workaround, prepend the relocate-kernels loader, which will invalidate the caches after moving the kernel to the correct load address. Reported-by: Andreas Ziegler <dev@andreas-ziegler.de> Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net>
* scripts: bundle-libraries: fix build on OS X (FS#1493)Jo-Philipp Wich2018-04-261-0/+4
| | | | | | | | This allegedly fixes compilation of the library bundler preload library on Apple OS X. The resulting executables have not been runtime tested due to a lack of suitable test hardware. Signed-off-by: Jo-Philipp Wich <jo@mein.io>
* toolchain/binutils: Remove old patchesDaniel Engberg2018-04-262-42/+0
| | | | | | | | Remove patches for arc-2016.09 Commit https://github.com/openwrt/openwrt/commit/8647f4f018e4dee663b65948d75105fae7bb3cdc made these patches obsolete Signed-off-by: Daniel Engberg <daniel.engberg.lists@pyret.net>
* toolchain/binutils: completely remove 2.28 supportHans Dedecker2018-04-261-5/+0
| | | | | | | | Commit 15e963915963cda515311531b182b9e0c52f35a0 removed support for binutils version 2.28 but did not remove it as selectable item from Binutils Version; let's remove this leftover as well. Signed-off-by: Hans Dedecker <dedeckeh@gmail.com>
* kernel: bump 4.14 to 4.14.36Koen Vandeputte2018-04-266-12/+12
| | | | | | | | | | | | | | | | Refreshed all patches. Compile-tested on: cns3xxx, imx6 Runtime-tested on: cns3xxx, imx6 Fixes for CVEs: CVE-2018-1108 CVE-2018-1092 CVE-2018-1094 CVE-2018-1095 Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com> Tested-by: Stijn Segers <foss@volatilesystems.org>
* kernel: bump 4.9 to 4.9.96Kevin Darbyshire-Bryant2018-04-2646-391/+337
| | | | | | | | | | | | | | | | | | Refresh patches, following required reworking: ar71xx/patches-4.9/930-chipidea-pullup.patch layerscape/patches-4.9/302-dts-support-layercape.patch sunxi/patches-4.9/0052-stmmac-form-4-12.patch Fixes for CVEs: CVE-2018-1108 CVE-2018-1092 Tested on: ar71xx Archer C7 v2 Signed-off-by: Kevin Darbyshire-Bryant <ldir@darbyshire-bryant.me.uk> Tested-by: Koen Vandeputte <koen.vandeputte@ncentric.com> Tested-by: Arjen de Korte <build+openwrt@de-korte.org>
* uboot-envtools: add support for ESPRESSObin and MACCHIATObinDamir Samardzic2018-04-251-0/+4
| | | | | | | | Added for convenience. These boards can be used as dev boards running various operating systems from different media, and this simplifies work with U-Boot environment. Signed-off-by: Damir Samardzic <damir.samardzic@sartura.hr>
* mvebu: cortexa72: enable Marvell 10G PHY by defaultDamir Samardzic2018-04-251-0/+1
| | | | | | This one enables 10 GbE ports on MACCHIATObin. Signed-off-by: Damir Samardzic <damir.samardzic@sartura.hr>
* ramips: fix mt7628 eval board pinmuxMathias Kresin2018-04-251-1/+1
| | | | | | | | | There is no pinmux group "jtag" for mt7628 and the pinmux driver fails to load due to the use of the not existing group. Fixes: FS#1515 Signed-off-by: Mathias Kresin <dev@kresin.me>
* ramips: create image for mt7628 evb boardMathias Kresin2018-04-231-0/+1
| | | | | | | The image for the EVB board got lost with the merge of the mt7628 and mt7688 subtargets. Signed-off-by: Mathias Kresin <dev@kresin.me>
* firmware-utils: tplink-safeloader: increase RE350 kernel sizeAlex Maclean2018-04-231-3/+3
| | | | | | | | 4.14 increased kernel size, so grow the kernel partition by 128K to compensate. Fixes FS#1479. Signed-off-by: Alex Maclean <monkeh@monkeh.net>
* ramips: use patch-dtb for F5D8235 V1Tobias Wolf2018-04-231-3/+1
| | | | | | | | | | The old DTB method (OWRTDTB) is not recognized by the boot process anymore with 4.9/4.14. This patch reuses KERNEL_DTB to get a valid DTB applied to the kernel image. Signed-off-by: Tobias Wolf <github-NTEO@vplace.de>
* kernel: fix usb interface on 3G dwm-158 modemGiuseppe Lippolis2018-04-231-0/+42
| | | | | | | | | | | | The current option driver binds to the usb interface 2,3,4,5. But the interface 4 and 5 doesn't answer to the AT commands. On the new openwrt configuration the wwan script select the 5th interface as control interface, failing to establish the 3G connection. Backport the fix for the problem. Signed-off-by: Giuseppe Lippolis <giu.lippolis@gmail.com>
* ipq40xx: add support for OpenMesh A62Sven Eckelmann2018-04-239-7/+287
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * QCA IPQ4019 * 256 MB of RAM * 32 MB of SPI NOR flash (s25fl256s1) - 2x 15 MB available; but one of the 15 MB regions is the recovery image * 2T2R 2.4 GHz - QCA4019 hw1.0 (SoC) - requires special BDF in QCA4019/hw1.0/board-2.bin with bus=ahb,bmi-chip-id=0,bmi-board-id=20,variant=OM-A62 * 2T2R 5 GHz (channel 36-64) - QCA9888 hw2.0 (PCI) - requires special BDF in QCA9888/hw2.0/board-2.bin bus=pci,bmi-chip-id=0,bmi-board-id=16,variant=OM-A62 * 2T2R 5 GHz (channel 100-165) - QCA4019 hw1.0 (SoC) - requires special BDF in QCA4019/hw1.0/board-2.bin with bus=ahb,bmi-chip-id=0,bmi-board-id=21,variant=OM-A62 * multi-color LED (controlled via red/green/blue GPIOs) * 1x button (reset; kmod-input-gpio-keys compatible) * external watchdog - triggered GPIO * 1x USB (xHCI) * TTL pins are on board (arrow points to VCC, then follows: GND, TX, RX) * 2x gigabit ethernet - phy@mdio3: + Label: Ethernet 1 + gmac0 (ethaddr) in original firmware + 802.3at POE+ - phy@mdio4: + Label: Ethernet 2 + gmac1 (eth1addr) in original firmware + 18-24V passive POE (mode B) * powered only via POE The tool ap51-flash (https://github.com/ap51-flash/ap51-flash) should be used to transfer the factory image to the u-boot when the device boots up. The initramfs image can be started using setenv bootargs 'loglevel=8 earlycon=msm_serial_dm,0x78af000 console=ttyMSM0,115200 mtdparts=spi0.0:256k(0:SBL1),128k(0:MIBIB),384k(0:QSEE),64k(0:CDT),64k(0:DDRPARAMS),64k(0:APPSBLENV),512k(0:APPSBL),64k(0:ART),64k(0:custom),64k(0:KEYS),15552k(inactive),15552k(inactive2)' tftpboot 0x84000000 openwrt-ipq40xx-openmesh_a62-initramfs-fit-uImage.itb set fdt_high 0x85000000 bootm 0x84000000 Signed-off-by: Sven Eckelmann <sven.eckelmann@openmesh.com>
* ipq40xx: fix gpio-hog related boot issuesSven Eckelmann2018-04-236-6/+109
| | | | | | | | | | | | | | | The pinctrl initialization fails with the MSM pinctrl code and gpio-hogs because either the gpio ranges are not yet initialized (missing gpio-range in DT) or that the msm driver unconditionally tries to re-initializes the ranges (gpio-range in DT). To allow gpio-hogs and similar early-boot gpio code, the gpio-ranges must be in the device tree and the pinctrl-msm code must check whether the range was already initialized by the DT. Signed-off-by: Sven Eckelmann <sven.eckelmann@openmesh.com> [drop changes to unrelated dtsi files, refresh patches] Signed-off-by: Mathias Kresin <dev@kresin.me>
* ipq-wifi: drop custom board-2.binsSven Eckelmann2018-04-237-7/+3
| | | | | | | | | | | | | The BDFs for all boards were upstreamed to the ath10k-firmware repository and are now part of ath10k-firmware 2018-04-19. We switched to the upstream board-2.bin, hence the files can be removed here. Keep the ipq-wifi package in case new boards are added. It might take some time till board-2.bins send upstream are merged. Signed-off-by: Sven Eckelmann <sven.eckelmann@openmesh.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-10-02 00:08:27 +0000
t AST\_REDUCE\_XNOR} & The unary reduction operators \break \lstinline[language=Verilog];~;, \lstinline[language=Verilog];&;, \lstinline[language=Verilog];|;, \lstinline[language=Verilog];^; and \lstinline[language=Verilog];~^; \\ \hline % {\tt AST\_REDUCE\_BOOL} & Conversion from multi-bit value to boolian value (equivialent to {\tt AST\_REDUCE\_OR}) \\ \hline % {\tt AST\_SHIFT\_LEFT}, {\tt AST\_SHIFT\_RIGHT}, {\tt AST\_SHIFT\_SLEFT}, {\tt AST\_SHIFT\_SRIGHT} & The shift operators \break \lstinline[language=Verilog];<<;, \lstinline[language=Verilog];>>;, \lstinline[language=Verilog];<<<; and \lstinline[language=Verilog];>>>; \\ \hline % {\tt AST\_LT}, {\tt AST\_LE}, {\tt AST\_EQ}, {\tt AST\_NE}, {\tt AST\_GE}, {\tt AST\_GT} & The relational operators \break \lstinline[language=Verilog];<;, \lstinline[language=Verilog];<=;, \lstinline[language=Verilog];==;, \lstinline[language=Verilog];!=;, \lstinline[language=Verilog];>=; and \lstinline[language=Verilog];>; \\ \hline % {\tt AST\_ADD}, {\tt AST\_SUB}, {\tt AST\_MUL}, {\tt AST\_DIV}, {\tt AST\_MOD}, {\tt AST\_POW} & The binary operators \break \lstinline[language=Verilog];+;, \lstinline[language=Verilog];-;, \lstinline[language=Verilog];*;, \lstinline[language=Verilog];/;, \lstinline[language=Verilog];%; and \lstinline[language=Verilog];**; \\ \hline % {\tt AST\_POS}, {\tt AST\_NEG} & The prefix operators \lstinline[language=Verilog];+; and \lstinline[language=Verilog];-; \\ \hline % {\tt AST\_LOGIC\_AND}, {\tt AST\_LOGIC\_OR}, {\tt AST\_LOGIC\_NOT} & The logic operators \lstinline[language=Verilog];&&;, \lstinline[language=Verilog];||; and \lstinline[language=Verilog];!; \\ \hline % {\tt AST\_TERNARY} & The ternary \lstinline[language=Verilog];?:;-operator \\ \hline % {\tt AST\_MEMRD} {\tt AST\_MEMWR} & Read and write memories. These nodes are generated by the AST simplifier for writes/reads to/from Verilog arrays. \\ \hline % {\tt AST\_ASSIGN} & An \lstinline[language=Verilog];assign; statement \\ \hline % {\tt AST\_CELL} & A cell instanciation \\ \hline % {\tt AST\_PRIMITIVE} & A primitive cell (\lstinline[language=Verilog];and;, \lstinline[language=Verilog];nand;, \lstinline[language=Verilog];or;, etc.) \\ \hline % {\tt AST\_ALWAYS}, {\tt AST\_INITIAL} & Verilog \lstinline[language=Verilog];always;- and \lstinline[language=Verilog];initial;-blocks \\ \hline % {\tt AST\_BLOCK} & A \lstinline[language=Verilog];begin;-\lstinline[language=Verilog];end;-block \\ \hline % {\tt AST\_ASSIGN\_EQ}. {\tt AST\_ASSIGN\_LE} & Blocking (\lstinline[language=Verilog];=;) and nonblocking (\lstinline[language=Verilog];<=;) assignments within an \lstinline[language=Verilog];always;- or \lstinline[language=Verilog];initial;-block \\ \hline % {\tt AST\_CASE}. {\tt AST\_COND}, {\tt AST\_DEFAULT} & The \lstinline[language=Verilog];case; (\lstinline[language=Verilog];if;) statements, conditions within a case and the default case respectively \\ \hline % {\tt AST\_FOR} & A \lstinline[language=Verilog];for;-loop witn an \lstinline[language=Verilog];always;- or \lstinline[language=Verilog];initial;-block \\ \hline % {\tt AST\_GENVAR}, {\tt AST\_GENBLOCK}, {\tt AST\_GENFOR}, {\tt AST\_GENIF} & The \lstinline[language=Verilog];genvar; and \lstinline[language=Verilog];generate; keywords and \lstinline[language=Verilog];for; and \lstinline[language=Verilog];if; within a generate block. \\ \hline % {\tt AST\_POSEDGE}, {\tt AST\_NEGEDGE}, {\tt AST\_EDGE} & Event conditions for \lstinline[language=Verilog];always; blocks. \\ \hline \end{tabular} \caption{AST node types with their corresponding Verilog constructs. \\ (continuation from previous page)} \label{tab:Verilog_AstNodeTypeCont} \end{table} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \begin{itemize} \item {\bf The node type} \\ This enum (\lstinline[language=C++]{AST::AstNodeType}) specifies the role of the node. Table~\ref{tab:Verilog_AstNodeType} contains a list of all node types. \item {\bf The child nodes} \\ This is a list of pointers to all children in the abstract syntax tree. \item {\bf Attributes} \\ As almost every AST node might have Verilog attributes assigned to it, the \lstinline[language=C++]{AST::AstNode} has direct support for attributes. Note that the attribute values are again AST nodes. \item {\bf Node content} \\ Each node might have additional content data. A series of member variables exist to hold such data. For example the member \lstinline[language=C++]{std::string str} can hold a string value and is used e.g.~in the {\tt AST\_IDENTIFIER} node type to store the identifier name. \item {\bf Source code location} \\ Each \lstinline[language=C++]{AST::AstNode} is automatically annotated with the current source code location by the \lstinline[language=C++]{AST::AstNode} constructor. It is stored in the \lstinline[language=C++]{std::string filename} and \lstinline[language=C++]{int linenum} member variables. \end{itemize} The \lstinline[language=C++]{AST::AstNode} constructor can be called with up to two child nodes that are automatically added to the list of child nodes for the new object. This simplifies the creation of AST nodes for simple expressions a bit. For example the bison code for parsing multiplications: \begin{lstlisting}[numbers=left,frame=single] basic_expr '*' attr basic_expr { $$ = new AstNode(AST_MUL, $1, $4); append_attr($$, $3); } | \end{lstlisting} The generated AST data structure is then passed directly to the AST frontend that performs the actual conversion to RTLIL. Note that the Yosys command {\tt read\_verilog} provides the options {\tt -yydebug} and {\tt -dump\_ast} that can be used to print the parse tree or abstract syntax tree respectively. \section{Transforming AST to RTLIL} The {\it AST Frontend} converts a set of modules in AST representation to modules in RTLIL representation and adds them to the current design. This is done in two steps: {\it simplification} and {\it RTLIL generation}. The source code to the AST frontend can be found in {\tt frontends/ast/} in the Yosys source tree. \subsection{AST Simplification} A full-featured AST is too complex to be transformed into RTLIL directly. Therefore it must first be brought into a simpler form. This is done by calling the \lstinline[language=C++]{AST::AstNode::simplify()} method of all {\tt AST\_MODULE} nodes in the AST. This initiates a recursive process that performs the following transformations on the AST data structure: \begin{itemize} \item Inline all task and function calls. \item Evaluate all \lstinline[language=Verilog]{generate}-statements and unroll all \lstinline[language=Verilog]{for}-loops. \item Perform const folding where it is neccessary (e.g.~in the value part of {\tt AST\_PARAMETER}, {\tt AST\_LOCALPARAM}, {\tt AST\_PARASET} and {\tt AST\_RANGE} nodes). \item Replace {\tt AST\_PRIMITIVE} nodes with appropriate {\tt AST\_ASSIGN} nodes. \item Replace dynamic bit ranges in the left-hand-side of assignments with {\tt AST\_CASE} nodes with {\tt AST\_COND} children for each possible case. \item Detect array access patterns that are too complicated for the {\tt RTLIL::Memory} abstraction and replace them with a set of signals and cases for all reads and/or writes. \item Otherwise replace array accesses with {\tt AST\_MEMRD} and {\tt AST\_MEMWR} nodes. \end{itemize} In addition to these transformations, the simplifier also annotates the AST with additional information that is needed for the RTLIL generator, namely: \begin{itemize} \item All ranges (width of signals and bit selections) are not only const folded but (when a constant value is found) are also written to member variables in the {\tt AST\_RANGE} node. \item All identifiers are resolved and all {\tt AST\_IDENTIFIER} nodes are annotated with a pointer to the AST node that contains the declaration of the identifier. If no declaration has been found, an {\tt AST\_AUTOWIRE} node is created and used for the annotation. \end{itemize} This produces an AST that is fairly easy to convert to the RTLIL format. \subsection{Generating RTLIL} After AST simplification, the \lstinline[language=C++]{AST::AstNode::genRTLIL()} method of each {\tt AST\_MODULE} node in the AST is called. This initiates a recursive process that generates equivialent RTLIL data for the AST data. The \lstinline[language=C++]{AST::AstNode::genRTLIL()} method returns an \lstinline[language=C++]{RTLIL::SigSpec} structure. For nodes that represent expressions (operators, constants, signals, etc.), the cells needed to implement the calculation described by the expression are created and the resulting signal is returned. That way it is easy to generate the circuits for large expressions using depth-first recursion. For nodes that do not represent an expression (such as {\tt AST\_CELL}), the corresponding circuit is generated and an empty \lstinline[language=C++]{RTLIL::SigSpec} is returned. \section{Synthesizing Verilog always Blocks} For behavioural Verilog code (code utilizing \lstinline[language=Verilog]{always}- and \lstinline[language=Verilog]{initial}-blocks) it is necessary to also generate \lstinline[language=C++]{RTLIL::Process} objects. This is done in the following way: \begin{itemize} \item Whenever \lstinline[language=C++]{AST::AstNode::genRTLIL()} encounters an \lstinline[language=Verilog]{always}- or \lstinline[language=Verilog]{initial}-block, it creates an instance of \lstinline[language=Verilog]{AST_INTERNAL::ProcessGenerator}. This object then generates the \lstinline[language=C++]{RTLIL::Process} object for the block. It also calls \lstinline[language=C++]{AST::AstNode::genRTLIL()} for all right-hand-side expressions contained within the block. % \begin{sloppypar} \item First the \lstinline[language=Verilog]{AST_INTERNAL::ProcessGenerator} creates a list of all signals assigned within the block. It then creates a set of temporary signals using the naming scheme {\tt \$\it<number>\tt \textbackslash\it <original\_name>} for each of the assigned signals. \end{sloppypar} % \item Then an \lstinline[language=C++]{RTLIL::Process} is created that assigns all intermediate values for each left-hand-side signal to the temporary signal in its \lstinline[language=C++]{RTLIL::CaseRule}/\lstinline[language=C++]{RTLIL::SwitchRule} tree. % \item Finally a \lstinline[language=C++]{RTLIL::SyncRule} is created for the \lstinline[language=C++]{RTLIL::Process} that assigns the temporary signals for the final values to the actual signals. % \item Calls to \lstinline[language=C++]{AST::AstNode::genRTLIL()} are generated for right hand sides as needed. When blocking assignments are used, \lstinline[language=C++]{AST::AstNode::genRTLIL()} is configured using global variables to use the temporary signals that hold the correct intermediate values whenever one of the previously assigned signals is used in an expression. \end{itemize} Unfortunately the generation of a correct \lstinline[language=C++]{RTLIL::CaseRule}/\lstinline[language=C++]{RTLIL::SwitchRule} tree for behavioural code is a non-trivial task. The AST frontend solves the problem using the approach described on the following pages. The following example illustrates what the algorithm is supposed to do. Consider the following Verilog code: \begin{lstlisting}[numbers=left,frame=single,language=Verilog] always @(posedge clock) begin out1 = in1; if (in2) out1 = !out1; out2 <= out1; if (in3) out2 <= out2; if (in4) if (in5) out3 <= in6; else out3 <= in7; out1 = out1 ^ out2; end \end{lstlisting} This is translated by the Verilog and AST frontends into the following RTLIL code (attributes, cell parameters and wire declarations not included): \begin{lstlisting}[numbers=left,frame=single,language=rtlil] cell $logic_not $logic_not$<input>:4$2 connect \A \in1 connect \Y $logic_not$<input>:4$2_Y end cell $xor $xor$<input>:13$3 connect \A $1\out1[0:0] connect \B \out2 connect \Y $xor$<input>:13$3_Y end process $proc$<input>:1$1 assign $0\out3[0:0] \out3 assign $0\out2[0:0] $1\out1[0:0] assign $0\out1[0:0] $xor$<input>:13$3_Y switch \in2 case 1'1 assign $1\out1[0:0] $logic_not$<input>:4$2_Y case assign $1\out1[0:0] \in1 end switch \in3 case 1'1 assign $0\out2[0:0] \out2 case end switch \in4 case 1'1 switch \in5 case 1'1 assign $0\out3[0:0] \in6 case assign $0\out3[0:0] \in7 end case end sync posedge \clock update \out1 $0\out1[0:0] update \out2 $0\out2[0:0] update \out3 $0\out3[0:0] end \end{lstlisting} Note that the two operators are translated into separate cells outside the generated process. The signal \lstinline[language=Verilog]{out1} is assigned using blocking assignments and therefore \lstinline[language=Verilog]{out1} has been replaced with a different signal in all expressions after the initial assignment. The signal \lstinline[language=Verilog]{out2} is assigned using nonblocking assignments and therefore is not substituted on the right-hand-side expressions. The \lstinline[language=C++]{RTLIL::CaseRule}/\lstinline[language=C++]{RTLIL::SwitchRule} tree must be interpreted the following way: \begin{itemize} \item On each case level (the body of the process is the {\it root case}), first the actions on this level are evaluated and then the switches within the case are evaluated. (Note that the last assignment on line 13 of the Verilog code has been moved to the beginning of the RTLIL process to line 13 of the RTLIL listing.) I.e.~the special cases deeper in the switch hierarchy override the defaults on the upper levels. The assignments in lines 12 and 22 of the RTLIL code serve as an example for this. Note that in contrast to this, the order within the \lstinline[language=C++]{RTLIL::SwitchRule} objects within a \lstinline[language=C++]{RTLIL::CaseRule} is preserved with respect to the original AST and Verilog code. % \item \begin{sloppypar} The whole \lstinline[language=C++]{RTLIL::CaseRule}/\lstinline[language=C++]{RTLIL::SwitchRule} tree describes an asynchronous circuit. I.e.~the decision tree formed by the switches can be seen independently for each assigned signal. Whenever one assigned signal changes, all signals that depend on the changed signals are to be updated. For example the assignments in lines 16 and 18 in the RTLIL code in fact influence the assignment in line 12, even though they are in the ``wrong order''. \end{sloppypar} \end{itemize} The only synchronous part of the process is in the \lstinline[language=C++]{RTLIL::SyncRule} object generated at line 35 in the RTLIL code. The sync rule is the only part of the process where the original signals are assigned. The synchronization event from the original Verilog code has been translated into the synchronization type ({\tt posedge}) and signal ({\tt \textbackslash clock}) for the \lstinline[language=C++]{RTLIL::SyncRule} object. In the case of this simple example the \lstinline[language=C++]{RTLIL::SyncRule} object is later simply transformed into a set of d-type flip-flops and the \lstinline[language=C++]{RTLIL::CaseRule}/\lstinline[language=C++]{RTLIL::SwitchRule} tree to a decision tree using multiplexers. \begin{sloppypar} In more complex examples (e.g.~asynchronous resets) the part of the \lstinline[language=C++]{RTLIL::CaseRule}/\lstinline[language=C++]{RTLIL::SwitchRule} tree that describes the asynchronous reset must first be transformed to the correct \lstinline[language=C++]{RTLIL::SyncRule} objects. This is done by the {\tt proc\_adff} pass. \end{sloppypar} \subsection{The ProcessGenerator Algorithm} The \lstinline[language=C++]{AST_INTERNAL::ProcessGenerator} uses the following internal state variables: \begin{itemize} \item \begin{sloppypar} \lstinline[language=C++]{subst_rvalue_from} and \lstinline[language=C++]{subst_rvalue_to} \\ These two variables hold the replacement pattern that should be used by \lstinline[language=C++]{AST::AstNode::genRTLIL()} for signals with blocking assignments. After initialization of \lstinline[language=C++]{AST_INTERNAL::ProcessGenerator} these two variables are empty. \end{sloppypar} % \item \lstinline[language=C++]{subst_lvalue_from} and \lstinline[language=C++]{subst_lvalue_to} \\ These two variables contain the mapping from left-hand-side signals ({\tt \textbackslash \it <name>}) to the current temporary signal for the same thing (initially {\tt \$0\textbackslash \it <name>}). % \item \lstinline[language=C++]{current_case} \\ A pointer to a \lstinline[language=C++]{RTLIL::CaseRule} object. Initially this is the root case of the generated \lstinline[language=C++]{RTLIL::Process}. \end{itemize} As the algorithm runs these variables are continously modified as well as pushed to the stack and later restored to their earlier values by popping from the stack. On startup the ProcessGenerator generates a new \lstinline[language=C++]{RTLIL::Process} object with an empty root case and initializes its state variables as described above. Then the \lstinline[language=C++]{RTLIL::SyncRule} objects are created using the synchronization events from the {\tt AST\_ALWAYS} node and the initial values of \lstinline[language=C++]{subst_lvalue_from} and \lstinline[language=C++]{subst_lvalue_to}. Then the AST for this process is evaluated recursively. During this recursive evaluation, three different relevant types of AST nodes can be discovered: {\tt AST\_ASSIGN\_LE} (nonblocking assignments), {\tt AST\_ASSIGN\_EQ} (blocking assignments) and {\tt AST\_CASE} (\lstinline[language=Verilog]{if} or \lstinline[language=Verilog]{case} statement). \subsubsection{Handling of Nonblocking Assignments} When an {\tt AST\_ASSIGN\_LE} node is discovered, the following actions are performed by the ProcessGenerator: \begin{itemize} \item The left-hand-side is evaluated using \lstinline[language=C++]{AST::AstNode::genRTLIL()} and mapped to a temporary signal name using \lstinline[language=C++]{subst_lvalue_from} and \lstinline[language=C++]{subst_lvalue_to}. % \item The right-hand-side is evaluated using \lstinline[language=C++]{AST::AstNode::genRTLIL()}. For this call, the values of \lstinline[language=C++]{subst_rvalue_from} and \lstinline[language=C++]{subst_rvalue_to} are used to map blocking-assigned signals correctly. % \item Remove all assignments to the same left-hand-side as this assignment from the \lstinline[language=C++]{current_case} and all cases within it. % \item Add the new assignment to the \lstinline[language=C++]{current_case}. \end{itemize} \subsubsection{Handling of Blocking Assignments} When an {\tt AST\_ASSIGN\_EQ} node is discovered, the following actions are performed by the ProcessGenerator: \begin{itemize} \item Perform all the steps that would be performed for a nonblocking assignment (see above). % \item Remove the found left-hand-side (before lvalue mapping) from \lstinline[language=C++]{subst_rvalue_from} and also remove the respective bits from \lstinline[language=C++]{subst_rvalue_to}. % \item Append the found left-hand-side (before lvalue mapping) to \lstinline[language=C++]{subst_rvalue_from} and append the found right-hand-side to \lstinline[language=C++]{subst_rvalue_to}. \end{itemize} \subsubsection{Handling of Cases and if-Statements} \begin{sloppypar} When an {\tt AST\_CASE} node is discovered, the following actions are performed by the ProcessGenerator: \begin{itemize} \item The values of \lstinline[language=C++]{subst_rvalue_from}, \lstinline[language=C++]{subst_rvalue_to}, \lstinline[language=C++]{subst_lvalue_from} and \lstinline[language=C++]{subst_lvalue_to} are pushed to the stack. % \item A new \lstinline[language=C++]{RTLIL::SwitchRule} object is generated, the selection expression is evaluated using \lstinline[language=C++]{AST::AstNode::genRTLIL()} (with the use of \lstinline[language=C++]{subst_rvalue_from} and \lstinline[language=C++]{subst_rvalue_to}) and added to the \lstinline[language=C++]{RTLIL::SwitchRule} object and the obect is added to the \lstinline[language=C++]{current_case}. % \item All lvalues assigned to within the {\tt AST\_CASE} node using blocking assignments are collected and saved in the local variable \lstinline[language=C++]{this_case_eq_lvalue}. % \item New temporary signals are generated for all signals in \lstinline[language=C++]{this_case_eq_lvalue} and stored in \lstinline[language=C++]{this_case_eq_ltemp}. % \item The signals in \lstinline[language=C++]{this_case_eq_lvalue} are mapped using \lstinline[language=C++]{subst_rvalue_from} and \lstinline[language=C++]{subst_rvalue_to} and the resulting set of signals is stored in \lstinline[language=C++]{this_case_eq_rvalue}. \end{itemize} Then the following steps are performed for each {\tt AST\_COND} node within the {\tt AST\_CASE} node: \begin{itemize} \item Set \lstinline[language=C++]{subst_rvalue_from}, \lstinline[language=C++]{subst_rvalue_to}, \lstinline[language=C++]{subst_lvalue_from} and \lstinline[language=C++]{subst_lvalue_to} to the values that have been pushed to the stack. % \item Remove \lstinline[language=C++]{this_case_eq_lvalue} from \lstinline[language=C++]{subst_lvalue_from}/\lstinline[language=C++]{subst_lvalue_to}. % \item Append \lstinline[language=C++]{this_case_eq_lvalue} to \lstinline[language=C++]{subst_lvalue_from} and append \lstinline[language=C++]{this_case_eq_ltemp} to \lstinline[language=C++]{subst_lvalue_to}. % \item Push the value of \lstinline[language=C++]{current_case}. % \item Create a new \lstinline[language=C++]{RTLIL::CaseRule}. Set \lstinline[language=C++]{current_case} to the new object and add the new object to the \lstinline[language=C++]{RTLIL::SwitchRule} created above. % \item Add an assignment from \lstinline[language=C++]{this_case_eq_rvalue} to \lstinline[language=C++]{this_case_eq_ltemp} to the new \lstinline[language=C++]{current_case}. % \item Evaluate the compare value for this case using \lstinline[language=C++]{AST::AstNode::genRTLIL()} (with the use of \lstinline[language=C++]{subst_rvalue_from} and \lstinline[language=C++]{subst_rvalue_to}) modify the new \lstinline[language=C++]{current_case} accordingly. % \item Recursion into the children of the {\tt AST\_COND} node. % \item Restore \lstinline[language=C++]{current_case} by popping the old value from the stack. \end{itemize} Finally the following steps are performed: \begin{itemize} \item The values of \lstinline[language=C++]{subst_rvalue_from}, \lstinline[language=C++]{subst_rvalue_to}, \lstinline[language=C++]{subst_lvalue_from} and \lstinline[language=C++]{subst_lvalue_to} are popped from the stack. % \item The signals from \lstinline[language=C++]{this_case_eq_lvalue} are removed from the \lstinline[language=C++]{subst_rvalue_from}/\lstinline[language=C++]{subst_rvalue_to}-pair. % \item The value of \lstinline[language=C++]{this_case_eq_lvalue} is appended to \lstinline[language=C++]{subst_rvalue_from} and the value of \lstinline[language=C++]{this_case_eq_ltemp} is appended to \lstinline[language=C++]{subst_rvalue_to}. % \item Map the signals in \lstinline[language=C++]{this_case_eq_lvalue} using \lstinline[language=C++]{subst_lvalue_from}/\lstinline[language=C++]{subst_lvalue_to}. % \item Remove all assignments to signals in \lstinline[language=C++]{this_case_eq_lvalue} in \lstinline[language=C++]{current_case} and all cases within it. % \item Add an assignment from \lstinline[language=C++]{this_case_eq_ltemp} to \lstinline[language=C++]{this_case_eq_lvalue} to \lstinline[language=C++]{current_case}. \end{itemize} \end{sloppypar} \subsubsection{Further Analysis of the Algorithm for Cases and if-Statements} With respect to nonblocking assignments the algorithm is easy: later assignments invalidate earlier assignments. For each signal assigned using nonblocking assignments exactly one temporary variable is generated (with the {\tt \$0}-prefix) and this variable is used for all assignments of the variable. Note how all the \lstinline[language=C++]{_eq_}-variables become empty when no blocking assignments are used and many of the steps in the algorithm can then be ignored as a result of this. For a variable with blocking assignments the algorithm shows the following behaviour: First a new temporary variable is created. This new temporary variable is then registered as the assignment target for all assignments for this variable within the cases for this {\tt AST\_CASE} node. Then for each case the new temporary variable is first assigned the old temporary variable. This assignment is overwritten if the variable is actually assigned in this case and is kept as a default value otherwise. This yields an \lstinline[language=C++]{RTLIL::CaseRule} that assigns the new temporary variable in all branches. So when all cases have been processed a final assignment is added to the containing block that assigns the new temporary variable to the old one. Note how this step always overrides a previous assignment to the old temporary variable. Other than nonblocking assignments, the old assignment could still have an effect somewhere in the design, as there have been calls to \lstinline[language=C++]{AST::AstNode::genRTLIL()} with a \lstinline[language=C++]{subst_rvalue_from}/\lstinline[language=C++]{subst_rvalue_to}-tuple that contained the right-hand-side of the old assignment. \subsection{The proc pass} The ProcessGenerator converts a behavioural model in AST representation to a behavioural model in \lstinline[language=C++]{RTLIL::Process} representation. The actual conversion from a behavioural model to an RTL representation is performed by the {\tt proc} pass and the passes it launches: \begin{itemize} \item {\tt proc\_clean} and {\tt proc\_rmdead} \\ These two passes just clean up the \lstinline[language=C++]{RTLIL::Process} structure. The {\tt proc\_clean} pass removes empty parts (eg. empty assignments) from the process and {\tt proc\_rmdead} detects and removes unreachable branches from the process's decision trees. % \item {\tt proc\_arst} \\ This pass detects processes that describe d-type flip-flops with asynchronous resets and rewrites the process to better reflect what they are modelling: Before this pass, an asynchronous reset has two edge-sensitive sync rules and one top-level \C{RTLIL::SwitchRule} for the reset path. After this pass the sync rule for the reset is level-sensitive and the top-level \C{RTLIL::SwitchRule} has been removed. % \item {\tt proc\_mux} \\ This pass converts the \C{RTLIL::CaseRule}/\C{RTLIL::SwitchRule}-tree to a tree of multiplexers per written signal. After this, the \C{RTLIL::Process} structure only contains the \C{RTLIL::SyncRule}s that describe the output registers. % \item {\tt proc\_dff} \\ This pass replaces the \C{RTLIL::SyncRule}s to d-type flip-flops (with asynchronous resets if neccessary). % \item {\tt proc\_clean} \\ A final call to {\tt proc\_clean} removes the now empty \C{RTLIL::Process} objects. \end{itemize} Performing these last processing steps in passes instead of in the Verilog frontend has two important benefits: First it improves the transparency of the process. Everything that happens in a seperate pass is easier to debug, as the RTLIL data structures can be easily investigated before and after each of the steps. Second it improves flexibility. This scheme can easily be extended to support other types of storage-elements, such as sr-latches or d-latches, without having to extend the actual Verilog frontend. \section{Synthesizing Verilog Arrays} \begin{fixme} Add some information on the generation of {\tt \$memrd} and {\tt \$memwr} cells and how they are processsed in the {\tt memory} pass. \end{fixme} \section{Synthesizing Parametric Designs} \begin{fixme} Add some information on the \lstinline[language=C++]{RTLIL::Module::derive()} method and how it is used to synthesize parametric modules via the {\tt hierarchy} pass. \end{fixme}
generated by cgit v1.2.3 (git 2.25.1) at 2025-10-02 00:08:27 +0000