| Commit message (Collapse) | Author | Age | Files | Lines |
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intel-microcode (3.20200616.1)
* New upstream microcode datafile 20200616
+ Downgraded microcodes (to a previously shipped revision):
sig 0x000406e3, pf_mask 0xc0, 2019-10-03, rev 0x00d6, size 101376
sig 0x000506e3, pf_mask 0x36, 2019-10-03, rev 0x00d6, size 101376
* Works around hangs on boot on Skylake-U/Y and Skylake Xeon E3,
* This update *removes* the SRBDS mitigations from the above processors
* Note that Debian had already downgraded 0x406e3 in release 3.20200609.2
intel-microcode (3.20200609.2)
* REGRESSION FIX: 0x406e3: rollback to rev 0xd6 and document regression
* Microcode rollbacks (closes: LP#1883002)
sig 0x000406e3, pf_mask 0xc0, 2019-10-03, rev 0x00d6, size 101376
* THIS REMOVES THE SECURITY FIXES FOR SKYLAKE-U/Y PROCESSORS
* Avoid hangs on boot on (some?) Skylake-U/Y processors,
* ucode-blacklist: blacklist models 0x8e and 0x9e from late-loading,
just in case. Note that Debian does not do late loading by itself.
Refer to LP#1883002 for the report, 0x806ec hangs upon late load.
intel-microcode (3.20200609.1)
* SECURITY UPDATE
* For most processors: SRBDS and/or VRDS, L1DCES mitigations depending
on the processor model
* For Skylake HEDT and Skylake Xeons with signature 0x50654: VRDS and
L1DCES mitigations, plus mitigations described in the changelog entry
for package release 3.20191112.1.
* Expect some performance impact, the mitigations are enabled by
default. A Linux kernel update will be issued that allows one to
selectively disable the mitigations.
* New upstream microcode datafile 20200609
* Implements mitigation for CVE-2020-0543 Special Register Buffer Data
Sampling (SRBDS), INTEL-SA-00320, CROSSTalk
* Implements mitigation for CVE-2020-0548 Vector Register Data Sampling
(VRDS), INTEL-SA-00329
* Implements mitigation for CVE-2020-0549 L1D Cache Eviction Sampling
(L1DCES), INTEL-SA-00329
* Known to fix the regression introduced in release 2019-11-12 (sig
0x50564, rev. 0x2000065), which would cause several systems with
Skylake Xeon, Skylake HEDT processors to hang while rebooting
* Updated Microcodes:
sig 0x000306c3, pf_mask 0x32, 2019-11-12, rev 0x0028, size 23552
sig 0x000306d4, pf_mask 0xc0, 2019-11-12, rev 0x002f, size 19456
sig 0x00040651, pf_mask 0x72, 2019-11-12, rev 0x0026, size 22528
sig 0x00040661, pf_mask 0x32, 2019-11-12, rev 0x001c, size 25600
sig 0x00040671, pf_mask 0x22, 2019-11-12, rev 0x0022, size 14336
sig 0x000406e3, pf_mask 0xc0, 2020-04-27, rev 0x00dc, size 104448
sig 0x00050653, pf_mask 0x97, 2020-04-24, rev 0x1000157, size 32768
sig 0x00050654, pf_mask 0xb7, 2020-04-24, rev 0x2006906, size 34816
sig 0x00050656, pf_mask 0xbf, 2020-04-23, rev 0x4002f01, size 52224
sig 0x00050657, pf_mask 0xbf, 2020-04-23, rev 0x5002f01, size 52224
sig 0x000506e3, pf_mask 0x36, 2020-04-27, rev 0x00dc, size 104448
sig 0x000806e9, pf_mask 0x10, 2020-04-27, rev 0x00d6, size 103424
sig 0x000806e9, pf_mask 0xc0, 2020-04-27, rev 0x00d6, size 103424
sig 0x000806ea, pf_mask 0xc0, 2020-04-27, rev 0x00d6, size 103424
sig 0x000806eb, pf_mask 0xd0, 2020-04-27, rev 0x00d6, size 103424
sig 0x000806ec, pf_mask 0x94, 2020-04-23, rev 0x00d6, size 103424
sig 0x000906e9, pf_mask 0x2a, 2020-04-23, rev 0x00d6, size 103424
sig 0x000906ea, pf_mask 0x22, 2020-04-27, rev 0x00d6, size 102400
sig 0x000906eb, pf_mask 0x02, 2020-04-23, rev 0x00d6, size 103424
sig 0x000906ec, pf_mask 0x22, 2020-04-27, rev 0x00d6, size 102400
sig 0x000906ed, pf_mask 0x22, 2020-04-23, rev 0x00d6, size 103424
* Restores the microcode-level fixes that were reverted by release
3.20191115.2 for sig 0x50654 (Skylake Xeon, Skylake HEDT)
intel-microcode (3.20200520.1)
* New upstream microcode datafile 20200520
+ Updated Microcodes:
sig 0x000206d6, pf_mask 0x6d, 2020-03-04, rev 0x0621, size 18432
sig 0x000206d7, pf_mask 0x6d, 2020-03-24, rev 0x071a, size 19456
intel-microcode (3.20200508.1)
* New upstream microcode datafile 20200508
+ Updated Microcodes:
sig 0x000706e5, pf_mask 0x80, 2020-03-12, rev 0x0078, size 107520
* Likely fixes several critical errata on IceLake-U/Y causing system
hangs
intel-microcode (3.20191115.2)
* Microcode rollbacks (closes: #946515, LP#1854764):
sig 0x00050654, pf_mask 0xb7, 2019-07-31, rev 0x2000064, size 33792
* Avoids hangs on warm reboots (cold boots work fine) on HEDT and
Xeon processors with signature 0x50654.
intel-microcode (3.20191115.1)
* New upstream microcode datafile 20191115
+ Updated Microcodes:
sig 0x000406e3, pf_mask 0xc0, 2019-10-03, rev 0x00d6, size 101376
sig 0x000506e3, pf_mask 0x36, 2019-10-03, rev 0x00d6, size 101376
sig 0x000806e9, pf_mask 0x10, 2019-10-15, rev 0x00ca, size 100352
sig 0x000806e9, pf_mask 0xc0, 2019-09-26, rev 0x00ca, size 100352
sig 0x000806ea, pf_mask 0xc0, 2019-10-03, rev 0x00ca, size 100352
sig 0x000806eb, pf_mask 0xd0, 2019-10-03, rev 0x00ca, size 100352
sig 0x000806ec, pf_mask 0x94, 2019-10-03, rev 0x00ca, size 100352
sig 0x000906e9, pf_mask 0x2a, 2019-10-03, rev 0x00ca, size 100352
sig 0x000906ea, pf_mask 0x22, 2019-10-03, rev 0x00ca, size 99328
sig 0x000906eb, pf_mask 0x02, 2019-10-03, rev 0x00ca, size 100352
sig 0x000906ec, pf_mask 0x22, 2019-10-03, rev 0x00ca, size 99328
sig 0x000906ed, pf_mask 0x22, 2019-10-03, rev 0x00ca, size 100352
sig 0x000a0660, pf_mask 0x80, 2019-10-03, rev 0x00ca, size 91136
intel-microcode (3.20191113.1)
* New upstream microcode datafile 20191113
+ SECURITY UPDATE, refer to the 3.20191112.1 changelog entry for details
Adds microcode update for CFL-S (Coffe Lake Desktop)
INTEL-SA-00270, CVE-2019-11135, CVE-2019-0117
+ Updated Microcodes (previously removed):
sig 0x000906ec, pf_mask 0x22, 2019-08-14, rev 0x00c6, size 99328
intel-microcode (3.20191112.1)
* New upstream microcode datafile 20191112
+ SECURITY UPDATE
- Implements MDS mitigation (TSX TAA), INTEL-SA-00270, CVE-2019-11135
- Implements TA Indirect Sharing mitigation, and improves the
MDS mitigation (VERW)
- Fixes FIVR (Xeon Voltage Modulation) vulnerability, INTEL-SA-00271,
CVE-2019-11139
- Fixes SGX vulnerabilities and errata (including CVE-2019-0117)
+ CRITICAL ERRATA FIXES
- Fixes Jcc conditional jump macro-fusion erratum (Skylake+, except
Ice Lake), causes a 0-3% typical perforance hit (can be as bad
as 10%). But ensures the processor will actually jump where it
should, so don't even *dream* of not applying this fix.
- Fixes AVX SHUF* instruction implementation flaw erratum
+ Removed Microcodes:
sig 0x000906ec, pf_mask 0x22, 2019-02-14, rev 0x00ae, size 98304
+ New Microcodes:
sig 0x000406d8, pf_mask 0x01, 2019-09-16, rev 0x012d, size 84992
sig 0x00050656, pf_mask 0xbf, 2019-09-05, rev 0x400002c, size 51200
sig 0x00060663, pf_mask 0x80, 2018-04-17, rev 0x002a, size 87040
sig 0x000706a8, pf_mask 0x01, 2019-08-29, rev 0x0016, size 74752
sig 0x000706e5, pf_mask 0x80, 2019-09-05, rev 0x0046, size 102400
sig 0x000a0660, pf_mask 0x80, 2019-08-27, rev 0x00c6, size 91136
+ Updated Microcodes:
sig 0x000406e3, pf_mask 0xc0, 2019-08-14, rev 0x00d4, size 101376
sig 0x00050654, pf_mask 0xb7, 2019-09-05, rev 0x2000065, size 34816
sig 0x00050657, pf_mask 0xbf, 2019-09-05, rev 0x500002c, size 51200
sig 0x000506e3, pf_mask 0x36, 2019-08-14, rev 0x00d4, size 101376
sig 0x000706a1, pf_mask 0x01, 2019-08-28, rev 0x0032, size 73728
sig 0x000806e9, pf_mask 0x10, 2019-08-14, rev 0x00c6, size 99328
sig 0x000806e9, pf_mask 0xc0, 2019-08-14, rev 0x00c6, size 100352
sig 0x000806ea, pf_mask 0xc0, 2019-08-14, rev 0x00c6, size 99328
sig 0x000806eb, pf_mask 0xd0, 2019-08-14, rev 0x00c6, size 100352
sig 0x000806ec, pf_mask 0x94, 2019-08-14, rev 0x00c6, size 100352
sig 0x000906e9, pf_mask 0x2a, 2019-08-14, rev 0x00c6, size 100352
sig 0x000906ea, pf_mask 0x22, 2019-08-14, rev 0x00c6, size 99328
sig 0x000906eb, pf_mask 0x02, 2019-08-14, rev 0x00c6, size 100352
sig 0x000906ed, pf_mask 0x22, 2019-08-14, rev 0x00c6, size 99328
+ Updated Microcodes (previously removed):
sig 0x00050653, pf_mask 0x97, 2019-09-09, rev 0x1000151, size 32768
Signed-off-by: Tan Zien <nabsdh9@gmail.com>
(cherry picked from commit e826e007658911df91385935e74621889abbda24)
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* New upstream microcode datafile 20190918
*Might* contain mitigations for INTEL-SA-00247 (RAMBleed), given
the set of processors being updated.
* Updated Microcodes:
sig 0x000306d4, pf_mask 0xc0, 2019-06-13, rev 0x002e, size 19456
sig 0x000306f4, pf_mask 0x80, 2019-06-17, rev 0x0016, size 18432
sig 0x00040671, pf_mask 0x22, 2019-06-13, rev 0x0021, size 14336
sig 0x000406f1, pf_mask 0xef, 2019-06-18, rev 0xb000038, size 30720
sig 0x00050654, pf_mask 0xb7, 2019-07-31, rev 0x2000064, size 33792
sig 0x00050657, pf_mask 0xbf, 2019-08-12, rev 0x500002b, size 51200
sig 0x00050662, pf_mask 0x10, 2019-06-17, rev 0x001c, size 32768
sig 0x00050663, pf_mask 0x10, 2019-06-17, rev 0x7000019, size 24576
sig 0x00050664, pf_mask 0x10, 2019-06-17, rev 0xf000017, size 24576
sig 0x00050665, pf_mask 0x10, 2019-06-17, rev 0xe00000f, size 19456
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
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* Implements MDS mitigation (RIDL, Fallout, Zombieload), INTEL-SA-00223
CVE-2018-12126, CVE-2018-12127, CVE-2018-12130, CVE-2019-11091
* Updated Microcodes:
sig 0x000206d6, pf_mask 0x6d, 2019-05-21, rev 0x061f, size 18432
sig 0x000206d7, pf_mask 0x6d, 2019-05-21, rev 0x0718, size 19456
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
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* New Microcodes:
sig 0x00030678, pf_mask 0x02, 2019-04-22, rev 0x0838, size 52224
sig 0x00030678, pf_mask 0x0c, 2019-04-22, rev 0x0838, size 52224
sig 0x00030679, pf_mask 0x0f, 2019-04-23, rev 0x090c, size 52224
sig 0x000406c3, pf_mask 0x01, 2019-04-23, rev 0x0368, size 69632
sig 0x000406c4, pf_mask 0x01, 2019-04-23, rev 0x0411, size 68608
sig 0x00050657, pf_mask 0xbf, 2019-02-27, rev 0x5000021, size 47104
sig 0x000806e9, pf_mask 0x10, 2018-10-18, rev 0x009e, size 98304
sig 0x000806eb, pf_mask 0xd0, 2018-10-25, rev 0x00a4, size 99328
sig 0x000806ec, pf_mask 0x94, 2019-02-12, rev 0x00b2, size 98304
sig 0x000906ec, pf_mask 0x22, 2018-09-29, rev 0x00a2, size 98304
sig 0x000906ed, pf_mask 0x22, 2019-02-04, rev 0x00b0, size 97280
* Updated Microcodes:
sig 0x000206a7, pf_mask 0x12, 2019-02-17, rev 0x002f, size 12288
sig 0x000306a9, pf_mask 0x12, 2019-02-13, rev 0x0021, size 14336
sig 0x000306c3, pf_mask 0x32, 2019-02-26, rev 0x0027, size 23552
sig 0x000306d4, pf_mask 0xc0, 2019-03-07, rev 0x002d, size 19456
sig 0x000306e4, pf_mask 0xed, 2019-03-14, rev 0x042e, size 16384
sig 0x000306e7, pf_mask 0xed, 2019-03-14, rev 0x0715, size 17408
sig 0x000306f2, pf_mask 0x6f, 2019-03-01, rev 0x0043, size 34816
sig 0x000306f4, pf_mask 0x80, 2019-03-01, rev 0x0014, size 18432
sig 0x00040651, pf_mask 0x72, 2019-02-26, rev 0x0025, size 21504
sig 0x00040661, pf_mask 0x32, 2019-02-26, rev 0x001b, size 25600
sig 0x00040671, pf_mask 0x22, 2019-03-07, rev 0x0020, size 14336
sig 0x000406e3, pf_mask 0xc0, 2019-04-01, rev 0x00cc, size 100352
sig 0x000406f1, pf_mask 0xef, 2019-03-02, rev 0xb000036, size 30720
sig 0x00050654, pf_mask 0xb7, 2019-04-02, rev 0x200005e, size 32768
sig 0x00050662, pf_mask 0x10, 2019-03-23, rev 0x001a, size 32768
sig 0x00050663, pf_mask 0x10, 2019-03-23, rev 0x7000017, size 24576
sig 0x00050664, pf_mask 0x10, 2019-03-23, rev 0xf000015, size 23552
sig 0x00050665, pf_mask 0x10, 2019-03-23, rev 0xe00000d, size 19456
sig 0x000506c9, pf_mask 0x03, 2019-01-15, rev 0x0038, size 17408
sig 0x000506ca, pf_mask 0x03, 2019-03-01, rev 0x0016, size 15360
sig 0x000506e3, pf_mask 0x36, 2019-04-01, rev 0x00cc, size 100352
sig 0x000506f1, pf_mask 0x01, 2019-03-21, rev 0x002e, size 11264
sig 0x000706a1, pf_mask 0x01, 2019-01-02, rev 0x002e, size 73728
sig 0x000806e9, pf_mask 0x10, 2019-04-01, rev 0x00b4, size 98304
sig 0x000806e9, pf_mask 0xc0, 2019-04-01, rev 0x00b4, size 99328
sig 0x000806ea, pf_mask 0xc0, 2019-04-01, rev 0x00b4, size 99328
sig 0x000806eb, pf_mask 0xd0, 2019-03-30, rev 0x00b8, size 98304
sig 0x000806ec, pf_mask 0x94, 2019-03-30, rev 0x00b8, size 97280
sig 0x000906e9, pf_mask 0x2a, 2019-04-01, rev 0x00b4, size 99328
sig 0x000906ea, pf_mask 0x22, 2019-04-01, rev 0x00b4, size 98304
sig 0x000906eb, pf_mask 0x02, 2019-04-01, rev 0x00b4, size 99328
sig 0x000906ec, pf_mask 0x22, 2019-02-14, rev 0x00ae, size 98304
sig 0x000906ed, pf_mask 0x22, 2019-03-17, rev 0x00b8, size 97280
* Implements MDS mitigation (RIDL, Fallout, Zombieload), INTEL-SA-00223
CVE-2018-12126, CVE-2018-12127, CVE-2018-12130, CVE-2019-11091
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
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This reverts commit 022ffb56b2491fd7d8051ac6e6c7622ecc313d8f.
Signed-off-by: John Crispin <john@phrozen.org>
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Create initrd image with packed microcode. This'll allow to load it at
early boot stage.
Signed-off-by: Tomasz Maciej Nowak <tomek_n@o2.pl>
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It is not necessary to have iucode-tool present on target system to have
functional intel-microcode package. The build time dependency is kept.
Signed-off-by: Tomasz Maciej Nowak <tomek_n@o2.pl>
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Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
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* New upstream microcode data file 20180703
+ Updated Microcodes:
sig 0x000206d6, pf_mask 0x6d, 2018-05-08, rev 0x061d, size 18432
sig 0x000206d7, pf_mask 0x6d, 2018-05-08, rev 0x0714, size 19456
sig 0x000306e4, pf_mask 0xed, 2018-04-25, rev 0x042d, size 15360
sig 0x000306e7, pf_mask 0xed, 2018-04-25, rev 0x0714, size 17408
sig 0x000306f2, pf_mask 0x6f, 2018-04-20, rev 0x003d, size 33792
sig 0x000306f4, pf_mask 0x80, 2018-04-20, rev 0x0012, size 17408
sig 0x000406f1, pf_mask 0xef, 2018-04-19, rev 0xb00002e, size 28672
sig 0x00050654, pf_mask 0xb7, 2018-05-15, rev 0x200004d, size 31744
sig 0x00050665, pf_mask 0x10, 2018-04-20, rev 0xe00000a, size 18432
sig 0x000706a1, pf_mask 0x01, 2017-12-26, rev 0x0022, size 73728
+ First batch of fixes for: Intel SA-00115, CVE-2018-3639, CVE-2018-3640
+ Implements IBRS/IBPB/STIPB support, Spectre-v2 mitigation
+ SSBD support (Spectre-v4 mitigation) and fix Spectre-v3a for:
Sandybridge server, Ivy Bridge server, Haswell server, Skylake server,
Broadwell server, a few HEDT Core i7/i9 models that are actually gimped
server dies.
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
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- Update microcode for 24 CPU types
- Implements IBRS/IBPB/STIPB support, Spectre-v2 mitigation for:
Sandybridge, Ivy Bridge, Haswell, Broadwell, Skylake, Kaby Lake,
Coffee Lake
- Missing production updates:
- Broadwell-E/EX Xeons (sig 0x406f1)
- Anniedale/Morefield, Apollo Lake, Avoton, Cherry Trail, Braswell,
Gemini Lake, Denverton
- New Microcodes:
- sig 0x00050653, pf_mask 0x97, 2018-01-29, rev 0x1000140
- sig 0x00050665, pf_mask 0x10, 2018-01-22, rev 0xe000009
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
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Compiling the Intel microcode package results in a
microcode.bin and a microcode-64.bin. As we can
decide based on the subtarget which should be used,
we'll only split the required .bin file with
iucode-tool.
x64 will get the intel-microcode-64.bin
All other variants will get intel-microcode.bin
The microcodes will be updated from preinit via a common
script - that's the earliest place where we can do it.
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
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