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* ath79: enable UART in SoC DTSI filesAdrian Schmutzler2021-02-241-2/+0
| | | | | | | | | | | | | | | The uart node is enabled on all devices except one (GL-USB150 *). Thus, let's not have a few hundred nodes to enable it, but do not disable it in the first place. Where the majority of devices is using it, also move the serial0 alias to the DTSI. *) Since GL-USB150 even defines serial0 alias, the missing uart is probably just a mistake. Anyway, disable it for now so this patch stays cosmetic. Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
* ath79: specify device-type for PCI controllersDavid Bauer2021-02-201-0/+2
| | | | | | | | Specify the device_type property for PCI as well as PCIe controllers. Otherwise, the PCI range parser will not be selected when using kernel 5.10. Signed-off-by: David Bauer <mail@david-bauer.net>
* ath79: move ath79-clk.h include to ath79.dtsiAdrian Schmutzler2020-09-251-1/+1
| | | | | | | | | | ath79.dtsi uses ATH79_CLK_MDIO, so the include <dt-bindings/clock/ath79-clk.h> needs to be moved there. Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
* ath79: drop and consolidate redundant chosen/bootargsAdrian Schmutzler2020-06-251-0/+4
| | | | | | | | | | | | | | In ath79, for several SoCs the console bootargs are defined to the very same value in every device's DTS. Consolidate these definitions in the SoC dtsi files and drop further redundant definitions elsewhere. The only device without any bootargs set has been OpenMesh OM5P-AC V2. This will now inherit the setting from qca955x.dtsi Note that while this tidies up master a lot, it might develop into a frequent pitfall for backports. Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
* ath79: fix dtc compiler warningsMathias Kresin2018-12-121-1/+1
| | | | | | | | | | | | The qca9557/qca956x reset-controller aren't a simple bus. A simple bus would require node unit addresses. Add the node unit addresses for the qca9557 usb phys. Add the regs for the USB_PWRCTL and USB_CONFIG registers even not yet used. Fix the wrong ar7100 pcie controller node unit address as well. Signed-off-by: Mathias Kresin <dev@kresin.me>
* ath79: add syscon compatible property to ar7100 ethernet nodesMatt Merhar2018-09-061-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | This adds "syscon" to the compatible properties for the eth0/eth1 nodes in ar7100.dtsi. Without this, a kernel panic is encountered on boot with some ar7100 boards. This for some reason wasn't an issue for the WNDR3800, which uses a Realtek switch chipset, but the panic was encountered on the RouterStation Pro (using an AR8216 switch) and some other boards that haven't yet been merged. The panic message mentions an unaligned access and happens in ag71xx_mdio_probe in drivers/net/ethernet/atheros/ag71xx/ag71xx_mdio.c. Even if the unaligned access is fixed, the ag71xx_mdio probe still fails without the "syscon" property. This was already being worked around in ar7161_ubnt_routerstation-pro.dts by overriding the compatible property, so this commit removes that as well. All of the other ath79 .dtsi already have this property, so no changes are needed elsewhere. Signed-off-by: Matt Merhar <mattmerhar@protonmail.com>
* ath79: fix ar7100 PCI IRQ handlingDmitry Tunin2018-08-281-5/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently all PCI devices get the same IRQ that affects performance badly. This commit adresses this problem and cleans the code. ar7100 has a special PCI interrupt controller@18060018 that works exactly the same way as misc interrupt controller. This patch does the following: 1. Defines pci-intc interrupt controller@18060018 in dtsi. 2. Removes interrupt-controller property from PCI node. 3. Sets a correct interrupt mask for PCI devices. 4. Removes all IRQ handling code from the PCI driver. "qca,ar7100-misc-intc" should be used as the compatible property, becuase on ar7100 the controlled status register is read-only and the ack method used in "qca,ar7240-misc-intc" won't work properly. There are two very minor downsides of this patch that don't affect perormance: 1. We allocate an IRQ domain of 32 IRQ, whan we need only 5. But ar7100 aren't tiny un terms of RAM and that is not very important and can be tuned if we implement "nr-interrupts" property". 2. It reuses the same irg chip name "MISC" for both controllers. Run tested on DIR-825 B1. Signed-off-by: Dmitry Tunin <hanipouspilot@gmail.com>
* ath79: ag71xx: apply interface mode to MII0/1_CTRL on ar71xx/ar913xChuanhong Guo2018-08-281-0/+2
| | | | | | | | | | | | | We currently don't have any code configuring interface mode in ath79, meaning that we relies on bootloader to set the correct interface mode. This patch added code to set interface correctly so that everything works even if bootloader configures it wrong.(e.g. on WNDR3800 u-boot set the second GMAC mode to RMII but it should be RGMII.) Introduced "qca,mac-idx" for the difference in MII_CTRL register value. Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
* ath79: ag71xx: remove PHY resetChuanhong Guo2018-08-091-4/+4
| | | | | | | | | | | | Bit 8/12 of reset controller which is marked as PHY_RESET/SWITCH_RESET in datasheets will trigger either a reset for builtin switch or assert an external ETH0_RESET_L/ETH1_RESET_L pin, which are usually connected to external PHY/switch. None of them should be triggered every time an interface is brought up in ethernet driver. Remove PHY reset support from ag71xx and definition for them in dtsi. Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
* ath79: relicense DTS files to the GPL 2.0+ / MITRafał Miłecki2018-05-071-1/+1
| | | | | | | | | | | | | | Some maintainers prefer DTS files licensed under permissive license like MIT / BSD. As all DT bindings should be OS independent and DTS files are pretty separated from Linux code it probably makes sense to share them across projects. The safest solution is to use dual licensing: that way it stays clear these files can be used in GPL projects without depending on current belief of licenses compatibility. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Acked-by: John Crispin <john@phrozen.org>
* ath79: add new OF only target for QCA MIPS siliconJohn Crispin2018-05-071-0/+204
This target aims to replace ar71xx mid-term. The big part that is still missing is making the MMIO/AHB wifi work using OF. NAND and mikrotik subtargets will follow. Signed-off-by: John Crispin <john@phrozen.org>