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While converting Nanostation M XW from current ar71xx code to ath79 I've
hit one issue, where the ethernet networking wasn't working, so I was
checking every bit in the networking setup path between ar71xx and
ath79.
I've came to the following code in ar71xx/mach-ubnt-xm.c:
static void __init ubnt_xw_init(void) {
...
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_MII_GMAC0 |
AR934X_ETH_CFG_MII_GMAC0_SLAVE);
...
}
Where this code is setting AR934X_ETH_CFG_MII_GMAC0_SLAVE bit in
AR934X_GMAC_REG_ETH_CFG register, but I couldn't find a way of setting
this bit from DTS, so this patch adds `mii-gmac0-slave` DTS property
which allows setting of this bit in `gmac-config`, which is then used in
Nanostation M XW DTS.
Tested-by: Joe Ayers <ae6xe@arrl.net>
Signed-off-by: Petr Štetiar <ynezz@true.cz>
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Some AR9344 boards do very poorly with the default settings and
need custom rxdv-delay, rxd-delay, txd-delay, txen-delay flags
to perform reasonably.
In this case the WD My Net Wi-Fi Range Extender can not even
manage 10Mbps on a 1Gbit link:
root@AR9344:~# iperf3 -s
-----------------------------------------------------------
Server listening on 5201
-----------------------------------------------------------
Accepted connection from client [...]
[ 5] local [...] connected to client
[ ID] Interval Transfer Bitrate
[ 5] 0.00-1.00 sec 1.09 MBytes 9.16 Mbits/sec
[ 5] 1.00-2.00 sec 895 KBytes 7.33 Mbits/sec
[ 5] 2.00-3.00 sec 762 KBytes 6.25 Mbits/sec
[...]
[ 5] 10.00-10.03 sec 17.0 KBytes 4.74 Mbits/sec
- - - - - - - - - - - - - - - - - - - - - - - - -
[ ID] Interval Transfer Bitrate
[ 5] 0.00-10.03 sec 9.00 MBytes 7.52 Mbits/sec
with but with the correct settings in place, it does much better:
root@AR9344:~# iperf3 -s
-----------------------------------------------------------
Server listening on 5201
-----------------------------------------------------------
Accepted connection from client [...]
[ 5] local [...] connected to client
[ ID] Interval Transfer Bitrate
[ 5] 0.00-1.00 sec 23.1 MBytes 193 Mbits/sec
[ 5] 1.00-2.00 sec 23.1 MBytes 194 Mbits/sec
[ 5] 2.00-3.00 sec 23.2 MBytes 195 Mbits/sec
[...]
[ 5] 10.00-10.04 sec 710 KBytes 180 Mbits/sec
- - - - - - - - - - - - - - - - - - - - - - - - -
[ ID] Interval Transfer Bitrate
[ 5] 0.00-10.04 sec 237 MBytes 198 Mbits/sec
The tx data and enable delay bits definitions are taken from Atheros'
AR9344 Data Sheet Section "8.6.1 Ethernet Configuration (ETH_CFG)" on
page 153.
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
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This commit adds the ability to configure the GMAC of the QCA956x.
Signed-off-by: David Bauer <mail@david-bauer.net>
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ar934x/qca955x.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
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