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path: root/target/linux/ipq40xx/patches-5.15/704-net-phy-define-PSGMII-PHY-interface-mode.patch
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* ipq40xx: add PSGMII PHY mode to phylink_get_linkmodes()Robert Marko2023-05-121-4/+12
| | | | | | | | | | | | | | | Upstream commit ("net: phylink: add generic validate implementation") was backported, however PSGMII PHY mode patch for ipq40xx was not updated to add PSGMII to phylink_get_linkmodes() so the following warning would be printed during kernel compilation: drivers/net/phy/phylink.c: In function 'phylink_get_linkmodes': drivers/net/phy/phylink.c:360:9: error: enumeration value 'PHY_INTERFACE_MODE_PSGMII' not handled in switch [-Werror=switch] 360 | switch (interface) { | ^~~~~~ Resolve the warning by adding the PSGMII mode to phylink_get_linkmodes(). Signed-off-by: Robert Marko <robimarko@gmail.com>
* kernel: bump 5.15 to 5.15.72John Audia2022-10-091-2/+2
| | | | | | | | | | | | | | | | | Removed upstreamed: generic/pending-5.15/722-net-mt7531-only-do-PLL-once-after-the-reset.patch[1] bcm53xx/patches-5.15/082-v6.0-clk-iproc-Do-not-rely-on-node-name-for-correct-PLL-s.patch[2] All other patches automatically rebased Build system: x86_64 Build-tested: bcm2711/RPi4B, mt7622/RT3200, mvebu/cortexa72 Run-tested: bcm2711/RPi4B, mt7622/RT3200, mvebu/cortexa72 (RB5009UG+S+IN) 1. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.15.72&id=5de02ab84aeca765da0e4d8e999af35325ac67c2 2. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.15.72&id=ab5c5787ab5ecdc4a7ea20b4ef542579e1beb49d Signed-off-by: John Audia <therealgraysky@proton.me>
* ipq40xx: add PSGMII PHY mode defineRobert Marko2022-10-021-0/+61
PSGMII is a Qualcomm specific mode similar to QSGMII but it has 5 SGMII lines instead of 4 in QSGMII. This just adds the support for the PHY layer to be able to identify the mode for further use. It is required for the DSA driver. Signed-off-by: Robert Marko <robert.marko@sartura.hr>