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* bcm27xx: add pwm-fan dependency to RPi PoEÁlvaro Fernández Rojas2022-05-221-1/+1
* realtek: replace RTL93xx GPIO patchesSander Vanheule2022-05-224-64/+234
* mediatek: mt7622: add support for ELECOM WRC-X3200GST3INAGAKI Hiroshi2022-05-214-5/+464
* ath79: NanoBeam M5 fix target_devicesJan-Niklas Burfeind2022-05-212-2/+2
* ath79: add support for Ubiquiti NanoBeam M5Jan-Niklas Burfeind2022-05-212-0/+34
* ath79: add support for MikroTik hAP (RB951Ui-2nD)Maciej Krüger2022-05-216-0/+21
* ath79: add support for MikroTik RouterBOARD hAP ac liteThibaut VARÈNE2022-05-217-0/+142
* bcm27xx: sound-soc-rpi-cirrus: fix packageÁlvaro Fernández Rojas2022-05-201-2/+4
* bcm63xx: add linux v5.15 supportÁlvaro Fernández Rojas2022-05-20133-0/+20886
* bcm27xx: modules: video: fix whitespaceÁlvaro Fernández Rojas2022-05-201-1/+1
* bcm27xx: enable PWM drivers in configÁlvaro Fernández Rojas2022-05-205-18/+18
* bmips: rework ARCH_HAS_SYNC_DMA_FOR_CPU_ALL patchÁlvaro Fernández Rojas2022-05-201-25/+39
* bmips: remove linux 5.10 compatibilityÁlvaro Fernández Rojas2022-05-2062-9491/+0
* bmips: switch to linux 5.15Álvaro Fernández Rojas2022-05-201-2/+1
* bmips: add linux v5.15 supportÁlvaro Fernández Rojas2022-05-2026-4/+1894
* bcm27xx: base-files: align network filesÁlvaro Fernández Rojas2022-05-192-4/+6
* bcm27xx: diag.sh: fix whitespaceÁlvaro Fernández Rojas2022-05-191-1/+1
* ipq40xx: mikrotik: dont include ath10k-board-qca4019 by defaultRobert Marko2022-05-191-0/+1
* ipq-wifi: remove packaged BDF-s for MikroTik devicesRobert Marko2022-05-191-6/+4
* ipq40xx: mikrotik: provide BDF-s on demandRobert Marko2022-05-191-0/+23
* config: limit CONFIG_DEBUG_INFO to top-level generic configsTony Ambardar2022-05-1818-19/+0
* kernel: add DEBUG_INFO_REDUCED config optionStijn Tintel2022-05-182-2/+0
* layerscape/armv8_64b: enable DEBUG_INFO_REDUCEDStijn Tintel2022-05-181-1/+0
* kernel: backport build fix for tools/resolve_btfidsStijn Tintel2022-05-182-0/+108
* bcm27xx: add CPU_FREQ_GOV_SCHEDUTILJohn Audia2022-05-173-0/+7
* bcm27xx: remove linux 5.10 configsÁlvaro Fernández Rojas2022-05-174-1721/+0
* bcm27xx: remove linux 5.10 compatibilityÁlvaro Fernández Rojas2022-05-17718-220355/+2
* bcm27xx: switch to 5.15Álvaro Fernández Rojas2022-05-171-2/+1
* bcm27xx: add support for linux v5.15Álvaro Fernández Rojas2022-05-17924-1/+265734
* kernel: Add missing devm_regulator_get_exclusive()Hauke Mehrtens2022-05-171-0/+79
* kernel: bump 5.15 to 5.15.40John Audia2022-05-165-10/+5
* kernel: bump 5.15 to 5.15.39John Audia2022-05-1632-1822/+2
* kernel: bump 5.10 to 5.10.115John Audia2022-05-1627-159/+43
* kernel: bump 5.10 to 5.10.114John Audia2022-05-1616-30/+30
* ramips: Add support for SERCOMM NA502SAndreas Böhler2022-05-164-0/+379
* ramips: add led_source for Asus RT-AC1200 devicesTamas Balogh2022-05-151-0/+1
* IPQ4019: AVM FRITZ!Box 7530: Remove NAND ECC restrictions from DTSAndreas Böhler2022-05-151-0/+3
* kernel: add support for Toshiba TC58NVG0S3HTA00 NAND flashAndreas Böhler2022-05-152-0/+72
* ath79: ZTE MF286[A,R]: add "Power button blocker" GPIO switchLech Perczak2022-05-151-0/+20
* ipq40xx: revert Cell-C RTL30VW to legacy caldata extractionPawel Dembicki2022-05-152-15/+2
* ath79: fix I2C on GL-AR300M devicesPtilopsis Leucotis2022-05-151-0/+9
* mpc85xx: enable error reporting for RAM and PCIeJosef Schlehofer2022-05-141-0/+4
* ipq-wifi: drop upstreamed board-2.binChristian Lamparter2022-05-143-20/+13
* ipq40xx: Lyra: update RGB LED-Controller node for 5.10+Christian Lamparter2022-05-142-47/+78
* apm821xx: use nested fixed-partitionsChristian Lamparter2022-05-142-24/+47
* bcm53xx: remove MR32's specific get_leds_dt codeChristian Lamparter2022-05-142-31/+0
* lantiq: xway: disable unused switch driversAleksander Jan Bajkowski2022-05-141-3/+0
* ramips: fix booting on Samknows SK-WB8Piotr Dymacz2022-05-131-0/+1
* realtek: do not reset SerDes on link changeBirger Koblitz2022-05-112-1/+3
* kernel: bump 5.15 to 5.15.38Rui Salvaterra2022-05-096-99/+11
generated by cgit v1.2.3 (git 2.25.1) at 2025-10-02 17:12:29 +0000
ass="o">::unique_ptr<ezSAT> { ezSatPtr() : unique_ptr<ezSAT>(yosys_satsolver->create()) { } }; struct SatGen { ezSAT *ez; SigMap *sigmap; std::string prefix; SigPool initial_state; std::map<std::string, RTLIL::SigSpec> asserts_a, asserts_en; std::map<std::string, RTLIL::SigSpec> assumes_a, assumes_en; std::map<std::string, std::map<RTLIL::SigBit, int>> imported_signals; std::map<std::pair<std::string, int>, bool> initstates; bool ignore_div_by_zero; bool model_undef; SatGen(ezSAT *ez, SigMap *sigmap, std::string prefix = std::string()) : ez(ez), sigmap(sigmap), prefix(prefix), ignore_div_by_zero(false), model_undef(false) { } void setContext(SigMap *sigmap, std::string prefix = std::string()) { this->sigmap = sigmap; this->prefix = prefix; } std::vector<int> importSigSpecWorker(RTLIL::SigSpec sig, std::string &pf, bool undef_mode, bool dup_undef) { log_assert(!undef_mode || model_undef); sigmap->apply(sig); std::vector<int> vec; vec.reserve(GetSize(sig)); for (auto &bit : sig) if (bit.wire == NULL) { if (model_undef && dup_undef && bit == RTLIL::State::Sx) vec.push_back(ez->frozen_literal()); else vec.push_back(bit == (undef_mode ? RTLIL::State::Sx : RTLIL::State::S1) ? ez->CONST_TRUE : ez->CONST_FALSE); } else { std::string name = pf + (bit.wire->width == 1 ? stringf("%s", log_id(bit.wire)) : stringf("%s [%d]", log_id(bit.wire->name), bit.offset)); vec.push_back(ez->frozen_literal(name)); imported_signals[pf][bit] = vec.back(); } return vec; } std::vector<int> importSigSpec(RTLIL::SigSpec sig, int timestep = -1) { log_assert(timestep != 0); std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep)); return importSigSpecWorker(sig, pf, false, false); } std::vector<int> importDefSigSpec(RTLIL::SigSpec sig, int timestep = -1) { log_assert(timestep != 0); std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep)); return importSigSpecWorker(sig, pf, false, true); } std::vector<int> importUndefSigSpec(RTLIL::SigSpec sig, int timestep = -1) { log_assert(timestep != 0); std::string pf = "undef:" + prefix + (timestep == -1 ? "" : stringf("@%d:", timestep)); return importSigSpecWorker(sig, pf, true, false); } int importSigBit(RTLIL::SigBit bit, int timestep = -1) { log_assert(timestep != 0); std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep)); return importSigSpecWorker(bit, pf, false, false).front(); } int importDefSigBit(RTLIL::SigBit bit, int timestep = -1) { log_assert(timestep != 0); std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep)); return importSigSpecWorker(bit, pf, false, true).front(); } int importUndefSigBit(RTLIL::SigBit bit, int timestep = -1) { log_assert(timestep != 0); std::string pf = "undef:" + prefix + (timestep == -1 ? "" : stringf("@%d:", timestep)); return importSigSpecWorker(bit, pf, true, false).front(); } bool importedSigBit(RTLIL::SigBit bit, int timestep = -1) { log_assert(timestep != 0); std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep)); return imported_signals[pf].count(bit) != 0; } void getAsserts(RTLIL::SigSpec &sig_a, RTLIL::SigSpec &sig_en, int timestep = -1) { std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep)); sig_a = asserts_a[pf]; sig_en = asserts_en[pf]; } void getAssumes(RTLIL::SigSpec &sig_a, RTLIL::SigSpec &sig_en, int timestep = -1) { std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep)); sig_a = assumes_a[pf]; sig_en = assumes_en[pf]; } int importAsserts(int timestep = -1) { std::vector<int> check_bits, enable_bits; std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep)); if (model_undef) { check_bits = ez->vec_and(ez->vec_not(importUndefSigSpec(asserts_a[pf], timestep)), importDefSigSpec(asserts_a[pf], timestep)); enable_bits = ez->vec_and(ez->vec_not(importUndefSigSpec(asserts_en[pf], timestep)), importDefSigSpec(asserts_en[pf], timestep)); } else { check_bits = importDefSigSpec(asserts_a[pf], timestep); enable_bits = importDefSigSpec(asserts_en[pf], timestep); } return ez->vec_reduce_and(ez->vec_or(check_bits, ez->vec_not(enable_bits))); } int importAssumes(int timestep = -1) { std::vector<int> check_bits, enable_bits; std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep)); if (model_undef) { check_bits = ez->vec_and(ez->vec_not(importUndefSigSpec(assumes_a[pf], timestep)), importDefSigSpec(assumes_a[pf], timestep)); enable_bits = ez->vec_and(ez->vec_not(importUndefSigSpec(assumes_en[pf], timestep)), importDefSigSpec(assumes_en[pf], timestep)); } else { check_bits = importDefSigSpec(assumes_a[pf], timestep); enable_bits = importDefSigSpec(assumes_en[pf], timestep); } return ez->vec_reduce_and(ez->vec_or(check_bits, ez->vec_not(enable_bits))); } int signals_eq(RTLIL::SigSpec lhs, RTLIL::SigSpec rhs, int timestep_lhs = -1, int timestep_rhs = -1) { if (timestep_rhs < 0) timestep_rhs = timestep_lhs; log_assert(lhs.size() == rhs.size()); std::vector<int> vec_lhs = importSigSpec(lhs, timestep_lhs); std::vector<int> vec_rhs = importSigSpec(rhs, timestep_rhs); if (!model_undef) return ez->vec_eq(vec_lhs, vec_rhs); std::vector<int> undef_lhs = importUndefSigSpec(lhs, timestep_lhs); std::vector<int> undef_rhs = importUndefSigSpec(rhs, timestep_rhs); std::vector<int> eq_bits; for (int i = 0; i < lhs.size(); i++) eq_bits.push_back(ez->AND(ez->IFF(undef_lhs.at(i), undef_rhs.at(i)), ez->IFF(ez->OR(vec_lhs.at(i), undef_lhs.at(i)), ez->OR(vec_rhs.at(i), undef_rhs.at(i))))); return ez->expression(ezSAT::OpAnd, eq_bits); } void extendSignalWidth(std::vector<int> &vec_a, std::vector<int> &vec_b, RTLIL::Cell *cell, size_t y_width = 0, bool forced_signed = false) { bool is_signed = forced_signed; if (!forced_signed && cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters.count(ID::B_SIGNED) > 0) is_signed = cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool(); while (vec_a.size() < vec_b.size() || vec_a.size() < y_width) vec_a.push_back(is_signed && vec_a.size() > 0 ? vec_a.back() : ez->CONST_FALSE); while (vec_b.size() < vec_a.size() || vec_b.size() < y_width) vec_b.push_back(is_signed && vec_b.size() > 0 ? vec_b.back() : ez->CONST_FALSE); } void extendSignalWidth(std::vector<int> &vec_a, std::vector<int> &vec_b, std::vector<int> &vec_y, RTLIL::Cell *cell, bool forced_signed = false) { extendSignalWidth(vec_a, vec_b, cell, vec_y.size(), forced_signed); while (vec_y.size() < vec_a.size()) vec_y.push_back(ez->literal()); } void extendSignalWidthUnary(std::vector<int> &vec_a, std::vector<int> &vec_y, RTLIL::Cell *cell, bool forced_signed = false) { bool is_signed = forced_signed || (cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters[ID::A_SIGNED].as_bool()); while (vec_a.size() < vec_y.size()) vec_a.push_back(is_signed && vec_a.size() > 0 ? vec_a.back() : ez->CONST_FALSE); while (vec_y.size() < vec_a.size()) vec_y.push_back(ez->literal()); } void undefGating(std::vector<int> &vec_y, std::vector<int> &vec_yy, std::vector<int> &vec_undef) { log_assert(model_undef); log_assert(vec_y.size() == vec_yy.size()); if (vec_y.size() > vec_undef.size()) { std::vector<int> trunc_y(vec_y.begin(), vec_y.begin() + vec_undef.size()); std::vector<int> trunc_yy(vec_yy.begin(), vec_yy.begin() + vec_undef.size()); ez->assume(ez->expression(ezSAT::OpAnd, ez->vec_or(vec_undef, ez->vec_iff(trunc_y, trunc_yy)))); } else { log_assert(vec_y.size() == vec_undef.size()); ez->assume(ez->expression(ezSAT::OpAnd, ez->vec_or(vec_undef, ez->vec_iff(vec_y, vec_yy)))); } } std::pair<std::vector<int>, std::vector<int>> mux(int s, int undef_s, const std::vector<int> &a, const std::vector<int> &undef_a, const std::vector<int> &b, const std::vector<int> &undef_b) { std::vector<int> res; std::vector<int> undef_res; res = ez->vec_ite(s, b, a); if (model_undef) { std::vector<int> unequal_ab = ez->vec_not(ez->vec_iff(a, b)); std::vector<int> undef_ab = ez->vec_or(unequal_ab, ez->vec_or(undef_a, undef_b)); undef_res = ez->vec_ite(undef_s, undef_ab, ez->vec_ite(s, undef_b, undef_a)); } return std::make_pair(res, undef_res); } void undefGating(int y, int yy, int undef) { ez->assume(ez->OR(undef, ez->IFF(y, yy))); } void setInitState(int timestep) { auto key = make_pair(prefix, timestep); log_assert(initstates.count(key) == 0 || initstates.at(key) == true); initstates[key] = true; } bool importCell(RTLIL::Cell *cell, int timestep = -1); }; YOSYS_NAMESPACE_END #endif
generated by cgit v1.2.3 (git 2.25.1) at 2025-10-02 17:12:26 +0000