From 668d3116796d5c121f058ed91b384b1bdb226aca Mon Sep 17 00:00:00 2001 From: John Crispin Date: Sat, 2 Jun 2007 23:17:43 +0000 Subject: the etrax bootloader tools source was added on initial merge, it is now sitting on the acme site, source should not be in this folder SVN-Revision: 7465 --- target/linux/etrax-2.6/image/e100boot/Makefile | 8 +- target/linux/etrax-2.6/image/e100boot/src/LICENSE | 26 - target/linux/etrax-2.6/image/e100boot/src/Makefile | 70 - .../etrax-2.6/image/e100boot/src/cbl/Makefile | 25 - .../etrax-2.6/image/e100boot/src/cbl/free_size | 42 - .../etrax-2.6/image/e100boot/src/cbl/net/Makefile | 6 - .../etrax-2.6/image/e100boot/src/cbl/net/common.d | 3 - .../image/e100boot/src/cbl/net/common_init.d | 3 - .../etrax-2.6/image/e100boot/src/cbl/net/crt0.d | 1 - .../image/e100boot/src/cbl/net/e100boot_version.c | 1 - .../image/e100boot/src/cbl/net/e100boot_version.d | 1 - .../etrax-2.6/image/e100boot/src/cbl/net/flash.d | 1 - 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100755 target/linux/etrax-2.6/image/e100boot/src/sbl/win32/boot_images.c delete mode 100644 target/linux/etrax-2.6/image/e100boot/src/sbl/win32/common.c delete mode 100755 target/linux/etrax-2.6/image/e100boot/src/sbl/win32/network.c delete mode 100644 target/linux/etrax-2.6/image/e100boot/src/sendserial/Makefile delete mode 100644 target/linux/etrax-2.6/image/e100boot/src/sendserial/sendserial.c diff --git a/target/linux/etrax-2.6/image/e100boot/Makefile b/target/linux/etrax-2.6/image/e100boot/Makefile index 64e3444393..2480cd502e 100644 --- a/target/linux/etrax-2.6/image/e100boot/Makefile +++ b/target/linux/etrax-2.6/image/e100boot/Makefile @@ -13,6 +13,10 @@ PKG_NAME:=e100boot PKG_VERSION:=0.1 PKG_RELEASE:=1 +PKG_SOURCE:=e100boot.tar.bz2 +PKG_SOURCE_URL:=http://www.acmesystems.it/download/owrt +PKG_MD5SUM:= + PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/$(PKG_NAME) CRLF_WORKAROUND=1 @@ -20,9 +24,7 @@ CRLF_WORKAROUND=1 include $(INCLUDE_DIR)/package.mk define Build/Compile - mkdir -p $(PKG_BUILD_DIR) - cp -r ./src/* $(PKG_BUILD_DIR) - make -C $(PKG_BUILD_DIR) + make -C $(PKG_BUILD_DIR) CC=$(TARGET_CC) STRIP=true endef define Build/InstallDev diff --git a/target/linux/etrax-2.6/image/e100boot/src/LICENSE b/target/linux/etrax-2.6/image/e100boot/src/LICENSE deleted file mode 100644 index afbcf2ec6c..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/LICENSE +++ /dev/null @@ -1,26 +0,0 @@ -Copyright (c) 2004, 2005 Axis Communications AB. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions -are met: - -1. Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. -2. Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. -3. Neither the name of Axis Communications AB nor the names of its - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY AXIS COMMUNCATIONS AB ``AS IS'' AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE -FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -SUCH DAMAGE. diff --git a/target/linux/etrax-2.6/image/e100boot/src/Makefile b/target/linux/etrax-2.6/image/e100boot/src/Makefile deleted file mode 100644 index 828b402211..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/Makefile +++ /dev/null @@ -1,70 +0,0 @@ -# -# Top Makefile for e100boot -# $Id: Makefile,v 1.20 2003/06/04 12:22:23 pkj Exp $ -# - -# Change these paths if necessary. Can also be specified on cmdline as -# 'make INSTALL_PATH=/foo/bar/'. - -INSTALL_NAME = e100boot -INSTALL_PATH = /usr/local -INSTALL_PATH_BIN = $(INSTALL_PATH)/bin -INSTALL_PATH_DOC = $(INSTALL_PATH)/man/man1 - -DIRS = libpcap-0.4 sbl doc - --include $(AXIS_TOP_DIR)/tools/build/Rules.axis -ifdef prefix -INSTALL_PATH = $(prefix) -endif - -INSTALL ?= install - -all: conf $(DIRS) - @for d in $(DIRS); do \ - echo -e "\n### Making $$d"; \ - $(MAKE) -C $$d || exit; \ - done - -conf: $(DIRS) - @for d in $(DIRS); do \ - if [ -x $$d/configure ] && [ ! -e $$d/Makefile ]; then \ - echo -e "\n### Configuring $$d"; \ - cd $$d; ./configure || exit; cd ..; \ - fi; \ - done - -tar: clean - @echo -e "\n### Making tarball." - tar -C ../ -zcf e100boot.tgz --exclude e100boot.tgz --exclude RCS --exclude CVS e100boot - - -install: all - $(INSTALL) -d $(INSTALL_PATH_BIN) $(INSTALL_PATH_DOC) - $(INSTALL) sbl/e100boot.stripped $(INSTALL_PATH_BIN)/$(INSTALL_NAME) - $(INSTALL) -m 0644 doc/e100boot.1 $(INSTALL_PATH_DOC)/$(INSTALL_NAME).1 - -install.setuid: - @echo -e "\n### Make install.setuid"; \ - if ! [ -e $(INSTALL_PATH_BIN)/$(INSTALL_NAME) ]; then \ - echo -e "\n### Binary $(INSTALL_PATH_BIN)/$(INSTALL_NAME) does not exist! Make install first."; \ - elif [ `id -u` = 0 ]; then \ - chown root.root $(INSTALL_PATH_BIN)/$(INSTALL_NAME); \ - chmod +s $(INSTALL_PATH_BIN)/$(INSTALL_NAME); \ - else \ - echo "### You must do this as root!"; \ - fi - -clean: - @for d in $(DIRS); do \ - if [ -e $$d/Makefile ]; then \ - echo -e "\n### Cleaning $$d"; \ - $(MAKE) -C $$d clean || exit; \ - fi; \ - done - -configsubs: conf configsubs-dirs - -configsubs-dirs: - $(MAKE) -C libpcap-0.4 configsubs - $(MAKE) -C sbl configsubs diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/Makefile b/target/linux/etrax-2.6/image/e100boot/src/cbl/Makefile deleted file mode 100644 index af7ed075d1..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/cbl/Makefile +++ /dev/null @@ -1,25 +0,0 @@ -# -# Makefile to generate .ima files for e100boot -# -# Hacked by ronny, rehacked by ronny -# -# $Id: Makefile,v 1.26 2003/03/13 14:18:31 cii Exp $ -# - -DIRS := net net_noleds ser ser_noleds - -all: $(DIRS) - @for d in $(DIRS); do \ - echo -e "\n### Making $$d"; \ - make -C $$d || exit; \ - done - @echo "***************************************************************" - @./free_size - @echo "***************************************************************" - -clean: - rm -f *.ima - @for d in $(DIRS); do \ - echo -e "\n### Cleaning $$d"; \ - make -C $$d clean || exit; \ - done; diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/free_size b/target/linux/etrax-2.6/image/e100boot/src/cbl/free_size deleted file mode 100755 index 73e1365e4b..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/cbl/free_size +++ /dev/null @@ -1,42 +0,0 @@ -#!/bin/sh -# -# Calculates the size left in ETRAX cache when bootloader is loaded. -# - -BOOT_FILE=`dirname $0`/net/net.out -HEADER_FILE=`dirname $0`/src/e100boot.h - -for FILE in $BOOT_FILE $HEADER_FILE; do - if [ ! -f $FILE ]; then - echo "Could not find the file \"$FILE\"!" - exit 1 - fi -done - -# The cache size is given in hex -CACHE_SIZE=2000 - -BSS_SIZE=`nm-cris $BOOT_FILE | grep Ebss | cut -d ' ' -f 1 | tr a-f A-F` - -TEXT_SIZE=`nm-cris $BOOT_FILE | grep Stext | cut -d ' ' -f 1 | tr a-f A-F` - -IO_BUF_END=`grep IO_BUF_END $HEADER_FILE | awk '{ print $3 }' | \ - cut -d x -f 2 | tr a-f A-F` - -IO_BUF_START=`grep IO_BUF_START $HEADER_FILE | awk '{ print $3 }' | \ - cut -d x -f 2 | tr a-f A-F` - -FREE_SIZE=`echo "ibase=16 ; \ - $CACHE_SIZE - \ - ($BSS_SIZE - $TEXT_SIZE + $IO_BUF_END - $IO_BUF_START)" | \ - bc` - -echo "Free cache size when cbl is loaded will be:" -echo -e "\t$FREE_SIZE bytes - size of stack" - -if [ $FREE_SIZE -lt 0 ]; then - echo "Bootloader is too large! You will have to do some optimizing..." - exit 1 -fi - -exit 0 diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/net/Makefile b/target/linux/etrax-2.6/image/e100boot/src/cbl/net/Makefile deleted file mode 100644 index a77cc5d6cd..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/cbl/net/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# -# $Id: Makefile,v 1.1 2002/07/01 14:36:40 pkj Exp $ -# - -IMAGE := net.ima -include ../rules.cbl diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/net/common.d b/target/linux/etrax-2.6/image/e100boot/src/cbl/net/common.d deleted file mode 100644 index efe422d771..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/cbl/net/common.d +++ /dev/null @@ -1,3 +0,0 @@ -common.o: ../src/common.c ../src/hwregs.h ../src/compiler.h \ - ../src/debug.h ../src/project.h ../src/hwregs_def.h ../src/hwregs_int.h \ - ../src/e100boot.h diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/net/common_init.d b/target/linux/etrax-2.6/image/e100boot/src/cbl/net/common_init.d deleted file mode 100644 index 3591272ad7..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/cbl/net/common_init.d +++ /dev/null @@ -1,3 +0,0 @@ -common_init.o: ../src/common_init.c ../src/hwregs.h ../src/compiler.h \ - ../src/debug.h ../src/project.h ../src/hwregs_def.h ../src/hwregs_int.h \ - ../src/e100boot.h diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/net/crt0.d b/target/linux/etrax-2.6/image/e100boot/src/cbl/net/crt0.d deleted file mode 100644 index e33f99ad17..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/cbl/net/crt0.d +++ /dev/null @@ -1 +0,0 @@ -crt0.o: ../src/crt0.S diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/net/e100boot_version.c b/target/linux/etrax-2.6/image/e100boot/src/cbl/net/e100boot_version.c deleted file mode 100644 index 7600f6d19b..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/cbl/net/e100boot_version.c +++ /dev/null @@ -1 +0,0 @@ -char e100boot_version[] = "This bootloader was built by root on Wed May 16 21:31:41 CEST 2007.\r\n"; diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/net/e100boot_version.d b/target/linux/etrax-2.6/image/e100boot/src/cbl/net/e100boot_version.d deleted file mode 100644 index fd45693367..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/cbl/net/e100boot_version.d +++ /dev/null @@ -1 +0,0 @@ -e100boot_version.o: e100boot_version.c diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/net/flash.d b/target/linux/etrax-2.6/image/e100boot/src/cbl/net/flash.d deleted file mode 100644 index f11cf68247..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/cbl/net/flash.d +++ /dev/null @@ -1 +0,0 @@ -flash.o: ../src/flash.c ../src/e100boot.h ../src/compiler.h diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/net/hwregs.d b/target/linux/etrax-2.6/image/e100boot/src/cbl/net/hwregs.d deleted file mode 100644 index 7158582d08..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/cbl/net/hwregs.d +++ /dev/null @@ -1,2 +0,0 @@ -hwregs.o: ../src/hwregs.c ../src/compiler.h ../src/hwregs.h \ - ../src/debug.h ../src/project.h ../src/hwregs_def.h ../src/hwregs_int.h diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/net/net_init.d b/target/linux/etrax-2.6/image/e100boot/src/cbl/net/net_init.d deleted file mode 100644 index c2b32bf286..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/cbl/net/net_init.d +++ /dev/null @@ -1,2 +0,0 @@ -net_init.o: ../src/net_init.c ../src/sv_addr_ag.h ../src/sv_addr.agh \ - ../src/e100boot.h ../src/compiler.h diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/net_noleds/Makefile b/target/linux/etrax-2.6/image/e100boot/src/cbl/net_noleds/Makefile deleted file mode 100644 index 9479cbab83..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/cbl/net_noleds/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# -# $Id: Makefile,v 1.1 2002/07/01 14:36:51 pkj Exp $ -# - -IMAGE := net_noleds.ima -include ../rules.cbl diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/net_noleds/common.d b/target/linux/etrax-2.6/image/e100boot/src/cbl/net_noleds/common.d deleted file mode 100644 index efe422d771..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/cbl/net_noleds/common.d +++ /dev/null @@ -1,3 +0,0 @@ -common.o: ../src/common.c ../src/hwregs.h ../src/compiler.h \ - ../src/debug.h ../src/project.h ../src/hwregs_def.h ../src/hwregs_int.h \ - ../src/e100boot.h diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/net_noleds/common_init.d b/target/linux/etrax-2.6/image/e100boot/src/cbl/net_noleds/common_init.d deleted file mode 100644 index 3591272ad7..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/cbl/net_noleds/common_init.d +++ /dev/null @@ -1,3 +0,0 @@ -common_init.o: ../src/common_init.c ../src/hwregs.h ../src/compiler.h \ - ../src/debug.h ../src/project.h ../src/hwregs_def.h ../src/hwregs_int.h \ - ../src/e100boot.h diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/net_noleds/crt0.d b/target/linux/etrax-2.6/image/e100boot/src/cbl/net_noleds/crt0.d deleted file mode 100644 index e33f99ad17..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/cbl/net_noleds/crt0.d +++ /dev/null @@ -1 +0,0 @@ -crt0.o: ../src/crt0.S diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/net_noleds/e100boot_version.c b/target/linux/etrax-2.6/image/e100boot/src/cbl/net_noleds/e100boot_version.c deleted file mode 100644 index b503ab3b01..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/cbl/net_noleds/e100boot_version.c +++ /dev/null @@ -1 +0,0 @@ -char e100boot_version[] = "This bootloader was built by root on Wed May 16 21:31:43 CEST 2007.\r\n"; diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/net_noleds/e100boot_version.d b/target/linux/etrax-2.6/image/e100boot/src/cbl/net_noleds/e100boot_version.d deleted file mode 100644 index fd45693367..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/cbl/net_noleds/e100boot_version.d +++ /dev/null @@ -1 +0,0 @@ -e100boot_version.o: e100boot_version.c diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/net_noleds/flash.d b/target/linux/etrax-2.6/image/e100boot/src/cbl/net_noleds/flash.d deleted file mode 100644 index f11cf68247..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/cbl/net_noleds/flash.d +++ /dev/null @@ -1 +0,0 @@ -flash.o: ../src/flash.c ../src/e100boot.h ../src/compiler.h diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/net_noleds/hwregs.d b/target/linux/etrax-2.6/image/e100boot/src/cbl/net_noleds/hwregs.d deleted file mode 100644 index 7158582d08..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/cbl/net_noleds/hwregs.d +++ /dev/null @@ -1,2 +0,0 @@ -hwregs.o: ../src/hwregs.c ../src/compiler.h ../src/hwregs.h \ - ../src/debug.h ../src/project.h ../src/hwregs_def.h ../src/hwregs_int.h diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/net_noleds/net_init.d b/target/linux/etrax-2.6/image/e100boot/src/cbl/net_noleds/net_init.d deleted file mode 100644 index c2b32bf286..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/cbl/net_noleds/net_init.d +++ /dev/null @@ -1,2 +0,0 @@ -net_init.o: ../src/net_init.c ../src/sv_addr_ag.h ../src/sv_addr.agh \ - ../src/e100boot.h ../src/compiler.h diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/rules.cbl b/target/linux/etrax-2.6/image/e100boot/src/cbl/rules.cbl deleted file mode 100644 index 5459090558..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/cbl/rules.cbl +++ /dev/null @@ -1,55 +0,0 @@ -# -# $Id: rules.cbl,v 1.4 2005/04/20 11:18:54 starvik Exp $ -# - -VPATH := .:../src - -ifeq ($(findstring _noleds,$(IMAGE)),_noleds) -USE_LEDS := 0 -else -USE_LEDS := 1 -endif - -MAKEFLAGS := r -INCS := -I. -DEFS := -DUSE_LEDS=$(USE_LEDS) -CFLAGS := -Os -Wall -Wmissing-prototypes -W -Wa,-N -nostdinc $(INCS) $(DEFS) -MMD -ASFLAGS := $(CFLAGS) -LNFLAGS := -Wl,--section-start,.startup=0x380000f0 -nostdlib -Os -Wl,-T../src/ldscript -CC := cris-axis-elf-gcc - -OUT := $(patsubst %.ima,%.out,$(IMAGE)) - -OBJS = crt0.o common_init.o -ifeq ($(findstring net,$(IMAGE)),net) -OBJS += net_init.o -else -OBJS += ser_init.o -endif -OBJS += common.o flash.o hwregs.o e100boot_version.o - -all: ../$(IMAGE) - -$(OUT): $(OBJS) ldscript - $(CC) -o $@ $(LNFLAGS) $(OBJS) - -../%.ima: %.out - bin-cris -o $@ $< - @find $@ -printf '# Size of image $@ is %s bytes.\n\n' - -$(OBJS): ../rules.cbl Makefile - -# We don't want this to be a dummy and be recreated every time we build, -# only after a make clean -e100boot_version.c: - @echo "Generating version file....." - @echo 'char e100boot_version[] = "This bootloader was built by '`id -u -n`' on '`date`'.\r\n";' > $@ - -dummy: - -clean: - rm -rf *.o *.d *.out *.ima deps e100boot_version.c - -ifneq ($(MAKECMDGOALS),clean) --include *.d -endif diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/ser.ima b/target/linux/etrax-2.6/image/e100boot/src/cbl/ser.ima deleted file mode 100755 index 388ccc3816..0000000000 Binary files a/target/linux/etrax-2.6/image/e100boot/src/cbl/ser.ima and /dev/null differ diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/ser/Makefile b/target/linux/etrax-2.6/image/e100boot/src/cbl/ser/Makefile deleted file mode 100644 index 0905a5a5b9..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/cbl/ser/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# -# $Id: Makefile,v 1.1 2002/07/01 14:37:01 pkj Exp $ -# - -IMAGE := ser.ima -include ../rules.cbl diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/ser/common.d b/target/linux/etrax-2.6/image/e100boot/src/cbl/ser/common.d deleted file mode 100644 index efe422d771..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/cbl/ser/common.d +++ /dev/null @@ -1,3 +0,0 @@ -common.o: ../src/common.c ../src/hwregs.h ../src/compiler.h \ - ../src/debug.h ../src/project.h ../src/hwregs_def.h ../src/hwregs_int.h \ - ../src/e100boot.h diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/ser/common_init.d b/target/linux/etrax-2.6/image/e100boot/src/cbl/ser/common_init.d deleted file mode 100644 index 3591272ad7..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/cbl/ser/common_init.d +++ /dev/null @@ -1,3 +0,0 @@ -common_init.o: ../src/common_init.c ../src/hwregs.h ../src/compiler.h \ - ../src/debug.h ../src/project.h ../src/hwregs_def.h ../src/hwregs_int.h \ - ../src/e100boot.h diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/ser/crt0.d b/target/linux/etrax-2.6/image/e100boot/src/cbl/ser/crt0.d deleted file mode 100644 index e33f99ad17..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/cbl/ser/crt0.d +++ /dev/null @@ -1 +0,0 @@ -crt0.o: ../src/crt0.S diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/ser/e100boot_version.c b/target/linux/etrax-2.6/image/e100boot/src/cbl/ser/e100boot_version.c deleted file mode 100644 index 6ffd0de217..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/cbl/ser/e100boot_version.c +++ /dev/null @@ -1 +0,0 @@ -char e100boot_version[] = "This bootloader was built by root on Wed May 16 21:31:44 CEST 2007.\r\n"; diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/ser/e100boot_version.d b/target/linux/etrax-2.6/image/e100boot/src/cbl/ser/e100boot_version.d deleted file mode 100644 index fd45693367..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/cbl/ser/e100boot_version.d +++ /dev/null @@ -1 +0,0 @@ -e100boot_version.o: e100boot_version.c diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/ser/flash.d b/target/linux/etrax-2.6/image/e100boot/src/cbl/ser/flash.d deleted file mode 100644 index f11cf68247..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/cbl/ser/flash.d +++ /dev/null @@ -1 +0,0 @@ -flash.o: ../src/flash.c ../src/e100boot.h ../src/compiler.h diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/ser/hwregs.d b/target/linux/etrax-2.6/image/e100boot/src/cbl/ser/hwregs.d deleted file mode 100644 index 7158582d08..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/cbl/ser/hwregs.d +++ /dev/null @@ -1,2 +0,0 @@ -hwregs.o: ../src/hwregs.c ../src/compiler.h ../src/hwregs.h \ - ../src/debug.h ../src/project.h ../src/hwregs_def.h ../src/hwregs_int.h diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/ser/ser.out b/target/linux/etrax-2.6/image/e100boot/src/cbl/ser/ser.out deleted file mode 100755 index 5c6156b7e8..0000000000 Binary files a/target/linux/etrax-2.6/image/e100boot/src/cbl/ser/ser.out and /dev/null differ diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/ser/ser_init.d b/target/linux/etrax-2.6/image/e100boot/src/cbl/ser/ser_init.d deleted file mode 100644 index 89a6d90de1..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/cbl/ser/ser_init.d +++ /dev/null @@ -1,3 +0,0 @@ -ser_init.o: ../src/ser_init.c ../src/hwregs.h ../src/compiler.h \ - ../src/debug.h ../src/project.h ../src/hwregs_def.h ../src/hwregs_int.h \ - ../src/sv_addr_ag.h ../src/sv_addr.agh ../src/e100boot.h diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/ser_noleds/Makefile b/target/linux/etrax-2.6/image/e100boot/src/cbl/ser_noleds/Makefile deleted file mode 100644 index 9bb999c38f..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/cbl/ser_noleds/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# -# $Id: Makefile,v 1.1 2002/07/01 14:37:10 pkj Exp $ -# - -IMAGE := ser_noleds.ima -include ../rules.cbl diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/ser_noleds/common.d b/target/linux/etrax-2.6/image/e100boot/src/cbl/ser_noleds/common.d deleted file mode 100644 index efe422d771..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/cbl/ser_noleds/common.d +++ /dev/null @@ -1,3 +0,0 @@ -common.o: ../src/common.c ../src/hwregs.h ../src/compiler.h \ - ../src/debug.h ../src/project.h ../src/hwregs_def.h ../src/hwregs_int.h \ - ../src/e100boot.h diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/ser_noleds/common_init.d b/target/linux/etrax-2.6/image/e100boot/src/cbl/ser_noleds/common_init.d deleted file mode 100644 index 3591272ad7..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/cbl/ser_noleds/common_init.d +++ /dev/null @@ -1,3 +0,0 @@ -common_init.o: ../src/common_init.c ../src/hwregs.h ../src/compiler.h \ - ../src/debug.h ../src/project.h ../src/hwregs_def.h ../src/hwregs_int.h \ - ../src/e100boot.h diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/ser_noleds/crt0.d b/target/linux/etrax-2.6/image/e100boot/src/cbl/ser_noleds/crt0.d deleted file mode 100644 index e33f99ad17..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/cbl/ser_noleds/crt0.d +++ /dev/null @@ -1 +0,0 @@ -crt0.o: ../src/crt0.S diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/ser_noleds/e100boot_version.c b/target/linux/etrax-2.6/image/e100boot/src/cbl/ser_noleds/e100boot_version.c deleted file mode 100644 index c4753698df..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/cbl/ser_noleds/e100boot_version.c +++ /dev/null @@ -1 +0,0 @@ -char e100boot_version[] = "This bootloader was built by root on Wed May 16 21:31:46 CEST 2007.\r\n"; diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/ser_noleds/e100boot_version.d b/target/linux/etrax-2.6/image/e100boot/src/cbl/ser_noleds/e100boot_version.d deleted file mode 100644 index fd45693367..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/cbl/ser_noleds/e100boot_version.d +++ /dev/null @@ -1 +0,0 @@ -e100boot_version.o: e100boot_version.c diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/ser_noleds/flash.d b/target/linux/etrax-2.6/image/e100boot/src/cbl/ser_noleds/flash.d deleted file mode 100644 index f11cf68247..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/cbl/ser_noleds/flash.d +++ /dev/null @@ -1 +0,0 @@ -flash.o: ../src/flash.c ../src/e100boot.h ../src/compiler.h diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/ser_noleds/hwregs.d b/target/linux/etrax-2.6/image/e100boot/src/cbl/ser_noleds/hwregs.d deleted file mode 100644 index 7158582d08..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/cbl/ser_noleds/hwregs.d +++ /dev/null @@ -1,2 +0,0 @@ -hwregs.o: ../src/hwregs.c ../src/compiler.h ../src/hwregs.h \ - ../src/debug.h ../src/project.h ../src/hwregs_def.h ../src/hwregs_int.h diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/ser_noleds/ser_init.d b/target/linux/etrax-2.6/image/e100boot/src/cbl/ser_noleds/ser_init.d deleted file mode 100644 index 89a6d90de1..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/cbl/ser_noleds/ser_init.d +++ /dev/null @@ -1,3 +0,0 @@ -ser_init.o: ../src/ser_init.c ../src/hwregs.h ../src/compiler.h \ - ../src/debug.h ../src/project.h ../src/hwregs_def.h ../src/hwregs_int.h \ - ../src/sv_addr_ag.h ../src/sv_addr.agh ../src/e100boot.h diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/src/common.c b/target/linux/etrax-2.6/image/e100boot/src/cbl/src/common.c deleted file mode 100644 index e4ebdc40d7..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/cbl/src/common.c +++ /dev/null @@ -1,486 +0,0 @@ -#include "hwregs.h" -#include "e100boot.h" - -static void toggle_led(void); - -static void read_load_info(void); -static void decode_load_info(void); - -static void read_file(byte* addr, udword size); - -#if USE_PRINT_DESCR -static void print_descr(dma_descr_T *d); -#endif - -static int memory_test(udword addr, udword size, udword *failed_address); -static void memory_dump(udword *from, udword *to); - -extern byte _Stext[]; -extern byte _Edata[]; - -#ifdef USE_BAUDRATE_CHANGING -byte change_baudrate; -udword new_baudrate; -#endif - -void -level2_boot(void) -{ -#if USE_LEDS - REG_SET(R_PORT_PA_DATA, data_out, 0xaa); -#endif - -#if 0 - io_buf_next = (byte*)IO_BUF_START; - io_buf_cur = (byte*)IO_BUF_START; -#endif - -#if 1 - send_string("\r\n\r\nDevice ID = "); - send_hex(ntohl(tx_header.id), NL); - send_string(e100boot_version); -#endif - -#if 1 - { - udword sum = 0; - byte *b; - - for (b = (byte*)_Stext; b != (byte*)_Edata; b++) { - sum += *b; - } - send_string("Checksum of bootloader is "); - send_hex(sum, NL); - } -#endif - - read_load_info(); - - __asm__ volatile ("jump _start"); -} - -void -toggle_led(void) -{ -#if USE_LEDS - REG_SET(R_PORT_PA_DATA, data_out, 0x55); - - while (1) { - REG_SET(R_PORT_PA_DATA, data_out, ~REG_GET(R_PORT_PA_READ, data_in)); - { - volatile udword i; - - for (i = 0; i != 2000000; i++) - ; - } - } -#else - while (1) { - } -#endif -} - -void -read_load_info(void) -{ -#ifdef USE_BAUDRATE_CHANGING - change_baudrate = 0; -#endif - - send_string("Waiting for load info.\r\n"); - - send_ack(); - - read_file((byte*)IO_BUF_START, IO_BUF_END - IO_BUF_START - CRC_LEN); - send_string("Got load info.\r\n"); - decode_load_info(); - -#ifdef USE_BAUDRATE_CHANGING - if (change_baudrate) { - REG_WR(R_SERIAL0_BAUD, new_baudrate); - { - udword i = 0; - - while (i++ < 1000000) - ; - } - send_ack(); - } -#endif - - toggle_led(); -} - -void -decode_load_info(void) -{ - udword *type_p = (udword*)IO_BUF_START; - udword failed_address; - udword i; - command_T *cmd; - - while (type_p != (udword*)(IO_BUF_END - CRC_LEN)) { /* !!! */ -// send_hex(type_p, NL); - *type_p = ntohl(*type_p); -// send_hex(*type_p, NL); - type_p++; - } - -// memory_dump(IO_BUF_START, IO_BUF_END); - - cmd = (command_T*)IO_BUF_START; - while (cmd->type) { - switch (cmd->type) { - case PACKET_INFO: - send_string("PACKET_INFO\r\n"); - send_hex(cmd->args.packet_info.addr, NL); - send_hex(cmd->args.packet_info.size, NL); - - seq--; - send_ack(); - seq++; - - read_file((byte*)cmd->args.packet_info.addr, cmd->args.packet_info.size); - - (byte*)cmd += sizeof cmd->type + sizeof cmd->args.packet_info; - break; - - case SET_REGISTER: - send_string("SET_REGISTER\r\n"); - send_hex(cmd->args.set_register.addr, NL); - send_hex(cmd->args.set_register.val, NL); - - *(udword*)cmd->args.set_register.addr = cmd->args.set_register.val; - - (byte*)cmd += sizeof cmd->type + sizeof cmd->args.set_register; - break; - - case GET_REGISTER: - send_string("GET_REGISTER\r\n"); - send_hex(cmd->args.get_register.addr, NL); - send_hex(*(udword*)cmd->args.get_register.addr, NL); - - (byte*)cmd += sizeof cmd->type + sizeof cmd->args.get_register; - break; - - case PAUSE_LOOP: - send_string("PAUSE_LOOP\r\n"); - send_hex(cmd->args.pause_loop.pause, NL); - - for (i = cmd->args.pause_loop.pause; i; i--) - ; - - (byte*)cmd += sizeof cmd->type + sizeof cmd->args.pause_loop; - break; - - case MEM_VERIFY: - send_string("MEM_VERIFY\r\n"); - send_hex(cmd->args.mem_verify.addr, NL); - send_hex(cmd->args.mem_verify.val, NL); - - if (*(udword*)cmd->args.mem_verify.addr != cmd->args.mem_verify.val) { - send_string("verify failed\r\n"); - goto decode_failed; - } - - (byte*)cmd += sizeof cmd->type + sizeof cmd->args.mem_verify; - break; - - case MEM_TEST: - send_string("MEM_TEST\r\n"); - send_hex(cmd->args.mem_test.from, NL); - send_hex(cmd->args.mem_test.to, NL); - - if (!memory_test(cmd->args.mem_test.from, - cmd->args.mem_test.to, - &failed_address)) { - send_string("### Memory test failed at "); - send_hex(failed_address, NL); - memory_dump((udword*)DWORD_ALIGN(failed_address - 64), - (udword*)DWORD_ALIGN(failed_address + 64)); - goto decode_failed; - } - send_string("Passed memory test.\r\n"); - - (byte*)cmd += sizeof cmd->type + sizeof cmd->args.mem_test; - break; - - case MEM_DUMP: - send_string("MEM_DUMP\r\n"); - send_hex(cmd->args.mem_dump.from_addr, NL); - send_hex(cmd->args.mem_dump.to_addr, NL); - - memory_dump((udword*)cmd->args.mem_dump.from_addr, - (udword*)cmd->args.mem_dump.to_addr); - - (byte*)cmd += sizeof cmd->type + sizeof cmd->args.mem_dump; - break; - - case MEM_CLEAR: - send_string("MEM_CLEAR\r\n"); - send_hex(cmd->args.mem_clear.from_addr, NL); - send_hex(cmd->args.mem_clear.to_addr, NL); - - for (i = cmd->args.mem_clear.from_addr; - i <= cmd->args.mem_clear.to_addr; - i++) { - *(byte*)i = 0x00; - } - - (byte*)cmd += sizeof cmd->type + sizeof cmd->args.mem_clear; - break; - - case FLASH: - send_string("FLASH\r\n"); - send_hex((udword)cmd->args.flash.source, NL); - send_hex(cmd->args.flash.offset, NL); - send_hex(cmd->args.flash.size, NL); - - if ((i = flash_write(cmd->args.flash.source, - cmd->args.flash.offset, - cmd->args.flash.size)) != ERR_FLASH_OK) { - if (i == ERR_FLASH_VERIFY) { - udword size = - (cmd->args.flash.size < 65536 ? cmd->args.flash.size : 65536); - - /* Try to erase the first block(s) we tried to flash to prevent a - unit which failed to flash correctly from booting */ - flash_write(NULL, cmd->args.flash.offset, size); - } - - goto decode_failed; - } - - (byte*)cmd += sizeof cmd->type + sizeof cmd->args.flash; - break; - - case JUMP: -#if 1 - /* for the printf function in our libc */ - REG_WR(R_DMA_CH8_FIRST, *(udword*)&tx_header.dest[0]); - REG_WR(R_DMA_CH9_FIRST, *(uword*)&tx_header.dest[4]); -// REG_WR(R_NETWORK_SA_1, &tx_header.dest[4]); -// REG_WR(R_NETWORK_SA_2, tx_header.id); -#endif - send_string("JUMP\r\n"); - send_hex(cmd->args.jump.addr, NL); - send_string("END\r\n"); - - __asm__ volatile ("jump %0" :: "r" (cmd->args.jump.addr)); - - (byte*)cmd += sizeof cmd->type + sizeof cmd->args.jump; - break; - - case LOOP: - send_string("LOOP\r\n"); - send_hex(cmd->args.bne.addr, NL); - send_hex(cmd->args.bne.target, NL); - - if (*(udword*)cmd->args.bne.addr) { - (*(udword*)cmd->args.bne.addr)--; - (byte*)cmd = cmd->args.bne.target; - } - else { - (byte*)cmd += sizeof cmd->type + sizeof cmd->args.bne; - } - break; - -#ifdef USE_BAUDRATE_CHANGING - case BAUDRATE: - send_string("BAUDRATE\r\n"); - send_hex(cmd->args.br.baudrate, NL); - - new_baudrate = cmd->args.br.baudrate; - - (byte*)cmd += sizeof cmd->type + sizeof cmd->args.br; - break; -#endif - - default: - send_string("### Unknown type: "); - send_hex(cmd->type, NL); - - goto decode_failed; - break; - } - } - -decode_failed: - send_string("END\r\n"); -} - -void -read_file(byte* addr, udword size) -{ - udword nbr_read_last; - udword sum; - byte *b; - byte *from; - -/* send_string(">read_file\r\n"); */ - - nbr_read = 0; - nbr_read_last = 0; - target_address = (udword)addr; - - if (interface == NETWORK) { - rx_descr2.buf = (udword)addr; - bytes_to_read = size; - rx_descr2.sw_len = size + CRC_LEN > 1500 ? 1500 : size + CRC_LEN; -/* rx_descr2.sw_len = 1500; */ - - REG_SET(R_DMA_CH1_FIRST, first, (udword)&rx_descr); - - /* Restart receiver so descriptor is re-read. */ - REG_SET(R_DMA_CH1_CMD, cmd, reset); - while (REG_EQL(R_DMA_CH1_CMD, cmd, reset)) { - } - - REG_SET(R_DMA_CH1_CMD, cmd, start); - - while (1) { -/* send_hex(rx_descr2.hw_len, NL); */ - from = (byte*)rx_descr2.buf; - if (read_data()) { - if (nbr_read < size) { - REG_SET(R_DMA_CH1_CMD, cmd, start); - } - -#if USE_PRINT_DESCR - print_descr(&rx_descr); - print_descr(&rx_descr2); -#endif - -#if 0 - send_string("Read "); - send_hex(rx_descr2.hw_len - CRC_LEN, NO_NL); - send_string(" bytes. "); - send_hex((udword)from, NO_NL); - send_string(" - "); - send_hex(rx_descr2.buf-1, NO_NL); - send_string(" ("); - send_hex(nbr_read, NO_NL); - send_string("/"); - send_hex(size, NO_NL); - send_string(")\r\n"); -#endif - - nbr_read_last = nbr_read; -/* from = (byte*)rx_descr2.buf; */ - - if (nbr_read >= size) { - break; - } - } - } - } - else { /* interface != NETWORK */ - while (nbr_read < size) { - read_data(); - } - } - - sum = 0; - for (b = addr; b != (byte*)(addr+size); b++) { - sum += *b; - } - send_string("Checksum of file is "); - send_hex(sum, NL); - -/* memory_dump((udword*)addr, (udword*)addr+size); */ -/* send_string("ctrl, NL); - - send_string("sw_len : "); - send_hex(d->sw_len, NL); - - send_string("next : "); - send_hex(d->next, NL); - - send_string("buf : "); - send_hex(d->buf, NL); - - send_string("status : "); - send_hex(d->status, NL); - - send_string("hw_len : "); - send_hex(d->hw_len, NL); -} -#endif - -int -memory_test(udword from, udword to, udword *failed_address) -{ - udword i; - udword j; - byte b; - - /* At each dword (but bytewise) write the inverse of the adress, - check that it worked, then write the inverse of the last byte - written. Exit on fail. The memory after a successfull test will - be: - - 0xC0000000 : 0xC0000000 0xC0000004 0xC0000008 0xC000000C - 0xC0000010 : 0xC0000010 0xC0000014 0xC0000018 0xC000001C - */ - - for (i = from; i < to; i += 4) { - for (j = 0; (j != sizeof(udword)) && (i+j < to); j++) { - b = ((~i) >> (j*8)) & 0xff; - *(volatile byte*)(i+j) = b; - if (*(volatile byte*)(i+j) == b) { - *(volatile byte*)(i+j) = ~b; - } - else { - *failed_address = i+j; - send_string("### Memory test 1 failed at "); - send_hex(*failed_address, NL); - return FALSE; - } - } - } - - /* Run through entire region, check bytewise that the dwords contain - the address to the dword. Exit on fail. */ - - for (i = from; i < to; i += 4) { - for (j = 0; (j != sizeof(udword)) && (i+j < to); j++) { - b = (i >> (j*8)) & 0xff; - if (*(volatile byte*)(i+j) != b) { - *failed_address = i+j; - send_string("### Memory test 2 failed at "); - send_hex(*failed_address, NL); - return FALSE; - } - } - } - - return TRUE; -} - -void -memory_dump(udword *from, udword *to) -{ - udword *i = from; - int j; - - for (; i <= to; i += 4) { - send_hex((udword)i, NO_NL); - send_string(" :"); - for(j = 0; j != 4 && (i+j <= to); j++) { - send_string(" "); - send_hex(*(udword*)(i+j), NO_NL); - } - send_string("\r\n"); - } -} diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/src/common_init.c b/target/linux/etrax-2.6/image/e100boot/src/cbl/src/common_init.c deleted file mode 100644 index 8104a4df3f..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/cbl/src/common_init.c +++ /dev/null @@ -1,209 +0,0 @@ -/***************************************************************************** -*! -*! FILE NAME : common_init.c -*! -*! DESCRIPTION: This piece of code is loaded at bootstrap and is put in the -*! cache at 0x380000F0. Depending of how R_BUS_STATUS<2:1> is -*! set different kinds of bootstrap is performed. -*! -*! 00 - Normal boot. No bootstrap is performed and this code -*! is never loaded. -*! 01 - Serial boot. 784 bytes is loaded and execution starts -*! at 0x380000F0. -*! 11 - Parallel boot. 784 bytes is loaded and execution starts -*! at 0x380000F0. -*! 10 - Network boot. 1484 bytes is loaded and execution start -*! at 0x380000F4. -*! -*! --------------------------------------------------------------------------- -*! HISTORY -*! -*! DATE NAME CHANGES -*! ---- ---- ------- -*! 980326 Ronny Ranerup Initial version -*! Sep 20 1999 Jonas Dellenvall Added port3 debug support -*! 20020206 ronny Yeah, and I removed it again... -*! -*! --------------------------------------------------------------------------- -*! (C) Copyright 1998-2002, Axis Communications AB, LUND, SWEDEN -*!***************************************************************************/ - -/* - - Misc notes: - - It is very important to keep this file short. This and the boot - interface specific parts must fit into the first boot packet. - -*/ - -/****************** INCLUDE FILES SECTION ***********************************/ - -#include "hwregs.h" -#include "e100boot.h" - -/****************** CONSTANT AND MACRO SECTION ******************************/ - -/****************** TYPE DEFINITION SECTION *********************************/ - -/****************** LOCAL FUNCTION DECLARATION SECTION **********************/ - -static int timeout(void); - -/****************** GLOBAL VARIABLE DECLARATION SECTION *********************/ - -udword nbr_read; /* How many bytes has been read from current file */ -byte interface; /* Which I/O interface is the current one */ -byte set_dest; /* Have we set the destination address in tx_header */ -udword last_timeout; - -struct packet_header_T tx_header; -dma_descr_T tx_descr; /* For packet header */ -dma_descr_T tx_descr2; /* packet data */ - -struct packet_header_T rx_header; -dma_descr_T rx_descr; /* For packet header */ -dma_descr_T rx_descr2; /* packet data */ - -udword seq; /* Sequence number of next wanted packet */ -byte serial_up; - -/****************** LOCAL VARIABLE DECLARATION SECTION **********************/ - -/****************** FUNCTION DEFINITION SECTION *****************************/ - -void -crt1(void) -{ - /* Do this only once so we don't reset the timers and destroy the 32 - bit timer-register used as random number generator */ - - REG_SET__R_TIMER_CTRL( - timerdiv1, 0, - timerdiv0, 0, - presc_timer1, normal, - i1, clr, - tm1, run, - clksel1, cascade0, - presc_ext, prescale, - i0, clr, - tm0, run, - clksel0, c9600Hz); - - REG_SET__R_TIMER_CTRL( - timerdiv1, 0, - timerdiv0, 0, - presc_timer1, normal, - i1, nop, - tm1, run, - clksel1, cascade0, - presc_ext, prescale, - i0, nop, - tm0, run, - clksel0, c9600Hz); - - start(); -} - -void -start(void) -{ -#if USE_LEDS - REG_SET__R_PORT_PA_DIR( - dir7, output, - dir6, output, - dir5, output, - dir4, output, - dir3, output, - dir2, output, - dir1, output, - dir0, input); /* not for prodtest */ - - REG_SET__R_PORT_PA_DATA(data_out, 0); - - REG_SET__R_PORT_PB_DIR( - dir7, output, - dir6, output, - dir5, output, - dir4, output, - dir3, output, - dir2, output, - dir1, output, - dir0, output); - - REG_SET__R_PORT_PB_DATA(data_out, 0xff); -#endif - - /* We must initialize all (global) variables here, since the .data - and .bss area are used before they are loaded. */ - - //serial_up = FALSE; - nbr_read = 0; - - /* Get a random value to use as id. */ - tx_header.id = htonl(REG_RD(R_TIMER_DATA)); - - /* timer01 is used as timer. */ - last_timeout = REG_GET(R_TIMER01_DATA, count); - - interface = REG_GET(R_BUS_STATUS, boot) - 1; /* 0,1,2 */ - rx_descr2.status = 0; - - /* Initialize the boot interface */ - init_interface(); - send_ack(); /* Ack the first bootpacket, i.e. this code. seq 0. */ - - while (1) { - if (read_data()) { - if (nbr_read >= (udword)bytes_to_read) { - break; - } - else if (interface == NETWORK) { - REG_SET(R_DMA_CH1_CMD, cmd, start); - } - } - } - -#if USE_LEDS - REG_SET(R_PORT_PA_DATA, data_out, 0x55); -#endif - - level2_boot(); -} - -int -read_data(void) -{ - if (handle_read()) { - return TRUE; - } - - if (timeout()) { - send_ack(); - } - - return FALSE; -} - -int -timeout(void) -{ - volatile int now = REG_GET(R_TIMER01_DATA, count); - int elapsed; - int wait_time = 9600; - - elapsed = last_timeout - now; - - if (elapsed < 0) { - elapsed = -elapsed; - } - - if (elapsed > wait_time) { - last_timeout = now; - return TRUE; - } - - return FALSE; -} - -/****************** END OF FILE common_init.c *******************************/ diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/src/compiler.h b/target/linux/etrax-2.6/image/e100boot/src/cbl/src/compiler.h deleted file mode 100644 index 004d0d105c..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/cbl/src/compiler.h +++ /dev/null @@ -1,10 +0,0 @@ -#ifndef _COMPILER_H -#define _COMPILER_H - -typedef int dword; -typedef unsigned int udword; -typedef signed short word; -typedef unsigned short uword; -typedef unsigned char byte; - -#endif diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/src/crt0.S b/target/linux/etrax-2.6/image/e100boot/src/cbl/src/crt0.S deleted file mode 100644 index 466d19c7e1..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/cbl/src/crt0.S +++ /dev/null @@ -1,17 +0,0 @@ - .global crt0 ; Needed because of a bug in binutils - .global _target_address - .global _bytes_to_read - - .section .startup, "ax" - - nop - nop - - -crt0: - move.d 0x38001f00, sp - jump _crt1 - -_bytes_to_read: .dword 0x12345678 -_target_address: .dword 0x87654321 - diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/src/debug.h b/target/linux/etrax-2.6/image/e100boot/src/cbl/src/debug.h deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/src/e100boot.h b/target/linux/etrax-2.6/image/e100boot/src/cbl/src/e100boot.h deleted file mode 100644 index d9fea143a5..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/cbl/src/e100boot.h +++ /dev/null @@ -1,332 +0,0 @@ -/* $Id: e100boot.h,v 1.9 2003/12/16 09:04:07 magnusmn Exp $ */ - -#include "compiler.h" - -#define DMA_DESCR__out_priority__BITNR 5 -#define DMA_DESCR__out_priority__WIDTH 1 -#define DMA_DESCR__out_priority__normal 0 -#define DMA_DESCR__out_priority__high 1 - -#define DMA_DESCR__ecp_cmd__BITNR 4 -#define DMA_DESCR__ecp_cmd__WIDTH 1 -#define DMA_DESCR__ecp_cmd__normal 0 -#define DMA_DESCR__ecp_cmd__high 1 - -#define DMA_DESCR__tx_err__BITNR 4 -#define DMA_DESCR__tx_err__WIDTH 1 -#define DMA_DESCR__tx_err__enable 1 -#define DMA_DESCR__tx_err__disable 0 - -#define DMA_DESCR__intr__BITNR 3 -#define DMA_DESCR__intr__WIDTH 1 -#define DMA_DESCR__intr__enable 1 -#define DMA_DESCR__intr__disable 0 - -#define DMA_DESCR__wait__BITNR 2 -#define DMA_DESCR__wait__WIDTH 1 -#define DMA_DESCR__wait__enable 1 -#define DMA_DESCR__wait__disable 0 - -#define DMA_DESCR__eop__BITNR 1 -#define DMA_DESCR__eop__WIDTH 1 -#define DMA_DESCR__eop__enable 1 -#define DMA_DESCR__eop__disable 0 - -#define DMA_DESCR__eol__BITNR 0 -#define DMA_DESCR__eol__WIDTH 1 -#define DMA_DESCR__eol__enable 1 -#define DMA_DESCR__eol__disable 0 - -#define DMA_DESCR__sw_len__BITNR 0 -#define DMA_DESCR__sw_len__WIDTH 16 - -#define DMA_DESCR__next__BITNR 0 -#define DMA_DESCR__next__WIDTH 32 - -#define DMA_DESCR__buf__BITNR 0 -#define DMA_DESCR__buf__WIDTH 32 - -#define DMA_DESCR__fifo_len__BITNR 8 -#define DMA_DESCR__fifo_len__WIDTH 7 - -#define DMA_DESCR__crc_err__BITNR 7 -#define DMA_DESCR__crc_err__WIDTH 1 -#define DMA_DESCR__crc_err__enable 1 -#define DMA_DESCR__crc_err__disable 0 - -#define DMA_DESCR__align_err__BITNR 6 -#define DMA_DESCR__align_err__WIDTH 1 -#define DMA_DESCR__align_err__enable 1 -#define DMA_DESCR__align_err__disable 0 - -#define DMA_DESCR__in_priority__BITNR 5 -#define DMA_DESCR__in_priority__WIDTH 1 -#define DMA_DESCR__in_priority__high 1 -#define DMA_DESCR__in_priority__normal 0 - -#define DMA_DESCR__stop__BITNR 4 -#define DMA_DESCR__stop__WIDTH 1 - -#define DMA_DESCR__rd_eop__BITNR 1 -#define DMA_DESCR__rd_eop__WIDTH 1 - -#define DMA_DESCR__hw_len__BITNR 0 -#define DMA_DESCR__hw_len__WIDTH 16 - -#define SET_ETHER_ADDR(a0_0,a0_1,a0_2,a0_3,a0_4,a0_5,a1_0,a1_1,a1_2,a1_3,a1_4,a1_5) \ - *R_NETWORK_SA_0 = a0_0 | (a0_1 << 8) | (a0_2 << 16) | (a0_3 << 24); \ - *R_NETWORK_SA_1 = a0_4 | (a0_5 << 8) | (a1_0 << 16) | (a1_1 << 24); \ - *R_NETWORK_SA_2 = a1_2 | (a1_3 << 8) | (a1_4 << 16) | (a1_5 << 24); - -#define DWORD_ALIGN(x) ((x) & 0xfffffffc) - -#define CRC_LEN 4 - -#define TRUE 1 -#define FALSE 0 - -#define NL 1 -#define NO_NL 0 - -#define SERIAL 0 -#define NETWORK 1 -#define PARALLEL 2 - -#define STRING 0 -#define INT 1 -#define ACK 2 -#define BOOT_PACKET 3 -#define BOOT_CMDS 4 -#define NET_INT 5 -#define NET_INT_NL 6 - -#define JUMP 1 -#define MEM_TEST 2 -#define PACKET_INFO 3 -#define SET_REGISTER 4 -#define GET_REGISTER 5 -#define MEM_DUMP 6 -#define MEM_CLEAR 7 -#define MEM_VERIFY 8 -#define FLASH 9 -#define PAUSE_LOOP 10 -#define LOOP 11 -#define BAUDRATE 12 - -#define ERR_FLASH_OK 0 -#define ERR_FLASH_NONE 1 -#define ERR_FLASH_TOO_SMALL 2 -#define ERR_FLASH_VERIFY 3 -#define ERR_FLASH_ERASE 4 - -#define TIMEOUT_LIMIT ( ((6250 * 1000) / 0xffff) / 2) - -#define TX_CTRL_EOP \ -(IO_STATE(DMA_DESCR, intr, disable) |\ - IO_STATE(DMA_DESCR, wait, enable) |\ - IO_STATE(DMA_DESCR, eop, enable) |\ - IO_STATE(DMA_DESCR, eol, enable)) - -#define TX_CTRL \ - (IO_STATE(DMA_DESCR, intr, disable) |\ - IO_STATE(DMA_DESCR, wait, disable) |\ - IO_STATE(DMA_DESCR, eop, disable) |\ - IO_STATE(DMA_DESCR, eol, disable)) - -#define LOAD_ADDRESS 0x38001000 -#define SIZEOF_BOOT_LEVEL_1 2048 - -/* This is where the commands are transfered to. */ -#define IO_BUF_START 0x38001f00 -#define IO_BUF_END 0x380020f0 /* bootcode start + cache size */ - -/* This should only be used in the cbl, but if we compile the sbl for - * elinux then __CRIS__ will be defined, and these are already defined - * in uC-libc. Check that __linux__ is not defined as well! - */ - -#if defined(__CRIS__) && !defined(__linux__) -#define NULL ((void*)0) - -static inline udword -htonl(udword x) -{ - __asm__ ("swapwb %0" : "=r" (x) : "0" (x)); - - return(x); -} -#ifndef ntohl -#define ntohl(x) htonl(x) -#endif - -static inline uword -htons(uword x) -{ - __asm__ ("swapb %0" : "=r" (x) : "0" (x)); - - return(x); -} -#ifndef ntohs -#define ntohs(x) htons(x) -#endif -#endif - -/*#define ntohs(x) \*/ -/*((unsigned short)((((unsigned short)(x) & 0x00ffU) << 8) | \*/ -/* (((unsigned short)(x) & 0xff00U) >> 8)))*/ -/* */ - -/*#define ntohl(x) \*/ -/*((unsigned long int)((((unsigned long int)(x) & 0x000000ffU) << 24) | \*/ -/* (((unsigned long int)(x) & 0x0000ff00U) << 8) | \*/ -/* (((unsigned long int)(x) & 0x00ff0000U) >> 8) | \*/ -/* (((unsigned long int)(x) & 0xff000000U) >> 24)))*/ - -struct packet_header_T /* Size = 38 */ -{ - byte dest[6]; - byte src[6]; - uword length; - udword snap1; - udword snap2; - udword tag; - udword seq; - udword type; - udword id; -} __attribute__ ((packed)); - -typedef struct dma_descr_T { - uword sw_len; /* 0-1 */ - uword ctrl; /* 2-3 */ - udword next; /* 4-7 */ - udword buf; /* 8-11 */ - uword hw_len; /* 12-13 */ - uword status; /* 14-15 */ -} dma_descr_T; - -typedef struct packet_info_T { - udword addr; - udword size; -} packet_info_T; - -typedef struct set_register_T { - udword addr; - udword val; -} set_register_T; - -typedef struct get_register_T { - udword addr; -} get_register_T; - -typedef struct pause_loop_T { - udword pause; -} pause_loop_T; - -typedef struct mem_verify_T { - udword addr; - udword val; -} mem_verify_T; - -typedef struct mem_test_T { - udword from; - udword to; -} mem_test_T; - -typedef struct mem_dump_T { - udword from_addr; - udword to_addr; -} mem_dump_T; - -typedef struct mem_clear_T { - udword from_addr; - udword to_addr; -} mem_clear_T; - -typedef struct flash_T { - unsigned char *source; - udword offset; - udword size; -} flash_T; - -typedef struct jump_T { - udword addr; -} jump_T; - -typedef struct bne_T { - udword addr; - udword target; -} bne_T; - -typedef struct br_T { - udword baudrate; -} br_T; - -typedef struct command_T { - udword type; - union { - packet_info_T packet_info; - set_register_T set_register; - get_register_T get_register; - pause_loop_T pause_loop; - mem_verify_T mem_verify; - mem_test_T mem_test; - mem_dump_T mem_dump; - mem_clear_T mem_clear; - flash_T flash; - jump_T jump; - bne_T bne; - br_T br; - } args; -} command_T; - -#define NETWORK_HEADER_LENGTH sizeof(struct packet_header_T) - -void crt1(void); -void start(void); -void level2_boot(void); -int read_data(void); -int handle_network_read(void); -int flash_write(const unsigned char *source, unsigned int offset, unsigned int size); - -void init_interface(void); -int handle_read(void); -void send_ack(void); -void send_string(char *str); -void send_hex(udword v, byte nl); - -extern char e100boot_version[]; - -extern volatile udword bytes_to_read; -extern volatile udword target_address; - -extern udword nbr_read; -extern byte interface; -extern byte set_dest; -extern udword last_timeout; -extern byte *io_buf_next; -extern byte *io_buf_cur; - -extern struct packet_header_T tx_header; -extern dma_descr_T tx_descr; -extern dma_descr_T tx_descr2; - -extern struct packet_header_T rx_header; -extern dma_descr_T rx_descr; -extern dma_descr_T rx_descr2; - -extern uword timeout_limit; -extern udword seq; -extern byte serial_up; - -enum { /* Available in: */ - d_eol = (1 << 0), /* flags */ - d_eop = (1 << 1), /* flags & status */ - d_wait = (1 << 2), /* flags */ - d_int = (1 << 3), /* flags */ - d_txerr = (1 << 4), /* flags */ - d_stop = (1 << 4), /* status */ - d_ecp = (1 << 4), /* flags & status */ - d_pri = (1 << 5), /* flags & status */ - d_alignerr = (1 << 6), /* status */ - d_crcerr = (1 << 7) /* status */ -}; diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/src/flash.c b/target/linux/etrax-2.6/image/e100boot/src/cbl/src/flash.c deleted file mode 100644 index 892e98ad75..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/cbl/src/flash.c +++ /dev/null @@ -1,1125 +0,0 @@ -/* $Id: flash.c,v 1.39 2004/04/20 07:57:57 jonashg Exp $ - * - * Stolen from the eLinux kernel and stripped down. - * - * HISTORY: - * - * $Log: flash.c,v $ - * Revision 1.39 2004/04/20 07:57:57 jonashg - * Clear flash_status fields to make it possible to flash several images - * sequentially. - * - * Revision 1.38 2003/12/16 09:04:07 magnusmn - * Removed FLASHFILL command - * - * Revision 1.37 2003/12/16 08:49:01 magnusmn - * Merging change_branch--fast_flash - * - * Revision 1.36.2.6 2003/12/15 17:21:27 magnusmn - * Reset counter when continuing with operations the next sector. - * - * Revision 1.36.2.5 2003/12/15 11:35:57 magnusmn - * Bail out if we try to erase the same sector more that 10 times - * - * Revision 1.36.2.4 2003/12/12 12:07:10 magnusmn - * FIX for ST M29W320DT - * Some chip need a reset to bring them back to read mode again. - * - * Revision 1.36.2.3 2003/11/10 16:38:04 orjanf - * Unified Erasing/Writing messages - * - * Revision 1.36.2.2 2003/11/10 15:52:34 magnusmn - * More info on a sector basis - * - * Revision 1.36.2.1 2003/11/07 16:23:20 magnusmn - * o Only erase a flash sector if we need to, that is if the source content isn't already is in place. - * o Don't erase a flash sector that already contain ones. - * o Don't write ones to a (d)word that already contain ones. - * o If there are two flashes, switch flash after an erase operation is started on one of them. - * o Flash fill doesn't work yet. - * o No timeout implemented, we will continue to erase/program until we succeed. - * o Interleave not tested. - * - * Revision 1.36 2003/10/16 17:08:51 jonashg - * Bugfix: reversed CFI-tables wasn't handled correctly since regions support was - * merged. - * - * Revision 1.35 2003/10/14 13:43:41 pkj - * Fixed compiler warnings. - * - * Revision 1.34 2003/10/14 10:48:13 magnusmn - * No need to write ones to a (d)word where there already are ones. This will save time during flash programming. - * - * Revision 1.33 2003/10/10 11:46:25 jonashg - * Merged change_branch--regions_support. - * - * Revision 1.32.2.3 2003/10/10 09:38:13 jonashg - * Corrected calculation of current region and sector before erase. - * - * Revision 1.32.2.2 2003/10/09 16:31:26 jonashg - * Regions support in JEDEC probe. - * - * Revision 1.32.2.1 2003/09/19 15:28:22 jonashg - * Support for unusual region layouts. It only works for CFI compliant chips (yet). - * - * Revision 1.32 2002/12/13 15:55:54 jonashg - * Fix for ST M29W160ET. It seems to need a reset before erase (even though the - * probe functions did reset it). - * - * Revision 1.31 2002/07/01 14:37:25 pkj - * Merged with the ASIC version of e100boot. Main difference is that - * information about the executed commands are sent back to e100boot - * instead of being sent to the debug port. This means there is no - * longer any need to use different boot loaders for different - * debug ports. - * - * Revision 1.30 2002/06/26 13:28:29 pkj - * flash_write() can now be used to erase an area (by specifying - * source as NULL), and to fill an area with the first udword of - * source by setting do_fill to TRUE). - * - * Revision 1.29 2002/06/26 13:19:37 pkj - * * flash_write() now returns a status code. - * * timeout is now decremented correctly in flash_write_part() to - * actually be able to trigger the timeout message. - * * Fixed all compiler warnings. - * - * Revision 1.28 2002/06/20 12:58:18 pkj - * Changed svinto_boot.h to e100boot.h - * - * Revision 1.27 2002/06/19 14:00:29 pkj - * * Broke out the probing of the flash chips from flash_write() - * into flash_probe_chips(). - * * flash_probe_chips() is not limited to two chips or that the - * first chip exists. - * - * Revision 1.26 2002/02/21 14:37:52 jonashg - * Optimized away my sanity. It's back now I think. - * - * Revision 1.25 2002/02/21 14:28:24 jonashg - * Added support for Atmel AT49?V16?T (had to optimize a bit to make room). - * - * Revision 1.24 2002/01/31 14:36:14 jonashg - * * Added support for Atmel AT49[BL]V16[01] (the chip used in the ETRAX MCM). - * * Replaced concurrent sector erase with sequential (we have found three - * different chips that cannot erase multiple sectors at the same time, - * one of the is the chip in the MCM). I haven't noticed any performance - * loss on chips (CFI and non-CFI) that can erase all sectors at the same - * time either (maybe they don't really erase them at the same time in - * hardware). - * * Added check for manufacturer id as well as device id (should have been - * done a long time ago). - * - * Revision 1.23 2001/11/21 15:52:44 jonashg - * Almost readable. - * - * Revision 1.22 2001/11/21 15:24:38 jonashg - * Increased readability and decreased size some 40bytes. - * - * Revision 1.21 2001/11/20 13:40:12 starvik - * Corrected handling for CFI capable bottom boot flashes - * Shorted some strings to make more space available - * - * Revision 1.20 2001/08/08 17:51:28 pkj - * Made it possible to flash at a start offset other than zero when - * there are more than one physical flash chip available. Previously - * it always started flashing from the start of the first flash if - * there were more than one, even though the start offset was set to - * something else... - * - * Revision 1.19 2001/06/19 14:51:17 jonashg - * Added support for non-CFI flash Toshiba TC58FVT800. - * - * Revision 1.18 2001/04/05 06:32:39 starvik - * Works with flashes with multiple banks - * - * Revision 1.17 2001/03/06 15:21:16 jonashg - * More output to user. - * - * Revision 1.16 2001/03/06 14:11:16 jonashg - * * Switch to second device correctly when flashing images that extend past the - * first device. - * * Only enter autoselect mode once saves a few bytes (not needed before reading - * device id, since it was done before reading manufacturer id). - * * A few unnecessary resets removed to save another few bytes. - * - * Revision 1.15 2001/02/28 14:52:43 jonashg - * * Reverted to old sector erase sequence (that was correct). - * * A bit of executable size optimization (a few hundred bytes). - * * Cleanup. - * - * Revision 1.14 2001/02/27 14:18:59 jonashg - * * Write full erase command sequence to all sectors that should be erased. - * * Write 16bit erase command to non-interleaved chips. - * - * Revision 1.13 2001/02/23 11:03:41 jonashg - * Added support for 2 x 16Mb flashes (32-bits buswidth). - * The CFI probe does not detect two parallel flash devices, but the normal - * probe does (it should be easy to add that in the CFI-probe, but I didn't - * have any hardware to try it on and the size of the executable is getting - * pretty close to the size of the ETRAX cache). - * - * Revision 1.12 2001/02/12 13:59:00 jonashg - * Bugfix: pointer arithmetics made bootsector calculation go wrong. - * - * Revision 1.11 2000/11/10 08:02:23 starvik - * Added CFI support - * - * Revision 1.10 2000/10/26 13:47:32 johana - * Added support for Fujitsu flash 16MBit (2MByte) MBM29LV160BE and MBM29LV160TE. - * NOT VERIFIED YET! - * - * Revision 1.9 2000/06/28 13:02:50 bjornw - * * Added support for SST39LF800 and SST39LF160 flashes - * * Fixed some indentation issues - * - * Revision 1.8 2000/06/13 11:51:11 starvik - * Support for two flashes. Second flash is erased and programmed if program - * is larger than first flash. - * - * Revision 1.7 2000/04/13 16:06:15 macce - * See if flash is empty before erasing it. Might save some production time. - * - * Revision 1.6 2000/01/27 17:52:07 bjornw - * * Added Toshiba flashes - * * Added proper bootblock erase for the different flashes - * (this caused the verify errors when trying to do ./flashitall before) - * - * Revision 1.5 2000/01/20 11:41:28 finn - * Improved the verify error printouts in flash_write. - * - * Revision 1.4 1999/12/21 19:32:53 bjornw - * Dont choke on full chip erases even though we dont implement it efficiently. - * - * Revision 1.3 1999/11/12 01:30:04 bjornw - * Added wait for busy to be ready. Removed some warnings. - * - * Revision 1.2 1999/10/27 07:42:42 johana - * Added support for ST M29W800T flash used in 5600 - * - * Revision 1.1 1999/10/27 01:37:12 bjornw - * Wrote routines to erase and flash data into a flash ROM. - * - */ - -#include "e100boot.h" - -//#define DEBUG - -#ifdef DEBUG -#define FDEBUG(x) x -#else -#define FDEBUG(x) -#endif - -/* Try turning of some of these if you run into space problems. */ -#define CFI_PROBE -#define JEDEC_PROBE -#define INTERLEAVE - -#define TYPE_X16 (16 / 8) - -#define nop() __asm__("nop") - -#define safe_printk send_string - -static char *message_bottom_boot_8 = "8Mb BB"; -static char *message_top_boot_8 = "8Mb TB"; -static char *message_bottom_boot_16 = "16Mb BB"; -static char *message_top_boot_16 = "16Mb TB"; -static char *message_top_boot_32 = "32Mb TB"; - -enum { - /* Addresses */ - ADDR_UNLOCK_1 = 0x0555, - ADDR_UNLOCK_2 = 0x02AA, - ADDR_MANUFACTURER = 0x0000, - ADDR_DEVICE_ID = 0x0001, - ADDR_CFI_QUERY = 0x0055, - - /* Commands */ - CMD_UNLOCK_DATA_1 = 0x00AA, - CMD_UNLOCK_DATA_2 = 0x0055, - CMD_MANUFACTURER_UNLOCK_DATA = 0x0090, - CMD_PROGRAM_UNLOCK_DATA = 0x00A0, - CMD_RESET_DATA = 0x00F0, - CMD_SECTOR_ERASE_UNLOCK_DATA_1 = 0x0080, - CMD_SECTOR_ERASE_UNLOCK_DATA_2 = 0x0030, - CMD_CFI_QUERY_DATA = 0x0098, - - /* Offsets */ - OFFSET_CFI_ID = 0x10, - OFFSET_CFI_SIZE = 0x27, - OFFSET_CFI_BLOCK_COUNT = 0x2C, - OFFSET_CFI_BLOCK = 0x2D, - - /* Manufacturers */ - MANUFACTURER_AMD = 0x01, - MANUFACTURER_ATMEL = 0x1F, - MANUFACTURER_FUJITSU = 0x04, - MANUFACTURER_SST = 0xBF, - MANUFACTURER_ST = 0x20, - MANUFACTURER_TOSHIBA = 0x98, - - - /* To save precious space we store mfr and dev id together */ - - /* AMD devices */ - AM29F800BB = 0x00012258, - AM29F800BT = 0x000122D6, - AM29LV800BB = 0x0001225B, - AM29LV800BT = 0x000122DA, - AM29LV160BT = 0x000122C4, - - /* Atmel devices */ - AT49xV16x = 0x001F00C0, - AT49xV16xT = 0x001F00C2, - AT49BV32xAT = 0x001F00C9, - - /* Fujitsu devices */ - MBM29LV160TE = 0x000422C4, - MBM29LV160BE = 0x00042249, - - /* SST devices */ - SST39LF800 = 0x00BF2781, - SST39LF160 = 0x00BF2782, - - /* ST devices */ - M29W800T = 0x002000D7, /* Used in 5600, similar - * to AM29LV800, but no - * unlock bypass - */ - /* Toshiba devices */ - TC58FVT160 = 0x009800C2, - TC58FVB160 = 0x00980043, - TC58FVT800 = 0x0098004F, - - /* Toggle bit mask */ - D6_MASK = 0x40 -}; - -struct region { - unsigned long offset; - unsigned int sector_size; - unsigned int numsectors; -}; - -#define MAXREGIONS 8 - -struct chip { - volatile unsigned char *base; -#ifdef INTERLEAVE - byte interleave; - byte buswidth; -#endif - unsigned int size; - unsigned short numregions; - struct region regions[MAXREGIONS]; -}; - -/* Allocate flash structures and initialize base. */ -static struct chip chips[2] = { - { (unsigned char *)0x80000000, -#ifdef INTERLEAVE - 0, 0, -#endif - 0, 0, { } }, - { (unsigned char *)0x84000000, -#ifdef INTERLEAVE - 0, 0, -#endif - 0, 0, { } } -}; - - - -static unsigned int -wide_read(struct chip *flash, unsigned long offset) -{ -#ifdef INTERLEAVE - switch (flash->buswidth) { - case 2: -#endif - return *((uword *)(flash->base + offset)); - -#ifdef INTERLEAVE - case 4: - return *((udword *)(flash->base + offset)); - } - - return 0; -#endif -} - -static int -wide_write_chunk(struct chip *flash, unsigned long offset, const void *chunk) -{ -#ifdef INTERLEAVE - switch (flash->buswidth) { - case 2: -#endif - *((uword *)(flash->base + offset)) = *((uword *)chunk); - return 2; - -#ifdef INTERLEAVE - case 4: - *((udword *)(flash->base + offset)) = *((udword *)chunk); - return 4; - } - - return 0; -#endif -} - -static void -wide_cmd(struct chip *flash, udword cmd, unsigned long offset) -{ -#ifdef INTERLEAVE - if (flash->interleave == 1) { -#endif - offset <<= 1; -#ifdef INTERLEAVE - } else if (flash->interleave == 2) { - cmd |= (cmd << 16); - offset <<= 2; - } else { - safe_printk("Unsupported interleave!\n"); - return; - } -#endif - - wide_write_chunk(flash, offset, &cmd); -} - -static void -flash_unlock(struct chip *flash) -{ - wide_cmd(flash, CMD_UNLOCK_DATA_1, ADDR_UNLOCK_1); - wide_cmd(flash, CMD_UNLOCK_DATA_2, ADDR_UNLOCK_2); -} - -static int -flash_is_busy(struct chip *flash, unsigned long offset) -{ -#ifdef INTERLEAVE - if (flash->interleave == 2) { - udword read1, read2; - - read1 = wide_read(flash, offset); - read2 = wide_read(flash, offset); - return (((read1 >> 16) & D6_MASK) != - ((read2 >> 16) & D6_MASK)) || - (((read1 & 0xffff) & D6_MASK) != - ((read2 & 0xffff) & D6_MASK)); - } -#endif - - return ((wide_read(flash, offset) & D6_MASK) != - (wide_read(flash, offset) & D6_MASK)); -} - - - -#ifdef CFI_PROBE -static int -try_cfi(struct chip *flash) -{ - int offset_shift = 1; - -#ifdef INTERLEAVE - if (flash->interleave == 2) { - offset_shift = 2; - } -#endif - - /* Enter CFI mode */ - wide_cmd(flash, CMD_CFI_QUERY_DATA, ADDR_CFI_QUERY); - - /* Check if flash responds correctly */ - if ((byte)wide_read(flash, (OFFSET_CFI_ID+0) << offset_shift) == 'Q' && - (byte)wide_read(flash, (OFFSET_CFI_ID+1) << offset_shift) == 'R' && - (byte)wide_read(flash, (OFFSET_CFI_ID+2) << offset_shift) == 'Y') { - int block; /* Current block */ - int block_count; /* Number of blocks */ - unsigned int offset = 0; /* Offset into flash */ - int reverse = 0; /* Reverse block table */ - int primary; /* Offset to vendor specific table */ - - safe_printk("Found 1 x CFI at "); - send_hex((udword)flash->base, NL); - - flash->size = - 1 << wide_read(flash, OFFSET_CFI_SIZE << offset_shift); - - /* CFI stores flash organization in blocks. Each block contains - * a number of sectors with the same size - */ - block_count = wide_read(flash, OFFSET_CFI_BLOCK_COUNT << - offset_shift); - - /* Check if table is reversed */ - primary = wide_read(flash, (OFFSET_CFI_ID+5) << offset_shift); - /* For CFI version 1.0 we don't know. Assume that id & 0x80 */ - /* indicates top boot */ - if ((byte)wide_read(flash, (primary+4) << offset_shift) == 0x30) - { - /* read device id */ - wide_cmd(flash, CMD_RESET_DATA, ADDR_UNLOCK_1); - flash_unlock(flash); - wide_cmd(flash, CMD_MANUFACTURER_UNLOCK_DATA, - ADDR_UNLOCK_1); - reverse = wide_read(flash, ADDR_DEVICE_ID * TYPE_X16 -#ifdef INTERLEAVE - * flash->interleave -#endif - ) & 0x80; - wide_cmd(flash, CMD_CFI_QUERY_DATA, ADDR_CFI_QUERY); - } else { - reverse = ((byte)wide_read(flash, - (primary+15) << offset_shift) == 3); - } - - flash->numregions = block_count; - if (block_count > MAXREGIONS) { - safe_printk("Too many regions on chip!\n"); - return 0; - } - - /* Blocks are stored backwards compared to flash organization */ - for (block = reverse ? block_count - 1 : 0; - reverse ? block >= 0 : block < block_count; - reverse ? block-- : block++) { - int region; - - /* Size of each sector in block. Size is stored as - * sector_size / 256. - */ - int sector_size = - (wide_read(flash, (OFFSET_CFI_BLOCK+block * 4+2) << - offset_shift) - | - (wide_read(flash, (OFFSET_CFI_BLOCK+block * 4+3) << - offset_shift) << 8) - ) << 8; - - /* Number of sectors */ - int sector_count = - (wide_read(flash, (OFFSET_CFI_BLOCK+block * 4+0) << - offset_shift) - | - (wide_read(flash, (OFFSET_CFI_BLOCK+block * 4+1) << - offset_shift) << 8) - ) + 1; - - region = reverse? block_count - 1 - block : block; - flash->regions[region].offset = offset; - flash->regions[region].sector_size = sector_size; - flash->regions[region].numsectors = sector_count; - - /* Can't use multiplication (we have no lib). */ - { - int temp; - for (temp = 0 ; temp < sector_count ; temp++) { - offset += sector_size; - } - } - -FDEBUG( - if (reverse) { - safe_printk("NOTE! reversed table:\n"); - } - safe_printk("region: "); - send_hex((udword)region, NL); - safe_printk(" offset: "); - send_hex((udword)flash->regions[region].offset, NL); - safe_printk(" sector_size: "); - send_hex((udword)flash->regions[region].sector_size, NL); - safe_printk(" numsectors: "); - send_hex((udword)flash->regions[region].numsectors, NL); -) - - /* Some flashes (SST) store information about alternate - * block sizes. Ignore those by breaking when the sum - * of the sector sizes == flash size. - */ - if (offset == flash->size) { - break; - } - } - - /* reset */ - wide_cmd(flash, CMD_RESET_DATA, ADDR_UNLOCK_1); - - return 1; - } - - /* reset */ - wide_cmd(flash, CMD_RESET_DATA, ADDR_UNLOCK_1); - - return 0; -} -#endif - - - -static int -flash_probe(struct chip *flash) -{ - char *message; - udword dev_id; - udword mfr_id; - udword id; - - if (flash->size -#ifdef CFI_PROBE - || try_cfi(flash) -#endif - ) { - return 1; - } - -#ifdef JEDEC_PROBE - /* Read manufacturer ID. */ - flash_unlock(flash); - wide_cmd(flash, CMD_MANUFACTURER_UNLOCK_DATA, ADDR_UNLOCK_1); - mfr_id = wide_read(flash, ADDR_MANUFACTURER * TYPE_X16 -#ifdef INTERLEAVE - * flash->interleave -#endif - ); - /* Read device ID. */ - dev_id = wide_read(flash, ADDR_DEVICE_ID * TYPE_X16 -#ifdef INTERLEAVE - * flash->interleave -#endif - ); -FDEBUG( - safe_printk("mfr_id: "); - send_hex(mfr_id, NL); - safe_printk("dev_id: "); - send_hex(dev_id, NL); -) - -#ifdef INTERLEAVE - if ((flash->interleave == 2) && - ((mfr_id >> 16) == (mfr_id & 0xffff)) && - ((dev_id >> 16) == (dev_id & 0xffff))) { - mfr_id &= 0xffff; - dev_id &= 0xffff; - } -#endif - - id = (mfr_id << 16) | dev_id; - - /* reset */ - wide_cmd(flash, CMD_RESET_DATA, ADDR_UNLOCK_1); - - /* Check device type and fill in correct sizes. */ - switch (id) { - case AM29LV160BT: - case TC58FVT160: - // case MBM29LV160TE: /* This is same id as AM29LV160BT */ - message = message_top_boot_16; - - flash->size = 0x00200000; - - flash->regions[0].offset = 0x00000000; - flash->regions[0].sector_size = 0x10000; - flash->regions[0].numsectors = 31; - - flash->regions[1].offset = 0x001F0000; - flash->regions[1].sector_size = 0x08000; - flash->regions[1].numsectors = 1; - - flash->regions[2].offset = 0x001F8000; - flash->regions[2].sector_size = 0x02000; - flash->regions[2].numsectors = 2; - - flash->regions[3].offset = 0x001FC000; - flash->regions[3].sector_size = 0x04000; - flash->regions[3].numsectors = 1; - break; - - // case AM29LV160BB: - case TC58FVB160: - case MBM29LV160BE: - message = message_bottom_boot_16; - - flash->size = 0x00200000; - - flash->regions[0].offset = 0x00000000; - flash->regions[0].sector_size = 0x04000; - flash->regions[0].numsectors = 1; - - flash->regions[1].offset = 0x00004000; - flash->regions[1].sector_size = 0x02000; - flash->regions[1].numsectors = 2; - - flash->regions[2].offset = 0x00008000; - flash->regions[2].sector_size = 0x08000; - flash->regions[2].numsectors = 1; - - flash->regions[3].offset = 0x00010000; - flash->regions[3].sector_size = 0x10000; - flash->regions[3].numsectors = 31; - break; - - case AM29LV800BB: - case AM29F800BB: - message = message_bottom_boot_8; - - flash->size = 0x00100000; - - flash->regions[0].offset = 0x00000000; - flash->regions[0].sector_size = 0x04000; - flash->regions[0].numsectors = 1; - - flash->regions[1].offset = 0x00004000; - flash->regions[1].sector_size = 0x02000; - flash->regions[1].numsectors = 2; - - flash->regions[2].offset = 0x00008000; - flash->regions[2].sector_size = 0x08000; - flash->regions[2].numsectors = 1; - - flash->regions[3].offset = 0x00010000; - flash->regions[3].sector_size = 0x10000; - flash->regions[3].numsectors = 15; - break; - - case M29W800T: - case AM29LV800BT: - case AM29F800BT: - case TC58FVT800: - message = message_top_boot_8; - - flash->size = 0x00100000; - - flash->regions[0].offset = 0x00000000; - flash->regions[0].sector_size = 0x10000; - flash->regions[0].numsectors = 15; - - flash->regions[1].offset = 0x000F0000; - flash->regions[1].sector_size = 0x08000; - flash->regions[1].numsectors = 1; - - flash->regions[2].offset = 0x000F8000; - flash->regions[2].sector_size = 0x02000; - flash->regions[2].numsectors = 2; - - flash->regions[3].offset = 0x000FC000; - flash->regions[3].sector_size = 0x04000; - flash->regions[3].numsectors = 1; - - break; - - case AT49xV16x: - message = message_bottom_boot_16; - - flash->size = 0x00200000; - - flash->regions[0].offset = 0x00000000; - flash->regions[0].sector_size = 0x02000; - flash->regions[0].numsectors = 8; - - flash->regions[1].offset = 0x00010000; - flash->regions[1].sector_size = 0x10000; - flash->regions[1].numsectors = 31; - - break; - - case AT49xV16xT: - message = message_top_boot_16; - - flash->size = 0x00200000; - - flash->regions[0].offset = 0x00000000; - flash->regions[0].sector_size = 0x10000; - flash->regions[0].numsectors = 31; - - flash->regions[1].offset = 0x001F0000; - flash->regions[1].sector_size = 0x02000; - flash->regions[1].numsectors = 8; - - break; - - case AT49BV32xAT: - message = message_top_boot_32; - - flash->size = 0x00400000; - - flash->regions[0].offset = 0x00000000; - flash->regions[0].sector_size = 0x10000; - flash->regions[0].numsectors = 63; - - flash->regions[1].offset = 0x001F0000; - flash->regions[1].sector_size = 0x02000; - flash->regions[1].numsectors = 8; - - break; - - default: -#endif -#ifdef INTERLEAVE - if (flash->interleave == 1) { -#endif - safe_printk("No single x16 at "); -#ifdef INTERLEAVE - } else { - safe_printk("No interleaved x16 at "); - } -#endif - send_hex((udword)flash->base, NL); - - return 0; -#ifdef JEDEC_PROBE - } - - safe_printk("Found "); -#ifdef INTERLEAVE - if (flash->interleave == 1) { -#endif - safe_printk("1"); -#ifdef INTERLEAVE - } - if (flash->interleave == 2) { - int count = 0; - - flash->size <<= 1; - while (count < MAXREGIONS) { - flash->regions[count].offset <<= 1; - flash->regions[count].sector_size <<= 1; - count++; - } - safe_printk("2"); - } -#endif - safe_printk(" x "); - safe_printk(message); - safe_printk(" at "); - send_hex((udword)flash->base, NL); - - return 1; -#endif -} - -/* Start erase of a sector but do no wait for completion */ -static void -start_sector_erase(struct chip *flash, unsigned long offset) -{ - flash_unlock(flash); - wide_cmd(flash, CMD_SECTOR_ERASE_UNLOCK_DATA_1, ADDR_UNLOCK_1); - flash_unlock(flash); - -#ifdef INTERLEAVE - if (flash->interleave == 2) { - *(udword *)(flash->base+offset) = (CMD_SECTOR_ERASE_UNLOCK_DATA_2 << 16) | - CMD_SECTOR_ERASE_UNLOCK_DATA_2; - } else { -#endif - *(uword *)(flash->base+offset) = CMD_SECTOR_ERASE_UNLOCK_DATA_2; -#ifdef INTERLEAVE - } -#endif -} - -/* Return the size of the sector at the given offset */ -static int -find_sector_size(struct chip *flash, unsigned long offset) -{ - unsigned int i, j; - int region_size; - /* Sanity check */ - if (offset >= flash->size) - return 0; - - for(i=0; i < MAXREGIONS; i++) - if (offset >= flash->regions[i].offset) { - region_size=0; - for (j=0; j < flash->regions[i].numsectors; j++) - region_size += flash->regions[i].sector_size; - if (offset < flash->regions[i].offset + region_size) - return flash->regions[i].sector_size; - } - - /* Should not happen */ - return 0; -} - -/* Check and see if we need to erase the sector */ -/* The return values mean */ -/* 0: The source and destination are the same. */ -/* 1: The source and destination are not the same, but flash sector already contains only ones. */ -/* 2: The source and destination are not the same and the flash sector is tainted by some zeroes. */ -static char -need_to_erase(struct chip *flash, unsigned long offset, const unsigned char *source, int size) -{ - int i; - unsigned long j; - - for (i = 0; i < size; i+=2) - if (*(uword*)(flash->base + i + offset) != *(uword*)(source + i)) { - /* Check if the sector only contain zeroes */ - for (j = offset; j < (size + offset); j+=2) { - if (*(uword*)(flash->base + j) != 0xffff) - return 2; - } - return 1; - } - - /* The source is equal to the destination */ - return 0; -} - -static unsigned int -flash_probe_chips(void) -{ - unsigned int tot_size = 0; - unsigned int i = 0; - - for (; i < sizeof chips/sizeof *chips; i++) { -#ifdef INTERLEAVE - byte interleave; - - for (interleave = 1; interleave < 4; interleave *= 2) { - chips[i].interleave = interleave; - if (interleave == 1) { - chips[i].buswidth = sizeof(uword); - } else { - chips[i].buswidth = sizeof(udword); - } - - if (flash_probe(&chips[i])) { - break; - } - } -#else - flash_probe(&chips[i]); -#endif - - tot_size += chips[i].size; - } - - return tot_size; -} - -/* Program a sector (given by size) at the given offset. Do not write only ones. */ -static void -program_sector(struct chip *flash, unsigned long offset, const unsigned char *source, int size) -{ - int chunk_size = 0; - int bytes_written = 0; - - - while (bytes_written < size) { - if ( -#ifdef INTERLEAVE - (flash->buswidth == 2) && -#endif - *(uword*)(source + bytes_written) == 0xffff) { - chunk_size=2; - } -#ifdef INTERLEAVE - else if ((flash->buswidth == 4) && *(udword*)(source + bytes_written) == 0xffffffff) { - chunk_size=4; - } -#endif - else { - flash_unlock(flash); - wide_cmd(flash, CMD_PROGRAM_UNLOCK_DATA, ADDR_UNLOCK_1); - chunk_size = wide_write_chunk(flash, offset + bytes_written, source + bytes_written); - while(flash_is_busy(flash, offset + bytes_written)) - /* Nothing */ - ; - } - - bytes_written += chunk_size; - } -} - -int -flash_write(const unsigned char *source, unsigned int offset, unsigned int size) -{ - struct flash_status { - unsigned char busy; /* Indicates if the flash is busy */ - const unsigned char *src; /* From where to get the source info */ - unsigned long offset; /* Start operations in flash at this offset */ - unsigned int size; /* Size to erase/program (if needed) */ - unsigned int bytes_done; /* Bytes written (if needed) */ - unsigned int erase_attempts; /* Keep track how many times we try to erase the same sector */ - }; - - unsigned int tot_size = flash_probe_chips(); - unsigned int i, j; - unsigned int current_sector_size; - unsigned long current_offset; - const unsigned char *current_src; - char need_erase; - struct flash_status *current_flash = NULL; - - static struct flash_status flash_status[2] = { - { 0, NULL, 0, 0, 0, 0 }, - { 0, NULL, 0, 0, 0, 0 } - }; - - if (!tot_size) { - /* No chips found, bail out. */ - return ERR_FLASH_NONE; - } - - if (offset + size > tot_size) { - safe_printk("Fatal: flash is too small.\n"); - return ERR_FLASH_TOO_SMALL; - } - - /* Initiate the flash_status structs so that we can keep track of what needs to be done - on the different flash chips */ - - /* Operations only on flash chip 1 */ - if (offset >= (&chips[0])->size) { - flash_status[0].size = 0; - flash_status[1].src = source; - flash_status[1].offset = offset - (&chips[0])->size; - flash_status[1].size = size; - } - /* Operations on both flash chips */ - else if ((offset < (&chips[0])->size) && ((offset+size) > (&chips[0])->size)) { - flash_status[0].src = source; - flash_status[0].offset = offset; - flash_status[0].size = (&chips[0])->size - offset; - flash_status[1].src = source + flash_status[0].size; - flash_status[1].offset = 0; - flash_status[1].size = size - flash_status[0].size; - } - /* Operations only on flash chip 0 */ - else { - flash_status[0].src = source; - flash_status[0].offset = offset; - flash_status[0].size = size; - flash_status[1].size = 0; - } - flash_status[0].busy = 0; - flash_status[0].bytes_done = 0; - flash_status[0].erase_attempts = 0; - flash_status[1].busy = 0; - flash_status[1].bytes_done = 0; - flash_status[1].erase_attempts = 0; -#if 0 - for (i = 0; i < 2; i++) { - safe_printk("\nFlash "); - send_hex(i, NL); - safe_printk("src:\t"); - send_hex((int)flash_status[i].src, NL); - safe_printk("offset:\t"); - send_hex(flash_status[i].offset, NL); - safe_printk("size:\t"); - send_hex(flash_status[i].size, NL); - safe_printk("\n"); - } -#endif - - /* Erase and write */ - - i = 0; /* Start operations on flash 0 */ - -#define CHANGE_FLASH - - while (((&flash_status[0])->bytes_done + (&flash_status[1])->bytes_done) < size) { - - struct flash_status *previous_flash = &flash_status[i ? 0 : 1]; - current_flash = &flash_status[i]; - -#ifdef CHANGE_FLASH - /* Change flash only if: - - There is a flash to change to and operations should be made on that flash *AND* - - There is more to write to the previous flash *AND* - - Operations should be made on the current flash *OR* - - The current flash is busy *OR* - - All has been written to the current flash */ - - if (previous_flash->size && (previous_flash->bytes_done < previous_flash->size) && - (!current_flash->size || current_flash->busy || - current_flash->bytes_done == current_flash->size)) - i = i ? 0 : 1; /* Change flash chip */ -#else - /* Finish one flash chip before continuing on the next one */ - - if ((&flash_status[i])->bytes_done == (&flash_status[i])->size) - i = i ? 0 : 1; /* Change flash chip */ -#endif - /* Bail out if we have tried to erase the same sector more that 10 times. */ - if(current_flash->erase_attempts > 10) { - safe_printk("Sector erase error\n"); - return ERR_FLASH_ERASE; - } - - /* Get the current status from the chip we are about to access */ - current_flash = &flash_status[i]; - current_offset = current_flash->offset + current_flash->bytes_done; - current_src = current_flash->src + current_flash->bytes_done; - current_sector_size = find_sector_size(&chips[i], current_offset); - - /* Make sure that the chip we are about to access has finished erasing */ - if (current_flash->busy) { - while (flash_is_busy(&chips[i], current_offset)) - /* nothing */ - ; - current_flash->busy = 0; - } - - /* Some flash chip need a reset to bring them back to read mode again. */ - wide_cmd(&chips[i], CMD_RESET_DATA, ADDR_UNLOCK_1); - - /* Find out if we need to erase the sector or not */ - need_erase = need_to_erase(&chips[i], current_offset, current_src, current_sector_size); - - if (need_erase == 0) { - current_flash->bytes_done += current_sector_size; - current_flash->erase_attempts = 0; - send_hex((int)(&chips[i])->base + current_offset, 0); - safe_printk(": No need to write\n"); - continue; - } else if (need_erase == 1) { - /* Erased, not worth printing. */ - } - else if (need_erase == 2) { - send_hex((int)(&chips[i])->base + current_offset, 0); - safe_printk(": Erasing "); - send_hex(current_sector_size, 0); - safe_printk(" bytes\n"); - start_sector_erase(&chips[i], current_offset); - current_flash->busy=1; - current_flash->erase_attempts++; - continue; - } - - /* The sector is ready to be programmed */ - send_hex((int)(&chips[i])->base + current_offset, 0); - safe_printk(": Writing "); - send_hex(current_sector_size, 0); - safe_printk(" bytes\n"); - program_sector(&chips[i], current_offset, current_src, current_sector_size); - current_flash->bytes_done += current_sector_size; - current_flash->erase_attempts = 0; - } - - /* Verify that the flash chip(s) have the correct content */ - for (i = 0; i < 2; i++) { - current_flash = &flash_status[i]; - if (!current_flash->size) - continue; - send_hex((int)(&chips[i])->base, 0); - safe_printk(": Verifying..."); - for (j = 0; j < current_flash->size; j+=2) { - if (*(uword*)(current_flash->offset + j + (&chips[i])->base) != - *(uword*)(current_flash->src + j)) { - safe_printk("Error at "); - send_hex(j, NL); - return ERR_FLASH_VERIFY; - } - } - safe_printk("OK\n"); - } - - return ERR_FLASH_OK; -} diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/src/hwregs.c b/target/linux/etrax-2.6/image/e100boot/src/cbl/src/hwregs.c deleted file mode 100644 index 3e0f32ff27..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/cbl/src/hwregs.c +++ /dev/null @@ -1,1713 +0,0 @@ -/*!********************************************************************** -*! -*! FILE NAME: hwregs.c -*! -*! DESCRIPTION: Shadow register and initiated flag variables, -*! and a function for initialization of these variables. -*! -*! -*! FUNCTIONS: void init_shadow__hwregs( void ) -*! -*! NOTE: This file is automatically generated, do _not_ edit. -*! Created: Thu Oct 3 01:21:27 2002 -*! By: Id: shadow_gen,v 1.14 2002/10/02 20:31:22 hp Exp -*! From: /n/asic/projects/etrax_ng/doc/work/etrax_ng_regs.rd 1.168 -*! /n/asic/projects/etrax_ng/include//hwregs.ctrl 1.3 -*! -*! NOTE: init_shadow__hwregs() initiate all write only registers -*! described in /n/asic/projects/etrax_ng/doc/work/etrax_ng_regs.rd. -*! Since one physical register may have several logical names you -*! must choose which of the logical registers to initiate. -*! This is done by the 'USE_GROUP__group-name' macro in the -*! hwregs_def.h file. -*! -*! As an example, in Etrax100 the following logical registers are -*! all the same physical register at address 0xb0000044: -*! -*! R_ATA_CONFIG -*! R_PAR0_CONFIG -*! R_SCSI0_CTRL -*! R_SHARED_RAM_ADDR -*! -*!---------------------------------------------------------------------- -*! HISTORY -*! -*! DATE NAME CHANGES -*! ---- ---- ------- -*! Apr 01 1998 Jan Bengtsson Initial version -*!---------------------------------------------------------------------- -*! -*! (C) Copyright 1998, Axis Communications AB, LUND, SWEDEN -*! -*!**********************************************************************/ -/* %Z% %M% %I% %G% */ - -/********************** INCLUDE FILES SECTION **************************/ - -#include "compiler.h" -#include "hwregs.h" - -#if REG_DEBUG -#include -#endif - -/********************** CONSTANT AND MACRO SECTION *********************/ - -/********************** TYPE DEFINITION SECTION ************************/ - -/********************** LOCAL FUNCTION DECLARATION SECTION *************/ - -/********************** GLOBAL VARIABLE DECLARATION SECTION ************/ - -#ifndef REG_NO_SHADOW -/* Shadows for write only registers. */ -reg_shadow_type__hwregs reg_shadow__hwregs; -#else -/* Use constant zero as shadow when there isn't a shadow register. */ -reg_shadow_type__hwregs reg_shadow__hwregs = 0; -#endif - -#if REG_DEBUG -#ifndef REG_NO_SHADOW -/* Initiated flags for shadow registers. */ -reg_initiated_type__hwregs reg_initiated__hwregs; -#else -/* No need for initiated flags when there isn't a shadow register. */ -reg_initiated_type__hwregs reg_initiated__hwregs = 0; -#endif -#endif - -/********************** FUNCTION DEFINITION SECTION ********************/ - -/*#********************************************************************** -*# -*# FUNCTION NAME: init_shadow__hwregs -*# -*# PARAMETERS : none -*# -*# RETURNS : nothing -*# -*# SIDE EFFECTS : Writes initial values to all write only registers -*# and their associated shadow registers. If REG_DEBUG -*# is non zero the reg_initiated struct is also initiated. -*# -*# DESCRIPTION : Initiate write only registers, their shadows, and in -*# debug mode the initiated flags. Default values for -*# the initialization are defined in hwregs_def.h. -*# -*# Note that one physical register may have several -*# logical names, and that you have to modify this -*# function to only initiate the physical register once! -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# -*#**********************************************************************/ - -void init_shadow__hwregs( void ) -{ -#if REG_DEBUG && !defined(REG_NO_SHADOW) - /* Initiate reg_initiated__hwregs struct to 0xff. */ - memset( ®_initiated__hwregs, 0xff, sizeof(reg_initiated_type__hwregs) ); -#endif - -#ifndef REG_NO_INIT_SHADOW - -#if USE_GROUP__Serial_port_registers - REG_SET__R_ALT_SER_BAUDRATE( - ser3_tr, R_ALT_SER_BAUDRATE__ser3_tr__DEFAULT, - ser3_rec, R_ALT_SER_BAUDRATE__ser3_rec__DEFAULT, - ser2_tr, R_ALT_SER_BAUDRATE__ser2_tr__DEFAULT, - ser2_rec, R_ALT_SER_BAUDRATE__ser2_rec__DEFAULT, - ser1_tr, R_ALT_SER_BAUDRATE__ser1_tr__DEFAULT, - ser1_rec, R_ALT_SER_BAUDRATE__ser1_rec__DEFAULT, - ser0_tr, R_ALT_SER_BAUDRATE__ser0_tr__DEFAULT, - ser0_rec, R_ALT_SER_BAUDRATE__ser0_rec__DEFAULT - ); -#endif - -#if USE_GROUP__ATA_interface_registers - REG_SET__R_ATA_CONFIG( - enable, R_ATA_CONFIG__enable__DEFAULT, - dma_strobe, R_ATA_CONFIG__dma_strobe__DEFAULT, - dma_hold, R_ATA_CONFIG__dma_hold__DEFAULT, - pio_setup, R_ATA_CONFIG__pio_setup__DEFAULT, - pio_strobe, R_ATA_CONFIG__pio_strobe__DEFAULT, - pio_hold, R_ATA_CONFIG__pio_hold__DEFAULT - ); -#endif - -#if USE_GROUP__ATA_interface_registers - REG_SET__R_ATA_CTRL_DATA( - sel, R_ATA_CTRL_DATA__sel__DEFAULT, - cs1, R_ATA_CTRL_DATA__cs1__DEFAULT, - cs0, R_ATA_CTRL_DATA__cs0__DEFAULT, - addr, R_ATA_CTRL_DATA__addr__DEFAULT, - rw, R_ATA_CTRL_DATA__rw__DEFAULT, - src_dst, R_ATA_CTRL_DATA__src_dst__DEFAULT, - handsh, R_ATA_CTRL_DATA__handsh__DEFAULT, - multi, R_ATA_CTRL_DATA__multi__DEFAULT, - dma_size, R_ATA_CTRL_DATA__dma_size__DEFAULT, - data, R_ATA_CTRL_DATA__data__DEFAULT - ); -#endif - -#if USE_GROUP__Bus_interface_configuration_registers - REG_SET__R_BUS_CONFIG( - sram_type, R_BUS_CONFIG__sram_type__DEFAULT, - dma_burst, R_BUS_CONFIG__dma_burst__DEFAULT, - pcs4_7_wr, R_BUS_CONFIG__pcs4_7_wr__DEFAULT, - pcs0_3_wr, R_BUS_CONFIG__pcs0_3_wr__DEFAULT, - sram_wr, R_BUS_CONFIG__sram_wr__DEFAULT, - flash_wr, R_BUS_CONFIG__flash_wr__DEFAULT, - pcs4_7_bw, R_BUS_CONFIG__pcs4_7_bw__DEFAULT, - pcs0_3_bw, R_BUS_CONFIG__pcs0_3_bw__DEFAULT, - sram_bw, R_BUS_CONFIG__sram_bw__DEFAULT, - flash_bw, R_BUS_CONFIG__flash_bw__DEFAULT - ); -#endif - -#if USE_GROUP__Timer_registers - REG_SET__R_CLOCK_PRESCALE( - ser_presc, R_CLOCK_PRESCALE__ser_presc__DEFAULT, - tim_presc, R_CLOCK_PRESCALE__tim_presc__DEFAULT - ); -#endif - -#if USE_GROUP__DMA_registers - REG_SET__R_DMA_CH0_CLR_INTR( - clr_eop, R_DMA_CH0_CLR_INTR__clr_eop__DEFAULT, - clr_descr, R_DMA_CH0_CLR_INTR__clr_descr__DEFAULT - ); -#endif - -#if USE_GROUP__DMA_registers - REG_SET__R_DMA_CH1_CLR_INTR( - clr_eop, R_DMA_CH1_CLR_INTR__clr_eop__DEFAULT, - clr_descr, R_DMA_CH1_CLR_INTR__clr_descr__DEFAULT - ); -#endif - -#if USE_GROUP__DMA_registers - REG_SET__R_DMA_CH2_CLR_INTR( - clr_eop, R_DMA_CH2_CLR_INTR__clr_eop__DEFAULT, - clr_descr, R_DMA_CH2_CLR_INTR__clr_descr__DEFAULT - ); -#endif - -#if USE_GROUP__DMA_registers - REG_SET__R_DMA_CH3_CLR_INTR( - clr_eop, R_DMA_CH3_CLR_INTR__clr_eop__DEFAULT, - clr_descr, R_DMA_CH3_CLR_INTR__clr_descr__DEFAULT - ); -#endif - -#if USE_GROUP__DMA_registers - REG_SET__R_DMA_CH4_CLR_INTR( - clr_eop, R_DMA_CH4_CLR_INTR__clr_eop__DEFAULT, - clr_descr, R_DMA_CH4_CLR_INTR__clr_descr__DEFAULT - ); -#endif - -#if USE_GROUP__DMA_registers - REG_SET__R_DMA_CH5_CLR_INTR( - clr_eop, R_DMA_CH5_CLR_INTR__clr_eop__DEFAULT, - clr_descr, R_DMA_CH5_CLR_INTR__clr_descr__DEFAULT - ); -#endif - -#if USE_GROUP__DMA_registers - REG_SET__R_DMA_CH6_CLR_INTR( - clr_eop, R_DMA_CH6_CLR_INTR__clr_eop__DEFAULT, - clr_descr, R_DMA_CH6_CLR_INTR__clr_descr__DEFAULT - ); -#endif - -#if USE_GROUP__DMA_registers - REG_SET__R_DMA_CH7_CLR_INTR( - clr_eop, R_DMA_CH7_CLR_INTR__clr_eop__DEFAULT, - clr_descr, R_DMA_CH7_CLR_INTR__clr_descr__DEFAULT - ); -#endif - -#if USE_GROUP__DMA_registers - REG_SET__R_DMA_CH8_CLR_INTR( - clr_eop, R_DMA_CH8_CLR_INTR__clr_eop__DEFAULT, - clr_descr, R_DMA_CH8_CLR_INTR__clr_descr__DEFAULT - ); -#endif - -#if USE_GROUP__DMA_registers - REG_SET__R_DMA_CH8_SUB0_CLR_INTR( - clr_descr, R_DMA_CH8_SUB0_CLR_INTR__clr_descr__DEFAULT - ); -#endif - -#if USE_GROUP__DMA_registers - REG_SET__R_DMA_CH8_SUB1_CLR_INTR( - clr_descr, R_DMA_CH8_SUB1_CLR_INTR__clr_descr__DEFAULT - ); -#endif - -#if USE_GROUP__DMA_registers - REG_SET__R_DMA_CH8_SUB2_CLR_INTR( - clr_descr, R_DMA_CH8_SUB2_CLR_INTR__clr_descr__DEFAULT - ); -#endif - -#if USE_GROUP__DMA_registers - REG_SET__R_DMA_CH8_SUB3_CLR_INTR( - clr_descr, R_DMA_CH8_SUB3_CLR_INTR__clr_descr__DEFAULT - ); -#endif - -#if USE_GROUP__DMA_registers - REG_SET__R_DMA_CH9_CLR_INTR( - clr_eop, R_DMA_CH9_CLR_INTR__clr_eop__DEFAULT, - clr_descr, R_DMA_CH9_CLR_INTR__clr_descr__DEFAULT - ); -#endif - -#if USE_GROUP__Bus_interface_configuration_registers - REG_SET__R_DRAM_CONFIG( - wmm1, R_DRAM_CONFIG__wmm1__DEFAULT, - wmm0, R_DRAM_CONFIG__wmm0__DEFAULT, - sh1, R_DRAM_CONFIG__sh1__DEFAULT, - sh0, R_DRAM_CONFIG__sh0__DEFAULT, - w, R_DRAM_CONFIG__w__DEFAULT, - c, R_DRAM_CONFIG__c__DEFAULT, - e, R_DRAM_CONFIG__e__DEFAULT, - group_sel, R_DRAM_CONFIG__group_sel__DEFAULT, - ca1, R_DRAM_CONFIG__ca1__DEFAULT, - bank23sel, R_DRAM_CONFIG__bank23sel__DEFAULT, - ca0, R_DRAM_CONFIG__ca0__DEFAULT, - bank01sel, R_DRAM_CONFIG__bank01sel__DEFAULT - ); -#endif - -#if USE_GROUP__Bus_interface_configuration_registers - REG_SET__R_DRAM_TIMING( - sdram, R_DRAM_TIMING__sdram__DEFAULT, - ref, R_DRAM_TIMING__ref__DEFAULT, - rp, R_DRAM_TIMING__rp__DEFAULT, - rs, R_DRAM_TIMING__rs__DEFAULT, - rh, R_DRAM_TIMING__rh__DEFAULT, - w, R_DRAM_TIMING__w__DEFAULT, - c, R_DRAM_TIMING__c__DEFAULT, - cz, R_DRAM_TIMING__cz__DEFAULT, - cp, R_DRAM_TIMING__cp__DEFAULT, - cw, R_DRAM_TIMING__cw__DEFAULT - ); -#endif - -#if USE_GROUP__External_DMA_registers - REG_SET__R_EXT_DMA_0_ADDR( - ext0_addr, R_EXT_DMA_0_ADDR__ext0_addr__DEFAULT - ); -#endif - -#if USE_GROUP__External_DMA_registers - REG_SET__R_EXT_DMA_0_CMD( - cnt, R_EXT_DMA_0_CMD__cnt__DEFAULT, - rqpol, R_EXT_DMA_0_CMD__rqpol__DEFAULT, - apol, R_EXT_DMA_0_CMD__apol__DEFAULT, - rq_ack, R_EXT_DMA_0_CMD__rq_ack__DEFAULT, - wid, R_EXT_DMA_0_CMD__wid__DEFAULT, - dir, R_EXT_DMA_0_CMD__dir__DEFAULT, - run, R_EXT_DMA_0_CMD__run__DEFAULT, - trf_count, R_EXT_DMA_0_CMD__trf_count__DEFAULT - ); -#endif - -#if USE_GROUP__External_DMA_registers - REG_SET__R_EXT_DMA_1_ADDR( - ext0_addr, R_EXT_DMA_1_ADDR__ext0_addr__DEFAULT - ); -#endif - -#if USE_GROUP__External_DMA_registers - REG_SET__R_EXT_DMA_1_CMD( - cnt, R_EXT_DMA_1_CMD__cnt__DEFAULT, - rqpol, R_EXT_DMA_1_CMD__rqpol__DEFAULT, - apol, R_EXT_DMA_1_CMD__apol__DEFAULT, - rq_ack, R_EXT_DMA_1_CMD__rq_ack__DEFAULT, - wid, R_EXT_DMA_1_CMD__wid__DEFAULT, - dir, R_EXT_DMA_1_CMD__dir__DEFAULT, - run, R_EXT_DMA_1_CMD__run__DEFAULT, - trf_count, R_EXT_DMA_1_CMD__trf_count__DEFAULT - ); -#endif - -#if USE_GROUP__General_config_registers - REG_SET__R_GEN_CONFIG( - par_w, R_GEN_CONFIG__par_w__DEFAULT, - usb2, R_GEN_CONFIG__usb2__DEFAULT, - usb1, R_GEN_CONFIG__usb1__DEFAULT, - g24dir, R_GEN_CONFIG__g24dir__DEFAULT, - g16_23dir, R_GEN_CONFIG__g16_23dir__DEFAULT, - g8_15dir, R_GEN_CONFIG__g8_15dir__DEFAULT, - g0dir, R_GEN_CONFIG__g0dir__DEFAULT, - dma9, R_GEN_CONFIG__dma9__DEFAULT, - dma8, R_GEN_CONFIG__dma8__DEFAULT, - dma7, R_GEN_CONFIG__dma7__DEFAULT, - dma6, R_GEN_CONFIG__dma6__DEFAULT, - dma5, R_GEN_CONFIG__dma5__DEFAULT, - dma4, R_GEN_CONFIG__dma4__DEFAULT, - dma3, R_GEN_CONFIG__dma3__DEFAULT, - dma2, R_GEN_CONFIG__dma2__DEFAULT, - mio_w, R_GEN_CONFIG__mio_w__DEFAULT, - ser3, R_GEN_CONFIG__ser3__DEFAULT, - par1, R_GEN_CONFIG__par1__DEFAULT, - scsi0w, R_GEN_CONFIG__scsi0w__DEFAULT, - scsi1, R_GEN_CONFIG__scsi1__DEFAULT, - mio, R_GEN_CONFIG__mio__DEFAULT, - ser2, R_GEN_CONFIG__ser2__DEFAULT, - par0, R_GEN_CONFIG__par0__DEFAULT, - ata, R_GEN_CONFIG__ata__DEFAULT, - scsi0, R_GEN_CONFIG__scsi0__DEFAULT - ); -#endif - -#if USE_GROUP__General_config_registers - REG_SET__R_GEN_CONFIG_II( - sermode3, R_GEN_CONFIG_II__sermode3__DEFAULT, - sermode1, R_GEN_CONFIG_II__sermode1__DEFAULT, - ext_clk, R_GEN_CONFIG_II__ext_clk__DEFAULT, - ser3, R_GEN_CONFIG_II__ser3__DEFAULT, - ser2, R_GEN_CONFIG_II__ser2__DEFAULT - ); -#endif - -#if USE_GROUP__Interrupt_mask_and_status_registers - REG_SET__R_IRQ_MASK0_CLR( - nmi_pin, R_IRQ_MASK0_CLR__nmi_pin__DEFAULT, - watchdog_nmi, R_IRQ_MASK0_CLR__watchdog_nmi__DEFAULT, - sqe_test_error, R_IRQ_MASK0_CLR__sqe_test_error__DEFAULT, - carrier_loss, R_IRQ_MASK0_CLR__carrier_loss__DEFAULT, - deferred, R_IRQ_MASK0_CLR__deferred__DEFAULT, - late_col, R_IRQ_MASK0_CLR__late_col__DEFAULT, - multiple_col, R_IRQ_MASK0_CLR__multiple_col__DEFAULT, - single_col, R_IRQ_MASK0_CLR__single_col__DEFAULT, - congestion, R_IRQ_MASK0_CLR__congestion__DEFAULT, - oversize, R_IRQ_MASK0_CLR__oversize__DEFAULT, - alignment_error, R_IRQ_MASK0_CLR__alignment_error__DEFAULT, - crc_error, R_IRQ_MASK0_CLR__crc_error__DEFAULT, - overrun, R_IRQ_MASK0_CLR__overrun__DEFAULT, - underrun, R_IRQ_MASK0_CLR__underrun__DEFAULT, - excessive_col, R_IRQ_MASK0_CLR__excessive_col__DEFAULT, - mdio, R_IRQ_MASK0_CLR__mdio__DEFAULT, - ata_drq3, R_IRQ_MASK0_CLR__ata_drq3__DEFAULT, - ata_drq2, R_IRQ_MASK0_CLR__ata_drq2__DEFAULT, - ata_drq1, R_IRQ_MASK0_CLR__ata_drq1__DEFAULT, - ata_drq0, R_IRQ_MASK0_CLR__ata_drq0__DEFAULT, - par0_ecp_cmd, R_IRQ_MASK0_CLR__par0_ecp_cmd__DEFAULT, - par0_peri, R_IRQ_MASK0_CLR__par0_peri__DEFAULT, - par0_data, R_IRQ_MASK0_CLR__par0_data__DEFAULT, - par0_ready, R_IRQ_MASK0_CLR__par0_ready__DEFAULT, - ata_dmaend, R_IRQ_MASK0_CLR__ata_dmaend__DEFAULT, - irq_ext_vector_nr, R_IRQ_MASK0_CLR__irq_ext_vector_nr__DEFAULT, - irq_int_vector_nr, R_IRQ_MASK0_CLR__irq_int_vector_nr__DEFAULT, - ext_dma1, R_IRQ_MASK0_CLR__ext_dma1__DEFAULT, - ext_dma0, R_IRQ_MASK0_CLR__ext_dma0__DEFAULT, - timer1, R_IRQ_MASK0_CLR__timer1__DEFAULT, - timer0, R_IRQ_MASK0_CLR__timer0__DEFAULT - ); -#endif - -#if USE_GROUP__Interrupt_mask_and_status_registers - REG_SET__R_IRQ_MASK0_SET( - nmi_pin, R_IRQ_MASK0_SET__nmi_pin__DEFAULT, - watchdog_nmi, R_IRQ_MASK0_SET__watchdog_nmi__DEFAULT, - sqe_test_error, R_IRQ_MASK0_SET__sqe_test_error__DEFAULT, - carrier_loss, R_IRQ_MASK0_SET__carrier_loss__DEFAULT, - deferred, R_IRQ_MASK0_SET__deferred__DEFAULT, - late_col, R_IRQ_MASK0_SET__late_col__DEFAULT, - multiple_col, R_IRQ_MASK0_SET__multiple_col__DEFAULT, - single_col, R_IRQ_MASK0_SET__single_col__DEFAULT, - congestion, R_IRQ_MASK0_SET__congestion__DEFAULT, - oversize, R_IRQ_MASK0_SET__oversize__DEFAULT, - alignment_error, R_IRQ_MASK0_SET__alignment_error__DEFAULT, - crc_error, R_IRQ_MASK0_SET__crc_error__DEFAULT, - overrun, R_IRQ_MASK0_SET__overrun__DEFAULT, - underrun, R_IRQ_MASK0_SET__underrun__DEFAULT, - excessive_col, R_IRQ_MASK0_SET__excessive_col__DEFAULT, - mdio, R_IRQ_MASK0_SET__mdio__DEFAULT, - ata_drq3, R_IRQ_MASK0_SET__ata_drq3__DEFAULT, - ata_drq2, R_IRQ_MASK0_SET__ata_drq2__DEFAULT, - ata_drq1, R_IRQ_MASK0_SET__ata_drq1__DEFAULT, - ata_drq0, R_IRQ_MASK0_SET__ata_drq0__DEFAULT, - par0_ecp_cmd, R_IRQ_MASK0_SET__par0_ecp_cmd__DEFAULT, - par0_peri, R_IRQ_MASK0_SET__par0_peri__DEFAULT, - par0_data, R_IRQ_MASK0_SET__par0_data__DEFAULT, - par0_ready, R_IRQ_MASK0_SET__par0_ready__DEFAULT, - ata_dmaend, R_IRQ_MASK0_SET__ata_dmaend__DEFAULT, - irq_ext_vector_nr, R_IRQ_MASK0_SET__irq_ext_vector_nr__DEFAULT, - irq_int_vector_nr, R_IRQ_MASK0_SET__irq_int_vector_nr__DEFAULT, - ext_dma1, R_IRQ_MASK0_SET__ext_dma1__DEFAULT, - ext_dma0, R_IRQ_MASK0_SET__ext_dma0__DEFAULT, - timer1, R_IRQ_MASK0_SET__timer1__DEFAULT, - timer0, R_IRQ_MASK0_SET__timer0__DEFAULT - ); -#endif - -#if USE_GROUP__Interrupt_mask_and_status_registers - REG_SET__R_IRQ_MASK1_CLR( - sw_int7, R_IRQ_MASK1_CLR__sw_int7__DEFAULT, - sw_int6, R_IRQ_MASK1_CLR__sw_int6__DEFAULT, - sw_int5, R_IRQ_MASK1_CLR__sw_int5__DEFAULT, - sw_int4, R_IRQ_MASK1_CLR__sw_int4__DEFAULT, - sw_int3, R_IRQ_MASK1_CLR__sw_int3__DEFAULT, - sw_int2, R_IRQ_MASK1_CLR__sw_int2__DEFAULT, - sw_int1, R_IRQ_MASK1_CLR__sw_int1__DEFAULT, - sw_int0, R_IRQ_MASK1_CLR__sw_int0__DEFAULT, - par1_ecp_cmd, R_IRQ_MASK1_CLR__par1_ecp_cmd__DEFAULT, - par1_peri, R_IRQ_MASK1_CLR__par1_peri__DEFAULT, - par1_data, R_IRQ_MASK1_CLR__par1_data__DEFAULT, - par1_ready, R_IRQ_MASK1_CLR__par1_ready__DEFAULT, - ser3_ready, R_IRQ_MASK1_CLR__ser3_ready__DEFAULT, - ser3_data, R_IRQ_MASK1_CLR__ser3_data__DEFAULT, - ser2_ready, R_IRQ_MASK1_CLR__ser2_ready__DEFAULT, - ser2_data, R_IRQ_MASK1_CLR__ser2_data__DEFAULT, - ser1_ready, R_IRQ_MASK1_CLR__ser1_ready__DEFAULT, - ser1_data, R_IRQ_MASK1_CLR__ser1_data__DEFAULT, - ser0_ready, R_IRQ_MASK1_CLR__ser0_ready__DEFAULT, - ser0_data, R_IRQ_MASK1_CLR__ser0_data__DEFAULT, - pa7, R_IRQ_MASK1_CLR__pa7__DEFAULT, - pa6, R_IRQ_MASK1_CLR__pa6__DEFAULT, - pa5, R_IRQ_MASK1_CLR__pa5__DEFAULT, - pa4, R_IRQ_MASK1_CLR__pa4__DEFAULT, - pa3, R_IRQ_MASK1_CLR__pa3__DEFAULT, - pa2, R_IRQ_MASK1_CLR__pa2__DEFAULT, - pa1, R_IRQ_MASK1_CLR__pa1__DEFAULT, - pa0, R_IRQ_MASK1_CLR__pa0__DEFAULT - ); -#endif - -#if USE_GROUP__Interrupt_mask_and_status_registers - REG_SET__R_IRQ_MASK1_SET( - sw_int7, R_IRQ_MASK1_SET__sw_int7__DEFAULT, - sw_int6, R_IRQ_MASK1_SET__sw_int6__DEFAULT, - sw_int5, R_IRQ_MASK1_SET__sw_int5__DEFAULT, - sw_int4, R_IRQ_MASK1_SET__sw_int4__DEFAULT, - sw_int3, R_IRQ_MASK1_SET__sw_int3__DEFAULT, - sw_int2, R_IRQ_MASK1_SET__sw_int2__DEFAULT, - sw_int1, R_IRQ_MASK1_SET__sw_int1__DEFAULT, - sw_int0, R_IRQ_MASK1_SET__sw_int0__DEFAULT, - par1_ecp_cmd, R_IRQ_MASK1_SET__par1_ecp_cmd__DEFAULT, - par1_peri, R_IRQ_MASK1_SET__par1_peri__DEFAULT, - par1_data, R_IRQ_MASK1_SET__par1_data__DEFAULT, - par1_ready, R_IRQ_MASK1_SET__par1_ready__DEFAULT, - ser3_ready, R_IRQ_MASK1_SET__ser3_ready__DEFAULT, - ser3_data, R_IRQ_MASK1_SET__ser3_data__DEFAULT, - ser2_ready, R_IRQ_MASK1_SET__ser2_ready__DEFAULT, - ser2_data, R_IRQ_MASK1_SET__ser2_data__DEFAULT, - ser1_ready, R_IRQ_MASK1_SET__ser1_ready__DEFAULT, - ser1_data, R_IRQ_MASK1_SET__ser1_data__DEFAULT, - ser0_ready, R_IRQ_MASK1_SET__ser0_ready__DEFAULT, - ser0_data, R_IRQ_MASK1_SET__ser0_data__DEFAULT, - pa7, R_IRQ_MASK1_SET__pa7__DEFAULT, - pa6, R_IRQ_MASK1_SET__pa6__DEFAULT, - pa5, R_IRQ_MASK1_SET__pa5__DEFAULT, - pa4, R_IRQ_MASK1_SET__pa4__DEFAULT, - pa3, R_IRQ_MASK1_SET__pa3__DEFAULT, - pa2, R_IRQ_MASK1_SET__pa2__DEFAULT, - pa1, R_IRQ_MASK1_SET__pa1__DEFAULT, - pa0, R_IRQ_MASK1_SET__pa0__DEFAULT - ); -#endif - -#if USE_GROUP__Interrupt_mask_and_status_registers - REG_SET__R_IRQ_MASK2_CLR( - dma8_sub3_descr, R_IRQ_MASK2_CLR__dma8_sub3_descr__DEFAULT, - dma8_sub2_descr, R_IRQ_MASK2_CLR__dma8_sub2_descr__DEFAULT, - dma8_sub1_descr, R_IRQ_MASK2_CLR__dma8_sub1_descr__DEFAULT, - dma8_sub0_descr, R_IRQ_MASK2_CLR__dma8_sub0_descr__DEFAULT, - dma9_eop, R_IRQ_MASK2_CLR__dma9_eop__DEFAULT, - dma9_descr, R_IRQ_MASK2_CLR__dma9_descr__DEFAULT, - dma8_eop, R_IRQ_MASK2_CLR__dma8_eop__DEFAULT, - dma8_descr, R_IRQ_MASK2_CLR__dma8_descr__DEFAULT, - dma7_eop, R_IRQ_MASK2_CLR__dma7_eop__DEFAULT, - dma7_descr, R_IRQ_MASK2_CLR__dma7_descr__DEFAULT, - dma6_eop, R_IRQ_MASK2_CLR__dma6_eop__DEFAULT, - dma6_descr, R_IRQ_MASK2_CLR__dma6_descr__DEFAULT, - dma5_eop, R_IRQ_MASK2_CLR__dma5_eop__DEFAULT, - dma5_descr, R_IRQ_MASK2_CLR__dma5_descr__DEFAULT, - dma4_eop, R_IRQ_MASK2_CLR__dma4_eop__DEFAULT, - dma4_descr, R_IRQ_MASK2_CLR__dma4_descr__DEFAULT, - dma3_eop, R_IRQ_MASK2_CLR__dma3_eop__DEFAULT, - dma3_descr, R_IRQ_MASK2_CLR__dma3_descr__DEFAULT, - dma2_eop, R_IRQ_MASK2_CLR__dma2_eop__DEFAULT, - dma2_descr, R_IRQ_MASK2_CLR__dma2_descr__DEFAULT, - dma1_eop, R_IRQ_MASK2_CLR__dma1_eop__DEFAULT, - dma1_descr, R_IRQ_MASK2_CLR__dma1_descr__DEFAULT, - dma0_eop, R_IRQ_MASK2_CLR__dma0_eop__DEFAULT, - dma0_descr, R_IRQ_MASK2_CLR__dma0_descr__DEFAULT - ); -#endif - -#if USE_GROUP__Interrupt_mask_and_status_registers - REG_SET__R_IRQ_MASK2_SET( - dma8_sub3_descr, R_IRQ_MASK2_SET__dma8_sub3_descr__DEFAULT, - dma8_sub2_descr, R_IRQ_MASK2_SET__dma8_sub2_descr__DEFAULT, - dma8_sub1_descr, R_IRQ_MASK2_SET__dma8_sub1_descr__DEFAULT, - dma8_sub0_descr, R_IRQ_MASK2_SET__dma8_sub0_descr__DEFAULT, - dma9_eop, R_IRQ_MASK2_SET__dma9_eop__DEFAULT, - dma9_descr, R_IRQ_MASK2_SET__dma9_descr__DEFAULT, - dma8_eop, R_IRQ_MASK2_SET__dma8_eop__DEFAULT, - dma8_descr, R_IRQ_MASK2_SET__dma8_descr__DEFAULT, - dma7_eop, R_IRQ_MASK2_SET__dma7_eop__DEFAULT, - dma7_descr, R_IRQ_MASK2_SET__dma7_descr__DEFAULT, - dma6_eop, R_IRQ_MASK2_SET__dma6_eop__DEFAULT, - dma6_descr, R_IRQ_MASK2_SET__dma6_descr__DEFAULT, - dma5_eop, R_IRQ_MASK2_SET__dma5_eop__DEFAULT, - dma5_descr, R_IRQ_MASK2_SET__dma5_descr__DEFAULT, - dma4_eop, R_IRQ_MASK2_SET__dma4_eop__DEFAULT, - dma4_descr, R_IRQ_MASK2_SET__dma4_descr__DEFAULT, - dma3_eop, R_IRQ_MASK2_SET__dma3_eop__DEFAULT, - dma3_descr, R_IRQ_MASK2_SET__dma3_descr__DEFAULT, - dma2_eop, R_IRQ_MASK2_SET__dma2_eop__DEFAULT, - dma2_descr, R_IRQ_MASK2_SET__dma2_descr__DEFAULT, - dma1_eop, R_IRQ_MASK2_SET__dma1_eop__DEFAULT, - dma1_descr, R_IRQ_MASK2_SET__dma1_descr__DEFAULT, - dma0_eop, R_IRQ_MASK2_SET__dma0_eop__DEFAULT, - dma0_descr, R_IRQ_MASK2_SET__dma0_descr__DEFAULT - ); -#endif - -#if USE_GROUP__MMU_registers - REG_SET__R_MMU_CONFIG( - mmu_enable, R_MMU_CONFIG__mmu_enable__DEFAULT, - inv_excp, R_MMU_CONFIG__inv_excp__DEFAULT, - acc_excp, R_MMU_CONFIG__acc_excp__DEFAULT, - we_excp, R_MMU_CONFIG__we_excp__DEFAULT, - seg_f, R_MMU_CONFIG__seg_f__DEFAULT, - seg_e, R_MMU_CONFIG__seg_e__DEFAULT, - seg_d, R_MMU_CONFIG__seg_d__DEFAULT, - seg_c, R_MMU_CONFIG__seg_c__DEFAULT, - seg_b, R_MMU_CONFIG__seg_b__DEFAULT, - seg_a, R_MMU_CONFIG__seg_a__DEFAULT, - seg_9, R_MMU_CONFIG__seg_9__DEFAULT, - seg_8, R_MMU_CONFIG__seg_8__DEFAULT, - seg_7, R_MMU_CONFIG__seg_7__DEFAULT, - seg_6, R_MMU_CONFIG__seg_6__DEFAULT, - seg_5, R_MMU_CONFIG__seg_5__DEFAULT, - seg_4, R_MMU_CONFIG__seg_4__DEFAULT, - seg_3, R_MMU_CONFIG__seg_3__DEFAULT, - seg_2, R_MMU_CONFIG__seg_2__DEFAULT, - seg_1, R_MMU_CONFIG__seg_1__DEFAULT, - seg_0, R_MMU_CONFIG__seg_0__DEFAULT - ); -#endif - -#if USE_GROUP__MMU_registers - REG_SET__R_MMU_CTRL( - inv_excp, R_MMU_CTRL__inv_excp__DEFAULT, - acc_excp, R_MMU_CTRL__acc_excp__DEFAULT, - we_excp, R_MMU_CTRL__we_excp__DEFAULT - ); -#endif - -#if USE_GROUP__MMU_registers - REG_SET__R_MMU_ENABLE( - mmu_enable, R_MMU_ENABLE__mmu_enable__DEFAULT - ); -#endif - -#if USE_GROUP__MMU_registers - REG_SET__R_MMU_KBASE_HI( - base_f, R_MMU_KBASE_HI__base_f__DEFAULT, - base_e, R_MMU_KBASE_HI__base_e__DEFAULT, - base_d, R_MMU_KBASE_HI__base_d__DEFAULT, - base_c, R_MMU_KBASE_HI__base_c__DEFAULT, - base_b, R_MMU_KBASE_HI__base_b__DEFAULT, - base_a, R_MMU_KBASE_HI__base_a__DEFAULT, - base_9, R_MMU_KBASE_HI__base_9__DEFAULT, - base_8, R_MMU_KBASE_HI__base_8__DEFAULT - ); -#endif - -#if USE_GROUP__MMU_registers - REG_SET__R_MMU_KBASE_LO( - base_7, R_MMU_KBASE_LO__base_7__DEFAULT, - base_6, R_MMU_KBASE_LO__base_6__DEFAULT, - base_5, R_MMU_KBASE_LO__base_5__DEFAULT, - base_4, R_MMU_KBASE_LO__base_4__DEFAULT, - base_3, R_MMU_KBASE_LO__base_3__DEFAULT, - base_2, R_MMU_KBASE_LO__base_2__DEFAULT, - base_1, R_MMU_KBASE_LO__base_1__DEFAULT, - base_0, R_MMU_KBASE_LO__base_0__DEFAULT - ); -#endif - -#if USE_GROUP__MMU_registers - REG_SET__R_MMU_KSEG( - seg_f, R_MMU_KSEG__seg_f__DEFAULT, - seg_e, R_MMU_KSEG__seg_e__DEFAULT, - seg_d, R_MMU_KSEG__seg_d__DEFAULT, - seg_c, R_MMU_KSEG__seg_c__DEFAULT, - seg_b, R_MMU_KSEG__seg_b__DEFAULT, - seg_a, R_MMU_KSEG__seg_a__DEFAULT, - seg_9, R_MMU_KSEG__seg_9__DEFAULT, - seg_8, R_MMU_KSEG__seg_8__DEFAULT, - seg_7, R_MMU_KSEG__seg_7__DEFAULT, - seg_6, R_MMU_KSEG__seg_6__DEFAULT, - seg_5, R_MMU_KSEG__seg_5__DEFAULT, - seg_4, R_MMU_KSEG__seg_4__DEFAULT, - seg_3, R_MMU_KSEG__seg_3__DEFAULT, - seg_2, R_MMU_KSEG__seg_2__DEFAULT, - seg_1, R_MMU_KSEG__seg_1__DEFAULT, - seg_0, R_MMU_KSEG__seg_0__DEFAULT - ); -#endif - -#if USE_GROUP__Network_interface_registers - REG_SET__R_NETWORK_GA_0( - ga_low, R_NETWORK_GA_0__ga_low__DEFAULT - ); -#endif - -#if USE_GROUP__Network_interface_registers - REG_SET__R_NETWORK_GA_1( - ga_high, R_NETWORK_GA_1__ga_high__DEFAULT - ); -#endif - -#if USE_GROUP__Network_interface_registers - REG_SET__R_NETWORK_GEN_CONFIG( - loopback, R_NETWORK_GEN_CONFIG__loopback__DEFAULT, - frame, R_NETWORK_GEN_CONFIG__frame__DEFAULT, - vg, R_NETWORK_GEN_CONFIG__vg__DEFAULT, - phy, R_NETWORK_GEN_CONFIG__phy__DEFAULT, - enable, R_NETWORK_GEN_CONFIG__enable__DEFAULT - ); -#endif - -#if USE_GROUP__Network_interface_registers - REG_SET__R_NETWORK_MGM_CTRL( - txd_pins, R_NETWORK_MGM_CTRL__txd_pins__DEFAULT, - txer_pin, R_NETWORK_MGM_CTRL__txer_pin__DEFAULT, - mdck, R_NETWORK_MGM_CTRL__mdck__DEFAULT, - mdoe, R_NETWORK_MGM_CTRL__mdoe__DEFAULT, - mdio, R_NETWORK_MGM_CTRL__mdio__DEFAULT - ); -#endif - -#if USE_GROUP__Network_interface_registers - REG_SET__R_NETWORK_REC_CONFIG( - max_size, R_NETWORK_REC_CONFIG__max_size__DEFAULT, - duplex, R_NETWORK_REC_CONFIG__duplex__DEFAULT, - bad_crc, R_NETWORK_REC_CONFIG__bad_crc__DEFAULT, - oversize, R_NETWORK_REC_CONFIG__oversize__DEFAULT, - undersize, R_NETWORK_REC_CONFIG__undersize__DEFAULT, - all_roots, R_NETWORK_REC_CONFIG__all_roots__DEFAULT, - tr_broadcast, R_NETWORK_REC_CONFIG__tr_broadcast__DEFAULT, - broadcast, R_NETWORK_REC_CONFIG__broadcast__DEFAULT, - individual, R_NETWORK_REC_CONFIG__individual__DEFAULT, - ma1, R_NETWORK_REC_CONFIG__ma1__DEFAULT, - ma0, R_NETWORK_REC_CONFIG__ma0__DEFAULT - ); -#endif - -#if USE_GROUP__Network_interface_registers - REG_SET__R_NETWORK_SA_0( - ma0_low, R_NETWORK_SA_0__ma0_low__DEFAULT - ); -#endif - -#if USE_GROUP__Network_interface_registers - REG_SET__R_NETWORK_SA_1( - ma1_low, R_NETWORK_SA_1__ma1_low__DEFAULT, - ma0_high, R_NETWORK_SA_1__ma0_high__DEFAULT - ); -#endif - -#if USE_GROUP__Network_interface_registers - REG_SET__R_NETWORK_SA_2( - ma1_high, R_NETWORK_SA_2__ma1_high__DEFAULT - ); -#endif - -#if USE_GROUP__Network_interface_registers - REG_SET__R_NETWORK_TR_CTRL( - clr_error, R_NETWORK_TR_CTRL__clr_error__DEFAULT, - delay, R_NETWORK_TR_CTRL__delay__DEFAULT, - cancel, R_NETWORK_TR_CTRL__cancel__DEFAULT, - cd, R_NETWORK_TR_CTRL__cd__DEFAULT, - retry, R_NETWORK_TR_CTRL__retry__DEFAULT, - pad, R_NETWORK_TR_CTRL__pad__DEFAULT, - crc, R_NETWORK_TR_CTRL__crc__DEFAULT - ); -#endif - -#if USE_GROUP__Parallel_printer_port_registers - REG_SET__R_PAR0_CONFIG( - ioe, R_PAR0_CONFIG__ioe__DEFAULT, - iseli, R_PAR0_CONFIG__iseli__DEFAULT, - iautofd, R_PAR0_CONFIG__iautofd__DEFAULT, - istrb, R_PAR0_CONFIG__istrb__DEFAULT, - iinit, R_PAR0_CONFIG__iinit__DEFAULT, - iperr, R_PAR0_CONFIG__iperr__DEFAULT, - iack, R_PAR0_CONFIG__iack__DEFAULT, - ibusy, R_PAR0_CONFIG__ibusy__DEFAULT, - ifault, R_PAR0_CONFIG__ifault__DEFAULT, - isel, R_PAR0_CONFIG__isel__DEFAULT, - ext_mode, R_PAR0_CONFIG__ext_mode__DEFAULT, - wide, R_PAR0_CONFIG__wide__DEFAULT, - dma, R_PAR0_CONFIG__dma__DEFAULT, - rle_in, R_PAR0_CONFIG__rle_in__DEFAULT, - rle_out, R_PAR0_CONFIG__rle_out__DEFAULT, - enable, R_PAR0_CONFIG__enable__DEFAULT, - force, R_PAR0_CONFIG__force__DEFAULT, - ign_ack, R_PAR0_CONFIG__ign_ack__DEFAULT, - oe_ack, R_PAR0_CONFIG__oe_ack__DEFAULT, - mode, R_PAR0_CONFIG__mode__DEFAULT - ); -#endif - -#if USE_GROUP__Parallel_printer_port_registers - REG_SET__R_PAR0_CTRL( - ctrl, R_PAR0_CTRL__ctrl__DEFAULT - ); -#endif - -#if USE_GROUP__Parallel_printer_port_registers - REG_SET__R_PAR0_CTRL_DATA( - peri_int, R_PAR0_CTRL_DATA__peri_int__DEFAULT, - oe, R_PAR0_CTRL_DATA__oe__DEFAULT, - seli, R_PAR0_CTRL_DATA__seli__DEFAULT, - autofd, R_PAR0_CTRL_DATA__autofd__DEFAULT, - strb, R_PAR0_CTRL_DATA__strb__DEFAULT, - init, R_PAR0_CTRL_DATA__init__DEFAULT, - ecp_cmd, R_PAR0_CTRL_DATA__ecp_cmd__DEFAULT, - data, R_PAR0_CTRL_DATA__data__DEFAULT - ); -#endif - -#if USE_GROUP__Parallel_printer_port_registers - REG_SET__R_PAR0_DELAY( - fine_hold, R_PAR0_DELAY__fine_hold__DEFAULT, - hold, R_PAR0_DELAY__hold__DEFAULT, - fine_strb, R_PAR0_DELAY__fine_strb__DEFAULT, - strobe, R_PAR0_DELAY__strobe__DEFAULT, - fine_setup, R_PAR0_DELAY__fine_setup__DEFAULT, - setup, R_PAR0_DELAY__setup__DEFAULT - ); -#endif - -#if USE_GROUP__Parallel_printer_port_registers - REG_SET__R_PAR1_CONFIG( - ioe, R_PAR1_CONFIG__ioe__DEFAULT, - iseli, R_PAR1_CONFIG__iseli__DEFAULT, - iautofd, R_PAR1_CONFIG__iautofd__DEFAULT, - istrb, R_PAR1_CONFIG__istrb__DEFAULT, - iinit, R_PAR1_CONFIG__iinit__DEFAULT, - iperr, R_PAR1_CONFIG__iperr__DEFAULT, - iack, R_PAR1_CONFIG__iack__DEFAULT, - ibusy, R_PAR1_CONFIG__ibusy__DEFAULT, - ifault, R_PAR1_CONFIG__ifault__DEFAULT, - isel, R_PAR1_CONFIG__isel__DEFAULT, - ext_mode, R_PAR1_CONFIG__ext_mode__DEFAULT, - dma, R_PAR1_CONFIG__dma__DEFAULT, - rle_in, R_PAR1_CONFIG__rle_in__DEFAULT, - rle_out, R_PAR1_CONFIG__rle_out__DEFAULT, - enable, R_PAR1_CONFIG__enable__DEFAULT, - force, R_PAR1_CONFIG__force__DEFAULT, - ign_ack, R_PAR1_CONFIG__ign_ack__DEFAULT, - oe_ack, R_PAR1_CONFIG__oe_ack__DEFAULT, - mode, R_PAR1_CONFIG__mode__DEFAULT - ); -#endif - -#if USE_GROUP__Parallel_printer_port_registers - REG_SET__R_PAR1_CTRL( - ctrl, R_PAR1_CTRL__ctrl__DEFAULT - ); -#endif - -#if USE_GROUP__Parallel_printer_port_registers - REG_SET__R_PAR1_CTRL_DATA( - peri_int, R_PAR1_CTRL_DATA__peri_int__DEFAULT, - oe, R_PAR1_CTRL_DATA__oe__DEFAULT, - seli, R_PAR1_CTRL_DATA__seli__DEFAULT, - autofd, R_PAR1_CTRL_DATA__autofd__DEFAULT, - strb, R_PAR1_CTRL_DATA__strb__DEFAULT, - init, R_PAR1_CTRL_DATA__init__DEFAULT, - ecp_cmd, R_PAR1_CTRL_DATA__ecp_cmd__DEFAULT, - data, R_PAR1_CTRL_DATA__data__DEFAULT - ); -#endif - -#if USE_GROUP__Parallel_printer_port_registers - REG_SET__R_PAR1_DELAY( - fine_hold, R_PAR1_DELAY__fine_hold__DEFAULT, - hold, R_PAR1_DELAY__hold__DEFAULT, - fine_strb, R_PAR1_DELAY__fine_strb__DEFAULT, - strobe, R_PAR1_DELAY__strobe__DEFAULT, - fine_setup, R_PAR1_DELAY__fine_setup__DEFAULT, - setup, R_PAR1_DELAY__setup__DEFAULT - ); -#endif - -#if USE_GROUP__General_port_configuration_registers - REG_SET__R_PORT_PA_DATA( - data_out, R_PORT_PA_DATA__data_out__DEFAULT - ); -#endif - -#if USE_GROUP__General_port_configuration_registers - REG_SET__R_PORT_PA_DIR( - dir7, R_PORT_PA_DIR__dir7__DEFAULT, - dir6, R_PORT_PA_DIR__dir6__DEFAULT, - dir5, R_PORT_PA_DIR__dir5__DEFAULT, - dir4, R_PORT_PA_DIR__dir4__DEFAULT, - dir3, R_PORT_PA_DIR__dir3__DEFAULT, - dir2, R_PORT_PA_DIR__dir2__DEFAULT, - dir1, R_PORT_PA_DIR__dir1__DEFAULT, - dir0, R_PORT_PA_DIR__dir0__DEFAULT - ); -#endif - -#if USE_GROUP__General_port_configuration_registers - REG_SET__R_PORT_PA_SET( - dir7, R_PORT_PA_SET__dir7__DEFAULT, - dir6, R_PORT_PA_SET__dir6__DEFAULT, - dir5, R_PORT_PA_SET__dir5__DEFAULT, - dir4, R_PORT_PA_SET__dir4__DEFAULT, - dir3, R_PORT_PA_SET__dir3__DEFAULT, - dir2, R_PORT_PA_SET__dir2__DEFAULT, - dir1, R_PORT_PA_SET__dir1__DEFAULT, - dir0, R_PORT_PA_SET__dir0__DEFAULT, - data_out, R_PORT_PA_SET__data_out__DEFAULT - ); -#endif - -#if USE_GROUP__General_port_configuration_registers - REG_SET__R_PORT_PB_CONFIG( - cs7, R_PORT_PB_CONFIG__cs7__DEFAULT, - cs6, R_PORT_PB_CONFIG__cs6__DEFAULT, - cs5, R_PORT_PB_CONFIG__cs5__DEFAULT, - cs4, R_PORT_PB_CONFIG__cs4__DEFAULT, - cs3, R_PORT_PB_CONFIG__cs3__DEFAULT, - cs2, R_PORT_PB_CONFIG__cs2__DEFAULT, - scsi1, R_PORT_PB_CONFIG__scsi1__DEFAULT, - scsi0, R_PORT_PB_CONFIG__scsi0__DEFAULT - ); -#endif - -#if USE_GROUP__General_port_configuration_registers - REG_SET__R_PORT_PB_DATA( - data_out, R_PORT_PB_DATA__data_out__DEFAULT - ); -#endif - -#if USE_GROUP__General_port_configuration_registers - REG_SET__R_PORT_PB_DIR( - dir7, R_PORT_PB_DIR__dir7__DEFAULT, - dir6, R_PORT_PB_DIR__dir6__DEFAULT, - dir5, R_PORT_PB_DIR__dir5__DEFAULT, - dir4, R_PORT_PB_DIR__dir4__DEFAULT, - dir3, R_PORT_PB_DIR__dir3__DEFAULT, - dir2, R_PORT_PB_DIR__dir2__DEFAULT, - dir1, R_PORT_PB_DIR__dir1__DEFAULT, - dir0, R_PORT_PB_DIR__dir0__DEFAULT - ); -#endif - -#if USE_GROUP__General_port_configuration_registers - REG_SET__R_PORT_PB_I2C( - syncser3, R_PORT_PB_I2C__syncser3__DEFAULT, - syncser1, R_PORT_PB_I2C__syncser1__DEFAULT, - i2c_en, R_PORT_PB_I2C__i2c_en__DEFAULT, - i2c_d, R_PORT_PB_I2C__i2c_d__DEFAULT, - i2c_clk, R_PORT_PB_I2C__i2c_clk__DEFAULT, - i2c_oe_, R_PORT_PB_I2C__i2c_oe___DEFAULT - ); -#endif - -#if USE_GROUP__General_port_configuration_registers - REG_SET__R_PORT_PB_SET( - syncser3, R_PORT_PB_SET__syncser3__DEFAULT, - syncser1, R_PORT_PB_SET__syncser1__DEFAULT, - i2c_en, R_PORT_PB_SET__i2c_en__DEFAULT, - i2c_d, R_PORT_PB_SET__i2c_d__DEFAULT, - i2c_clk, R_PORT_PB_SET__i2c_clk__DEFAULT, - i2c_oe_, R_PORT_PB_SET__i2c_oe___DEFAULT, - cs7, R_PORT_PB_SET__cs7__DEFAULT, - cs6, R_PORT_PB_SET__cs6__DEFAULT, - cs5, R_PORT_PB_SET__cs5__DEFAULT, - cs4, R_PORT_PB_SET__cs4__DEFAULT, - cs3, R_PORT_PB_SET__cs3__DEFAULT, - cs2, R_PORT_PB_SET__cs2__DEFAULT, - scsi1, R_PORT_PB_SET__scsi1__DEFAULT, - scsi0, R_PORT_PB_SET__scsi0__DEFAULT, - dir7, R_PORT_PB_SET__dir7__DEFAULT, - dir6, R_PORT_PB_SET__dir6__DEFAULT, - dir5, R_PORT_PB_SET__dir5__DEFAULT, - dir4, R_PORT_PB_SET__dir4__DEFAULT, - dir3, R_PORT_PB_SET__dir3__DEFAULT, - dir2, R_PORT_PB_SET__dir2__DEFAULT, - dir1, R_PORT_PB_SET__dir1__DEFAULT, - dir0, R_PORT_PB_SET__dir0__DEFAULT, - data_out, R_PORT_PB_SET__data_out__DEFAULT - ); -#endif - -#if USE_GROUP__SCSI_registers - REG_SET__R_SCSI0_CMD( - asynch_setup, R_SCSI0_CMD__asynch_setup__DEFAULT, - command, R_SCSI0_CMD__command__DEFAULT - ); -#endif - -#if USE_GROUP__SCSI_registers - REG_SET__R_SCSI0_CMD_DATA( - parity_in, R_SCSI0_CMD_DATA__parity_in__DEFAULT, - skip, R_SCSI0_CMD_DATA__skip__DEFAULT, - clr_status, R_SCSI0_CMD_DATA__clr_status__DEFAULT, - asynch_setup, R_SCSI0_CMD_DATA__asynch_setup__DEFAULT, - command, R_SCSI0_CMD_DATA__command__DEFAULT, - data_out, R_SCSI0_CMD_DATA__data_out__DEFAULT - ); -#endif - -#if USE_GROUP__SCSI_registers - REG_SET__R_SCSI0_CTRL( - id_type, R_SCSI0_CTRL__id_type__DEFAULT, - sel_timeout, R_SCSI0_CTRL__sel_timeout__DEFAULT, - synch_per, R_SCSI0_CTRL__synch_per__DEFAULT, - rst, R_SCSI0_CTRL__rst__DEFAULT, - atn, R_SCSI0_CTRL__atn__DEFAULT, - my_id, R_SCSI0_CTRL__my_id__DEFAULT, - target_id, R_SCSI0_CTRL__target_id__DEFAULT, - fast_20, R_SCSI0_CTRL__fast_20__DEFAULT, - bus_width, R_SCSI0_CTRL__bus_width__DEFAULT, - synch, R_SCSI0_CTRL__synch__DEFAULT, - enable, R_SCSI0_CTRL__enable__DEFAULT - ); -#endif - -#if USE_GROUP__SCSI_registers - REG_SET__R_SCSI0_DATA( - data_out, R_SCSI0_DATA__data_out__DEFAULT - ); -#endif - -#if USE_GROUP__SCSI_registers - REG_SET__R_SCSI0_STATUS_CTRL( - parity_in, R_SCSI0_STATUS_CTRL__parity_in__DEFAULT, - skip, R_SCSI0_STATUS_CTRL__skip__DEFAULT, - clr_status, R_SCSI0_STATUS_CTRL__clr_status__DEFAULT - ); -#endif - -#if USE_GROUP__SCSI_registers - REG_SET__R_SCSI1_CMD( - asynch_setup, R_SCSI1_CMD__asynch_setup__DEFAULT, - command, R_SCSI1_CMD__command__DEFAULT - ); -#endif - -#if USE_GROUP__SCSI_registers - REG_SET__R_SCSI1_CMD_DATA( - parity_in, R_SCSI1_CMD_DATA__parity_in__DEFAULT, - skip, R_SCSI1_CMD_DATA__skip__DEFAULT, - clr_status, R_SCSI1_CMD_DATA__clr_status__DEFAULT, - asynch_setup, R_SCSI1_CMD_DATA__asynch_setup__DEFAULT, - command, R_SCSI1_CMD_DATA__command__DEFAULT, - data_out, R_SCSI1_CMD_DATA__data_out__DEFAULT - ); -#endif - -#if USE_GROUP__SCSI_registers - REG_SET__R_SCSI1_CTRL( - id_type, R_SCSI1_CTRL__id_type__DEFAULT, - sel_timeout, R_SCSI1_CTRL__sel_timeout__DEFAULT, - synch_per, R_SCSI1_CTRL__synch_per__DEFAULT, - rst, R_SCSI1_CTRL__rst__DEFAULT, - atn, R_SCSI1_CTRL__atn__DEFAULT, - my_id, R_SCSI1_CTRL__my_id__DEFAULT, - target_id, R_SCSI1_CTRL__target_id__DEFAULT, - fast_20, R_SCSI1_CTRL__fast_20__DEFAULT, - bus_width, R_SCSI1_CTRL__bus_width__DEFAULT, - synch, R_SCSI1_CTRL__synch__DEFAULT, - enable, R_SCSI1_CTRL__enable__DEFAULT - ); -#endif - -#if USE_GROUP__SCSI_registers - REG_SET__R_SCSI1_DATA( - data_out, R_SCSI1_DATA__data_out__DEFAULT - ); -#endif - -#if USE_GROUP__SCSI_registers - REG_SET__R_SCSI1_STATUS_CTRL( - parity_in, R_SCSI1_STATUS_CTRL__parity_in__DEFAULT, - skip, R_SCSI1_STATUS_CTRL__skip__DEFAULT, - clr_status, R_SCSI1_STATUS_CTRL__clr_status__DEFAULT - ); -#endif - -#if USE_GROUP__Bus_interface_configuration_registers - REG_SET__R_SDRAM_CONFIG( - wmm1, R_SDRAM_CONFIG__wmm1__DEFAULT, - wmm0, R_SDRAM_CONFIG__wmm0__DEFAULT, - sh1, R_SDRAM_CONFIG__sh1__DEFAULT, - sh0, R_SDRAM_CONFIG__sh0__DEFAULT, - w, R_SDRAM_CONFIG__w__DEFAULT, - type1, R_SDRAM_CONFIG__type1__DEFAULT, - type0, R_SDRAM_CONFIG__type0__DEFAULT, - group_sel, R_SDRAM_CONFIG__group_sel__DEFAULT, - ca1, R_SDRAM_CONFIG__ca1__DEFAULT, - bank_sel1, R_SDRAM_CONFIG__bank_sel1__DEFAULT, - ca0, R_SDRAM_CONFIG__ca0__DEFAULT, - bank_sel0, R_SDRAM_CONFIG__bank_sel0__DEFAULT - ); -#endif - -#if USE_GROUP__Bus_interface_configuration_registers - REG_SET__R_SDRAM_TIMING( - sdram, R_SDRAM_TIMING__sdram__DEFAULT, - mrs_data, R_SDRAM_TIMING__mrs_data__DEFAULT, - ref, R_SDRAM_TIMING__ref__DEFAULT, - ddr, R_SDRAM_TIMING__ddr__DEFAULT, - clk100, R_SDRAM_TIMING__clk100__DEFAULT, - ps, R_SDRAM_TIMING__ps__DEFAULT, - cmd, R_SDRAM_TIMING__cmd__DEFAULT, - pde, R_SDRAM_TIMING__pde__DEFAULT, - rc, R_SDRAM_TIMING__rc__DEFAULT, - rp, R_SDRAM_TIMING__rp__DEFAULT, - rcd, R_SDRAM_TIMING__rcd__DEFAULT, - cl, R_SDRAM_TIMING__cl__DEFAULT - ); -#endif - -#if USE_GROUP__Serial_port_registers - REG_SET__R_SERIAL0_BAUD( - tr_baud, R_SERIAL0_BAUD__tr_baud__DEFAULT, - rec_baud, R_SERIAL0_BAUD__rec_baud__DEFAULT - ); -#endif - -#if USE_GROUP__Serial_port_registers - REG_SET__R_SERIAL0_CTRL( - tr_baud, R_SERIAL0_CTRL__tr_baud__DEFAULT, - rec_baud, R_SERIAL0_CTRL__rec_baud__DEFAULT, - dma_err, R_SERIAL0_CTRL__dma_err__DEFAULT, - rec_enable, R_SERIAL0_CTRL__rec_enable__DEFAULT, - rts_, R_SERIAL0_CTRL__rts___DEFAULT, - sampling, R_SERIAL0_CTRL__sampling__DEFAULT, - rec_stick_par, R_SERIAL0_CTRL__rec_stick_par__DEFAULT, - rec_par, R_SERIAL0_CTRL__rec_par__DEFAULT, - rec_par_en, R_SERIAL0_CTRL__rec_par_en__DEFAULT, - rec_bitnr, R_SERIAL0_CTRL__rec_bitnr__DEFAULT, - txd, R_SERIAL0_CTRL__txd__DEFAULT, - tr_enable, R_SERIAL0_CTRL__tr_enable__DEFAULT, - auto_cts, R_SERIAL0_CTRL__auto_cts__DEFAULT, - stop_bits, R_SERIAL0_CTRL__stop_bits__DEFAULT, - tr_stick_par, R_SERIAL0_CTRL__tr_stick_par__DEFAULT, - tr_par, R_SERIAL0_CTRL__tr_par__DEFAULT, - tr_par_en, R_SERIAL0_CTRL__tr_par_en__DEFAULT, - tr_bitnr, R_SERIAL0_CTRL__tr_bitnr__DEFAULT, - data_out, R_SERIAL0_CTRL__data_out__DEFAULT - ); -#endif - -#if USE_GROUP__Serial_port_registers - REG_SET__R_SERIAL0_REC_CTRL( - dma_err, R_SERIAL0_REC_CTRL__dma_err__DEFAULT, - rec_enable, R_SERIAL0_REC_CTRL__rec_enable__DEFAULT, - rts_, R_SERIAL0_REC_CTRL__rts___DEFAULT, - sampling, R_SERIAL0_REC_CTRL__sampling__DEFAULT, - rec_stick_par, R_SERIAL0_REC_CTRL__rec_stick_par__DEFAULT, - rec_par, R_SERIAL0_REC_CTRL__rec_par__DEFAULT, - rec_par_en, R_SERIAL0_REC_CTRL__rec_par_en__DEFAULT, - rec_bitnr, R_SERIAL0_REC_CTRL__rec_bitnr__DEFAULT - ); -#endif - -#if USE_GROUP__Serial_port_registers - REG_SET__R_SERIAL0_TR_CTRL( - txd, R_SERIAL0_TR_CTRL__txd__DEFAULT, - tr_enable, R_SERIAL0_TR_CTRL__tr_enable__DEFAULT, - auto_cts, R_SERIAL0_TR_CTRL__auto_cts__DEFAULT, - stop_bits, R_SERIAL0_TR_CTRL__stop_bits__DEFAULT, - tr_stick_par, R_SERIAL0_TR_CTRL__tr_stick_par__DEFAULT, - tr_par, R_SERIAL0_TR_CTRL__tr_par__DEFAULT, - tr_par_en, R_SERIAL0_TR_CTRL__tr_par_en__DEFAULT, - tr_bitnr, R_SERIAL0_TR_CTRL__tr_bitnr__DEFAULT - ); -#endif - -#if USE_GROUP__Serial_port_registers - REG_SET__R_SERIAL0_TR_DATA( - data_out, R_SERIAL0_TR_DATA__data_out__DEFAULT - ); -#endif - -#if USE_GROUP__Serial_port_registers - REG_SET__R_SERIAL0_XOFF( - tx_stop, R_SERIAL0_XOFF__tx_stop__DEFAULT, - auto_xoff, R_SERIAL0_XOFF__auto_xoff__DEFAULT, - xoff_char, R_SERIAL0_XOFF__xoff_char__DEFAULT - ); -#endif - -#if USE_GROUP__Serial_port_registers - REG_SET__R_SERIAL1_BAUD( - tr_baud, R_SERIAL1_BAUD__tr_baud__DEFAULT, - rec_baud, R_SERIAL1_BAUD__rec_baud__DEFAULT - ); -#endif - -#if USE_GROUP__Serial_port_registers - REG_SET__R_SERIAL1_CTRL( - tr_baud, R_SERIAL1_CTRL__tr_baud__DEFAULT, - rec_baud, R_SERIAL1_CTRL__rec_baud__DEFAULT, - dma_err, R_SERIAL1_CTRL__dma_err__DEFAULT, - rec_enable, R_SERIAL1_CTRL__rec_enable__DEFAULT, - rts_, R_SERIAL1_CTRL__rts___DEFAULT, - sampling, R_SERIAL1_CTRL__sampling__DEFAULT, - rec_stick_par, R_SERIAL1_CTRL__rec_stick_par__DEFAULT, - rec_par, R_SERIAL1_CTRL__rec_par__DEFAULT, - rec_par_en, R_SERIAL1_CTRL__rec_par_en__DEFAULT, - rec_bitnr, R_SERIAL1_CTRL__rec_bitnr__DEFAULT, - txd, R_SERIAL1_CTRL__txd__DEFAULT, - tr_enable, R_SERIAL1_CTRL__tr_enable__DEFAULT, - auto_cts, R_SERIAL1_CTRL__auto_cts__DEFAULT, - stop_bits, R_SERIAL1_CTRL__stop_bits__DEFAULT, - tr_stick_par, R_SERIAL1_CTRL__tr_stick_par__DEFAULT, - tr_par, R_SERIAL1_CTRL__tr_par__DEFAULT, - tr_par_en, R_SERIAL1_CTRL__tr_par_en__DEFAULT, - tr_bitnr, R_SERIAL1_CTRL__tr_bitnr__DEFAULT, - data_out, R_SERIAL1_CTRL__data_out__DEFAULT - ); -#endif - -#if USE_GROUP__Serial_port_registers - REG_SET__R_SERIAL1_REC_CTRL( - dma_err, R_SERIAL1_REC_CTRL__dma_err__DEFAULT, - rec_enable, R_SERIAL1_REC_CTRL__rec_enable__DEFAULT, - rts_, R_SERIAL1_REC_CTRL__rts___DEFAULT, - sampling, R_SERIAL1_REC_CTRL__sampling__DEFAULT, - rec_stick_par, R_SERIAL1_REC_CTRL__rec_stick_par__DEFAULT, - rec_par, R_SERIAL1_REC_CTRL__rec_par__DEFAULT, - rec_par_en, R_SERIAL1_REC_CTRL__rec_par_en__DEFAULT, - rec_bitnr, R_SERIAL1_REC_CTRL__rec_bitnr__DEFAULT - ); -#endif - -#if USE_GROUP__Serial_port_registers - REG_SET__R_SERIAL1_TR_CTRL( - txd, R_SERIAL1_TR_CTRL__txd__DEFAULT, - tr_enable, R_SERIAL1_TR_CTRL__tr_enable__DEFAULT, - auto_cts, R_SERIAL1_TR_CTRL__auto_cts__DEFAULT, - stop_bits, R_SERIAL1_TR_CTRL__stop_bits__DEFAULT, - tr_stick_par, R_SERIAL1_TR_CTRL__tr_stick_par__DEFAULT, - tr_par, R_SERIAL1_TR_CTRL__tr_par__DEFAULT, - tr_par_en, R_SERIAL1_TR_CTRL__tr_par_en__DEFAULT, - tr_bitnr, R_SERIAL1_TR_CTRL__tr_bitnr__DEFAULT - ); -#endif - -#if USE_GROUP__Serial_port_registers - REG_SET__R_SERIAL1_TR_DATA( - data_out, R_SERIAL1_TR_DATA__data_out__DEFAULT - ); -#endif - -#if USE_GROUP__Serial_port_registers - REG_SET__R_SERIAL1_XOFF( - tx_stop, R_SERIAL1_XOFF__tx_stop__DEFAULT, - auto_xoff, R_SERIAL1_XOFF__auto_xoff__DEFAULT, - xoff_char, R_SERIAL1_XOFF__xoff_char__DEFAULT - ); -#endif - -#if USE_GROUP__Serial_port_registers - REG_SET__R_SERIAL2_BAUD( - tr_baud, R_SERIAL2_BAUD__tr_baud__DEFAULT, - rec_baud, R_SERIAL2_BAUD__rec_baud__DEFAULT - ); -#endif - -#if USE_GROUP__Serial_port_registers - REG_SET__R_SERIAL2_CTRL( - tr_baud, R_SERIAL2_CTRL__tr_baud__DEFAULT, - rec_baud, R_SERIAL2_CTRL__rec_baud__DEFAULT, - dma_err, R_SERIAL2_CTRL__dma_err__DEFAULT, - rec_enable, R_SERIAL2_CTRL__rec_enable__DEFAULT, - rts_, R_SERIAL2_CTRL__rts___DEFAULT, - sampling, R_SERIAL2_CTRL__sampling__DEFAULT, - rec_stick_par, R_SERIAL2_CTRL__rec_stick_par__DEFAULT, - rec_par, R_SERIAL2_CTRL__rec_par__DEFAULT, - rec_par_en, R_SERIAL2_CTRL__rec_par_en__DEFAULT, - rec_bitnr, R_SERIAL2_CTRL__rec_bitnr__DEFAULT, - txd, R_SERIAL2_CTRL__txd__DEFAULT, - tr_enable, R_SERIAL2_CTRL__tr_enable__DEFAULT, - auto_cts, R_SERIAL2_CTRL__auto_cts__DEFAULT, - stop_bits, R_SERIAL2_CTRL__stop_bits__DEFAULT, - tr_stick_par, R_SERIAL2_CTRL__tr_stick_par__DEFAULT, - tr_par, R_SERIAL2_CTRL__tr_par__DEFAULT, - tr_par_en, R_SERIAL2_CTRL__tr_par_en__DEFAULT, - tr_bitnr, R_SERIAL2_CTRL__tr_bitnr__DEFAULT, - data_out, R_SERIAL2_CTRL__data_out__DEFAULT - ); -#endif - -#if USE_GROUP__Serial_port_registers - REG_SET__R_SERIAL2_REC_CTRL( - dma_err, R_SERIAL2_REC_CTRL__dma_err__DEFAULT, - rec_enable, R_SERIAL2_REC_CTRL__rec_enable__DEFAULT, - rts_, R_SERIAL2_REC_CTRL__rts___DEFAULT, - sampling, R_SERIAL2_REC_CTRL__sampling__DEFAULT, - rec_stick_par, R_SERIAL2_REC_CTRL__rec_stick_par__DEFAULT, - rec_par, R_SERIAL2_REC_CTRL__rec_par__DEFAULT, - rec_par_en, R_SERIAL2_REC_CTRL__rec_par_en__DEFAULT, - rec_bitnr, R_SERIAL2_REC_CTRL__rec_bitnr__DEFAULT - ); -#endif - -#if USE_GROUP__Serial_port_registers - REG_SET__R_SERIAL2_TR_CTRL( - txd, R_SERIAL2_TR_CTRL__txd__DEFAULT, - tr_enable, R_SERIAL2_TR_CTRL__tr_enable__DEFAULT, - auto_cts, R_SERIAL2_TR_CTRL__auto_cts__DEFAULT, - stop_bits, R_SERIAL2_TR_CTRL__stop_bits__DEFAULT, - tr_stick_par, R_SERIAL2_TR_CTRL__tr_stick_par__DEFAULT, - tr_par, R_SERIAL2_TR_CTRL__tr_par__DEFAULT, - tr_par_en, R_SERIAL2_TR_CTRL__tr_par_en__DEFAULT, - tr_bitnr, R_SERIAL2_TR_CTRL__tr_bitnr__DEFAULT - ); -#endif - -#if USE_GROUP__Serial_port_registers - REG_SET__R_SERIAL2_TR_DATA( - data_out, R_SERIAL2_TR_DATA__data_out__DEFAULT - ); -#endif - -#if USE_GROUP__Serial_port_registers - REG_SET__R_SERIAL2_XOFF( - tx_stop, R_SERIAL2_XOFF__tx_stop__DEFAULT, - auto_xoff, R_SERIAL2_XOFF__auto_xoff__DEFAULT, - xoff_char, R_SERIAL2_XOFF__xoff_char__DEFAULT - ); -#endif - -#if USE_GROUP__Serial_port_registers - REG_SET__R_SERIAL3_BAUD( - tr_baud, R_SERIAL3_BAUD__tr_baud__DEFAULT, - rec_baud, R_SERIAL3_BAUD__rec_baud__DEFAULT - ); -#endif - -#if USE_GROUP__Serial_port_registers - REG_SET__R_SERIAL3_CTRL( - tr_baud, R_SERIAL3_CTRL__tr_baud__DEFAULT, - rec_baud, R_SERIAL3_CTRL__rec_baud__DEFAULT, - dma_err, R_SERIAL3_CTRL__dma_err__DEFAULT, - rec_enable, R_SERIAL3_CTRL__rec_enable__DEFAULT, - rts_, R_SERIAL3_CTRL__rts___DEFAULT, - sampling, R_SERIAL3_CTRL__sampling__DEFAULT, - rec_stick_par, R_SERIAL3_CTRL__rec_stick_par__DEFAULT, - rec_par, R_SERIAL3_CTRL__rec_par__DEFAULT, - rec_par_en, R_SERIAL3_CTRL__rec_par_en__DEFAULT, - rec_bitnr, R_SERIAL3_CTRL__rec_bitnr__DEFAULT, - txd, R_SERIAL3_CTRL__txd__DEFAULT, - tr_enable, R_SERIAL3_CTRL__tr_enable__DEFAULT, - auto_cts, R_SERIAL3_CTRL__auto_cts__DEFAULT, - stop_bits, R_SERIAL3_CTRL__stop_bits__DEFAULT, - tr_stick_par, R_SERIAL3_CTRL__tr_stick_par__DEFAULT, - tr_par, R_SERIAL3_CTRL__tr_par__DEFAULT, - tr_par_en, R_SERIAL3_CTRL__tr_par_en__DEFAULT, - tr_bitnr, R_SERIAL3_CTRL__tr_bitnr__DEFAULT, - data_out, R_SERIAL3_CTRL__data_out__DEFAULT - ); -#endif - -#if USE_GROUP__Serial_port_registers - REG_SET__R_SERIAL3_REC_CTRL( - dma_err, R_SERIAL3_REC_CTRL__dma_err__DEFAULT, - rec_enable, R_SERIAL3_REC_CTRL__rec_enable__DEFAULT, - rts_, R_SERIAL3_REC_CTRL__rts___DEFAULT, - sampling, R_SERIAL3_REC_CTRL__sampling__DEFAULT, - rec_stick_par, R_SERIAL3_REC_CTRL__rec_stick_par__DEFAULT, - rec_par, R_SERIAL3_REC_CTRL__rec_par__DEFAULT, - rec_par_en, R_SERIAL3_REC_CTRL__rec_par_en__DEFAULT, - rec_bitnr, R_SERIAL3_REC_CTRL__rec_bitnr__DEFAULT - ); -#endif - -#if USE_GROUP__Serial_port_registers - REG_SET__R_SERIAL3_TR_CTRL( - txd, R_SERIAL3_TR_CTRL__txd__DEFAULT, - tr_enable, R_SERIAL3_TR_CTRL__tr_enable__DEFAULT, - auto_cts, R_SERIAL3_TR_CTRL__auto_cts__DEFAULT, - stop_bits, R_SERIAL3_TR_CTRL__stop_bits__DEFAULT, - tr_stick_par, R_SERIAL3_TR_CTRL__tr_stick_par__DEFAULT, - tr_par, R_SERIAL3_TR_CTRL__tr_par__DEFAULT, - tr_par_en, R_SERIAL3_TR_CTRL__tr_par_en__DEFAULT, - tr_bitnr, R_SERIAL3_TR_CTRL__tr_bitnr__DEFAULT - ); -#endif - -#if USE_GROUP__Serial_port_registers - REG_SET__R_SERIAL3_TR_DATA( - data_out, R_SERIAL3_TR_DATA__data_out__DEFAULT - ); -#endif - -#if USE_GROUP__Serial_port_registers - REG_SET__R_SERIAL3_XOFF( - tx_stop, R_SERIAL3_XOFF__tx_stop__DEFAULT, - auto_xoff, R_SERIAL3_XOFF__auto_xoff__DEFAULT, - xoff_char, R_SERIAL3_XOFF__xoff_char__DEFAULT - ); -#endif - -#if USE_GROUP__Timer_registers - REG_SET__R_SERIAL_PRESCALE( - ser_presc, R_SERIAL_PRESCALE__ser_presc__DEFAULT - ); -#endif - -#if USE_GROUP__DMA_registers - REG_SET__R_SET_EOP( - ch9_eop, R_SET_EOP__ch9_eop__DEFAULT, - ch7_eop, R_SET_EOP__ch7_eop__DEFAULT, - ch5_eop, R_SET_EOP__ch5_eop__DEFAULT, - ch3_eop, R_SET_EOP__ch3_eop__DEFAULT - ); -#endif - -#if USE_GROUP__Shared_RAM_interface_registers - REG_SET__R_SHARED_RAM_ADDR( - base_addr, R_SHARED_RAM_ADDR__base_addr__DEFAULT - ); -#endif - -#if USE_GROUP__Shared_RAM_interface_registers - REG_SET__R_SHARED_RAM_CONFIG( - width, R_SHARED_RAM_CONFIG__width__DEFAULT, - enable, R_SHARED_RAM_CONFIG__enable__DEFAULT, - pint, R_SHARED_RAM_CONFIG__pint__DEFAULT, - clri, R_SHARED_RAM_CONFIG__clri__DEFAULT - ); -#endif - -#if USE_GROUP__Test_mode_registers - REG_SET__R_SINGLE_STEP( - single_step, R_SINGLE_STEP__single_step__DEFAULT, - step_wr, R_SINGLE_STEP__step_wr__DEFAULT, - step_rd, R_SINGLE_STEP__step_rd__DEFAULT, - step_fetch, R_SINGLE_STEP__step_fetch__DEFAULT - ); -#endif - -#if USE_GROUP__Syncrounous_serial_port_registers - REG_SET__R_SYNC_SERIAL1_CTRL( - tr_baud, R_SYNC_SERIAL1_CTRL__tr_baud__DEFAULT, - dma_enable, R_SYNC_SERIAL1_CTRL__dma_enable__DEFAULT, - mode, R_SYNC_SERIAL1_CTRL__mode__DEFAULT, - error, R_SYNC_SERIAL1_CTRL__error__DEFAULT, - rec_enable, R_SYNC_SERIAL1_CTRL__rec_enable__DEFAULT, - f_synctype, R_SYNC_SERIAL1_CTRL__f_synctype__DEFAULT, - f_syncsize, R_SYNC_SERIAL1_CTRL__f_syncsize__DEFAULT, - f_sync, R_SYNC_SERIAL1_CTRL__f_sync__DEFAULT, - clk_mode, R_SYNC_SERIAL1_CTRL__clk_mode__DEFAULT, - clk_halt, R_SYNC_SERIAL1_CTRL__clk_halt__DEFAULT, - bitorder, R_SYNC_SERIAL1_CTRL__bitorder__DEFAULT, - tr_enable, R_SYNC_SERIAL1_CTRL__tr_enable__DEFAULT, - wordsize, R_SYNC_SERIAL1_CTRL__wordsize__DEFAULT, - buf_empty, R_SYNC_SERIAL1_CTRL__buf_empty__DEFAULT, - buf_full, R_SYNC_SERIAL1_CTRL__buf_full__DEFAULT, - flow_ctrl, R_SYNC_SERIAL1_CTRL__flow_ctrl__DEFAULT, - clk_polarity, R_SYNC_SERIAL1_CTRL__clk_polarity__DEFAULT, - frame_polarity, R_SYNC_SERIAL1_CTRL__frame_polarity__DEFAULT, - status_polarity, R_SYNC_SERIAL1_CTRL__status_polarity__DEFAULT, - clk_driver, R_SYNC_SERIAL1_CTRL__clk_driver__DEFAULT, - frame_driver, R_SYNC_SERIAL1_CTRL__frame_driver__DEFAULT, - status_driver, R_SYNC_SERIAL1_CTRL__status_driver__DEFAULT, - def_out0, R_SYNC_SERIAL1_CTRL__def_out0__DEFAULT - ); -#endif - -#if USE_GROUP__Syncrounous_serial_port_registers - REG_SET__R_SYNC_SERIAL1_TR_BYTE( - data_out, R_SYNC_SERIAL1_TR_BYTE__data_out__DEFAULT - ); -#endif - -#if USE_GROUP__Syncrounous_serial_port_registers - REG_SET__R_SYNC_SERIAL1_TR_DATA( - data_out, R_SYNC_SERIAL1_TR_DATA__data_out__DEFAULT - ); -#endif - -#if USE_GROUP__Syncrounous_serial_port_registers - REG_SET__R_SYNC_SERIAL1_TR_WORD( - data_out, R_SYNC_SERIAL1_TR_WORD__data_out__DEFAULT - ); -#endif - -#if USE_GROUP__Syncrounous_serial_port_registers - REG_SET__R_SYNC_SERIAL3_CTRL( - tr_baud, R_SYNC_SERIAL3_CTRL__tr_baud__DEFAULT, - dma_enable, R_SYNC_SERIAL3_CTRL__dma_enable__DEFAULT, - mode, R_SYNC_SERIAL3_CTRL__mode__DEFAULT, - error, R_SYNC_SERIAL3_CTRL__error__DEFAULT, - rec_enable, R_SYNC_SERIAL3_CTRL__rec_enable__DEFAULT, - f_synctype, R_SYNC_SERIAL3_CTRL__f_synctype__DEFAULT, - f_syncsize, R_SYNC_SERIAL3_CTRL__f_syncsize__DEFAULT, - f_sync, R_SYNC_SERIAL3_CTRL__f_sync__DEFAULT, - clk_mode, R_SYNC_SERIAL3_CTRL__clk_mode__DEFAULT, - clk_halt, R_SYNC_SERIAL3_CTRL__clk_halt__DEFAULT, - bitorder, R_SYNC_SERIAL3_CTRL__bitorder__DEFAULT, - tr_enable, R_SYNC_SERIAL3_CTRL__tr_enable__DEFAULT, - wordsize, R_SYNC_SERIAL3_CTRL__wordsize__DEFAULT, - buf_empty, R_SYNC_SERIAL3_CTRL__buf_empty__DEFAULT, - buf_full, R_SYNC_SERIAL3_CTRL__buf_full__DEFAULT, - flow_ctrl, R_SYNC_SERIAL3_CTRL__flow_ctrl__DEFAULT, - clk_polarity, R_SYNC_SERIAL3_CTRL__clk_polarity__DEFAULT, - frame_polarity, R_SYNC_SERIAL3_CTRL__frame_polarity__DEFAULT, - status_polarity, R_SYNC_SERIAL3_CTRL__status_polarity__DEFAULT, - clk_driver, R_SYNC_SERIAL3_CTRL__clk_driver__DEFAULT, - frame_driver, R_SYNC_SERIAL3_CTRL__frame_driver__DEFAULT, - status_driver, R_SYNC_SERIAL3_CTRL__status_driver__DEFAULT, - def_out0, R_SYNC_SERIAL3_CTRL__def_out0__DEFAULT - ); -#endif - -#if USE_GROUP__Syncrounous_serial_port_registers - REG_SET__R_SYNC_SERIAL3_TR_BYTE( - data_out, R_SYNC_SERIAL3_TR_BYTE__data_out__DEFAULT - ); -#endif - -#if USE_GROUP__Syncrounous_serial_port_registers - REG_SET__R_SYNC_SERIAL3_TR_DATA( - data_out, R_SYNC_SERIAL3_TR_DATA__data_out__DEFAULT - ); -#endif - -#if USE_GROUP__Syncrounous_serial_port_registers - REG_SET__R_SYNC_SERIAL3_TR_WORD( - data_out, R_SYNC_SERIAL3_TR_WORD__data_out__DEFAULT - ); -#endif - -#if USE_GROUP__Timer_registers - REG_SET__R_SYNC_SERIAL_PRESCALE( - clk_sel_u3, R_SYNC_SERIAL_PRESCALE__clk_sel_u3__DEFAULT, - word_stb_sel_u3, R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__DEFAULT, - clk_sel_u1, R_SYNC_SERIAL_PRESCALE__clk_sel_u1__DEFAULT, - word_stb_sel_u1, R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__DEFAULT, - prescaler, R_SYNC_SERIAL_PRESCALE__prescaler__DEFAULT, - warp_mode, R_SYNC_SERIAL_PRESCALE__warp_mode__DEFAULT, - frame_rate, R_SYNC_SERIAL_PRESCALE__frame_rate__DEFAULT, - word_rate, R_SYNC_SERIAL_PRESCALE__word_rate__DEFAULT - ); -#endif - -#if USE_GROUP__Test_mode_registers - REG_SET__R_TEST_MODE( - single_step, R_TEST_MODE__single_step__DEFAULT, - step_wr, R_TEST_MODE__step_wr__DEFAULT, - step_rd, R_TEST_MODE__step_rd__DEFAULT, - step_fetch, R_TEST_MODE__step_fetch__DEFAULT, - mmu_test, R_TEST_MODE__mmu_test__DEFAULT, - usb_test, R_TEST_MODE__usb_test__DEFAULT, - scsi_timer_test, R_TEST_MODE__scsi_timer_test__DEFAULT, - backoff, R_TEST_MODE__backoff__DEFAULT, - snmp_test, R_TEST_MODE__snmp_test__DEFAULT, - snmp_inc, R_TEST_MODE__snmp_inc__DEFAULT, - ser_loop, R_TEST_MODE__ser_loop__DEFAULT, - baudrate, R_TEST_MODE__baudrate__DEFAULT, - timer, R_TEST_MODE__timer__DEFAULT, - cache_test, R_TEST_MODE__cache_test__DEFAULT, - tag_test, R_TEST_MODE__tag_test__DEFAULT, - cache_enable, R_TEST_MODE__cache_enable__DEFAULT - ); -#endif - -#if USE_GROUP__Timer_registers - REG_SET__R_TIMER_CTRL( - timerdiv1, R_TIMER_CTRL__timerdiv1__DEFAULT, - timerdiv0, R_TIMER_CTRL__timerdiv0__DEFAULT, - presc_timer1, R_TIMER_CTRL__presc_timer1__DEFAULT, - i1, R_TIMER_CTRL__i1__DEFAULT, - tm1, R_TIMER_CTRL__tm1__DEFAULT, - clksel1, R_TIMER_CTRL__clksel1__DEFAULT, - presc_ext, R_TIMER_CTRL__presc_ext__DEFAULT, - i0, R_TIMER_CTRL__i0__DEFAULT, - tm0, R_TIMER_CTRL__tm0__DEFAULT, - clksel0, R_TIMER_CTRL__clksel0__DEFAULT - ); -#endif - -#if USE_GROUP__Timer_registers - REG_SET__R_TIMER_PRESCALE( - tim_presc, R_TIMER_PRESCALE__tim_presc__DEFAULT - ); -#endif - -#if USE_GROUP__USB_interface_control_registers - REG_SET__R_USB_IRQ_MASK_CLR( - iso_eof, R_USB_IRQ_MASK_CLR__iso_eof__DEFAULT, - intr_eof, R_USB_IRQ_MASK_CLR__intr_eof__DEFAULT, - iso_eot, R_USB_IRQ_MASK_CLR__iso_eot__DEFAULT, - intr_eot, R_USB_IRQ_MASK_CLR__intr_eot__DEFAULT, - ctl_eot, R_USB_IRQ_MASK_CLR__ctl_eot__DEFAULT, - bulk_eot, R_USB_IRQ_MASK_CLR__bulk_eot__DEFAULT, - epid_attn, R_USB_IRQ_MASK_CLR__epid_attn__DEFAULT, - sof, R_USB_IRQ_MASK_CLR__sof__DEFAULT, - port_status, R_USB_IRQ_MASK_CLR__port_status__DEFAULT, - ctl_status, R_USB_IRQ_MASK_CLR__ctl_status__DEFAULT - ); -#endif - -#if USE_GROUP__USB_interface_control_registers - REG_SET__R_USB_IRQ_MASK_CLR_DEV( - out_eot, R_USB_IRQ_MASK_CLR_DEV__out_eot__DEFAULT, - ep3_in_eot, R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__DEFAULT, - ep2_in_eot, R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__DEFAULT, - ep1_in_eot, R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__DEFAULT, - ep0_in_eot, R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__DEFAULT, - epid_attn, R_USB_IRQ_MASK_CLR_DEV__epid_attn__DEFAULT, - sof, R_USB_IRQ_MASK_CLR_DEV__sof__DEFAULT, - port_status, R_USB_IRQ_MASK_CLR_DEV__port_status__DEFAULT, - ctl_status, R_USB_IRQ_MASK_CLR_DEV__ctl_status__DEFAULT - ); -#endif - -#if USE_GROUP__USB_interface_control_registers - REG_SET__R_USB_IRQ_MASK_SET( - iso_eof, R_USB_IRQ_MASK_SET__iso_eof__DEFAULT, - intr_eof, R_USB_IRQ_MASK_SET__intr_eof__DEFAULT, - iso_eot, R_USB_IRQ_MASK_SET__iso_eot__DEFAULT, - intr_eot, R_USB_IRQ_MASK_SET__intr_eot__DEFAULT, - ctl_eot, R_USB_IRQ_MASK_SET__ctl_eot__DEFAULT, - bulk_eot, R_USB_IRQ_MASK_SET__bulk_eot__DEFAULT, - epid_attn, R_USB_IRQ_MASK_SET__epid_attn__DEFAULT, - sof, R_USB_IRQ_MASK_SET__sof__DEFAULT, - port_status, R_USB_IRQ_MASK_SET__port_status__DEFAULT, - ctl_status, R_USB_IRQ_MASK_SET__ctl_status__DEFAULT - ); -#endif - -#if USE_GROUP__USB_interface_control_registers - REG_SET__R_USB_IRQ_MASK_SET_DEV( - out_eot, R_USB_IRQ_MASK_SET_DEV__out_eot__DEFAULT, - ep3_in_eot, R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__DEFAULT, - ep2_in_eot, R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__DEFAULT, - ep1_in_eot, R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__DEFAULT, - ep0_in_eot, R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__DEFAULT, - epid_attn, R_USB_IRQ_MASK_SET_DEV__epid_attn__DEFAULT, - sof, R_USB_IRQ_MASK_SET_DEV__sof__DEFAULT, - port_status, R_USB_IRQ_MASK_SET_DEV__port_status__DEFAULT, - ctl_status, R_USB_IRQ_MASK_SET_DEV__ctl_status__DEFAULT - ); -#endif - -#if USE_GROUP__USB_interface_control_registers - REG_SET__R_USB_PORT1_DISABLE( - disable, R_USB_PORT1_DISABLE__disable__DEFAULT - ); -#endif - -#if USE_GROUP__USB_interface_control_registers - REG_SET__R_USB_PORT2_DISABLE( - disable, R_USB_PORT2_DISABLE__disable__DEFAULT - ); -#endif - -#if USE_GROUP__Interrupt_mask_and_status_registers - REG_SET__R_VECT_MASK_CLR( - usb, R_VECT_MASK_CLR__usb__DEFAULT, - dma9, R_VECT_MASK_CLR__dma9__DEFAULT, - dma8, R_VECT_MASK_CLR__dma8__DEFAULT, - dma7, R_VECT_MASK_CLR__dma7__DEFAULT, - dma6, R_VECT_MASK_CLR__dma6__DEFAULT, - dma5, R_VECT_MASK_CLR__dma5__DEFAULT, - dma4, R_VECT_MASK_CLR__dma4__DEFAULT, - dma3, R_VECT_MASK_CLR__dma3__DEFAULT, - dma2, R_VECT_MASK_CLR__dma2__DEFAULT, - dma1, R_VECT_MASK_CLR__dma1__DEFAULT, - dma0, R_VECT_MASK_CLR__dma0__DEFAULT, - ext_dma1, R_VECT_MASK_CLR__ext_dma1__DEFAULT, - ext_dma0, R_VECT_MASK_CLR__ext_dma0__DEFAULT, - pa, R_VECT_MASK_CLR__pa__DEFAULT, - irq_intnr, R_VECT_MASK_CLR__irq_intnr__DEFAULT, - sw, R_VECT_MASK_CLR__sw__DEFAULT, - serial, R_VECT_MASK_CLR__serial__DEFAULT, - snmp, R_VECT_MASK_CLR__snmp__DEFAULT, - network, R_VECT_MASK_CLR__network__DEFAULT, - scsi1, R_VECT_MASK_CLR__scsi1__DEFAULT, - scsi0, R_VECT_MASK_CLR__scsi0__DEFAULT, - timer1, R_VECT_MASK_CLR__timer1__DEFAULT, - timer0, R_VECT_MASK_CLR__timer0__DEFAULT, - nmi, R_VECT_MASK_CLR__nmi__DEFAULT, - some, R_VECT_MASK_CLR__some__DEFAULT - ); -#endif - -#if USE_GROUP__Interrupt_mask_and_status_registers - REG_SET__R_VECT_MASK_SET( - usb, R_VECT_MASK_SET__usb__DEFAULT, - dma9, R_VECT_MASK_SET__dma9__DEFAULT, - dma8, R_VECT_MASK_SET__dma8__DEFAULT, - dma7, R_VECT_MASK_SET__dma7__DEFAULT, - dma6, R_VECT_MASK_SET__dma6__DEFAULT, - dma5, R_VECT_MASK_SET__dma5__DEFAULT, - dma4, R_VECT_MASK_SET__dma4__DEFAULT, - dma3, R_VECT_MASK_SET__dma3__DEFAULT, - dma2, R_VECT_MASK_SET__dma2__DEFAULT, - dma1, R_VECT_MASK_SET__dma1__DEFAULT, - dma0, R_VECT_MASK_SET__dma0__DEFAULT, - ext_dma1, R_VECT_MASK_SET__ext_dma1__DEFAULT, - ext_dma0, R_VECT_MASK_SET__ext_dma0__DEFAULT, - pa, R_VECT_MASK_SET__pa__DEFAULT, - irq_intnr, R_VECT_MASK_SET__irq_intnr__DEFAULT, - sw, R_VECT_MASK_SET__sw__DEFAULT, - serial, R_VECT_MASK_SET__serial__DEFAULT, - snmp, R_VECT_MASK_SET__snmp__DEFAULT, - network, R_VECT_MASK_SET__network__DEFAULT, - scsi1, R_VECT_MASK_SET__scsi1__DEFAULT, - scsi0, R_VECT_MASK_SET__scsi0__DEFAULT, - timer1, R_VECT_MASK_SET__timer1__DEFAULT, - timer0, R_VECT_MASK_SET__timer0__DEFAULT, - nmi, R_VECT_MASK_SET__nmi__DEFAULT, - some, R_VECT_MASK_SET__some__DEFAULT - ); -#endif - -#if USE_GROUP__Bus_interface_configuration_registers - REG_SET__R_WAITSTATES( - pcs4_7_zw, R_WAITSTATES__pcs4_7_zw__DEFAULT, - pcs4_7_ew, R_WAITSTATES__pcs4_7_ew__DEFAULT, - pcs4_7_lw, R_WAITSTATES__pcs4_7_lw__DEFAULT, - pcs0_3_zw, R_WAITSTATES__pcs0_3_zw__DEFAULT, - pcs0_3_ew, R_WAITSTATES__pcs0_3_ew__DEFAULT, - pcs0_3_lw, R_WAITSTATES__pcs0_3_lw__DEFAULT, - sram_zw, R_WAITSTATES__sram_zw__DEFAULT, - sram_ew, R_WAITSTATES__sram_ew__DEFAULT, - sram_lw, R_WAITSTATES__sram_lw__DEFAULT, - flash_zw, R_WAITSTATES__flash_zw__DEFAULT, - flash_ew, R_WAITSTATES__flash_ew__DEFAULT, - flash_lw, R_WAITSTATES__flash_lw__DEFAULT - ); -#endif - -#if USE_GROUP__Timer_registers - REG_SET__R_WATCHDOG( - key, R_WATCHDOG__key__DEFAULT, - enable, R_WATCHDOG__enable__DEFAULT - ); -#endif -#endif -} /* init_shadow__hwregs */ diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/src/hwregs.h b/target/linux/etrax-2.6/image/e100boot/src/cbl/src/hwregs.h deleted file mode 100644 index 9210a9faae..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/cbl/src/hwregs.h +++ /dev/null @@ -1,44822 +0,0 @@ -/*!********************************************************************** -*! -*! FILE NAME: hwregs.h -*! -*! DESCRIPTION: Interface to shadow registers. -*! -*! FUNCTIONS: none -*! -*! NOTE: This file is automatically generated, do _not_ edit. -*! Created: Thu Oct 3 01:21:27 2002 -*! By: Id: shadow_gen,v 1.14 2002/10/02 20:31:22 hp Exp -*! From: /n/asic/projects/etrax_ng/doc/work/etrax_ng_regs.rd 1.168 -*! /n/asic/projects/etrax_ng/include//hwregs.ctrl 1.3 -*! -*! MACROS: REG_GET -*! REG_IGET -*! REG_VGET -*! REG_SET -*! REG_ISET -*! REG_VSET -*! REG_SET_VAL -*! REG_SET__register-name (one for each register) -*! REG_SET__register-name__SHADOW (one for each register) -*! REG_MASK__register-name (one for each register) -*! REG_VAL__register-name (one for each register) -*! REG_EQL -*! REG_IEQL -*! REG_VEQL -*! REG_VAL -*! REG_CHK_VAL -*! REG_RD -*! REG_IRD -*! REG_WR -*! REG_IWR -*! REG_ADDR -*! REG_BITNR -*! -*!---------------------------------------------------------------------- -*! HISTORY -*! -*! DATE NAME CHANGES -*! ---- ---- ------- -*! Apr 01 1998 Jan Bengtsson Initial version -*! Oct 01 2002 Hans-Peter Nilsson Large mechanical changes to correct -*! use of the ## operator. -*!---------------------------------------------------------------------- -*! -*! (C) Copyright 1998, 2002 Axis Communications AB, LUND, SWEDEN -*! -*!**********************************************************************/ -/* %Z% %M% %I% %G% */ - -#ifndef __HWREGS_H__ -#define __HWREGS_H__ - -/********************** INCLUDE FILES SECTION **************************/ -#ifndef __ASSEMBLER__ -#include "compiler.h" -#include "debug.h" -#endif /* __ASSEMBLER__ */ - -#include "project.h" -#include "hwregs_def.h" - -#ifndef __ASSEMBLER__ - -#ifndef __REG_GENERAL_1_H__ -#define __REG_GENERAL_1_H__ - -/* -** This part of hwregs.h is common to all shadow -** register modules, and should therefore only be included once to -** avoid macro redefinitions. -*/ - -/* REG_DEBUG is by default controlled by DEBUG from debug.h. */ -#ifndef REG_DEBUG -#ifdef DEBUG -#define REG_DEBUG 1 -#else -#define REG_DEBUG 0 -#endif /* DEBUG */ -#endif /* REG_DEBUG */ - -#endif /* __REG_GENERAL_1_H__ */ - -#endif /* __ASSEMBLER__ */ - -/********************** TYPE DEFINITION SECTION ************************/ -#ifndef __ASSEMBLER__ - -#ifndef REG_NO_SHADOW - -/* Only write only registers need a shadow register. */ - -typedef struct { -#if USE_GROUP__Bus_interface_configuration_registers - byte R_WAITSTATES[4]; - byte R_BUS_CONFIG[4]; - byte R_DRAM_TIMING[4]; - byte R_DRAM_CONFIG[4]; -#endif -#if USE_GROUP__External_DMA_registers - byte R_EXT_DMA_0_CMD[4]; - byte R_EXT_DMA_0_ADDR[4]; - byte R_EXT_DMA_1_CMD[4]; - byte R_EXT_DMA_1_ADDR[4]; -#endif -#if USE_GROUP__Timer_registers - byte R_TIMER_CTRL[4]; - byte R_WATCHDOG[4]; -#endif -#if USE_GROUP__General_config_registers - byte R_GEN_CONFIG[4]; -#endif -#if USE_GROUP__General_port_configuration_registers - byte R_PORT_PA_SET[4]; -#endif -#if USE_GROUP__General_config_registers - byte R_GEN_CONFIG_II[4]; -#endif -#if USE_GROUP__General_port_configuration_registers - byte R_PORT_PB_SET[4]; -#endif -#if USE_GROUP__DMA_registers - byte R_SET_EOP[4]; -#endif -#if USE_GROUP__ATA_interface_registers || \ - USE_GROUP__Parallel_printer_port_registers || \ - USE_GROUP__SCSI_registers || \ - USE_GROUP__Shared_RAM_interface_registers - byte R_ATA_CTRL_DATA[4]; - byte R_ATA_CONFIG[4]; -#endif -#if USE_GROUP__Parallel_printer_port_registers - byte R_PAR0_DELAY[4]; -#endif -#if USE_GROUP__Parallel_printer_port_registers || \ - USE_GROUP__SCSI_registers || \ - USE_GROUP__USB_interface_control_registers - byte R_PAR1_CTRL_DATA[4]; -#endif -#if USE_GROUP__Parallel_printer_port_registers || \ - USE_GROUP__SCSI_registers - byte R_PAR1_CONFIG[4]; -#endif -#if USE_GROUP__Parallel_printer_port_registers - byte R_PAR1_DELAY[4]; -#endif -#if USE_GROUP__Serial_port_registers - byte R_ALT_SER_BAUDRATE[4]; - byte R_SERIAL0_CTRL[4]; - byte R_SERIAL0_XOFF[4]; -#endif -#if USE_GROUP__Serial_port_registers || \ - USE_GROUP__Syncrounous_serial_port_registers || \ - USE_GROUP__USB_interface_control_registers - byte R_SERIAL1_CTRL[4]; -#endif -#if USE_GROUP__Serial_port_registers || \ - USE_GROUP__Syncrounous_serial_port_registers - byte R_SERIAL1_XOFF[4]; -#endif -#if USE_GROUP__Serial_port_registers - byte R_SERIAL2_CTRL[4]; - byte R_SERIAL2_XOFF[4]; -#endif -#if USE_GROUP__Serial_port_registers || \ - USE_GROUP__Syncrounous_serial_port_registers - byte R_SERIAL3_CTRL[4]; - byte R_SERIAL3_XOFF[4]; -#endif -#if USE_GROUP__Network_interface_registers - byte R_NETWORK_SA_0[4]; - byte R_NETWORK_SA_1[4]; - byte R_NETWORK_SA_2[4]; - byte R_NETWORK_GA_0[4]; - byte R_NETWORK_GA_1[4]; - byte R_NETWORK_REC_CONFIG[4]; - byte R_NETWORK_GEN_CONFIG[4]; - byte R_NETWORK_TR_CTRL[4]; - byte R_NETWORK_MGM_CTRL[4]; -#endif -#if USE_GROUP__Interrupt_mask_and_status_registers - byte R_IRQ_MASK0_CLR[4]; - byte R_IRQ_MASK0_SET[4]; - byte R_IRQ_MASK1_CLR[4]; - byte R_IRQ_MASK1_SET[4]; - byte R_IRQ_MASK2_CLR[4]; - byte R_IRQ_MASK2_SET[4]; - byte R_VECT_MASK_CLR[4]; - byte R_VECT_MASK_SET[4]; -#endif -#if USE_GROUP__Timer_registers - byte R_CLOCK_PRESCALE[4]; - byte R_SYNC_SERIAL_PRESCALE[4]; -#endif -#if USE_GROUP__Test_mode_registers - byte R_TEST_MODE[4]; -#endif -#if USE_GROUP__DMA_registers - byte R_DMA_CH0_CLR_INTR[1]; - byte R_DMA_CH1_CLR_INTR[1]; - byte R_DMA_CH2_CLR_INTR[1]; - byte R_DMA_CH3_CLR_INTR[1]; - byte R_DMA_CH4_CLR_INTR[1]; - byte R_DMA_CH8_SUB0_CLR_INTR[1]; - byte R_DMA_CH5_CLR_INTR[1]; - byte R_DMA_CH8_SUB1_CLR_INTR[1]; - byte R_DMA_CH6_CLR_INTR[1]; - byte R_DMA_CH8_SUB2_CLR_INTR[1]; - byte R_DMA_CH7_CLR_INTR[1]; - byte R_DMA_CH8_SUB3_CLR_INTR[1]; - byte R_DMA_CH8_CLR_INTR[1]; - byte R_DMA_CH9_CLR_INTR[1]; -#endif -#if USE_GROUP__USB_interface_control_registers - byte R_USB_IRQ_MASK_SET[2]; - byte R_USB_IRQ_MASK_CLR[2]; -#endif -#if USE_GROUP__MMU_registers - byte R_MMU_CONFIG[4]; - byte R_MMU_KBASE_LO[4]; - byte R_MMU_KBASE_HI[4]; -#endif -} reg_shadow_type__hwregs; - -#else /* REG_NO_SHADOW */ - -typedef const udword reg_shadow_type__hwregs; - -#endif /* REG_NO_SHADOW */ - -extern reg_shadow_type__hwregs reg_shadow__hwregs; - -#if REG_DEBUG - -/* - * Only write only registers need an initiated flag. - * Flag is set to all ones at startup, and cleared to - * zero when initiated. - */ - -#ifndef REG_NO_SHADOW - -typedef struct { -#if USE_GROUP__Bus_interface_configuration_registers - byte R_WAITSTATES[4]; - byte R_BUS_CONFIG[4]; - byte R_DRAM_TIMING[4]; - byte R_DRAM_CONFIG[4]; -#endif -#if USE_GROUP__External_DMA_registers - byte R_EXT_DMA_0_CMD[4]; - byte R_EXT_DMA_0_ADDR[4]; - byte R_EXT_DMA_1_CMD[4]; - byte R_EXT_DMA_1_ADDR[4]; -#endif -#if USE_GROUP__Timer_registers - byte R_TIMER_CTRL[4]; - byte R_WATCHDOG[4]; -#endif -#if USE_GROUP__General_config_registers - byte R_GEN_CONFIG[4]; -#endif -#if USE_GROUP__General_port_configuration_registers - byte R_PORT_PA_SET[4]; -#endif -#if USE_GROUP__General_config_registers - byte R_GEN_CONFIG_II[4]; -#endif -#if USE_GROUP__General_port_configuration_registers - byte R_PORT_PB_SET[4]; -#endif -#if USE_GROUP__DMA_registers - byte R_SET_EOP[4]; -#endif -#if USE_GROUP__ATA_interface_registers || \ - USE_GROUP__Parallel_printer_port_registers || \ - USE_GROUP__SCSI_registers || \ - USE_GROUP__Shared_RAM_interface_registers - byte R_ATA_CTRL_DATA[4]; - byte R_ATA_CONFIG[4]; -#endif -#if USE_GROUP__Parallel_printer_port_registers - byte R_PAR0_DELAY[4]; -#endif -#if USE_GROUP__Parallel_printer_port_registers || \ - USE_GROUP__SCSI_registers || \ - USE_GROUP__USB_interface_control_registers - byte R_PAR1_CTRL_DATA[4]; -#endif -#if USE_GROUP__Parallel_printer_port_registers || \ - USE_GROUP__SCSI_registers - byte R_PAR1_CONFIG[4]; -#endif -#if USE_GROUP__Parallel_printer_port_registers - byte R_PAR1_DELAY[4]; -#endif -#if USE_GROUP__Serial_port_registers - byte R_ALT_SER_BAUDRATE[4]; - byte R_SERIAL0_CTRL[4]; - byte R_SERIAL0_XOFF[4]; -#endif -#if USE_GROUP__Serial_port_registers || \ - USE_GROUP__Syncrounous_serial_port_registers || \ - USE_GROUP__USB_interface_control_registers - byte R_SERIAL1_CTRL[4]; -#endif -#if USE_GROUP__Serial_port_registers || \ - USE_GROUP__Syncrounous_serial_port_registers - byte R_SERIAL1_XOFF[4]; -#endif -#if USE_GROUP__Serial_port_registers - byte R_SERIAL2_CTRL[4]; - byte R_SERIAL2_XOFF[4]; -#endif -#if USE_GROUP__Serial_port_registers || \ - USE_GROUP__Syncrounous_serial_port_registers - byte R_SERIAL3_CTRL[4]; - byte R_SERIAL3_XOFF[4]; -#endif -#if USE_GROUP__Network_interface_registers - byte R_NETWORK_SA_0[4]; - byte R_NETWORK_SA_1[4]; - byte R_NETWORK_SA_2[4]; - byte R_NETWORK_GA_0[4]; - byte R_NETWORK_GA_1[4]; - byte R_NETWORK_REC_CONFIG[4]; - byte R_NETWORK_GEN_CONFIG[4]; - byte R_NETWORK_TR_CTRL[4]; - byte R_NETWORK_MGM_CTRL[4]; -#endif -#if USE_GROUP__Interrupt_mask_and_status_registers - byte R_IRQ_MASK0_CLR[4]; - byte R_IRQ_MASK0_SET[4]; - byte R_IRQ_MASK1_CLR[4]; - byte R_IRQ_MASK1_SET[4]; - byte R_IRQ_MASK2_CLR[4]; - byte R_IRQ_MASK2_SET[4]; - byte R_VECT_MASK_CLR[4]; - byte R_VECT_MASK_SET[4]; -#endif -#if USE_GROUP__Timer_registers - byte R_CLOCK_PRESCALE[4]; - byte R_SYNC_SERIAL_PRESCALE[4]; -#endif -#if USE_GROUP__Test_mode_registers - byte R_TEST_MODE[4]; -#endif -#if USE_GROUP__DMA_registers - byte R_DMA_CH0_CLR_INTR[1]; - byte R_DMA_CH1_CLR_INTR[1]; - byte R_DMA_CH2_CLR_INTR[1]; - byte R_DMA_CH3_CLR_INTR[1]; - byte R_DMA_CH4_CLR_INTR[1]; - byte R_DMA_CH8_SUB0_CLR_INTR[1]; - byte R_DMA_CH5_CLR_INTR[1]; - byte R_DMA_CH8_SUB1_CLR_INTR[1]; - byte R_DMA_CH6_CLR_INTR[1]; - byte R_DMA_CH8_SUB2_CLR_INTR[1]; - byte R_DMA_CH7_CLR_INTR[1]; - byte R_DMA_CH8_SUB3_CLR_INTR[1]; - byte R_DMA_CH8_CLR_INTR[1]; - byte R_DMA_CH9_CLR_INTR[1]; -#endif -#if USE_GROUP__USB_interface_control_registers - byte R_USB_IRQ_MASK_SET[2]; - byte R_USB_IRQ_MASK_CLR[2]; -#endif -#if USE_GROUP__MMU_registers - byte R_MMU_CONFIG[4]; - byte R_MMU_KBASE_LO[4]; - byte R_MMU_KBASE_HI[4]; -#endif -} reg_initiated_type__hwregs; - -#else /* REG_NO_SHADOW */ - -typedef const udword reg_initiated_type__hwregs; - -#endif /* REG_NO_SHADOW */ - -extern reg_initiated_type__hwregs reg_initiated__hwregs; - -#endif /* REG_DEBUG */ - -extern void init_shadow__hwregs(); - -#endif /* __ASSEMBLER__ */ - - -/********************** CONSTANT AND MACRO SECTION *********************/ -#ifndef __REG_GENERAL_2_H__ -#define __REG_GENERAL_2_H__ - -/* -** This part of hwregs.h is common to all shadow -** register modules, and should therefore only be included once to -** avoid macro redefinitions. -*/ - -#ifndef __ASSEMBLER__ - -/* - * Register type-casts - */ -#define REG_TYPECAST_UDWORD (volatile udword*) -#define REG_TYPECAST_RO_UDWORD (const volatile udword*) -#define REG_TYPECAST_UWORD (volatile uword*) -#define REG_TYPECAST_RO_UWORD (const volatile uword*) -#define REG_TYPECAST_BYTE (volatile byte*) -#define REG_TYPECAST_RO_BYTE (const volatile byte*) - -/* - * Shadow register type-casts - */ -#define REG_STYPECAST_UDWORD (udword*) -#define REG_STYPECAST_UWORD (uword*) -#define REG_STYPECAST_BYTE (byte*) - -#else - -/* - * Register type-casts - */ -#define REG_TYPECAST_UDWORD -#define REG_TYPECAST_RO_UDWORD -#define REG_TYPECAST_UWORD -#define REG_TYPECAST_RO_UWORD -#define REG_TYPECAST_BYTE -#define REG_TYPECAST_RO_BYTE - -/* - * Shadow register type-casts - */ -#define REG_STYPECAST_UDWORD -#define REG_STYPECAST_UWORD -#define REG_STYPECAST_BYTE - -#endif - - -#define REG_UDWORD udword -#define REG_UWORD uword -#define REG_BYTE byte - -#define REG__on 0xffffffffU -#define REG__off 0 - -#endif /* __REG_GENERAL_2_H__ */ - -#include "hwregs_int.h" - -#ifndef __REG_GENERAL_3_H__ -#define __REG_GENERAL_3_H__ - -/* -** This part of hwregs.h is common to all shadow -** register modules, and should therefore only be included once to -** avoid macro redefinitions. -*/ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_GET -*# -*# PARAMETERS : reg : Name of a register. -*# field : Name of a field. -*# -*# RETURNS : Value of field field in register reg. -*# -*# SIDE EFFECTS: May evaluate REG_SERROR. -*# -*# DESCRIPTION : Read a field in a register. Also see description -*# of REG_GET_WO, REG_GET_RO, and REG_GET_RW. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to reg and field parameters when -*# passing on to other macros. -*#**********************************************************************/ - -#define REG_GET(reg,field) ( \ - reg##__GET(reg##_, field##_) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_IGET -*# -*# PARAMETERS : i : Interface number. -*# reg : Name of a register. -*# field : Name of a field. -*# -*# RETURNS : Value of field field in register reg. -*# -*# SIDE EFFECTS: May evaluate REG_SERROR, and REG_IERROR. -*# -*# DESCRIPTION : Read a field in a register for interface i. -*# Also see description of REG_IGET_WO, REG_IGET_RO, -*# and REG_IGET_RW. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to reg and field parameters when -*# passing on to other macros. -*#**********************************************************************/ - -#define REG_IGET(i,reg,field) ( \ - reg##__IGET(i, reg##_, field##_) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VGET -*# -*# PARAMETERS : reg : Name of a register. -*# field : Name of a field. -*# var : Variable or value to read from. -*# -*# RETURNS : Value of field field in variable var. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Interprets variable var as register reg, and read field -*# field from variable var. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*#**********************************************************************/ - -#define REG_VGET(reg,field,var) ( \ - ((reg##__TYPE var) & reg##__##field##__##field##__MASK) >> \ - reg##__##field##__BITNR \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET -*# -*# PARAMETERS : reg : Name of a register. -*# field : Name of a field. -*# val : Value to write to field. -*# -*# RETURNS : Integer value written to complete register. -*# -*# SIDE EFFECTS: May evaluate REG_SERROR and REG_VERROR. -*# -*# DESCRIPTION : Write val parameter to field field in register reg. -*# Parameter reg must be a write only or read write -*# register. Also see description of REG_SET_WO, and -*# REG_SET_RW. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to reg and field parameters when -*# passing on to other macros. -*#**********************************************************************/ - -#define REG_SET(reg,field,val) ( \ - reg##__SET(reg##_, field##_, val) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_ISET -*# -*# PARAMETERS : i : Interface number. -*# reg : Name of a register. -*# field : Name of a field. -*# val : Value to write to field. -*# -*# RETURNS : Integer value written to complete register. -*# -*# SIDE EFFECTS: May evaluate REG_IERROR, REG_SERROR, and REG_VERROR. -*# -*# DESCRIPTION : Write val parameter to field field in register reg -*# of interface i. Parameter reg must be a write only -*# or read write register. Also see description of -*# REG_ISET_WO, and REG_ISET_RW. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to reg and field parameters when -*# passing on to other macros. -*#**********************************************************************/ - -#define REG_ISET(i,reg,field,val) ( \ - reg##__ISET(i, reg##_, field##_, val) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VSET -*# -*# PARAMETERS : reg : Name of a register. -*# field : Name of a field. -*# val : Value to write to field. -*# var : Variable to write to. -*# -*# RETURNS : Integer value of variable var after write. -*# -*# SIDE EFFECTS: May evaluate REG_VERROR. -*# -*# DESCRIPTION : Interpret variable var as register reg, and write val -*# parameter to field field in variable var. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to reg and field parameters when -*# passing on to other macros. -*#**********************************************************************/ - -#define REG_VSET(reg,field,val,var) ( \ - var = \ - ((reg##__TYPE var) & REG_IMASK (reg##_, field##_)) | \ - (reg##__##field##__##field##__VAL(reg##_, field##_, val) << \ - reg##__##field##__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET_VAL -*# -*# PARAMETERS : reg : Name of a register. -*# field : Name of a field. -*# val : Integer value to write to symbolic field. -*# -*# RETURNS : Integer value written to complete register. -*# -*# SIDE EFFECTS: May evaluate REG_SERROR and REG_VERROR. -*# -*# DESCRIPTION : Write val parameter to field field in register reg. -*# Parameter reg must be a write only or read write register. -*# Also see description of REG_SET_VAL_WO, and REG_SET_VAL_RW. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to reg and field parameters when -*# passing on to other macros. -*#**********************************************************************/ - -#define REG_SET_VAL(reg,field,val) ( \ - reg##__SET_VAL(reg##_, field##_, val) \ -) - -/* - * See end of file for these. - * - * #define REG_SET__register-name - * #define REG_SET__register-name__SHADOW - * #define REG_MASK__register-name - * #define REG_VAL__register-name - */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_EQL -*# -*# PARAMETERS : reg : Name of a register. -*# field : Name of a field. -*# val : Value to compare with field. -*# -*# RETURNS : TRUE, FALSE -*# -*# SIDE EFFECTS: May evaluate REG_SERROR and REG_VERROR. -*# -*# DESCRIPTION : Compare val parameter with field field in register reg. -*# Also description of REG_EQL_WO, REG_EQL_RO, and -*# REG_EQL_RW. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to reg and field parameters when -*# passing on to other macros. -*#**********************************************************************/ -#define REG_EQL(reg,field,val) ( \ - reg##__EQL(reg##_, field##_, val) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_IEQL -*# -*# PARAMETERS : i : Interface number. -*# reg : Name of a register. -*# field : Name of a field. -*# val : Value to compare with field. -*# -*# RETURNS : TRUE, FALSE -*# -*# SIDE EFFECTS: May evaluate REG_VERROR, REG_IERROR, and REG_SERROR. -*# -*# DESCRIPTION : Compare val parameter with field field in register reg -*# of interface i. Also see description of REG_IEQL_WO, -*# REG_IEQ_RO, and REG_IEQL_RW. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to reg and field parameters when -*# passing on to other macros. -*#**********************************************************************/ - -#define REG_IEQL(i,reg,field,val) ( \ - reg##__IEQL(i,reg##_,field##_,val) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VEQL -*# -*# PARAMETERS : reg : Name of a register. -*# field : Name of a field. -*# val : Value to compare with field. -*# var : Variable (or value) to compare with. -*# -*# RETURNS : TRUE, FALSE -*# -*# SIDE EFFECTS: May evaluate REG_VERROR. -*# -*# DESCRIPTION : Interprets variable var as register reg, and compare -*# compare field field with parameter val. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to reg and field parameters when -*# passing on to other macros. -*#**********************************************************************/ - -#define REG_VEQL(reg,field,val,var) ( \ - ( ((reg##__TYPE (var)) & reg##__##field##__##field##__MASK) >> \ - reg##__##field##__BITNR \ - ) == reg##__##field##__##field##__VAL(reg##_, field##_, val) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL -*# -*# PARAMETERS : reg : Name of a register. -*# field : Name of a field. -*# val : A symbolic constant. -*# -*# RETURNS : val or (val << REG_VERROR()) macro. -*# -*# SIDE EFFECTS: May evaluate REG_VERROR macro. -*# -*# DESCRIPTION : Convert a symbolic constant to an integer value. -*# Intended to be used for enumerated fields. Also -*# Also works for value fields, in which case the val -*# parameter is checked for range and returned if OK, -*# and if val is out of range (val << REG_VERROR) is -*# returned. Also see description of REG_VAL_VAL, and -*# REG_VAL_ENUM. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to reg and field parameters when -*# passing on to other macros. -*#**********************************************************************/ - -#define REG_VAL(reg,field,val) ( \ - reg##__##field##__##field##__VAL(reg##_, field##_, val) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_CHK_VAL -*# -*# PARAMETERS : reg : Name of a register. -*# field : Name of a field. -*# val : An integer value. -*# -*# RETURNS : 1 if val is within allowed range for field, otherwise 0. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Check if parameter val is within the field range, -*# and return 1 if it is, otherwise 0. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*#**********************************************************************/ - -#define REG_CHK_VAL(reg,field,val) ( \ - (udword)(~(val)) <= (udword)(~(reg##__##field##__MIN)) && \ - (udword)(val) <= (udword)(reg##__##field##__MAX) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_RD -*# -*# PARAMETERS : reg : Name of a register. -*# -*# RETURNS : Contents of register reg. -*# -*# SIDE EFFECTS: May evaluate REG_SERROR. -*# -*# DESCRIPTION : Read contents of register reg. Also see description of -*# REG_RD_WO, REG_RD_RO, and REG_RD_RW. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to reg parameter when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_RD(reg) ( \ - reg##__RD(reg##_) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_IRD -*# -*# PARAMETERS : i : Interface number. -*# reg : Name of a register. -*# -*# RETURNS : Contents of register reg. -*# -*# SIDE EFFECTS: May evaluate REG_SERROR and REG_IERROR. -*# -*# DESCRIPTION : Read contents of register reg. Also see description of -*# REG_IRD_WO, REG_IRD_RO, and REG_IRD_RW. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to reg parameter when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_IRD(i,reg) ( \ - reg##__IRD(i,reg##_) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_WR -*# -*# PARAMETERS : reg : Name of a register. -*# var : Variable (or value) to write to reg. -*# -*# RETURNS : integer value written to register reg. -*# -*# SIDE EFFECTS: May evaluate REG_SERROR. -*# -*# DESCRIPTION : Write value of var parameter to register reg. Also see -*# description of REG_WR_WO, and REG_WR_RW. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to reg parameter when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_WR(reg,var) ( \ - reg##__WR(reg##_,var) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_IWR -*# -*# PARAMETERS : i : Interface number. -*# reg : Name of a register. -*# var : Variable (or value) to write to reg. -*# -*# RETURNS : integer value written to register reg. -*# -*# SIDE EFFECTS: May evaluate REG_SERROR. -*# -*# DESCRIPTION : Write value of var parameter to register reg of -*# interface i. Also see description of REG_IWR_WO, -*# and REG_IWR_RW. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to reg parameter when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_IWR(i,reg,var) ( \ - reg##__IWR(i##_, reg##_, var) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_ADDR -*# -*# PARAMETERS : reg : Name of a register. -*# -*# RETURNS : Address to register reg. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Calculate address to register reg. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*#**********************************************************************/ - -#define REG_ADDR(reg) ( \ - reg##__ADDR \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_BITNR -*# -*# PARAMETERS : reg : Name of a register. -*# field : Name of a field in register reg. -*# -*# RETURNS : Position of least significant bit of field in reg.. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Calculate position of least significant bit of -*# field field in register reg. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*#**********************************************************************/ - -#define REG_BITNR(reg,field) ( \ - reg##__##field##__BITNR \ -) - -#endif /* __REG_GENERAL_3_H__ */ - - -/* - * R_ALT_SER_BAUDRATE - * - type: WO - * - addr: 0xb000005c - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_ALT_SER_BAUDRATE -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_ALT_SER_BAUDRATE. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_ALT_SER_BAUDRATE. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_ALT_SER_BAUDRATE(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - *R_ALT_SER_BAUDRATE__SADDR = ( \ - REG_INITIATED(R_ALT_SER_BAUDRATE_) \ - REG_VAL__R_ALT_SER_BAUDRATE_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \ - ), \ - R_ALT_SER_BAUDRATE__WRITE(R_ALT_SER_BAUDRATE__ADDR, *R_ALT_SER_BAUDRATE__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_ALT_SER_BAUDRATE__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_ALT_SER_BAUDRATE. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_ALT_SER_BAUDRATE. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_ALT_SER_BAUDRATE__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - *R_ALT_SER_BAUDRATE__SADDR = ( \ - REG_INITIATED(R_ALT_SER_BAUDRATE_) \ - REG_VAL__R_ALT_SER_BAUDRATE_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_ALT_SER_BAUDRATE -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_ALT_SER_BAUDRATE(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - (R_ALT_SER_BAUDRATE__ser3_tr__##f1##__MASK & REG__##v1) | \ - (R_ALT_SER_BAUDRATE__ser3_rec__##f2##__MASK & REG__##v2) | \ - (R_ALT_SER_BAUDRATE__ser2_tr__##f3##__MASK & REG__##v3) | \ - (R_ALT_SER_BAUDRATE__ser2_rec__##f4##__MASK & REG__##v4) | \ - (R_ALT_SER_BAUDRATE__ser1_tr__##f5##__MASK & REG__##v5) | \ - (R_ALT_SER_BAUDRATE__ser1_rec__##f6##__MASK & REG__##v6) | \ - (R_ALT_SER_BAUDRATE__ser0_tr__##f7##__MASK & REG__##v7) | \ - (R_ALT_SER_BAUDRATE__ser0_rec__##f8##__MASK & REG__##v8) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_ALT_SER_BAUDRATE -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_ALT_SER_BAUDRATE. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_ALT_SER_BAUDRATE(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - (R_ALT_SER_BAUDRATE__ser3_tr__##f1##__VAL(R_ALT_SER_BAUDRATE_, ser3_tr_, v1) << R_ALT_SER_BAUDRATE__ser3_tr__BITNR) | \ - (R_ALT_SER_BAUDRATE__ser3_rec__##f2##__VAL(R_ALT_SER_BAUDRATE_, ser3_rec_, v2) << R_ALT_SER_BAUDRATE__ser3_rec__BITNR) | \ - (R_ALT_SER_BAUDRATE__ser2_tr__##f3##__VAL(R_ALT_SER_BAUDRATE_, ser2_tr_, v3) << R_ALT_SER_BAUDRATE__ser2_tr__BITNR) | \ - (R_ALT_SER_BAUDRATE__ser2_rec__##f4##__VAL(R_ALT_SER_BAUDRATE_, ser2_rec_, v4) << R_ALT_SER_BAUDRATE__ser2_rec__BITNR) | \ - (R_ALT_SER_BAUDRATE__ser1_tr__##f5##__VAL(R_ALT_SER_BAUDRATE_, ser1_tr_, v5) << R_ALT_SER_BAUDRATE__ser1_tr__BITNR) | \ - (R_ALT_SER_BAUDRATE__ser1_rec__##f6##__VAL(R_ALT_SER_BAUDRATE_, ser1_rec_, v6) << R_ALT_SER_BAUDRATE__ser1_rec__BITNR) | \ - (R_ALT_SER_BAUDRATE__ser0_tr__##f7##__VAL(R_ALT_SER_BAUDRATE_, ser0_tr_, v7) << R_ALT_SER_BAUDRATE__ser0_tr__BITNR) | \ - (R_ALT_SER_BAUDRATE__ser0_rec__##f8##__VAL(R_ALT_SER_BAUDRATE_, ser0_rec_, v8) << R_ALT_SER_BAUDRATE__ser0_rec__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_ALT_SER_BAUDRATE_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_ALT_SER_BAUDRATE. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_ALT_SER_BAUDRATE_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8) ( \ - (R_ALT_SER_BAUDRATE__ser3_tr__##f1_##_VAL(R_ALT_SER_BAUDRATE_, ser3_tr_, v1) << R_ALT_SER_BAUDRATE__ser3_tr__BITNR) | \ - (R_ALT_SER_BAUDRATE__ser3_rec__##f2_##_VAL(R_ALT_SER_BAUDRATE_, ser3_rec_, v2) << R_ALT_SER_BAUDRATE__ser3_rec__BITNR) | \ - (R_ALT_SER_BAUDRATE__ser2_tr__##f3_##_VAL(R_ALT_SER_BAUDRATE_, ser2_tr_, v3) << R_ALT_SER_BAUDRATE__ser2_tr__BITNR) | \ - (R_ALT_SER_BAUDRATE__ser2_rec__##f4_##_VAL(R_ALT_SER_BAUDRATE_, ser2_rec_, v4) << R_ALT_SER_BAUDRATE__ser2_rec__BITNR) | \ - (R_ALT_SER_BAUDRATE__ser1_tr__##f5_##_VAL(R_ALT_SER_BAUDRATE_, ser1_tr_, v5) << R_ALT_SER_BAUDRATE__ser1_tr__BITNR) | \ - (R_ALT_SER_BAUDRATE__ser1_rec__##f6_##_VAL(R_ALT_SER_BAUDRATE_, ser1_rec_, v6) << R_ALT_SER_BAUDRATE__ser1_rec__BITNR) | \ - (R_ALT_SER_BAUDRATE__ser0_tr__##f7_##_VAL(R_ALT_SER_BAUDRATE_, ser0_tr_, v7) << R_ALT_SER_BAUDRATE__ser0_tr__BITNR) | \ - (R_ALT_SER_BAUDRATE__ser0_rec__##f8_##_VAL(R_ALT_SER_BAUDRATE_, ser0_rec_, v8) << R_ALT_SER_BAUDRATE__ser0_rec__BITNR) \ -) - -#endif - -/* - * R_ATA_CONFIG - * - type: WO - * - addr: 0xb0000044 - * - group: ATA interface registers - */ - -#if USE_GROUP__ATA_interface_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_ATA_CONFIG -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_ATA_CONFIG. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_ATA_CONFIG. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_ATA_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \ - *R_ATA_CONFIG__SADDR = ( \ - REG_INITIATED(R_ATA_CONFIG_) \ - REG_VAL__R_ATA_CONFIG_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6) \ - ), \ - R_ATA_CONFIG__WRITE(R_ATA_CONFIG__ADDR, *R_ATA_CONFIG__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_ATA_CONFIG__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_ATA_CONFIG. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_ATA_CONFIG. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_ATA_CONFIG__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \ - *R_ATA_CONFIG__SADDR = ( \ - REG_INITIATED(R_ATA_CONFIG_) \ - REG_VAL__R_ATA_CONFIG_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_ATA_CONFIG -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_ATA_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \ - (R_ATA_CONFIG__enable__##f1##__MASK & REG__##v1) | \ - (R_ATA_CONFIG__dma_strobe__##f2##__MASK & REG__##v2) | \ - (R_ATA_CONFIG__dma_hold__##f3##__MASK & REG__##v3) | \ - (R_ATA_CONFIG__pio_setup__##f4##__MASK & REG__##v4) | \ - (R_ATA_CONFIG__pio_strobe__##f5##__MASK & REG__##v5) | \ - (R_ATA_CONFIG__pio_hold__##f6##__MASK & REG__##v6) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_ATA_CONFIG -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_ATA_CONFIG. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_ATA_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \ - (R_ATA_CONFIG__enable__##f1##__VAL(R_ATA_CONFIG_, enable_, v1) << R_ATA_CONFIG__enable__BITNR) | \ - (R_ATA_CONFIG__dma_strobe__##f2##__VAL(R_ATA_CONFIG_, dma_strobe_, v2) << R_ATA_CONFIG__dma_strobe__BITNR) | \ - (R_ATA_CONFIG__dma_hold__##f3##__VAL(R_ATA_CONFIG_, dma_hold_, v3) << R_ATA_CONFIG__dma_hold__BITNR) | \ - (R_ATA_CONFIG__pio_setup__##f4##__VAL(R_ATA_CONFIG_, pio_setup_, v4) << R_ATA_CONFIG__pio_setup__BITNR) | \ - (R_ATA_CONFIG__pio_strobe__##f5##__VAL(R_ATA_CONFIG_, pio_strobe_, v5) << R_ATA_CONFIG__pio_strobe__BITNR) | \ - (R_ATA_CONFIG__pio_hold__##f6##__VAL(R_ATA_CONFIG_, pio_hold_, v6) << R_ATA_CONFIG__pio_hold__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_ATA_CONFIG_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_ATA_CONFIG. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_ATA_CONFIG_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6) ( \ - (R_ATA_CONFIG__enable__##f1_##_VAL(R_ATA_CONFIG_, enable_, v1) << R_ATA_CONFIG__enable__BITNR) | \ - (R_ATA_CONFIG__dma_strobe__##f2_##_VAL(R_ATA_CONFIG_, dma_strobe_, v2) << R_ATA_CONFIG__dma_strobe__BITNR) | \ - (R_ATA_CONFIG__dma_hold__##f3_##_VAL(R_ATA_CONFIG_, dma_hold_, v3) << R_ATA_CONFIG__dma_hold__BITNR) | \ - (R_ATA_CONFIG__pio_setup__##f4_##_VAL(R_ATA_CONFIG_, pio_setup_, v4) << R_ATA_CONFIG__pio_setup__BITNR) | \ - (R_ATA_CONFIG__pio_strobe__##f5_##_VAL(R_ATA_CONFIG_, pio_strobe_, v5) << R_ATA_CONFIG__pio_strobe__BITNR) | \ - (R_ATA_CONFIG__pio_hold__##f6_##_VAL(R_ATA_CONFIG_, pio_hold_, v6) << R_ATA_CONFIG__pio_hold__BITNR) \ -) - -#endif - -/* - * R_ATA_CTRL_DATA - * - type: WO - * - addr: 0xb0000040 - * - group: ATA interface registers - */ - -#if USE_GROUP__ATA_interface_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_ATA_CTRL_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_ATA_CTRL_DATA. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_ATA_CTRL_DATA. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_ATA_CTRL_DATA(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \ - *R_ATA_CTRL_DATA__SADDR = ( \ - REG_INITIATED(R_ATA_CTRL_DATA_) \ - REG_VAL__R_ATA_CTRL_DATA_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10) \ - ), \ - R_ATA_CTRL_DATA__WRITE(R_ATA_CTRL_DATA__ADDR, *R_ATA_CTRL_DATA__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_ATA_CTRL_DATA__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_ATA_CTRL_DATA. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_ATA_CTRL_DATA. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_ATA_CTRL_DATA__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \ - *R_ATA_CTRL_DATA__SADDR = ( \ - REG_INITIATED(R_ATA_CTRL_DATA_) \ - REG_VAL__R_ATA_CTRL_DATA_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_ATA_CTRL_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_ATA_CTRL_DATA(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \ - (R_ATA_CTRL_DATA__sel__##f1##__MASK & REG__##v1) | \ - (R_ATA_CTRL_DATA__cs1__##f2##__MASK & REG__##v2) | \ - (R_ATA_CTRL_DATA__cs0__##f3##__MASK & REG__##v3) | \ - (R_ATA_CTRL_DATA__addr__##f4##__MASK & REG__##v4) | \ - (R_ATA_CTRL_DATA__rw__##f5##__MASK & REG__##v5) | \ - (R_ATA_CTRL_DATA__src_dst__##f6##__MASK & REG__##v6) | \ - (R_ATA_CTRL_DATA__handsh__##f7##__MASK & REG__##v7) | \ - (R_ATA_CTRL_DATA__multi__##f8##__MASK & REG__##v8) | \ - (R_ATA_CTRL_DATA__dma_size__##f9##__MASK & REG__##v9) | \ - (R_ATA_CTRL_DATA__data__##f10##__MASK & REG__##v10) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_ATA_CTRL_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_ATA_CTRL_DATA. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_ATA_CTRL_DATA(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \ - (R_ATA_CTRL_DATA__sel__##f1##__VAL(R_ATA_CTRL_DATA_, sel_, v1) << R_ATA_CTRL_DATA__sel__BITNR) | \ - (R_ATA_CTRL_DATA__cs1__##f2##__VAL(R_ATA_CTRL_DATA_, cs1_, v2) << R_ATA_CTRL_DATA__cs1__BITNR) | \ - (R_ATA_CTRL_DATA__cs0__##f3##__VAL(R_ATA_CTRL_DATA_, cs0_, v3) << R_ATA_CTRL_DATA__cs0__BITNR) | \ - (R_ATA_CTRL_DATA__addr__##f4##__VAL(R_ATA_CTRL_DATA_, addr_, v4) << R_ATA_CTRL_DATA__addr__BITNR) | \ - (R_ATA_CTRL_DATA__rw__##f5##__VAL(R_ATA_CTRL_DATA_, rw_, v5) << R_ATA_CTRL_DATA__rw__BITNR) | \ - (R_ATA_CTRL_DATA__src_dst__##f6##__VAL(R_ATA_CTRL_DATA_, src_dst_, v6) << R_ATA_CTRL_DATA__src_dst__BITNR) | \ - (R_ATA_CTRL_DATA__handsh__##f7##__VAL(R_ATA_CTRL_DATA_, handsh_, v7) << R_ATA_CTRL_DATA__handsh__BITNR) | \ - (R_ATA_CTRL_DATA__multi__##f8##__VAL(R_ATA_CTRL_DATA_, multi_, v8) << R_ATA_CTRL_DATA__multi__BITNR) | \ - (R_ATA_CTRL_DATA__dma_size__##f9##__VAL(R_ATA_CTRL_DATA_, dma_size_, v9) << R_ATA_CTRL_DATA__dma_size__BITNR) | \ - (R_ATA_CTRL_DATA__data__##f10##__VAL(R_ATA_CTRL_DATA_, data_, v10) << R_ATA_CTRL_DATA__data__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_ATA_CTRL_DATA_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_ATA_CTRL_DATA. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_ATA_CTRL_DATA_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10) ( \ - (R_ATA_CTRL_DATA__sel__##f1_##_VAL(R_ATA_CTRL_DATA_, sel_, v1) << R_ATA_CTRL_DATA__sel__BITNR) | \ - (R_ATA_CTRL_DATA__cs1__##f2_##_VAL(R_ATA_CTRL_DATA_, cs1_, v2) << R_ATA_CTRL_DATA__cs1__BITNR) | \ - (R_ATA_CTRL_DATA__cs0__##f3_##_VAL(R_ATA_CTRL_DATA_, cs0_, v3) << R_ATA_CTRL_DATA__cs0__BITNR) | \ - (R_ATA_CTRL_DATA__addr__##f4_##_VAL(R_ATA_CTRL_DATA_, addr_, v4) << R_ATA_CTRL_DATA__addr__BITNR) | \ - (R_ATA_CTRL_DATA__rw__##f5_##_VAL(R_ATA_CTRL_DATA_, rw_, v5) << R_ATA_CTRL_DATA__rw__BITNR) | \ - (R_ATA_CTRL_DATA__src_dst__##f6_##_VAL(R_ATA_CTRL_DATA_, src_dst_, v6) << R_ATA_CTRL_DATA__src_dst__BITNR) | \ - (R_ATA_CTRL_DATA__handsh__##f7_##_VAL(R_ATA_CTRL_DATA_, handsh_, v7) << R_ATA_CTRL_DATA__handsh__BITNR) | \ - (R_ATA_CTRL_DATA__multi__##f8_##_VAL(R_ATA_CTRL_DATA_, multi_, v8) << R_ATA_CTRL_DATA__multi__BITNR) | \ - (R_ATA_CTRL_DATA__dma_size__##f9_##_VAL(R_ATA_CTRL_DATA_, dma_size_, v9) << R_ATA_CTRL_DATA__dma_size__BITNR) | \ - (R_ATA_CTRL_DATA__data__##f10_##_VAL(R_ATA_CTRL_DATA_, data_, v10) << R_ATA_CTRL_DATA__data__BITNR) \ -) - -#endif - -/* - * R_ATA_STATUS_DATA - * - type: RO - * - addr: 0xb0000040 - * - group: ATA interface registers - */ - -#if USE_GROUP__ATA_interface_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_ATA_STATUS_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_ATA_STATUS_DATA(f1,v1,f2,v2,f3,v3,f4,v4) ( \ - (R_ATA_STATUS_DATA__busy__##f1##__MASK & REG__##v1) | \ - (R_ATA_STATUS_DATA__tr_rdy__##f2##__MASK & REG__##v2) | \ - (R_ATA_STATUS_DATA__dav__##f3##__MASK & REG__##v3) | \ - (R_ATA_STATUS_DATA__data__##f4##__MASK & REG__##v4) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_ATA_STATUS_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_ATA_STATUS_DATA. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_ATA_STATUS_DATA(f1,v1,f2,v2,f3,v3,f4,v4) ( \ - (R_ATA_STATUS_DATA__busy__##f1##__VAL(R_ATA_STATUS_DATA_, busy_, v1) << R_ATA_STATUS_DATA__busy__BITNR) | \ - (R_ATA_STATUS_DATA__tr_rdy__##f2##__VAL(R_ATA_STATUS_DATA_, tr_rdy_, v2) << R_ATA_STATUS_DATA__tr_rdy__BITNR) | \ - (R_ATA_STATUS_DATA__dav__##f3##__VAL(R_ATA_STATUS_DATA_, dav_, v3) << R_ATA_STATUS_DATA__dav__BITNR) | \ - (R_ATA_STATUS_DATA__data__##f4##__VAL(R_ATA_STATUS_DATA_, data_, v4) << R_ATA_STATUS_DATA__data__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_ATA_STATUS_DATA_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_ATA_STATUS_DATA. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_ATA_STATUS_DATA_(f1_,v1,f2_,v2,f3_,v3,f4_,v4) ( \ - (R_ATA_STATUS_DATA__busy__##f1_##_VAL(R_ATA_STATUS_DATA_, busy_, v1) << R_ATA_STATUS_DATA__busy__BITNR) | \ - (R_ATA_STATUS_DATA__tr_rdy__##f2_##_VAL(R_ATA_STATUS_DATA_, tr_rdy_, v2) << R_ATA_STATUS_DATA__tr_rdy__BITNR) | \ - (R_ATA_STATUS_DATA__dav__##f3_##_VAL(R_ATA_STATUS_DATA_, dav_, v3) << R_ATA_STATUS_DATA__dav__BITNR) | \ - (R_ATA_STATUS_DATA__data__##f4_##_VAL(R_ATA_STATUS_DATA_, data_, v4) << R_ATA_STATUS_DATA__data__BITNR) \ -) - -#endif - -/* - * R_ATA_TRANSFER_CNT - * - type: RW - * - addr: 0xb0000048 - * - group: ATA interface registers - */ - -#if USE_GROUP__ATA_interface_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_ATA_TRANSFER_CNT -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_ATA_TRANSFER_CNT. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_ATA_TRANSFER_CNT. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_ATA_TRANSFER_CNT(f1,v1) ( \ - R_ATA_TRANSFER_CNT__WRITE(R_ATA_TRANSFER_CNT__ADDR, ( \ - REG_VAL__R_ATA_TRANSFER_CNT_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_ATA_TRANSFER_CNT -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_ATA_TRANSFER_CNT(f1,v1) ( \ - (R_ATA_TRANSFER_CNT__count__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_ATA_TRANSFER_CNT -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_ATA_TRANSFER_CNT. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_ATA_TRANSFER_CNT(f1,v1) ( \ - (R_ATA_TRANSFER_CNT__count__##f1##__VAL(R_ATA_TRANSFER_CNT_, count_, v1) << R_ATA_TRANSFER_CNT__count__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_ATA_TRANSFER_CNT_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_ATA_TRANSFER_CNT. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_ATA_TRANSFER_CNT_(f1_,v1) ( \ - (R_ATA_TRANSFER_CNT__count__##f1_##_VAL(R_ATA_TRANSFER_CNT_, count_, v1) << R_ATA_TRANSFER_CNT__count__BITNR) \ -) - -#endif - -/* - * R_BUS_CONFIG - * - type: WO - * - addr: 0xb0000004 - * - group: Bus interface configuration registers - */ - -#if USE_GROUP__Bus_interface_configuration_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_BUS_CONFIG -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_BUS_CONFIG. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_BUS_CONFIG. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_BUS_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \ - *R_BUS_CONFIG__SADDR = ( \ - REG_INITIATED(R_BUS_CONFIG_) \ - REG_VAL__R_BUS_CONFIG_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10) \ - ), \ - R_BUS_CONFIG__WRITE(R_BUS_CONFIG__ADDR, *R_BUS_CONFIG__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_BUS_CONFIG__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_BUS_CONFIG. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_BUS_CONFIG. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_BUS_CONFIG__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \ - *R_BUS_CONFIG__SADDR = ( \ - REG_INITIATED(R_BUS_CONFIG_) \ - REG_VAL__R_BUS_CONFIG_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_BUS_CONFIG -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_BUS_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \ - (R_BUS_CONFIG__sram_type__##f1##__MASK & REG__##v1) | \ - (R_BUS_CONFIG__dma_burst__##f2##__MASK & REG__##v2) | \ - (R_BUS_CONFIG__pcs4_7_wr__##f3##__MASK & REG__##v3) | \ - (R_BUS_CONFIG__pcs0_3_wr__##f4##__MASK & REG__##v4) | \ - (R_BUS_CONFIG__sram_wr__##f5##__MASK & REG__##v5) | \ - (R_BUS_CONFIG__flash_wr__##f6##__MASK & REG__##v6) | \ - (R_BUS_CONFIG__pcs4_7_bw__##f7##__MASK & REG__##v7) | \ - (R_BUS_CONFIG__pcs0_3_bw__##f8##__MASK & REG__##v8) | \ - (R_BUS_CONFIG__sram_bw__##f9##__MASK & REG__##v9) | \ - (R_BUS_CONFIG__flash_bw__##f10##__MASK & REG__##v10) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_BUS_CONFIG -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_BUS_CONFIG. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_BUS_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \ - (R_BUS_CONFIG__sram_type__##f1##__VAL(R_BUS_CONFIG_, sram_type_, v1) << R_BUS_CONFIG__sram_type__BITNR) | \ - (R_BUS_CONFIG__dma_burst__##f2##__VAL(R_BUS_CONFIG_, dma_burst_, v2) << R_BUS_CONFIG__dma_burst__BITNR) | \ - (R_BUS_CONFIG__pcs4_7_wr__##f3##__VAL(R_BUS_CONFIG_, pcs4_7_wr_, v3) << R_BUS_CONFIG__pcs4_7_wr__BITNR) | \ - (R_BUS_CONFIG__pcs0_3_wr__##f4##__VAL(R_BUS_CONFIG_, pcs0_3_wr_, v4) << R_BUS_CONFIG__pcs0_3_wr__BITNR) | \ - (R_BUS_CONFIG__sram_wr__##f5##__VAL(R_BUS_CONFIG_, sram_wr_, v5) << R_BUS_CONFIG__sram_wr__BITNR) | \ - (R_BUS_CONFIG__flash_wr__##f6##__VAL(R_BUS_CONFIG_, flash_wr_, v6) << R_BUS_CONFIG__flash_wr__BITNR) | \ - (R_BUS_CONFIG__pcs4_7_bw__##f7##__VAL(R_BUS_CONFIG_, pcs4_7_bw_, v7) << R_BUS_CONFIG__pcs4_7_bw__BITNR) | \ - (R_BUS_CONFIG__pcs0_3_bw__##f8##__VAL(R_BUS_CONFIG_, pcs0_3_bw_, v8) << R_BUS_CONFIG__pcs0_3_bw__BITNR) | \ - (R_BUS_CONFIG__sram_bw__##f9##__VAL(R_BUS_CONFIG_, sram_bw_, v9) << R_BUS_CONFIG__sram_bw__BITNR) | \ - (R_BUS_CONFIG__flash_bw__##f10##__VAL(R_BUS_CONFIG_, flash_bw_, v10) << R_BUS_CONFIG__flash_bw__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_BUS_CONFIG_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_BUS_CONFIG. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_BUS_CONFIG_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10) ( \ - (R_BUS_CONFIG__sram_type__##f1_##_VAL(R_BUS_CONFIG_, sram_type_, v1) << R_BUS_CONFIG__sram_type__BITNR) | \ - (R_BUS_CONFIG__dma_burst__##f2_##_VAL(R_BUS_CONFIG_, dma_burst_, v2) << R_BUS_CONFIG__dma_burst__BITNR) | \ - (R_BUS_CONFIG__pcs4_7_wr__##f3_##_VAL(R_BUS_CONFIG_, pcs4_7_wr_, v3) << R_BUS_CONFIG__pcs4_7_wr__BITNR) | \ - (R_BUS_CONFIG__pcs0_3_wr__##f4_##_VAL(R_BUS_CONFIG_, pcs0_3_wr_, v4) << R_BUS_CONFIG__pcs0_3_wr__BITNR) | \ - (R_BUS_CONFIG__sram_wr__##f5_##_VAL(R_BUS_CONFIG_, sram_wr_, v5) << R_BUS_CONFIG__sram_wr__BITNR) | \ - (R_BUS_CONFIG__flash_wr__##f6_##_VAL(R_BUS_CONFIG_, flash_wr_, v6) << R_BUS_CONFIG__flash_wr__BITNR) | \ - (R_BUS_CONFIG__pcs4_7_bw__##f7_##_VAL(R_BUS_CONFIG_, pcs4_7_bw_, v7) << R_BUS_CONFIG__pcs4_7_bw__BITNR) | \ - (R_BUS_CONFIG__pcs0_3_bw__##f8_##_VAL(R_BUS_CONFIG_, pcs0_3_bw_, v8) << R_BUS_CONFIG__pcs0_3_bw__BITNR) | \ - (R_BUS_CONFIG__sram_bw__##f9_##_VAL(R_BUS_CONFIG_, sram_bw_, v9) << R_BUS_CONFIG__sram_bw__BITNR) | \ - (R_BUS_CONFIG__flash_bw__##f10_##_VAL(R_BUS_CONFIG_, flash_bw_, v10) << R_BUS_CONFIG__flash_bw__BITNR) \ -) - -#endif - -/* - * R_BUS_STATUS - * - type: RO - * - addr: 0xb0000004 - * - group: Bus interface configuration registers - */ - -#if USE_GROUP__Bus_interface_configuration_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_BUS_STATUS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_BUS_STATUS(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5) ( \ - (R_BUS_STATUS__pll_lock_tm__##f1##__MASK & REG__##v1) | \ - (R_BUS_STATUS__both_faults__##f2##__MASK & REG__##v2) | \ - (R_BUS_STATUS__bsen___##f3##__MASK & REG__##v3) | \ - (R_BUS_STATUS__boot__##f4##__MASK & REG__##v4) | \ - (R_BUS_STATUS__flashw__##f5##__MASK & REG__##v5) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_BUS_STATUS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_BUS_STATUS. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_BUS_STATUS(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5) ( \ - (R_BUS_STATUS__pll_lock_tm__##f1##__VAL(R_BUS_STATUS_, pll_lock_tm_, v1) << R_BUS_STATUS__pll_lock_tm__BITNR) | \ - (R_BUS_STATUS__both_faults__##f2##__VAL(R_BUS_STATUS_, both_faults_, v2) << R_BUS_STATUS__both_faults__BITNR) | \ - (R_BUS_STATUS__bsen___##f3##__VAL(R_BUS_STATUS_, bsen__, v3) << R_BUS_STATUS__bsen___BITNR) | \ - (R_BUS_STATUS__boot__##f4##__VAL(R_BUS_STATUS_, boot_, v4) << R_BUS_STATUS__boot__BITNR) | \ - (R_BUS_STATUS__flashw__##f5##__VAL(R_BUS_STATUS_, flashw_, v5) << R_BUS_STATUS__flashw__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_BUS_STATUS_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_BUS_STATUS. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_BUS_STATUS_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5) ( \ - (R_BUS_STATUS__pll_lock_tm__##f1_##_VAL(R_BUS_STATUS_, pll_lock_tm_, v1) << R_BUS_STATUS__pll_lock_tm__BITNR) | \ - (R_BUS_STATUS__both_faults__##f2_##_VAL(R_BUS_STATUS_, both_faults_, v2) << R_BUS_STATUS__both_faults__BITNR) | \ - (R_BUS_STATUS__bsen___##f3_##_VAL(R_BUS_STATUS_, bsen__, v3) << R_BUS_STATUS__bsen___BITNR) | \ - (R_BUS_STATUS__boot__##f4_##_VAL(R_BUS_STATUS_, boot_, v4) << R_BUS_STATUS__boot__BITNR) | \ - (R_BUS_STATUS__flashw__##f5_##_VAL(R_BUS_STATUS_, flashw_, v5) << R_BUS_STATUS__flashw__BITNR) \ -) - -#endif - -/* - * R_CLOCK_PRESCALE - * - type: WO - * - addr: 0xb00000f0 - * - group: Timer registers - */ - -#if USE_GROUP__Timer_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_CLOCK_PRESCALE -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_CLOCK_PRESCALE. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_CLOCK_PRESCALE. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_CLOCK_PRESCALE(f1,v1,f2,v2) ( \ - *R_CLOCK_PRESCALE__SADDR = ( \ - REG_INITIATED(R_CLOCK_PRESCALE_) \ - REG_VAL__R_CLOCK_PRESCALE_(f1##_,v1,f2##_,v2) \ - ), \ - R_CLOCK_PRESCALE__WRITE(R_CLOCK_PRESCALE__ADDR, *R_CLOCK_PRESCALE__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_CLOCK_PRESCALE__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_CLOCK_PRESCALE. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_CLOCK_PRESCALE. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_CLOCK_PRESCALE__SHADOW(f1,v1,f2,v2) ( \ - *R_CLOCK_PRESCALE__SADDR = ( \ - REG_INITIATED(R_CLOCK_PRESCALE_) \ - REG_VAL__R_CLOCK_PRESCALE_(f1##_,v1,f2##_,v2) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_CLOCK_PRESCALE -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_CLOCK_PRESCALE(f1,v1,f2,v2) ( \ - (R_CLOCK_PRESCALE__ser_presc__##f1##__MASK & REG__##v1) | \ - (R_CLOCK_PRESCALE__tim_presc__##f2##__MASK & REG__##v2) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_CLOCK_PRESCALE -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_CLOCK_PRESCALE. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_CLOCK_PRESCALE(f1,v1,f2,v2) ( \ - (R_CLOCK_PRESCALE__ser_presc__##f1##__VAL(R_CLOCK_PRESCALE_, ser_presc_, v1) << R_CLOCK_PRESCALE__ser_presc__BITNR) | \ - (R_CLOCK_PRESCALE__tim_presc__##f2##__VAL(R_CLOCK_PRESCALE_, tim_presc_, v2) << R_CLOCK_PRESCALE__tim_presc__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_CLOCK_PRESCALE_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_CLOCK_PRESCALE. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_CLOCK_PRESCALE_(f1_,v1,f2_,v2) ( \ - (R_CLOCK_PRESCALE__ser_presc__##f1_##_VAL(R_CLOCK_PRESCALE_, ser_presc_, v1) << R_CLOCK_PRESCALE__ser_presc__BITNR) | \ - (R_CLOCK_PRESCALE__tim_presc__##f2_##_VAL(R_CLOCK_PRESCALE_, tim_presc_, v2) << R_CLOCK_PRESCALE__tim_presc__BITNR) \ -) - -#endif - -/* - * R_DMA_CH0_BUF - * - type: RW - * - addr: 0xb0000108 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH0_BUF -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH0_BUF. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH0_BUF. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH0_BUF(f1,v1) ( \ - R_DMA_CH0_BUF__WRITE(R_DMA_CH0_BUF__ADDR, ( \ - REG_VAL__R_DMA_CH0_BUF_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH0_BUF -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH0_BUF(f1,v1) ( \ - (R_DMA_CH0_BUF__buf__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH0_BUF -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH0_BUF. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH0_BUF(f1,v1) ( \ - (R_DMA_CH0_BUF__buf__##f1##__VAL(R_DMA_CH0_BUF_, buf_, v1) << R_DMA_CH0_BUF__buf__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH0_BUF_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH0_BUF. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH0_BUF_(f1_,v1) ( \ - (R_DMA_CH0_BUF__buf__##f1_##_VAL(R_DMA_CH0_BUF_, buf_, v1) << R_DMA_CH0_BUF__buf__BITNR) \ -) - -#endif - -/* - * R_DMA_CH0_CLR_INTR - * - type: WO - * - addr: 0xb00001d1 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH0_CLR_INTR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH0_CLR_INTR. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH0_CLR_INTR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH0_CLR_INTR(f1,v1,f2,v2) ( \ - *R_DMA_CH0_CLR_INTR__SADDR = ( \ - REG_INITIATED(R_DMA_CH0_CLR_INTR_) \ - REG_VAL__R_DMA_CH0_CLR_INTR_(f1##_,v1,f2##_,v2) \ - ), \ - R_DMA_CH0_CLR_INTR__WRITE(R_DMA_CH0_CLR_INTR__ADDR, *R_DMA_CH0_CLR_INTR__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH0_CLR_INTR__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH0_CLR_INTR. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_DMA_CH0_CLR_INTR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH0_CLR_INTR__SHADOW(f1,v1,f2,v2) ( \ - *R_DMA_CH0_CLR_INTR__SADDR = ( \ - REG_INITIATED(R_DMA_CH0_CLR_INTR_) \ - REG_VAL__R_DMA_CH0_CLR_INTR_(f1##_,v1,f2##_,v2) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH0_CLR_INTR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH0_CLR_INTR(f1,v1,f2,v2) ( \ - (R_DMA_CH0_CLR_INTR__clr_eop__##f1##__MASK & REG__##v1) | \ - (R_DMA_CH0_CLR_INTR__clr_descr__##f2##__MASK & REG__##v2) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH0_CLR_INTR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH0_CLR_INTR. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH0_CLR_INTR(f1,v1,f2,v2) ( \ - (R_DMA_CH0_CLR_INTR__clr_eop__##f1##__VAL(R_DMA_CH0_CLR_INTR_, clr_eop_, v1) << R_DMA_CH0_CLR_INTR__clr_eop__BITNR) | \ - (R_DMA_CH0_CLR_INTR__clr_descr__##f2##__VAL(R_DMA_CH0_CLR_INTR_, clr_descr_, v2) << R_DMA_CH0_CLR_INTR__clr_descr__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH0_CLR_INTR_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH0_CLR_INTR. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH0_CLR_INTR_(f1_,v1,f2_,v2) ( \ - (R_DMA_CH0_CLR_INTR__clr_eop__##f1_##_VAL(R_DMA_CH0_CLR_INTR_, clr_eop_, v1) << R_DMA_CH0_CLR_INTR__clr_eop__BITNR) | \ - (R_DMA_CH0_CLR_INTR__clr_descr__##f2_##_VAL(R_DMA_CH0_CLR_INTR_, clr_descr_, v2) << R_DMA_CH0_CLR_INTR__clr_descr__BITNR) \ -) - -#endif - -/* - * R_DMA_CH0_CMD - * - type: RW - * - addr: 0xb00001d0 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH0_CMD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH0_CMD. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH0_CMD. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH0_CMD(f1,v1) ( \ - R_DMA_CH0_CMD__WRITE(R_DMA_CH0_CMD__ADDR, ( \ - REG_VAL__R_DMA_CH0_CMD_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH0_CMD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH0_CMD(f1,v1) ( \ - (R_DMA_CH0_CMD__cmd__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH0_CMD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH0_CMD. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH0_CMD(f1,v1) ( \ - (R_DMA_CH0_CMD__cmd__##f1##__VAL(R_DMA_CH0_CMD_, cmd_, v1) << R_DMA_CH0_CMD__cmd__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH0_CMD_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH0_CMD. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH0_CMD_(f1_,v1) ( \ - (R_DMA_CH0_CMD__cmd__##f1_##_VAL(R_DMA_CH0_CMD_, cmd_, v1) << R_DMA_CH0_CMD__cmd__BITNR) \ -) - -#endif - -/* - * R_DMA_CH0_DESCR - * - type: RW - * - addr: 0xb000010c - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH0_DESCR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH0_DESCR. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH0_DESCR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH0_DESCR(f1,v1) ( \ - R_DMA_CH0_DESCR__WRITE(R_DMA_CH0_DESCR__ADDR, ( \ - REG_VAL__R_DMA_CH0_DESCR_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH0_DESCR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH0_DESCR(f1,v1) ( \ - (R_DMA_CH0_DESCR__descr__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH0_DESCR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH0_DESCR. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH0_DESCR(f1,v1) ( \ - (R_DMA_CH0_DESCR__descr__##f1##__VAL(R_DMA_CH0_DESCR_, descr_, v1) << R_DMA_CH0_DESCR__descr__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH0_DESCR_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH0_DESCR. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH0_DESCR_(f1_,v1) ( \ - (R_DMA_CH0_DESCR__descr__##f1_##_VAL(R_DMA_CH0_DESCR_, descr_, v1) << R_DMA_CH0_DESCR__descr__BITNR) \ -) - -#endif - -/* - * R_DMA_CH0_FIRST - * - type: RW - * - addr: 0xb00001a0 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH0_FIRST -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH0_FIRST. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH0_FIRST. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH0_FIRST(f1,v1) ( \ - R_DMA_CH0_FIRST__WRITE(R_DMA_CH0_FIRST__ADDR, ( \ - REG_VAL__R_DMA_CH0_FIRST_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH0_FIRST -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH0_FIRST(f1,v1) ( \ - (R_DMA_CH0_FIRST__first__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH0_FIRST -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH0_FIRST. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH0_FIRST(f1,v1) ( \ - (R_DMA_CH0_FIRST__first__##f1##__VAL(R_DMA_CH0_FIRST_, first_, v1) << R_DMA_CH0_FIRST__first__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH0_FIRST_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH0_FIRST. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH0_FIRST_(f1_,v1) ( \ - (R_DMA_CH0_FIRST__first__##f1_##_VAL(R_DMA_CH0_FIRST_, first_, v1) << R_DMA_CH0_FIRST__first__BITNR) \ -) - -#endif - -/* - * R_DMA_CH0_HWSW - * - type: RW - * - addr: 0xb0000100 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH0_HWSW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH0_HWSW. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH0_HWSW. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH0_HWSW(f1,v1,f2,v2) ( \ - R_DMA_CH0_HWSW__WRITE(R_DMA_CH0_HWSW__ADDR, ( \ - REG_VAL__R_DMA_CH0_HWSW_(f1##_,v1,f2##_,v2) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH0_HWSW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH0_HWSW(f1,v1,f2,v2) ( \ - (R_DMA_CH0_HWSW__hw__##f1##__MASK & REG__##v1) | \ - (R_DMA_CH0_HWSW__sw__##f2##__MASK & REG__##v2) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH0_HWSW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH0_HWSW. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH0_HWSW(f1,v1,f2,v2) ( \ - (R_DMA_CH0_HWSW__hw__##f1##__VAL(R_DMA_CH0_HWSW_, hw_, v1) << R_DMA_CH0_HWSW__hw__BITNR) | \ - (R_DMA_CH0_HWSW__sw__##f2##__VAL(R_DMA_CH0_HWSW_, sw_, v2) << R_DMA_CH0_HWSW__sw__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH0_HWSW_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH0_HWSW. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH0_HWSW_(f1_,v1,f2_,v2) ( \ - (R_DMA_CH0_HWSW__hw__##f1_##_VAL(R_DMA_CH0_HWSW_, hw_, v1) << R_DMA_CH0_HWSW__hw__BITNR) | \ - (R_DMA_CH0_HWSW__sw__##f2_##_VAL(R_DMA_CH0_HWSW_, sw_, v2) << R_DMA_CH0_HWSW__sw__BITNR) \ -) - -#endif - -/* - * R_DMA_CH0_NEXT - * - type: RW - * - addr: 0xb0000104 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH0_NEXT -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH0_NEXT. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH0_NEXT. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH0_NEXT(f1,v1) ( \ - R_DMA_CH0_NEXT__WRITE(R_DMA_CH0_NEXT__ADDR, ( \ - REG_VAL__R_DMA_CH0_NEXT_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH0_NEXT -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH0_NEXT(f1,v1) ( \ - (R_DMA_CH0_NEXT__next__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH0_NEXT -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH0_NEXT. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH0_NEXT(f1,v1) ( \ - (R_DMA_CH0_NEXT__next__##f1##__VAL(R_DMA_CH0_NEXT_, next_, v1) << R_DMA_CH0_NEXT__next__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH0_NEXT_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH0_NEXT. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH0_NEXT_(f1_,v1) ( \ - (R_DMA_CH0_NEXT__next__##f1_##_VAL(R_DMA_CH0_NEXT_, next_, v1) << R_DMA_CH0_NEXT__next__BITNR) \ -) - -#endif - -/* - * R_DMA_CH0_STATUS - * - type: RO - * - addr: 0xb00001d2 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH0_STATUS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH0_STATUS(f1,v1) ( \ - (R_DMA_CH0_STATUS__avail__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH0_STATUS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH0_STATUS. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH0_STATUS(f1,v1) ( \ - (R_DMA_CH0_STATUS__avail__##f1##__VAL(R_DMA_CH0_STATUS_, avail_, v1) << R_DMA_CH0_STATUS__avail__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH0_STATUS_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH0_STATUS. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH0_STATUS_(f1_,v1) ( \ - (R_DMA_CH0_STATUS__avail__##f1_##_VAL(R_DMA_CH0_STATUS_, avail_, v1) << R_DMA_CH0_STATUS__avail__BITNR) \ -) - -#endif - -/* - * R_DMA_CH1_BUF - * - type: RW - * - addr: 0xb0000118 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH1_BUF -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH1_BUF. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH1_BUF. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH1_BUF(f1,v1) ( \ - R_DMA_CH1_BUF__WRITE(R_DMA_CH1_BUF__ADDR, ( \ - REG_VAL__R_DMA_CH1_BUF_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH1_BUF -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH1_BUF(f1,v1) ( \ - (R_DMA_CH1_BUF__buf__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH1_BUF -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH1_BUF. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH1_BUF(f1,v1) ( \ - (R_DMA_CH1_BUF__buf__##f1##__VAL(R_DMA_CH1_BUF_, buf_, v1) << R_DMA_CH1_BUF__buf__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH1_BUF_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH1_BUF. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH1_BUF_(f1_,v1) ( \ - (R_DMA_CH1_BUF__buf__##f1_##_VAL(R_DMA_CH1_BUF_, buf_, v1) << R_DMA_CH1_BUF__buf__BITNR) \ -) - -#endif - -/* - * R_DMA_CH1_CLR_INTR - * - type: WO - * - addr: 0xb00001d5 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH1_CLR_INTR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH1_CLR_INTR. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH1_CLR_INTR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH1_CLR_INTR(f1,v1,f2,v2) ( \ - *R_DMA_CH1_CLR_INTR__SADDR = ( \ - REG_INITIATED(R_DMA_CH1_CLR_INTR_) \ - REG_VAL__R_DMA_CH1_CLR_INTR_(f1##_,v1,f2##_,v2) \ - ), \ - R_DMA_CH1_CLR_INTR__WRITE(R_DMA_CH1_CLR_INTR__ADDR, *R_DMA_CH1_CLR_INTR__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH1_CLR_INTR__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH1_CLR_INTR. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_DMA_CH1_CLR_INTR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH1_CLR_INTR__SHADOW(f1,v1,f2,v2) ( \ - *R_DMA_CH1_CLR_INTR__SADDR = ( \ - REG_INITIATED(R_DMA_CH1_CLR_INTR_) \ - REG_VAL__R_DMA_CH1_CLR_INTR_(f1##_,v1,f2##_,v2) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH1_CLR_INTR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH1_CLR_INTR(f1,v1,f2,v2) ( \ - (R_DMA_CH1_CLR_INTR__clr_eop__##f1##__MASK & REG__##v1) | \ - (R_DMA_CH1_CLR_INTR__clr_descr__##f2##__MASK & REG__##v2) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH1_CLR_INTR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH1_CLR_INTR. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH1_CLR_INTR(f1,v1,f2,v2) ( \ - (R_DMA_CH1_CLR_INTR__clr_eop__##f1##__VAL(R_DMA_CH1_CLR_INTR_, clr_eop_, v1) << R_DMA_CH1_CLR_INTR__clr_eop__BITNR) | \ - (R_DMA_CH1_CLR_INTR__clr_descr__##f2##__VAL(R_DMA_CH1_CLR_INTR_, clr_descr_, v2) << R_DMA_CH1_CLR_INTR__clr_descr__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH1_CLR_INTR_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH1_CLR_INTR. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH1_CLR_INTR_(f1_,v1,f2_,v2) ( \ - (R_DMA_CH1_CLR_INTR__clr_eop__##f1_##_VAL(R_DMA_CH1_CLR_INTR_, clr_eop_, v1) << R_DMA_CH1_CLR_INTR__clr_eop__BITNR) | \ - (R_DMA_CH1_CLR_INTR__clr_descr__##f2_##_VAL(R_DMA_CH1_CLR_INTR_, clr_descr_, v2) << R_DMA_CH1_CLR_INTR__clr_descr__BITNR) \ -) - -#endif - -/* - * R_DMA_CH1_CMD - * - type: RW - * - addr: 0xb00001d4 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH1_CMD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH1_CMD. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH1_CMD. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH1_CMD(f1,v1) ( \ - R_DMA_CH1_CMD__WRITE(R_DMA_CH1_CMD__ADDR, ( \ - REG_VAL__R_DMA_CH1_CMD_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH1_CMD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH1_CMD(f1,v1) ( \ - (R_DMA_CH1_CMD__cmd__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH1_CMD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH1_CMD. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH1_CMD(f1,v1) ( \ - (R_DMA_CH1_CMD__cmd__##f1##__VAL(R_DMA_CH1_CMD_, cmd_, v1) << R_DMA_CH1_CMD__cmd__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH1_CMD_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH1_CMD. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH1_CMD_(f1_,v1) ( \ - (R_DMA_CH1_CMD__cmd__##f1_##_VAL(R_DMA_CH1_CMD_, cmd_, v1) << R_DMA_CH1_CMD__cmd__BITNR) \ -) - -#endif - -/* - * R_DMA_CH1_DESCR - * - type: RW - * - addr: 0xb000011c - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH1_DESCR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH1_DESCR. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH1_DESCR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH1_DESCR(f1,v1) ( \ - R_DMA_CH1_DESCR__WRITE(R_DMA_CH1_DESCR__ADDR, ( \ - REG_VAL__R_DMA_CH1_DESCR_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH1_DESCR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH1_DESCR(f1,v1) ( \ - (R_DMA_CH1_DESCR__descr__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH1_DESCR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH1_DESCR. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH1_DESCR(f1,v1) ( \ - (R_DMA_CH1_DESCR__descr__##f1##__VAL(R_DMA_CH1_DESCR_, descr_, v1) << R_DMA_CH1_DESCR__descr__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH1_DESCR_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH1_DESCR. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH1_DESCR_(f1_,v1) ( \ - (R_DMA_CH1_DESCR__descr__##f1_##_VAL(R_DMA_CH1_DESCR_, descr_, v1) << R_DMA_CH1_DESCR__descr__BITNR) \ -) - -#endif - -/* - * R_DMA_CH1_FIRST - * - type: RW - * - addr: 0xb00001a4 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH1_FIRST -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH1_FIRST. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH1_FIRST. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH1_FIRST(f1,v1) ( \ - R_DMA_CH1_FIRST__WRITE(R_DMA_CH1_FIRST__ADDR, ( \ - REG_VAL__R_DMA_CH1_FIRST_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH1_FIRST -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH1_FIRST(f1,v1) ( \ - (R_DMA_CH1_FIRST__first__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH1_FIRST -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH1_FIRST. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH1_FIRST(f1,v1) ( \ - (R_DMA_CH1_FIRST__first__##f1##__VAL(R_DMA_CH1_FIRST_, first_, v1) << R_DMA_CH1_FIRST__first__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH1_FIRST_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH1_FIRST. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH1_FIRST_(f1_,v1) ( \ - (R_DMA_CH1_FIRST__first__##f1_##_VAL(R_DMA_CH1_FIRST_, first_, v1) << R_DMA_CH1_FIRST__first__BITNR) \ -) - -#endif - -/* - * R_DMA_CH1_HWSW - * - type: RW - * - addr: 0xb0000110 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH1_HWSW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH1_HWSW. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH1_HWSW. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH1_HWSW(f1,v1,f2,v2) ( \ - R_DMA_CH1_HWSW__WRITE(R_DMA_CH1_HWSW__ADDR, ( \ - REG_VAL__R_DMA_CH1_HWSW_(f1##_,v1,f2##_,v2) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH1_HWSW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH1_HWSW(f1,v1,f2,v2) ( \ - (R_DMA_CH1_HWSW__hw__##f1##__MASK & REG__##v1) | \ - (R_DMA_CH1_HWSW__sw__##f2##__MASK & REG__##v2) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH1_HWSW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH1_HWSW. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH1_HWSW(f1,v1,f2,v2) ( \ - (R_DMA_CH1_HWSW__hw__##f1##__VAL(R_DMA_CH1_HWSW_, hw_, v1) << R_DMA_CH1_HWSW__hw__BITNR) | \ - (R_DMA_CH1_HWSW__sw__##f2##__VAL(R_DMA_CH1_HWSW_, sw_, v2) << R_DMA_CH1_HWSW__sw__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH1_HWSW_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH1_HWSW. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH1_HWSW_(f1_,v1,f2_,v2) ( \ - (R_DMA_CH1_HWSW__hw__##f1_##_VAL(R_DMA_CH1_HWSW_, hw_, v1) << R_DMA_CH1_HWSW__hw__BITNR) | \ - (R_DMA_CH1_HWSW__sw__##f2_##_VAL(R_DMA_CH1_HWSW_, sw_, v2) << R_DMA_CH1_HWSW__sw__BITNR) \ -) - -#endif - -/* - * R_DMA_CH1_NEXT - * - type: RW - * - addr: 0xb0000114 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH1_NEXT -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH1_NEXT. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH1_NEXT. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH1_NEXT(f1,v1) ( \ - R_DMA_CH1_NEXT__WRITE(R_DMA_CH1_NEXT__ADDR, ( \ - REG_VAL__R_DMA_CH1_NEXT_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH1_NEXT -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH1_NEXT(f1,v1) ( \ - (R_DMA_CH1_NEXT__next__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH1_NEXT -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH1_NEXT. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH1_NEXT(f1,v1) ( \ - (R_DMA_CH1_NEXT__next__##f1##__VAL(R_DMA_CH1_NEXT_, next_, v1) << R_DMA_CH1_NEXT__next__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH1_NEXT_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH1_NEXT. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH1_NEXT_(f1_,v1) ( \ - (R_DMA_CH1_NEXT__next__##f1_##_VAL(R_DMA_CH1_NEXT_, next_, v1) << R_DMA_CH1_NEXT__next__BITNR) \ -) - -#endif - -/* - * R_DMA_CH1_STATUS - * - type: RO - * - addr: 0xb00001d6 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH1_STATUS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH1_STATUS(f1,v1) ( \ - (R_DMA_CH1_STATUS__avail__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH1_STATUS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH1_STATUS. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH1_STATUS(f1,v1) ( \ - (R_DMA_CH1_STATUS__avail__##f1##__VAL(R_DMA_CH1_STATUS_, avail_, v1) << R_DMA_CH1_STATUS__avail__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH1_STATUS_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH1_STATUS. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH1_STATUS_(f1_,v1) ( \ - (R_DMA_CH1_STATUS__avail__##f1_##_VAL(R_DMA_CH1_STATUS_, avail_, v1) << R_DMA_CH1_STATUS__avail__BITNR) \ -) - -#endif - -/* - * R_DMA_CH2_BUF - * - type: RW - * - addr: 0xb0000128 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH2_BUF -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH2_BUF. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH2_BUF. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH2_BUF(f1,v1) ( \ - R_DMA_CH2_BUF__WRITE(R_DMA_CH2_BUF__ADDR, ( \ - REG_VAL__R_DMA_CH2_BUF_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH2_BUF -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH2_BUF(f1,v1) ( \ - (R_DMA_CH2_BUF__buf__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH2_BUF -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH2_BUF. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH2_BUF(f1,v1) ( \ - (R_DMA_CH2_BUF__buf__##f1##__VAL(R_DMA_CH2_BUF_, buf_, v1) << R_DMA_CH2_BUF__buf__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH2_BUF_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH2_BUF. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH2_BUF_(f1_,v1) ( \ - (R_DMA_CH2_BUF__buf__##f1_##_VAL(R_DMA_CH2_BUF_, buf_, v1) << R_DMA_CH2_BUF__buf__BITNR) \ -) - -#endif - -/* - * R_DMA_CH2_CLR_INTR - * - type: WO - * - addr: 0xb00001d9 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH2_CLR_INTR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH2_CLR_INTR. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH2_CLR_INTR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH2_CLR_INTR(f1,v1,f2,v2) ( \ - *R_DMA_CH2_CLR_INTR__SADDR = ( \ - REG_INITIATED(R_DMA_CH2_CLR_INTR_) \ - REG_VAL__R_DMA_CH2_CLR_INTR_(f1##_,v1,f2##_,v2) \ - ), \ - R_DMA_CH2_CLR_INTR__WRITE(R_DMA_CH2_CLR_INTR__ADDR, *R_DMA_CH2_CLR_INTR__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH2_CLR_INTR__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH2_CLR_INTR. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_DMA_CH2_CLR_INTR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH2_CLR_INTR__SHADOW(f1,v1,f2,v2) ( \ - *R_DMA_CH2_CLR_INTR__SADDR = ( \ - REG_INITIATED(R_DMA_CH2_CLR_INTR_) \ - REG_VAL__R_DMA_CH2_CLR_INTR_(f1##_,v1,f2##_,v2) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH2_CLR_INTR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH2_CLR_INTR(f1,v1,f2,v2) ( \ - (R_DMA_CH2_CLR_INTR__clr_eop__##f1##__MASK & REG__##v1) | \ - (R_DMA_CH2_CLR_INTR__clr_descr__##f2##__MASK & REG__##v2) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH2_CLR_INTR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH2_CLR_INTR. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH2_CLR_INTR(f1,v1,f2,v2) ( \ - (R_DMA_CH2_CLR_INTR__clr_eop__##f1##__VAL(R_DMA_CH2_CLR_INTR_, clr_eop_, v1) << R_DMA_CH2_CLR_INTR__clr_eop__BITNR) | \ - (R_DMA_CH2_CLR_INTR__clr_descr__##f2##__VAL(R_DMA_CH2_CLR_INTR_, clr_descr_, v2) << R_DMA_CH2_CLR_INTR__clr_descr__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH2_CLR_INTR_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH2_CLR_INTR. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH2_CLR_INTR_(f1_,v1,f2_,v2) ( \ - (R_DMA_CH2_CLR_INTR__clr_eop__##f1_##_VAL(R_DMA_CH2_CLR_INTR_, clr_eop_, v1) << R_DMA_CH2_CLR_INTR__clr_eop__BITNR) | \ - (R_DMA_CH2_CLR_INTR__clr_descr__##f2_##_VAL(R_DMA_CH2_CLR_INTR_, clr_descr_, v2) << R_DMA_CH2_CLR_INTR__clr_descr__BITNR) \ -) - -#endif - -/* - * R_DMA_CH2_CMD - * - type: RW - * - addr: 0xb00001d8 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH2_CMD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH2_CMD. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH2_CMD. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH2_CMD(f1,v1) ( \ - R_DMA_CH2_CMD__WRITE(R_DMA_CH2_CMD__ADDR, ( \ - REG_VAL__R_DMA_CH2_CMD_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH2_CMD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH2_CMD(f1,v1) ( \ - (R_DMA_CH2_CMD__cmd__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH2_CMD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH2_CMD. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH2_CMD(f1,v1) ( \ - (R_DMA_CH2_CMD__cmd__##f1##__VAL(R_DMA_CH2_CMD_, cmd_, v1) << R_DMA_CH2_CMD__cmd__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH2_CMD_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH2_CMD. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH2_CMD_(f1_,v1) ( \ - (R_DMA_CH2_CMD__cmd__##f1_##_VAL(R_DMA_CH2_CMD_, cmd_, v1) << R_DMA_CH2_CMD__cmd__BITNR) \ -) - -#endif - -/* - * R_DMA_CH2_DESCR - * - type: RW - * - addr: 0xb000012c - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH2_DESCR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH2_DESCR. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH2_DESCR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH2_DESCR(f1,v1) ( \ - R_DMA_CH2_DESCR__WRITE(R_DMA_CH2_DESCR__ADDR, ( \ - REG_VAL__R_DMA_CH2_DESCR_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH2_DESCR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH2_DESCR(f1,v1) ( \ - (R_DMA_CH2_DESCR__descr__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH2_DESCR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH2_DESCR. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH2_DESCR(f1,v1) ( \ - (R_DMA_CH2_DESCR__descr__##f1##__VAL(R_DMA_CH2_DESCR_, descr_, v1) << R_DMA_CH2_DESCR__descr__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH2_DESCR_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH2_DESCR. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH2_DESCR_(f1_,v1) ( \ - (R_DMA_CH2_DESCR__descr__##f1_##_VAL(R_DMA_CH2_DESCR_, descr_, v1) << R_DMA_CH2_DESCR__descr__BITNR) \ -) - -#endif - -/* - * R_DMA_CH2_FIRST - * - type: RW - * - addr: 0xb00001a8 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH2_FIRST -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH2_FIRST. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH2_FIRST. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH2_FIRST(f1,v1) ( \ - R_DMA_CH2_FIRST__WRITE(R_DMA_CH2_FIRST__ADDR, ( \ - REG_VAL__R_DMA_CH2_FIRST_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH2_FIRST -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH2_FIRST(f1,v1) ( \ - (R_DMA_CH2_FIRST__first__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH2_FIRST -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH2_FIRST. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH2_FIRST(f1,v1) ( \ - (R_DMA_CH2_FIRST__first__##f1##__VAL(R_DMA_CH2_FIRST_, first_, v1) << R_DMA_CH2_FIRST__first__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH2_FIRST_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH2_FIRST. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH2_FIRST_(f1_,v1) ( \ - (R_DMA_CH2_FIRST__first__##f1_##_VAL(R_DMA_CH2_FIRST_, first_, v1) << R_DMA_CH2_FIRST__first__BITNR) \ -) - -#endif - -/* - * R_DMA_CH2_HWSW - * - type: RW - * - addr: 0xb0000120 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH2_HWSW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH2_HWSW. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH2_HWSW. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH2_HWSW(f1,v1,f2,v2) ( \ - R_DMA_CH2_HWSW__WRITE(R_DMA_CH2_HWSW__ADDR, ( \ - REG_VAL__R_DMA_CH2_HWSW_(f1##_,v1,f2##_,v2) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH2_HWSW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH2_HWSW(f1,v1,f2,v2) ( \ - (R_DMA_CH2_HWSW__hw__##f1##__MASK & REG__##v1) | \ - (R_DMA_CH2_HWSW__sw__##f2##__MASK & REG__##v2) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH2_HWSW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH2_HWSW. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH2_HWSW(f1,v1,f2,v2) ( \ - (R_DMA_CH2_HWSW__hw__##f1##__VAL(R_DMA_CH2_HWSW_, hw_, v1) << R_DMA_CH2_HWSW__hw__BITNR) | \ - (R_DMA_CH2_HWSW__sw__##f2##__VAL(R_DMA_CH2_HWSW_, sw_, v2) << R_DMA_CH2_HWSW__sw__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH2_HWSW_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH2_HWSW. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH2_HWSW_(f1_,v1,f2_,v2) ( \ - (R_DMA_CH2_HWSW__hw__##f1_##_VAL(R_DMA_CH2_HWSW_, hw_, v1) << R_DMA_CH2_HWSW__hw__BITNR) | \ - (R_DMA_CH2_HWSW__sw__##f2_##_VAL(R_DMA_CH2_HWSW_, sw_, v2) << R_DMA_CH2_HWSW__sw__BITNR) \ -) - -#endif - -/* - * R_DMA_CH2_NEXT - * - type: RW - * - addr: 0xb0000124 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH2_NEXT -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH2_NEXT. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH2_NEXT. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH2_NEXT(f1,v1) ( \ - R_DMA_CH2_NEXT__WRITE(R_DMA_CH2_NEXT__ADDR, ( \ - REG_VAL__R_DMA_CH2_NEXT_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH2_NEXT -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH2_NEXT(f1,v1) ( \ - (R_DMA_CH2_NEXT__next__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH2_NEXT -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH2_NEXT. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH2_NEXT(f1,v1) ( \ - (R_DMA_CH2_NEXT__next__##f1##__VAL(R_DMA_CH2_NEXT_, next_, v1) << R_DMA_CH2_NEXT__next__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH2_NEXT_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH2_NEXT. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH2_NEXT_(f1_,v1) ( \ - (R_DMA_CH2_NEXT__next__##f1_##_VAL(R_DMA_CH2_NEXT_, next_, v1) << R_DMA_CH2_NEXT__next__BITNR) \ -) - -#endif - -/* - * R_DMA_CH2_STATUS - * - type: RO - * - addr: 0xb00001da - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH2_STATUS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH2_STATUS(f1,v1) ( \ - (R_DMA_CH2_STATUS__avail__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH2_STATUS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH2_STATUS. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH2_STATUS(f1,v1) ( \ - (R_DMA_CH2_STATUS__avail__##f1##__VAL(R_DMA_CH2_STATUS_, avail_, v1) << R_DMA_CH2_STATUS__avail__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH2_STATUS_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH2_STATUS. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH2_STATUS_(f1_,v1) ( \ - (R_DMA_CH2_STATUS__avail__##f1_##_VAL(R_DMA_CH2_STATUS_, avail_, v1) << R_DMA_CH2_STATUS__avail__BITNR) \ -) - -#endif - -/* - * R_DMA_CH3_BUF - * - type: RW - * - addr: 0xb0000138 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH3_BUF -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH3_BUF. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH3_BUF. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH3_BUF(f1,v1) ( \ - R_DMA_CH3_BUF__WRITE(R_DMA_CH3_BUF__ADDR, ( \ - REG_VAL__R_DMA_CH3_BUF_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH3_BUF -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH3_BUF(f1,v1) ( \ - (R_DMA_CH3_BUF__buf__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH3_BUF -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH3_BUF. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH3_BUF(f1,v1) ( \ - (R_DMA_CH3_BUF__buf__##f1##__VAL(R_DMA_CH3_BUF_, buf_, v1) << R_DMA_CH3_BUF__buf__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH3_BUF_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH3_BUF. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH3_BUF_(f1_,v1) ( \ - (R_DMA_CH3_BUF__buf__##f1_##_VAL(R_DMA_CH3_BUF_, buf_, v1) << R_DMA_CH3_BUF__buf__BITNR) \ -) - -#endif - -/* - * R_DMA_CH3_CLR_INTR - * - type: WO - * - addr: 0xb00001dd - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH3_CLR_INTR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH3_CLR_INTR. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH3_CLR_INTR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH3_CLR_INTR(f1,v1,f2,v2) ( \ - *R_DMA_CH3_CLR_INTR__SADDR = ( \ - REG_INITIATED(R_DMA_CH3_CLR_INTR_) \ - REG_VAL__R_DMA_CH3_CLR_INTR_(f1##_,v1,f2##_,v2) \ - ), \ - R_DMA_CH3_CLR_INTR__WRITE(R_DMA_CH3_CLR_INTR__ADDR, *R_DMA_CH3_CLR_INTR__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH3_CLR_INTR__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH3_CLR_INTR. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_DMA_CH3_CLR_INTR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH3_CLR_INTR__SHADOW(f1,v1,f2,v2) ( \ - *R_DMA_CH3_CLR_INTR__SADDR = ( \ - REG_INITIATED(R_DMA_CH3_CLR_INTR_) \ - REG_VAL__R_DMA_CH3_CLR_INTR_(f1##_,v1,f2##_,v2) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH3_CLR_INTR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH3_CLR_INTR(f1,v1,f2,v2) ( \ - (R_DMA_CH3_CLR_INTR__clr_eop__##f1##__MASK & REG__##v1) | \ - (R_DMA_CH3_CLR_INTR__clr_descr__##f2##__MASK & REG__##v2) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH3_CLR_INTR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH3_CLR_INTR. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH3_CLR_INTR(f1,v1,f2,v2) ( \ - (R_DMA_CH3_CLR_INTR__clr_eop__##f1##__VAL(R_DMA_CH3_CLR_INTR_, clr_eop_, v1) << R_DMA_CH3_CLR_INTR__clr_eop__BITNR) | \ - (R_DMA_CH3_CLR_INTR__clr_descr__##f2##__VAL(R_DMA_CH3_CLR_INTR_, clr_descr_, v2) << R_DMA_CH3_CLR_INTR__clr_descr__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH3_CLR_INTR_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH3_CLR_INTR. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH3_CLR_INTR_(f1_,v1,f2_,v2) ( \ - (R_DMA_CH3_CLR_INTR__clr_eop__##f1_##_VAL(R_DMA_CH3_CLR_INTR_, clr_eop_, v1) << R_DMA_CH3_CLR_INTR__clr_eop__BITNR) | \ - (R_DMA_CH3_CLR_INTR__clr_descr__##f2_##_VAL(R_DMA_CH3_CLR_INTR_, clr_descr_, v2) << R_DMA_CH3_CLR_INTR__clr_descr__BITNR) \ -) - -#endif - -/* - * R_DMA_CH3_CMD - * - type: RW - * - addr: 0xb00001dc - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH3_CMD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH3_CMD. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH3_CMD. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH3_CMD(f1,v1) ( \ - R_DMA_CH3_CMD__WRITE(R_DMA_CH3_CMD__ADDR, ( \ - REG_VAL__R_DMA_CH3_CMD_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH3_CMD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH3_CMD(f1,v1) ( \ - (R_DMA_CH3_CMD__cmd__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH3_CMD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH3_CMD. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH3_CMD(f1,v1) ( \ - (R_DMA_CH3_CMD__cmd__##f1##__VAL(R_DMA_CH3_CMD_, cmd_, v1) << R_DMA_CH3_CMD__cmd__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH3_CMD_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH3_CMD. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH3_CMD_(f1_,v1) ( \ - (R_DMA_CH3_CMD__cmd__##f1_##_VAL(R_DMA_CH3_CMD_, cmd_, v1) << R_DMA_CH3_CMD__cmd__BITNR) \ -) - -#endif - -/* - * R_DMA_CH3_DESCR - * - type: RW - * - addr: 0xb000013c - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH3_DESCR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH3_DESCR. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH3_DESCR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH3_DESCR(f1,v1) ( \ - R_DMA_CH3_DESCR__WRITE(R_DMA_CH3_DESCR__ADDR, ( \ - REG_VAL__R_DMA_CH3_DESCR_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH3_DESCR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH3_DESCR(f1,v1) ( \ - (R_DMA_CH3_DESCR__descr__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH3_DESCR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH3_DESCR. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH3_DESCR(f1,v1) ( \ - (R_DMA_CH3_DESCR__descr__##f1##__VAL(R_DMA_CH3_DESCR_, descr_, v1) << R_DMA_CH3_DESCR__descr__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH3_DESCR_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH3_DESCR. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH3_DESCR_(f1_,v1) ( \ - (R_DMA_CH3_DESCR__descr__##f1_##_VAL(R_DMA_CH3_DESCR_, descr_, v1) << R_DMA_CH3_DESCR__descr__BITNR) \ -) - -#endif - -/* - * R_DMA_CH3_FIRST - * - type: RW - * - addr: 0xb00001ac - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH3_FIRST -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH3_FIRST. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH3_FIRST. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH3_FIRST(f1,v1) ( \ - R_DMA_CH3_FIRST__WRITE(R_DMA_CH3_FIRST__ADDR, ( \ - REG_VAL__R_DMA_CH3_FIRST_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH3_FIRST -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH3_FIRST(f1,v1) ( \ - (R_DMA_CH3_FIRST__first__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH3_FIRST -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH3_FIRST. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH3_FIRST(f1,v1) ( \ - (R_DMA_CH3_FIRST__first__##f1##__VAL(R_DMA_CH3_FIRST_, first_, v1) << R_DMA_CH3_FIRST__first__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH3_FIRST_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH3_FIRST. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH3_FIRST_(f1_,v1) ( \ - (R_DMA_CH3_FIRST__first__##f1_##_VAL(R_DMA_CH3_FIRST_, first_, v1) << R_DMA_CH3_FIRST__first__BITNR) \ -) - -#endif - -/* - * R_DMA_CH3_HWSW - * - type: RW - * - addr: 0xb0000130 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH3_HWSW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH3_HWSW. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH3_HWSW. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH3_HWSW(f1,v1,f2,v2) ( \ - R_DMA_CH3_HWSW__WRITE(R_DMA_CH3_HWSW__ADDR, ( \ - REG_VAL__R_DMA_CH3_HWSW_(f1##_,v1,f2##_,v2) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH3_HWSW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH3_HWSW(f1,v1,f2,v2) ( \ - (R_DMA_CH3_HWSW__hw__##f1##__MASK & REG__##v1) | \ - (R_DMA_CH3_HWSW__sw__##f2##__MASK & REG__##v2) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH3_HWSW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH3_HWSW. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH3_HWSW(f1,v1,f2,v2) ( \ - (R_DMA_CH3_HWSW__hw__##f1##__VAL(R_DMA_CH3_HWSW_, hw_, v1) << R_DMA_CH3_HWSW__hw__BITNR) | \ - (R_DMA_CH3_HWSW__sw__##f2##__VAL(R_DMA_CH3_HWSW_, sw_, v2) << R_DMA_CH3_HWSW__sw__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH3_HWSW_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH3_HWSW. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH3_HWSW_(f1_,v1,f2_,v2) ( \ - (R_DMA_CH3_HWSW__hw__##f1_##_VAL(R_DMA_CH3_HWSW_, hw_, v1) << R_DMA_CH3_HWSW__hw__BITNR) | \ - (R_DMA_CH3_HWSW__sw__##f2_##_VAL(R_DMA_CH3_HWSW_, sw_, v2) << R_DMA_CH3_HWSW__sw__BITNR) \ -) - -#endif - -/* - * R_DMA_CH3_NEXT - * - type: RW - * - addr: 0xb0000134 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH3_NEXT -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH3_NEXT. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH3_NEXT. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH3_NEXT(f1,v1) ( \ - R_DMA_CH3_NEXT__WRITE(R_DMA_CH3_NEXT__ADDR, ( \ - REG_VAL__R_DMA_CH3_NEXT_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH3_NEXT -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH3_NEXT(f1,v1) ( \ - (R_DMA_CH3_NEXT__next__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH3_NEXT -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH3_NEXT. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH3_NEXT(f1,v1) ( \ - (R_DMA_CH3_NEXT__next__##f1##__VAL(R_DMA_CH3_NEXT_, next_, v1) << R_DMA_CH3_NEXT__next__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH3_NEXT_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH3_NEXT. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH3_NEXT_(f1_,v1) ( \ - (R_DMA_CH3_NEXT__next__##f1_##_VAL(R_DMA_CH3_NEXT_, next_, v1) << R_DMA_CH3_NEXT__next__BITNR) \ -) - -#endif - -/* - * R_DMA_CH3_STATUS - * - type: RO - * - addr: 0xb00001de - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH3_STATUS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH3_STATUS(f1,v1) ( \ - (R_DMA_CH3_STATUS__avail__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH3_STATUS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH3_STATUS. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH3_STATUS(f1,v1) ( \ - (R_DMA_CH3_STATUS__avail__##f1##__VAL(R_DMA_CH3_STATUS_, avail_, v1) << R_DMA_CH3_STATUS__avail__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH3_STATUS_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH3_STATUS. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH3_STATUS_(f1_,v1) ( \ - (R_DMA_CH3_STATUS__avail__##f1_##_VAL(R_DMA_CH3_STATUS_, avail_, v1) << R_DMA_CH3_STATUS__avail__BITNR) \ -) - -#endif - -/* - * R_DMA_CH4_BUF - * - type: RW - * - addr: 0xb0000148 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH4_BUF -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH4_BUF. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH4_BUF. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH4_BUF(f1,v1) ( \ - R_DMA_CH4_BUF__WRITE(R_DMA_CH4_BUF__ADDR, ( \ - REG_VAL__R_DMA_CH4_BUF_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH4_BUF -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH4_BUF(f1,v1) ( \ - (R_DMA_CH4_BUF__buf__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH4_BUF -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH4_BUF. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH4_BUF(f1,v1) ( \ - (R_DMA_CH4_BUF__buf__##f1##__VAL(R_DMA_CH4_BUF_, buf_, v1) << R_DMA_CH4_BUF__buf__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH4_BUF_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH4_BUF. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH4_BUF_(f1_,v1) ( \ - (R_DMA_CH4_BUF__buf__##f1_##_VAL(R_DMA_CH4_BUF_, buf_, v1) << R_DMA_CH4_BUF__buf__BITNR) \ -) - -#endif - -/* - * R_DMA_CH4_CLR_INTR - * - type: WO - * - addr: 0xb00001e1 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH4_CLR_INTR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH4_CLR_INTR. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH4_CLR_INTR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH4_CLR_INTR(f1,v1,f2,v2) ( \ - *R_DMA_CH4_CLR_INTR__SADDR = ( \ - REG_INITIATED(R_DMA_CH4_CLR_INTR_) \ - REG_VAL__R_DMA_CH4_CLR_INTR_(f1##_,v1,f2##_,v2) \ - ), \ - R_DMA_CH4_CLR_INTR__WRITE(R_DMA_CH4_CLR_INTR__ADDR, *R_DMA_CH4_CLR_INTR__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH4_CLR_INTR__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH4_CLR_INTR. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_DMA_CH4_CLR_INTR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH4_CLR_INTR__SHADOW(f1,v1,f2,v2) ( \ - *R_DMA_CH4_CLR_INTR__SADDR = ( \ - REG_INITIATED(R_DMA_CH4_CLR_INTR_) \ - REG_VAL__R_DMA_CH4_CLR_INTR_(f1##_,v1,f2##_,v2) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH4_CLR_INTR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH4_CLR_INTR(f1,v1,f2,v2) ( \ - (R_DMA_CH4_CLR_INTR__clr_eop__##f1##__MASK & REG__##v1) | \ - (R_DMA_CH4_CLR_INTR__clr_descr__##f2##__MASK & REG__##v2) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH4_CLR_INTR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH4_CLR_INTR. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH4_CLR_INTR(f1,v1,f2,v2) ( \ - (R_DMA_CH4_CLR_INTR__clr_eop__##f1##__VAL(R_DMA_CH4_CLR_INTR_, clr_eop_, v1) << R_DMA_CH4_CLR_INTR__clr_eop__BITNR) | \ - (R_DMA_CH4_CLR_INTR__clr_descr__##f2##__VAL(R_DMA_CH4_CLR_INTR_, clr_descr_, v2) << R_DMA_CH4_CLR_INTR__clr_descr__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH4_CLR_INTR_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH4_CLR_INTR. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH4_CLR_INTR_(f1_,v1,f2_,v2) ( \ - (R_DMA_CH4_CLR_INTR__clr_eop__##f1_##_VAL(R_DMA_CH4_CLR_INTR_, clr_eop_, v1) << R_DMA_CH4_CLR_INTR__clr_eop__BITNR) | \ - (R_DMA_CH4_CLR_INTR__clr_descr__##f2_##_VAL(R_DMA_CH4_CLR_INTR_, clr_descr_, v2) << R_DMA_CH4_CLR_INTR__clr_descr__BITNR) \ -) - -#endif - -/* - * R_DMA_CH4_CMD - * - type: RW - * - addr: 0xb00001e0 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH4_CMD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH4_CMD. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH4_CMD. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH4_CMD(f1,v1) ( \ - R_DMA_CH4_CMD__WRITE(R_DMA_CH4_CMD__ADDR, ( \ - REG_VAL__R_DMA_CH4_CMD_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH4_CMD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH4_CMD(f1,v1) ( \ - (R_DMA_CH4_CMD__cmd__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH4_CMD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH4_CMD. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH4_CMD(f1,v1) ( \ - (R_DMA_CH4_CMD__cmd__##f1##__VAL(R_DMA_CH4_CMD_, cmd_, v1) << R_DMA_CH4_CMD__cmd__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH4_CMD_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH4_CMD. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH4_CMD_(f1_,v1) ( \ - (R_DMA_CH4_CMD__cmd__##f1_##_VAL(R_DMA_CH4_CMD_, cmd_, v1) << R_DMA_CH4_CMD__cmd__BITNR) \ -) - -#endif - -/* - * R_DMA_CH4_DESCR - * - type: RW - * - addr: 0xb000014c - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH4_DESCR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH4_DESCR. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH4_DESCR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH4_DESCR(f1,v1) ( \ - R_DMA_CH4_DESCR__WRITE(R_DMA_CH4_DESCR__ADDR, ( \ - REG_VAL__R_DMA_CH4_DESCR_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH4_DESCR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH4_DESCR(f1,v1) ( \ - (R_DMA_CH4_DESCR__descr__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH4_DESCR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH4_DESCR. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH4_DESCR(f1,v1) ( \ - (R_DMA_CH4_DESCR__descr__##f1##__VAL(R_DMA_CH4_DESCR_, descr_, v1) << R_DMA_CH4_DESCR__descr__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH4_DESCR_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH4_DESCR. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH4_DESCR_(f1_,v1) ( \ - (R_DMA_CH4_DESCR__descr__##f1_##_VAL(R_DMA_CH4_DESCR_, descr_, v1) << R_DMA_CH4_DESCR__descr__BITNR) \ -) - -#endif - -/* - * R_DMA_CH4_FIRST - * - type: RW - * - addr: 0xb00001b0 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH4_FIRST -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH4_FIRST. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH4_FIRST. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH4_FIRST(f1,v1) ( \ - R_DMA_CH4_FIRST__WRITE(R_DMA_CH4_FIRST__ADDR, ( \ - REG_VAL__R_DMA_CH4_FIRST_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH4_FIRST -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH4_FIRST(f1,v1) ( \ - (R_DMA_CH4_FIRST__first__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH4_FIRST -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH4_FIRST. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH4_FIRST(f1,v1) ( \ - (R_DMA_CH4_FIRST__first__##f1##__VAL(R_DMA_CH4_FIRST_, first_, v1) << R_DMA_CH4_FIRST__first__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH4_FIRST_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH4_FIRST. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH4_FIRST_(f1_,v1) ( \ - (R_DMA_CH4_FIRST__first__##f1_##_VAL(R_DMA_CH4_FIRST_, first_, v1) << R_DMA_CH4_FIRST__first__BITNR) \ -) - -#endif - -/* - * R_DMA_CH4_HWSW - * - type: RW - * - addr: 0xb0000140 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH4_HWSW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH4_HWSW. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH4_HWSW. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH4_HWSW(f1,v1,f2,v2) ( \ - R_DMA_CH4_HWSW__WRITE(R_DMA_CH4_HWSW__ADDR, ( \ - REG_VAL__R_DMA_CH4_HWSW_(f1##_,v1,f2##_,v2) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH4_HWSW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH4_HWSW(f1,v1,f2,v2) ( \ - (R_DMA_CH4_HWSW__hw__##f1##__MASK & REG__##v1) | \ - (R_DMA_CH4_HWSW__sw__##f2##__MASK & REG__##v2) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH4_HWSW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH4_HWSW. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH4_HWSW(f1,v1,f2,v2) ( \ - (R_DMA_CH4_HWSW__hw__##f1##__VAL(R_DMA_CH4_HWSW_, hw_, v1) << R_DMA_CH4_HWSW__hw__BITNR) | \ - (R_DMA_CH4_HWSW__sw__##f2##__VAL(R_DMA_CH4_HWSW_, sw_, v2) << R_DMA_CH4_HWSW__sw__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH4_HWSW_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH4_HWSW. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH4_HWSW_(f1_,v1,f2_,v2) ( \ - (R_DMA_CH4_HWSW__hw__##f1_##_VAL(R_DMA_CH4_HWSW_, hw_, v1) << R_DMA_CH4_HWSW__hw__BITNR) | \ - (R_DMA_CH4_HWSW__sw__##f2_##_VAL(R_DMA_CH4_HWSW_, sw_, v2) << R_DMA_CH4_HWSW__sw__BITNR) \ -) - -#endif - -/* - * R_DMA_CH4_NEXT - * - type: RW - * - addr: 0xb0000144 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH4_NEXT -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH4_NEXT. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH4_NEXT. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH4_NEXT(f1,v1) ( \ - R_DMA_CH4_NEXT__WRITE(R_DMA_CH4_NEXT__ADDR, ( \ - REG_VAL__R_DMA_CH4_NEXT_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH4_NEXT -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH4_NEXT(f1,v1) ( \ - (R_DMA_CH4_NEXT__next__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH4_NEXT -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH4_NEXT. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH4_NEXT(f1,v1) ( \ - (R_DMA_CH4_NEXT__next__##f1##__VAL(R_DMA_CH4_NEXT_, next_, v1) << R_DMA_CH4_NEXT__next__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH4_NEXT_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH4_NEXT. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH4_NEXT_(f1_,v1) ( \ - (R_DMA_CH4_NEXT__next__##f1_##_VAL(R_DMA_CH4_NEXT_, next_, v1) << R_DMA_CH4_NEXT__next__BITNR) \ -) - -#endif - -/* - * R_DMA_CH4_STATUS - * - type: RO - * - addr: 0xb00001e2 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH4_STATUS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH4_STATUS(f1,v1) ( \ - (R_DMA_CH4_STATUS__avail__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH4_STATUS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH4_STATUS. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH4_STATUS(f1,v1) ( \ - (R_DMA_CH4_STATUS__avail__##f1##__VAL(R_DMA_CH4_STATUS_, avail_, v1) << R_DMA_CH4_STATUS__avail__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH4_STATUS_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH4_STATUS. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH4_STATUS_(f1_,v1) ( \ - (R_DMA_CH4_STATUS__avail__##f1_##_VAL(R_DMA_CH4_STATUS_, avail_, v1) << R_DMA_CH4_STATUS__avail__BITNR) \ -) - -#endif - -/* - * R_DMA_CH5_BUF - * - type: RW - * - addr: 0xb0000158 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH5_BUF -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH5_BUF. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH5_BUF. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH5_BUF(f1,v1) ( \ - R_DMA_CH5_BUF__WRITE(R_DMA_CH5_BUF__ADDR, ( \ - REG_VAL__R_DMA_CH5_BUF_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH5_BUF -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH5_BUF(f1,v1) ( \ - (R_DMA_CH5_BUF__buf__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH5_BUF -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH5_BUF. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH5_BUF(f1,v1) ( \ - (R_DMA_CH5_BUF__buf__##f1##__VAL(R_DMA_CH5_BUF_, buf_, v1) << R_DMA_CH5_BUF__buf__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH5_BUF_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH5_BUF. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH5_BUF_(f1_,v1) ( \ - (R_DMA_CH5_BUF__buf__##f1_##_VAL(R_DMA_CH5_BUF_, buf_, v1) << R_DMA_CH5_BUF__buf__BITNR) \ -) - -#endif - -/* - * R_DMA_CH5_CLR_INTR - * - type: WO - * - addr: 0xb00001e5 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH5_CLR_INTR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH5_CLR_INTR. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH5_CLR_INTR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH5_CLR_INTR(f1,v1,f2,v2) ( \ - *R_DMA_CH5_CLR_INTR__SADDR = ( \ - REG_INITIATED(R_DMA_CH5_CLR_INTR_) \ - REG_VAL__R_DMA_CH5_CLR_INTR_(f1##_,v1,f2##_,v2) \ - ), \ - R_DMA_CH5_CLR_INTR__WRITE(R_DMA_CH5_CLR_INTR__ADDR, *R_DMA_CH5_CLR_INTR__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH5_CLR_INTR__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH5_CLR_INTR. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_DMA_CH5_CLR_INTR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH5_CLR_INTR__SHADOW(f1,v1,f2,v2) ( \ - *R_DMA_CH5_CLR_INTR__SADDR = ( \ - REG_INITIATED(R_DMA_CH5_CLR_INTR_) \ - REG_VAL__R_DMA_CH5_CLR_INTR_(f1##_,v1,f2##_,v2) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH5_CLR_INTR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH5_CLR_INTR(f1,v1,f2,v2) ( \ - (R_DMA_CH5_CLR_INTR__clr_eop__##f1##__MASK & REG__##v1) | \ - (R_DMA_CH5_CLR_INTR__clr_descr__##f2##__MASK & REG__##v2) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH5_CLR_INTR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH5_CLR_INTR. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH5_CLR_INTR(f1,v1,f2,v2) ( \ - (R_DMA_CH5_CLR_INTR__clr_eop__##f1##__VAL(R_DMA_CH5_CLR_INTR_, clr_eop_, v1) << R_DMA_CH5_CLR_INTR__clr_eop__BITNR) | \ - (R_DMA_CH5_CLR_INTR__clr_descr__##f2##__VAL(R_DMA_CH5_CLR_INTR_, clr_descr_, v2) << R_DMA_CH5_CLR_INTR__clr_descr__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH5_CLR_INTR_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH5_CLR_INTR. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH5_CLR_INTR_(f1_,v1,f2_,v2) ( \ - (R_DMA_CH5_CLR_INTR__clr_eop__##f1_##_VAL(R_DMA_CH5_CLR_INTR_, clr_eop_, v1) << R_DMA_CH5_CLR_INTR__clr_eop__BITNR) | \ - (R_DMA_CH5_CLR_INTR__clr_descr__##f2_##_VAL(R_DMA_CH5_CLR_INTR_, clr_descr_, v2) << R_DMA_CH5_CLR_INTR__clr_descr__BITNR) \ -) - -#endif - -/* - * R_DMA_CH5_CMD - * - type: RW - * - addr: 0xb00001e4 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH5_CMD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH5_CMD. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH5_CMD. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH5_CMD(f1,v1) ( \ - R_DMA_CH5_CMD__WRITE(R_DMA_CH5_CMD__ADDR, ( \ - REG_VAL__R_DMA_CH5_CMD_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH5_CMD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH5_CMD(f1,v1) ( \ - (R_DMA_CH5_CMD__cmd__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH5_CMD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH5_CMD. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH5_CMD(f1,v1) ( \ - (R_DMA_CH5_CMD__cmd__##f1##__VAL(R_DMA_CH5_CMD_, cmd_, v1) << R_DMA_CH5_CMD__cmd__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH5_CMD_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH5_CMD. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH5_CMD_(f1_,v1) ( \ - (R_DMA_CH5_CMD__cmd__##f1_##_VAL(R_DMA_CH5_CMD_, cmd_, v1) << R_DMA_CH5_CMD__cmd__BITNR) \ -) - -#endif - -/* - * R_DMA_CH5_DESCR - * - type: RW - * - addr: 0xb000015c - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH5_DESCR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH5_DESCR. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH5_DESCR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH5_DESCR(f1,v1) ( \ - R_DMA_CH5_DESCR__WRITE(R_DMA_CH5_DESCR__ADDR, ( \ - REG_VAL__R_DMA_CH5_DESCR_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH5_DESCR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH5_DESCR(f1,v1) ( \ - (R_DMA_CH5_DESCR__descr__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH5_DESCR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH5_DESCR. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH5_DESCR(f1,v1) ( \ - (R_DMA_CH5_DESCR__descr__##f1##__VAL(R_DMA_CH5_DESCR_, descr_, v1) << R_DMA_CH5_DESCR__descr__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH5_DESCR_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH5_DESCR. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH5_DESCR_(f1_,v1) ( \ - (R_DMA_CH5_DESCR__descr__##f1_##_VAL(R_DMA_CH5_DESCR_, descr_, v1) << R_DMA_CH5_DESCR__descr__BITNR) \ -) - -#endif - -/* - * R_DMA_CH5_FIRST - * - type: RW - * - addr: 0xb00001b4 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH5_FIRST -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH5_FIRST. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH5_FIRST. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH5_FIRST(f1,v1) ( \ - R_DMA_CH5_FIRST__WRITE(R_DMA_CH5_FIRST__ADDR, ( \ - REG_VAL__R_DMA_CH5_FIRST_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH5_FIRST -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH5_FIRST(f1,v1) ( \ - (R_DMA_CH5_FIRST__first__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH5_FIRST -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH5_FIRST. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH5_FIRST(f1,v1) ( \ - (R_DMA_CH5_FIRST__first__##f1##__VAL(R_DMA_CH5_FIRST_, first_, v1) << R_DMA_CH5_FIRST__first__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH5_FIRST_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH5_FIRST. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH5_FIRST_(f1_,v1) ( \ - (R_DMA_CH5_FIRST__first__##f1_##_VAL(R_DMA_CH5_FIRST_, first_, v1) << R_DMA_CH5_FIRST__first__BITNR) \ -) - -#endif - -/* - * R_DMA_CH5_HWSW - * - type: RW - * - addr: 0xb0000150 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH5_HWSW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH5_HWSW. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH5_HWSW. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH5_HWSW(f1,v1,f2,v2) ( \ - R_DMA_CH5_HWSW__WRITE(R_DMA_CH5_HWSW__ADDR, ( \ - REG_VAL__R_DMA_CH5_HWSW_(f1##_,v1,f2##_,v2) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH5_HWSW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH5_HWSW(f1,v1,f2,v2) ( \ - (R_DMA_CH5_HWSW__hw__##f1##__MASK & REG__##v1) | \ - (R_DMA_CH5_HWSW__sw__##f2##__MASK & REG__##v2) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH5_HWSW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH5_HWSW. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH5_HWSW(f1,v1,f2,v2) ( \ - (R_DMA_CH5_HWSW__hw__##f1##__VAL(R_DMA_CH5_HWSW_, hw_, v1) << R_DMA_CH5_HWSW__hw__BITNR) | \ - (R_DMA_CH5_HWSW__sw__##f2##__VAL(R_DMA_CH5_HWSW_, sw_, v2) << R_DMA_CH5_HWSW__sw__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH5_HWSW_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH5_HWSW. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH5_HWSW_(f1_,v1,f2_,v2) ( \ - (R_DMA_CH5_HWSW__hw__##f1_##_VAL(R_DMA_CH5_HWSW_, hw_, v1) << R_DMA_CH5_HWSW__hw__BITNR) | \ - (R_DMA_CH5_HWSW__sw__##f2_##_VAL(R_DMA_CH5_HWSW_, sw_, v2) << R_DMA_CH5_HWSW__sw__BITNR) \ -) - -#endif - -/* - * R_DMA_CH5_NEXT - * - type: RW - * - addr: 0xb0000154 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH5_NEXT -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH5_NEXT. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH5_NEXT. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH5_NEXT(f1,v1) ( \ - R_DMA_CH5_NEXT__WRITE(R_DMA_CH5_NEXT__ADDR, ( \ - REG_VAL__R_DMA_CH5_NEXT_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH5_NEXT -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH5_NEXT(f1,v1) ( \ - (R_DMA_CH5_NEXT__next__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH5_NEXT -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH5_NEXT. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH5_NEXT(f1,v1) ( \ - (R_DMA_CH5_NEXT__next__##f1##__VAL(R_DMA_CH5_NEXT_, next_, v1) << R_DMA_CH5_NEXT__next__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH5_NEXT_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH5_NEXT. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH5_NEXT_(f1_,v1) ( \ - (R_DMA_CH5_NEXT__next__##f1_##_VAL(R_DMA_CH5_NEXT_, next_, v1) << R_DMA_CH5_NEXT__next__BITNR) \ -) - -#endif - -/* - * R_DMA_CH5_STATUS - * - type: RO - * - addr: 0xb00001e6 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH5_STATUS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH5_STATUS(f1,v1) ( \ - (R_DMA_CH5_STATUS__avail__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH5_STATUS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH5_STATUS. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH5_STATUS(f1,v1) ( \ - (R_DMA_CH5_STATUS__avail__##f1##__VAL(R_DMA_CH5_STATUS_, avail_, v1) << R_DMA_CH5_STATUS__avail__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH5_STATUS_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH5_STATUS. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH5_STATUS_(f1_,v1) ( \ - (R_DMA_CH5_STATUS__avail__##f1_##_VAL(R_DMA_CH5_STATUS_, avail_, v1) << R_DMA_CH5_STATUS__avail__BITNR) \ -) - -#endif - -/* - * R_DMA_CH6_BUF - * - type: RW - * - addr: 0xb0000168 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH6_BUF -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH6_BUF. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH6_BUF. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH6_BUF(f1,v1) ( \ - R_DMA_CH6_BUF__WRITE(R_DMA_CH6_BUF__ADDR, ( \ - REG_VAL__R_DMA_CH6_BUF_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH6_BUF -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH6_BUF(f1,v1) ( \ - (R_DMA_CH6_BUF__buf__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH6_BUF -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH6_BUF. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH6_BUF(f1,v1) ( \ - (R_DMA_CH6_BUF__buf__##f1##__VAL(R_DMA_CH6_BUF_, buf_, v1) << R_DMA_CH6_BUF__buf__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH6_BUF_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH6_BUF. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH6_BUF_(f1_,v1) ( \ - (R_DMA_CH6_BUF__buf__##f1_##_VAL(R_DMA_CH6_BUF_, buf_, v1) << R_DMA_CH6_BUF__buf__BITNR) \ -) - -#endif - -/* - * R_DMA_CH6_CLR_INTR - * - type: WO - * - addr: 0xb00001e9 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH6_CLR_INTR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH6_CLR_INTR. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH6_CLR_INTR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH6_CLR_INTR(f1,v1,f2,v2) ( \ - *R_DMA_CH6_CLR_INTR__SADDR = ( \ - REG_INITIATED(R_DMA_CH6_CLR_INTR_) \ - REG_VAL__R_DMA_CH6_CLR_INTR_(f1##_,v1,f2##_,v2) \ - ), \ - R_DMA_CH6_CLR_INTR__WRITE(R_DMA_CH6_CLR_INTR__ADDR, *R_DMA_CH6_CLR_INTR__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH6_CLR_INTR__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH6_CLR_INTR. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_DMA_CH6_CLR_INTR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH6_CLR_INTR__SHADOW(f1,v1,f2,v2) ( \ - *R_DMA_CH6_CLR_INTR__SADDR = ( \ - REG_INITIATED(R_DMA_CH6_CLR_INTR_) \ - REG_VAL__R_DMA_CH6_CLR_INTR_(f1##_,v1,f2##_,v2) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH6_CLR_INTR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH6_CLR_INTR(f1,v1,f2,v2) ( \ - (R_DMA_CH6_CLR_INTR__clr_eop__##f1##__MASK & REG__##v1) | \ - (R_DMA_CH6_CLR_INTR__clr_descr__##f2##__MASK & REG__##v2) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH6_CLR_INTR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH6_CLR_INTR. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH6_CLR_INTR(f1,v1,f2,v2) ( \ - (R_DMA_CH6_CLR_INTR__clr_eop__##f1##__VAL(R_DMA_CH6_CLR_INTR_, clr_eop_, v1) << R_DMA_CH6_CLR_INTR__clr_eop__BITNR) | \ - (R_DMA_CH6_CLR_INTR__clr_descr__##f2##__VAL(R_DMA_CH6_CLR_INTR_, clr_descr_, v2) << R_DMA_CH6_CLR_INTR__clr_descr__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH6_CLR_INTR_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH6_CLR_INTR. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH6_CLR_INTR_(f1_,v1,f2_,v2) ( \ - (R_DMA_CH6_CLR_INTR__clr_eop__##f1_##_VAL(R_DMA_CH6_CLR_INTR_, clr_eop_, v1) << R_DMA_CH6_CLR_INTR__clr_eop__BITNR) | \ - (R_DMA_CH6_CLR_INTR__clr_descr__##f2_##_VAL(R_DMA_CH6_CLR_INTR_, clr_descr_, v2) << R_DMA_CH6_CLR_INTR__clr_descr__BITNR) \ -) - -#endif - -/* - * R_DMA_CH6_CMD - * - type: RW - * - addr: 0xb00001e8 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH6_CMD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH6_CMD. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH6_CMD. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH6_CMD(f1,v1) ( \ - R_DMA_CH6_CMD__WRITE(R_DMA_CH6_CMD__ADDR, ( \ - REG_VAL__R_DMA_CH6_CMD_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH6_CMD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH6_CMD(f1,v1) ( \ - (R_DMA_CH6_CMD__cmd__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH6_CMD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH6_CMD. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH6_CMD(f1,v1) ( \ - (R_DMA_CH6_CMD__cmd__##f1##__VAL(R_DMA_CH6_CMD_, cmd_, v1) << R_DMA_CH6_CMD__cmd__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH6_CMD_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH6_CMD. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH6_CMD_(f1_,v1) ( \ - (R_DMA_CH6_CMD__cmd__##f1_##_VAL(R_DMA_CH6_CMD_, cmd_, v1) << R_DMA_CH6_CMD__cmd__BITNR) \ -) - -#endif - -/* - * R_DMA_CH6_DESCR - * - type: RW - * - addr: 0xb000016c - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH6_DESCR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH6_DESCR. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH6_DESCR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH6_DESCR(f1,v1) ( \ - R_DMA_CH6_DESCR__WRITE(R_DMA_CH6_DESCR__ADDR, ( \ - REG_VAL__R_DMA_CH6_DESCR_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH6_DESCR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH6_DESCR(f1,v1) ( \ - (R_DMA_CH6_DESCR__descr__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH6_DESCR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH6_DESCR. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH6_DESCR(f1,v1) ( \ - (R_DMA_CH6_DESCR__descr__##f1##__VAL(R_DMA_CH6_DESCR_, descr_, v1) << R_DMA_CH6_DESCR__descr__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH6_DESCR_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH6_DESCR. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH6_DESCR_(f1_,v1) ( \ - (R_DMA_CH6_DESCR__descr__##f1_##_VAL(R_DMA_CH6_DESCR_, descr_, v1) << R_DMA_CH6_DESCR__descr__BITNR) \ -) - -#endif - -/* - * R_DMA_CH6_FIRST - * - type: RW - * - addr: 0xb00001b8 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH6_FIRST -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH6_FIRST. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH6_FIRST. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH6_FIRST(f1,v1) ( \ - R_DMA_CH6_FIRST__WRITE(R_DMA_CH6_FIRST__ADDR, ( \ - REG_VAL__R_DMA_CH6_FIRST_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH6_FIRST -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH6_FIRST(f1,v1) ( \ - (R_DMA_CH6_FIRST__first__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH6_FIRST -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH6_FIRST. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH6_FIRST(f1,v1) ( \ - (R_DMA_CH6_FIRST__first__##f1##__VAL(R_DMA_CH6_FIRST_, first_, v1) << R_DMA_CH6_FIRST__first__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH6_FIRST_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH6_FIRST. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH6_FIRST_(f1_,v1) ( \ - (R_DMA_CH6_FIRST__first__##f1_##_VAL(R_DMA_CH6_FIRST_, first_, v1) << R_DMA_CH6_FIRST__first__BITNR) \ -) - -#endif - -/* - * R_DMA_CH6_HWSW - * - type: RW - * - addr: 0xb0000160 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH6_HWSW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH6_HWSW. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH6_HWSW. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH6_HWSW(f1,v1,f2,v2) ( \ - R_DMA_CH6_HWSW__WRITE(R_DMA_CH6_HWSW__ADDR, ( \ - REG_VAL__R_DMA_CH6_HWSW_(f1##_,v1,f2##_,v2) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH6_HWSW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH6_HWSW(f1,v1,f2,v2) ( \ - (R_DMA_CH6_HWSW__hw__##f1##__MASK & REG__##v1) | \ - (R_DMA_CH6_HWSW__sw__##f2##__MASK & REG__##v2) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH6_HWSW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH6_HWSW. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH6_HWSW(f1,v1,f2,v2) ( \ - (R_DMA_CH6_HWSW__hw__##f1##__VAL(R_DMA_CH6_HWSW_, hw_, v1) << R_DMA_CH6_HWSW__hw__BITNR) | \ - (R_DMA_CH6_HWSW__sw__##f2##__VAL(R_DMA_CH6_HWSW_, sw_, v2) << R_DMA_CH6_HWSW__sw__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH6_HWSW_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH6_HWSW. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH6_HWSW_(f1_,v1,f2_,v2) ( \ - (R_DMA_CH6_HWSW__hw__##f1_##_VAL(R_DMA_CH6_HWSW_, hw_, v1) << R_DMA_CH6_HWSW__hw__BITNR) | \ - (R_DMA_CH6_HWSW__sw__##f2_##_VAL(R_DMA_CH6_HWSW_, sw_, v2) << R_DMA_CH6_HWSW__sw__BITNR) \ -) - -#endif - -/* - * R_DMA_CH6_NEXT - * - type: RW - * - addr: 0xb0000164 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH6_NEXT -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH6_NEXT. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH6_NEXT. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH6_NEXT(f1,v1) ( \ - R_DMA_CH6_NEXT__WRITE(R_DMA_CH6_NEXT__ADDR, ( \ - REG_VAL__R_DMA_CH6_NEXT_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH6_NEXT -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH6_NEXT(f1,v1) ( \ - (R_DMA_CH6_NEXT__next__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH6_NEXT -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH6_NEXT. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH6_NEXT(f1,v1) ( \ - (R_DMA_CH6_NEXT__next__##f1##__VAL(R_DMA_CH6_NEXT_, next_, v1) << R_DMA_CH6_NEXT__next__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH6_NEXT_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH6_NEXT. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH6_NEXT_(f1_,v1) ( \ - (R_DMA_CH6_NEXT__next__##f1_##_VAL(R_DMA_CH6_NEXT_, next_, v1) << R_DMA_CH6_NEXT__next__BITNR) \ -) - -#endif - -/* - * R_DMA_CH6_STATUS - * - type: RO - * - addr: 0xb00001ea - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH6_STATUS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH6_STATUS(f1,v1) ( \ - (R_DMA_CH6_STATUS__avail__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH6_STATUS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH6_STATUS. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH6_STATUS(f1,v1) ( \ - (R_DMA_CH6_STATUS__avail__##f1##__VAL(R_DMA_CH6_STATUS_, avail_, v1) << R_DMA_CH6_STATUS__avail__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH6_STATUS_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH6_STATUS. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH6_STATUS_(f1_,v1) ( \ - (R_DMA_CH6_STATUS__avail__##f1_##_VAL(R_DMA_CH6_STATUS_, avail_, v1) << R_DMA_CH6_STATUS__avail__BITNR) \ -) - -#endif - -/* - * R_DMA_CH7_BUF - * - type: RW - * - addr: 0xb0000178 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH7_BUF -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH7_BUF. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH7_BUF. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH7_BUF(f1,v1) ( \ - R_DMA_CH7_BUF__WRITE(R_DMA_CH7_BUF__ADDR, ( \ - REG_VAL__R_DMA_CH7_BUF_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH7_BUF -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH7_BUF(f1,v1) ( \ - (R_DMA_CH7_BUF__buf__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH7_BUF -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH7_BUF. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH7_BUF(f1,v1) ( \ - (R_DMA_CH7_BUF__buf__##f1##__VAL(R_DMA_CH7_BUF_, buf_, v1) << R_DMA_CH7_BUF__buf__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH7_BUF_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH7_BUF. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH7_BUF_(f1_,v1) ( \ - (R_DMA_CH7_BUF__buf__##f1_##_VAL(R_DMA_CH7_BUF_, buf_, v1) << R_DMA_CH7_BUF__buf__BITNR) \ -) - -#endif - -/* - * R_DMA_CH7_CLR_INTR - * - type: WO - * - addr: 0xb00001ed - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH7_CLR_INTR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH7_CLR_INTR. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH7_CLR_INTR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH7_CLR_INTR(f1,v1,f2,v2) ( \ - *R_DMA_CH7_CLR_INTR__SADDR = ( \ - REG_INITIATED(R_DMA_CH7_CLR_INTR_) \ - REG_VAL__R_DMA_CH7_CLR_INTR_(f1##_,v1,f2##_,v2) \ - ), \ - R_DMA_CH7_CLR_INTR__WRITE(R_DMA_CH7_CLR_INTR__ADDR, *R_DMA_CH7_CLR_INTR__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH7_CLR_INTR__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH7_CLR_INTR. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_DMA_CH7_CLR_INTR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH7_CLR_INTR__SHADOW(f1,v1,f2,v2) ( \ - *R_DMA_CH7_CLR_INTR__SADDR = ( \ - REG_INITIATED(R_DMA_CH7_CLR_INTR_) \ - REG_VAL__R_DMA_CH7_CLR_INTR_(f1##_,v1,f2##_,v2) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH7_CLR_INTR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH7_CLR_INTR(f1,v1,f2,v2) ( \ - (R_DMA_CH7_CLR_INTR__clr_eop__##f1##__MASK & REG__##v1) | \ - (R_DMA_CH7_CLR_INTR__clr_descr__##f2##__MASK & REG__##v2) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH7_CLR_INTR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH7_CLR_INTR. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH7_CLR_INTR(f1,v1,f2,v2) ( \ - (R_DMA_CH7_CLR_INTR__clr_eop__##f1##__VAL(R_DMA_CH7_CLR_INTR_, clr_eop_, v1) << R_DMA_CH7_CLR_INTR__clr_eop__BITNR) | \ - (R_DMA_CH7_CLR_INTR__clr_descr__##f2##__VAL(R_DMA_CH7_CLR_INTR_, clr_descr_, v2) << R_DMA_CH7_CLR_INTR__clr_descr__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH7_CLR_INTR_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH7_CLR_INTR. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH7_CLR_INTR_(f1_,v1,f2_,v2) ( \ - (R_DMA_CH7_CLR_INTR__clr_eop__##f1_##_VAL(R_DMA_CH7_CLR_INTR_, clr_eop_, v1) << R_DMA_CH7_CLR_INTR__clr_eop__BITNR) | \ - (R_DMA_CH7_CLR_INTR__clr_descr__##f2_##_VAL(R_DMA_CH7_CLR_INTR_, clr_descr_, v2) << R_DMA_CH7_CLR_INTR__clr_descr__BITNR) \ -) - -#endif - -/* - * R_DMA_CH7_CMD - * - type: RW - * - addr: 0xb00001ec - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH7_CMD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH7_CMD. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH7_CMD. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH7_CMD(f1,v1) ( \ - R_DMA_CH7_CMD__WRITE(R_DMA_CH7_CMD__ADDR, ( \ - REG_VAL__R_DMA_CH7_CMD_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH7_CMD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH7_CMD(f1,v1) ( \ - (R_DMA_CH7_CMD__cmd__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH7_CMD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH7_CMD. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH7_CMD(f1,v1) ( \ - (R_DMA_CH7_CMD__cmd__##f1##__VAL(R_DMA_CH7_CMD_, cmd_, v1) << R_DMA_CH7_CMD__cmd__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH7_CMD_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH7_CMD. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH7_CMD_(f1_,v1) ( \ - (R_DMA_CH7_CMD__cmd__##f1_##_VAL(R_DMA_CH7_CMD_, cmd_, v1) << R_DMA_CH7_CMD__cmd__BITNR) \ -) - -#endif - -/* - * R_DMA_CH7_DESCR - * - type: RW - * - addr: 0xb000017c - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH7_DESCR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH7_DESCR. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH7_DESCR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH7_DESCR(f1,v1) ( \ - R_DMA_CH7_DESCR__WRITE(R_DMA_CH7_DESCR__ADDR, ( \ - REG_VAL__R_DMA_CH7_DESCR_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH7_DESCR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH7_DESCR(f1,v1) ( \ - (R_DMA_CH7_DESCR__descr__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH7_DESCR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH7_DESCR. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH7_DESCR(f1,v1) ( \ - (R_DMA_CH7_DESCR__descr__##f1##__VAL(R_DMA_CH7_DESCR_, descr_, v1) << R_DMA_CH7_DESCR__descr__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH7_DESCR_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH7_DESCR. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH7_DESCR_(f1_,v1) ( \ - (R_DMA_CH7_DESCR__descr__##f1_##_VAL(R_DMA_CH7_DESCR_, descr_, v1) << R_DMA_CH7_DESCR__descr__BITNR) \ -) - -#endif - -/* - * R_DMA_CH7_FIRST - * - type: RW - * - addr: 0xb00001bc - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH7_FIRST -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH7_FIRST. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH7_FIRST. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH7_FIRST(f1,v1) ( \ - R_DMA_CH7_FIRST__WRITE(R_DMA_CH7_FIRST__ADDR, ( \ - REG_VAL__R_DMA_CH7_FIRST_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH7_FIRST -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH7_FIRST(f1,v1) ( \ - (R_DMA_CH7_FIRST__first__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH7_FIRST -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH7_FIRST. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH7_FIRST(f1,v1) ( \ - (R_DMA_CH7_FIRST__first__##f1##__VAL(R_DMA_CH7_FIRST_, first_, v1) << R_DMA_CH7_FIRST__first__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH7_FIRST_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH7_FIRST. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH7_FIRST_(f1_,v1) ( \ - (R_DMA_CH7_FIRST__first__##f1_##_VAL(R_DMA_CH7_FIRST_, first_, v1) << R_DMA_CH7_FIRST__first__BITNR) \ -) - -#endif - -/* - * R_DMA_CH7_HWSW - * - type: RW - * - addr: 0xb0000170 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH7_HWSW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH7_HWSW. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH7_HWSW. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH7_HWSW(f1,v1,f2,v2) ( \ - R_DMA_CH7_HWSW__WRITE(R_DMA_CH7_HWSW__ADDR, ( \ - REG_VAL__R_DMA_CH7_HWSW_(f1##_,v1,f2##_,v2) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH7_HWSW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH7_HWSW(f1,v1,f2,v2) ( \ - (R_DMA_CH7_HWSW__hw__##f1##__MASK & REG__##v1) | \ - (R_DMA_CH7_HWSW__sw__##f2##__MASK & REG__##v2) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH7_HWSW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH7_HWSW. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH7_HWSW(f1,v1,f2,v2) ( \ - (R_DMA_CH7_HWSW__hw__##f1##__VAL(R_DMA_CH7_HWSW_, hw_, v1) << R_DMA_CH7_HWSW__hw__BITNR) | \ - (R_DMA_CH7_HWSW__sw__##f2##__VAL(R_DMA_CH7_HWSW_, sw_, v2) << R_DMA_CH7_HWSW__sw__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH7_HWSW_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH7_HWSW. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH7_HWSW_(f1_,v1,f2_,v2) ( \ - (R_DMA_CH7_HWSW__hw__##f1_##_VAL(R_DMA_CH7_HWSW_, hw_, v1) << R_DMA_CH7_HWSW__hw__BITNR) | \ - (R_DMA_CH7_HWSW__sw__##f2_##_VAL(R_DMA_CH7_HWSW_, sw_, v2) << R_DMA_CH7_HWSW__sw__BITNR) \ -) - -#endif - -/* - * R_DMA_CH7_NEXT - * - type: RW - * - addr: 0xb0000174 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH7_NEXT -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH7_NEXT. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH7_NEXT. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH7_NEXT(f1,v1) ( \ - R_DMA_CH7_NEXT__WRITE(R_DMA_CH7_NEXT__ADDR, ( \ - REG_VAL__R_DMA_CH7_NEXT_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH7_NEXT -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH7_NEXT(f1,v1) ( \ - (R_DMA_CH7_NEXT__next__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH7_NEXT -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH7_NEXT. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH7_NEXT(f1,v1) ( \ - (R_DMA_CH7_NEXT__next__##f1##__VAL(R_DMA_CH7_NEXT_, next_, v1) << R_DMA_CH7_NEXT__next__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH7_NEXT_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH7_NEXT. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH7_NEXT_(f1_,v1) ( \ - (R_DMA_CH7_NEXT__next__##f1_##_VAL(R_DMA_CH7_NEXT_, next_, v1) << R_DMA_CH7_NEXT__next__BITNR) \ -) - -#endif - -/* - * R_DMA_CH7_STATUS - * - type: RO - * - addr: 0xb00001ee - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH7_STATUS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH7_STATUS(f1,v1) ( \ - (R_DMA_CH7_STATUS__avail__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH7_STATUS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH7_STATUS. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH7_STATUS(f1,v1) ( \ - (R_DMA_CH7_STATUS__avail__##f1##__VAL(R_DMA_CH7_STATUS_, avail_, v1) << R_DMA_CH7_STATUS__avail__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH7_STATUS_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH7_STATUS. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH7_STATUS_(f1_,v1) ( \ - (R_DMA_CH7_STATUS__avail__##f1_##_VAL(R_DMA_CH7_STATUS_, avail_, v1) << R_DMA_CH7_STATUS__avail__BITNR) \ -) - -#endif - -/* - * R_DMA_CH8_BUF - * - type: RW - * - addr: 0xb0000188 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH8_BUF -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH8_BUF. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH8_BUF. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH8_BUF(f1,v1) ( \ - R_DMA_CH8_BUF__WRITE(R_DMA_CH8_BUF__ADDR, ( \ - REG_VAL__R_DMA_CH8_BUF_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH8_BUF -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH8_BUF(f1,v1) ( \ - (R_DMA_CH8_BUF__buf__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH8_BUF -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH8_BUF. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH8_BUF(f1,v1) ( \ - (R_DMA_CH8_BUF__buf__##f1##__VAL(R_DMA_CH8_BUF_, buf_, v1) << R_DMA_CH8_BUF__buf__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH8_BUF_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH8_BUF. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH8_BUF_(f1_,v1) ( \ - (R_DMA_CH8_BUF__buf__##f1_##_VAL(R_DMA_CH8_BUF_, buf_, v1) << R_DMA_CH8_BUF__buf__BITNR) \ -) - -#endif - -/* - * R_DMA_CH8_CLR_INTR - * - type: WO - * - addr: 0xb00001f1 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH8_CLR_INTR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH8_CLR_INTR. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH8_CLR_INTR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH8_CLR_INTR(f1,v1,f2,v2) ( \ - *R_DMA_CH8_CLR_INTR__SADDR = ( \ - REG_INITIATED(R_DMA_CH8_CLR_INTR_) \ - REG_VAL__R_DMA_CH8_CLR_INTR_(f1##_,v1,f2##_,v2) \ - ), \ - R_DMA_CH8_CLR_INTR__WRITE(R_DMA_CH8_CLR_INTR__ADDR, *R_DMA_CH8_CLR_INTR__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH8_CLR_INTR__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH8_CLR_INTR. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_DMA_CH8_CLR_INTR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH8_CLR_INTR__SHADOW(f1,v1,f2,v2) ( \ - *R_DMA_CH8_CLR_INTR__SADDR = ( \ - REG_INITIATED(R_DMA_CH8_CLR_INTR_) \ - REG_VAL__R_DMA_CH8_CLR_INTR_(f1##_,v1,f2##_,v2) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH8_CLR_INTR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH8_CLR_INTR(f1,v1,f2,v2) ( \ - (R_DMA_CH8_CLR_INTR__clr_eop__##f1##__MASK & REG__##v1) | \ - (R_DMA_CH8_CLR_INTR__clr_descr__##f2##__MASK & REG__##v2) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH8_CLR_INTR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH8_CLR_INTR. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH8_CLR_INTR(f1,v1,f2,v2) ( \ - (R_DMA_CH8_CLR_INTR__clr_eop__##f1##__VAL(R_DMA_CH8_CLR_INTR_, clr_eop_, v1) << R_DMA_CH8_CLR_INTR__clr_eop__BITNR) | \ - (R_DMA_CH8_CLR_INTR__clr_descr__##f2##__VAL(R_DMA_CH8_CLR_INTR_, clr_descr_, v2) << R_DMA_CH8_CLR_INTR__clr_descr__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH8_CLR_INTR_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH8_CLR_INTR. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH8_CLR_INTR_(f1_,v1,f2_,v2) ( \ - (R_DMA_CH8_CLR_INTR__clr_eop__##f1_##_VAL(R_DMA_CH8_CLR_INTR_, clr_eop_, v1) << R_DMA_CH8_CLR_INTR__clr_eop__BITNR) | \ - (R_DMA_CH8_CLR_INTR__clr_descr__##f2_##_VAL(R_DMA_CH8_CLR_INTR_, clr_descr_, v2) << R_DMA_CH8_CLR_INTR__clr_descr__BITNR) \ -) - -#endif - -/* - * R_DMA_CH8_CMD - * - type: RW - * - addr: 0xb00001f0 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH8_CMD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH8_CMD. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH8_CMD. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH8_CMD(f1,v1) ( \ - R_DMA_CH8_CMD__WRITE(R_DMA_CH8_CMD__ADDR, ( \ - REG_VAL__R_DMA_CH8_CMD_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH8_CMD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH8_CMD(f1,v1) ( \ - (R_DMA_CH8_CMD__cmd__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH8_CMD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH8_CMD. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH8_CMD(f1,v1) ( \ - (R_DMA_CH8_CMD__cmd__##f1##__VAL(R_DMA_CH8_CMD_, cmd_, v1) << R_DMA_CH8_CMD__cmd__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH8_CMD_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH8_CMD. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH8_CMD_(f1_,v1) ( \ - (R_DMA_CH8_CMD__cmd__##f1_##_VAL(R_DMA_CH8_CMD_, cmd_, v1) << R_DMA_CH8_CMD__cmd__BITNR) \ -) - -#endif - -/* - * R_DMA_CH8_DESCR - * - type: RW - * - addr: 0xb000018c - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH8_DESCR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH8_DESCR. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH8_DESCR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH8_DESCR(f1,v1) ( \ - R_DMA_CH8_DESCR__WRITE(R_DMA_CH8_DESCR__ADDR, ( \ - REG_VAL__R_DMA_CH8_DESCR_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH8_DESCR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH8_DESCR(f1,v1) ( \ - (R_DMA_CH8_DESCR__descr__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH8_DESCR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH8_DESCR. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH8_DESCR(f1,v1) ( \ - (R_DMA_CH8_DESCR__descr__##f1##__VAL(R_DMA_CH8_DESCR_, descr_, v1) << R_DMA_CH8_DESCR__descr__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH8_DESCR_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH8_DESCR. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH8_DESCR_(f1_,v1) ( \ - (R_DMA_CH8_DESCR__descr__##f1_##_VAL(R_DMA_CH8_DESCR_, descr_, v1) << R_DMA_CH8_DESCR__descr__BITNR) \ -) - -#endif - -/* - * R_DMA_CH8_FIRST - * - type: RW - * - addr: 0xb00001c0 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH8_FIRST -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH8_FIRST. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH8_FIRST. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH8_FIRST(f1,v1) ( \ - R_DMA_CH8_FIRST__WRITE(R_DMA_CH8_FIRST__ADDR, ( \ - REG_VAL__R_DMA_CH8_FIRST_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH8_FIRST -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH8_FIRST(f1,v1) ( \ - (R_DMA_CH8_FIRST__first__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH8_FIRST -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH8_FIRST. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH8_FIRST(f1,v1) ( \ - (R_DMA_CH8_FIRST__first__##f1##__VAL(R_DMA_CH8_FIRST_, first_, v1) << R_DMA_CH8_FIRST__first__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH8_FIRST_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH8_FIRST. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH8_FIRST_(f1_,v1) ( \ - (R_DMA_CH8_FIRST__first__##f1_##_VAL(R_DMA_CH8_FIRST_, first_, v1) << R_DMA_CH8_FIRST__first__BITNR) \ -) - -#endif - -/* - * R_DMA_CH8_HWSW - * - type: RW - * - addr: 0xb0000180 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH8_HWSW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH8_HWSW. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH8_HWSW. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH8_HWSW(f1,v1,f2,v2) ( \ - R_DMA_CH8_HWSW__WRITE(R_DMA_CH8_HWSW__ADDR, ( \ - REG_VAL__R_DMA_CH8_HWSW_(f1##_,v1,f2##_,v2) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH8_HWSW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH8_HWSW(f1,v1,f2,v2) ( \ - (R_DMA_CH8_HWSW__hw__##f1##__MASK & REG__##v1) | \ - (R_DMA_CH8_HWSW__sw__##f2##__MASK & REG__##v2) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH8_HWSW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH8_HWSW. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH8_HWSW(f1,v1,f2,v2) ( \ - (R_DMA_CH8_HWSW__hw__##f1##__VAL(R_DMA_CH8_HWSW_, hw_, v1) << R_DMA_CH8_HWSW__hw__BITNR) | \ - (R_DMA_CH8_HWSW__sw__##f2##__VAL(R_DMA_CH8_HWSW_, sw_, v2) << R_DMA_CH8_HWSW__sw__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH8_HWSW_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH8_HWSW. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH8_HWSW_(f1_,v1,f2_,v2) ( \ - (R_DMA_CH8_HWSW__hw__##f1_##_VAL(R_DMA_CH8_HWSW_, hw_, v1) << R_DMA_CH8_HWSW__hw__BITNR) | \ - (R_DMA_CH8_HWSW__sw__##f2_##_VAL(R_DMA_CH8_HWSW_, sw_, v2) << R_DMA_CH8_HWSW__sw__BITNR) \ -) - -#endif - -/* - * R_DMA_CH8_NEP - * - type: RW - * - addr: 0xb00001c0 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH8_NEP -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH8_NEP. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH8_NEP. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH8_NEP(f1,v1) ( \ - R_DMA_CH8_NEP__WRITE(R_DMA_CH8_NEP__ADDR, ( \ - REG_VAL__R_DMA_CH8_NEP_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH8_NEP -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH8_NEP(f1,v1) ( \ - (R_DMA_CH8_NEP__nep__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH8_NEP -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH8_NEP. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH8_NEP(f1,v1) ( \ - (R_DMA_CH8_NEP__nep__##f1##__VAL(R_DMA_CH8_NEP_, nep_, v1) << R_DMA_CH8_NEP__nep__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH8_NEP_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH8_NEP. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH8_NEP_(f1_,v1) ( \ - (R_DMA_CH8_NEP__nep__##f1_##_VAL(R_DMA_CH8_NEP_, nep_, v1) << R_DMA_CH8_NEP__nep__BITNR) \ -) - -#endif - -/* - * R_DMA_CH8_NEXT - * - type: RW - * - addr: 0xb0000184 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH8_NEXT -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH8_NEXT. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH8_NEXT. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH8_NEXT(f1,v1) ( \ - R_DMA_CH8_NEXT__WRITE(R_DMA_CH8_NEXT__ADDR, ( \ - REG_VAL__R_DMA_CH8_NEXT_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH8_NEXT -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH8_NEXT(f1,v1) ( \ - (R_DMA_CH8_NEXT__next__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH8_NEXT -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH8_NEXT. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH8_NEXT(f1,v1) ( \ - (R_DMA_CH8_NEXT__next__##f1##__VAL(R_DMA_CH8_NEXT_, next_, v1) << R_DMA_CH8_NEXT__next__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH8_NEXT_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH8_NEXT. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH8_NEXT_(f1_,v1) ( \ - (R_DMA_CH8_NEXT__next__##f1_##_VAL(R_DMA_CH8_NEXT_, next_, v1) << R_DMA_CH8_NEXT__next__BITNR) \ -) - -#endif - -/* - * R_DMA_CH8_STATUS - * - type: RO - * - addr: 0xb00001f2 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH8_STATUS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH8_STATUS(f1,v1) ( \ - (R_DMA_CH8_STATUS__avail__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH8_STATUS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH8_STATUS. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH8_STATUS(f1,v1) ( \ - (R_DMA_CH8_STATUS__avail__##f1##__VAL(R_DMA_CH8_STATUS_, avail_, v1) << R_DMA_CH8_STATUS__avail__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH8_STATUS_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH8_STATUS. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH8_STATUS_(f1_,v1) ( \ - (R_DMA_CH8_STATUS__avail__##f1_##_VAL(R_DMA_CH8_STATUS_, avail_, v1) << R_DMA_CH8_STATUS__avail__BITNR) \ -) - -#endif - -/* - * R_DMA_CH8_SUB - * - type: RW - * - addr: 0xb000018c - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH8_SUB -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH8_SUB. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH8_SUB. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH8_SUB(f1,v1) ( \ - R_DMA_CH8_SUB__WRITE(R_DMA_CH8_SUB__ADDR, ( \ - REG_VAL__R_DMA_CH8_SUB_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH8_SUB -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH8_SUB(f1,v1) ( \ - (R_DMA_CH8_SUB__sub__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH8_SUB -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH8_SUB. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH8_SUB(f1,v1) ( \ - (R_DMA_CH8_SUB__sub__##f1##__VAL(R_DMA_CH8_SUB_, sub_, v1) << R_DMA_CH8_SUB__sub__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH8_SUB_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH8_SUB. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH8_SUB_(f1_,v1) ( \ - (R_DMA_CH8_SUB__sub__##f1_##_VAL(R_DMA_CH8_SUB_, sub_, v1) << R_DMA_CH8_SUB__sub__BITNR) \ -) - -#endif - -/* - * R_DMA_CH8_SUB0_CLR_INTR - * - type: WO - * - addr: 0xb00001e3 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH8_SUB0_CLR_INTR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH8_SUB0_CLR_INTR. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH8_SUB0_CLR_INTR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH8_SUB0_CLR_INTR(f1,v1) ( \ - *R_DMA_CH8_SUB0_CLR_INTR__SADDR = ( \ - REG_INITIATED(R_DMA_CH8_SUB0_CLR_INTR_) \ - REG_VAL__R_DMA_CH8_SUB0_CLR_INTR_(f1##_,v1) \ - ), \ - R_DMA_CH8_SUB0_CLR_INTR__WRITE(R_DMA_CH8_SUB0_CLR_INTR__ADDR, *R_DMA_CH8_SUB0_CLR_INTR__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH8_SUB0_CLR_INTR__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH8_SUB0_CLR_INTR. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_DMA_CH8_SUB0_CLR_INTR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH8_SUB0_CLR_INTR__SHADOW(f1,v1) ( \ - *R_DMA_CH8_SUB0_CLR_INTR__SADDR = ( \ - REG_INITIATED(R_DMA_CH8_SUB0_CLR_INTR_) \ - REG_VAL__R_DMA_CH8_SUB0_CLR_INTR_(f1##_,v1) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH8_SUB0_CLR_INTR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH8_SUB0_CLR_INTR(f1,v1) ( \ - (R_DMA_CH8_SUB0_CLR_INTR__clr_descr__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH8_SUB0_CLR_INTR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH8_SUB0_CLR_INTR. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH8_SUB0_CLR_INTR(f1,v1) ( \ - (R_DMA_CH8_SUB0_CLR_INTR__clr_descr__##f1##__VAL(R_DMA_CH8_SUB0_CLR_INTR_, clr_descr_, v1) << R_DMA_CH8_SUB0_CLR_INTR__clr_descr__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH8_SUB0_CLR_INTR_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH8_SUB0_CLR_INTR. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH8_SUB0_CLR_INTR_(f1_,v1) ( \ - (R_DMA_CH8_SUB0_CLR_INTR__clr_descr__##f1_##_VAL(R_DMA_CH8_SUB0_CLR_INTR_, clr_descr_, v1) << R_DMA_CH8_SUB0_CLR_INTR__clr_descr__BITNR) \ -) - -#endif - -/* - * R_DMA_CH8_SUB0_CMD - * - type: RW - * - addr: 0xb00001d3 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH8_SUB0_CMD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH8_SUB0_CMD. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH8_SUB0_CMD. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH8_SUB0_CMD(f1,v1) ( \ - R_DMA_CH8_SUB0_CMD__WRITE(R_DMA_CH8_SUB0_CMD__ADDR, ( \ - REG_VAL__R_DMA_CH8_SUB0_CMD_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH8_SUB0_CMD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH8_SUB0_CMD(f1,v1) ( \ - (R_DMA_CH8_SUB0_CMD__cmd__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH8_SUB0_CMD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH8_SUB0_CMD. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH8_SUB0_CMD(f1,v1) ( \ - (R_DMA_CH8_SUB0_CMD__cmd__##f1##__VAL(R_DMA_CH8_SUB0_CMD_, cmd_, v1) << R_DMA_CH8_SUB0_CMD__cmd__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH8_SUB0_CMD_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH8_SUB0_CMD. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH8_SUB0_CMD_(f1_,v1) ( \ - (R_DMA_CH8_SUB0_CMD__cmd__##f1_##_VAL(R_DMA_CH8_SUB0_CMD_, cmd_, v1) << R_DMA_CH8_SUB0_CMD__cmd__BITNR) \ -) - -#endif - -/* - * R_DMA_CH8_SUB0_EP - * - type: RW - * - addr: 0xb00001c8 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH8_SUB0_EP -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH8_SUB0_EP. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH8_SUB0_EP. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH8_SUB0_EP(f1,v1) ( \ - R_DMA_CH8_SUB0_EP__WRITE(R_DMA_CH8_SUB0_EP__ADDR, ( \ - REG_VAL__R_DMA_CH8_SUB0_EP_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH8_SUB0_EP -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH8_SUB0_EP(f1,v1) ( \ - (R_DMA_CH8_SUB0_EP__ep__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH8_SUB0_EP -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH8_SUB0_EP. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH8_SUB0_EP(f1,v1) ( \ - (R_DMA_CH8_SUB0_EP__ep__##f1##__VAL(R_DMA_CH8_SUB0_EP_, ep_, v1) << R_DMA_CH8_SUB0_EP__ep__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH8_SUB0_EP_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH8_SUB0_EP. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH8_SUB0_EP_(f1_,v1) ( \ - (R_DMA_CH8_SUB0_EP__ep__##f1_##_VAL(R_DMA_CH8_SUB0_EP_, ep_, v1) << R_DMA_CH8_SUB0_EP__ep__BITNR) \ -) - -#endif - -/* - * R_DMA_CH8_SUB1_CLR_INTR - * - type: WO - * - addr: 0xb00001e7 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH8_SUB1_CLR_INTR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH8_SUB1_CLR_INTR. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH8_SUB1_CLR_INTR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH8_SUB1_CLR_INTR(f1,v1) ( \ - *R_DMA_CH8_SUB1_CLR_INTR__SADDR = ( \ - REG_INITIATED(R_DMA_CH8_SUB1_CLR_INTR_) \ - REG_VAL__R_DMA_CH8_SUB1_CLR_INTR_(f1##_,v1) \ - ), \ - R_DMA_CH8_SUB1_CLR_INTR__WRITE(R_DMA_CH8_SUB1_CLR_INTR__ADDR, *R_DMA_CH8_SUB1_CLR_INTR__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH8_SUB1_CLR_INTR__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH8_SUB1_CLR_INTR. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_DMA_CH8_SUB1_CLR_INTR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH8_SUB1_CLR_INTR__SHADOW(f1,v1) ( \ - *R_DMA_CH8_SUB1_CLR_INTR__SADDR = ( \ - REG_INITIATED(R_DMA_CH8_SUB1_CLR_INTR_) \ - REG_VAL__R_DMA_CH8_SUB1_CLR_INTR_(f1##_,v1) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH8_SUB1_CLR_INTR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH8_SUB1_CLR_INTR(f1,v1) ( \ - (R_DMA_CH8_SUB1_CLR_INTR__clr_descr__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH8_SUB1_CLR_INTR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH8_SUB1_CLR_INTR. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH8_SUB1_CLR_INTR(f1,v1) ( \ - (R_DMA_CH8_SUB1_CLR_INTR__clr_descr__##f1##__VAL(R_DMA_CH8_SUB1_CLR_INTR_, clr_descr_, v1) << R_DMA_CH8_SUB1_CLR_INTR__clr_descr__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH8_SUB1_CLR_INTR_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH8_SUB1_CLR_INTR. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH8_SUB1_CLR_INTR_(f1_,v1) ( \ - (R_DMA_CH8_SUB1_CLR_INTR__clr_descr__##f1_##_VAL(R_DMA_CH8_SUB1_CLR_INTR_, clr_descr_, v1) << R_DMA_CH8_SUB1_CLR_INTR__clr_descr__BITNR) \ -) - -#endif - -/* - * R_DMA_CH8_SUB1_CMD - * - type: RW - * - addr: 0xb00001d7 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH8_SUB1_CMD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH8_SUB1_CMD. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH8_SUB1_CMD. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH8_SUB1_CMD(f1,v1) ( \ - R_DMA_CH8_SUB1_CMD__WRITE(R_DMA_CH8_SUB1_CMD__ADDR, ( \ - REG_VAL__R_DMA_CH8_SUB1_CMD_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH8_SUB1_CMD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH8_SUB1_CMD(f1,v1) ( \ - (R_DMA_CH8_SUB1_CMD__cmd__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH8_SUB1_CMD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH8_SUB1_CMD. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH8_SUB1_CMD(f1,v1) ( \ - (R_DMA_CH8_SUB1_CMD__cmd__##f1##__VAL(R_DMA_CH8_SUB1_CMD_, cmd_, v1) << R_DMA_CH8_SUB1_CMD__cmd__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH8_SUB1_CMD_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH8_SUB1_CMD. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH8_SUB1_CMD_(f1_,v1) ( \ - (R_DMA_CH8_SUB1_CMD__cmd__##f1_##_VAL(R_DMA_CH8_SUB1_CMD_, cmd_, v1) << R_DMA_CH8_SUB1_CMD__cmd__BITNR) \ -) - -#endif - -/* - * R_DMA_CH8_SUB1_EP - * - type: RW - * - addr: 0xb00001cc - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH8_SUB1_EP -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH8_SUB1_EP. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH8_SUB1_EP. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH8_SUB1_EP(f1,v1) ( \ - R_DMA_CH8_SUB1_EP__WRITE(R_DMA_CH8_SUB1_EP__ADDR, ( \ - REG_VAL__R_DMA_CH8_SUB1_EP_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH8_SUB1_EP -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH8_SUB1_EP(f1,v1) ( \ - (R_DMA_CH8_SUB1_EP__ep__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH8_SUB1_EP -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH8_SUB1_EP. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH8_SUB1_EP(f1,v1) ( \ - (R_DMA_CH8_SUB1_EP__ep__##f1##__VAL(R_DMA_CH8_SUB1_EP_, ep_, v1) << R_DMA_CH8_SUB1_EP__ep__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH8_SUB1_EP_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH8_SUB1_EP. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH8_SUB1_EP_(f1_,v1) ( \ - (R_DMA_CH8_SUB1_EP__ep__##f1_##_VAL(R_DMA_CH8_SUB1_EP_, ep_, v1) << R_DMA_CH8_SUB1_EP__ep__BITNR) \ -) - -#endif - -/* - * R_DMA_CH8_SUB2_CLR_INTR - * - type: WO - * - addr: 0xb00001eb - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH8_SUB2_CLR_INTR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH8_SUB2_CLR_INTR. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH8_SUB2_CLR_INTR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH8_SUB2_CLR_INTR(f1,v1) ( \ - *R_DMA_CH8_SUB2_CLR_INTR__SADDR = ( \ - REG_INITIATED(R_DMA_CH8_SUB2_CLR_INTR_) \ - REG_VAL__R_DMA_CH8_SUB2_CLR_INTR_(f1##_,v1) \ - ), \ - R_DMA_CH8_SUB2_CLR_INTR__WRITE(R_DMA_CH8_SUB2_CLR_INTR__ADDR, *R_DMA_CH8_SUB2_CLR_INTR__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH8_SUB2_CLR_INTR__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH8_SUB2_CLR_INTR. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_DMA_CH8_SUB2_CLR_INTR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH8_SUB2_CLR_INTR__SHADOW(f1,v1) ( \ - *R_DMA_CH8_SUB2_CLR_INTR__SADDR = ( \ - REG_INITIATED(R_DMA_CH8_SUB2_CLR_INTR_) \ - REG_VAL__R_DMA_CH8_SUB2_CLR_INTR_(f1##_,v1) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH8_SUB2_CLR_INTR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH8_SUB2_CLR_INTR(f1,v1) ( \ - (R_DMA_CH8_SUB2_CLR_INTR__clr_descr__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH8_SUB2_CLR_INTR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH8_SUB2_CLR_INTR. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH8_SUB2_CLR_INTR(f1,v1) ( \ - (R_DMA_CH8_SUB2_CLR_INTR__clr_descr__##f1##__VAL(R_DMA_CH8_SUB2_CLR_INTR_, clr_descr_, v1) << R_DMA_CH8_SUB2_CLR_INTR__clr_descr__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH8_SUB2_CLR_INTR_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH8_SUB2_CLR_INTR. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH8_SUB2_CLR_INTR_(f1_,v1) ( \ - (R_DMA_CH8_SUB2_CLR_INTR__clr_descr__##f1_##_VAL(R_DMA_CH8_SUB2_CLR_INTR_, clr_descr_, v1) << R_DMA_CH8_SUB2_CLR_INTR__clr_descr__BITNR) \ -) - -#endif - -/* - * R_DMA_CH8_SUB2_CMD - * - type: RW - * - addr: 0xb00001db - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH8_SUB2_CMD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH8_SUB2_CMD. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH8_SUB2_CMD. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH8_SUB2_CMD(f1,v1) ( \ - R_DMA_CH8_SUB2_CMD__WRITE(R_DMA_CH8_SUB2_CMD__ADDR, ( \ - REG_VAL__R_DMA_CH8_SUB2_CMD_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH8_SUB2_CMD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH8_SUB2_CMD(f1,v1) ( \ - (R_DMA_CH8_SUB2_CMD__cmd__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH8_SUB2_CMD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH8_SUB2_CMD. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH8_SUB2_CMD(f1,v1) ( \ - (R_DMA_CH8_SUB2_CMD__cmd__##f1##__VAL(R_DMA_CH8_SUB2_CMD_, cmd_, v1) << R_DMA_CH8_SUB2_CMD__cmd__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH8_SUB2_CMD_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH8_SUB2_CMD. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH8_SUB2_CMD_(f1_,v1) ( \ - (R_DMA_CH8_SUB2_CMD__cmd__##f1_##_VAL(R_DMA_CH8_SUB2_CMD_, cmd_, v1) << R_DMA_CH8_SUB2_CMD__cmd__BITNR) \ -) - -#endif - -/* - * R_DMA_CH8_SUB2_EP - * - type: RW - * - addr: 0xb00001f8 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH8_SUB2_EP -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH8_SUB2_EP. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH8_SUB2_EP. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH8_SUB2_EP(f1,v1) ( \ - R_DMA_CH8_SUB2_EP__WRITE(R_DMA_CH8_SUB2_EP__ADDR, ( \ - REG_VAL__R_DMA_CH8_SUB2_EP_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH8_SUB2_EP -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH8_SUB2_EP(f1,v1) ( \ - (R_DMA_CH8_SUB2_EP__ep__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH8_SUB2_EP -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH8_SUB2_EP. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH8_SUB2_EP(f1,v1) ( \ - (R_DMA_CH8_SUB2_EP__ep__##f1##__VAL(R_DMA_CH8_SUB2_EP_, ep_, v1) << R_DMA_CH8_SUB2_EP__ep__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH8_SUB2_EP_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH8_SUB2_EP. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH8_SUB2_EP_(f1_,v1) ( \ - (R_DMA_CH8_SUB2_EP__ep__##f1_##_VAL(R_DMA_CH8_SUB2_EP_, ep_, v1) << R_DMA_CH8_SUB2_EP__ep__BITNR) \ -) - -#endif - -/* - * R_DMA_CH8_SUB3_CLR_INTR - * - type: WO - * - addr: 0xb00001ef - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH8_SUB3_CLR_INTR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH8_SUB3_CLR_INTR. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH8_SUB3_CLR_INTR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH8_SUB3_CLR_INTR(f1,v1) ( \ - *R_DMA_CH8_SUB3_CLR_INTR__SADDR = ( \ - REG_INITIATED(R_DMA_CH8_SUB3_CLR_INTR_) \ - REG_VAL__R_DMA_CH8_SUB3_CLR_INTR_(f1##_,v1) \ - ), \ - R_DMA_CH8_SUB3_CLR_INTR__WRITE(R_DMA_CH8_SUB3_CLR_INTR__ADDR, *R_DMA_CH8_SUB3_CLR_INTR__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH8_SUB3_CLR_INTR__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH8_SUB3_CLR_INTR. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_DMA_CH8_SUB3_CLR_INTR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH8_SUB3_CLR_INTR__SHADOW(f1,v1) ( \ - *R_DMA_CH8_SUB3_CLR_INTR__SADDR = ( \ - REG_INITIATED(R_DMA_CH8_SUB3_CLR_INTR_) \ - REG_VAL__R_DMA_CH8_SUB3_CLR_INTR_(f1##_,v1) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH8_SUB3_CLR_INTR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH8_SUB3_CLR_INTR(f1,v1) ( \ - (R_DMA_CH8_SUB3_CLR_INTR__clr_descr__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH8_SUB3_CLR_INTR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH8_SUB3_CLR_INTR. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH8_SUB3_CLR_INTR(f1,v1) ( \ - (R_DMA_CH8_SUB3_CLR_INTR__clr_descr__##f1##__VAL(R_DMA_CH8_SUB3_CLR_INTR_, clr_descr_, v1) << R_DMA_CH8_SUB3_CLR_INTR__clr_descr__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH8_SUB3_CLR_INTR_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH8_SUB3_CLR_INTR. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH8_SUB3_CLR_INTR_(f1_,v1) ( \ - (R_DMA_CH8_SUB3_CLR_INTR__clr_descr__##f1_##_VAL(R_DMA_CH8_SUB3_CLR_INTR_, clr_descr_, v1) << R_DMA_CH8_SUB3_CLR_INTR__clr_descr__BITNR) \ -) - -#endif - -/* - * R_DMA_CH8_SUB3_CMD - * - type: RW - * - addr: 0xb00001df - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH8_SUB3_CMD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH8_SUB3_CMD. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH8_SUB3_CMD. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH8_SUB3_CMD(f1,v1) ( \ - R_DMA_CH8_SUB3_CMD__WRITE(R_DMA_CH8_SUB3_CMD__ADDR, ( \ - REG_VAL__R_DMA_CH8_SUB3_CMD_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH8_SUB3_CMD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH8_SUB3_CMD(f1,v1) ( \ - (R_DMA_CH8_SUB3_CMD__cmd__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH8_SUB3_CMD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH8_SUB3_CMD. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH8_SUB3_CMD(f1,v1) ( \ - (R_DMA_CH8_SUB3_CMD__cmd__##f1##__VAL(R_DMA_CH8_SUB3_CMD_, cmd_, v1) << R_DMA_CH8_SUB3_CMD__cmd__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH8_SUB3_CMD_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH8_SUB3_CMD. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH8_SUB3_CMD_(f1_,v1) ( \ - (R_DMA_CH8_SUB3_CMD__cmd__##f1_##_VAL(R_DMA_CH8_SUB3_CMD_, cmd_, v1) << R_DMA_CH8_SUB3_CMD__cmd__BITNR) \ -) - -#endif - -/* - * R_DMA_CH8_SUB3_EP - * - type: RW - * - addr: 0xb00001fc - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH8_SUB3_EP -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH8_SUB3_EP. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH8_SUB3_EP. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH8_SUB3_EP(f1,v1) ( \ - R_DMA_CH8_SUB3_EP__WRITE(R_DMA_CH8_SUB3_EP__ADDR, ( \ - REG_VAL__R_DMA_CH8_SUB3_EP_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH8_SUB3_EP -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH8_SUB3_EP(f1,v1) ( \ - (R_DMA_CH8_SUB3_EP__ep__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH8_SUB3_EP -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH8_SUB3_EP. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH8_SUB3_EP(f1,v1) ( \ - (R_DMA_CH8_SUB3_EP__ep__##f1##__VAL(R_DMA_CH8_SUB3_EP_, ep_, v1) << R_DMA_CH8_SUB3_EP__ep__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH8_SUB3_EP_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH8_SUB3_EP. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH8_SUB3_EP_(f1_,v1) ( \ - (R_DMA_CH8_SUB3_EP__ep__##f1_##_VAL(R_DMA_CH8_SUB3_EP_, ep_, v1) << R_DMA_CH8_SUB3_EP__ep__BITNR) \ -) - -#endif - -/* - * R_DMA_CH9_BUF - * - type: RW - * - addr: 0xb0000198 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH9_BUF -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH9_BUF. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH9_BUF. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH9_BUF(f1,v1) ( \ - R_DMA_CH9_BUF__WRITE(R_DMA_CH9_BUF__ADDR, ( \ - REG_VAL__R_DMA_CH9_BUF_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH9_BUF -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH9_BUF(f1,v1) ( \ - (R_DMA_CH9_BUF__buf__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH9_BUF -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH9_BUF. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH9_BUF(f1,v1) ( \ - (R_DMA_CH9_BUF__buf__##f1##__VAL(R_DMA_CH9_BUF_, buf_, v1) << R_DMA_CH9_BUF__buf__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH9_BUF_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH9_BUF. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH9_BUF_(f1_,v1) ( \ - (R_DMA_CH9_BUF__buf__##f1_##_VAL(R_DMA_CH9_BUF_, buf_, v1) << R_DMA_CH9_BUF__buf__BITNR) \ -) - -#endif - -/* - * R_DMA_CH9_CLR_INTR - * - type: WO - * - addr: 0xb00001f5 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH9_CLR_INTR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH9_CLR_INTR. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH9_CLR_INTR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH9_CLR_INTR(f1,v1,f2,v2) ( \ - *R_DMA_CH9_CLR_INTR__SADDR = ( \ - REG_INITIATED(R_DMA_CH9_CLR_INTR_) \ - REG_VAL__R_DMA_CH9_CLR_INTR_(f1##_,v1,f2##_,v2) \ - ), \ - R_DMA_CH9_CLR_INTR__WRITE(R_DMA_CH9_CLR_INTR__ADDR, *R_DMA_CH9_CLR_INTR__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH9_CLR_INTR__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH9_CLR_INTR. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_DMA_CH9_CLR_INTR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH9_CLR_INTR__SHADOW(f1,v1,f2,v2) ( \ - *R_DMA_CH9_CLR_INTR__SADDR = ( \ - REG_INITIATED(R_DMA_CH9_CLR_INTR_) \ - REG_VAL__R_DMA_CH9_CLR_INTR_(f1##_,v1,f2##_,v2) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH9_CLR_INTR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH9_CLR_INTR(f1,v1,f2,v2) ( \ - (R_DMA_CH9_CLR_INTR__clr_eop__##f1##__MASK & REG__##v1) | \ - (R_DMA_CH9_CLR_INTR__clr_descr__##f2##__MASK & REG__##v2) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH9_CLR_INTR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH9_CLR_INTR. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH9_CLR_INTR(f1,v1,f2,v2) ( \ - (R_DMA_CH9_CLR_INTR__clr_eop__##f1##__VAL(R_DMA_CH9_CLR_INTR_, clr_eop_, v1) << R_DMA_CH9_CLR_INTR__clr_eop__BITNR) | \ - (R_DMA_CH9_CLR_INTR__clr_descr__##f2##__VAL(R_DMA_CH9_CLR_INTR_, clr_descr_, v2) << R_DMA_CH9_CLR_INTR__clr_descr__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH9_CLR_INTR_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH9_CLR_INTR. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH9_CLR_INTR_(f1_,v1,f2_,v2) ( \ - (R_DMA_CH9_CLR_INTR__clr_eop__##f1_##_VAL(R_DMA_CH9_CLR_INTR_, clr_eop_, v1) << R_DMA_CH9_CLR_INTR__clr_eop__BITNR) | \ - (R_DMA_CH9_CLR_INTR__clr_descr__##f2_##_VAL(R_DMA_CH9_CLR_INTR_, clr_descr_, v2) << R_DMA_CH9_CLR_INTR__clr_descr__BITNR) \ -) - -#endif - -/* - * R_DMA_CH9_CMD - * - type: RW - * - addr: 0xb00001f4 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH9_CMD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH9_CMD. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH9_CMD. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH9_CMD(f1,v1) ( \ - R_DMA_CH9_CMD__WRITE(R_DMA_CH9_CMD__ADDR, ( \ - REG_VAL__R_DMA_CH9_CMD_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH9_CMD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH9_CMD(f1,v1) ( \ - (R_DMA_CH9_CMD__cmd__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH9_CMD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH9_CMD. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH9_CMD(f1,v1) ( \ - (R_DMA_CH9_CMD__cmd__##f1##__VAL(R_DMA_CH9_CMD_, cmd_, v1) << R_DMA_CH9_CMD__cmd__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH9_CMD_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH9_CMD. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH9_CMD_(f1_,v1) ( \ - (R_DMA_CH9_CMD__cmd__##f1_##_VAL(R_DMA_CH9_CMD_, cmd_, v1) << R_DMA_CH9_CMD__cmd__BITNR) \ -) - -#endif - -/* - * R_DMA_CH9_DESCR - * - type: RW - * - addr: 0xb000019c - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH9_DESCR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH9_DESCR. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH9_DESCR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH9_DESCR(f1,v1) ( \ - R_DMA_CH9_DESCR__WRITE(R_DMA_CH9_DESCR__ADDR, ( \ - REG_VAL__R_DMA_CH9_DESCR_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH9_DESCR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH9_DESCR(f1,v1) ( \ - (R_DMA_CH9_DESCR__descr__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH9_DESCR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH9_DESCR. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH9_DESCR(f1,v1) ( \ - (R_DMA_CH9_DESCR__descr__##f1##__VAL(R_DMA_CH9_DESCR_, descr_, v1) << R_DMA_CH9_DESCR__descr__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH9_DESCR_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH9_DESCR. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH9_DESCR_(f1_,v1) ( \ - (R_DMA_CH9_DESCR__descr__##f1_##_VAL(R_DMA_CH9_DESCR_, descr_, v1) << R_DMA_CH9_DESCR__descr__BITNR) \ -) - -#endif - -/* - * R_DMA_CH9_FIRST - * - type: RW - * - addr: 0xb00001c4 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH9_FIRST -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH9_FIRST. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH9_FIRST. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH9_FIRST(f1,v1) ( \ - R_DMA_CH9_FIRST__WRITE(R_DMA_CH9_FIRST__ADDR, ( \ - REG_VAL__R_DMA_CH9_FIRST_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH9_FIRST -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH9_FIRST(f1,v1) ( \ - (R_DMA_CH9_FIRST__first__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH9_FIRST -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH9_FIRST. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH9_FIRST(f1,v1) ( \ - (R_DMA_CH9_FIRST__first__##f1##__VAL(R_DMA_CH9_FIRST_, first_, v1) << R_DMA_CH9_FIRST__first__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH9_FIRST_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH9_FIRST. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH9_FIRST_(f1_,v1) ( \ - (R_DMA_CH9_FIRST__first__##f1_##_VAL(R_DMA_CH9_FIRST_, first_, v1) << R_DMA_CH9_FIRST__first__BITNR) \ -) - -#endif - -/* - * R_DMA_CH9_HWSW - * - type: RW - * - addr: 0xb0000190 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH9_HWSW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH9_HWSW. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH9_HWSW. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH9_HWSW(f1,v1,f2,v2) ( \ - R_DMA_CH9_HWSW__WRITE(R_DMA_CH9_HWSW__ADDR, ( \ - REG_VAL__R_DMA_CH9_HWSW_(f1##_,v1,f2##_,v2) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH9_HWSW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH9_HWSW(f1,v1,f2,v2) ( \ - (R_DMA_CH9_HWSW__hw__##f1##__MASK & REG__##v1) | \ - (R_DMA_CH9_HWSW__sw__##f2##__MASK & REG__##v2) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH9_HWSW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH9_HWSW. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH9_HWSW(f1,v1,f2,v2) ( \ - (R_DMA_CH9_HWSW__hw__##f1##__VAL(R_DMA_CH9_HWSW_, hw_, v1) << R_DMA_CH9_HWSW__hw__BITNR) | \ - (R_DMA_CH9_HWSW__sw__##f2##__VAL(R_DMA_CH9_HWSW_, sw_, v2) << R_DMA_CH9_HWSW__sw__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH9_HWSW_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH9_HWSW. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH9_HWSW_(f1_,v1,f2_,v2) ( \ - (R_DMA_CH9_HWSW__hw__##f1_##_VAL(R_DMA_CH9_HWSW_, hw_, v1) << R_DMA_CH9_HWSW__hw__BITNR) | \ - (R_DMA_CH9_HWSW__sw__##f2_##_VAL(R_DMA_CH9_HWSW_, sw_, v2) << R_DMA_CH9_HWSW__sw__BITNR) \ -) - -#endif - -/* - * R_DMA_CH9_NEXT - * - type: RW - * - addr: 0xb0000194 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DMA_CH9_NEXT -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DMA_CH9_NEXT. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DMA_CH9_NEXT. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DMA_CH9_NEXT(f1,v1) ( \ - R_DMA_CH9_NEXT__WRITE(R_DMA_CH9_NEXT__ADDR, ( \ - REG_VAL__R_DMA_CH9_NEXT_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH9_NEXT -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH9_NEXT(f1,v1) ( \ - (R_DMA_CH9_NEXT__next__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH9_NEXT -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH9_NEXT. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH9_NEXT(f1,v1) ( \ - (R_DMA_CH9_NEXT__next__##f1##__VAL(R_DMA_CH9_NEXT_, next_, v1) << R_DMA_CH9_NEXT__next__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH9_NEXT_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH9_NEXT. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH9_NEXT_(f1_,v1) ( \ - (R_DMA_CH9_NEXT__next__##f1_##_VAL(R_DMA_CH9_NEXT_, next_, v1) << R_DMA_CH9_NEXT__next__BITNR) \ -) - -#endif - -/* - * R_DMA_CH9_STATUS - * - type: RO - * - addr: 0xb00001f6 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DMA_CH9_STATUS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DMA_CH9_STATUS(f1,v1) ( \ - (R_DMA_CH9_STATUS__avail__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH9_STATUS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH9_STATUS. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH9_STATUS(f1,v1) ( \ - (R_DMA_CH9_STATUS__avail__##f1##__VAL(R_DMA_CH9_STATUS_, avail_, v1) << R_DMA_CH9_STATUS__avail__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DMA_CH9_STATUS_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DMA_CH9_STATUS. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DMA_CH9_STATUS_(f1_,v1) ( \ - (R_DMA_CH9_STATUS__avail__##f1_##_VAL(R_DMA_CH9_STATUS_, avail_, v1) << R_DMA_CH9_STATUS__avail__BITNR) \ -) - -#endif - -/* - * R_DRAM_CONFIG - * - type: WO - * - addr: 0xb000000c - * - group: Bus interface configuration registers - */ - -#if USE_GROUP__Bus_interface_configuration_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DRAM_CONFIG -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DRAM_CONFIG. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DRAM_CONFIG. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DRAM_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12) ( \ - *R_DRAM_CONFIG__SADDR = ( \ - REG_INITIATED(R_DRAM_CONFIG_) \ - REG_VAL__R_DRAM_CONFIG_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12) \ - ), \ - R_DRAM_CONFIG__WRITE(R_DRAM_CONFIG__ADDR, *R_DRAM_CONFIG__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DRAM_CONFIG__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DRAM_CONFIG. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_DRAM_CONFIG. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DRAM_CONFIG__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12) ( \ - *R_DRAM_CONFIG__SADDR = ( \ - REG_INITIATED(R_DRAM_CONFIG_) \ - REG_VAL__R_DRAM_CONFIG_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DRAM_CONFIG -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DRAM_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12) ( \ - (R_DRAM_CONFIG__wmm1__##f1##__MASK & REG__##v1) | \ - (R_DRAM_CONFIG__wmm0__##f2##__MASK & REG__##v2) | \ - (R_DRAM_CONFIG__sh1__##f3##__MASK & REG__##v3) | \ - (R_DRAM_CONFIG__sh0__##f4##__MASK & REG__##v4) | \ - (R_DRAM_CONFIG__w__##f5##__MASK & REG__##v5) | \ - (R_DRAM_CONFIG__c__##f6##__MASK & REG__##v6) | \ - (R_DRAM_CONFIG__e__##f7##__MASK & REG__##v7) | \ - (R_DRAM_CONFIG__group_sel__##f8##__MASK & REG__##v8) | \ - (R_DRAM_CONFIG__ca1__##f9##__MASK & REG__##v9) | \ - (R_DRAM_CONFIG__bank23sel__##f10##__MASK & REG__##v10) | \ - (R_DRAM_CONFIG__ca0__##f11##__MASK & REG__##v11) | \ - (R_DRAM_CONFIG__bank01sel__##f12##__MASK & REG__##v12) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DRAM_CONFIG -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DRAM_CONFIG. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DRAM_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12) ( \ - (R_DRAM_CONFIG__wmm1__##f1##__VAL(R_DRAM_CONFIG_, wmm1_, v1) << R_DRAM_CONFIG__wmm1__BITNR) | \ - (R_DRAM_CONFIG__wmm0__##f2##__VAL(R_DRAM_CONFIG_, wmm0_, v2) << R_DRAM_CONFIG__wmm0__BITNR) | \ - (R_DRAM_CONFIG__sh1__##f3##__VAL(R_DRAM_CONFIG_, sh1_, v3) << R_DRAM_CONFIG__sh1__BITNR) | \ - (R_DRAM_CONFIG__sh0__##f4##__VAL(R_DRAM_CONFIG_, sh0_, v4) << R_DRAM_CONFIG__sh0__BITNR) | \ - (R_DRAM_CONFIG__w__##f5##__VAL(R_DRAM_CONFIG_, w_, v5) << R_DRAM_CONFIG__w__BITNR) | \ - (R_DRAM_CONFIG__c__##f6##__VAL(R_DRAM_CONFIG_, c_, v6) << R_DRAM_CONFIG__c__BITNR) | \ - (R_DRAM_CONFIG__e__##f7##__VAL(R_DRAM_CONFIG_, e_, v7) << R_DRAM_CONFIG__e__BITNR) | \ - (R_DRAM_CONFIG__group_sel__##f8##__VAL(R_DRAM_CONFIG_, group_sel_, v8) << R_DRAM_CONFIG__group_sel__BITNR) | \ - (R_DRAM_CONFIG__ca1__##f9##__VAL(R_DRAM_CONFIG_, ca1_, v9) << R_DRAM_CONFIG__ca1__BITNR) | \ - (R_DRAM_CONFIG__bank23sel__##f10##__VAL(R_DRAM_CONFIG_, bank23sel_, v10) << R_DRAM_CONFIG__bank23sel__BITNR) | \ - (R_DRAM_CONFIG__ca0__##f11##__VAL(R_DRAM_CONFIG_, ca0_, v11) << R_DRAM_CONFIG__ca0__BITNR) | \ - (R_DRAM_CONFIG__bank01sel__##f12##__VAL(R_DRAM_CONFIG_, bank01sel_, v12) << R_DRAM_CONFIG__bank01sel__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DRAM_CONFIG_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DRAM_CONFIG. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DRAM_CONFIG_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12) ( \ - (R_DRAM_CONFIG__wmm1__##f1_##_VAL(R_DRAM_CONFIG_, wmm1_, v1) << R_DRAM_CONFIG__wmm1__BITNR) | \ - (R_DRAM_CONFIG__wmm0__##f2_##_VAL(R_DRAM_CONFIG_, wmm0_, v2) << R_DRAM_CONFIG__wmm0__BITNR) | \ - (R_DRAM_CONFIG__sh1__##f3_##_VAL(R_DRAM_CONFIG_, sh1_, v3) << R_DRAM_CONFIG__sh1__BITNR) | \ - (R_DRAM_CONFIG__sh0__##f4_##_VAL(R_DRAM_CONFIG_, sh0_, v4) << R_DRAM_CONFIG__sh0__BITNR) | \ - (R_DRAM_CONFIG__w__##f5_##_VAL(R_DRAM_CONFIG_, w_, v5) << R_DRAM_CONFIG__w__BITNR) | \ - (R_DRAM_CONFIG__c__##f6_##_VAL(R_DRAM_CONFIG_, c_, v6) << R_DRAM_CONFIG__c__BITNR) | \ - (R_DRAM_CONFIG__e__##f7_##_VAL(R_DRAM_CONFIG_, e_, v7) << R_DRAM_CONFIG__e__BITNR) | \ - (R_DRAM_CONFIG__group_sel__##f8_##_VAL(R_DRAM_CONFIG_, group_sel_, v8) << R_DRAM_CONFIG__group_sel__BITNR) | \ - (R_DRAM_CONFIG__ca1__##f9_##_VAL(R_DRAM_CONFIG_, ca1_, v9) << R_DRAM_CONFIG__ca1__BITNR) | \ - (R_DRAM_CONFIG__bank23sel__##f10_##_VAL(R_DRAM_CONFIG_, bank23sel_, v10) << R_DRAM_CONFIG__bank23sel__BITNR) | \ - (R_DRAM_CONFIG__ca0__##f11_##_VAL(R_DRAM_CONFIG_, ca0_, v11) << R_DRAM_CONFIG__ca0__BITNR) | \ - (R_DRAM_CONFIG__bank01sel__##f12_##_VAL(R_DRAM_CONFIG_, bank01sel_, v12) << R_DRAM_CONFIG__bank01sel__BITNR) \ -) - -#endif - -/* - * R_DRAM_TIMING - * - type: WO - * - addr: 0xb0000008 - * - group: Bus interface configuration registers - */ - -#if USE_GROUP__Bus_interface_configuration_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DRAM_TIMING -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DRAM_TIMING. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_DRAM_TIMING. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DRAM_TIMING(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \ - *R_DRAM_TIMING__SADDR = ( \ - REG_INITIATED(R_DRAM_TIMING_) \ - REG_VAL__R_DRAM_TIMING_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10) \ - ), \ - R_DRAM_TIMING__WRITE(R_DRAM_TIMING__ADDR, *R_DRAM_TIMING__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_DRAM_TIMING__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_DRAM_TIMING. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_DRAM_TIMING. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_DRAM_TIMING__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \ - *R_DRAM_TIMING__SADDR = ( \ - REG_INITIATED(R_DRAM_TIMING_) \ - REG_VAL__R_DRAM_TIMING_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_DRAM_TIMING -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_DRAM_TIMING(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \ - (R_DRAM_TIMING__sdram__##f1##__MASK & REG__##v1) | \ - (R_DRAM_TIMING__ref__##f2##__MASK & REG__##v2) | \ - (R_DRAM_TIMING__rp__##f3##__MASK & REG__##v3) | \ - (R_DRAM_TIMING__rs__##f4##__MASK & REG__##v4) | \ - (R_DRAM_TIMING__rh__##f5##__MASK & REG__##v5) | \ - (R_DRAM_TIMING__w__##f6##__MASK & REG__##v6) | \ - (R_DRAM_TIMING__c__##f7##__MASK & REG__##v7) | \ - (R_DRAM_TIMING__cz__##f8##__MASK & REG__##v8) | \ - (R_DRAM_TIMING__cp__##f9##__MASK & REG__##v9) | \ - (R_DRAM_TIMING__cw__##f10##__MASK & REG__##v10) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DRAM_TIMING -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DRAM_TIMING. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_DRAM_TIMING(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \ - (R_DRAM_TIMING__sdram__##f1##__VAL(R_DRAM_TIMING_, sdram_, v1) << R_DRAM_TIMING__sdram__BITNR) | \ - (R_DRAM_TIMING__ref__##f2##__VAL(R_DRAM_TIMING_, ref_, v2) << R_DRAM_TIMING__ref__BITNR) | \ - (R_DRAM_TIMING__rp__##f3##__VAL(R_DRAM_TIMING_, rp_, v3) << R_DRAM_TIMING__rp__BITNR) | \ - (R_DRAM_TIMING__rs__##f4##__VAL(R_DRAM_TIMING_, rs_, v4) << R_DRAM_TIMING__rs__BITNR) | \ - (R_DRAM_TIMING__rh__##f5##__VAL(R_DRAM_TIMING_, rh_, v5) << R_DRAM_TIMING__rh__BITNR) | \ - (R_DRAM_TIMING__w__##f6##__VAL(R_DRAM_TIMING_, w_, v6) << R_DRAM_TIMING__w__BITNR) | \ - (R_DRAM_TIMING__c__##f7##__VAL(R_DRAM_TIMING_, c_, v7) << R_DRAM_TIMING__c__BITNR) | \ - (R_DRAM_TIMING__cz__##f8##__VAL(R_DRAM_TIMING_, cz_, v8) << R_DRAM_TIMING__cz__BITNR) | \ - (R_DRAM_TIMING__cp__##f9##__VAL(R_DRAM_TIMING_, cp_, v9) << R_DRAM_TIMING__cp__BITNR) | \ - (R_DRAM_TIMING__cw__##f10##__VAL(R_DRAM_TIMING_, cw_, v10) << R_DRAM_TIMING__cw__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_DRAM_TIMING_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_DRAM_TIMING. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_DRAM_TIMING_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10) ( \ - (R_DRAM_TIMING__sdram__##f1_##_VAL(R_DRAM_TIMING_, sdram_, v1) << R_DRAM_TIMING__sdram__BITNR) | \ - (R_DRAM_TIMING__ref__##f2_##_VAL(R_DRAM_TIMING_, ref_, v2) << R_DRAM_TIMING__ref__BITNR) | \ - (R_DRAM_TIMING__rp__##f3_##_VAL(R_DRAM_TIMING_, rp_, v3) << R_DRAM_TIMING__rp__BITNR) | \ - (R_DRAM_TIMING__rs__##f4_##_VAL(R_DRAM_TIMING_, rs_, v4) << R_DRAM_TIMING__rs__BITNR) | \ - (R_DRAM_TIMING__rh__##f5_##_VAL(R_DRAM_TIMING_, rh_, v5) << R_DRAM_TIMING__rh__BITNR) | \ - (R_DRAM_TIMING__w__##f6_##_VAL(R_DRAM_TIMING_, w_, v6) << R_DRAM_TIMING__w__BITNR) | \ - (R_DRAM_TIMING__c__##f7_##_VAL(R_DRAM_TIMING_, c_, v7) << R_DRAM_TIMING__c__BITNR) | \ - (R_DRAM_TIMING__cz__##f8_##_VAL(R_DRAM_TIMING_, cz_, v8) << R_DRAM_TIMING__cz__BITNR) | \ - (R_DRAM_TIMING__cp__##f9_##_VAL(R_DRAM_TIMING_, cp_, v9) << R_DRAM_TIMING__cp__BITNR) | \ - (R_DRAM_TIMING__cw__##f10_##_VAL(R_DRAM_TIMING_, cw_, v10) << R_DRAM_TIMING__cw__BITNR) \ -) - -#endif - -/* - * R_EXT_DMA_0_ADDR - * - type: WO - * - addr: 0xb0000014 - * - group: External DMA registers - */ - -#if USE_GROUP__External_DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_EXT_DMA_0_ADDR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_EXT_DMA_0_ADDR. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_EXT_DMA_0_ADDR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_EXT_DMA_0_ADDR(f1,v1) ( \ - *R_EXT_DMA_0_ADDR__SADDR = ( \ - REG_INITIATED(R_EXT_DMA_0_ADDR_) \ - REG_VAL__R_EXT_DMA_0_ADDR_(f1##_,v1) \ - ), \ - R_EXT_DMA_0_ADDR__WRITE(R_EXT_DMA_0_ADDR__ADDR, *R_EXT_DMA_0_ADDR__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_EXT_DMA_0_ADDR__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_EXT_DMA_0_ADDR. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_EXT_DMA_0_ADDR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_EXT_DMA_0_ADDR__SHADOW(f1,v1) ( \ - *R_EXT_DMA_0_ADDR__SADDR = ( \ - REG_INITIATED(R_EXT_DMA_0_ADDR_) \ - REG_VAL__R_EXT_DMA_0_ADDR_(f1##_,v1) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_EXT_DMA_0_ADDR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_EXT_DMA_0_ADDR(f1,v1) ( \ - (R_EXT_DMA_0_ADDR__ext0_addr__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_EXT_DMA_0_ADDR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_EXT_DMA_0_ADDR. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_EXT_DMA_0_ADDR(f1,v1) ( \ - (R_EXT_DMA_0_ADDR__ext0_addr__##f1##__VAL(R_EXT_DMA_0_ADDR_, ext0_addr_, v1) << R_EXT_DMA_0_ADDR__ext0_addr__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_EXT_DMA_0_ADDR_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_EXT_DMA_0_ADDR. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_EXT_DMA_0_ADDR_(f1_,v1) ( \ - (R_EXT_DMA_0_ADDR__ext0_addr__##f1_##_VAL(R_EXT_DMA_0_ADDR_, ext0_addr_, v1) << R_EXT_DMA_0_ADDR__ext0_addr__BITNR) \ -) - -#endif - -/* - * R_EXT_DMA_0_CMD - * - type: WO - * - addr: 0xb0000010 - * - group: External DMA registers - */ - -#if USE_GROUP__External_DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_EXT_DMA_0_CMD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_EXT_DMA_0_CMD. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_EXT_DMA_0_CMD. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_EXT_DMA_0_CMD(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - *R_EXT_DMA_0_CMD__SADDR = ( \ - REG_INITIATED(R_EXT_DMA_0_CMD_) \ - REG_VAL__R_EXT_DMA_0_CMD_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \ - ), \ - R_EXT_DMA_0_CMD__WRITE(R_EXT_DMA_0_CMD__ADDR, *R_EXT_DMA_0_CMD__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_EXT_DMA_0_CMD__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_EXT_DMA_0_CMD. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_EXT_DMA_0_CMD. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_EXT_DMA_0_CMD__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - *R_EXT_DMA_0_CMD__SADDR = ( \ - REG_INITIATED(R_EXT_DMA_0_CMD_) \ - REG_VAL__R_EXT_DMA_0_CMD_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_EXT_DMA_0_CMD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_EXT_DMA_0_CMD(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - (R_EXT_DMA_0_CMD__cnt__##f1##__MASK & REG__##v1) | \ - (R_EXT_DMA_0_CMD__rqpol__##f2##__MASK & REG__##v2) | \ - (R_EXT_DMA_0_CMD__apol__##f3##__MASK & REG__##v3) | \ - (R_EXT_DMA_0_CMD__rq_ack__##f4##__MASK & REG__##v4) | \ - (R_EXT_DMA_0_CMD__wid__##f5##__MASK & REG__##v5) | \ - (R_EXT_DMA_0_CMD__dir__##f6##__MASK & REG__##v6) | \ - (R_EXT_DMA_0_CMD__run__##f7##__MASK & REG__##v7) | \ - (R_EXT_DMA_0_CMD__trf_count__##f8##__MASK & REG__##v8) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_EXT_DMA_0_CMD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_EXT_DMA_0_CMD. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_EXT_DMA_0_CMD(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - (R_EXT_DMA_0_CMD__cnt__##f1##__VAL(R_EXT_DMA_0_CMD_, cnt_, v1) << R_EXT_DMA_0_CMD__cnt__BITNR) | \ - (R_EXT_DMA_0_CMD__rqpol__##f2##__VAL(R_EXT_DMA_0_CMD_, rqpol_, v2) << R_EXT_DMA_0_CMD__rqpol__BITNR) | \ - (R_EXT_DMA_0_CMD__apol__##f3##__VAL(R_EXT_DMA_0_CMD_, apol_, v3) << R_EXT_DMA_0_CMD__apol__BITNR) | \ - (R_EXT_DMA_0_CMD__rq_ack__##f4##__VAL(R_EXT_DMA_0_CMD_, rq_ack_, v4) << R_EXT_DMA_0_CMD__rq_ack__BITNR) | \ - (R_EXT_DMA_0_CMD__wid__##f5##__VAL(R_EXT_DMA_0_CMD_, wid_, v5) << R_EXT_DMA_0_CMD__wid__BITNR) | \ - (R_EXT_DMA_0_CMD__dir__##f6##__VAL(R_EXT_DMA_0_CMD_, dir_, v6) << R_EXT_DMA_0_CMD__dir__BITNR) | \ - (R_EXT_DMA_0_CMD__run__##f7##__VAL(R_EXT_DMA_0_CMD_, run_, v7) << R_EXT_DMA_0_CMD__run__BITNR) | \ - (R_EXT_DMA_0_CMD__trf_count__##f8##__VAL(R_EXT_DMA_0_CMD_, trf_count_, v8) << R_EXT_DMA_0_CMD__trf_count__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_EXT_DMA_0_CMD_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_EXT_DMA_0_CMD. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_EXT_DMA_0_CMD_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8) ( \ - (R_EXT_DMA_0_CMD__cnt__##f1_##_VAL(R_EXT_DMA_0_CMD_, cnt_, v1) << R_EXT_DMA_0_CMD__cnt__BITNR) | \ - (R_EXT_DMA_0_CMD__rqpol__##f2_##_VAL(R_EXT_DMA_0_CMD_, rqpol_, v2) << R_EXT_DMA_0_CMD__rqpol__BITNR) | \ - (R_EXT_DMA_0_CMD__apol__##f3_##_VAL(R_EXT_DMA_0_CMD_, apol_, v3) << R_EXT_DMA_0_CMD__apol__BITNR) | \ - (R_EXT_DMA_0_CMD__rq_ack__##f4_##_VAL(R_EXT_DMA_0_CMD_, rq_ack_, v4) << R_EXT_DMA_0_CMD__rq_ack__BITNR) | \ - (R_EXT_DMA_0_CMD__wid__##f5_##_VAL(R_EXT_DMA_0_CMD_, wid_, v5) << R_EXT_DMA_0_CMD__wid__BITNR) | \ - (R_EXT_DMA_0_CMD__dir__##f6_##_VAL(R_EXT_DMA_0_CMD_, dir_, v6) << R_EXT_DMA_0_CMD__dir__BITNR) | \ - (R_EXT_DMA_0_CMD__run__##f7_##_VAL(R_EXT_DMA_0_CMD_, run_, v7) << R_EXT_DMA_0_CMD__run__BITNR) | \ - (R_EXT_DMA_0_CMD__trf_count__##f8_##_VAL(R_EXT_DMA_0_CMD_, trf_count_, v8) << R_EXT_DMA_0_CMD__trf_count__BITNR) \ -) - -#endif - -/* - * R_EXT_DMA_0_STAT - * - type: RO - * - addr: 0xb0000010 - * - group: External DMA registers - */ - -#if USE_GROUP__External_DMA_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_EXT_DMA_0_STAT -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_EXT_DMA_0_STAT(f1,v1,f2,v2) ( \ - (R_EXT_DMA_0_STAT__run__##f1##__MASK & REG__##v1) | \ - (R_EXT_DMA_0_STAT__trf_count__##f2##__MASK & REG__##v2) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_EXT_DMA_0_STAT -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_EXT_DMA_0_STAT. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_EXT_DMA_0_STAT(f1,v1,f2,v2) ( \ - (R_EXT_DMA_0_STAT__run__##f1##__VAL(R_EXT_DMA_0_STAT_, run_, v1) << R_EXT_DMA_0_STAT__run__BITNR) | \ - (R_EXT_DMA_0_STAT__trf_count__##f2##__VAL(R_EXT_DMA_0_STAT_, trf_count_, v2) << R_EXT_DMA_0_STAT__trf_count__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_EXT_DMA_0_STAT_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_EXT_DMA_0_STAT. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_EXT_DMA_0_STAT_(f1_,v1,f2_,v2) ( \ - (R_EXT_DMA_0_STAT__run__##f1_##_VAL(R_EXT_DMA_0_STAT_, run_, v1) << R_EXT_DMA_0_STAT__run__BITNR) | \ - (R_EXT_DMA_0_STAT__trf_count__##f2_##_VAL(R_EXT_DMA_0_STAT_, trf_count_, v2) << R_EXT_DMA_0_STAT__trf_count__BITNR) \ -) - -#endif - -/* - * R_EXT_DMA_1_ADDR - * - type: WO - * - addr: 0xb000001c - * - group: External DMA registers - */ - -#if USE_GROUP__External_DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_EXT_DMA_1_ADDR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_EXT_DMA_1_ADDR. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_EXT_DMA_1_ADDR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_EXT_DMA_1_ADDR(f1,v1) ( \ - *R_EXT_DMA_1_ADDR__SADDR = ( \ - REG_INITIATED(R_EXT_DMA_1_ADDR_) \ - REG_VAL__R_EXT_DMA_1_ADDR_(f1##_,v1) \ - ), \ - R_EXT_DMA_1_ADDR__WRITE(R_EXT_DMA_1_ADDR__ADDR, *R_EXT_DMA_1_ADDR__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_EXT_DMA_1_ADDR__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_EXT_DMA_1_ADDR. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_EXT_DMA_1_ADDR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_EXT_DMA_1_ADDR__SHADOW(f1,v1) ( \ - *R_EXT_DMA_1_ADDR__SADDR = ( \ - REG_INITIATED(R_EXT_DMA_1_ADDR_) \ - REG_VAL__R_EXT_DMA_1_ADDR_(f1##_,v1) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_EXT_DMA_1_ADDR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_EXT_DMA_1_ADDR(f1,v1) ( \ - (R_EXT_DMA_1_ADDR__ext0_addr__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_EXT_DMA_1_ADDR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_EXT_DMA_1_ADDR. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_EXT_DMA_1_ADDR(f1,v1) ( \ - (R_EXT_DMA_1_ADDR__ext0_addr__##f1##__VAL(R_EXT_DMA_1_ADDR_, ext0_addr_, v1) << R_EXT_DMA_1_ADDR__ext0_addr__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_EXT_DMA_1_ADDR_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_EXT_DMA_1_ADDR. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_EXT_DMA_1_ADDR_(f1_,v1) ( \ - (R_EXT_DMA_1_ADDR__ext0_addr__##f1_##_VAL(R_EXT_DMA_1_ADDR_, ext0_addr_, v1) << R_EXT_DMA_1_ADDR__ext0_addr__BITNR) \ -) - -#endif - -/* - * R_EXT_DMA_1_CMD - * - type: WO - * - addr: 0xb0000018 - * - group: External DMA registers - */ - -#if USE_GROUP__External_DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_EXT_DMA_1_CMD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_EXT_DMA_1_CMD. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_EXT_DMA_1_CMD. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_EXT_DMA_1_CMD(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - *R_EXT_DMA_1_CMD__SADDR = ( \ - REG_INITIATED(R_EXT_DMA_1_CMD_) \ - REG_VAL__R_EXT_DMA_1_CMD_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \ - ), \ - R_EXT_DMA_1_CMD__WRITE(R_EXT_DMA_1_CMD__ADDR, *R_EXT_DMA_1_CMD__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_EXT_DMA_1_CMD__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_EXT_DMA_1_CMD. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_EXT_DMA_1_CMD. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_EXT_DMA_1_CMD__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - *R_EXT_DMA_1_CMD__SADDR = ( \ - REG_INITIATED(R_EXT_DMA_1_CMD_) \ - REG_VAL__R_EXT_DMA_1_CMD_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_EXT_DMA_1_CMD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_EXT_DMA_1_CMD(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - (R_EXT_DMA_1_CMD__cnt__##f1##__MASK & REG__##v1) | \ - (R_EXT_DMA_1_CMD__rqpol__##f2##__MASK & REG__##v2) | \ - (R_EXT_DMA_1_CMD__apol__##f3##__MASK & REG__##v3) | \ - (R_EXT_DMA_1_CMD__rq_ack__##f4##__MASK & REG__##v4) | \ - (R_EXT_DMA_1_CMD__wid__##f5##__MASK & REG__##v5) | \ - (R_EXT_DMA_1_CMD__dir__##f6##__MASK & REG__##v6) | \ - (R_EXT_DMA_1_CMD__run__##f7##__MASK & REG__##v7) | \ - (R_EXT_DMA_1_CMD__trf_count__##f8##__MASK & REG__##v8) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_EXT_DMA_1_CMD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_EXT_DMA_1_CMD. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_EXT_DMA_1_CMD(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - (R_EXT_DMA_1_CMD__cnt__##f1##__VAL(R_EXT_DMA_1_CMD_, cnt_, v1) << R_EXT_DMA_1_CMD__cnt__BITNR) | \ - (R_EXT_DMA_1_CMD__rqpol__##f2##__VAL(R_EXT_DMA_1_CMD_, rqpol_, v2) << R_EXT_DMA_1_CMD__rqpol__BITNR) | \ - (R_EXT_DMA_1_CMD__apol__##f3##__VAL(R_EXT_DMA_1_CMD_, apol_, v3) << R_EXT_DMA_1_CMD__apol__BITNR) | \ - (R_EXT_DMA_1_CMD__rq_ack__##f4##__VAL(R_EXT_DMA_1_CMD_, rq_ack_, v4) << R_EXT_DMA_1_CMD__rq_ack__BITNR) | \ - (R_EXT_DMA_1_CMD__wid__##f5##__VAL(R_EXT_DMA_1_CMD_, wid_, v5) << R_EXT_DMA_1_CMD__wid__BITNR) | \ - (R_EXT_DMA_1_CMD__dir__##f6##__VAL(R_EXT_DMA_1_CMD_, dir_, v6) << R_EXT_DMA_1_CMD__dir__BITNR) | \ - (R_EXT_DMA_1_CMD__run__##f7##__VAL(R_EXT_DMA_1_CMD_, run_, v7) << R_EXT_DMA_1_CMD__run__BITNR) | \ - (R_EXT_DMA_1_CMD__trf_count__##f8##__VAL(R_EXT_DMA_1_CMD_, trf_count_, v8) << R_EXT_DMA_1_CMD__trf_count__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_EXT_DMA_1_CMD_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_EXT_DMA_1_CMD. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_EXT_DMA_1_CMD_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8) ( \ - (R_EXT_DMA_1_CMD__cnt__##f1_##_VAL(R_EXT_DMA_1_CMD_, cnt_, v1) << R_EXT_DMA_1_CMD__cnt__BITNR) | \ - (R_EXT_DMA_1_CMD__rqpol__##f2_##_VAL(R_EXT_DMA_1_CMD_, rqpol_, v2) << R_EXT_DMA_1_CMD__rqpol__BITNR) | \ - (R_EXT_DMA_1_CMD__apol__##f3_##_VAL(R_EXT_DMA_1_CMD_, apol_, v3) << R_EXT_DMA_1_CMD__apol__BITNR) | \ - (R_EXT_DMA_1_CMD__rq_ack__##f4_##_VAL(R_EXT_DMA_1_CMD_, rq_ack_, v4) << R_EXT_DMA_1_CMD__rq_ack__BITNR) | \ - (R_EXT_DMA_1_CMD__wid__##f5_##_VAL(R_EXT_DMA_1_CMD_, wid_, v5) << R_EXT_DMA_1_CMD__wid__BITNR) | \ - (R_EXT_DMA_1_CMD__dir__##f6_##_VAL(R_EXT_DMA_1_CMD_, dir_, v6) << R_EXT_DMA_1_CMD__dir__BITNR) | \ - (R_EXT_DMA_1_CMD__run__##f7_##_VAL(R_EXT_DMA_1_CMD_, run_, v7) << R_EXT_DMA_1_CMD__run__BITNR) | \ - (R_EXT_DMA_1_CMD__trf_count__##f8_##_VAL(R_EXT_DMA_1_CMD_, trf_count_, v8) << R_EXT_DMA_1_CMD__trf_count__BITNR) \ -) - -#endif - -/* - * R_EXT_DMA_1_STAT - * - type: RO - * - addr: 0xb0000018 - * - group: External DMA registers - */ - -#if USE_GROUP__External_DMA_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_EXT_DMA_1_STAT -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_EXT_DMA_1_STAT(f1,v1,f2,v2) ( \ - (R_EXT_DMA_1_STAT__run__##f1##__MASK & REG__##v1) | \ - (R_EXT_DMA_1_STAT__trf_count__##f2##__MASK & REG__##v2) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_EXT_DMA_1_STAT -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_EXT_DMA_1_STAT. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_EXT_DMA_1_STAT(f1,v1,f2,v2) ( \ - (R_EXT_DMA_1_STAT__run__##f1##__VAL(R_EXT_DMA_1_STAT_, run_, v1) << R_EXT_DMA_1_STAT__run__BITNR) | \ - (R_EXT_DMA_1_STAT__trf_count__##f2##__VAL(R_EXT_DMA_1_STAT_, trf_count_, v2) << R_EXT_DMA_1_STAT__trf_count__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_EXT_DMA_1_STAT_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_EXT_DMA_1_STAT. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_EXT_DMA_1_STAT_(f1_,v1,f2_,v2) ( \ - (R_EXT_DMA_1_STAT__run__##f1_##_VAL(R_EXT_DMA_1_STAT_, run_, v1) << R_EXT_DMA_1_STAT__run__BITNR) | \ - (R_EXT_DMA_1_STAT__trf_count__##f2_##_VAL(R_EXT_DMA_1_STAT_, trf_count_, v2) << R_EXT_DMA_1_STAT__trf_count__BITNR) \ -) - -#endif - -/* - * R_GEN_CONFIG - * - type: WO - * - addr: 0xb000002c - * - group: General config registers - */ - -#if USE_GROUP__General_config_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_GEN_CONFIG -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_GEN_CONFIG. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_GEN_CONFIG. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_GEN_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25) ( \ - *R_GEN_CONFIG__SADDR = ( \ - REG_INITIATED(R_GEN_CONFIG_) \ - REG_VAL__R_GEN_CONFIG_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20,f21##_,v21,f22##_,v22,f23##_,v23,f24##_,v24,f25##_,v25) \ - ), \ - R_GEN_CONFIG__WRITE(R_GEN_CONFIG__ADDR, *R_GEN_CONFIG__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_GEN_CONFIG__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_GEN_CONFIG. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_GEN_CONFIG. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_GEN_CONFIG__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25) ( \ - *R_GEN_CONFIG__SADDR = ( \ - REG_INITIATED(R_GEN_CONFIG_) \ - REG_VAL__R_GEN_CONFIG_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20,f21##_,v21,f22##_,v22,f23##_,v23,f24##_,v24,f25##_,v25) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_GEN_CONFIG -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_GEN_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25) ( \ - (R_GEN_CONFIG__par_w__##f1##__MASK & REG__##v1) | \ - (R_GEN_CONFIG__usb2__##f2##__MASK & REG__##v2) | \ - (R_GEN_CONFIG__usb1__##f3##__MASK & REG__##v3) | \ - (R_GEN_CONFIG__g24dir__##f4##__MASK & REG__##v4) | \ - (R_GEN_CONFIG__g16_23dir__##f5##__MASK & REG__##v5) | \ - (R_GEN_CONFIG__g8_15dir__##f6##__MASK & REG__##v6) | \ - (R_GEN_CONFIG__g0dir__##f7##__MASK & REG__##v7) | \ - (R_GEN_CONFIG__dma9__##f8##__MASK & REG__##v8) | \ - (R_GEN_CONFIG__dma8__##f9##__MASK & REG__##v9) | \ - (R_GEN_CONFIG__dma7__##f10##__MASK & REG__##v10) | \ - (R_GEN_CONFIG__dma6__##f11##__MASK & REG__##v11) | \ - (R_GEN_CONFIG__dma5__##f12##__MASK & REG__##v12) | \ - (R_GEN_CONFIG__dma4__##f13##__MASK & REG__##v13) | \ - (R_GEN_CONFIG__dma3__##f14##__MASK & REG__##v14) | \ - (R_GEN_CONFIG__dma2__##f15##__MASK & REG__##v15) | \ - (R_GEN_CONFIG__mio_w__##f16##__MASK & REG__##v16) | \ - (R_GEN_CONFIG__ser3__##f17##__MASK & REG__##v17) | \ - (R_GEN_CONFIG__par1__##f18##__MASK & REG__##v18) | \ - (R_GEN_CONFIG__scsi0w__##f19##__MASK & REG__##v19) | \ - (R_GEN_CONFIG__scsi1__##f20##__MASK & REG__##v20) | \ - (R_GEN_CONFIG__mio__##f21##__MASK & REG__##v21) | \ - (R_GEN_CONFIG__ser2__##f22##__MASK & REG__##v22) | \ - (R_GEN_CONFIG__par0__##f23##__MASK & REG__##v23) | \ - (R_GEN_CONFIG__ata__##f24##__MASK & REG__##v24) | \ - (R_GEN_CONFIG__scsi0__##f25##__MASK & REG__##v25) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_GEN_CONFIG -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_GEN_CONFIG. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_GEN_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25) ( \ - (R_GEN_CONFIG__par_w__##f1##__VAL(R_GEN_CONFIG_, par_w_, v1) << R_GEN_CONFIG__par_w__BITNR) | \ - (R_GEN_CONFIG__usb2__##f2##__VAL(R_GEN_CONFIG_, usb2_, v2) << R_GEN_CONFIG__usb2__BITNR) | \ - (R_GEN_CONFIG__usb1__##f3##__VAL(R_GEN_CONFIG_, usb1_, v3) << R_GEN_CONFIG__usb1__BITNR) | \ - (R_GEN_CONFIG__g24dir__##f4##__VAL(R_GEN_CONFIG_, g24dir_, v4) << R_GEN_CONFIG__g24dir__BITNR) | \ - (R_GEN_CONFIG__g16_23dir__##f5##__VAL(R_GEN_CONFIG_, g16_23dir_, v5) << R_GEN_CONFIG__g16_23dir__BITNR) | \ - (R_GEN_CONFIG__g8_15dir__##f6##__VAL(R_GEN_CONFIG_, g8_15dir_, v6) << R_GEN_CONFIG__g8_15dir__BITNR) | \ - (R_GEN_CONFIG__g0dir__##f7##__VAL(R_GEN_CONFIG_, g0dir_, v7) << R_GEN_CONFIG__g0dir__BITNR) | \ - (R_GEN_CONFIG__dma9__##f8##__VAL(R_GEN_CONFIG_, dma9_, v8) << R_GEN_CONFIG__dma9__BITNR) | \ - (R_GEN_CONFIG__dma8__##f9##__VAL(R_GEN_CONFIG_, dma8_, v9) << R_GEN_CONFIG__dma8__BITNR) | \ - (R_GEN_CONFIG__dma7__##f10##__VAL(R_GEN_CONFIG_, dma7_, v10) << R_GEN_CONFIG__dma7__BITNR) | \ - (R_GEN_CONFIG__dma6__##f11##__VAL(R_GEN_CONFIG_, dma6_, v11) << R_GEN_CONFIG__dma6__BITNR) | \ - (R_GEN_CONFIG__dma5__##f12##__VAL(R_GEN_CONFIG_, dma5_, v12) << R_GEN_CONFIG__dma5__BITNR) | \ - (R_GEN_CONFIG__dma4__##f13##__VAL(R_GEN_CONFIG_, dma4_, v13) << R_GEN_CONFIG__dma4__BITNR) | \ - (R_GEN_CONFIG__dma3__##f14##__VAL(R_GEN_CONFIG_, dma3_, v14) << R_GEN_CONFIG__dma3__BITNR) | \ - (R_GEN_CONFIG__dma2__##f15##__VAL(R_GEN_CONFIG_, dma2_, v15) << R_GEN_CONFIG__dma2__BITNR) | \ - (R_GEN_CONFIG__mio_w__##f16##__VAL(R_GEN_CONFIG_, mio_w_, v16) << R_GEN_CONFIG__mio_w__BITNR) | \ - (R_GEN_CONFIG__ser3__##f17##__VAL(R_GEN_CONFIG_, ser3_, v17) << R_GEN_CONFIG__ser3__BITNR) | \ - (R_GEN_CONFIG__par1__##f18##__VAL(R_GEN_CONFIG_, par1_, v18) << R_GEN_CONFIG__par1__BITNR) | \ - (R_GEN_CONFIG__scsi0w__##f19##__VAL(R_GEN_CONFIG_, scsi0w_, v19) << R_GEN_CONFIG__scsi0w__BITNR) | \ - (R_GEN_CONFIG__scsi1__##f20##__VAL(R_GEN_CONFIG_, scsi1_, v20) << R_GEN_CONFIG__scsi1__BITNR) | \ - (R_GEN_CONFIG__mio__##f21##__VAL(R_GEN_CONFIG_, mio_, v21) << R_GEN_CONFIG__mio__BITNR) | \ - (R_GEN_CONFIG__ser2__##f22##__VAL(R_GEN_CONFIG_, ser2_, v22) << R_GEN_CONFIG__ser2__BITNR) | \ - (R_GEN_CONFIG__par0__##f23##__VAL(R_GEN_CONFIG_, par0_, v23) << R_GEN_CONFIG__par0__BITNR) | \ - (R_GEN_CONFIG__ata__##f24##__VAL(R_GEN_CONFIG_, ata_, v24) << R_GEN_CONFIG__ata__BITNR) | \ - (R_GEN_CONFIG__scsi0__##f25##__VAL(R_GEN_CONFIG_, scsi0_, v25) << R_GEN_CONFIG__scsi0__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_GEN_CONFIG_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_GEN_CONFIG. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_GEN_CONFIG_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16,f17_,v17,f18_,v18,f19_,v19,f20_,v20,f21_,v21,f22_,v22,f23_,v23,f24_,v24,f25_,v25) ( \ - (R_GEN_CONFIG__par_w__##f1_##_VAL(R_GEN_CONFIG_, par_w_, v1) << R_GEN_CONFIG__par_w__BITNR) | \ - (R_GEN_CONFIG__usb2__##f2_##_VAL(R_GEN_CONFIG_, usb2_, v2) << R_GEN_CONFIG__usb2__BITNR) | \ - (R_GEN_CONFIG__usb1__##f3_##_VAL(R_GEN_CONFIG_, usb1_, v3) << R_GEN_CONFIG__usb1__BITNR) | \ - (R_GEN_CONFIG__g24dir__##f4_##_VAL(R_GEN_CONFIG_, g24dir_, v4) << R_GEN_CONFIG__g24dir__BITNR) | \ - (R_GEN_CONFIG__g16_23dir__##f5_##_VAL(R_GEN_CONFIG_, g16_23dir_, v5) << R_GEN_CONFIG__g16_23dir__BITNR) | \ - (R_GEN_CONFIG__g8_15dir__##f6_##_VAL(R_GEN_CONFIG_, g8_15dir_, v6) << R_GEN_CONFIG__g8_15dir__BITNR) | \ - (R_GEN_CONFIG__g0dir__##f7_##_VAL(R_GEN_CONFIG_, g0dir_, v7) << R_GEN_CONFIG__g0dir__BITNR) | \ - (R_GEN_CONFIG__dma9__##f8_##_VAL(R_GEN_CONFIG_, dma9_, v8) << R_GEN_CONFIG__dma9__BITNR) | \ - (R_GEN_CONFIG__dma8__##f9_##_VAL(R_GEN_CONFIG_, dma8_, v9) << R_GEN_CONFIG__dma8__BITNR) | \ - (R_GEN_CONFIG__dma7__##f10_##_VAL(R_GEN_CONFIG_, dma7_, v10) << R_GEN_CONFIG__dma7__BITNR) | \ - (R_GEN_CONFIG__dma6__##f11_##_VAL(R_GEN_CONFIG_, dma6_, v11) << R_GEN_CONFIG__dma6__BITNR) | \ - (R_GEN_CONFIG__dma5__##f12_##_VAL(R_GEN_CONFIG_, dma5_, v12) << R_GEN_CONFIG__dma5__BITNR) | \ - (R_GEN_CONFIG__dma4__##f13_##_VAL(R_GEN_CONFIG_, dma4_, v13) << R_GEN_CONFIG__dma4__BITNR) | \ - (R_GEN_CONFIG__dma3__##f14_##_VAL(R_GEN_CONFIG_, dma3_, v14) << R_GEN_CONFIG__dma3__BITNR) | \ - (R_GEN_CONFIG__dma2__##f15_##_VAL(R_GEN_CONFIG_, dma2_, v15) << R_GEN_CONFIG__dma2__BITNR) | \ - (R_GEN_CONFIG__mio_w__##f16_##_VAL(R_GEN_CONFIG_, mio_w_, v16) << R_GEN_CONFIG__mio_w__BITNR) | \ - (R_GEN_CONFIG__ser3__##f17_##_VAL(R_GEN_CONFIG_, ser3_, v17) << R_GEN_CONFIG__ser3__BITNR) | \ - (R_GEN_CONFIG__par1__##f18_##_VAL(R_GEN_CONFIG_, par1_, v18) << R_GEN_CONFIG__par1__BITNR) | \ - (R_GEN_CONFIG__scsi0w__##f19_##_VAL(R_GEN_CONFIG_, scsi0w_, v19) << R_GEN_CONFIG__scsi0w__BITNR) | \ - (R_GEN_CONFIG__scsi1__##f20_##_VAL(R_GEN_CONFIG_, scsi1_, v20) << R_GEN_CONFIG__scsi1__BITNR) | \ - (R_GEN_CONFIG__mio__##f21_##_VAL(R_GEN_CONFIG_, mio_, v21) << R_GEN_CONFIG__mio__BITNR) | \ - (R_GEN_CONFIG__ser2__##f22_##_VAL(R_GEN_CONFIG_, ser2_, v22) << R_GEN_CONFIG__ser2__BITNR) | \ - (R_GEN_CONFIG__par0__##f23_##_VAL(R_GEN_CONFIG_, par0_, v23) << R_GEN_CONFIG__par0__BITNR) | \ - (R_GEN_CONFIG__ata__##f24_##_VAL(R_GEN_CONFIG_, ata_, v24) << R_GEN_CONFIG__ata__BITNR) | \ - (R_GEN_CONFIG__scsi0__##f25_##_VAL(R_GEN_CONFIG_, scsi0_, v25) << R_GEN_CONFIG__scsi0__BITNR) \ -) - -#endif - -/* - * R_GEN_CONFIG_II - * - type: WO - * - addr: 0xb0000034 - * - group: General config registers - */ - -#if USE_GROUP__General_config_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_GEN_CONFIG_II -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_GEN_CONFIG_II. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_GEN_CONFIG_II. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_GEN_CONFIG_II(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5) ( \ - *R_GEN_CONFIG_II__SADDR = ( \ - REG_INITIATED(R_GEN_CONFIG_II_) \ - REG_VAL__R_GEN_CONFIG_II_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5) \ - ), \ - R_GEN_CONFIG_II__WRITE(R_GEN_CONFIG_II__ADDR, *R_GEN_CONFIG_II__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_GEN_CONFIG_II__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_GEN_CONFIG_II. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_GEN_CONFIG_II. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_GEN_CONFIG_II__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5) ( \ - *R_GEN_CONFIG_II__SADDR = ( \ - REG_INITIATED(R_GEN_CONFIG_II_) \ - REG_VAL__R_GEN_CONFIG_II_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_GEN_CONFIG_II -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_GEN_CONFIG_II(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5) ( \ - (R_GEN_CONFIG_II__sermode3__##f1##__MASK & REG__##v1) | \ - (R_GEN_CONFIG_II__sermode1__##f2##__MASK & REG__##v2) | \ - (R_GEN_CONFIG_II__ext_clk__##f3##__MASK & REG__##v3) | \ - (R_GEN_CONFIG_II__ser3__##f4##__MASK & REG__##v4) | \ - (R_GEN_CONFIG_II__ser2__##f5##__MASK & REG__##v5) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_GEN_CONFIG_II -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_GEN_CONFIG_II. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_GEN_CONFIG_II(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5) ( \ - (R_GEN_CONFIG_II__sermode3__##f1##__VAL(R_GEN_CONFIG_II_, sermode3_, v1) << R_GEN_CONFIG_II__sermode3__BITNR) | \ - (R_GEN_CONFIG_II__sermode1__##f2##__VAL(R_GEN_CONFIG_II_, sermode1_, v2) << R_GEN_CONFIG_II__sermode1__BITNR) | \ - (R_GEN_CONFIG_II__ext_clk__##f3##__VAL(R_GEN_CONFIG_II_, ext_clk_, v3) << R_GEN_CONFIG_II__ext_clk__BITNR) | \ - (R_GEN_CONFIG_II__ser3__##f4##__VAL(R_GEN_CONFIG_II_, ser3_, v4) << R_GEN_CONFIG_II__ser3__BITNR) | \ - (R_GEN_CONFIG_II__ser2__##f5##__VAL(R_GEN_CONFIG_II_, ser2_, v5) << R_GEN_CONFIG_II__ser2__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_GEN_CONFIG_II_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_GEN_CONFIG_II. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_GEN_CONFIG_II_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5) ( \ - (R_GEN_CONFIG_II__sermode3__##f1_##_VAL(R_GEN_CONFIG_II_, sermode3_, v1) << R_GEN_CONFIG_II__sermode3__BITNR) | \ - (R_GEN_CONFIG_II__sermode1__##f2_##_VAL(R_GEN_CONFIG_II_, sermode1_, v2) << R_GEN_CONFIG_II__sermode1__BITNR) | \ - (R_GEN_CONFIG_II__ext_clk__##f3_##_VAL(R_GEN_CONFIG_II_, ext_clk_, v3) << R_GEN_CONFIG_II__ext_clk__BITNR) | \ - (R_GEN_CONFIG_II__ser3__##f4_##_VAL(R_GEN_CONFIG_II_, ser3_, v4) << R_GEN_CONFIG_II__ser3__BITNR) | \ - (R_GEN_CONFIG_II__ser2__##f5_##_VAL(R_GEN_CONFIG_II_, ser2_, v5) << R_GEN_CONFIG_II__ser2__BITNR) \ -) - -#endif - -/* - * R_IRQ_MASK0_CLR - * - type: WO - * - addr: 0xb00000c0 - * - group: Interrupt mask and status registers - */ - -#if USE_GROUP__Interrupt_mask_and_status_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_IRQ_MASK0_CLR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_IRQ_MASK0_CLR. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_IRQ_MASK0_CLR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_IRQ_MASK0_CLR(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25,f26,v26,f27,v27,f28,v28,f29,v29,f30,v30,f31,v31) ( \ - *R_IRQ_MASK0_CLR__SADDR = ( \ - REG_INITIATED(R_IRQ_MASK0_CLR_) \ - REG_VAL__R_IRQ_MASK0_CLR_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20,f21##_,v21,f22##_,v22,f23##_,v23,f24##_,v24,f25##_,v25,f26##_,v26,f27##_,v27,f28##_,v28,f29##_,v29,f30##_,v30,f31##_,v31) \ - ), \ - R_IRQ_MASK0_CLR__WRITE(R_IRQ_MASK0_CLR__ADDR, *R_IRQ_MASK0_CLR__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_IRQ_MASK0_CLR__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_IRQ_MASK0_CLR. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_IRQ_MASK0_CLR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_IRQ_MASK0_CLR__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25,f26,v26,f27,v27,f28,v28,f29,v29,f30,v30,f31,v31) ( \ - *R_IRQ_MASK0_CLR__SADDR = ( \ - REG_INITIATED(R_IRQ_MASK0_CLR_) \ - REG_VAL__R_IRQ_MASK0_CLR_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20,f21##_,v21,f22##_,v22,f23##_,v23,f24##_,v24,f25##_,v25,f26##_,v26,f27##_,v27,f28##_,v28,f29##_,v29,f30##_,v30,f31##_,v31) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_IRQ_MASK0_CLR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_IRQ_MASK0_CLR(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25,f26,v26,f27,v27,f28,v28,f29,v29,f30,v30,f31,v31) ( \ - (R_IRQ_MASK0_CLR__nmi_pin__##f1##__MASK & REG__##v1) | \ - (R_IRQ_MASK0_CLR__watchdog_nmi__##f2##__MASK & REG__##v2) | \ - (R_IRQ_MASK0_CLR__sqe_test_error__##f3##__MASK & REG__##v3) | \ - (R_IRQ_MASK0_CLR__carrier_loss__##f4##__MASK & REG__##v4) | \ - (R_IRQ_MASK0_CLR__deferred__##f5##__MASK & REG__##v5) | \ - (R_IRQ_MASK0_CLR__late_col__##f6##__MASK & REG__##v6) | \ - (R_IRQ_MASK0_CLR__multiple_col__##f7##__MASK & REG__##v7) | \ - (R_IRQ_MASK0_CLR__single_col__##f8##__MASK & REG__##v8) | \ - (R_IRQ_MASK0_CLR__congestion__##f9##__MASK & REG__##v9) | \ - (R_IRQ_MASK0_CLR__oversize__##f10##__MASK & REG__##v10) | \ - (R_IRQ_MASK0_CLR__alignment_error__##f11##__MASK & REG__##v11) | \ - (R_IRQ_MASK0_CLR__crc_error__##f12##__MASK & REG__##v12) | \ - (R_IRQ_MASK0_CLR__overrun__##f13##__MASK & REG__##v13) | \ - (R_IRQ_MASK0_CLR__underrun__##f14##__MASK & REG__##v14) | \ - (R_IRQ_MASK0_CLR__excessive_col__##f15##__MASK & REG__##v15) | \ - (R_IRQ_MASK0_CLR__mdio__##f16##__MASK & REG__##v16) | \ - (R_IRQ_MASK0_CLR__ata_drq3__##f17##__MASK & REG__##v17) | \ - (R_IRQ_MASK0_CLR__ata_drq2__##f18##__MASK & REG__##v18) | \ - (R_IRQ_MASK0_CLR__ata_drq1__##f19##__MASK & REG__##v19) | \ - (R_IRQ_MASK0_CLR__ata_drq0__##f20##__MASK & REG__##v20) | \ - (R_IRQ_MASK0_CLR__par0_ecp_cmd__##f21##__MASK & REG__##v21) | \ - (R_IRQ_MASK0_CLR__par0_peri__##f22##__MASK & REG__##v22) | \ - (R_IRQ_MASK0_CLR__par0_data__##f23##__MASK & REG__##v23) | \ - (R_IRQ_MASK0_CLR__par0_ready__##f24##__MASK & REG__##v24) | \ - (R_IRQ_MASK0_CLR__ata_dmaend__##f25##__MASK & REG__##v25) | \ - (R_IRQ_MASK0_CLR__irq_ext_vector_nr__##f26##__MASK & REG__##v26) | \ - (R_IRQ_MASK0_CLR__irq_int_vector_nr__##f27##__MASK & REG__##v27) | \ - (R_IRQ_MASK0_CLR__ext_dma1__##f28##__MASK & REG__##v28) | \ - (R_IRQ_MASK0_CLR__ext_dma0__##f29##__MASK & REG__##v29) | \ - (R_IRQ_MASK0_CLR__timer1__##f30##__MASK & REG__##v30) | \ - (R_IRQ_MASK0_CLR__timer0__##f31##__MASK & REG__##v31) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_IRQ_MASK0_CLR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_IRQ_MASK0_CLR. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_IRQ_MASK0_CLR(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25,f26,v26,f27,v27,f28,v28,f29,v29,f30,v30,f31,v31) ( \ - (R_IRQ_MASK0_CLR__nmi_pin__##f1##__VAL(R_IRQ_MASK0_CLR_, nmi_pin_, v1) << R_IRQ_MASK0_CLR__nmi_pin__BITNR) | \ - (R_IRQ_MASK0_CLR__watchdog_nmi__##f2##__VAL(R_IRQ_MASK0_CLR_, watchdog_nmi_, v2) << R_IRQ_MASK0_CLR__watchdog_nmi__BITNR) | \ - (R_IRQ_MASK0_CLR__sqe_test_error__##f3##__VAL(R_IRQ_MASK0_CLR_, sqe_test_error_, v3) << R_IRQ_MASK0_CLR__sqe_test_error__BITNR) | \ - (R_IRQ_MASK0_CLR__carrier_loss__##f4##__VAL(R_IRQ_MASK0_CLR_, carrier_loss_, v4) << R_IRQ_MASK0_CLR__carrier_loss__BITNR) | \ - (R_IRQ_MASK0_CLR__deferred__##f5##__VAL(R_IRQ_MASK0_CLR_, deferred_, v5) << R_IRQ_MASK0_CLR__deferred__BITNR) | \ - (R_IRQ_MASK0_CLR__late_col__##f6##__VAL(R_IRQ_MASK0_CLR_, late_col_, v6) << R_IRQ_MASK0_CLR__late_col__BITNR) | \ - (R_IRQ_MASK0_CLR__multiple_col__##f7##__VAL(R_IRQ_MASK0_CLR_, multiple_col_, v7) << R_IRQ_MASK0_CLR__multiple_col__BITNR) | \ - (R_IRQ_MASK0_CLR__single_col__##f8##__VAL(R_IRQ_MASK0_CLR_, single_col_, v8) << R_IRQ_MASK0_CLR__single_col__BITNR) | \ - (R_IRQ_MASK0_CLR__congestion__##f9##__VAL(R_IRQ_MASK0_CLR_, congestion_, v9) << R_IRQ_MASK0_CLR__congestion__BITNR) | \ - (R_IRQ_MASK0_CLR__oversize__##f10##__VAL(R_IRQ_MASK0_CLR_, oversize_, v10) << R_IRQ_MASK0_CLR__oversize__BITNR) | \ - (R_IRQ_MASK0_CLR__alignment_error__##f11##__VAL(R_IRQ_MASK0_CLR_, alignment_error_, v11) << R_IRQ_MASK0_CLR__alignment_error__BITNR) | \ - (R_IRQ_MASK0_CLR__crc_error__##f12##__VAL(R_IRQ_MASK0_CLR_, crc_error_, v12) << R_IRQ_MASK0_CLR__crc_error__BITNR) | \ - (R_IRQ_MASK0_CLR__overrun__##f13##__VAL(R_IRQ_MASK0_CLR_, overrun_, v13) << R_IRQ_MASK0_CLR__overrun__BITNR) | \ - (R_IRQ_MASK0_CLR__underrun__##f14##__VAL(R_IRQ_MASK0_CLR_, underrun_, v14) << R_IRQ_MASK0_CLR__underrun__BITNR) | \ - (R_IRQ_MASK0_CLR__excessive_col__##f15##__VAL(R_IRQ_MASK0_CLR_, excessive_col_, v15) << R_IRQ_MASK0_CLR__excessive_col__BITNR) | \ - (R_IRQ_MASK0_CLR__mdio__##f16##__VAL(R_IRQ_MASK0_CLR_, mdio_, v16) << R_IRQ_MASK0_CLR__mdio__BITNR) | \ - (R_IRQ_MASK0_CLR__ata_drq3__##f17##__VAL(R_IRQ_MASK0_CLR_, ata_drq3_, v17) << R_IRQ_MASK0_CLR__ata_drq3__BITNR) | \ - (R_IRQ_MASK0_CLR__ata_drq2__##f18##__VAL(R_IRQ_MASK0_CLR_, ata_drq2_, v18) << R_IRQ_MASK0_CLR__ata_drq2__BITNR) | \ - (R_IRQ_MASK0_CLR__ata_drq1__##f19##__VAL(R_IRQ_MASK0_CLR_, ata_drq1_, v19) << R_IRQ_MASK0_CLR__ata_drq1__BITNR) | \ - (R_IRQ_MASK0_CLR__ata_drq0__##f20##__VAL(R_IRQ_MASK0_CLR_, ata_drq0_, v20) << R_IRQ_MASK0_CLR__ata_drq0__BITNR) | \ - (R_IRQ_MASK0_CLR__par0_ecp_cmd__##f21##__VAL(R_IRQ_MASK0_CLR_, par0_ecp_cmd_, v21) << R_IRQ_MASK0_CLR__par0_ecp_cmd__BITNR) | \ - (R_IRQ_MASK0_CLR__par0_peri__##f22##__VAL(R_IRQ_MASK0_CLR_, par0_peri_, v22) << R_IRQ_MASK0_CLR__par0_peri__BITNR) | \ - (R_IRQ_MASK0_CLR__par0_data__##f23##__VAL(R_IRQ_MASK0_CLR_, par0_data_, v23) << R_IRQ_MASK0_CLR__par0_data__BITNR) | \ - (R_IRQ_MASK0_CLR__par0_ready__##f24##__VAL(R_IRQ_MASK0_CLR_, par0_ready_, v24) << R_IRQ_MASK0_CLR__par0_ready__BITNR) | \ - (R_IRQ_MASK0_CLR__ata_dmaend__##f25##__VAL(R_IRQ_MASK0_CLR_, ata_dmaend_, v25) << R_IRQ_MASK0_CLR__ata_dmaend__BITNR) | \ - (R_IRQ_MASK0_CLR__irq_ext_vector_nr__##f26##__VAL(R_IRQ_MASK0_CLR_, irq_ext_vector_nr_, v26) << R_IRQ_MASK0_CLR__irq_ext_vector_nr__BITNR) | \ - (R_IRQ_MASK0_CLR__irq_int_vector_nr__##f27##__VAL(R_IRQ_MASK0_CLR_, irq_int_vector_nr_, v27) << R_IRQ_MASK0_CLR__irq_int_vector_nr__BITNR) | \ - (R_IRQ_MASK0_CLR__ext_dma1__##f28##__VAL(R_IRQ_MASK0_CLR_, ext_dma1_, v28) << R_IRQ_MASK0_CLR__ext_dma1__BITNR) | \ - (R_IRQ_MASK0_CLR__ext_dma0__##f29##__VAL(R_IRQ_MASK0_CLR_, ext_dma0_, v29) << R_IRQ_MASK0_CLR__ext_dma0__BITNR) | \ - (R_IRQ_MASK0_CLR__timer1__##f30##__VAL(R_IRQ_MASK0_CLR_, timer1_, v30) << R_IRQ_MASK0_CLR__timer1__BITNR) | \ - (R_IRQ_MASK0_CLR__timer0__##f31##__VAL(R_IRQ_MASK0_CLR_, timer0_, v31) << R_IRQ_MASK0_CLR__timer0__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_IRQ_MASK0_CLR_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_IRQ_MASK0_CLR. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_IRQ_MASK0_CLR_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16,f17_,v17,f18_,v18,f19_,v19,f20_,v20,f21_,v21,f22_,v22,f23_,v23,f24_,v24,f25_,v25,f26_,v26,f27_,v27,f28_,v28,f29_,v29,f30_,v30,f31_,v31) ( \ - (R_IRQ_MASK0_CLR__nmi_pin__##f1_##_VAL(R_IRQ_MASK0_CLR_, nmi_pin_, v1) << R_IRQ_MASK0_CLR__nmi_pin__BITNR) | \ - (R_IRQ_MASK0_CLR__watchdog_nmi__##f2_##_VAL(R_IRQ_MASK0_CLR_, watchdog_nmi_, v2) << R_IRQ_MASK0_CLR__watchdog_nmi__BITNR) | \ - (R_IRQ_MASK0_CLR__sqe_test_error__##f3_##_VAL(R_IRQ_MASK0_CLR_, sqe_test_error_, v3) << R_IRQ_MASK0_CLR__sqe_test_error__BITNR) | \ - (R_IRQ_MASK0_CLR__carrier_loss__##f4_##_VAL(R_IRQ_MASK0_CLR_, carrier_loss_, v4) << R_IRQ_MASK0_CLR__carrier_loss__BITNR) | \ - (R_IRQ_MASK0_CLR__deferred__##f5_##_VAL(R_IRQ_MASK0_CLR_, deferred_, v5) << R_IRQ_MASK0_CLR__deferred__BITNR) | \ - (R_IRQ_MASK0_CLR__late_col__##f6_##_VAL(R_IRQ_MASK0_CLR_, late_col_, v6) << R_IRQ_MASK0_CLR__late_col__BITNR) | \ - (R_IRQ_MASK0_CLR__multiple_col__##f7_##_VAL(R_IRQ_MASK0_CLR_, multiple_col_, v7) << R_IRQ_MASK0_CLR__multiple_col__BITNR) | \ - (R_IRQ_MASK0_CLR__single_col__##f8_##_VAL(R_IRQ_MASK0_CLR_, single_col_, v8) << R_IRQ_MASK0_CLR__single_col__BITNR) | \ - (R_IRQ_MASK0_CLR__congestion__##f9_##_VAL(R_IRQ_MASK0_CLR_, congestion_, v9) << R_IRQ_MASK0_CLR__congestion__BITNR) | \ - (R_IRQ_MASK0_CLR__oversize__##f10_##_VAL(R_IRQ_MASK0_CLR_, oversize_, v10) << R_IRQ_MASK0_CLR__oversize__BITNR) | \ - (R_IRQ_MASK0_CLR__alignment_error__##f11_##_VAL(R_IRQ_MASK0_CLR_, alignment_error_, v11) << R_IRQ_MASK0_CLR__alignment_error__BITNR) | \ - (R_IRQ_MASK0_CLR__crc_error__##f12_##_VAL(R_IRQ_MASK0_CLR_, crc_error_, v12) << R_IRQ_MASK0_CLR__crc_error__BITNR) | \ - (R_IRQ_MASK0_CLR__overrun__##f13_##_VAL(R_IRQ_MASK0_CLR_, overrun_, v13) << R_IRQ_MASK0_CLR__overrun__BITNR) | \ - (R_IRQ_MASK0_CLR__underrun__##f14_##_VAL(R_IRQ_MASK0_CLR_, underrun_, v14) << R_IRQ_MASK0_CLR__underrun__BITNR) | \ - (R_IRQ_MASK0_CLR__excessive_col__##f15_##_VAL(R_IRQ_MASK0_CLR_, excessive_col_, v15) << R_IRQ_MASK0_CLR__excessive_col__BITNR) | \ - (R_IRQ_MASK0_CLR__mdio__##f16_##_VAL(R_IRQ_MASK0_CLR_, mdio_, v16) << R_IRQ_MASK0_CLR__mdio__BITNR) | \ - (R_IRQ_MASK0_CLR__ata_drq3__##f17_##_VAL(R_IRQ_MASK0_CLR_, ata_drq3_, v17) << R_IRQ_MASK0_CLR__ata_drq3__BITNR) | \ - (R_IRQ_MASK0_CLR__ata_drq2__##f18_##_VAL(R_IRQ_MASK0_CLR_, ata_drq2_, v18) << R_IRQ_MASK0_CLR__ata_drq2__BITNR) | \ - (R_IRQ_MASK0_CLR__ata_drq1__##f19_##_VAL(R_IRQ_MASK0_CLR_, ata_drq1_, v19) << R_IRQ_MASK0_CLR__ata_drq1__BITNR) | \ - (R_IRQ_MASK0_CLR__ata_drq0__##f20_##_VAL(R_IRQ_MASK0_CLR_, ata_drq0_, v20) << R_IRQ_MASK0_CLR__ata_drq0__BITNR) | \ - (R_IRQ_MASK0_CLR__par0_ecp_cmd__##f21_##_VAL(R_IRQ_MASK0_CLR_, par0_ecp_cmd_, v21) << R_IRQ_MASK0_CLR__par0_ecp_cmd__BITNR) | \ - (R_IRQ_MASK0_CLR__par0_peri__##f22_##_VAL(R_IRQ_MASK0_CLR_, par0_peri_, v22) << R_IRQ_MASK0_CLR__par0_peri__BITNR) | \ - (R_IRQ_MASK0_CLR__par0_data__##f23_##_VAL(R_IRQ_MASK0_CLR_, par0_data_, v23) << R_IRQ_MASK0_CLR__par0_data__BITNR) | \ - (R_IRQ_MASK0_CLR__par0_ready__##f24_##_VAL(R_IRQ_MASK0_CLR_, par0_ready_, v24) << R_IRQ_MASK0_CLR__par0_ready__BITNR) | \ - (R_IRQ_MASK0_CLR__ata_dmaend__##f25_##_VAL(R_IRQ_MASK0_CLR_, ata_dmaend_, v25) << R_IRQ_MASK0_CLR__ata_dmaend__BITNR) | \ - (R_IRQ_MASK0_CLR__irq_ext_vector_nr__##f26_##_VAL(R_IRQ_MASK0_CLR_, irq_ext_vector_nr_, v26) << R_IRQ_MASK0_CLR__irq_ext_vector_nr__BITNR) | \ - (R_IRQ_MASK0_CLR__irq_int_vector_nr__##f27_##_VAL(R_IRQ_MASK0_CLR_, irq_int_vector_nr_, v27) << R_IRQ_MASK0_CLR__irq_int_vector_nr__BITNR) | \ - (R_IRQ_MASK0_CLR__ext_dma1__##f28_##_VAL(R_IRQ_MASK0_CLR_, ext_dma1_, v28) << R_IRQ_MASK0_CLR__ext_dma1__BITNR) | \ - (R_IRQ_MASK0_CLR__ext_dma0__##f29_##_VAL(R_IRQ_MASK0_CLR_, ext_dma0_, v29) << R_IRQ_MASK0_CLR__ext_dma0__BITNR) | \ - (R_IRQ_MASK0_CLR__timer1__##f30_##_VAL(R_IRQ_MASK0_CLR_, timer1_, v30) << R_IRQ_MASK0_CLR__timer1__BITNR) | \ - (R_IRQ_MASK0_CLR__timer0__##f31_##_VAL(R_IRQ_MASK0_CLR_, timer0_, v31) << R_IRQ_MASK0_CLR__timer0__BITNR) \ -) - -#endif - -/* - * R_IRQ_MASK0_RD - * - type: RO - * - addr: 0xb00000c0 - * - group: Interrupt mask and status registers - */ - -#if USE_GROUP__Interrupt_mask_and_status_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_IRQ_MASK0_RD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_IRQ_MASK0_RD(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25,f26,v26,f27,v27,f28,v28,f29,v29,f30,v30,f31,v31) ( \ - (R_IRQ_MASK0_RD__nmi_pin__##f1##__MASK & REG__##v1) | \ - (R_IRQ_MASK0_RD__watchdog_nmi__##f2##__MASK & REG__##v2) | \ - (R_IRQ_MASK0_RD__sqe_test_error__##f3##__MASK & REG__##v3) | \ - (R_IRQ_MASK0_RD__carrier_loss__##f4##__MASK & REG__##v4) | \ - (R_IRQ_MASK0_RD__deferred__##f5##__MASK & REG__##v5) | \ - (R_IRQ_MASK0_RD__late_col__##f6##__MASK & REG__##v6) | \ - (R_IRQ_MASK0_RD__multiple_col__##f7##__MASK & REG__##v7) | \ - (R_IRQ_MASK0_RD__single_col__##f8##__MASK & REG__##v8) | \ - (R_IRQ_MASK0_RD__congestion__##f9##__MASK & REG__##v9) | \ - (R_IRQ_MASK0_RD__oversize__##f10##__MASK & REG__##v10) | \ - (R_IRQ_MASK0_RD__alignment_error__##f11##__MASK & REG__##v11) | \ - (R_IRQ_MASK0_RD__crc_error__##f12##__MASK & REG__##v12) | \ - (R_IRQ_MASK0_RD__overrun__##f13##__MASK & REG__##v13) | \ - (R_IRQ_MASK0_RD__underrun__##f14##__MASK & REG__##v14) | \ - (R_IRQ_MASK0_RD__excessive_col__##f15##__MASK & REG__##v15) | \ - (R_IRQ_MASK0_RD__mdio__##f16##__MASK & REG__##v16) | \ - (R_IRQ_MASK0_RD__ata_drq3__##f17##__MASK & REG__##v17) | \ - (R_IRQ_MASK0_RD__ata_drq2__##f18##__MASK & REG__##v18) | \ - (R_IRQ_MASK0_RD__ata_drq1__##f19##__MASK & REG__##v19) | \ - (R_IRQ_MASK0_RD__ata_drq0__##f20##__MASK & REG__##v20) | \ - (R_IRQ_MASK0_RD__par0_ecp_cmd__##f21##__MASK & REG__##v21) | \ - (R_IRQ_MASK0_RD__par0_peri__##f22##__MASK & REG__##v22) | \ - (R_IRQ_MASK0_RD__par0_data__##f23##__MASK & REG__##v23) | \ - (R_IRQ_MASK0_RD__par0_ready__##f24##__MASK & REG__##v24) | \ - (R_IRQ_MASK0_RD__ata_dmaend__##f25##__MASK & REG__##v25) | \ - (R_IRQ_MASK0_RD__irq_ext_vector_nr__##f26##__MASK & REG__##v26) | \ - (R_IRQ_MASK0_RD__irq_int_vector_nr__##f27##__MASK & REG__##v27) | \ - (R_IRQ_MASK0_RD__ext_dma1__##f28##__MASK & REG__##v28) | \ - (R_IRQ_MASK0_RD__ext_dma0__##f29##__MASK & REG__##v29) | \ - (R_IRQ_MASK0_RD__timer1__##f30##__MASK & REG__##v30) | \ - (R_IRQ_MASK0_RD__timer0__##f31##__MASK & REG__##v31) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_IRQ_MASK0_RD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_IRQ_MASK0_RD. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_IRQ_MASK0_RD(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25,f26,v26,f27,v27,f28,v28,f29,v29,f30,v30,f31,v31) ( \ - (R_IRQ_MASK0_RD__nmi_pin__##f1##__VAL(R_IRQ_MASK0_RD_, nmi_pin_, v1) << R_IRQ_MASK0_RD__nmi_pin__BITNR) | \ - (R_IRQ_MASK0_RD__watchdog_nmi__##f2##__VAL(R_IRQ_MASK0_RD_, watchdog_nmi_, v2) << R_IRQ_MASK0_RD__watchdog_nmi__BITNR) | \ - (R_IRQ_MASK0_RD__sqe_test_error__##f3##__VAL(R_IRQ_MASK0_RD_, sqe_test_error_, v3) << R_IRQ_MASK0_RD__sqe_test_error__BITNR) | \ - (R_IRQ_MASK0_RD__carrier_loss__##f4##__VAL(R_IRQ_MASK0_RD_, carrier_loss_, v4) << R_IRQ_MASK0_RD__carrier_loss__BITNR) | \ - (R_IRQ_MASK0_RD__deferred__##f5##__VAL(R_IRQ_MASK0_RD_, deferred_, v5) << R_IRQ_MASK0_RD__deferred__BITNR) | \ - (R_IRQ_MASK0_RD__late_col__##f6##__VAL(R_IRQ_MASK0_RD_, late_col_, v6) << R_IRQ_MASK0_RD__late_col__BITNR) | \ - (R_IRQ_MASK0_RD__multiple_col__##f7##__VAL(R_IRQ_MASK0_RD_, multiple_col_, v7) << R_IRQ_MASK0_RD__multiple_col__BITNR) | \ - (R_IRQ_MASK0_RD__single_col__##f8##__VAL(R_IRQ_MASK0_RD_, single_col_, v8) << R_IRQ_MASK0_RD__single_col__BITNR) | \ - (R_IRQ_MASK0_RD__congestion__##f9##__VAL(R_IRQ_MASK0_RD_, congestion_, v9) << R_IRQ_MASK0_RD__congestion__BITNR) | \ - (R_IRQ_MASK0_RD__oversize__##f10##__VAL(R_IRQ_MASK0_RD_, oversize_, v10) << R_IRQ_MASK0_RD__oversize__BITNR) | \ - (R_IRQ_MASK0_RD__alignment_error__##f11##__VAL(R_IRQ_MASK0_RD_, alignment_error_, v11) << R_IRQ_MASK0_RD__alignment_error__BITNR) | \ - (R_IRQ_MASK0_RD__crc_error__##f12##__VAL(R_IRQ_MASK0_RD_, crc_error_, v12) << R_IRQ_MASK0_RD__crc_error__BITNR) | \ - (R_IRQ_MASK0_RD__overrun__##f13##__VAL(R_IRQ_MASK0_RD_, overrun_, v13) << R_IRQ_MASK0_RD__overrun__BITNR) | \ - (R_IRQ_MASK0_RD__underrun__##f14##__VAL(R_IRQ_MASK0_RD_, underrun_, v14) << R_IRQ_MASK0_RD__underrun__BITNR) | \ - (R_IRQ_MASK0_RD__excessive_col__##f15##__VAL(R_IRQ_MASK0_RD_, excessive_col_, v15) << R_IRQ_MASK0_RD__excessive_col__BITNR) | \ - (R_IRQ_MASK0_RD__mdio__##f16##__VAL(R_IRQ_MASK0_RD_, mdio_, v16) << R_IRQ_MASK0_RD__mdio__BITNR) | \ - (R_IRQ_MASK0_RD__ata_drq3__##f17##__VAL(R_IRQ_MASK0_RD_, ata_drq3_, v17) << R_IRQ_MASK0_RD__ata_drq3__BITNR) | \ - (R_IRQ_MASK0_RD__ata_drq2__##f18##__VAL(R_IRQ_MASK0_RD_, ata_drq2_, v18) << R_IRQ_MASK0_RD__ata_drq2__BITNR) | \ - (R_IRQ_MASK0_RD__ata_drq1__##f19##__VAL(R_IRQ_MASK0_RD_, ata_drq1_, v19) << R_IRQ_MASK0_RD__ata_drq1__BITNR) | \ - (R_IRQ_MASK0_RD__ata_drq0__##f20##__VAL(R_IRQ_MASK0_RD_, ata_drq0_, v20) << R_IRQ_MASK0_RD__ata_drq0__BITNR) | \ - (R_IRQ_MASK0_RD__par0_ecp_cmd__##f21##__VAL(R_IRQ_MASK0_RD_, par0_ecp_cmd_, v21) << R_IRQ_MASK0_RD__par0_ecp_cmd__BITNR) | \ - (R_IRQ_MASK0_RD__par0_peri__##f22##__VAL(R_IRQ_MASK0_RD_, par0_peri_, v22) << R_IRQ_MASK0_RD__par0_peri__BITNR) | \ - (R_IRQ_MASK0_RD__par0_data__##f23##__VAL(R_IRQ_MASK0_RD_, par0_data_, v23) << R_IRQ_MASK0_RD__par0_data__BITNR) | \ - (R_IRQ_MASK0_RD__par0_ready__##f24##__VAL(R_IRQ_MASK0_RD_, par0_ready_, v24) << R_IRQ_MASK0_RD__par0_ready__BITNR) | \ - (R_IRQ_MASK0_RD__ata_dmaend__##f25##__VAL(R_IRQ_MASK0_RD_, ata_dmaend_, v25) << R_IRQ_MASK0_RD__ata_dmaend__BITNR) | \ - (R_IRQ_MASK0_RD__irq_ext_vector_nr__##f26##__VAL(R_IRQ_MASK0_RD_, irq_ext_vector_nr_, v26) << R_IRQ_MASK0_RD__irq_ext_vector_nr__BITNR) | \ - (R_IRQ_MASK0_RD__irq_int_vector_nr__##f27##__VAL(R_IRQ_MASK0_RD_, irq_int_vector_nr_, v27) << R_IRQ_MASK0_RD__irq_int_vector_nr__BITNR) | \ - (R_IRQ_MASK0_RD__ext_dma1__##f28##__VAL(R_IRQ_MASK0_RD_, ext_dma1_, v28) << R_IRQ_MASK0_RD__ext_dma1__BITNR) | \ - (R_IRQ_MASK0_RD__ext_dma0__##f29##__VAL(R_IRQ_MASK0_RD_, ext_dma0_, v29) << R_IRQ_MASK0_RD__ext_dma0__BITNR) | \ - (R_IRQ_MASK0_RD__timer1__##f30##__VAL(R_IRQ_MASK0_RD_, timer1_, v30) << R_IRQ_MASK0_RD__timer1__BITNR) | \ - (R_IRQ_MASK0_RD__timer0__##f31##__VAL(R_IRQ_MASK0_RD_, timer0_, v31) << R_IRQ_MASK0_RD__timer0__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_IRQ_MASK0_RD_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_IRQ_MASK0_RD. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_IRQ_MASK0_RD_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16,f17_,v17,f18_,v18,f19_,v19,f20_,v20,f21_,v21,f22_,v22,f23_,v23,f24_,v24,f25_,v25,f26_,v26,f27_,v27,f28_,v28,f29_,v29,f30_,v30,f31_,v31) ( \ - (R_IRQ_MASK0_RD__nmi_pin__##f1_##_VAL(R_IRQ_MASK0_RD_, nmi_pin_, v1) << R_IRQ_MASK0_RD__nmi_pin__BITNR) | \ - (R_IRQ_MASK0_RD__watchdog_nmi__##f2_##_VAL(R_IRQ_MASK0_RD_, watchdog_nmi_, v2) << R_IRQ_MASK0_RD__watchdog_nmi__BITNR) | \ - (R_IRQ_MASK0_RD__sqe_test_error__##f3_##_VAL(R_IRQ_MASK0_RD_, sqe_test_error_, v3) << R_IRQ_MASK0_RD__sqe_test_error__BITNR) | \ - (R_IRQ_MASK0_RD__carrier_loss__##f4_##_VAL(R_IRQ_MASK0_RD_, carrier_loss_, v4) << R_IRQ_MASK0_RD__carrier_loss__BITNR) | \ - (R_IRQ_MASK0_RD__deferred__##f5_##_VAL(R_IRQ_MASK0_RD_, deferred_, v5) << R_IRQ_MASK0_RD__deferred__BITNR) | \ - (R_IRQ_MASK0_RD__late_col__##f6_##_VAL(R_IRQ_MASK0_RD_, late_col_, v6) << R_IRQ_MASK0_RD__late_col__BITNR) | \ - (R_IRQ_MASK0_RD__multiple_col__##f7_##_VAL(R_IRQ_MASK0_RD_, multiple_col_, v7) << R_IRQ_MASK0_RD__multiple_col__BITNR) | \ - (R_IRQ_MASK0_RD__single_col__##f8_##_VAL(R_IRQ_MASK0_RD_, single_col_, v8) << R_IRQ_MASK0_RD__single_col__BITNR) | \ - (R_IRQ_MASK0_RD__congestion__##f9_##_VAL(R_IRQ_MASK0_RD_, congestion_, v9) << R_IRQ_MASK0_RD__congestion__BITNR) | \ - (R_IRQ_MASK0_RD__oversize__##f10_##_VAL(R_IRQ_MASK0_RD_, oversize_, v10) << R_IRQ_MASK0_RD__oversize__BITNR) | \ - (R_IRQ_MASK0_RD__alignment_error__##f11_##_VAL(R_IRQ_MASK0_RD_, alignment_error_, v11) << R_IRQ_MASK0_RD__alignment_error__BITNR) | \ - (R_IRQ_MASK0_RD__crc_error__##f12_##_VAL(R_IRQ_MASK0_RD_, crc_error_, v12) << R_IRQ_MASK0_RD__crc_error__BITNR) | \ - (R_IRQ_MASK0_RD__overrun__##f13_##_VAL(R_IRQ_MASK0_RD_, overrun_, v13) << R_IRQ_MASK0_RD__overrun__BITNR) | \ - (R_IRQ_MASK0_RD__underrun__##f14_##_VAL(R_IRQ_MASK0_RD_, underrun_, v14) << R_IRQ_MASK0_RD__underrun__BITNR) | \ - (R_IRQ_MASK0_RD__excessive_col__##f15_##_VAL(R_IRQ_MASK0_RD_, excessive_col_, v15) << R_IRQ_MASK0_RD__excessive_col__BITNR) | \ - (R_IRQ_MASK0_RD__mdio__##f16_##_VAL(R_IRQ_MASK0_RD_, mdio_, v16) << R_IRQ_MASK0_RD__mdio__BITNR) | \ - (R_IRQ_MASK0_RD__ata_drq3__##f17_##_VAL(R_IRQ_MASK0_RD_, ata_drq3_, v17) << R_IRQ_MASK0_RD__ata_drq3__BITNR) | \ - (R_IRQ_MASK0_RD__ata_drq2__##f18_##_VAL(R_IRQ_MASK0_RD_, ata_drq2_, v18) << R_IRQ_MASK0_RD__ata_drq2__BITNR) | \ - (R_IRQ_MASK0_RD__ata_drq1__##f19_##_VAL(R_IRQ_MASK0_RD_, ata_drq1_, v19) << R_IRQ_MASK0_RD__ata_drq1__BITNR) | \ - (R_IRQ_MASK0_RD__ata_drq0__##f20_##_VAL(R_IRQ_MASK0_RD_, ata_drq0_, v20) << R_IRQ_MASK0_RD__ata_drq0__BITNR) | \ - (R_IRQ_MASK0_RD__par0_ecp_cmd__##f21_##_VAL(R_IRQ_MASK0_RD_, par0_ecp_cmd_, v21) << R_IRQ_MASK0_RD__par0_ecp_cmd__BITNR) | \ - (R_IRQ_MASK0_RD__par0_peri__##f22_##_VAL(R_IRQ_MASK0_RD_, par0_peri_, v22) << R_IRQ_MASK0_RD__par0_peri__BITNR) | \ - (R_IRQ_MASK0_RD__par0_data__##f23_##_VAL(R_IRQ_MASK0_RD_, par0_data_, v23) << R_IRQ_MASK0_RD__par0_data__BITNR) | \ - (R_IRQ_MASK0_RD__par0_ready__##f24_##_VAL(R_IRQ_MASK0_RD_, par0_ready_, v24) << R_IRQ_MASK0_RD__par0_ready__BITNR) | \ - (R_IRQ_MASK0_RD__ata_dmaend__##f25_##_VAL(R_IRQ_MASK0_RD_, ata_dmaend_, v25) << R_IRQ_MASK0_RD__ata_dmaend__BITNR) | \ - (R_IRQ_MASK0_RD__irq_ext_vector_nr__##f26_##_VAL(R_IRQ_MASK0_RD_, irq_ext_vector_nr_, v26) << R_IRQ_MASK0_RD__irq_ext_vector_nr__BITNR) | \ - (R_IRQ_MASK0_RD__irq_int_vector_nr__##f27_##_VAL(R_IRQ_MASK0_RD_, irq_int_vector_nr_, v27) << R_IRQ_MASK0_RD__irq_int_vector_nr__BITNR) | \ - (R_IRQ_MASK0_RD__ext_dma1__##f28_##_VAL(R_IRQ_MASK0_RD_, ext_dma1_, v28) << R_IRQ_MASK0_RD__ext_dma1__BITNR) | \ - (R_IRQ_MASK0_RD__ext_dma0__##f29_##_VAL(R_IRQ_MASK0_RD_, ext_dma0_, v29) << R_IRQ_MASK0_RD__ext_dma0__BITNR) | \ - (R_IRQ_MASK0_RD__timer1__##f30_##_VAL(R_IRQ_MASK0_RD_, timer1_, v30) << R_IRQ_MASK0_RD__timer1__BITNR) | \ - (R_IRQ_MASK0_RD__timer0__##f31_##_VAL(R_IRQ_MASK0_RD_, timer0_, v31) << R_IRQ_MASK0_RD__timer0__BITNR) \ -) - -#endif - -/* - * R_IRQ_MASK0_SET - * - type: WO - * - addr: 0xb00000c4 - * - group: Interrupt mask and status registers - */ - -#if USE_GROUP__Interrupt_mask_and_status_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_IRQ_MASK0_SET -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_IRQ_MASK0_SET. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_IRQ_MASK0_SET. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_IRQ_MASK0_SET(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25,f26,v26,f27,v27,f28,v28,f29,v29,f30,v30,f31,v31) ( \ - *R_IRQ_MASK0_SET__SADDR = ( \ - REG_INITIATED(R_IRQ_MASK0_SET_) \ - REG_VAL__R_IRQ_MASK0_SET_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20,f21##_,v21,f22##_,v22,f23##_,v23,f24##_,v24,f25##_,v25,f26##_,v26,f27##_,v27,f28##_,v28,f29##_,v29,f30##_,v30,f31##_,v31) \ - ), \ - R_IRQ_MASK0_SET__WRITE(R_IRQ_MASK0_SET__ADDR, *R_IRQ_MASK0_SET__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_IRQ_MASK0_SET__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_IRQ_MASK0_SET. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_IRQ_MASK0_SET. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_IRQ_MASK0_SET__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25,f26,v26,f27,v27,f28,v28,f29,v29,f30,v30,f31,v31) ( \ - *R_IRQ_MASK0_SET__SADDR = ( \ - REG_INITIATED(R_IRQ_MASK0_SET_) \ - REG_VAL__R_IRQ_MASK0_SET_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20,f21##_,v21,f22##_,v22,f23##_,v23,f24##_,v24,f25##_,v25,f26##_,v26,f27##_,v27,f28##_,v28,f29##_,v29,f30##_,v30,f31##_,v31) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_IRQ_MASK0_SET -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_IRQ_MASK0_SET(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25,f26,v26,f27,v27,f28,v28,f29,v29,f30,v30,f31,v31) ( \ - (R_IRQ_MASK0_SET__nmi_pin__##f1##__MASK & REG__##v1) | \ - (R_IRQ_MASK0_SET__watchdog_nmi__##f2##__MASK & REG__##v2) | \ - (R_IRQ_MASK0_SET__sqe_test_error__##f3##__MASK & REG__##v3) | \ - (R_IRQ_MASK0_SET__carrier_loss__##f4##__MASK & REG__##v4) | \ - (R_IRQ_MASK0_SET__deferred__##f5##__MASK & REG__##v5) | \ - (R_IRQ_MASK0_SET__late_col__##f6##__MASK & REG__##v6) | \ - (R_IRQ_MASK0_SET__multiple_col__##f7##__MASK & REG__##v7) | \ - (R_IRQ_MASK0_SET__single_col__##f8##__MASK & REG__##v8) | \ - (R_IRQ_MASK0_SET__congestion__##f9##__MASK & REG__##v9) | \ - (R_IRQ_MASK0_SET__oversize__##f10##__MASK & REG__##v10) | \ - (R_IRQ_MASK0_SET__alignment_error__##f11##__MASK & REG__##v11) | \ - (R_IRQ_MASK0_SET__crc_error__##f12##__MASK & REG__##v12) | \ - (R_IRQ_MASK0_SET__overrun__##f13##__MASK & REG__##v13) | \ - (R_IRQ_MASK0_SET__underrun__##f14##__MASK & REG__##v14) | \ - (R_IRQ_MASK0_SET__excessive_col__##f15##__MASK & REG__##v15) | \ - (R_IRQ_MASK0_SET__mdio__##f16##__MASK & REG__##v16) | \ - (R_IRQ_MASK0_SET__ata_drq3__##f17##__MASK & REG__##v17) | \ - (R_IRQ_MASK0_SET__ata_drq2__##f18##__MASK & REG__##v18) | \ - (R_IRQ_MASK0_SET__ata_drq1__##f19##__MASK & REG__##v19) | \ - (R_IRQ_MASK0_SET__ata_drq0__##f20##__MASK & REG__##v20) | \ - (R_IRQ_MASK0_SET__par0_ecp_cmd__##f21##__MASK & REG__##v21) | \ - (R_IRQ_MASK0_SET__par0_peri__##f22##__MASK & REG__##v22) | \ - (R_IRQ_MASK0_SET__par0_data__##f23##__MASK & REG__##v23) | \ - (R_IRQ_MASK0_SET__par0_ready__##f24##__MASK & REG__##v24) | \ - (R_IRQ_MASK0_SET__ata_dmaend__##f25##__MASK & REG__##v25) | \ - (R_IRQ_MASK0_SET__irq_ext_vector_nr__##f26##__MASK & REG__##v26) | \ - (R_IRQ_MASK0_SET__irq_int_vector_nr__##f27##__MASK & REG__##v27) | \ - (R_IRQ_MASK0_SET__ext_dma1__##f28##__MASK & REG__##v28) | \ - (R_IRQ_MASK0_SET__ext_dma0__##f29##__MASK & REG__##v29) | \ - (R_IRQ_MASK0_SET__timer1__##f30##__MASK & REG__##v30) | \ - (R_IRQ_MASK0_SET__timer0__##f31##__MASK & REG__##v31) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_IRQ_MASK0_SET -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_IRQ_MASK0_SET. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_IRQ_MASK0_SET(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25,f26,v26,f27,v27,f28,v28,f29,v29,f30,v30,f31,v31) ( \ - (R_IRQ_MASK0_SET__nmi_pin__##f1##__VAL(R_IRQ_MASK0_SET_, nmi_pin_, v1) << R_IRQ_MASK0_SET__nmi_pin__BITNR) | \ - (R_IRQ_MASK0_SET__watchdog_nmi__##f2##__VAL(R_IRQ_MASK0_SET_, watchdog_nmi_, v2) << R_IRQ_MASK0_SET__watchdog_nmi__BITNR) | \ - (R_IRQ_MASK0_SET__sqe_test_error__##f3##__VAL(R_IRQ_MASK0_SET_, sqe_test_error_, v3) << R_IRQ_MASK0_SET__sqe_test_error__BITNR) | \ - (R_IRQ_MASK0_SET__carrier_loss__##f4##__VAL(R_IRQ_MASK0_SET_, carrier_loss_, v4) << R_IRQ_MASK0_SET__carrier_loss__BITNR) | \ - (R_IRQ_MASK0_SET__deferred__##f5##__VAL(R_IRQ_MASK0_SET_, deferred_, v5) << R_IRQ_MASK0_SET__deferred__BITNR) | \ - (R_IRQ_MASK0_SET__late_col__##f6##__VAL(R_IRQ_MASK0_SET_, late_col_, v6) << R_IRQ_MASK0_SET__late_col__BITNR) | \ - (R_IRQ_MASK0_SET__multiple_col__##f7##__VAL(R_IRQ_MASK0_SET_, multiple_col_, v7) << R_IRQ_MASK0_SET__multiple_col__BITNR) | \ - (R_IRQ_MASK0_SET__single_col__##f8##__VAL(R_IRQ_MASK0_SET_, single_col_, v8) << R_IRQ_MASK0_SET__single_col__BITNR) | \ - (R_IRQ_MASK0_SET__congestion__##f9##__VAL(R_IRQ_MASK0_SET_, congestion_, v9) << R_IRQ_MASK0_SET__congestion__BITNR) | \ - (R_IRQ_MASK0_SET__oversize__##f10##__VAL(R_IRQ_MASK0_SET_, oversize_, v10) << R_IRQ_MASK0_SET__oversize__BITNR) | \ - (R_IRQ_MASK0_SET__alignment_error__##f11##__VAL(R_IRQ_MASK0_SET_, alignment_error_, v11) << R_IRQ_MASK0_SET__alignment_error__BITNR) | \ - (R_IRQ_MASK0_SET__crc_error__##f12##__VAL(R_IRQ_MASK0_SET_, crc_error_, v12) << R_IRQ_MASK0_SET__crc_error__BITNR) | \ - (R_IRQ_MASK0_SET__overrun__##f13##__VAL(R_IRQ_MASK0_SET_, overrun_, v13) << R_IRQ_MASK0_SET__overrun__BITNR) | \ - (R_IRQ_MASK0_SET__underrun__##f14##__VAL(R_IRQ_MASK0_SET_, underrun_, v14) << R_IRQ_MASK0_SET__underrun__BITNR) | \ - (R_IRQ_MASK0_SET__excessive_col__##f15##__VAL(R_IRQ_MASK0_SET_, excessive_col_, v15) << R_IRQ_MASK0_SET__excessive_col__BITNR) | \ - (R_IRQ_MASK0_SET__mdio__##f16##__VAL(R_IRQ_MASK0_SET_, mdio_, v16) << R_IRQ_MASK0_SET__mdio__BITNR) | \ - (R_IRQ_MASK0_SET__ata_drq3__##f17##__VAL(R_IRQ_MASK0_SET_, ata_drq3_, v17) << R_IRQ_MASK0_SET__ata_drq3__BITNR) | \ - (R_IRQ_MASK0_SET__ata_drq2__##f18##__VAL(R_IRQ_MASK0_SET_, ata_drq2_, v18) << R_IRQ_MASK0_SET__ata_drq2__BITNR) | \ - (R_IRQ_MASK0_SET__ata_drq1__##f19##__VAL(R_IRQ_MASK0_SET_, ata_drq1_, v19) << R_IRQ_MASK0_SET__ata_drq1__BITNR) | \ - (R_IRQ_MASK0_SET__ata_drq0__##f20##__VAL(R_IRQ_MASK0_SET_, ata_drq0_, v20) << R_IRQ_MASK0_SET__ata_drq0__BITNR) | \ - (R_IRQ_MASK0_SET__par0_ecp_cmd__##f21##__VAL(R_IRQ_MASK0_SET_, par0_ecp_cmd_, v21) << R_IRQ_MASK0_SET__par0_ecp_cmd__BITNR) | \ - (R_IRQ_MASK0_SET__par0_peri__##f22##__VAL(R_IRQ_MASK0_SET_, par0_peri_, v22) << R_IRQ_MASK0_SET__par0_peri__BITNR) | \ - (R_IRQ_MASK0_SET__par0_data__##f23##__VAL(R_IRQ_MASK0_SET_, par0_data_, v23) << R_IRQ_MASK0_SET__par0_data__BITNR) | \ - (R_IRQ_MASK0_SET__par0_ready__##f24##__VAL(R_IRQ_MASK0_SET_, par0_ready_, v24) << R_IRQ_MASK0_SET__par0_ready__BITNR) | \ - (R_IRQ_MASK0_SET__ata_dmaend__##f25##__VAL(R_IRQ_MASK0_SET_, ata_dmaend_, v25) << R_IRQ_MASK0_SET__ata_dmaend__BITNR) | \ - (R_IRQ_MASK0_SET__irq_ext_vector_nr__##f26##__VAL(R_IRQ_MASK0_SET_, irq_ext_vector_nr_, v26) << R_IRQ_MASK0_SET__irq_ext_vector_nr__BITNR) | \ - (R_IRQ_MASK0_SET__irq_int_vector_nr__##f27##__VAL(R_IRQ_MASK0_SET_, irq_int_vector_nr_, v27) << R_IRQ_MASK0_SET__irq_int_vector_nr__BITNR) | \ - (R_IRQ_MASK0_SET__ext_dma1__##f28##__VAL(R_IRQ_MASK0_SET_, ext_dma1_, v28) << R_IRQ_MASK0_SET__ext_dma1__BITNR) | \ - (R_IRQ_MASK0_SET__ext_dma0__##f29##__VAL(R_IRQ_MASK0_SET_, ext_dma0_, v29) << R_IRQ_MASK0_SET__ext_dma0__BITNR) | \ - (R_IRQ_MASK0_SET__timer1__##f30##__VAL(R_IRQ_MASK0_SET_, timer1_, v30) << R_IRQ_MASK0_SET__timer1__BITNR) | \ - (R_IRQ_MASK0_SET__timer0__##f31##__VAL(R_IRQ_MASK0_SET_, timer0_, v31) << R_IRQ_MASK0_SET__timer0__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_IRQ_MASK0_SET_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_IRQ_MASK0_SET. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_IRQ_MASK0_SET_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16,f17_,v17,f18_,v18,f19_,v19,f20_,v20,f21_,v21,f22_,v22,f23_,v23,f24_,v24,f25_,v25,f26_,v26,f27_,v27,f28_,v28,f29_,v29,f30_,v30,f31_,v31) ( \ - (R_IRQ_MASK0_SET__nmi_pin__##f1_##_VAL(R_IRQ_MASK0_SET_, nmi_pin_, v1) << R_IRQ_MASK0_SET__nmi_pin__BITNR) | \ - (R_IRQ_MASK0_SET__watchdog_nmi__##f2_##_VAL(R_IRQ_MASK0_SET_, watchdog_nmi_, v2) << R_IRQ_MASK0_SET__watchdog_nmi__BITNR) | \ - (R_IRQ_MASK0_SET__sqe_test_error__##f3_##_VAL(R_IRQ_MASK0_SET_, sqe_test_error_, v3) << R_IRQ_MASK0_SET__sqe_test_error__BITNR) | \ - (R_IRQ_MASK0_SET__carrier_loss__##f4_##_VAL(R_IRQ_MASK0_SET_, carrier_loss_, v4) << R_IRQ_MASK0_SET__carrier_loss__BITNR) | \ - (R_IRQ_MASK0_SET__deferred__##f5_##_VAL(R_IRQ_MASK0_SET_, deferred_, v5) << R_IRQ_MASK0_SET__deferred__BITNR) | \ - (R_IRQ_MASK0_SET__late_col__##f6_##_VAL(R_IRQ_MASK0_SET_, late_col_, v6) << R_IRQ_MASK0_SET__late_col__BITNR) | \ - (R_IRQ_MASK0_SET__multiple_col__##f7_##_VAL(R_IRQ_MASK0_SET_, multiple_col_, v7) << R_IRQ_MASK0_SET__multiple_col__BITNR) | \ - (R_IRQ_MASK0_SET__single_col__##f8_##_VAL(R_IRQ_MASK0_SET_, single_col_, v8) << R_IRQ_MASK0_SET__single_col__BITNR) | \ - (R_IRQ_MASK0_SET__congestion__##f9_##_VAL(R_IRQ_MASK0_SET_, congestion_, v9) << R_IRQ_MASK0_SET__congestion__BITNR) | \ - (R_IRQ_MASK0_SET__oversize__##f10_##_VAL(R_IRQ_MASK0_SET_, oversize_, v10) << R_IRQ_MASK0_SET__oversize__BITNR) | \ - (R_IRQ_MASK0_SET__alignment_error__##f11_##_VAL(R_IRQ_MASK0_SET_, alignment_error_, v11) << R_IRQ_MASK0_SET__alignment_error__BITNR) | \ - (R_IRQ_MASK0_SET__crc_error__##f12_##_VAL(R_IRQ_MASK0_SET_, crc_error_, v12) << R_IRQ_MASK0_SET__crc_error__BITNR) | \ - (R_IRQ_MASK0_SET__overrun__##f13_##_VAL(R_IRQ_MASK0_SET_, overrun_, v13) << R_IRQ_MASK0_SET__overrun__BITNR) | \ - (R_IRQ_MASK0_SET__underrun__##f14_##_VAL(R_IRQ_MASK0_SET_, underrun_, v14) << R_IRQ_MASK0_SET__underrun__BITNR) | \ - (R_IRQ_MASK0_SET__excessive_col__##f15_##_VAL(R_IRQ_MASK0_SET_, excessive_col_, v15) << R_IRQ_MASK0_SET__excessive_col__BITNR) | \ - (R_IRQ_MASK0_SET__mdio__##f16_##_VAL(R_IRQ_MASK0_SET_, mdio_, v16) << R_IRQ_MASK0_SET__mdio__BITNR) | \ - (R_IRQ_MASK0_SET__ata_drq3__##f17_##_VAL(R_IRQ_MASK0_SET_, ata_drq3_, v17) << R_IRQ_MASK0_SET__ata_drq3__BITNR) | \ - (R_IRQ_MASK0_SET__ata_drq2__##f18_##_VAL(R_IRQ_MASK0_SET_, ata_drq2_, v18) << R_IRQ_MASK0_SET__ata_drq2__BITNR) | \ - (R_IRQ_MASK0_SET__ata_drq1__##f19_##_VAL(R_IRQ_MASK0_SET_, ata_drq1_, v19) << R_IRQ_MASK0_SET__ata_drq1__BITNR) | \ - (R_IRQ_MASK0_SET__ata_drq0__##f20_##_VAL(R_IRQ_MASK0_SET_, ata_drq0_, v20) << R_IRQ_MASK0_SET__ata_drq0__BITNR) | \ - (R_IRQ_MASK0_SET__par0_ecp_cmd__##f21_##_VAL(R_IRQ_MASK0_SET_, par0_ecp_cmd_, v21) << R_IRQ_MASK0_SET__par0_ecp_cmd__BITNR) | \ - (R_IRQ_MASK0_SET__par0_peri__##f22_##_VAL(R_IRQ_MASK0_SET_, par0_peri_, v22) << R_IRQ_MASK0_SET__par0_peri__BITNR) | \ - (R_IRQ_MASK0_SET__par0_data__##f23_##_VAL(R_IRQ_MASK0_SET_, par0_data_, v23) << R_IRQ_MASK0_SET__par0_data__BITNR) | \ - (R_IRQ_MASK0_SET__par0_ready__##f24_##_VAL(R_IRQ_MASK0_SET_, par0_ready_, v24) << R_IRQ_MASK0_SET__par0_ready__BITNR) | \ - (R_IRQ_MASK0_SET__ata_dmaend__##f25_##_VAL(R_IRQ_MASK0_SET_, ata_dmaend_, v25) << R_IRQ_MASK0_SET__ata_dmaend__BITNR) | \ - (R_IRQ_MASK0_SET__irq_ext_vector_nr__##f26_##_VAL(R_IRQ_MASK0_SET_, irq_ext_vector_nr_, v26) << R_IRQ_MASK0_SET__irq_ext_vector_nr__BITNR) | \ - (R_IRQ_MASK0_SET__irq_int_vector_nr__##f27_##_VAL(R_IRQ_MASK0_SET_, irq_int_vector_nr_, v27) << R_IRQ_MASK0_SET__irq_int_vector_nr__BITNR) | \ - (R_IRQ_MASK0_SET__ext_dma1__##f28_##_VAL(R_IRQ_MASK0_SET_, ext_dma1_, v28) << R_IRQ_MASK0_SET__ext_dma1__BITNR) | \ - (R_IRQ_MASK0_SET__ext_dma0__##f29_##_VAL(R_IRQ_MASK0_SET_, ext_dma0_, v29) << R_IRQ_MASK0_SET__ext_dma0__BITNR) | \ - (R_IRQ_MASK0_SET__timer1__##f30_##_VAL(R_IRQ_MASK0_SET_, timer1_, v30) << R_IRQ_MASK0_SET__timer1__BITNR) | \ - (R_IRQ_MASK0_SET__timer0__##f31_##_VAL(R_IRQ_MASK0_SET_, timer0_, v31) << R_IRQ_MASK0_SET__timer0__BITNR) \ -) - -#endif - -/* - * R_IRQ_MASK1_CLR - * - type: WO - * - addr: 0xb00000c8 - * - group: Interrupt mask and status registers - */ - -#if USE_GROUP__Interrupt_mask_and_status_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_IRQ_MASK1_CLR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_IRQ_MASK1_CLR. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_IRQ_MASK1_CLR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_IRQ_MASK1_CLR(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25,f26,v26,f27,v27,f28,v28) ( \ - *R_IRQ_MASK1_CLR__SADDR = ( \ - REG_INITIATED(R_IRQ_MASK1_CLR_) \ - REG_VAL__R_IRQ_MASK1_CLR_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20,f21##_,v21,f22##_,v22,f23##_,v23,f24##_,v24,f25##_,v25,f26##_,v26,f27##_,v27,f28##_,v28) \ - ), \ - R_IRQ_MASK1_CLR__WRITE(R_IRQ_MASK1_CLR__ADDR, *R_IRQ_MASK1_CLR__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_IRQ_MASK1_CLR__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_IRQ_MASK1_CLR. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_IRQ_MASK1_CLR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_IRQ_MASK1_CLR__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25,f26,v26,f27,v27,f28,v28) ( \ - *R_IRQ_MASK1_CLR__SADDR = ( \ - REG_INITIATED(R_IRQ_MASK1_CLR_) \ - REG_VAL__R_IRQ_MASK1_CLR_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20,f21##_,v21,f22##_,v22,f23##_,v23,f24##_,v24,f25##_,v25,f26##_,v26,f27##_,v27,f28##_,v28) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_IRQ_MASK1_CLR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_IRQ_MASK1_CLR(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25,f26,v26,f27,v27,f28,v28) ( \ - (R_IRQ_MASK1_CLR__sw_int7__##f1##__MASK & REG__##v1) | \ - (R_IRQ_MASK1_CLR__sw_int6__##f2##__MASK & REG__##v2) | \ - (R_IRQ_MASK1_CLR__sw_int5__##f3##__MASK & REG__##v3) | \ - (R_IRQ_MASK1_CLR__sw_int4__##f4##__MASK & REG__##v4) | \ - (R_IRQ_MASK1_CLR__sw_int3__##f5##__MASK & REG__##v5) | \ - (R_IRQ_MASK1_CLR__sw_int2__##f6##__MASK & REG__##v6) | \ - (R_IRQ_MASK1_CLR__sw_int1__##f7##__MASK & REG__##v7) | \ - (R_IRQ_MASK1_CLR__sw_int0__##f8##__MASK & REG__##v8) | \ - (R_IRQ_MASK1_CLR__par1_ecp_cmd__##f9##__MASK & REG__##v9) | \ - (R_IRQ_MASK1_CLR__par1_peri__##f10##__MASK & REG__##v10) | \ - (R_IRQ_MASK1_CLR__par1_data__##f11##__MASK & REG__##v11) | \ - (R_IRQ_MASK1_CLR__par1_ready__##f12##__MASK & REG__##v12) | \ - (R_IRQ_MASK1_CLR__ser3_ready__##f13##__MASK & REG__##v13) | \ - (R_IRQ_MASK1_CLR__ser3_data__##f14##__MASK & REG__##v14) | \ - (R_IRQ_MASK1_CLR__ser2_ready__##f15##__MASK & REG__##v15) | \ - (R_IRQ_MASK1_CLR__ser2_data__##f16##__MASK & REG__##v16) | \ - (R_IRQ_MASK1_CLR__ser1_ready__##f17##__MASK & REG__##v17) | \ - (R_IRQ_MASK1_CLR__ser1_data__##f18##__MASK & REG__##v18) | \ - (R_IRQ_MASK1_CLR__ser0_ready__##f19##__MASK & REG__##v19) | \ - (R_IRQ_MASK1_CLR__ser0_data__##f20##__MASK & REG__##v20) | \ - (R_IRQ_MASK1_CLR__pa7__##f21##__MASK & REG__##v21) | \ - (R_IRQ_MASK1_CLR__pa6__##f22##__MASK & REG__##v22) | \ - (R_IRQ_MASK1_CLR__pa5__##f23##__MASK & REG__##v23) | \ - (R_IRQ_MASK1_CLR__pa4__##f24##__MASK & REG__##v24) | \ - (R_IRQ_MASK1_CLR__pa3__##f25##__MASK & REG__##v25) | \ - (R_IRQ_MASK1_CLR__pa2__##f26##__MASK & REG__##v26) | \ - (R_IRQ_MASK1_CLR__pa1__##f27##__MASK & REG__##v27) | \ - (R_IRQ_MASK1_CLR__pa0__##f28##__MASK & REG__##v28) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_IRQ_MASK1_CLR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_IRQ_MASK1_CLR. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_IRQ_MASK1_CLR(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25,f26,v26,f27,v27,f28,v28) ( \ - (R_IRQ_MASK1_CLR__sw_int7__##f1##__VAL(R_IRQ_MASK1_CLR_, sw_int7_, v1) << R_IRQ_MASK1_CLR__sw_int7__BITNR) | \ - (R_IRQ_MASK1_CLR__sw_int6__##f2##__VAL(R_IRQ_MASK1_CLR_, sw_int6_, v2) << R_IRQ_MASK1_CLR__sw_int6__BITNR) | \ - (R_IRQ_MASK1_CLR__sw_int5__##f3##__VAL(R_IRQ_MASK1_CLR_, sw_int5_, v3) << R_IRQ_MASK1_CLR__sw_int5__BITNR) | \ - (R_IRQ_MASK1_CLR__sw_int4__##f4##__VAL(R_IRQ_MASK1_CLR_, sw_int4_, v4) << R_IRQ_MASK1_CLR__sw_int4__BITNR) | \ - (R_IRQ_MASK1_CLR__sw_int3__##f5##__VAL(R_IRQ_MASK1_CLR_, sw_int3_, v5) << R_IRQ_MASK1_CLR__sw_int3__BITNR) | \ - (R_IRQ_MASK1_CLR__sw_int2__##f6##__VAL(R_IRQ_MASK1_CLR_, sw_int2_, v6) << R_IRQ_MASK1_CLR__sw_int2__BITNR) | \ - (R_IRQ_MASK1_CLR__sw_int1__##f7##__VAL(R_IRQ_MASK1_CLR_, sw_int1_, v7) << R_IRQ_MASK1_CLR__sw_int1__BITNR) | \ - (R_IRQ_MASK1_CLR__sw_int0__##f8##__VAL(R_IRQ_MASK1_CLR_, sw_int0_, v8) << R_IRQ_MASK1_CLR__sw_int0__BITNR) | \ - (R_IRQ_MASK1_CLR__par1_ecp_cmd__##f9##__VAL(R_IRQ_MASK1_CLR_, par1_ecp_cmd_, v9) << R_IRQ_MASK1_CLR__par1_ecp_cmd__BITNR) | \ - (R_IRQ_MASK1_CLR__par1_peri__##f10##__VAL(R_IRQ_MASK1_CLR_, par1_peri_, v10) << R_IRQ_MASK1_CLR__par1_peri__BITNR) | \ - (R_IRQ_MASK1_CLR__par1_data__##f11##__VAL(R_IRQ_MASK1_CLR_, par1_data_, v11) << R_IRQ_MASK1_CLR__par1_data__BITNR) | \ - (R_IRQ_MASK1_CLR__par1_ready__##f12##__VAL(R_IRQ_MASK1_CLR_, par1_ready_, v12) << R_IRQ_MASK1_CLR__par1_ready__BITNR) | \ - (R_IRQ_MASK1_CLR__ser3_ready__##f13##__VAL(R_IRQ_MASK1_CLR_, ser3_ready_, v13) << R_IRQ_MASK1_CLR__ser3_ready__BITNR) | \ - (R_IRQ_MASK1_CLR__ser3_data__##f14##__VAL(R_IRQ_MASK1_CLR_, ser3_data_, v14) << R_IRQ_MASK1_CLR__ser3_data__BITNR) | \ - (R_IRQ_MASK1_CLR__ser2_ready__##f15##__VAL(R_IRQ_MASK1_CLR_, ser2_ready_, v15) << R_IRQ_MASK1_CLR__ser2_ready__BITNR) | \ - (R_IRQ_MASK1_CLR__ser2_data__##f16##__VAL(R_IRQ_MASK1_CLR_, ser2_data_, v16) << R_IRQ_MASK1_CLR__ser2_data__BITNR) | \ - (R_IRQ_MASK1_CLR__ser1_ready__##f17##__VAL(R_IRQ_MASK1_CLR_, ser1_ready_, v17) << R_IRQ_MASK1_CLR__ser1_ready__BITNR) | \ - (R_IRQ_MASK1_CLR__ser1_data__##f18##__VAL(R_IRQ_MASK1_CLR_, ser1_data_, v18) << R_IRQ_MASK1_CLR__ser1_data__BITNR) | \ - (R_IRQ_MASK1_CLR__ser0_ready__##f19##__VAL(R_IRQ_MASK1_CLR_, ser0_ready_, v19) << R_IRQ_MASK1_CLR__ser0_ready__BITNR) | \ - (R_IRQ_MASK1_CLR__ser0_data__##f20##__VAL(R_IRQ_MASK1_CLR_, ser0_data_, v20) << R_IRQ_MASK1_CLR__ser0_data__BITNR) | \ - (R_IRQ_MASK1_CLR__pa7__##f21##__VAL(R_IRQ_MASK1_CLR_, pa7_, v21) << R_IRQ_MASK1_CLR__pa7__BITNR) | \ - (R_IRQ_MASK1_CLR__pa6__##f22##__VAL(R_IRQ_MASK1_CLR_, pa6_, v22) << R_IRQ_MASK1_CLR__pa6__BITNR) | \ - (R_IRQ_MASK1_CLR__pa5__##f23##__VAL(R_IRQ_MASK1_CLR_, pa5_, v23) << R_IRQ_MASK1_CLR__pa5__BITNR) | \ - (R_IRQ_MASK1_CLR__pa4__##f24##__VAL(R_IRQ_MASK1_CLR_, pa4_, v24) << R_IRQ_MASK1_CLR__pa4__BITNR) | \ - (R_IRQ_MASK1_CLR__pa3__##f25##__VAL(R_IRQ_MASK1_CLR_, pa3_, v25) << R_IRQ_MASK1_CLR__pa3__BITNR) | \ - (R_IRQ_MASK1_CLR__pa2__##f26##__VAL(R_IRQ_MASK1_CLR_, pa2_, v26) << R_IRQ_MASK1_CLR__pa2__BITNR) | \ - (R_IRQ_MASK1_CLR__pa1__##f27##__VAL(R_IRQ_MASK1_CLR_, pa1_, v27) << R_IRQ_MASK1_CLR__pa1__BITNR) | \ - (R_IRQ_MASK1_CLR__pa0__##f28##__VAL(R_IRQ_MASK1_CLR_, pa0_, v28) << R_IRQ_MASK1_CLR__pa0__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_IRQ_MASK1_CLR_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_IRQ_MASK1_CLR. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_IRQ_MASK1_CLR_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16,f17_,v17,f18_,v18,f19_,v19,f20_,v20,f21_,v21,f22_,v22,f23_,v23,f24_,v24,f25_,v25,f26_,v26,f27_,v27,f28_,v28) ( \ - (R_IRQ_MASK1_CLR__sw_int7__##f1_##_VAL(R_IRQ_MASK1_CLR_, sw_int7_, v1) << R_IRQ_MASK1_CLR__sw_int7__BITNR) | \ - (R_IRQ_MASK1_CLR__sw_int6__##f2_##_VAL(R_IRQ_MASK1_CLR_, sw_int6_, v2) << R_IRQ_MASK1_CLR__sw_int6__BITNR) | \ - (R_IRQ_MASK1_CLR__sw_int5__##f3_##_VAL(R_IRQ_MASK1_CLR_, sw_int5_, v3) << R_IRQ_MASK1_CLR__sw_int5__BITNR) | \ - (R_IRQ_MASK1_CLR__sw_int4__##f4_##_VAL(R_IRQ_MASK1_CLR_, sw_int4_, v4) << R_IRQ_MASK1_CLR__sw_int4__BITNR) | \ - (R_IRQ_MASK1_CLR__sw_int3__##f5_##_VAL(R_IRQ_MASK1_CLR_, sw_int3_, v5) << R_IRQ_MASK1_CLR__sw_int3__BITNR) | \ - (R_IRQ_MASK1_CLR__sw_int2__##f6_##_VAL(R_IRQ_MASK1_CLR_, sw_int2_, v6) << R_IRQ_MASK1_CLR__sw_int2__BITNR) | \ - (R_IRQ_MASK1_CLR__sw_int1__##f7_##_VAL(R_IRQ_MASK1_CLR_, sw_int1_, v7) << R_IRQ_MASK1_CLR__sw_int1__BITNR) | \ - (R_IRQ_MASK1_CLR__sw_int0__##f8_##_VAL(R_IRQ_MASK1_CLR_, sw_int0_, v8) << R_IRQ_MASK1_CLR__sw_int0__BITNR) | \ - (R_IRQ_MASK1_CLR__par1_ecp_cmd__##f9_##_VAL(R_IRQ_MASK1_CLR_, par1_ecp_cmd_, v9) << R_IRQ_MASK1_CLR__par1_ecp_cmd__BITNR) | \ - (R_IRQ_MASK1_CLR__par1_peri__##f10_##_VAL(R_IRQ_MASK1_CLR_, par1_peri_, v10) << R_IRQ_MASK1_CLR__par1_peri__BITNR) | \ - (R_IRQ_MASK1_CLR__par1_data__##f11_##_VAL(R_IRQ_MASK1_CLR_, par1_data_, v11) << R_IRQ_MASK1_CLR__par1_data__BITNR) | \ - (R_IRQ_MASK1_CLR__par1_ready__##f12_##_VAL(R_IRQ_MASK1_CLR_, par1_ready_, v12) << R_IRQ_MASK1_CLR__par1_ready__BITNR) | \ - (R_IRQ_MASK1_CLR__ser3_ready__##f13_##_VAL(R_IRQ_MASK1_CLR_, ser3_ready_, v13) << R_IRQ_MASK1_CLR__ser3_ready__BITNR) | \ - (R_IRQ_MASK1_CLR__ser3_data__##f14_##_VAL(R_IRQ_MASK1_CLR_, ser3_data_, v14) << R_IRQ_MASK1_CLR__ser3_data__BITNR) | \ - (R_IRQ_MASK1_CLR__ser2_ready__##f15_##_VAL(R_IRQ_MASK1_CLR_, ser2_ready_, v15) << R_IRQ_MASK1_CLR__ser2_ready__BITNR) | \ - (R_IRQ_MASK1_CLR__ser2_data__##f16_##_VAL(R_IRQ_MASK1_CLR_, ser2_data_, v16) << R_IRQ_MASK1_CLR__ser2_data__BITNR) | \ - (R_IRQ_MASK1_CLR__ser1_ready__##f17_##_VAL(R_IRQ_MASK1_CLR_, ser1_ready_, v17) << R_IRQ_MASK1_CLR__ser1_ready__BITNR) | \ - (R_IRQ_MASK1_CLR__ser1_data__##f18_##_VAL(R_IRQ_MASK1_CLR_, ser1_data_, v18) << R_IRQ_MASK1_CLR__ser1_data__BITNR) | \ - (R_IRQ_MASK1_CLR__ser0_ready__##f19_##_VAL(R_IRQ_MASK1_CLR_, ser0_ready_, v19) << R_IRQ_MASK1_CLR__ser0_ready__BITNR) | \ - (R_IRQ_MASK1_CLR__ser0_data__##f20_##_VAL(R_IRQ_MASK1_CLR_, ser0_data_, v20) << R_IRQ_MASK1_CLR__ser0_data__BITNR) | \ - (R_IRQ_MASK1_CLR__pa7__##f21_##_VAL(R_IRQ_MASK1_CLR_, pa7_, v21) << R_IRQ_MASK1_CLR__pa7__BITNR) | \ - (R_IRQ_MASK1_CLR__pa6__##f22_##_VAL(R_IRQ_MASK1_CLR_, pa6_, v22) << R_IRQ_MASK1_CLR__pa6__BITNR) | \ - (R_IRQ_MASK1_CLR__pa5__##f23_##_VAL(R_IRQ_MASK1_CLR_, pa5_, v23) << R_IRQ_MASK1_CLR__pa5__BITNR) | \ - (R_IRQ_MASK1_CLR__pa4__##f24_##_VAL(R_IRQ_MASK1_CLR_, pa4_, v24) << R_IRQ_MASK1_CLR__pa4__BITNR) | \ - (R_IRQ_MASK1_CLR__pa3__##f25_##_VAL(R_IRQ_MASK1_CLR_, pa3_, v25) << R_IRQ_MASK1_CLR__pa3__BITNR) | \ - (R_IRQ_MASK1_CLR__pa2__##f26_##_VAL(R_IRQ_MASK1_CLR_, pa2_, v26) << R_IRQ_MASK1_CLR__pa2__BITNR) | \ - (R_IRQ_MASK1_CLR__pa1__##f27_##_VAL(R_IRQ_MASK1_CLR_, pa1_, v27) << R_IRQ_MASK1_CLR__pa1__BITNR) | \ - (R_IRQ_MASK1_CLR__pa0__##f28_##_VAL(R_IRQ_MASK1_CLR_, pa0_, v28) << R_IRQ_MASK1_CLR__pa0__BITNR) \ -) - -#endif - -/* - * R_IRQ_MASK1_RD - * - type: RO - * - addr: 0xb00000c8 - * - group: Interrupt mask and status registers - */ - -#if USE_GROUP__Interrupt_mask_and_status_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_IRQ_MASK1_RD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_IRQ_MASK1_RD(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25,f26,v26,f27,v27,f28,v28) ( \ - (R_IRQ_MASK1_RD__sw_int7__##f1##__MASK & REG__##v1) | \ - (R_IRQ_MASK1_RD__sw_int6__##f2##__MASK & REG__##v2) | \ - (R_IRQ_MASK1_RD__sw_int5__##f3##__MASK & REG__##v3) | \ - (R_IRQ_MASK1_RD__sw_int4__##f4##__MASK & REG__##v4) | \ - (R_IRQ_MASK1_RD__sw_int3__##f5##__MASK & REG__##v5) | \ - (R_IRQ_MASK1_RD__sw_int2__##f6##__MASK & REG__##v6) | \ - (R_IRQ_MASK1_RD__sw_int1__##f7##__MASK & REG__##v7) | \ - (R_IRQ_MASK1_RD__sw_int0__##f8##__MASK & REG__##v8) | \ - (R_IRQ_MASK1_RD__par1_ecp_cmd__##f9##__MASK & REG__##v9) | \ - (R_IRQ_MASK1_RD__par1_peri__##f10##__MASK & REG__##v10) | \ - (R_IRQ_MASK1_RD__par1_data__##f11##__MASK & REG__##v11) | \ - (R_IRQ_MASK1_RD__par1_ready__##f12##__MASK & REG__##v12) | \ - (R_IRQ_MASK1_RD__ser3_ready__##f13##__MASK & REG__##v13) | \ - (R_IRQ_MASK1_RD__ser3_data__##f14##__MASK & REG__##v14) | \ - (R_IRQ_MASK1_RD__ser2_ready__##f15##__MASK & REG__##v15) | \ - (R_IRQ_MASK1_RD__ser2_data__##f16##__MASK & REG__##v16) | \ - (R_IRQ_MASK1_RD__ser1_ready__##f17##__MASK & REG__##v17) | \ - (R_IRQ_MASK1_RD__ser1_data__##f18##__MASK & REG__##v18) | \ - (R_IRQ_MASK1_RD__ser0_ready__##f19##__MASK & REG__##v19) | \ - (R_IRQ_MASK1_RD__ser0_data__##f20##__MASK & REG__##v20) | \ - (R_IRQ_MASK1_RD__pa7__##f21##__MASK & REG__##v21) | \ - (R_IRQ_MASK1_RD__pa6__##f22##__MASK & REG__##v22) | \ - (R_IRQ_MASK1_RD__pa5__##f23##__MASK & REG__##v23) | \ - (R_IRQ_MASK1_RD__pa4__##f24##__MASK & REG__##v24) | \ - (R_IRQ_MASK1_RD__pa3__##f25##__MASK & REG__##v25) | \ - (R_IRQ_MASK1_RD__pa2__##f26##__MASK & REG__##v26) | \ - (R_IRQ_MASK1_RD__pa1__##f27##__MASK & REG__##v27) | \ - (R_IRQ_MASK1_RD__pa0__##f28##__MASK & REG__##v28) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_IRQ_MASK1_RD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_IRQ_MASK1_RD. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_IRQ_MASK1_RD(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25,f26,v26,f27,v27,f28,v28) ( \ - (R_IRQ_MASK1_RD__sw_int7__##f1##__VAL(R_IRQ_MASK1_RD_, sw_int7_, v1) << R_IRQ_MASK1_RD__sw_int7__BITNR) | \ - (R_IRQ_MASK1_RD__sw_int6__##f2##__VAL(R_IRQ_MASK1_RD_, sw_int6_, v2) << R_IRQ_MASK1_RD__sw_int6__BITNR) | \ - (R_IRQ_MASK1_RD__sw_int5__##f3##__VAL(R_IRQ_MASK1_RD_, sw_int5_, v3) << R_IRQ_MASK1_RD__sw_int5__BITNR) | \ - (R_IRQ_MASK1_RD__sw_int4__##f4##__VAL(R_IRQ_MASK1_RD_, sw_int4_, v4) << R_IRQ_MASK1_RD__sw_int4__BITNR) | \ - (R_IRQ_MASK1_RD__sw_int3__##f5##__VAL(R_IRQ_MASK1_RD_, sw_int3_, v5) << R_IRQ_MASK1_RD__sw_int3__BITNR) | \ - (R_IRQ_MASK1_RD__sw_int2__##f6##__VAL(R_IRQ_MASK1_RD_, sw_int2_, v6) << R_IRQ_MASK1_RD__sw_int2__BITNR) | \ - (R_IRQ_MASK1_RD__sw_int1__##f7##__VAL(R_IRQ_MASK1_RD_, sw_int1_, v7) << R_IRQ_MASK1_RD__sw_int1__BITNR) | \ - (R_IRQ_MASK1_RD__sw_int0__##f8##__VAL(R_IRQ_MASK1_RD_, sw_int0_, v8) << R_IRQ_MASK1_RD__sw_int0__BITNR) | \ - (R_IRQ_MASK1_RD__par1_ecp_cmd__##f9##__VAL(R_IRQ_MASK1_RD_, par1_ecp_cmd_, v9) << R_IRQ_MASK1_RD__par1_ecp_cmd__BITNR) | \ - (R_IRQ_MASK1_RD__par1_peri__##f10##__VAL(R_IRQ_MASK1_RD_, par1_peri_, v10) << R_IRQ_MASK1_RD__par1_peri__BITNR) | \ - (R_IRQ_MASK1_RD__par1_data__##f11##__VAL(R_IRQ_MASK1_RD_, par1_data_, v11) << R_IRQ_MASK1_RD__par1_data__BITNR) | \ - (R_IRQ_MASK1_RD__par1_ready__##f12##__VAL(R_IRQ_MASK1_RD_, par1_ready_, v12) << R_IRQ_MASK1_RD__par1_ready__BITNR) | \ - (R_IRQ_MASK1_RD__ser3_ready__##f13##__VAL(R_IRQ_MASK1_RD_, ser3_ready_, v13) << R_IRQ_MASK1_RD__ser3_ready__BITNR) | \ - (R_IRQ_MASK1_RD__ser3_data__##f14##__VAL(R_IRQ_MASK1_RD_, ser3_data_, v14) << R_IRQ_MASK1_RD__ser3_data__BITNR) | \ - (R_IRQ_MASK1_RD__ser2_ready__##f15##__VAL(R_IRQ_MASK1_RD_, ser2_ready_, v15) << R_IRQ_MASK1_RD__ser2_ready__BITNR) | \ - (R_IRQ_MASK1_RD__ser2_data__##f16##__VAL(R_IRQ_MASK1_RD_, ser2_data_, v16) << R_IRQ_MASK1_RD__ser2_data__BITNR) | \ - (R_IRQ_MASK1_RD__ser1_ready__##f17##__VAL(R_IRQ_MASK1_RD_, ser1_ready_, v17) << R_IRQ_MASK1_RD__ser1_ready__BITNR) | \ - (R_IRQ_MASK1_RD__ser1_data__##f18##__VAL(R_IRQ_MASK1_RD_, ser1_data_, v18) << R_IRQ_MASK1_RD__ser1_data__BITNR) | \ - (R_IRQ_MASK1_RD__ser0_ready__##f19##__VAL(R_IRQ_MASK1_RD_, ser0_ready_, v19) << R_IRQ_MASK1_RD__ser0_ready__BITNR) | \ - (R_IRQ_MASK1_RD__ser0_data__##f20##__VAL(R_IRQ_MASK1_RD_, ser0_data_, v20) << R_IRQ_MASK1_RD__ser0_data__BITNR) | \ - (R_IRQ_MASK1_RD__pa7__##f21##__VAL(R_IRQ_MASK1_RD_, pa7_, v21) << R_IRQ_MASK1_RD__pa7__BITNR) | \ - (R_IRQ_MASK1_RD__pa6__##f22##__VAL(R_IRQ_MASK1_RD_, pa6_, v22) << R_IRQ_MASK1_RD__pa6__BITNR) | \ - (R_IRQ_MASK1_RD__pa5__##f23##__VAL(R_IRQ_MASK1_RD_, pa5_, v23) << R_IRQ_MASK1_RD__pa5__BITNR) | \ - (R_IRQ_MASK1_RD__pa4__##f24##__VAL(R_IRQ_MASK1_RD_, pa4_, v24) << R_IRQ_MASK1_RD__pa4__BITNR) | \ - (R_IRQ_MASK1_RD__pa3__##f25##__VAL(R_IRQ_MASK1_RD_, pa3_, v25) << R_IRQ_MASK1_RD__pa3__BITNR) | \ - (R_IRQ_MASK1_RD__pa2__##f26##__VAL(R_IRQ_MASK1_RD_, pa2_, v26) << R_IRQ_MASK1_RD__pa2__BITNR) | \ - (R_IRQ_MASK1_RD__pa1__##f27##__VAL(R_IRQ_MASK1_RD_, pa1_, v27) << R_IRQ_MASK1_RD__pa1__BITNR) | \ - (R_IRQ_MASK1_RD__pa0__##f28##__VAL(R_IRQ_MASK1_RD_, pa0_, v28) << R_IRQ_MASK1_RD__pa0__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_IRQ_MASK1_RD_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_IRQ_MASK1_RD. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_IRQ_MASK1_RD_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16,f17_,v17,f18_,v18,f19_,v19,f20_,v20,f21_,v21,f22_,v22,f23_,v23,f24_,v24,f25_,v25,f26_,v26,f27_,v27,f28_,v28) ( \ - (R_IRQ_MASK1_RD__sw_int7__##f1_##_VAL(R_IRQ_MASK1_RD_, sw_int7_, v1) << R_IRQ_MASK1_RD__sw_int7__BITNR) | \ - (R_IRQ_MASK1_RD__sw_int6__##f2_##_VAL(R_IRQ_MASK1_RD_, sw_int6_, v2) << R_IRQ_MASK1_RD__sw_int6__BITNR) | \ - (R_IRQ_MASK1_RD__sw_int5__##f3_##_VAL(R_IRQ_MASK1_RD_, sw_int5_, v3) << R_IRQ_MASK1_RD__sw_int5__BITNR) | \ - (R_IRQ_MASK1_RD__sw_int4__##f4_##_VAL(R_IRQ_MASK1_RD_, sw_int4_, v4) << R_IRQ_MASK1_RD__sw_int4__BITNR) | \ - (R_IRQ_MASK1_RD__sw_int3__##f5_##_VAL(R_IRQ_MASK1_RD_, sw_int3_, v5) << R_IRQ_MASK1_RD__sw_int3__BITNR) | \ - (R_IRQ_MASK1_RD__sw_int2__##f6_##_VAL(R_IRQ_MASK1_RD_, sw_int2_, v6) << R_IRQ_MASK1_RD__sw_int2__BITNR) | \ - (R_IRQ_MASK1_RD__sw_int1__##f7_##_VAL(R_IRQ_MASK1_RD_, sw_int1_, v7) << R_IRQ_MASK1_RD__sw_int1__BITNR) | \ - (R_IRQ_MASK1_RD__sw_int0__##f8_##_VAL(R_IRQ_MASK1_RD_, sw_int0_, v8) << R_IRQ_MASK1_RD__sw_int0__BITNR) | \ - (R_IRQ_MASK1_RD__par1_ecp_cmd__##f9_##_VAL(R_IRQ_MASK1_RD_, par1_ecp_cmd_, v9) << R_IRQ_MASK1_RD__par1_ecp_cmd__BITNR) | \ - (R_IRQ_MASK1_RD__par1_peri__##f10_##_VAL(R_IRQ_MASK1_RD_, par1_peri_, v10) << R_IRQ_MASK1_RD__par1_peri__BITNR) | \ - (R_IRQ_MASK1_RD__par1_data__##f11_##_VAL(R_IRQ_MASK1_RD_, par1_data_, v11) << R_IRQ_MASK1_RD__par1_data__BITNR) | \ - (R_IRQ_MASK1_RD__par1_ready__##f12_##_VAL(R_IRQ_MASK1_RD_, par1_ready_, v12) << R_IRQ_MASK1_RD__par1_ready__BITNR) | \ - (R_IRQ_MASK1_RD__ser3_ready__##f13_##_VAL(R_IRQ_MASK1_RD_, ser3_ready_, v13) << R_IRQ_MASK1_RD__ser3_ready__BITNR) | \ - (R_IRQ_MASK1_RD__ser3_data__##f14_##_VAL(R_IRQ_MASK1_RD_, ser3_data_, v14) << R_IRQ_MASK1_RD__ser3_data__BITNR) | \ - (R_IRQ_MASK1_RD__ser2_ready__##f15_##_VAL(R_IRQ_MASK1_RD_, ser2_ready_, v15) << R_IRQ_MASK1_RD__ser2_ready__BITNR) | \ - (R_IRQ_MASK1_RD__ser2_data__##f16_##_VAL(R_IRQ_MASK1_RD_, ser2_data_, v16) << R_IRQ_MASK1_RD__ser2_data__BITNR) | \ - (R_IRQ_MASK1_RD__ser1_ready__##f17_##_VAL(R_IRQ_MASK1_RD_, ser1_ready_, v17) << R_IRQ_MASK1_RD__ser1_ready__BITNR) | \ - (R_IRQ_MASK1_RD__ser1_data__##f18_##_VAL(R_IRQ_MASK1_RD_, ser1_data_, v18) << R_IRQ_MASK1_RD__ser1_data__BITNR) | \ - (R_IRQ_MASK1_RD__ser0_ready__##f19_##_VAL(R_IRQ_MASK1_RD_, ser0_ready_, v19) << R_IRQ_MASK1_RD__ser0_ready__BITNR) | \ - (R_IRQ_MASK1_RD__ser0_data__##f20_##_VAL(R_IRQ_MASK1_RD_, ser0_data_, v20) << R_IRQ_MASK1_RD__ser0_data__BITNR) | \ - (R_IRQ_MASK1_RD__pa7__##f21_##_VAL(R_IRQ_MASK1_RD_, pa7_, v21) << R_IRQ_MASK1_RD__pa7__BITNR) | \ - (R_IRQ_MASK1_RD__pa6__##f22_##_VAL(R_IRQ_MASK1_RD_, pa6_, v22) << R_IRQ_MASK1_RD__pa6__BITNR) | \ - (R_IRQ_MASK1_RD__pa5__##f23_##_VAL(R_IRQ_MASK1_RD_, pa5_, v23) << R_IRQ_MASK1_RD__pa5__BITNR) | \ - (R_IRQ_MASK1_RD__pa4__##f24_##_VAL(R_IRQ_MASK1_RD_, pa4_, v24) << R_IRQ_MASK1_RD__pa4__BITNR) | \ - (R_IRQ_MASK1_RD__pa3__##f25_##_VAL(R_IRQ_MASK1_RD_, pa3_, v25) << R_IRQ_MASK1_RD__pa3__BITNR) | \ - (R_IRQ_MASK1_RD__pa2__##f26_##_VAL(R_IRQ_MASK1_RD_, pa2_, v26) << R_IRQ_MASK1_RD__pa2__BITNR) | \ - (R_IRQ_MASK1_RD__pa1__##f27_##_VAL(R_IRQ_MASK1_RD_, pa1_, v27) << R_IRQ_MASK1_RD__pa1__BITNR) | \ - (R_IRQ_MASK1_RD__pa0__##f28_##_VAL(R_IRQ_MASK1_RD_, pa0_, v28) << R_IRQ_MASK1_RD__pa0__BITNR) \ -) - -#endif - -/* - * R_IRQ_MASK1_SET - * - type: WO - * - addr: 0xb00000cc - * - group: Interrupt mask and status registers - */ - -#if USE_GROUP__Interrupt_mask_and_status_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_IRQ_MASK1_SET -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_IRQ_MASK1_SET. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_IRQ_MASK1_SET. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_IRQ_MASK1_SET(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25,f26,v26,f27,v27,f28,v28) ( \ - *R_IRQ_MASK1_SET__SADDR = ( \ - REG_INITIATED(R_IRQ_MASK1_SET_) \ - REG_VAL__R_IRQ_MASK1_SET_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20,f21##_,v21,f22##_,v22,f23##_,v23,f24##_,v24,f25##_,v25,f26##_,v26,f27##_,v27,f28##_,v28) \ - ), \ - R_IRQ_MASK1_SET__WRITE(R_IRQ_MASK1_SET__ADDR, *R_IRQ_MASK1_SET__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_IRQ_MASK1_SET__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_IRQ_MASK1_SET. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_IRQ_MASK1_SET. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_IRQ_MASK1_SET__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25,f26,v26,f27,v27,f28,v28) ( \ - *R_IRQ_MASK1_SET__SADDR = ( \ - REG_INITIATED(R_IRQ_MASK1_SET_) \ - REG_VAL__R_IRQ_MASK1_SET_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20,f21##_,v21,f22##_,v22,f23##_,v23,f24##_,v24,f25##_,v25,f26##_,v26,f27##_,v27,f28##_,v28) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_IRQ_MASK1_SET -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_IRQ_MASK1_SET(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25,f26,v26,f27,v27,f28,v28) ( \ - (R_IRQ_MASK1_SET__sw_int7__##f1##__MASK & REG__##v1) | \ - (R_IRQ_MASK1_SET__sw_int6__##f2##__MASK & REG__##v2) | \ - (R_IRQ_MASK1_SET__sw_int5__##f3##__MASK & REG__##v3) | \ - (R_IRQ_MASK1_SET__sw_int4__##f4##__MASK & REG__##v4) | \ - (R_IRQ_MASK1_SET__sw_int3__##f5##__MASK & REG__##v5) | \ - (R_IRQ_MASK1_SET__sw_int2__##f6##__MASK & REG__##v6) | \ - (R_IRQ_MASK1_SET__sw_int1__##f7##__MASK & REG__##v7) | \ - (R_IRQ_MASK1_SET__sw_int0__##f8##__MASK & REG__##v8) | \ - (R_IRQ_MASK1_SET__par1_ecp_cmd__##f9##__MASK & REG__##v9) | \ - (R_IRQ_MASK1_SET__par1_peri__##f10##__MASK & REG__##v10) | \ - (R_IRQ_MASK1_SET__par1_data__##f11##__MASK & REG__##v11) | \ - (R_IRQ_MASK1_SET__par1_ready__##f12##__MASK & REG__##v12) | \ - (R_IRQ_MASK1_SET__ser3_ready__##f13##__MASK & REG__##v13) | \ - (R_IRQ_MASK1_SET__ser3_data__##f14##__MASK & REG__##v14) | \ - (R_IRQ_MASK1_SET__ser2_ready__##f15##__MASK & REG__##v15) | \ - (R_IRQ_MASK1_SET__ser2_data__##f16##__MASK & REG__##v16) | \ - (R_IRQ_MASK1_SET__ser1_ready__##f17##__MASK & REG__##v17) | \ - (R_IRQ_MASK1_SET__ser1_data__##f18##__MASK & REG__##v18) | \ - (R_IRQ_MASK1_SET__ser0_ready__##f19##__MASK & REG__##v19) | \ - (R_IRQ_MASK1_SET__ser0_data__##f20##__MASK & REG__##v20) | \ - (R_IRQ_MASK1_SET__pa7__##f21##__MASK & REG__##v21) | \ - (R_IRQ_MASK1_SET__pa6__##f22##__MASK & REG__##v22) | \ - (R_IRQ_MASK1_SET__pa5__##f23##__MASK & REG__##v23) | \ - (R_IRQ_MASK1_SET__pa4__##f24##__MASK & REG__##v24) | \ - (R_IRQ_MASK1_SET__pa3__##f25##__MASK & REG__##v25) | \ - (R_IRQ_MASK1_SET__pa2__##f26##__MASK & REG__##v26) | \ - (R_IRQ_MASK1_SET__pa1__##f27##__MASK & REG__##v27) | \ - (R_IRQ_MASK1_SET__pa0__##f28##__MASK & REG__##v28) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_IRQ_MASK1_SET -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_IRQ_MASK1_SET. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_IRQ_MASK1_SET(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25,f26,v26,f27,v27,f28,v28) ( \ - (R_IRQ_MASK1_SET__sw_int7__##f1##__VAL(R_IRQ_MASK1_SET_, sw_int7_, v1) << R_IRQ_MASK1_SET__sw_int7__BITNR) | \ - (R_IRQ_MASK1_SET__sw_int6__##f2##__VAL(R_IRQ_MASK1_SET_, sw_int6_, v2) << R_IRQ_MASK1_SET__sw_int6__BITNR) | \ - (R_IRQ_MASK1_SET__sw_int5__##f3##__VAL(R_IRQ_MASK1_SET_, sw_int5_, v3) << R_IRQ_MASK1_SET__sw_int5__BITNR) | \ - (R_IRQ_MASK1_SET__sw_int4__##f4##__VAL(R_IRQ_MASK1_SET_, sw_int4_, v4) << R_IRQ_MASK1_SET__sw_int4__BITNR) | \ - (R_IRQ_MASK1_SET__sw_int3__##f5##__VAL(R_IRQ_MASK1_SET_, sw_int3_, v5) << R_IRQ_MASK1_SET__sw_int3__BITNR) | \ - (R_IRQ_MASK1_SET__sw_int2__##f6##__VAL(R_IRQ_MASK1_SET_, sw_int2_, v6) << R_IRQ_MASK1_SET__sw_int2__BITNR) | \ - (R_IRQ_MASK1_SET__sw_int1__##f7##__VAL(R_IRQ_MASK1_SET_, sw_int1_, v7) << R_IRQ_MASK1_SET__sw_int1__BITNR) | \ - (R_IRQ_MASK1_SET__sw_int0__##f8##__VAL(R_IRQ_MASK1_SET_, sw_int0_, v8) << R_IRQ_MASK1_SET__sw_int0__BITNR) | \ - (R_IRQ_MASK1_SET__par1_ecp_cmd__##f9##__VAL(R_IRQ_MASK1_SET_, par1_ecp_cmd_, v9) << R_IRQ_MASK1_SET__par1_ecp_cmd__BITNR) | \ - (R_IRQ_MASK1_SET__par1_peri__##f10##__VAL(R_IRQ_MASK1_SET_, par1_peri_, v10) << R_IRQ_MASK1_SET__par1_peri__BITNR) | \ - (R_IRQ_MASK1_SET__par1_data__##f11##__VAL(R_IRQ_MASK1_SET_, par1_data_, v11) << R_IRQ_MASK1_SET__par1_data__BITNR) | \ - (R_IRQ_MASK1_SET__par1_ready__##f12##__VAL(R_IRQ_MASK1_SET_, par1_ready_, v12) << R_IRQ_MASK1_SET__par1_ready__BITNR) | \ - (R_IRQ_MASK1_SET__ser3_ready__##f13##__VAL(R_IRQ_MASK1_SET_, ser3_ready_, v13) << R_IRQ_MASK1_SET__ser3_ready__BITNR) | \ - (R_IRQ_MASK1_SET__ser3_data__##f14##__VAL(R_IRQ_MASK1_SET_, ser3_data_, v14) << R_IRQ_MASK1_SET__ser3_data__BITNR) | \ - (R_IRQ_MASK1_SET__ser2_ready__##f15##__VAL(R_IRQ_MASK1_SET_, ser2_ready_, v15) << R_IRQ_MASK1_SET__ser2_ready__BITNR) | \ - (R_IRQ_MASK1_SET__ser2_data__##f16##__VAL(R_IRQ_MASK1_SET_, ser2_data_, v16) << R_IRQ_MASK1_SET__ser2_data__BITNR) | \ - (R_IRQ_MASK1_SET__ser1_ready__##f17##__VAL(R_IRQ_MASK1_SET_, ser1_ready_, v17) << R_IRQ_MASK1_SET__ser1_ready__BITNR) | \ - (R_IRQ_MASK1_SET__ser1_data__##f18##__VAL(R_IRQ_MASK1_SET_, ser1_data_, v18) << R_IRQ_MASK1_SET__ser1_data__BITNR) | \ - (R_IRQ_MASK1_SET__ser0_ready__##f19##__VAL(R_IRQ_MASK1_SET_, ser0_ready_, v19) << R_IRQ_MASK1_SET__ser0_ready__BITNR) | \ - (R_IRQ_MASK1_SET__ser0_data__##f20##__VAL(R_IRQ_MASK1_SET_, ser0_data_, v20) << R_IRQ_MASK1_SET__ser0_data__BITNR) | \ - (R_IRQ_MASK1_SET__pa7__##f21##__VAL(R_IRQ_MASK1_SET_, pa7_, v21) << R_IRQ_MASK1_SET__pa7__BITNR) | \ - (R_IRQ_MASK1_SET__pa6__##f22##__VAL(R_IRQ_MASK1_SET_, pa6_, v22) << R_IRQ_MASK1_SET__pa6__BITNR) | \ - (R_IRQ_MASK1_SET__pa5__##f23##__VAL(R_IRQ_MASK1_SET_, pa5_, v23) << R_IRQ_MASK1_SET__pa5__BITNR) | \ - (R_IRQ_MASK1_SET__pa4__##f24##__VAL(R_IRQ_MASK1_SET_, pa4_, v24) << R_IRQ_MASK1_SET__pa4__BITNR) | \ - (R_IRQ_MASK1_SET__pa3__##f25##__VAL(R_IRQ_MASK1_SET_, pa3_, v25) << R_IRQ_MASK1_SET__pa3__BITNR) | \ - (R_IRQ_MASK1_SET__pa2__##f26##__VAL(R_IRQ_MASK1_SET_, pa2_, v26) << R_IRQ_MASK1_SET__pa2__BITNR) | \ - (R_IRQ_MASK1_SET__pa1__##f27##__VAL(R_IRQ_MASK1_SET_, pa1_, v27) << R_IRQ_MASK1_SET__pa1__BITNR) | \ - (R_IRQ_MASK1_SET__pa0__##f28##__VAL(R_IRQ_MASK1_SET_, pa0_, v28) << R_IRQ_MASK1_SET__pa0__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_IRQ_MASK1_SET_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_IRQ_MASK1_SET. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_IRQ_MASK1_SET_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16,f17_,v17,f18_,v18,f19_,v19,f20_,v20,f21_,v21,f22_,v22,f23_,v23,f24_,v24,f25_,v25,f26_,v26,f27_,v27,f28_,v28) ( \ - (R_IRQ_MASK1_SET__sw_int7__##f1_##_VAL(R_IRQ_MASK1_SET_, sw_int7_, v1) << R_IRQ_MASK1_SET__sw_int7__BITNR) | \ - (R_IRQ_MASK1_SET__sw_int6__##f2_##_VAL(R_IRQ_MASK1_SET_, sw_int6_, v2) << R_IRQ_MASK1_SET__sw_int6__BITNR) | \ - (R_IRQ_MASK1_SET__sw_int5__##f3_##_VAL(R_IRQ_MASK1_SET_, sw_int5_, v3) << R_IRQ_MASK1_SET__sw_int5__BITNR) | \ - (R_IRQ_MASK1_SET__sw_int4__##f4_##_VAL(R_IRQ_MASK1_SET_, sw_int4_, v4) << R_IRQ_MASK1_SET__sw_int4__BITNR) | \ - (R_IRQ_MASK1_SET__sw_int3__##f5_##_VAL(R_IRQ_MASK1_SET_, sw_int3_, v5) << R_IRQ_MASK1_SET__sw_int3__BITNR) | \ - (R_IRQ_MASK1_SET__sw_int2__##f6_##_VAL(R_IRQ_MASK1_SET_, sw_int2_, v6) << R_IRQ_MASK1_SET__sw_int2__BITNR) | \ - (R_IRQ_MASK1_SET__sw_int1__##f7_##_VAL(R_IRQ_MASK1_SET_, sw_int1_, v7) << R_IRQ_MASK1_SET__sw_int1__BITNR) | \ - (R_IRQ_MASK1_SET__sw_int0__##f8_##_VAL(R_IRQ_MASK1_SET_, sw_int0_, v8) << R_IRQ_MASK1_SET__sw_int0__BITNR) | \ - (R_IRQ_MASK1_SET__par1_ecp_cmd__##f9_##_VAL(R_IRQ_MASK1_SET_, par1_ecp_cmd_, v9) << R_IRQ_MASK1_SET__par1_ecp_cmd__BITNR) | \ - (R_IRQ_MASK1_SET__par1_peri__##f10_##_VAL(R_IRQ_MASK1_SET_, par1_peri_, v10) << R_IRQ_MASK1_SET__par1_peri__BITNR) | \ - (R_IRQ_MASK1_SET__par1_data__##f11_##_VAL(R_IRQ_MASK1_SET_, par1_data_, v11) << R_IRQ_MASK1_SET__par1_data__BITNR) | \ - (R_IRQ_MASK1_SET__par1_ready__##f12_##_VAL(R_IRQ_MASK1_SET_, par1_ready_, v12) << R_IRQ_MASK1_SET__par1_ready__BITNR) | \ - (R_IRQ_MASK1_SET__ser3_ready__##f13_##_VAL(R_IRQ_MASK1_SET_, ser3_ready_, v13) << R_IRQ_MASK1_SET__ser3_ready__BITNR) | \ - (R_IRQ_MASK1_SET__ser3_data__##f14_##_VAL(R_IRQ_MASK1_SET_, ser3_data_, v14) << R_IRQ_MASK1_SET__ser3_data__BITNR) | \ - (R_IRQ_MASK1_SET__ser2_ready__##f15_##_VAL(R_IRQ_MASK1_SET_, ser2_ready_, v15) << R_IRQ_MASK1_SET__ser2_ready__BITNR) | \ - (R_IRQ_MASK1_SET__ser2_data__##f16_##_VAL(R_IRQ_MASK1_SET_, ser2_data_, v16) << R_IRQ_MASK1_SET__ser2_data__BITNR) | \ - (R_IRQ_MASK1_SET__ser1_ready__##f17_##_VAL(R_IRQ_MASK1_SET_, ser1_ready_, v17) << R_IRQ_MASK1_SET__ser1_ready__BITNR) | \ - (R_IRQ_MASK1_SET__ser1_data__##f18_##_VAL(R_IRQ_MASK1_SET_, ser1_data_, v18) << R_IRQ_MASK1_SET__ser1_data__BITNR) | \ - (R_IRQ_MASK1_SET__ser0_ready__##f19_##_VAL(R_IRQ_MASK1_SET_, ser0_ready_, v19) << R_IRQ_MASK1_SET__ser0_ready__BITNR) | \ - (R_IRQ_MASK1_SET__ser0_data__##f20_##_VAL(R_IRQ_MASK1_SET_, ser0_data_, v20) << R_IRQ_MASK1_SET__ser0_data__BITNR) | \ - (R_IRQ_MASK1_SET__pa7__##f21_##_VAL(R_IRQ_MASK1_SET_, pa7_, v21) << R_IRQ_MASK1_SET__pa7__BITNR) | \ - (R_IRQ_MASK1_SET__pa6__##f22_##_VAL(R_IRQ_MASK1_SET_, pa6_, v22) << R_IRQ_MASK1_SET__pa6__BITNR) | \ - (R_IRQ_MASK1_SET__pa5__##f23_##_VAL(R_IRQ_MASK1_SET_, pa5_, v23) << R_IRQ_MASK1_SET__pa5__BITNR) | \ - (R_IRQ_MASK1_SET__pa4__##f24_##_VAL(R_IRQ_MASK1_SET_, pa4_, v24) << R_IRQ_MASK1_SET__pa4__BITNR) | \ - (R_IRQ_MASK1_SET__pa3__##f25_##_VAL(R_IRQ_MASK1_SET_, pa3_, v25) << R_IRQ_MASK1_SET__pa3__BITNR) | \ - (R_IRQ_MASK1_SET__pa2__##f26_##_VAL(R_IRQ_MASK1_SET_, pa2_, v26) << R_IRQ_MASK1_SET__pa2__BITNR) | \ - (R_IRQ_MASK1_SET__pa1__##f27_##_VAL(R_IRQ_MASK1_SET_, pa1_, v27) << R_IRQ_MASK1_SET__pa1__BITNR) | \ - (R_IRQ_MASK1_SET__pa0__##f28_##_VAL(R_IRQ_MASK1_SET_, pa0_, v28) << R_IRQ_MASK1_SET__pa0__BITNR) \ -) - -#endif - -/* - * R_IRQ_MASK2_CLR - * - type: WO - * - addr: 0xb00000d0 - * - group: Interrupt mask and status registers - */ - -#if USE_GROUP__Interrupt_mask_and_status_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_IRQ_MASK2_CLR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_IRQ_MASK2_CLR. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_IRQ_MASK2_CLR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_IRQ_MASK2_CLR(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24) ( \ - *R_IRQ_MASK2_CLR__SADDR = ( \ - REG_INITIATED(R_IRQ_MASK2_CLR_) \ - REG_VAL__R_IRQ_MASK2_CLR_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20,f21##_,v21,f22##_,v22,f23##_,v23,f24##_,v24) \ - ), \ - R_IRQ_MASK2_CLR__WRITE(R_IRQ_MASK2_CLR__ADDR, *R_IRQ_MASK2_CLR__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_IRQ_MASK2_CLR__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_IRQ_MASK2_CLR. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_IRQ_MASK2_CLR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_IRQ_MASK2_CLR__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24) ( \ - *R_IRQ_MASK2_CLR__SADDR = ( \ - REG_INITIATED(R_IRQ_MASK2_CLR_) \ - REG_VAL__R_IRQ_MASK2_CLR_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20,f21##_,v21,f22##_,v22,f23##_,v23,f24##_,v24) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_IRQ_MASK2_CLR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_IRQ_MASK2_CLR(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24) ( \ - (R_IRQ_MASK2_CLR__dma8_sub3_descr__##f1##__MASK & REG__##v1) | \ - (R_IRQ_MASK2_CLR__dma8_sub2_descr__##f2##__MASK & REG__##v2) | \ - (R_IRQ_MASK2_CLR__dma8_sub1_descr__##f3##__MASK & REG__##v3) | \ - (R_IRQ_MASK2_CLR__dma8_sub0_descr__##f4##__MASK & REG__##v4) | \ - (R_IRQ_MASK2_CLR__dma9_eop__##f5##__MASK & REG__##v5) | \ - (R_IRQ_MASK2_CLR__dma9_descr__##f6##__MASK & REG__##v6) | \ - (R_IRQ_MASK2_CLR__dma8_eop__##f7##__MASK & REG__##v7) | \ - (R_IRQ_MASK2_CLR__dma8_descr__##f8##__MASK & REG__##v8) | \ - (R_IRQ_MASK2_CLR__dma7_eop__##f9##__MASK & REG__##v9) | \ - (R_IRQ_MASK2_CLR__dma7_descr__##f10##__MASK & REG__##v10) | \ - (R_IRQ_MASK2_CLR__dma6_eop__##f11##__MASK & REG__##v11) | \ - (R_IRQ_MASK2_CLR__dma6_descr__##f12##__MASK & REG__##v12) | \ - (R_IRQ_MASK2_CLR__dma5_eop__##f13##__MASK & REG__##v13) | \ - (R_IRQ_MASK2_CLR__dma5_descr__##f14##__MASK & REG__##v14) | \ - (R_IRQ_MASK2_CLR__dma4_eop__##f15##__MASK & REG__##v15) | \ - (R_IRQ_MASK2_CLR__dma4_descr__##f16##__MASK & REG__##v16) | \ - (R_IRQ_MASK2_CLR__dma3_eop__##f17##__MASK & REG__##v17) | \ - (R_IRQ_MASK2_CLR__dma3_descr__##f18##__MASK & REG__##v18) | \ - (R_IRQ_MASK2_CLR__dma2_eop__##f19##__MASK & REG__##v19) | \ - (R_IRQ_MASK2_CLR__dma2_descr__##f20##__MASK & REG__##v20) | \ - (R_IRQ_MASK2_CLR__dma1_eop__##f21##__MASK & REG__##v21) | \ - (R_IRQ_MASK2_CLR__dma1_descr__##f22##__MASK & REG__##v22) | \ - (R_IRQ_MASK2_CLR__dma0_eop__##f23##__MASK & REG__##v23) | \ - (R_IRQ_MASK2_CLR__dma0_descr__##f24##__MASK & REG__##v24) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_IRQ_MASK2_CLR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_IRQ_MASK2_CLR. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_IRQ_MASK2_CLR(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24) ( \ - (R_IRQ_MASK2_CLR__dma8_sub3_descr__##f1##__VAL(R_IRQ_MASK2_CLR_, dma8_sub3_descr_, v1) << R_IRQ_MASK2_CLR__dma8_sub3_descr__BITNR) | \ - (R_IRQ_MASK2_CLR__dma8_sub2_descr__##f2##__VAL(R_IRQ_MASK2_CLR_, dma8_sub2_descr_, v2) << R_IRQ_MASK2_CLR__dma8_sub2_descr__BITNR) | \ - (R_IRQ_MASK2_CLR__dma8_sub1_descr__##f3##__VAL(R_IRQ_MASK2_CLR_, dma8_sub1_descr_, v3) << R_IRQ_MASK2_CLR__dma8_sub1_descr__BITNR) | \ - (R_IRQ_MASK2_CLR__dma8_sub0_descr__##f4##__VAL(R_IRQ_MASK2_CLR_, dma8_sub0_descr_, v4) << R_IRQ_MASK2_CLR__dma8_sub0_descr__BITNR) | \ - (R_IRQ_MASK2_CLR__dma9_eop__##f5##__VAL(R_IRQ_MASK2_CLR_, dma9_eop_, v5) << R_IRQ_MASK2_CLR__dma9_eop__BITNR) | \ - (R_IRQ_MASK2_CLR__dma9_descr__##f6##__VAL(R_IRQ_MASK2_CLR_, dma9_descr_, v6) << R_IRQ_MASK2_CLR__dma9_descr__BITNR) | \ - (R_IRQ_MASK2_CLR__dma8_eop__##f7##__VAL(R_IRQ_MASK2_CLR_, dma8_eop_, v7) << R_IRQ_MASK2_CLR__dma8_eop__BITNR) | \ - (R_IRQ_MASK2_CLR__dma8_descr__##f8##__VAL(R_IRQ_MASK2_CLR_, dma8_descr_, v8) << R_IRQ_MASK2_CLR__dma8_descr__BITNR) | \ - (R_IRQ_MASK2_CLR__dma7_eop__##f9##__VAL(R_IRQ_MASK2_CLR_, dma7_eop_, v9) << R_IRQ_MASK2_CLR__dma7_eop__BITNR) | \ - (R_IRQ_MASK2_CLR__dma7_descr__##f10##__VAL(R_IRQ_MASK2_CLR_, dma7_descr_, v10) << R_IRQ_MASK2_CLR__dma7_descr__BITNR) | \ - (R_IRQ_MASK2_CLR__dma6_eop__##f11##__VAL(R_IRQ_MASK2_CLR_, dma6_eop_, v11) << R_IRQ_MASK2_CLR__dma6_eop__BITNR) | \ - (R_IRQ_MASK2_CLR__dma6_descr__##f12##__VAL(R_IRQ_MASK2_CLR_, dma6_descr_, v12) << R_IRQ_MASK2_CLR__dma6_descr__BITNR) | \ - (R_IRQ_MASK2_CLR__dma5_eop__##f13##__VAL(R_IRQ_MASK2_CLR_, dma5_eop_, v13) << R_IRQ_MASK2_CLR__dma5_eop__BITNR) | \ - (R_IRQ_MASK2_CLR__dma5_descr__##f14##__VAL(R_IRQ_MASK2_CLR_, dma5_descr_, v14) << R_IRQ_MASK2_CLR__dma5_descr__BITNR) | \ - (R_IRQ_MASK2_CLR__dma4_eop__##f15##__VAL(R_IRQ_MASK2_CLR_, dma4_eop_, v15) << R_IRQ_MASK2_CLR__dma4_eop__BITNR) | \ - (R_IRQ_MASK2_CLR__dma4_descr__##f16##__VAL(R_IRQ_MASK2_CLR_, dma4_descr_, v16) << R_IRQ_MASK2_CLR__dma4_descr__BITNR) | \ - (R_IRQ_MASK2_CLR__dma3_eop__##f17##__VAL(R_IRQ_MASK2_CLR_, dma3_eop_, v17) << R_IRQ_MASK2_CLR__dma3_eop__BITNR) | \ - (R_IRQ_MASK2_CLR__dma3_descr__##f18##__VAL(R_IRQ_MASK2_CLR_, dma3_descr_, v18) << R_IRQ_MASK2_CLR__dma3_descr__BITNR) | \ - (R_IRQ_MASK2_CLR__dma2_eop__##f19##__VAL(R_IRQ_MASK2_CLR_, dma2_eop_, v19) << R_IRQ_MASK2_CLR__dma2_eop__BITNR) | \ - (R_IRQ_MASK2_CLR__dma2_descr__##f20##__VAL(R_IRQ_MASK2_CLR_, dma2_descr_, v20) << R_IRQ_MASK2_CLR__dma2_descr__BITNR) | \ - (R_IRQ_MASK2_CLR__dma1_eop__##f21##__VAL(R_IRQ_MASK2_CLR_, dma1_eop_, v21) << R_IRQ_MASK2_CLR__dma1_eop__BITNR) | \ - (R_IRQ_MASK2_CLR__dma1_descr__##f22##__VAL(R_IRQ_MASK2_CLR_, dma1_descr_, v22) << R_IRQ_MASK2_CLR__dma1_descr__BITNR) | \ - (R_IRQ_MASK2_CLR__dma0_eop__##f23##__VAL(R_IRQ_MASK2_CLR_, dma0_eop_, v23) << R_IRQ_MASK2_CLR__dma0_eop__BITNR) | \ - (R_IRQ_MASK2_CLR__dma0_descr__##f24##__VAL(R_IRQ_MASK2_CLR_, dma0_descr_, v24) << R_IRQ_MASK2_CLR__dma0_descr__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_IRQ_MASK2_CLR_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_IRQ_MASK2_CLR. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_IRQ_MASK2_CLR_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16,f17_,v17,f18_,v18,f19_,v19,f20_,v20,f21_,v21,f22_,v22,f23_,v23,f24_,v24) ( \ - (R_IRQ_MASK2_CLR__dma8_sub3_descr__##f1_##_VAL(R_IRQ_MASK2_CLR_, dma8_sub3_descr_, v1) << R_IRQ_MASK2_CLR__dma8_sub3_descr__BITNR) | \ - (R_IRQ_MASK2_CLR__dma8_sub2_descr__##f2_##_VAL(R_IRQ_MASK2_CLR_, dma8_sub2_descr_, v2) << R_IRQ_MASK2_CLR__dma8_sub2_descr__BITNR) | \ - (R_IRQ_MASK2_CLR__dma8_sub1_descr__##f3_##_VAL(R_IRQ_MASK2_CLR_, dma8_sub1_descr_, v3) << R_IRQ_MASK2_CLR__dma8_sub1_descr__BITNR) | \ - (R_IRQ_MASK2_CLR__dma8_sub0_descr__##f4_##_VAL(R_IRQ_MASK2_CLR_, dma8_sub0_descr_, v4) << R_IRQ_MASK2_CLR__dma8_sub0_descr__BITNR) | \ - (R_IRQ_MASK2_CLR__dma9_eop__##f5_##_VAL(R_IRQ_MASK2_CLR_, dma9_eop_, v5) << R_IRQ_MASK2_CLR__dma9_eop__BITNR) | \ - (R_IRQ_MASK2_CLR__dma9_descr__##f6_##_VAL(R_IRQ_MASK2_CLR_, dma9_descr_, v6) << R_IRQ_MASK2_CLR__dma9_descr__BITNR) | \ - (R_IRQ_MASK2_CLR__dma8_eop__##f7_##_VAL(R_IRQ_MASK2_CLR_, dma8_eop_, v7) << R_IRQ_MASK2_CLR__dma8_eop__BITNR) | \ - (R_IRQ_MASK2_CLR__dma8_descr__##f8_##_VAL(R_IRQ_MASK2_CLR_, dma8_descr_, v8) << R_IRQ_MASK2_CLR__dma8_descr__BITNR) | \ - (R_IRQ_MASK2_CLR__dma7_eop__##f9_##_VAL(R_IRQ_MASK2_CLR_, dma7_eop_, v9) << R_IRQ_MASK2_CLR__dma7_eop__BITNR) | \ - (R_IRQ_MASK2_CLR__dma7_descr__##f10_##_VAL(R_IRQ_MASK2_CLR_, dma7_descr_, v10) << R_IRQ_MASK2_CLR__dma7_descr__BITNR) | \ - (R_IRQ_MASK2_CLR__dma6_eop__##f11_##_VAL(R_IRQ_MASK2_CLR_, dma6_eop_, v11) << R_IRQ_MASK2_CLR__dma6_eop__BITNR) | \ - (R_IRQ_MASK2_CLR__dma6_descr__##f12_##_VAL(R_IRQ_MASK2_CLR_, dma6_descr_, v12) << R_IRQ_MASK2_CLR__dma6_descr__BITNR) | \ - (R_IRQ_MASK2_CLR__dma5_eop__##f13_##_VAL(R_IRQ_MASK2_CLR_, dma5_eop_, v13) << R_IRQ_MASK2_CLR__dma5_eop__BITNR) | \ - (R_IRQ_MASK2_CLR__dma5_descr__##f14_##_VAL(R_IRQ_MASK2_CLR_, dma5_descr_, v14) << R_IRQ_MASK2_CLR__dma5_descr__BITNR) | \ - (R_IRQ_MASK2_CLR__dma4_eop__##f15_##_VAL(R_IRQ_MASK2_CLR_, dma4_eop_, v15) << R_IRQ_MASK2_CLR__dma4_eop__BITNR) | \ - (R_IRQ_MASK2_CLR__dma4_descr__##f16_##_VAL(R_IRQ_MASK2_CLR_, dma4_descr_, v16) << R_IRQ_MASK2_CLR__dma4_descr__BITNR) | \ - (R_IRQ_MASK2_CLR__dma3_eop__##f17_##_VAL(R_IRQ_MASK2_CLR_, dma3_eop_, v17) << R_IRQ_MASK2_CLR__dma3_eop__BITNR) | \ - (R_IRQ_MASK2_CLR__dma3_descr__##f18_##_VAL(R_IRQ_MASK2_CLR_, dma3_descr_, v18) << R_IRQ_MASK2_CLR__dma3_descr__BITNR) | \ - (R_IRQ_MASK2_CLR__dma2_eop__##f19_##_VAL(R_IRQ_MASK2_CLR_, dma2_eop_, v19) << R_IRQ_MASK2_CLR__dma2_eop__BITNR) | \ - (R_IRQ_MASK2_CLR__dma2_descr__##f20_##_VAL(R_IRQ_MASK2_CLR_, dma2_descr_, v20) << R_IRQ_MASK2_CLR__dma2_descr__BITNR) | \ - (R_IRQ_MASK2_CLR__dma1_eop__##f21_##_VAL(R_IRQ_MASK2_CLR_, dma1_eop_, v21) << R_IRQ_MASK2_CLR__dma1_eop__BITNR) | \ - (R_IRQ_MASK2_CLR__dma1_descr__##f22_##_VAL(R_IRQ_MASK2_CLR_, dma1_descr_, v22) << R_IRQ_MASK2_CLR__dma1_descr__BITNR) | \ - (R_IRQ_MASK2_CLR__dma0_eop__##f23_##_VAL(R_IRQ_MASK2_CLR_, dma0_eop_, v23) << R_IRQ_MASK2_CLR__dma0_eop__BITNR) | \ - (R_IRQ_MASK2_CLR__dma0_descr__##f24_##_VAL(R_IRQ_MASK2_CLR_, dma0_descr_, v24) << R_IRQ_MASK2_CLR__dma0_descr__BITNR) \ -) - -#endif - -/* - * R_IRQ_MASK2_RD - * - type: RO - * - addr: 0xb00000d0 - * - group: Interrupt mask and status registers - */ - -#if USE_GROUP__Interrupt_mask_and_status_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_IRQ_MASK2_RD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_IRQ_MASK2_RD(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24) ( \ - (R_IRQ_MASK2_RD__dma8_sub3_descr__##f1##__MASK & REG__##v1) | \ - (R_IRQ_MASK2_RD__dma8_sub2_descr__##f2##__MASK & REG__##v2) | \ - (R_IRQ_MASK2_RD__dma8_sub1_descr__##f3##__MASK & REG__##v3) | \ - (R_IRQ_MASK2_RD__dma8_sub0_descr__##f4##__MASK & REG__##v4) | \ - (R_IRQ_MASK2_RD__dma9_eop__##f5##__MASK & REG__##v5) | \ - (R_IRQ_MASK2_RD__dma9_descr__##f6##__MASK & REG__##v6) | \ - (R_IRQ_MASK2_RD__dma8_eop__##f7##__MASK & REG__##v7) | \ - (R_IRQ_MASK2_RD__dma8_descr__##f8##__MASK & REG__##v8) | \ - (R_IRQ_MASK2_RD__dma7_eop__##f9##__MASK & REG__##v9) | \ - (R_IRQ_MASK2_RD__dma7_descr__##f10##__MASK & REG__##v10) | \ - (R_IRQ_MASK2_RD__dma6_eop__##f11##__MASK & REG__##v11) | \ - (R_IRQ_MASK2_RD__dma6_descr__##f12##__MASK & REG__##v12) | \ - (R_IRQ_MASK2_RD__dma5_eop__##f13##__MASK & REG__##v13) | \ - (R_IRQ_MASK2_RD__dma5_descr__##f14##__MASK & REG__##v14) | \ - (R_IRQ_MASK2_RD__dma4_eop__##f15##__MASK & REG__##v15) | \ - (R_IRQ_MASK2_RD__dma4_descr__##f16##__MASK & REG__##v16) | \ - (R_IRQ_MASK2_RD__dma3_eop__##f17##__MASK & REG__##v17) | \ - (R_IRQ_MASK2_RD__dma3_descr__##f18##__MASK & REG__##v18) | \ - (R_IRQ_MASK2_RD__dma2_eop__##f19##__MASK & REG__##v19) | \ - (R_IRQ_MASK2_RD__dma2_descr__##f20##__MASK & REG__##v20) | \ - (R_IRQ_MASK2_RD__dma1_eop__##f21##__MASK & REG__##v21) | \ - (R_IRQ_MASK2_RD__dma1_descr__##f22##__MASK & REG__##v22) | \ - (R_IRQ_MASK2_RD__dma0_eop__##f23##__MASK & REG__##v23) | \ - (R_IRQ_MASK2_RD__dma0_descr__##f24##__MASK & REG__##v24) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_IRQ_MASK2_RD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_IRQ_MASK2_RD. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_IRQ_MASK2_RD(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24) ( \ - (R_IRQ_MASK2_RD__dma8_sub3_descr__##f1##__VAL(R_IRQ_MASK2_RD_, dma8_sub3_descr_, v1) << R_IRQ_MASK2_RD__dma8_sub3_descr__BITNR) | \ - (R_IRQ_MASK2_RD__dma8_sub2_descr__##f2##__VAL(R_IRQ_MASK2_RD_, dma8_sub2_descr_, v2) << R_IRQ_MASK2_RD__dma8_sub2_descr__BITNR) | \ - (R_IRQ_MASK2_RD__dma8_sub1_descr__##f3##__VAL(R_IRQ_MASK2_RD_, dma8_sub1_descr_, v3) << R_IRQ_MASK2_RD__dma8_sub1_descr__BITNR) | \ - (R_IRQ_MASK2_RD__dma8_sub0_descr__##f4##__VAL(R_IRQ_MASK2_RD_, dma8_sub0_descr_, v4) << R_IRQ_MASK2_RD__dma8_sub0_descr__BITNR) | \ - (R_IRQ_MASK2_RD__dma9_eop__##f5##__VAL(R_IRQ_MASK2_RD_, dma9_eop_, v5) << R_IRQ_MASK2_RD__dma9_eop__BITNR) | \ - (R_IRQ_MASK2_RD__dma9_descr__##f6##__VAL(R_IRQ_MASK2_RD_, dma9_descr_, v6) << R_IRQ_MASK2_RD__dma9_descr__BITNR) | \ - (R_IRQ_MASK2_RD__dma8_eop__##f7##__VAL(R_IRQ_MASK2_RD_, dma8_eop_, v7) << R_IRQ_MASK2_RD__dma8_eop__BITNR) | \ - (R_IRQ_MASK2_RD__dma8_descr__##f8##__VAL(R_IRQ_MASK2_RD_, dma8_descr_, v8) << R_IRQ_MASK2_RD__dma8_descr__BITNR) | \ - (R_IRQ_MASK2_RD__dma7_eop__##f9##__VAL(R_IRQ_MASK2_RD_, dma7_eop_, v9) << R_IRQ_MASK2_RD__dma7_eop__BITNR) | \ - (R_IRQ_MASK2_RD__dma7_descr__##f10##__VAL(R_IRQ_MASK2_RD_, dma7_descr_, v10) << R_IRQ_MASK2_RD__dma7_descr__BITNR) | \ - (R_IRQ_MASK2_RD__dma6_eop__##f11##__VAL(R_IRQ_MASK2_RD_, dma6_eop_, v11) << R_IRQ_MASK2_RD__dma6_eop__BITNR) | \ - (R_IRQ_MASK2_RD__dma6_descr__##f12##__VAL(R_IRQ_MASK2_RD_, dma6_descr_, v12) << R_IRQ_MASK2_RD__dma6_descr__BITNR) | \ - (R_IRQ_MASK2_RD__dma5_eop__##f13##__VAL(R_IRQ_MASK2_RD_, dma5_eop_, v13) << R_IRQ_MASK2_RD__dma5_eop__BITNR) | \ - (R_IRQ_MASK2_RD__dma5_descr__##f14##__VAL(R_IRQ_MASK2_RD_, dma5_descr_, v14) << R_IRQ_MASK2_RD__dma5_descr__BITNR) | \ - (R_IRQ_MASK2_RD__dma4_eop__##f15##__VAL(R_IRQ_MASK2_RD_, dma4_eop_, v15) << R_IRQ_MASK2_RD__dma4_eop__BITNR) | \ - (R_IRQ_MASK2_RD__dma4_descr__##f16##__VAL(R_IRQ_MASK2_RD_, dma4_descr_, v16) << R_IRQ_MASK2_RD__dma4_descr__BITNR) | \ - (R_IRQ_MASK2_RD__dma3_eop__##f17##__VAL(R_IRQ_MASK2_RD_, dma3_eop_, v17) << R_IRQ_MASK2_RD__dma3_eop__BITNR) | \ - (R_IRQ_MASK2_RD__dma3_descr__##f18##__VAL(R_IRQ_MASK2_RD_, dma3_descr_, v18) << R_IRQ_MASK2_RD__dma3_descr__BITNR) | \ - (R_IRQ_MASK2_RD__dma2_eop__##f19##__VAL(R_IRQ_MASK2_RD_, dma2_eop_, v19) << R_IRQ_MASK2_RD__dma2_eop__BITNR) | \ - (R_IRQ_MASK2_RD__dma2_descr__##f20##__VAL(R_IRQ_MASK2_RD_, dma2_descr_, v20) << R_IRQ_MASK2_RD__dma2_descr__BITNR) | \ - (R_IRQ_MASK2_RD__dma1_eop__##f21##__VAL(R_IRQ_MASK2_RD_, dma1_eop_, v21) << R_IRQ_MASK2_RD__dma1_eop__BITNR) | \ - (R_IRQ_MASK2_RD__dma1_descr__##f22##__VAL(R_IRQ_MASK2_RD_, dma1_descr_, v22) << R_IRQ_MASK2_RD__dma1_descr__BITNR) | \ - (R_IRQ_MASK2_RD__dma0_eop__##f23##__VAL(R_IRQ_MASK2_RD_, dma0_eop_, v23) << R_IRQ_MASK2_RD__dma0_eop__BITNR) | \ - (R_IRQ_MASK2_RD__dma0_descr__##f24##__VAL(R_IRQ_MASK2_RD_, dma0_descr_, v24) << R_IRQ_MASK2_RD__dma0_descr__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_IRQ_MASK2_RD_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_IRQ_MASK2_RD. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_IRQ_MASK2_RD_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16,f17_,v17,f18_,v18,f19_,v19,f20_,v20,f21_,v21,f22_,v22,f23_,v23,f24_,v24) ( \ - (R_IRQ_MASK2_RD__dma8_sub3_descr__##f1_##_VAL(R_IRQ_MASK2_RD_, dma8_sub3_descr_, v1) << R_IRQ_MASK2_RD__dma8_sub3_descr__BITNR) | \ - (R_IRQ_MASK2_RD__dma8_sub2_descr__##f2_##_VAL(R_IRQ_MASK2_RD_, dma8_sub2_descr_, v2) << R_IRQ_MASK2_RD__dma8_sub2_descr__BITNR) | \ - (R_IRQ_MASK2_RD__dma8_sub1_descr__##f3_##_VAL(R_IRQ_MASK2_RD_, dma8_sub1_descr_, v3) << R_IRQ_MASK2_RD__dma8_sub1_descr__BITNR) | \ - (R_IRQ_MASK2_RD__dma8_sub0_descr__##f4_##_VAL(R_IRQ_MASK2_RD_, dma8_sub0_descr_, v4) << R_IRQ_MASK2_RD__dma8_sub0_descr__BITNR) | \ - (R_IRQ_MASK2_RD__dma9_eop__##f5_##_VAL(R_IRQ_MASK2_RD_, dma9_eop_, v5) << R_IRQ_MASK2_RD__dma9_eop__BITNR) | \ - (R_IRQ_MASK2_RD__dma9_descr__##f6_##_VAL(R_IRQ_MASK2_RD_, dma9_descr_, v6) << R_IRQ_MASK2_RD__dma9_descr__BITNR) | \ - (R_IRQ_MASK2_RD__dma8_eop__##f7_##_VAL(R_IRQ_MASK2_RD_, dma8_eop_, v7) << R_IRQ_MASK2_RD__dma8_eop__BITNR) | \ - (R_IRQ_MASK2_RD__dma8_descr__##f8_##_VAL(R_IRQ_MASK2_RD_, dma8_descr_, v8) << R_IRQ_MASK2_RD__dma8_descr__BITNR) | \ - (R_IRQ_MASK2_RD__dma7_eop__##f9_##_VAL(R_IRQ_MASK2_RD_, dma7_eop_, v9) << R_IRQ_MASK2_RD__dma7_eop__BITNR) | \ - (R_IRQ_MASK2_RD__dma7_descr__##f10_##_VAL(R_IRQ_MASK2_RD_, dma7_descr_, v10) << R_IRQ_MASK2_RD__dma7_descr__BITNR) | \ - (R_IRQ_MASK2_RD__dma6_eop__##f11_##_VAL(R_IRQ_MASK2_RD_, dma6_eop_, v11) << R_IRQ_MASK2_RD__dma6_eop__BITNR) | \ - (R_IRQ_MASK2_RD__dma6_descr__##f12_##_VAL(R_IRQ_MASK2_RD_, dma6_descr_, v12) << R_IRQ_MASK2_RD__dma6_descr__BITNR) | \ - (R_IRQ_MASK2_RD__dma5_eop__##f13_##_VAL(R_IRQ_MASK2_RD_, dma5_eop_, v13) << R_IRQ_MASK2_RD__dma5_eop__BITNR) | \ - (R_IRQ_MASK2_RD__dma5_descr__##f14_##_VAL(R_IRQ_MASK2_RD_, dma5_descr_, v14) << R_IRQ_MASK2_RD__dma5_descr__BITNR) | \ - (R_IRQ_MASK2_RD__dma4_eop__##f15_##_VAL(R_IRQ_MASK2_RD_, dma4_eop_, v15) << R_IRQ_MASK2_RD__dma4_eop__BITNR) | \ - (R_IRQ_MASK2_RD__dma4_descr__##f16_##_VAL(R_IRQ_MASK2_RD_, dma4_descr_, v16) << R_IRQ_MASK2_RD__dma4_descr__BITNR) | \ - (R_IRQ_MASK2_RD__dma3_eop__##f17_##_VAL(R_IRQ_MASK2_RD_, dma3_eop_, v17) << R_IRQ_MASK2_RD__dma3_eop__BITNR) | \ - (R_IRQ_MASK2_RD__dma3_descr__##f18_##_VAL(R_IRQ_MASK2_RD_, dma3_descr_, v18) << R_IRQ_MASK2_RD__dma3_descr__BITNR) | \ - (R_IRQ_MASK2_RD__dma2_eop__##f19_##_VAL(R_IRQ_MASK2_RD_, dma2_eop_, v19) << R_IRQ_MASK2_RD__dma2_eop__BITNR) | \ - (R_IRQ_MASK2_RD__dma2_descr__##f20_##_VAL(R_IRQ_MASK2_RD_, dma2_descr_, v20) << R_IRQ_MASK2_RD__dma2_descr__BITNR) | \ - (R_IRQ_MASK2_RD__dma1_eop__##f21_##_VAL(R_IRQ_MASK2_RD_, dma1_eop_, v21) << R_IRQ_MASK2_RD__dma1_eop__BITNR) | \ - (R_IRQ_MASK2_RD__dma1_descr__##f22_##_VAL(R_IRQ_MASK2_RD_, dma1_descr_, v22) << R_IRQ_MASK2_RD__dma1_descr__BITNR) | \ - (R_IRQ_MASK2_RD__dma0_eop__##f23_##_VAL(R_IRQ_MASK2_RD_, dma0_eop_, v23) << R_IRQ_MASK2_RD__dma0_eop__BITNR) | \ - (R_IRQ_MASK2_RD__dma0_descr__##f24_##_VAL(R_IRQ_MASK2_RD_, dma0_descr_, v24) << R_IRQ_MASK2_RD__dma0_descr__BITNR) \ -) - -#endif - -/* - * R_IRQ_MASK2_SET - * - type: WO - * - addr: 0xb00000d4 - * - group: Interrupt mask and status registers - */ - -#if USE_GROUP__Interrupt_mask_and_status_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_IRQ_MASK2_SET -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_IRQ_MASK2_SET. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_IRQ_MASK2_SET. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_IRQ_MASK2_SET(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24) ( \ - *R_IRQ_MASK2_SET__SADDR = ( \ - REG_INITIATED(R_IRQ_MASK2_SET_) \ - REG_VAL__R_IRQ_MASK2_SET_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20,f21##_,v21,f22##_,v22,f23##_,v23,f24##_,v24) \ - ), \ - R_IRQ_MASK2_SET__WRITE(R_IRQ_MASK2_SET__ADDR, *R_IRQ_MASK2_SET__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_IRQ_MASK2_SET__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_IRQ_MASK2_SET. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_IRQ_MASK2_SET. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_IRQ_MASK2_SET__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24) ( \ - *R_IRQ_MASK2_SET__SADDR = ( \ - REG_INITIATED(R_IRQ_MASK2_SET_) \ - REG_VAL__R_IRQ_MASK2_SET_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20,f21##_,v21,f22##_,v22,f23##_,v23,f24##_,v24) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_IRQ_MASK2_SET -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_IRQ_MASK2_SET(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24) ( \ - (R_IRQ_MASK2_SET__dma8_sub3_descr__##f1##__MASK & REG__##v1) | \ - (R_IRQ_MASK2_SET__dma8_sub2_descr__##f2##__MASK & REG__##v2) | \ - (R_IRQ_MASK2_SET__dma8_sub1_descr__##f3##__MASK & REG__##v3) | \ - (R_IRQ_MASK2_SET__dma8_sub0_descr__##f4##__MASK & REG__##v4) | \ - (R_IRQ_MASK2_SET__dma9_eop__##f5##__MASK & REG__##v5) | \ - (R_IRQ_MASK2_SET__dma9_descr__##f6##__MASK & REG__##v6) | \ - (R_IRQ_MASK2_SET__dma8_eop__##f7##__MASK & REG__##v7) | \ - (R_IRQ_MASK2_SET__dma8_descr__##f8##__MASK & REG__##v8) | \ - (R_IRQ_MASK2_SET__dma7_eop__##f9##__MASK & REG__##v9) | \ - (R_IRQ_MASK2_SET__dma7_descr__##f10##__MASK & REG__##v10) | \ - (R_IRQ_MASK2_SET__dma6_eop__##f11##__MASK & REG__##v11) | \ - (R_IRQ_MASK2_SET__dma6_descr__##f12##__MASK & REG__##v12) | \ - (R_IRQ_MASK2_SET__dma5_eop__##f13##__MASK & REG__##v13) | \ - (R_IRQ_MASK2_SET__dma5_descr__##f14##__MASK & REG__##v14) | \ - (R_IRQ_MASK2_SET__dma4_eop__##f15##__MASK & REG__##v15) | \ - (R_IRQ_MASK2_SET__dma4_descr__##f16##__MASK & REG__##v16) | \ - (R_IRQ_MASK2_SET__dma3_eop__##f17##__MASK & REG__##v17) | \ - (R_IRQ_MASK2_SET__dma3_descr__##f18##__MASK & REG__##v18) | \ - (R_IRQ_MASK2_SET__dma2_eop__##f19##__MASK & REG__##v19) | \ - (R_IRQ_MASK2_SET__dma2_descr__##f20##__MASK & REG__##v20) | \ - (R_IRQ_MASK2_SET__dma1_eop__##f21##__MASK & REG__##v21) | \ - (R_IRQ_MASK2_SET__dma1_descr__##f22##__MASK & REG__##v22) | \ - (R_IRQ_MASK2_SET__dma0_eop__##f23##__MASK & REG__##v23) | \ - (R_IRQ_MASK2_SET__dma0_descr__##f24##__MASK & REG__##v24) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_IRQ_MASK2_SET -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_IRQ_MASK2_SET. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_IRQ_MASK2_SET(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24) ( \ - (R_IRQ_MASK2_SET__dma8_sub3_descr__##f1##__VAL(R_IRQ_MASK2_SET_, dma8_sub3_descr_, v1) << R_IRQ_MASK2_SET__dma8_sub3_descr__BITNR) | \ - (R_IRQ_MASK2_SET__dma8_sub2_descr__##f2##__VAL(R_IRQ_MASK2_SET_, dma8_sub2_descr_, v2) << R_IRQ_MASK2_SET__dma8_sub2_descr__BITNR) | \ - (R_IRQ_MASK2_SET__dma8_sub1_descr__##f3##__VAL(R_IRQ_MASK2_SET_, dma8_sub1_descr_, v3) << R_IRQ_MASK2_SET__dma8_sub1_descr__BITNR) | \ - (R_IRQ_MASK2_SET__dma8_sub0_descr__##f4##__VAL(R_IRQ_MASK2_SET_, dma8_sub0_descr_, v4) << R_IRQ_MASK2_SET__dma8_sub0_descr__BITNR) | \ - (R_IRQ_MASK2_SET__dma9_eop__##f5##__VAL(R_IRQ_MASK2_SET_, dma9_eop_, v5) << R_IRQ_MASK2_SET__dma9_eop__BITNR) | \ - (R_IRQ_MASK2_SET__dma9_descr__##f6##__VAL(R_IRQ_MASK2_SET_, dma9_descr_, v6) << R_IRQ_MASK2_SET__dma9_descr__BITNR) | \ - (R_IRQ_MASK2_SET__dma8_eop__##f7##__VAL(R_IRQ_MASK2_SET_, dma8_eop_, v7) << R_IRQ_MASK2_SET__dma8_eop__BITNR) | \ - (R_IRQ_MASK2_SET__dma8_descr__##f8##__VAL(R_IRQ_MASK2_SET_, dma8_descr_, v8) << R_IRQ_MASK2_SET__dma8_descr__BITNR) | \ - (R_IRQ_MASK2_SET__dma7_eop__##f9##__VAL(R_IRQ_MASK2_SET_, dma7_eop_, v9) << R_IRQ_MASK2_SET__dma7_eop__BITNR) | \ - (R_IRQ_MASK2_SET__dma7_descr__##f10##__VAL(R_IRQ_MASK2_SET_, dma7_descr_, v10) << R_IRQ_MASK2_SET__dma7_descr__BITNR) | \ - (R_IRQ_MASK2_SET__dma6_eop__##f11##__VAL(R_IRQ_MASK2_SET_, dma6_eop_, v11) << R_IRQ_MASK2_SET__dma6_eop__BITNR) | \ - (R_IRQ_MASK2_SET__dma6_descr__##f12##__VAL(R_IRQ_MASK2_SET_, dma6_descr_, v12) << R_IRQ_MASK2_SET__dma6_descr__BITNR) | \ - (R_IRQ_MASK2_SET__dma5_eop__##f13##__VAL(R_IRQ_MASK2_SET_, dma5_eop_, v13) << R_IRQ_MASK2_SET__dma5_eop__BITNR) | \ - (R_IRQ_MASK2_SET__dma5_descr__##f14##__VAL(R_IRQ_MASK2_SET_, dma5_descr_, v14) << R_IRQ_MASK2_SET__dma5_descr__BITNR) | \ - (R_IRQ_MASK2_SET__dma4_eop__##f15##__VAL(R_IRQ_MASK2_SET_, dma4_eop_, v15) << R_IRQ_MASK2_SET__dma4_eop__BITNR) | \ - (R_IRQ_MASK2_SET__dma4_descr__##f16##__VAL(R_IRQ_MASK2_SET_, dma4_descr_, v16) << R_IRQ_MASK2_SET__dma4_descr__BITNR) | \ - (R_IRQ_MASK2_SET__dma3_eop__##f17##__VAL(R_IRQ_MASK2_SET_, dma3_eop_, v17) << R_IRQ_MASK2_SET__dma3_eop__BITNR) | \ - (R_IRQ_MASK2_SET__dma3_descr__##f18##__VAL(R_IRQ_MASK2_SET_, dma3_descr_, v18) << R_IRQ_MASK2_SET__dma3_descr__BITNR) | \ - (R_IRQ_MASK2_SET__dma2_eop__##f19##__VAL(R_IRQ_MASK2_SET_, dma2_eop_, v19) << R_IRQ_MASK2_SET__dma2_eop__BITNR) | \ - (R_IRQ_MASK2_SET__dma2_descr__##f20##__VAL(R_IRQ_MASK2_SET_, dma2_descr_, v20) << R_IRQ_MASK2_SET__dma2_descr__BITNR) | \ - (R_IRQ_MASK2_SET__dma1_eop__##f21##__VAL(R_IRQ_MASK2_SET_, dma1_eop_, v21) << R_IRQ_MASK2_SET__dma1_eop__BITNR) | \ - (R_IRQ_MASK2_SET__dma1_descr__##f22##__VAL(R_IRQ_MASK2_SET_, dma1_descr_, v22) << R_IRQ_MASK2_SET__dma1_descr__BITNR) | \ - (R_IRQ_MASK2_SET__dma0_eop__##f23##__VAL(R_IRQ_MASK2_SET_, dma0_eop_, v23) << R_IRQ_MASK2_SET__dma0_eop__BITNR) | \ - (R_IRQ_MASK2_SET__dma0_descr__##f24##__VAL(R_IRQ_MASK2_SET_, dma0_descr_, v24) << R_IRQ_MASK2_SET__dma0_descr__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_IRQ_MASK2_SET_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_IRQ_MASK2_SET. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_IRQ_MASK2_SET_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16,f17_,v17,f18_,v18,f19_,v19,f20_,v20,f21_,v21,f22_,v22,f23_,v23,f24_,v24) ( \ - (R_IRQ_MASK2_SET__dma8_sub3_descr__##f1_##_VAL(R_IRQ_MASK2_SET_, dma8_sub3_descr_, v1) << R_IRQ_MASK2_SET__dma8_sub3_descr__BITNR) | \ - (R_IRQ_MASK2_SET__dma8_sub2_descr__##f2_##_VAL(R_IRQ_MASK2_SET_, dma8_sub2_descr_, v2) << R_IRQ_MASK2_SET__dma8_sub2_descr__BITNR) | \ - (R_IRQ_MASK2_SET__dma8_sub1_descr__##f3_##_VAL(R_IRQ_MASK2_SET_, dma8_sub1_descr_, v3) << R_IRQ_MASK2_SET__dma8_sub1_descr__BITNR) | \ - (R_IRQ_MASK2_SET__dma8_sub0_descr__##f4_##_VAL(R_IRQ_MASK2_SET_, dma8_sub0_descr_, v4) << R_IRQ_MASK2_SET__dma8_sub0_descr__BITNR) | \ - (R_IRQ_MASK2_SET__dma9_eop__##f5_##_VAL(R_IRQ_MASK2_SET_, dma9_eop_, v5) << R_IRQ_MASK2_SET__dma9_eop__BITNR) | \ - (R_IRQ_MASK2_SET__dma9_descr__##f6_##_VAL(R_IRQ_MASK2_SET_, dma9_descr_, v6) << R_IRQ_MASK2_SET__dma9_descr__BITNR) | \ - (R_IRQ_MASK2_SET__dma8_eop__##f7_##_VAL(R_IRQ_MASK2_SET_, dma8_eop_, v7) << R_IRQ_MASK2_SET__dma8_eop__BITNR) | \ - (R_IRQ_MASK2_SET__dma8_descr__##f8_##_VAL(R_IRQ_MASK2_SET_, dma8_descr_, v8) << R_IRQ_MASK2_SET__dma8_descr__BITNR) | \ - (R_IRQ_MASK2_SET__dma7_eop__##f9_##_VAL(R_IRQ_MASK2_SET_, dma7_eop_, v9) << R_IRQ_MASK2_SET__dma7_eop__BITNR) | \ - (R_IRQ_MASK2_SET__dma7_descr__##f10_##_VAL(R_IRQ_MASK2_SET_, dma7_descr_, v10) << R_IRQ_MASK2_SET__dma7_descr__BITNR) | \ - (R_IRQ_MASK2_SET__dma6_eop__##f11_##_VAL(R_IRQ_MASK2_SET_, dma6_eop_, v11) << R_IRQ_MASK2_SET__dma6_eop__BITNR) | \ - (R_IRQ_MASK2_SET__dma6_descr__##f12_##_VAL(R_IRQ_MASK2_SET_, dma6_descr_, v12) << R_IRQ_MASK2_SET__dma6_descr__BITNR) | \ - (R_IRQ_MASK2_SET__dma5_eop__##f13_##_VAL(R_IRQ_MASK2_SET_, dma5_eop_, v13) << R_IRQ_MASK2_SET__dma5_eop__BITNR) | \ - (R_IRQ_MASK2_SET__dma5_descr__##f14_##_VAL(R_IRQ_MASK2_SET_, dma5_descr_, v14) << R_IRQ_MASK2_SET__dma5_descr__BITNR) | \ - (R_IRQ_MASK2_SET__dma4_eop__##f15_##_VAL(R_IRQ_MASK2_SET_, dma4_eop_, v15) << R_IRQ_MASK2_SET__dma4_eop__BITNR) | \ - (R_IRQ_MASK2_SET__dma4_descr__##f16_##_VAL(R_IRQ_MASK2_SET_, dma4_descr_, v16) << R_IRQ_MASK2_SET__dma4_descr__BITNR) | \ - (R_IRQ_MASK2_SET__dma3_eop__##f17_##_VAL(R_IRQ_MASK2_SET_, dma3_eop_, v17) << R_IRQ_MASK2_SET__dma3_eop__BITNR) | \ - (R_IRQ_MASK2_SET__dma3_descr__##f18_##_VAL(R_IRQ_MASK2_SET_, dma3_descr_, v18) << R_IRQ_MASK2_SET__dma3_descr__BITNR) | \ - (R_IRQ_MASK2_SET__dma2_eop__##f19_##_VAL(R_IRQ_MASK2_SET_, dma2_eop_, v19) << R_IRQ_MASK2_SET__dma2_eop__BITNR) | \ - (R_IRQ_MASK2_SET__dma2_descr__##f20_##_VAL(R_IRQ_MASK2_SET_, dma2_descr_, v20) << R_IRQ_MASK2_SET__dma2_descr__BITNR) | \ - (R_IRQ_MASK2_SET__dma1_eop__##f21_##_VAL(R_IRQ_MASK2_SET_, dma1_eop_, v21) << R_IRQ_MASK2_SET__dma1_eop__BITNR) | \ - (R_IRQ_MASK2_SET__dma1_descr__##f22_##_VAL(R_IRQ_MASK2_SET_, dma1_descr_, v22) << R_IRQ_MASK2_SET__dma1_descr__BITNR) | \ - (R_IRQ_MASK2_SET__dma0_eop__##f23_##_VAL(R_IRQ_MASK2_SET_, dma0_eop_, v23) << R_IRQ_MASK2_SET__dma0_eop__BITNR) | \ - (R_IRQ_MASK2_SET__dma0_descr__##f24_##_VAL(R_IRQ_MASK2_SET_, dma0_descr_, v24) << R_IRQ_MASK2_SET__dma0_descr__BITNR) \ -) - -#endif - -/* - * R_IRQ_READ0 - * - type: RO - * - addr: 0xb00000c4 - * - group: Interrupt mask and status registers - */ - -#if USE_GROUP__Interrupt_mask_and_status_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_IRQ_READ0 -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_IRQ_READ0(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25,f26,v26,f27,v27,f28,v28,f29,v29,f30,v30,f31,v31) ( \ - (R_IRQ_READ0__nmi_pin__##f1##__MASK & REG__##v1) | \ - (R_IRQ_READ0__watchdog_nmi__##f2##__MASK & REG__##v2) | \ - (R_IRQ_READ0__sqe_test_error__##f3##__MASK & REG__##v3) | \ - (R_IRQ_READ0__carrier_loss__##f4##__MASK & REG__##v4) | \ - (R_IRQ_READ0__deferred__##f5##__MASK & REG__##v5) | \ - (R_IRQ_READ0__late_col__##f6##__MASK & REG__##v6) | \ - (R_IRQ_READ0__multiple_col__##f7##__MASK & REG__##v7) | \ - (R_IRQ_READ0__single_col__##f8##__MASK & REG__##v8) | \ - (R_IRQ_READ0__congestion__##f9##__MASK & REG__##v9) | \ - (R_IRQ_READ0__oversize__##f10##__MASK & REG__##v10) | \ - (R_IRQ_READ0__alignment_error__##f11##__MASK & REG__##v11) | \ - (R_IRQ_READ0__crc_error__##f12##__MASK & REG__##v12) | \ - (R_IRQ_READ0__overrun__##f13##__MASK & REG__##v13) | \ - (R_IRQ_READ0__underrun__##f14##__MASK & REG__##v14) | \ - (R_IRQ_READ0__excessive_col__##f15##__MASK & REG__##v15) | \ - (R_IRQ_READ0__mdio__##f16##__MASK & REG__##v16) | \ - (R_IRQ_READ0__ata_drq3__##f17##__MASK & REG__##v17) | \ - (R_IRQ_READ0__ata_drq2__##f18##__MASK & REG__##v18) | \ - (R_IRQ_READ0__ata_drq1__##f19##__MASK & REG__##v19) | \ - (R_IRQ_READ0__ata_drq0__##f20##__MASK & REG__##v20) | \ - (R_IRQ_READ0__par0_ecp_cmd__##f21##__MASK & REG__##v21) | \ - (R_IRQ_READ0__par0_peri__##f22##__MASK & REG__##v22) | \ - (R_IRQ_READ0__par0_data__##f23##__MASK & REG__##v23) | \ - (R_IRQ_READ0__par0_ready__##f24##__MASK & REG__##v24) | \ - (R_IRQ_READ0__ata_dmaend__##f25##__MASK & REG__##v25) | \ - (R_IRQ_READ0__irq_ext_vector_nr__##f26##__MASK & REG__##v26) | \ - (R_IRQ_READ0__irq_int_vector_nr__##f27##__MASK & REG__##v27) | \ - (R_IRQ_READ0__ext_dma1__##f28##__MASK & REG__##v28) | \ - (R_IRQ_READ0__ext_dma0__##f29##__MASK & REG__##v29) | \ - (R_IRQ_READ0__timer1__##f30##__MASK & REG__##v30) | \ - (R_IRQ_READ0__timer0__##f31##__MASK & REG__##v31) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_IRQ_READ0 -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_IRQ_READ0. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_IRQ_READ0(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25,f26,v26,f27,v27,f28,v28,f29,v29,f30,v30,f31,v31) ( \ - (R_IRQ_READ0__nmi_pin__##f1##__VAL(R_IRQ_READ0_, nmi_pin_, v1) << R_IRQ_READ0__nmi_pin__BITNR) | \ - (R_IRQ_READ0__watchdog_nmi__##f2##__VAL(R_IRQ_READ0_, watchdog_nmi_, v2) << R_IRQ_READ0__watchdog_nmi__BITNR) | \ - (R_IRQ_READ0__sqe_test_error__##f3##__VAL(R_IRQ_READ0_, sqe_test_error_, v3) << R_IRQ_READ0__sqe_test_error__BITNR) | \ - (R_IRQ_READ0__carrier_loss__##f4##__VAL(R_IRQ_READ0_, carrier_loss_, v4) << R_IRQ_READ0__carrier_loss__BITNR) | \ - (R_IRQ_READ0__deferred__##f5##__VAL(R_IRQ_READ0_, deferred_, v5) << R_IRQ_READ0__deferred__BITNR) | \ - (R_IRQ_READ0__late_col__##f6##__VAL(R_IRQ_READ0_, late_col_, v6) << R_IRQ_READ0__late_col__BITNR) | \ - (R_IRQ_READ0__multiple_col__##f7##__VAL(R_IRQ_READ0_, multiple_col_, v7) << R_IRQ_READ0__multiple_col__BITNR) | \ - (R_IRQ_READ0__single_col__##f8##__VAL(R_IRQ_READ0_, single_col_, v8) << R_IRQ_READ0__single_col__BITNR) | \ - (R_IRQ_READ0__congestion__##f9##__VAL(R_IRQ_READ0_, congestion_, v9) << R_IRQ_READ0__congestion__BITNR) | \ - (R_IRQ_READ0__oversize__##f10##__VAL(R_IRQ_READ0_, oversize_, v10) << R_IRQ_READ0__oversize__BITNR) | \ - (R_IRQ_READ0__alignment_error__##f11##__VAL(R_IRQ_READ0_, alignment_error_, v11) << R_IRQ_READ0__alignment_error__BITNR) | \ - (R_IRQ_READ0__crc_error__##f12##__VAL(R_IRQ_READ0_, crc_error_, v12) << R_IRQ_READ0__crc_error__BITNR) | \ - (R_IRQ_READ0__overrun__##f13##__VAL(R_IRQ_READ0_, overrun_, v13) << R_IRQ_READ0__overrun__BITNR) | \ - (R_IRQ_READ0__underrun__##f14##__VAL(R_IRQ_READ0_, underrun_, v14) << R_IRQ_READ0__underrun__BITNR) | \ - (R_IRQ_READ0__excessive_col__##f15##__VAL(R_IRQ_READ0_, excessive_col_, v15) << R_IRQ_READ0__excessive_col__BITNR) | \ - (R_IRQ_READ0__mdio__##f16##__VAL(R_IRQ_READ0_, mdio_, v16) << R_IRQ_READ0__mdio__BITNR) | \ - (R_IRQ_READ0__ata_drq3__##f17##__VAL(R_IRQ_READ0_, ata_drq3_, v17) << R_IRQ_READ0__ata_drq3__BITNR) | \ - (R_IRQ_READ0__ata_drq2__##f18##__VAL(R_IRQ_READ0_, ata_drq2_, v18) << R_IRQ_READ0__ata_drq2__BITNR) | \ - (R_IRQ_READ0__ata_drq1__##f19##__VAL(R_IRQ_READ0_, ata_drq1_, v19) << R_IRQ_READ0__ata_drq1__BITNR) | \ - (R_IRQ_READ0__ata_drq0__##f20##__VAL(R_IRQ_READ0_, ata_drq0_, v20) << R_IRQ_READ0__ata_drq0__BITNR) | \ - (R_IRQ_READ0__par0_ecp_cmd__##f21##__VAL(R_IRQ_READ0_, par0_ecp_cmd_, v21) << R_IRQ_READ0__par0_ecp_cmd__BITNR) | \ - (R_IRQ_READ0__par0_peri__##f22##__VAL(R_IRQ_READ0_, par0_peri_, v22) << R_IRQ_READ0__par0_peri__BITNR) | \ - (R_IRQ_READ0__par0_data__##f23##__VAL(R_IRQ_READ0_, par0_data_, v23) << R_IRQ_READ0__par0_data__BITNR) | \ - (R_IRQ_READ0__par0_ready__##f24##__VAL(R_IRQ_READ0_, par0_ready_, v24) << R_IRQ_READ0__par0_ready__BITNR) | \ - (R_IRQ_READ0__ata_dmaend__##f25##__VAL(R_IRQ_READ0_, ata_dmaend_, v25) << R_IRQ_READ0__ata_dmaend__BITNR) | \ - (R_IRQ_READ0__irq_ext_vector_nr__##f26##__VAL(R_IRQ_READ0_, irq_ext_vector_nr_, v26) << R_IRQ_READ0__irq_ext_vector_nr__BITNR) | \ - (R_IRQ_READ0__irq_int_vector_nr__##f27##__VAL(R_IRQ_READ0_, irq_int_vector_nr_, v27) << R_IRQ_READ0__irq_int_vector_nr__BITNR) | \ - (R_IRQ_READ0__ext_dma1__##f28##__VAL(R_IRQ_READ0_, ext_dma1_, v28) << R_IRQ_READ0__ext_dma1__BITNR) | \ - (R_IRQ_READ0__ext_dma0__##f29##__VAL(R_IRQ_READ0_, ext_dma0_, v29) << R_IRQ_READ0__ext_dma0__BITNR) | \ - (R_IRQ_READ0__timer1__##f30##__VAL(R_IRQ_READ0_, timer1_, v30) << R_IRQ_READ0__timer1__BITNR) | \ - (R_IRQ_READ0__timer0__##f31##__VAL(R_IRQ_READ0_, timer0_, v31) << R_IRQ_READ0__timer0__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_IRQ_READ0_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_IRQ_READ0. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_IRQ_READ0_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16,f17_,v17,f18_,v18,f19_,v19,f20_,v20,f21_,v21,f22_,v22,f23_,v23,f24_,v24,f25_,v25,f26_,v26,f27_,v27,f28_,v28,f29_,v29,f30_,v30,f31_,v31) ( \ - (R_IRQ_READ0__nmi_pin__##f1_##_VAL(R_IRQ_READ0_, nmi_pin_, v1) << R_IRQ_READ0__nmi_pin__BITNR) | \ - (R_IRQ_READ0__watchdog_nmi__##f2_##_VAL(R_IRQ_READ0_, watchdog_nmi_, v2) << R_IRQ_READ0__watchdog_nmi__BITNR) | \ - (R_IRQ_READ0__sqe_test_error__##f3_##_VAL(R_IRQ_READ0_, sqe_test_error_, v3) << R_IRQ_READ0__sqe_test_error__BITNR) | \ - (R_IRQ_READ0__carrier_loss__##f4_##_VAL(R_IRQ_READ0_, carrier_loss_, v4) << R_IRQ_READ0__carrier_loss__BITNR) | \ - (R_IRQ_READ0__deferred__##f5_##_VAL(R_IRQ_READ0_, deferred_, v5) << R_IRQ_READ0__deferred__BITNR) | \ - (R_IRQ_READ0__late_col__##f6_##_VAL(R_IRQ_READ0_, late_col_, v6) << R_IRQ_READ0__late_col__BITNR) | \ - (R_IRQ_READ0__multiple_col__##f7_##_VAL(R_IRQ_READ0_, multiple_col_, v7) << R_IRQ_READ0__multiple_col__BITNR) | \ - (R_IRQ_READ0__single_col__##f8_##_VAL(R_IRQ_READ0_, single_col_, v8) << R_IRQ_READ0__single_col__BITNR) | \ - (R_IRQ_READ0__congestion__##f9_##_VAL(R_IRQ_READ0_, congestion_, v9) << R_IRQ_READ0__congestion__BITNR) | \ - (R_IRQ_READ0__oversize__##f10_##_VAL(R_IRQ_READ0_, oversize_, v10) << R_IRQ_READ0__oversize__BITNR) | \ - (R_IRQ_READ0__alignment_error__##f11_##_VAL(R_IRQ_READ0_, alignment_error_, v11) << R_IRQ_READ0__alignment_error__BITNR) | \ - (R_IRQ_READ0__crc_error__##f12_##_VAL(R_IRQ_READ0_, crc_error_, v12) << R_IRQ_READ0__crc_error__BITNR) | \ - (R_IRQ_READ0__overrun__##f13_##_VAL(R_IRQ_READ0_, overrun_, v13) << R_IRQ_READ0__overrun__BITNR) | \ - (R_IRQ_READ0__underrun__##f14_##_VAL(R_IRQ_READ0_, underrun_, v14) << R_IRQ_READ0__underrun__BITNR) | \ - (R_IRQ_READ0__excessive_col__##f15_##_VAL(R_IRQ_READ0_, excessive_col_, v15) << R_IRQ_READ0__excessive_col__BITNR) | \ - (R_IRQ_READ0__mdio__##f16_##_VAL(R_IRQ_READ0_, mdio_, v16) << R_IRQ_READ0__mdio__BITNR) | \ - (R_IRQ_READ0__ata_drq3__##f17_##_VAL(R_IRQ_READ0_, ata_drq3_, v17) << R_IRQ_READ0__ata_drq3__BITNR) | \ - (R_IRQ_READ0__ata_drq2__##f18_##_VAL(R_IRQ_READ0_, ata_drq2_, v18) << R_IRQ_READ0__ata_drq2__BITNR) | \ - (R_IRQ_READ0__ata_drq1__##f19_##_VAL(R_IRQ_READ0_, ata_drq1_, v19) << R_IRQ_READ0__ata_drq1__BITNR) | \ - (R_IRQ_READ0__ata_drq0__##f20_##_VAL(R_IRQ_READ0_, ata_drq0_, v20) << R_IRQ_READ0__ata_drq0__BITNR) | \ - (R_IRQ_READ0__par0_ecp_cmd__##f21_##_VAL(R_IRQ_READ0_, par0_ecp_cmd_, v21) << R_IRQ_READ0__par0_ecp_cmd__BITNR) | \ - (R_IRQ_READ0__par0_peri__##f22_##_VAL(R_IRQ_READ0_, par0_peri_, v22) << R_IRQ_READ0__par0_peri__BITNR) | \ - (R_IRQ_READ0__par0_data__##f23_##_VAL(R_IRQ_READ0_, par0_data_, v23) << R_IRQ_READ0__par0_data__BITNR) | \ - (R_IRQ_READ0__par0_ready__##f24_##_VAL(R_IRQ_READ0_, par0_ready_, v24) << R_IRQ_READ0__par0_ready__BITNR) | \ - (R_IRQ_READ0__ata_dmaend__##f25_##_VAL(R_IRQ_READ0_, ata_dmaend_, v25) << R_IRQ_READ0__ata_dmaend__BITNR) | \ - (R_IRQ_READ0__irq_ext_vector_nr__##f26_##_VAL(R_IRQ_READ0_, irq_ext_vector_nr_, v26) << R_IRQ_READ0__irq_ext_vector_nr__BITNR) | \ - (R_IRQ_READ0__irq_int_vector_nr__##f27_##_VAL(R_IRQ_READ0_, irq_int_vector_nr_, v27) << R_IRQ_READ0__irq_int_vector_nr__BITNR) | \ - (R_IRQ_READ0__ext_dma1__##f28_##_VAL(R_IRQ_READ0_, ext_dma1_, v28) << R_IRQ_READ0__ext_dma1__BITNR) | \ - (R_IRQ_READ0__ext_dma0__##f29_##_VAL(R_IRQ_READ0_, ext_dma0_, v29) << R_IRQ_READ0__ext_dma0__BITNR) | \ - (R_IRQ_READ0__timer1__##f30_##_VAL(R_IRQ_READ0_, timer1_, v30) << R_IRQ_READ0__timer1__BITNR) | \ - (R_IRQ_READ0__timer0__##f31_##_VAL(R_IRQ_READ0_, timer0_, v31) << R_IRQ_READ0__timer0__BITNR) \ -) - -#endif - -/* - * R_IRQ_READ1 - * - type: RO - * - addr: 0xb00000cc - * - group: Interrupt mask and status registers - */ - -#if USE_GROUP__Interrupt_mask_and_status_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_IRQ_READ1 -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_IRQ_READ1(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25,f26,v26,f27,v27,f28,v28) ( \ - (R_IRQ_READ1__sw_int7__##f1##__MASK & REG__##v1) | \ - (R_IRQ_READ1__sw_int6__##f2##__MASK & REG__##v2) | \ - (R_IRQ_READ1__sw_int5__##f3##__MASK & REG__##v3) | \ - (R_IRQ_READ1__sw_int4__##f4##__MASK & REG__##v4) | \ - (R_IRQ_READ1__sw_int3__##f5##__MASK & REG__##v5) | \ - (R_IRQ_READ1__sw_int2__##f6##__MASK & REG__##v6) | \ - (R_IRQ_READ1__sw_int1__##f7##__MASK & REG__##v7) | \ - (R_IRQ_READ1__sw_int0__##f8##__MASK & REG__##v8) | \ - (R_IRQ_READ1__par1_ecp_cmd__##f9##__MASK & REG__##v9) | \ - (R_IRQ_READ1__par1_peri__##f10##__MASK & REG__##v10) | \ - (R_IRQ_READ1__par1_data__##f11##__MASK & REG__##v11) | \ - (R_IRQ_READ1__par1_ready__##f12##__MASK & REG__##v12) | \ - (R_IRQ_READ1__ser3_ready__##f13##__MASK & REG__##v13) | \ - (R_IRQ_READ1__ser3_data__##f14##__MASK & REG__##v14) | \ - (R_IRQ_READ1__ser2_ready__##f15##__MASK & REG__##v15) | \ - (R_IRQ_READ1__ser2_data__##f16##__MASK & REG__##v16) | \ - (R_IRQ_READ1__ser1_ready__##f17##__MASK & REG__##v17) | \ - (R_IRQ_READ1__ser1_data__##f18##__MASK & REG__##v18) | \ - (R_IRQ_READ1__ser0_ready__##f19##__MASK & REG__##v19) | \ - (R_IRQ_READ1__ser0_data__##f20##__MASK & REG__##v20) | \ - (R_IRQ_READ1__pa7__##f21##__MASK & REG__##v21) | \ - (R_IRQ_READ1__pa6__##f22##__MASK & REG__##v22) | \ - (R_IRQ_READ1__pa5__##f23##__MASK & REG__##v23) | \ - (R_IRQ_READ1__pa4__##f24##__MASK & REG__##v24) | \ - (R_IRQ_READ1__pa3__##f25##__MASK & REG__##v25) | \ - (R_IRQ_READ1__pa2__##f26##__MASK & REG__##v26) | \ - (R_IRQ_READ1__pa1__##f27##__MASK & REG__##v27) | \ - (R_IRQ_READ1__pa0__##f28##__MASK & REG__##v28) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_IRQ_READ1 -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_IRQ_READ1. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_IRQ_READ1(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25,f26,v26,f27,v27,f28,v28) ( \ - (R_IRQ_READ1__sw_int7__##f1##__VAL(R_IRQ_READ1_, sw_int7_, v1) << R_IRQ_READ1__sw_int7__BITNR) | \ - (R_IRQ_READ1__sw_int6__##f2##__VAL(R_IRQ_READ1_, sw_int6_, v2) << R_IRQ_READ1__sw_int6__BITNR) | \ - (R_IRQ_READ1__sw_int5__##f3##__VAL(R_IRQ_READ1_, sw_int5_, v3) << R_IRQ_READ1__sw_int5__BITNR) | \ - (R_IRQ_READ1__sw_int4__##f4##__VAL(R_IRQ_READ1_, sw_int4_, v4) << R_IRQ_READ1__sw_int4__BITNR) | \ - (R_IRQ_READ1__sw_int3__##f5##__VAL(R_IRQ_READ1_, sw_int3_, v5) << R_IRQ_READ1__sw_int3__BITNR) | \ - (R_IRQ_READ1__sw_int2__##f6##__VAL(R_IRQ_READ1_, sw_int2_, v6) << R_IRQ_READ1__sw_int2__BITNR) | \ - (R_IRQ_READ1__sw_int1__##f7##__VAL(R_IRQ_READ1_, sw_int1_, v7) << R_IRQ_READ1__sw_int1__BITNR) | \ - (R_IRQ_READ1__sw_int0__##f8##__VAL(R_IRQ_READ1_, sw_int0_, v8) << R_IRQ_READ1__sw_int0__BITNR) | \ - (R_IRQ_READ1__par1_ecp_cmd__##f9##__VAL(R_IRQ_READ1_, par1_ecp_cmd_, v9) << R_IRQ_READ1__par1_ecp_cmd__BITNR) | \ - (R_IRQ_READ1__par1_peri__##f10##__VAL(R_IRQ_READ1_, par1_peri_, v10) << R_IRQ_READ1__par1_peri__BITNR) | \ - (R_IRQ_READ1__par1_data__##f11##__VAL(R_IRQ_READ1_, par1_data_, v11) << R_IRQ_READ1__par1_data__BITNR) | \ - (R_IRQ_READ1__par1_ready__##f12##__VAL(R_IRQ_READ1_, par1_ready_, v12) << R_IRQ_READ1__par1_ready__BITNR) | \ - (R_IRQ_READ1__ser3_ready__##f13##__VAL(R_IRQ_READ1_, ser3_ready_, v13) << R_IRQ_READ1__ser3_ready__BITNR) | \ - (R_IRQ_READ1__ser3_data__##f14##__VAL(R_IRQ_READ1_, ser3_data_, v14) << R_IRQ_READ1__ser3_data__BITNR) | \ - (R_IRQ_READ1__ser2_ready__##f15##__VAL(R_IRQ_READ1_, ser2_ready_, v15) << R_IRQ_READ1__ser2_ready__BITNR) | \ - (R_IRQ_READ1__ser2_data__##f16##__VAL(R_IRQ_READ1_, ser2_data_, v16) << R_IRQ_READ1__ser2_data__BITNR) | \ - (R_IRQ_READ1__ser1_ready__##f17##__VAL(R_IRQ_READ1_, ser1_ready_, v17) << R_IRQ_READ1__ser1_ready__BITNR) | \ - (R_IRQ_READ1__ser1_data__##f18##__VAL(R_IRQ_READ1_, ser1_data_, v18) << R_IRQ_READ1__ser1_data__BITNR) | \ - (R_IRQ_READ1__ser0_ready__##f19##__VAL(R_IRQ_READ1_, ser0_ready_, v19) << R_IRQ_READ1__ser0_ready__BITNR) | \ - (R_IRQ_READ1__ser0_data__##f20##__VAL(R_IRQ_READ1_, ser0_data_, v20) << R_IRQ_READ1__ser0_data__BITNR) | \ - (R_IRQ_READ1__pa7__##f21##__VAL(R_IRQ_READ1_, pa7_, v21) << R_IRQ_READ1__pa7__BITNR) | \ - (R_IRQ_READ1__pa6__##f22##__VAL(R_IRQ_READ1_, pa6_, v22) << R_IRQ_READ1__pa6__BITNR) | \ - (R_IRQ_READ1__pa5__##f23##__VAL(R_IRQ_READ1_, pa5_, v23) << R_IRQ_READ1__pa5__BITNR) | \ - (R_IRQ_READ1__pa4__##f24##__VAL(R_IRQ_READ1_, pa4_, v24) << R_IRQ_READ1__pa4__BITNR) | \ - (R_IRQ_READ1__pa3__##f25##__VAL(R_IRQ_READ1_, pa3_, v25) << R_IRQ_READ1__pa3__BITNR) | \ - (R_IRQ_READ1__pa2__##f26##__VAL(R_IRQ_READ1_, pa2_, v26) << R_IRQ_READ1__pa2__BITNR) | \ - (R_IRQ_READ1__pa1__##f27##__VAL(R_IRQ_READ1_, pa1_, v27) << R_IRQ_READ1__pa1__BITNR) | \ - (R_IRQ_READ1__pa0__##f28##__VAL(R_IRQ_READ1_, pa0_, v28) << R_IRQ_READ1__pa0__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_IRQ_READ1_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_IRQ_READ1. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_IRQ_READ1_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16,f17_,v17,f18_,v18,f19_,v19,f20_,v20,f21_,v21,f22_,v22,f23_,v23,f24_,v24,f25_,v25,f26_,v26,f27_,v27,f28_,v28) ( \ - (R_IRQ_READ1__sw_int7__##f1_##_VAL(R_IRQ_READ1_, sw_int7_, v1) << R_IRQ_READ1__sw_int7__BITNR) | \ - (R_IRQ_READ1__sw_int6__##f2_##_VAL(R_IRQ_READ1_, sw_int6_, v2) << R_IRQ_READ1__sw_int6__BITNR) | \ - (R_IRQ_READ1__sw_int5__##f3_##_VAL(R_IRQ_READ1_, sw_int5_, v3) << R_IRQ_READ1__sw_int5__BITNR) | \ - (R_IRQ_READ1__sw_int4__##f4_##_VAL(R_IRQ_READ1_, sw_int4_, v4) << R_IRQ_READ1__sw_int4__BITNR) | \ - (R_IRQ_READ1__sw_int3__##f5_##_VAL(R_IRQ_READ1_, sw_int3_, v5) << R_IRQ_READ1__sw_int3__BITNR) | \ - (R_IRQ_READ1__sw_int2__##f6_##_VAL(R_IRQ_READ1_, sw_int2_, v6) << R_IRQ_READ1__sw_int2__BITNR) | \ - (R_IRQ_READ1__sw_int1__##f7_##_VAL(R_IRQ_READ1_, sw_int1_, v7) << R_IRQ_READ1__sw_int1__BITNR) | \ - (R_IRQ_READ1__sw_int0__##f8_##_VAL(R_IRQ_READ1_, sw_int0_, v8) << R_IRQ_READ1__sw_int0__BITNR) | \ - (R_IRQ_READ1__par1_ecp_cmd__##f9_##_VAL(R_IRQ_READ1_, par1_ecp_cmd_, v9) << R_IRQ_READ1__par1_ecp_cmd__BITNR) | \ - (R_IRQ_READ1__par1_peri__##f10_##_VAL(R_IRQ_READ1_, par1_peri_, v10) << R_IRQ_READ1__par1_peri__BITNR) | \ - (R_IRQ_READ1__par1_data__##f11_##_VAL(R_IRQ_READ1_, par1_data_, v11) << R_IRQ_READ1__par1_data__BITNR) | \ - (R_IRQ_READ1__par1_ready__##f12_##_VAL(R_IRQ_READ1_, par1_ready_, v12) << R_IRQ_READ1__par1_ready__BITNR) | \ - (R_IRQ_READ1__ser3_ready__##f13_##_VAL(R_IRQ_READ1_, ser3_ready_, v13) << R_IRQ_READ1__ser3_ready__BITNR) | \ - (R_IRQ_READ1__ser3_data__##f14_##_VAL(R_IRQ_READ1_, ser3_data_, v14) << R_IRQ_READ1__ser3_data__BITNR) | \ - (R_IRQ_READ1__ser2_ready__##f15_##_VAL(R_IRQ_READ1_, ser2_ready_, v15) << R_IRQ_READ1__ser2_ready__BITNR) | \ - (R_IRQ_READ1__ser2_data__##f16_##_VAL(R_IRQ_READ1_, ser2_data_, v16) << R_IRQ_READ1__ser2_data__BITNR) | \ - (R_IRQ_READ1__ser1_ready__##f17_##_VAL(R_IRQ_READ1_, ser1_ready_, v17) << R_IRQ_READ1__ser1_ready__BITNR) | \ - (R_IRQ_READ1__ser1_data__##f18_##_VAL(R_IRQ_READ1_, ser1_data_, v18) << R_IRQ_READ1__ser1_data__BITNR) | \ - (R_IRQ_READ1__ser0_ready__##f19_##_VAL(R_IRQ_READ1_, ser0_ready_, v19) << R_IRQ_READ1__ser0_ready__BITNR) | \ - (R_IRQ_READ1__ser0_data__##f20_##_VAL(R_IRQ_READ1_, ser0_data_, v20) << R_IRQ_READ1__ser0_data__BITNR) | \ - (R_IRQ_READ1__pa7__##f21_##_VAL(R_IRQ_READ1_, pa7_, v21) << R_IRQ_READ1__pa7__BITNR) | \ - (R_IRQ_READ1__pa6__##f22_##_VAL(R_IRQ_READ1_, pa6_, v22) << R_IRQ_READ1__pa6__BITNR) | \ - (R_IRQ_READ1__pa5__##f23_##_VAL(R_IRQ_READ1_, pa5_, v23) << R_IRQ_READ1__pa5__BITNR) | \ - (R_IRQ_READ1__pa4__##f24_##_VAL(R_IRQ_READ1_, pa4_, v24) << R_IRQ_READ1__pa4__BITNR) | \ - (R_IRQ_READ1__pa3__##f25_##_VAL(R_IRQ_READ1_, pa3_, v25) << R_IRQ_READ1__pa3__BITNR) | \ - (R_IRQ_READ1__pa2__##f26_##_VAL(R_IRQ_READ1_, pa2_, v26) << R_IRQ_READ1__pa2__BITNR) | \ - (R_IRQ_READ1__pa1__##f27_##_VAL(R_IRQ_READ1_, pa1_, v27) << R_IRQ_READ1__pa1__BITNR) | \ - (R_IRQ_READ1__pa0__##f28_##_VAL(R_IRQ_READ1_, pa0_, v28) << R_IRQ_READ1__pa0__BITNR) \ -) - -#endif - -/* - * R_IRQ_READ2 - * - type: RO - * - addr: 0xb00000d4 - * - group: Interrupt mask and status registers - */ - -#if USE_GROUP__Interrupt_mask_and_status_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_IRQ_READ2 -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_IRQ_READ2(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24) ( \ - (R_IRQ_READ2__dma8_sub3_descr__##f1##__MASK & REG__##v1) | \ - (R_IRQ_READ2__dma8_sub2_descr__##f2##__MASK & REG__##v2) | \ - (R_IRQ_READ2__dma8_sub1_descr__##f3##__MASK & REG__##v3) | \ - (R_IRQ_READ2__dma8_sub0_descr__##f4##__MASK & REG__##v4) | \ - (R_IRQ_READ2__dma9_eop__##f5##__MASK & REG__##v5) | \ - (R_IRQ_READ2__dma9_descr__##f6##__MASK & REG__##v6) | \ - (R_IRQ_READ2__dma8_eop__##f7##__MASK & REG__##v7) | \ - (R_IRQ_READ2__dma8_descr__##f8##__MASK & REG__##v8) | \ - (R_IRQ_READ2__dma7_eop__##f9##__MASK & REG__##v9) | \ - (R_IRQ_READ2__dma7_descr__##f10##__MASK & REG__##v10) | \ - (R_IRQ_READ2__dma6_eop__##f11##__MASK & REG__##v11) | \ - (R_IRQ_READ2__dma6_descr__##f12##__MASK & REG__##v12) | \ - (R_IRQ_READ2__dma5_eop__##f13##__MASK & REG__##v13) | \ - (R_IRQ_READ2__dma5_descr__##f14##__MASK & REG__##v14) | \ - (R_IRQ_READ2__dma4_eop__##f15##__MASK & REG__##v15) | \ - (R_IRQ_READ2__dma4_descr__##f16##__MASK & REG__##v16) | \ - (R_IRQ_READ2__dma3_eop__##f17##__MASK & REG__##v17) | \ - (R_IRQ_READ2__dma3_descr__##f18##__MASK & REG__##v18) | \ - (R_IRQ_READ2__dma2_eop__##f19##__MASK & REG__##v19) | \ - (R_IRQ_READ2__dma2_descr__##f20##__MASK & REG__##v20) | \ - (R_IRQ_READ2__dma1_eop__##f21##__MASK & REG__##v21) | \ - (R_IRQ_READ2__dma1_descr__##f22##__MASK & REG__##v22) | \ - (R_IRQ_READ2__dma0_eop__##f23##__MASK & REG__##v23) | \ - (R_IRQ_READ2__dma0_descr__##f24##__MASK & REG__##v24) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_IRQ_READ2 -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_IRQ_READ2. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_IRQ_READ2(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24) ( \ - (R_IRQ_READ2__dma8_sub3_descr__##f1##__VAL(R_IRQ_READ2_, dma8_sub3_descr_, v1) << R_IRQ_READ2__dma8_sub3_descr__BITNR) | \ - (R_IRQ_READ2__dma8_sub2_descr__##f2##__VAL(R_IRQ_READ2_, dma8_sub2_descr_, v2) << R_IRQ_READ2__dma8_sub2_descr__BITNR) | \ - (R_IRQ_READ2__dma8_sub1_descr__##f3##__VAL(R_IRQ_READ2_, dma8_sub1_descr_, v3) << R_IRQ_READ2__dma8_sub1_descr__BITNR) | \ - (R_IRQ_READ2__dma8_sub0_descr__##f4##__VAL(R_IRQ_READ2_, dma8_sub0_descr_, v4) << R_IRQ_READ2__dma8_sub0_descr__BITNR) | \ - (R_IRQ_READ2__dma9_eop__##f5##__VAL(R_IRQ_READ2_, dma9_eop_, v5) << R_IRQ_READ2__dma9_eop__BITNR) | \ - (R_IRQ_READ2__dma9_descr__##f6##__VAL(R_IRQ_READ2_, dma9_descr_, v6) << R_IRQ_READ2__dma9_descr__BITNR) | \ - (R_IRQ_READ2__dma8_eop__##f7##__VAL(R_IRQ_READ2_, dma8_eop_, v7) << R_IRQ_READ2__dma8_eop__BITNR) | \ - (R_IRQ_READ2__dma8_descr__##f8##__VAL(R_IRQ_READ2_, dma8_descr_, v8) << R_IRQ_READ2__dma8_descr__BITNR) | \ - (R_IRQ_READ2__dma7_eop__##f9##__VAL(R_IRQ_READ2_, dma7_eop_, v9) << R_IRQ_READ2__dma7_eop__BITNR) | \ - (R_IRQ_READ2__dma7_descr__##f10##__VAL(R_IRQ_READ2_, dma7_descr_, v10) << R_IRQ_READ2__dma7_descr__BITNR) | \ - (R_IRQ_READ2__dma6_eop__##f11##__VAL(R_IRQ_READ2_, dma6_eop_, v11) << R_IRQ_READ2__dma6_eop__BITNR) | \ - (R_IRQ_READ2__dma6_descr__##f12##__VAL(R_IRQ_READ2_, dma6_descr_, v12) << R_IRQ_READ2__dma6_descr__BITNR) | \ - (R_IRQ_READ2__dma5_eop__##f13##__VAL(R_IRQ_READ2_, dma5_eop_, v13) << R_IRQ_READ2__dma5_eop__BITNR) | \ - (R_IRQ_READ2__dma5_descr__##f14##__VAL(R_IRQ_READ2_, dma5_descr_, v14) << R_IRQ_READ2__dma5_descr__BITNR) | \ - (R_IRQ_READ2__dma4_eop__##f15##__VAL(R_IRQ_READ2_, dma4_eop_, v15) << R_IRQ_READ2__dma4_eop__BITNR) | \ - (R_IRQ_READ2__dma4_descr__##f16##__VAL(R_IRQ_READ2_, dma4_descr_, v16) << R_IRQ_READ2__dma4_descr__BITNR) | \ - (R_IRQ_READ2__dma3_eop__##f17##__VAL(R_IRQ_READ2_, dma3_eop_, v17) << R_IRQ_READ2__dma3_eop__BITNR) | \ - (R_IRQ_READ2__dma3_descr__##f18##__VAL(R_IRQ_READ2_, dma3_descr_, v18) << R_IRQ_READ2__dma3_descr__BITNR) | \ - (R_IRQ_READ2__dma2_eop__##f19##__VAL(R_IRQ_READ2_, dma2_eop_, v19) << R_IRQ_READ2__dma2_eop__BITNR) | \ - (R_IRQ_READ2__dma2_descr__##f20##__VAL(R_IRQ_READ2_, dma2_descr_, v20) << R_IRQ_READ2__dma2_descr__BITNR) | \ - (R_IRQ_READ2__dma1_eop__##f21##__VAL(R_IRQ_READ2_, dma1_eop_, v21) << R_IRQ_READ2__dma1_eop__BITNR) | \ - (R_IRQ_READ2__dma1_descr__##f22##__VAL(R_IRQ_READ2_, dma1_descr_, v22) << R_IRQ_READ2__dma1_descr__BITNR) | \ - (R_IRQ_READ2__dma0_eop__##f23##__VAL(R_IRQ_READ2_, dma0_eop_, v23) << R_IRQ_READ2__dma0_eop__BITNR) | \ - (R_IRQ_READ2__dma0_descr__##f24##__VAL(R_IRQ_READ2_, dma0_descr_, v24) << R_IRQ_READ2__dma0_descr__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_IRQ_READ2_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_IRQ_READ2. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_IRQ_READ2_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16,f17_,v17,f18_,v18,f19_,v19,f20_,v20,f21_,v21,f22_,v22,f23_,v23,f24_,v24) ( \ - (R_IRQ_READ2__dma8_sub3_descr__##f1_##_VAL(R_IRQ_READ2_, dma8_sub3_descr_, v1) << R_IRQ_READ2__dma8_sub3_descr__BITNR) | \ - (R_IRQ_READ2__dma8_sub2_descr__##f2_##_VAL(R_IRQ_READ2_, dma8_sub2_descr_, v2) << R_IRQ_READ2__dma8_sub2_descr__BITNR) | \ - (R_IRQ_READ2__dma8_sub1_descr__##f3_##_VAL(R_IRQ_READ2_, dma8_sub1_descr_, v3) << R_IRQ_READ2__dma8_sub1_descr__BITNR) | \ - (R_IRQ_READ2__dma8_sub0_descr__##f4_##_VAL(R_IRQ_READ2_, dma8_sub0_descr_, v4) << R_IRQ_READ2__dma8_sub0_descr__BITNR) | \ - (R_IRQ_READ2__dma9_eop__##f5_##_VAL(R_IRQ_READ2_, dma9_eop_, v5) << R_IRQ_READ2__dma9_eop__BITNR) | \ - (R_IRQ_READ2__dma9_descr__##f6_##_VAL(R_IRQ_READ2_, dma9_descr_, v6) << R_IRQ_READ2__dma9_descr__BITNR) | \ - (R_IRQ_READ2__dma8_eop__##f7_##_VAL(R_IRQ_READ2_, dma8_eop_, v7) << R_IRQ_READ2__dma8_eop__BITNR) | \ - (R_IRQ_READ2__dma8_descr__##f8_##_VAL(R_IRQ_READ2_, dma8_descr_, v8) << R_IRQ_READ2__dma8_descr__BITNR) | \ - (R_IRQ_READ2__dma7_eop__##f9_##_VAL(R_IRQ_READ2_, dma7_eop_, v9) << R_IRQ_READ2__dma7_eop__BITNR) | \ - (R_IRQ_READ2__dma7_descr__##f10_##_VAL(R_IRQ_READ2_, dma7_descr_, v10) << R_IRQ_READ2__dma7_descr__BITNR) | \ - (R_IRQ_READ2__dma6_eop__##f11_##_VAL(R_IRQ_READ2_, dma6_eop_, v11) << R_IRQ_READ2__dma6_eop__BITNR) | \ - (R_IRQ_READ2__dma6_descr__##f12_##_VAL(R_IRQ_READ2_, dma6_descr_, v12) << R_IRQ_READ2__dma6_descr__BITNR) | \ - (R_IRQ_READ2__dma5_eop__##f13_##_VAL(R_IRQ_READ2_, dma5_eop_, v13) << R_IRQ_READ2__dma5_eop__BITNR) | \ - (R_IRQ_READ2__dma5_descr__##f14_##_VAL(R_IRQ_READ2_, dma5_descr_, v14) << R_IRQ_READ2__dma5_descr__BITNR) | \ - (R_IRQ_READ2__dma4_eop__##f15_##_VAL(R_IRQ_READ2_, dma4_eop_, v15) << R_IRQ_READ2__dma4_eop__BITNR) | \ - (R_IRQ_READ2__dma4_descr__##f16_##_VAL(R_IRQ_READ2_, dma4_descr_, v16) << R_IRQ_READ2__dma4_descr__BITNR) | \ - (R_IRQ_READ2__dma3_eop__##f17_##_VAL(R_IRQ_READ2_, dma3_eop_, v17) << R_IRQ_READ2__dma3_eop__BITNR) | \ - (R_IRQ_READ2__dma3_descr__##f18_##_VAL(R_IRQ_READ2_, dma3_descr_, v18) << R_IRQ_READ2__dma3_descr__BITNR) | \ - (R_IRQ_READ2__dma2_eop__##f19_##_VAL(R_IRQ_READ2_, dma2_eop_, v19) << R_IRQ_READ2__dma2_eop__BITNR) | \ - (R_IRQ_READ2__dma2_descr__##f20_##_VAL(R_IRQ_READ2_, dma2_descr_, v20) << R_IRQ_READ2__dma2_descr__BITNR) | \ - (R_IRQ_READ2__dma1_eop__##f21_##_VAL(R_IRQ_READ2_, dma1_eop_, v21) << R_IRQ_READ2__dma1_eop__BITNR) | \ - (R_IRQ_READ2__dma1_descr__##f22_##_VAL(R_IRQ_READ2_, dma1_descr_, v22) << R_IRQ_READ2__dma1_descr__BITNR) | \ - (R_IRQ_READ2__dma0_eop__##f23_##_VAL(R_IRQ_READ2_, dma0_eop_, v23) << R_IRQ_READ2__dma0_eop__BITNR) | \ - (R_IRQ_READ2__dma0_descr__##f24_##_VAL(R_IRQ_READ2_, dma0_descr_, v24) << R_IRQ_READ2__dma0_descr__BITNR) \ -) - -#endif - -/* - * R_MMU_CAUSE - * - type: RO - * - addr: 0xb0000250 - * - group: MMU registers - */ - -#if USE_GROUP__MMU_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_MMU_CAUSE -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_MMU_CAUSE(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7) ( \ - (R_MMU_CAUSE__vpn__##f1##__MASK & REG__##v1) | \ - (R_MMU_CAUSE__miss_excp__##f2##__MASK & REG__##v2) | \ - (R_MMU_CAUSE__inv_excp__##f3##__MASK & REG__##v3) | \ - (R_MMU_CAUSE__acc_excp__##f4##__MASK & REG__##v4) | \ - (R_MMU_CAUSE__we_excp__##f5##__MASK & REG__##v5) | \ - (R_MMU_CAUSE__wr_rd__##f6##__MASK & REG__##v6) | \ - (R_MMU_CAUSE__page_id__##f7##__MASK & REG__##v7) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_MMU_CAUSE -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_MMU_CAUSE. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_MMU_CAUSE(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7) ( \ - (R_MMU_CAUSE__vpn__##f1##__VAL(R_MMU_CAUSE_, vpn_, v1) << R_MMU_CAUSE__vpn__BITNR) | \ - (R_MMU_CAUSE__miss_excp__##f2##__VAL(R_MMU_CAUSE_, miss_excp_, v2) << R_MMU_CAUSE__miss_excp__BITNR) | \ - (R_MMU_CAUSE__inv_excp__##f3##__VAL(R_MMU_CAUSE_, inv_excp_, v3) << R_MMU_CAUSE__inv_excp__BITNR) | \ - (R_MMU_CAUSE__acc_excp__##f4##__VAL(R_MMU_CAUSE_, acc_excp_, v4) << R_MMU_CAUSE__acc_excp__BITNR) | \ - (R_MMU_CAUSE__we_excp__##f5##__VAL(R_MMU_CAUSE_, we_excp_, v5) << R_MMU_CAUSE__we_excp__BITNR) | \ - (R_MMU_CAUSE__wr_rd__##f6##__VAL(R_MMU_CAUSE_, wr_rd_, v6) << R_MMU_CAUSE__wr_rd__BITNR) | \ - (R_MMU_CAUSE__page_id__##f7##__VAL(R_MMU_CAUSE_, page_id_, v7) << R_MMU_CAUSE__page_id__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_MMU_CAUSE_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_MMU_CAUSE. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_MMU_CAUSE_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7) ( \ - (R_MMU_CAUSE__vpn__##f1_##_VAL(R_MMU_CAUSE_, vpn_, v1) << R_MMU_CAUSE__vpn__BITNR) | \ - (R_MMU_CAUSE__miss_excp__##f2_##_VAL(R_MMU_CAUSE_, miss_excp_, v2) << R_MMU_CAUSE__miss_excp__BITNR) | \ - (R_MMU_CAUSE__inv_excp__##f3_##_VAL(R_MMU_CAUSE_, inv_excp_, v3) << R_MMU_CAUSE__inv_excp__BITNR) | \ - (R_MMU_CAUSE__acc_excp__##f4_##_VAL(R_MMU_CAUSE_, acc_excp_, v4) << R_MMU_CAUSE__acc_excp__BITNR) | \ - (R_MMU_CAUSE__we_excp__##f5_##_VAL(R_MMU_CAUSE_, we_excp_, v5) << R_MMU_CAUSE__we_excp__BITNR) | \ - (R_MMU_CAUSE__wr_rd__##f6_##_VAL(R_MMU_CAUSE_, wr_rd_, v6) << R_MMU_CAUSE__wr_rd__BITNR) | \ - (R_MMU_CAUSE__page_id__##f7_##_VAL(R_MMU_CAUSE_, page_id_, v7) << R_MMU_CAUSE__page_id__BITNR) \ -) - -#endif - -/* - * R_MMU_CONFIG - * - type: WO - * - addr: 0xb0000240 - * - group: MMU registers - */ - -#if USE_GROUP__MMU_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_MMU_CONFIG -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_MMU_CONFIG. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_MMU_CONFIG. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_MMU_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20) ( \ - *R_MMU_CONFIG__SADDR = ( \ - REG_INITIATED(R_MMU_CONFIG_) \ - REG_VAL__R_MMU_CONFIG_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20) \ - ), \ - R_MMU_CONFIG__WRITE(R_MMU_CONFIG__ADDR, *R_MMU_CONFIG__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_MMU_CONFIG__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_MMU_CONFIG. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_MMU_CONFIG. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_MMU_CONFIG__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20) ( \ - *R_MMU_CONFIG__SADDR = ( \ - REG_INITIATED(R_MMU_CONFIG_) \ - REG_VAL__R_MMU_CONFIG_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_MMU_CONFIG -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_MMU_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20) ( \ - (R_MMU_CONFIG__mmu_enable__##f1##__MASK & REG__##v1) | \ - (R_MMU_CONFIG__inv_excp__##f2##__MASK & REG__##v2) | \ - (R_MMU_CONFIG__acc_excp__##f3##__MASK & REG__##v3) | \ - (R_MMU_CONFIG__we_excp__##f4##__MASK & REG__##v4) | \ - (R_MMU_CONFIG__seg_f__##f5##__MASK & REG__##v5) | \ - (R_MMU_CONFIG__seg_e__##f6##__MASK & REG__##v6) | \ - (R_MMU_CONFIG__seg_d__##f7##__MASK & REG__##v7) | \ - (R_MMU_CONFIG__seg_c__##f8##__MASK & REG__##v8) | \ - (R_MMU_CONFIG__seg_b__##f9##__MASK & REG__##v9) | \ - (R_MMU_CONFIG__seg_a__##f10##__MASK & REG__##v10) | \ - (R_MMU_CONFIG__seg_9__##f11##__MASK & REG__##v11) | \ - (R_MMU_CONFIG__seg_8__##f12##__MASK & REG__##v12) | \ - (R_MMU_CONFIG__seg_7__##f13##__MASK & REG__##v13) | \ - (R_MMU_CONFIG__seg_6__##f14##__MASK & REG__##v14) | \ - (R_MMU_CONFIG__seg_5__##f15##__MASK & REG__##v15) | \ - (R_MMU_CONFIG__seg_4__##f16##__MASK & REG__##v16) | \ - (R_MMU_CONFIG__seg_3__##f17##__MASK & REG__##v17) | \ - (R_MMU_CONFIG__seg_2__##f18##__MASK & REG__##v18) | \ - (R_MMU_CONFIG__seg_1__##f19##__MASK & REG__##v19) | \ - (R_MMU_CONFIG__seg_0__##f20##__MASK & REG__##v20) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_MMU_CONFIG -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_MMU_CONFIG. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_MMU_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20) ( \ - (R_MMU_CONFIG__mmu_enable__##f1##__VAL(R_MMU_CONFIG_, mmu_enable_, v1) << R_MMU_CONFIG__mmu_enable__BITNR) | \ - (R_MMU_CONFIG__inv_excp__##f2##__VAL(R_MMU_CONFIG_, inv_excp_, v2) << R_MMU_CONFIG__inv_excp__BITNR) | \ - (R_MMU_CONFIG__acc_excp__##f3##__VAL(R_MMU_CONFIG_, acc_excp_, v3) << R_MMU_CONFIG__acc_excp__BITNR) | \ - (R_MMU_CONFIG__we_excp__##f4##__VAL(R_MMU_CONFIG_, we_excp_, v4) << R_MMU_CONFIG__we_excp__BITNR) | \ - (R_MMU_CONFIG__seg_f__##f5##__VAL(R_MMU_CONFIG_, seg_f_, v5) << R_MMU_CONFIG__seg_f__BITNR) | \ - (R_MMU_CONFIG__seg_e__##f6##__VAL(R_MMU_CONFIG_, seg_e_, v6) << R_MMU_CONFIG__seg_e__BITNR) | \ - (R_MMU_CONFIG__seg_d__##f7##__VAL(R_MMU_CONFIG_, seg_d_, v7) << R_MMU_CONFIG__seg_d__BITNR) | \ - (R_MMU_CONFIG__seg_c__##f8##__VAL(R_MMU_CONFIG_, seg_c_, v8) << R_MMU_CONFIG__seg_c__BITNR) | \ - (R_MMU_CONFIG__seg_b__##f9##__VAL(R_MMU_CONFIG_, seg_b_, v9) << R_MMU_CONFIG__seg_b__BITNR) | \ - (R_MMU_CONFIG__seg_a__##f10##__VAL(R_MMU_CONFIG_, seg_a_, v10) << R_MMU_CONFIG__seg_a__BITNR) | \ - (R_MMU_CONFIG__seg_9__##f11##__VAL(R_MMU_CONFIG_, seg_9_, v11) << R_MMU_CONFIG__seg_9__BITNR) | \ - (R_MMU_CONFIG__seg_8__##f12##__VAL(R_MMU_CONFIG_, seg_8_, v12) << R_MMU_CONFIG__seg_8__BITNR) | \ - (R_MMU_CONFIG__seg_7__##f13##__VAL(R_MMU_CONFIG_, seg_7_, v13) << R_MMU_CONFIG__seg_7__BITNR) | \ - (R_MMU_CONFIG__seg_6__##f14##__VAL(R_MMU_CONFIG_, seg_6_, v14) << R_MMU_CONFIG__seg_6__BITNR) | \ - (R_MMU_CONFIG__seg_5__##f15##__VAL(R_MMU_CONFIG_, seg_5_, v15) << R_MMU_CONFIG__seg_5__BITNR) | \ - (R_MMU_CONFIG__seg_4__##f16##__VAL(R_MMU_CONFIG_, seg_4_, v16) << R_MMU_CONFIG__seg_4__BITNR) | \ - (R_MMU_CONFIG__seg_3__##f17##__VAL(R_MMU_CONFIG_, seg_3_, v17) << R_MMU_CONFIG__seg_3__BITNR) | \ - (R_MMU_CONFIG__seg_2__##f18##__VAL(R_MMU_CONFIG_, seg_2_, v18) << R_MMU_CONFIG__seg_2__BITNR) | \ - (R_MMU_CONFIG__seg_1__##f19##__VAL(R_MMU_CONFIG_, seg_1_, v19) << R_MMU_CONFIG__seg_1__BITNR) | \ - (R_MMU_CONFIG__seg_0__##f20##__VAL(R_MMU_CONFIG_, seg_0_, v20) << R_MMU_CONFIG__seg_0__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_MMU_CONFIG_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_MMU_CONFIG. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_MMU_CONFIG_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16,f17_,v17,f18_,v18,f19_,v19,f20_,v20) ( \ - (R_MMU_CONFIG__mmu_enable__##f1_##_VAL(R_MMU_CONFIG_, mmu_enable_, v1) << R_MMU_CONFIG__mmu_enable__BITNR) | \ - (R_MMU_CONFIG__inv_excp__##f2_##_VAL(R_MMU_CONFIG_, inv_excp_, v2) << R_MMU_CONFIG__inv_excp__BITNR) | \ - (R_MMU_CONFIG__acc_excp__##f3_##_VAL(R_MMU_CONFIG_, acc_excp_, v3) << R_MMU_CONFIG__acc_excp__BITNR) | \ - (R_MMU_CONFIG__we_excp__##f4_##_VAL(R_MMU_CONFIG_, we_excp_, v4) << R_MMU_CONFIG__we_excp__BITNR) | \ - (R_MMU_CONFIG__seg_f__##f5_##_VAL(R_MMU_CONFIG_, seg_f_, v5) << R_MMU_CONFIG__seg_f__BITNR) | \ - (R_MMU_CONFIG__seg_e__##f6_##_VAL(R_MMU_CONFIG_, seg_e_, v6) << R_MMU_CONFIG__seg_e__BITNR) | \ - (R_MMU_CONFIG__seg_d__##f7_##_VAL(R_MMU_CONFIG_, seg_d_, v7) << R_MMU_CONFIG__seg_d__BITNR) | \ - (R_MMU_CONFIG__seg_c__##f8_##_VAL(R_MMU_CONFIG_, seg_c_, v8) << R_MMU_CONFIG__seg_c__BITNR) | \ - (R_MMU_CONFIG__seg_b__##f9_##_VAL(R_MMU_CONFIG_, seg_b_, v9) << R_MMU_CONFIG__seg_b__BITNR) | \ - (R_MMU_CONFIG__seg_a__##f10_##_VAL(R_MMU_CONFIG_, seg_a_, v10) << R_MMU_CONFIG__seg_a__BITNR) | \ - (R_MMU_CONFIG__seg_9__##f11_##_VAL(R_MMU_CONFIG_, seg_9_, v11) << R_MMU_CONFIG__seg_9__BITNR) | \ - (R_MMU_CONFIG__seg_8__##f12_##_VAL(R_MMU_CONFIG_, seg_8_, v12) << R_MMU_CONFIG__seg_8__BITNR) | \ - (R_MMU_CONFIG__seg_7__##f13_##_VAL(R_MMU_CONFIG_, seg_7_, v13) << R_MMU_CONFIG__seg_7__BITNR) | \ - (R_MMU_CONFIG__seg_6__##f14_##_VAL(R_MMU_CONFIG_, seg_6_, v14) << R_MMU_CONFIG__seg_6__BITNR) | \ - (R_MMU_CONFIG__seg_5__##f15_##_VAL(R_MMU_CONFIG_, seg_5_, v15) << R_MMU_CONFIG__seg_5__BITNR) | \ - (R_MMU_CONFIG__seg_4__##f16_##_VAL(R_MMU_CONFIG_, seg_4_, v16) << R_MMU_CONFIG__seg_4__BITNR) | \ - (R_MMU_CONFIG__seg_3__##f17_##_VAL(R_MMU_CONFIG_, seg_3_, v17) << R_MMU_CONFIG__seg_3__BITNR) | \ - (R_MMU_CONFIG__seg_2__##f18_##_VAL(R_MMU_CONFIG_, seg_2_, v18) << R_MMU_CONFIG__seg_2__BITNR) | \ - (R_MMU_CONFIG__seg_1__##f19_##_VAL(R_MMU_CONFIG_, seg_1_, v19) << R_MMU_CONFIG__seg_1__BITNR) | \ - (R_MMU_CONFIG__seg_0__##f20_##_VAL(R_MMU_CONFIG_, seg_0_, v20) << R_MMU_CONFIG__seg_0__BITNR) \ -) - -#endif - -/* - * R_MMU_CONTEXT - * - type: RW - * - addr: 0xb000024c - * - group: MMU registers - */ - -#if USE_GROUP__MMU_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_MMU_CONTEXT -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_MMU_CONTEXT. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_MMU_CONTEXT. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_MMU_CONTEXT(f1,v1) ( \ - R_MMU_CONTEXT__WRITE(R_MMU_CONTEXT__ADDR, ( \ - REG_VAL__R_MMU_CONTEXT_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_MMU_CONTEXT -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_MMU_CONTEXT(f1,v1) ( \ - (R_MMU_CONTEXT__page_id__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_MMU_CONTEXT -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_MMU_CONTEXT. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_MMU_CONTEXT(f1,v1) ( \ - (R_MMU_CONTEXT__page_id__##f1##__VAL(R_MMU_CONTEXT_, page_id_, v1) << R_MMU_CONTEXT__page_id__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_MMU_CONTEXT_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_MMU_CONTEXT. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_MMU_CONTEXT_(f1_,v1) ( \ - (R_MMU_CONTEXT__page_id__##f1_##_VAL(R_MMU_CONTEXT_, page_id_, v1) << R_MMU_CONTEXT__page_id__BITNR) \ -) - -#endif - -/* - * R_MMU_CTRL - * - type: WO - * - addr: 0xb0000242 - * - group: MMU registers - */ - -#if USE_GROUP__MMU_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_MMU_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_MMU_CTRL. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_MMU_CTRL. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_MMU_CTRL(f1,v1,f2,v2,f3,v3) ( \ - *R_MMU_CTRL__SADDR = ( \ - REG_INITIATED(R_MMU_CTRL_) \ - REG_VAL__R_MMU_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3) \ - ), \ - R_MMU_CTRL__WRITE(R_MMU_CTRL__ADDR, *R_MMU_CTRL__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_MMU_CTRL__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_MMU_CTRL. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_MMU_CTRL. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_MMU_CTRL__SHADOW(f1,v1,f2,v2,f3,v3) ( \ - *R_MMU_CTRL__SADDR = ( \ - REG_INITIATED(R_MMU_CTRL_) \ - REG_VAL__R_MMU_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_MMU_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_MMU_CTRL(f1,v1,f2,v2,f3,v3) ( \ - (R_MMU_CTRL__inv_excp__##f1##__MASK & REG__##v1) | \ - (R_MMU_CTRL__acc_excp__##f2##__MASK & REG__##v2) | \ - (R_MMU_CTRL__we_excp__##f3##__MASK & REG__##v3) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_MMU_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_MMU_CTRL. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_MMU_CTRL(f1,v1,f2,v2,f3,v3) ( \ - (R_MMU_CTRL__inv_excp__##f1##__VAL(R_MMU_CTRL_, inv_excp_, v1) << R_MMU_CTRL__inv_excp__BITNR) | \ - (R_MMU_CTRL__acc_excp__##f2##__VAL(R_MMU_CTRL_, acc_excp_, v2) << R_MMU_CTRL__acc_excp__BITNR) | \ - (R_MMU_CTRL__we_excp__##f3##__VAL(R_MMU_CTRL_, we_excp_, v3) << R_MMU_CTRL__we_excp__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_MMU_CTRL_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_MMU_CTRL. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_MMU_CTRL_(f1_,v1,f2_,v2,f3_,v3) ( \ - (R_MMU_CTRL__inv_excp__##f1_##_VAL(R_MMU_CTRL_, inv_excp_, v1) << R_MMU_CTRL__inv_excp__BITNR) | \ - (R_MMU_CTRL__acc_excp__##f2_##_VAL(R_MMU_CTRL_, acc_excp_, v2) << R_MMU_CTRL__acc_excp__BITNR) | \ - (R_MMU_CTRL__we_excp__##f3_##_VAL(R_MMU_CTRL_, we_excp_, v3) << R_MMU_CTRL__we_excp__BITNR) \ -) - -#endif - -/* - * R_MMU_ENABLE - * - type: WO - * - addr: 0xb0000243 - * - group: MMU registers - */ - -#if USE_GROUP__MMU_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_MMU_ENABLE -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_MMU_ENABLE. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_MMU_ENABLE. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_MMU_ENABLE(f1,v1) ( \ - *R_MMU_ENABLE__SADDR = ( \ - REG_INITIATED(R_MMU_ENABLE_) \ - REG_VAL__R_MMU_ENABLE_(f1##_,v1) \ - ), \ - R_MMU_ENABLE__WRITE(R_MMU_ENABLE__ADDR, *R_MMU_ENABLE__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_MMU_ENABLE__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_MMU_ENABLE. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_MMU_ENABLE. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_MMU_ENABLE__SHADOW(f1,v1) ( \ - *R_MMU_ENABLE__SADDR = ( \ - REG_INITIATED(R_MMU_ENABLE_) \ - REG_VAL__R_MMU_ENABLE_(f1##_,v1) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_MMU_ENABLE -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_MMU_ENABLE(f1,v1) ( \ - (R_MMU_ENABLE__mmu_enable__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_MMU_ENABLE -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_MMU_ENABLE. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_MMU_ENABLE(f1,v1) ( \ - (R_MMU_ENABLE__mmu_enable__##f1##__VAL(R_MMU_ENABLE_, mmu_enable_, v1) << R_MMU_ENABLE__mmu_enable__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_MMU_ENABLE_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_MMU_ENABLE. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_MMU_ENABLE_(f1_,v1) ( \ - (R_MMU_ENABLE__mmu_enable__##f1_##_VAL(R_MMU_ENABLE_, mmu_enable_, v1) << R_MMU_ENABLE__mmu_enable__BITNR) \ -) - -#endif - -/* - * R_MMU_KBASE_HI - * - type: WO - * - addr: 0xb0000248 - * - group: MMU registers - */ - -#if USE_GROUP__MMU_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_MMU_KBASE_HI -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_MMU_KBASE_HI. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_MMU_KBASE_HI. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_MMU_KBASE_HI(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - *R_MMU_KBASE_HI__SADDR = ( \ - REG_INITIATED(R_MMU_KBASE_HI_) \ - REG_VAL__R_MMU_KBASE_HI_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \ - ), \ - R_MMU_KBASE_HI__WRITE(R_MMU_KBASE_HI__ADDR, *R_MMU_KBASE_HI__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_MMU_KBASE_HI__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_MMU_KBASE_HI. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_MMU_KBASE_HI. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_MMU_KBASE_HI__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - *R_MMU_KBASE_HI__SADDR = ( \ - REG_INITIATED(R_MMU_KBASE_HI_) \ - REG_VAL__R_MMU_KBASE_HI_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_MMU_KBASE_HI -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_MMU_KBASE_HI(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - (R_MMU_KBASE_HI__base_f__##f1##__MASK & REG__##v1) | \ - (R_MMU_KBASE_HI__base_e__##f2##__MASK & REG__##v2) | \ - (R_MMU_KBASE_HI__base_d__##f3##__MASK & REG__##v3) | \ - (R_MMU_KBASE_HI__base_c__##f4##__MASK & REG__##v4) | \ - (R_MMU_KBASE_HI__base_b__##f5##__MASK & REG__##v5) | \ - (R_MMU_KBASE_HI__base_a__##f6##__MASK & REG__##v6) | \ - (R_MMU_KBASE_HI__base_9__##f7##__MASK & REG__##v7) | \ - (R_MMU_KBASE_HI__base_8__##f8##__MASK & REG__##v8) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_MMU_KBASE_HI -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_MMU_KBASE_HI. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_MMU_KBASE_HI(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - (R_MMU_KBASE_HI__base_f__##f1##__VAL(R_MMU_KBASE_HI_, base_f_, v1) << R_MMU_KBASE_HI__base_f__BITNR) | \ - (R_MMU_KBASE_HI__base_e__##f2##__VAL(R_MMU_KBASE_HI_, base_e_, v2) << R_MMU_KBASE_HI__base_e__BITNR) | \ - (R_MMU_KBASE_HI__base_d__##f3##__VAL(R_MMU_KBASE_HI_, base_d_, v3) << R_MMU_KBASE_HI__base_d__BITNR) | \ - (R_MMU_KBASE_HI__base_c__##f4##__VAL(R_MMU_KBASE_HI_, base_c_, v4) << R_MMU_KBASE_HI__base_c__BITNR) | \ - (R_MMU_KBASE_HI__base_b__##f5##__VAL(R_MMU_KBASE_HI_, base_b_, v5) << R_MMU_KBASE_HI__base_b__BITNR) | \ - (R_MMU_KBASE_HI__base_a__##f6##__VAL(R_MMU_KBASE_HI_, base_a_, v6) << R_MMU_KBASE_HI__base_a__BITNR) | \ - (R_MMU_KBASE_HI__base_9__##f7##__VAL(R_MMU_KBASE_HI_, base_9_, v7) << R_MMU_KBASE_HI__base_9__BITNR) | \ - (R_MMU_KBASE_HI__base_8__##f8##__VAL(R_MMU_KBASE_HI_, base_8_, v8) << R_MMU_KBASE_HI__base_8__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_MMU_KBASE_HI_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_MMU_KBASE_HI. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_MMU_KBASE_HI_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8) ( \ - (R_MMU_KBASE_HI__base_f__##f1_##_VAL(R_MMU_KBASE_HI_, base_f_, v1) << R_MMU_KBASE_HI__base_f__BITNR) | \ - (R_MMU_KBASE_HI__base_e__##f2_##_VAL(R_MMU_KBASE_HI_, base_e_, v2) << R_MMU_KBASE_HI__base_e__BITNR) | \ - (R_MMU_KBASE_HI__base_d__##f3_##_VAL(R_MMU_KBASE_HI_, base_d_, v3) << R_MMU_KBASE_HI__base_d__BITNR) | \ - (R_MMU_KBASE_HI__base_c__##f4_##_VAL(R_MMU_KBASE_HI_, base_c_, v4) << R_MMU_KBASE_HI__base_c__BITNR) | \ - (R_MMU_KBASE_HI__base_b__##f5_##_VAL(R_MMU_KBASE_HI_, base_b_, v5) << R_MMU_KBASE_HI__base_b__BITNR) | \ - (R_MMU_KBASE_HI__base_a__##f6_##_VAL(R_MMU_KBASE_HI_, base_a_, v6) << R_MMU_KBASE_HI__base_a__BITNR) | \ - (R_MMU_KBASE_HI__base_9__##f7_##_VAL(R_MMU_KBASE_HI_, base_9_, v7) << R_MMU_KBASE_HI__base_9__BITNR) | \ - (R_MMU_KBASE_HI__base_8__##f8_##_VAL(R_MMU_KBASE_HI_, base_8_, v8) << R_MMU_KBASE_HI__base_8__BITNR) \ -) - -#endif - -/* - * R_MMU_KBASE_LO - * - type: WO - * - addr: 0xb0000244 - * - group: MMU registers - */ - -#if USE_GROUP__MMU_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_MMU_KBASE_LO -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_MMU_KBASE_LO. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_MMU_KBASE_LO. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_MMU_KBASE_LO(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - *R_MMU_KBASE_LO__SADDR = ( \ - REG_INITIATED(R_MMU_KBASE_LO_) \ - REG_VAL__R_MMU_KBASE_LO_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \ - ), \ - R_MMU_KBASE_LO__WRITE(R_MMU_KBASE_LO__ADDR, *R_MMU_KBASE_LO__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_MMU_KBASE_LO__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_MMU_KBASE_LO. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_MMU_KBASE_LO. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_MMU_KBASE_LO__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - *R_MMU_KBASE_LO__SADDR = ( \ - REG_INITIATED(R_MMU_KBASE_LO_) \ - REG_VAL__R_MMU_KBASE_LO_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_MMU_KBASE_LO -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_MMU_KBASE_LO(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - (R_MMU_KBASE_LO__base_7__##f1##__MASK & REG__##v1) | \ - (R_MMU_KBASE_LO__base_6__##f2##__MASK & REG__##v2) | \ - (R_MMU_KBASE_LO__base_5__##f3##__MASK & REG__##v3) | \ - (R_MMU_KBASE_LO__base_4__##f4##__MASK & REG__##v4) | \ - (R_MMU_KBASE_LO__base_3__##f5##__MASK & REG__##v5) | \ - (R_MMU_KBASE_LO__base_2__##f6##__MASK & REG__##v6) | \ - (R_MMU_KBASE_LO__base_1__##f7##__MASK & REG__##v7) | \ - (R_MMU_KBASE_LO__base_0__##f8##__MASK & REG__##v8) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_MMU_KBASE_LO -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_MMU_KBASE_LO. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_MMU_KBASE_LO(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - (R_MMU_KBASE_LO__base_7__##f1##__VAL(R_MMU_KBASE_LO_, base_7_, v1) << R_MMU_KBASE_LO__base_7__BITNR) | \ - (R_MMU_KBASE_LO__base_6__##f2##__VAL(R_MMU_KBASE_LO_, base_6_, v2) << R_MMU_KBASE_LO__base_6__BITNR) | \ - (R_MMU_KBASE_LO__base_5__##f3##__VAL(R_MMU_KBASE_LO_, base_5_, v3) << R_MMU_KBASE_LO__base_5__BITNR) | \ - (R_MMU_KBASE_LO__base_4__##f4##__VAL(R_MMU_KBASE_LO_, base_4_, v4) << R_MMU_KBASE_LO__base_4__BITNR) | \ - (R_MMU_KBASE_LO__base_3__##f5##__VAL(R_MMU_KBASE_LO_, base_3_, v5) << R_MMU_KBASE_LO__base_3__BITNR) | \ - (R_MMU_KBASE_LO__base_2__##f6##__VAL(R_MMU_KBASE_LO_, base_2_, v6) << R_MMU_KBASE_LO__base_2__BITNR) | \ - (R_MMU_KBASE_LO__base_1__##f7##__VAL(R_MMU_KBASE_LO_, base_1_, v7) << R_MMU_KBASE_LO__base_1__BITNR) | \ - (R_MMU_KBASE_LO__base_0__##f8##__VAL(R_MMU_KBASE_LO_, base_0_, v8) << R_MMU_KBASE_LO__base_0__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_MMU_KBASE_LO_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_MMU_KBASE_LO. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_MMU_KBASE_LO_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8) ( \ - (R_MMU_KBASE_LO__base_7__##f1_##_VAL(R_MMU_KBASE_LO_, base_7_, v1) << R_MMU_KBASE_LO__base_7__BITNR) | \ - (R_MMU_KBASE_LO__base_6__##f2_##_VAL(R_MMU_KBASE_LO_, base_6_, v2) << R_MMU_KBASE_LO__base_6__BITNR) | \ - (R_MMU_KBASE_LO__base_5__##f3_##_VAL(R_MMU_KBASE_LO_, base_5_, v3) << R_MMU_KBASE_LO__base_5__BITNR) | \ - (R_MMU_KBASE_LO__base_4__##f4_##_VAL(R_MMU_KBASE_LO_, base_4_, v4) << R_MMU_KBASE_LO__base_4__BITNR) | \ - (R_MMU_KBASE_LO__base_3__##f5_##_VAL(R_MMU_KBASE_LO_, base_3_, v5) << R_MMU_KBASE_LO__base_3__BITNR) | \ - (R_MMU_KBASE_LO__base_2__##f6_##_VAL(R_MMU_KBASE_LO_, base_2_, v6) << R_MMU_KBASE_LO__base_2__BITNR) | \ - (R_MMU_KBASE_LO__base_1__##f7_##_VAL(R_MMU_KBASE_LO_, base_1_, v7) << R_MMU_KBASE_LO__base_1__BITNR) | \ - (R_MMU_KBASE_LO__base_0__##f8_##_VAL(R_MMU_KBASE_LO_, base_0_, v8) << R_MMU_KBASE_LO__base_0__BITNR) \ -) - -#endif - -/* - * R_MMU_KSEG - * - type: WO - * - addr: 0xb0000240 - * - group: MMU registers - */ - -#if USE_GROUP__MMU_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_MMU_KSEG -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_MMU_KSEG. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_MMU_KSEG. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_MMU_KSEG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16) ( \ - *R_MMU_KSEG__SADDR = ( \ - REG_INITIATED(R_MMU_KSEG_) \ - REG_VAL__R_MMU_KSEG_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16) \ - ), \ - R_MMU_KSEG__WRITE(R_MMU_KSEG__ADDR, *R_MMU_KSEG__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_MMU_KSEG__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_MMU_KSEG. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_MMU_KSEG. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_MMU_KSEG__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16) ( \ - *R_MMU_KSEG__SADDR = ( \ - REG_INITIATED(R_MMU_KSEG_) \ - REG_VAL__R_MMU_KSEG_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_MMU_KSEG -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_MMU_KSEG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16) ( \ - (R_MMU_KSEG__seg_f__##f1##__MASK & REG__##v1) | \ - (R_MMU_KSEG__seg_e__##f2##__MASK & REG__##v2) | \ - (R_MMU_KSEG__seg_d__##f3##__MASK & REG__##v3) | \ - (R_MMU_KSEG__seg_c__##f4##__MASK & REG__##v4) | \ - (R_MMU_KSEG__seg_b__##f5##__MASK & REG__##v5) | \ - (R_MMU_KSEG__seg_a__##f6##__MASK & REG__##v6) | \ - (R_MMU_KSEG__seg_9__##f7##__MASK & REG__##v7) | \ - (R_MMU_KSEG__seg_8__##f8##__MASK & REG__##v8) | \ - (R_MMU_KSEG__seg_7__##f9##__MASK & REG__##v9) | \ - (R_MMU_KSEG__seg_6__##f10##__MASK & REG__##v10) | \ - (R_MMU_KSEG__seg_5__##f11##__MASK & REG__##v11) | \ - (R_MMU_KSEG__seg_4__##f12##__MASK & REG__##v12) | \ - (R_MMU_KSEG__seg_3__##f13##__MASK & REG__##v13) | \ - (R_MMU_KSEG__seg_2__##f14##__MASK & REG__##v14) | \ - (R_MMU_KSEG__seg_1__##f15##__MASK & REG__##v15) | \ - (R_MMU_KSEG__seg_0__##f16##__MASK & REG__##v16) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_MMU_KSEG -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_MMU_KSEG. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_MMU_KSEG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16) ( \ - (R_MMU_KSEG__seg_f__##f1##__VAL(R_MMU_KSEG_, seg_f_, v1) << R_MMU_KSEG__seg_f__BITNR) | \ - (R_MMU_KSEG__seg_e__##f2##__VAL(R_MMU_KSEG_, seg_e_, v2) << R_MMU_KSEG__seg_e__BITNR) | \ - (R_MMU_KSEG__seg_d__##f3##__VAL(R_MMU_KSEG_, seg_d_, v3) << R_MMU_KSEG__seg_d__BITNR) | \ - (R_MMU_KSEG__seg_c__##f4##__VAL(R_MMU_KSEG_, seg_c_, v4) << R_MMU_KSEG__seg_c__BITNR) | \ - (R_MMU_KSEG__seg_b__##f5##__VAL(R_MMU_KSEG_, seg_b_, v5) << R_MMU_KSEG__seg_b__BITNR) | \ - (R_MMU_KSEG__seg_a__##f6##__VAL(R_MMU_KSEG_, seg_a_, v6) << R_MMU_KSEG__seg_a__BITNR) | \ - (R_MMU_KSEG__seg_9__##f7##__VAL(R_MMU_KSEG_, seg_9_, v7) << R_MMU_KSEG__seg_9__BITNR) | \ - (R_MMU_KSEG__seg_8__##f8##__VAL(R_MMU_KSEG_, seg_8_, v8) << R_MMU_KSEG__seg_8__BITNR) | \ - (R_MMU_KSEG__seg_7__##f9##__VAL(R_MMU_KSEG_, seg_7_, v9) << R_MMU_KSEG__seg_7__BITNR) | \ - (R_MMU_KSEG__seg_6__##f10##__VAL(R_MMU_KSEG_, seg_6_, v10) << R_MMU_KSEG__seg_6__BITNR) | \ - (R_MMU_KSEG__seg_5__##f11##__VAL(R_MMU_KSEG_, seg_5_, v11) << R_MMU_KSEG__seg_5__BITNR) | \ - (R_MMU_KSEG__seg_4__##f12##__VAL(R_MMU_KSEG_, seg_4_, v12) << R_MMU_KSEG__seg_4__BITNR) | \ - (R_MMU_KSEG__seg_3__##f13##__VAL(R_MMU_KSEG_, seg_3_, v13) << R_MMU_KSEG__seg_3__BITNR) | \ - (R_MMU_KSEG__seg_2__##f14##__VAL(R_MMU_KSEG_, seg_2_, v14) << R_MMU_KSEG__seg_2__BITNR) | \ - (R_MMU_KSEG__seg_1__##f15##__VAL(R_MMU_KSEG_, seg_1_, v15) << R_MMU_KSEG__seg_1__BITNR) | \ - (R_MMU_KSEG__seg_0__##f16##__VAL(R_MMU_KSEG_, seg_0_, v16) << R_MMU_KSEG__seg_0__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_MMU_KSEG_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_MMU_KSEG. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_MMU_KSEG_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16) ( \ - (R_MMU_KSEG__seg_f__##f1_##_VAL(R_MMU_KSEG_, seg_f_, v1) << R_MMU_KSEG__seg_f__BITNR) | \ - (R_MMU_KSEG__seg_e__##f2_##_VAL(R_MMU_KSEG_, seg_e_, v2) << R_MMU_KSEG__seg_e__BITNR) | \ - (R_MMU_KSEG__seg_d__##f3_##_VAL(R_MMU_KSEG_, seg_d_, v3) << R_MMU_KSEG__seg_d__BITNR) | \ - (R_MMU_KSEG__seg_c__##f4_##_VAL(R_MMU_KSEG_, seg_c_, v4) << R_MMU_KSEG__seg_c__BITNR) | \ - (R_MMU_KSEG__seg_b__##f5_##_VAL(R_MMU_KSEG_, seg_b_, v5) << R_MMU_KSEG__seg_b__BITNR) | \ - (R_MMU_KSEG__seg_a__##f6_##_VAL(R_MMU_KSEG_, seg_a_, v6) << R_MMU_KSEG__seg_a__BITNR) | \ - (R_MMU_KSEG__seg_9__##f7_##_VAL(R_MMU_KSEG_, seg_9_, v7) << R_MMU_KSEG__seg_9__BITNR) | \ - (R_MMU_KSEG__seg_8__##f8_##_VAL(R_MMU_KSEG_, seg_8_, v8) << R_MMU_KSEG__seg_8__BITNR) | \ - (R_MMU_KSEG__seg_7__##f9_##_VAL(R_MMU_KSEG_, seg_7_, v9) << R_MMU_KSEG__seg_7__BITNR) | \ - (R_MMU_KSEG__seg_6__##f10_##_VAL(R_MMU_KSEG_, seg_6_, v10) << R_MMU_KSEG__seg_6__BITNR) | \ - (R_MMU_KSEG__seg_5__##f11_##_VAL(R_MMU_KSEG_, seg_5_, v11) << R_MMU_KSEG__seg_5__BITNR) | \ - (R_MMU_KSEG__seg_4__##f12_##_VAL(R_MMU_KSEG_, seg_4_, v12) << R_MMU_KSEG__seg_4__BITNR) | \ - (R_MMU_KSEG__seg_3__##f13_##_VAL(R_MMU_KSEG_, seg_3_, v13) << R_MMU_KSEG__seg_3__BITNR) | \ - (R_MMU_KSEG__seg_2__##f14_##_VAL(R_MMU_KSEG_, seg_2_, v14) << R_MMU_KSEG__seg_2__BITNR) | \ - (R_MMU_KSEG__seg_1__##f15_##_VAL(R_MMU_KSEG_, seg_1_, v15) << R_MMU_KSEG__seg_1__BITNR) | \ - (R_MMU_KSEG__seg_0__##f16_##_VAL(R_MMU_KSEG_, seg_0_, v16) << R_MMU_KSEG__seg_0__BITNR) \ -) - -#endif - -/* - * R_NETWORK_GA_0 - * - type: WO - * - addr: 0xb000008c - * - group: Network interface registers - */ - -#if USE_GROUP__Network_interface_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_NETWORK_GA_0 -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_NETWORK_GA_0. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_NETWORK_GA_0. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_NETWORK_GA_0(f1,v1) ( \ - *R_NETWORK_GA_0__SADDR = ( \ - REG_INITIATED(R_NETWORK_GA_0_) \ - REG_VAL__R_NETWORK_GA_0_(f1##_,v1) \ - ), \ - R_NETWORK_GA_0__WRITE(R_NETWORK_GA_0__ADDR, *R_NETWORK_GA_0__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_NETWORK_GA_0__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_NETWORK_GA_0. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_NETWORK_GA_0. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_NETWORK_GA_0__SHADOW(f1,v1) ( \ - *R_NETWORK_GA_0__SADDR = ( \ - REG_INITIATED(R_NETWORK_GA_0_) \ - REG_VAL__R_NETWORK_GA_0_(f1##_,v1) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_NETWORK_GA_0 -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_NETWORK_GA_0(f1,v1) ( \ - (R_NETWORK_GA_0__ga_low__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_NETWORK_GA_0 -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_NETWORK_GA_0. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_NETWORK_GA_0(f1,v1) ( \ - (R_NETWORK_GA_0__ga_low__##f1##__VAL(R_NETWORK_GA_0_, ga_low_, v1) << R_NETWORK_GA_0__ga_low__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_NETWORK_GA_0_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_NETWORK_GA_0. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_NETWORK_GA_0_(f1_,v1) ( \ - (R_NETWORK_GA_0__ga_low__##f1_##_VAL(R_NETWORK_GA_0_, ga_low_, v1) << R_NETWORK_GA_0__ga_low__BITNR) \ -) - -#endif - -/* - * R_NETWORK_GA_1 - * - type: WO - * - addr: 0xb0000090 - * - group: Network interface registers - */ - -#if USE_GROUP__Network_interface_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_NETWORK_GA_1 -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_NETWORK_GA_1. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_NETWORK_GA_1. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_NETWORK_GA_1(f1,v1) ( \ - *R_NETWORK_GA_1__SADDR = ( \ - REG_INITIATED(R_NETWORK_GA_1_) \ - REG_VAL__R_NETWORK_GA_1_(f1##_,v1) \ - ), \ - R_NETWORK_GA_1__WRITE(R_NETWORK_GA_1__ADDR, *R_NETWORK_GA_1__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_NETWORK_GA_1__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_NETWORK_GA_1. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_NETWORK_GA_1. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_NETWORK_GA_1__SHADOW(f1,v1) ( \ - *R_NETWORK_GA_1__SADDR = ( \ - REG_INITIATED(R_NETWORK_GA_1_) \ - REG_VAL__R_NETWORK_GA_1_(f1##_,v1) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_NETWORK_GA_1 -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_NETWORK_GA_1(f1,v1) ( \ - (R_NETWORK_GA_1__ga_high__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_NETWORK_GA_1 -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_NETWORK_GA_1. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_NETWORK_GA_1(f1,v1) ( \ - (R_NETWORK_GA_1__ga_high__##f1##__VAL(R_NETWORK_GA_1_, ga_high_, v1) << R_NETWORK_GA_1__ga_high__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_NETWORK_GA_1_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_NETWORK_GA_1. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_NETWORK_GA_1_(f1_,v1) ( \ - (R_NETWORK_GA_1__ga_high__##f1_##_VAL(R_NETWORK_GA_1_, ga_high_, v1) << R_NETWORK_GA_1__ga_high__BITNR) \ -) - -#endif - -/* - * R_NETWORK_GEN_CONFIG - * - type: WO - * - addr: 0xb0000098 - * - group: Network interface registers - */ - -#if USE_GROUP__Network_interface_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_NETWORK_GEN_CONFIG -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_NETWORK_GEN_CONFIG. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_NETWORK_GEN_CONFIG. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_NETWORK_GEN_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5) ( \ - *R_NETWORK_GEN_CONFIG__SADDR = ( \ - REG_INITIATED(R_NETWORK_GEN_CONFIG_) \ - REG_VAL__R_NETWORK_GEN_CONFIG_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5) \ - ), \ - R_NETWORK_GEN_CONFIG__WRITE(R_NETWORK_GEN_CONFIG__ADDR, *R_NETWORK_GEN_CONFIG__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_NETWORK_GEN_CONFIG__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_NETWORK_GEN_CONFIG. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_NETWORK_GEN_CONFIG. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_NETWORK_GEN_CONFIG__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5) ( \ - *R_NETWORK_GEN_CONFIG__SADDR = ( \ - REG_INITIATED(R_NETWORK_GEN_CONFIG_) \ - REG_VAL__R_NETWORK_GEN_CONFIG_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_NETWORK_GEN_CONFIG -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_NETWORK_GEN_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5) ( \ - (R_NETWORK_GEN_CONFIG__loopback__##f1##__MASK & REG__##v1) | \ - (R_NETWORK_GEN_CONFIG__frame__##f2##__MASK & REG__##v2) | \ - (R_NETWORK_GEN_CONFIG__vg__##f3##__MASK & REG__##v3) | \ - (R_NETWORK_GEN_CONFIG__phy__##f4##__MASK & REG__##v4) | \ - (R_NETWORK_GEN_CONFIG__enable__##f5##__MASK & REG__##v5) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_NETWORK_GEN_CONFIG -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_NETWORK_GEN_CONFIG. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_NETWORK_GEN_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5) ( \ - (R_NETWORK_GEN_CONFIG__loopback__##f1##__VAL(R_NETWORK_GEN_CONFIG_, loopback_, v1) << R_NETWORK_GEN_CONFIG__loopback__BITNR) | \ - (R_NETWORK_GEN_CONFIG__frame__##f2##__VAL(R_NETWORK_GEN_CONFIG_, frame_, v2) << R_NETWORK_GEN_CONFIG__frame__BITNR) | \ - (R_NETWORK_GEN_CONFIG__vg__##f3##__VAL(R_NETWORK_GEN_CONFIG_, vg_, v3) << R_NETWORK_GEN_CONFIG__vg__BITNR) | \ - (R_NETWORK_GEN_CONFIG__phy__##f4##__VAL(R_NETWORK_GEN_CONFIG_, phy_, v4) << R_NETWORK_GEN_CONFIG__phy__BITNR) | \ - (R_NETWORK_GEN_CONFIG__enable__##f5##__VAL(R_NETWORK_GEN_CONFIG_, enable_, v5) << R_NETWORK_GEN_CONFIG__enable__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_NETWORK_GEN_CONFIG_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_NETWORK_GEN_CONFIG. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_NETWORK_GEN_CONFIG_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5) ( \ - (R_NETWORK_GEN_CONFIG__loopback__##f1_##_VAL(R_NETWORK_GEN_CONFIG_, loopback_, v1) << R_NETWORK_GEN_CONFIG__loopback__BITNR) | \ - (R_NETWORK_GEN_CONFIG__frame__##f2_##_VAL(R_NETWORK_GEN_CONFIG_, frame_, v2) << R_NETWORK_GEN_CONFIG__frame__BITNR) | \ - (R_NETWORK_GEN_CONFIG__vg__##f3_##_VAL(R_NETWORK_GEN_CONFIG_, vg_, v3) << R_NETWORK_GEN_CONFIG__vg__BITNR) | \ - (R_NETWORK_GEN_CONFIG__phy__##f4_##_VAL(R_NETWORK_GEN_CONFIG_, phy_, v4) << R_NETWORK_GEN_CONFIG__phy__BITNR) | \ - (R_NETWORK_GEN_CONFIG__enable__##f5_##_VAL(R_NETWORK_GEN_CONFIG_, enable_, v5) << R_NETWORK_GEN_CONFIG__enable__BITNR) \ -) - -#endif - -/* - * R_NETWORK_MGM_CTRL - * - type: WO - * - addr: 0xb00000a0 - * - group: Network interface registers - */ - -#if USE_GROUP__Network_interface_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_NETWORK_MGM_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_NETWORK_MGM_CTRL. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_NETWORK_MGM_CTRL. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_NETWORK_MGM_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5) ( \ - *R_NETWORK_MGM_CTRL__SADDR = ( \ - REG_INITIATED(R_NETWORK_MGM_CTRL_) \ - REG_VAL__R_NETWORK_MGM_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5) \ - ), \ - R_NETWORK_MGM_CTRL__WRITE(R_NETWORK_MGM_CTRL__ADDR, *R_NETWORK_MGM_CTRL__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_NETWORK_MGM_CTRL__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_NETWORK_MGM_CTRL. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_NETWORK_MGM_CTRL. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_NETWORK_MGM_CTRL__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5) ( \ - *R_NETWORK_MGM_CTRL__SADDR = ( \ - REG_INITIATED(R_NETWORK_MGM_CTRL_) \ - REG_VAL__R_NETWORK_MGM_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_NETWORK_MGM_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_NETWORK_MGM_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5) ( \ - (R_NETWORK_MGM_CTRL__txd_pins__##f1##__MASK & REG__##v1) | \ - (R_NETWORK_MGM_CTRL__txer_pin__##f2##__MASK & REG__##v2) | \ - (R_NETWORK_MGM_CTRL__mdck__##f3##__MASK & REG__##v3) | \ - (R_NETWORK_MGM_CTRL__mdoe__##f4##__MASK & REG__##v4) | \ - (R_NETWORK_MGM_CTRL__mdio__##f5##__MASK & REG__##v5) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_NETWORK_MGM_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_NETWORK_MGM_CTRL. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_NETWORK_MGM_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5) ( \ - (R_NETWORK_MGM_CTRL__txd_pins__##f1##__VAL(R_NETWORK_MGM_CTRL_, txd_pins_, v1) << R_NETWORK_MGM_CTRL__txd_pins__BITNR) | \ - (R_NETWORK_MGM_CTRL__txer_pin__##f2##__VAL(R_NETWORK_MGM_CTRL_, txer_pin_, v2) << R_NETWORK_MGM_CTRL__txer_pin__BITNR) | \ - (R_NETWORK_MGM_CTRL__mdck__##f3##__VAL(R_NETWORK_MGM_CTRL_, mdck_, v3) << R_NETWORK_MGM_CTRL__mdck__BITNR) | \ - (R_NETWORK_MGM_CTRL__mdoe__##f4##__VAL(R_NETWORK_MGM_CTRL_, mdoe_, v4) << R_NETWORK_MGM_CTRL__mdoe__BITNR) | \ - (R_NETWORK_MGM_CTRL__mdio__##f5##__VAL(R_NETWORK_MGM_CTRL_, mdio_, v5) << R_NETWORK_MGM_CTRL__mdio__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_NETWORK_MGM_CTRL_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_NETWORK_MGM_CTRL. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_NETWORK_MGM_CTRL_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5) ( \ - (R_NETWORK_MGM_CTRL__txd_pins__##f1_##_VAL(R_NETWORK_MGM_CTRL_, txd_pins_, v1) << R_NETWORK_MGM_CTRL__txd_pins__BITNR) | \ - (R_NETWORK_MGM_CTRL__txer_pin__##f2_##_VAL(R_NETWORK_MGM_CTRL_, txer_pin_, v2) << R_NETWORK_MGM_CTRL__txer_pin__BITNR) | \ - (R_NETWORK_MGM_CTRL__mdck__##f3_##_VAL(R_NETWORK_MGM_CTRL_, mdck_, v3) << R_NETWORK_MGM_CTRL__mdck__BITNR) | \ - (R_NETWORK_MGM_CTRL__mdoe__##f4_##_VAL(R_NETWORK_MGM_CTRL_, mdoe_, v4) << R_NETWORK_MGM_CTRL__mdoe__BITNR) | \ - (R_NETWORK_MGM_CTRL__mdio__##f5_##_VAL(R_NETWORK_MGM_CTRL_, mdio_, v5) << R_NETWORK_MGM_CTRL__mdio__BITNR) \ -) - -#endif - -/* - * R_NETWORK_REC_CONFIG - * - type: WO - * - addr: 0xb0000094 - * - group: Network interface registers - */ - -#if USE_GROUP__Network_interface_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_NETWORK_REC_CONFIG -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_NETWORK_REC_CONFIG. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_NETWORK_REC_CONFIG. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_NETWORK_REC_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11) ( \ - *R_NETWORK_REC_CONFIG__SADDR = ( \ - REG_INITIATED(R_NETWORK_REC_CONFIG_) \ - REG_VAL__R_NETWORK_REC_CONFIG_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11) \ - ), \ - R_NETWORK_REC_CONFIG__WRITE(R_NETWORK_REC_CONFIG__ADDR, *R_NETWORK_REC_CONFIG__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_NETWORK_REC_CONFIG__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_NETWORK_REC_CONFIG. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_NETWORK_REC_CONFIG. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_NETWORK_REC_CONFIG__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11) ( \ - *R_NETWORK_REC_CONFIG__SADDR = ( \ - REG_INITIATED(R_NETWORK_REC_CONFIG_) \ - REG_VAL__R_NETWORK_REC_CONFIG_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_NETWORK_REC_CONFIG -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_NETWORK_REC_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11) ( \ - (R_NETWORK_REC_CONFIG__max_size__##f1##__MASK & REG__##v1) | \ - (R_NETWORK_REC_CONFIG__duplex__##f2##__MASK & REG__##v2) | \ - (R_NETWORK_REC_CONFIG__bad_crc__##f3##__MASK & REG__##v3) | \ - (R_NETWORK_REC_CONFIG__oversize__##f4##__MASK & REG__##v4) | \ - (R_NETWORK_REC_CONFIG__undersize__##f5##__MASK & REG__##v5) | \ - (R_NETWORK_REC_CONFIG__all_roots__##f6##__MASK & REG__##v6) | \ - (R_NETWORK_REC_CONFIG__tr_broadcast__##f7##__MASK & REG__##v7) | \ - (R_NETWORK_REC_CONFIG__broadcast__##f8##__MASK & REG__##v8) | \ - (R_NETWORK_REC_CONFIG__individual__##f9##__MASK & REG__##v9) | \ - (R_NETWORK_REC_CONFIG__ma1__##f10##__MASK & REG__##v10) | \ - (R_NETWORK_REC_CONFIG__ma0__##f11##__MASK & REG__##v11) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_NETWORK_REC_CONFIG -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_NETWORK_REC_CONFIG. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_NETWORK_REC_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11) ( \ - (R_NETWORK_REC_CONFIG__max_size__##f1##__VAL(R_NETWORK_REC_CONFIG_, max_size_, v1) << R_NETWORK_REC_CONFIG__max_size__BITNR) | \ - (R_NETWORK_REC_CONFIG__duplex__##f2##__VAL(R_NETWORK_REC_CONFIG_, duplex_, v2) << R_NETWORK_REC_CONFIG__duplex__BITNR) | \ - (R_NETWORK_REC_CONFIG__bad_crc__##f3##__VAL(R_NETWORK_REC_CONFIG_, bad_crc_, v3) << R_NETWORK_REC_CONFIG__bad_crc__BITNR) | \ - (R_NETWORK_REC_CONFIG__oversize__##f4##__VAL(R_NETWORK_REC_CONFIG_, oversize_, v4) << R_NETWORK_REC_CONFIG__oversize__BITNR) | \ - (R_NETWORK_REC_CONFIG__undersize__##f5##__VAL(R_NETWORK_REC_CONFIG_, undersize_, v5) << R_NETWORK_REC_CONFIG__undersize__BITNR) | \ - (R_NETWORK_REC_CONFIG__all_roots__##f6##__VAL(R_NETWORK_REC_CONFIG_, all_roots_, v6) << R_NETWORK_REC_CONFIG__all_roots__BITNR) | \ - (R_NETWORK_REC_CONFIG__tr_broadcast__##f7##__VAL(R_NETWORK_REC_CONFIG_, tr_broadcast_, v7) << R_NETWORK_REC_CONFIG__tr_broadcast__BITNR) | \ - (R_NETWORK_REC_CONFIG__broadcast__##f8##__VAL(R_NETWORK_REC_CONFIG_, broadcast_, v8) << R_NETWORK_REC_CONFIG__broadcast__BITNR) | \ - (R_NETWORK_REC_CONFIG__individual__##f9##__VAL(R_NETWORK_REC_CONFIG_, individual_, v9) << R_NETWORK_REC_CONFIG__individual__BITNR) | \ - (R_NETWORK_REC_CONFIG__ma1__##f10##__VAL(R_NETWORK_REC_CONFIG_, ma1_, v10) << R_NETWORK_REC_CONFIG__ma1__BITNR) | \ - (R_NETWORK_REC_CONFIG__ma0__##f11##__VAL(R_NETWORK_REC_CONFIG_, ma0_, v11) << R_NETWORK_REC_CONFIG__ma0__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_NETWORK_REC_CONFIG_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_NETWORK_REC_CONFIG. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_NETWORK_REC_CONFIG_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11) ( \ - (R_NETWORK_REC_CONFIG__max_size__##f1_##_VAL(R_NETWORK_REC_CONFIG_, max_size_, v1) << R_NETWORK_REC_CONFIG__max_size__BITNR) | \ - (R_NETWORK_REC_CONFIG__duplex__##f2_##_VAL(R_NETWORK_REC_CONFIG_, duplex_, v2) << R_NETWORK_REC_CONFIG__duplex__BITNR) | \ - (R_NETWORK_REC_CONFIG__bad_crc__##f3_##_VAL(R_NETWORK_REC_CONFIG_, bad_crc_, v3) << R_NETWORK_REC_CONFIG__bad_crc__BITNR) | \ - (R_NETWORK_REC_CONFIG__oversize__##f4_##_VAL(R_NETWORK_REC_CONFIG_, oversize_, v4) << R_NETWORK_REC_CONFIG__oversize__BITNR) | \ - (R_NETWORK_REC_CONFIG__undersize__##f5_##_VAL(R_NETWORK_REC_CONFIG_, undersize_, v5) << R_NETWORK_REC_CONFIG__undersize__BITNR) | \ - (R_NETWORK_REC_CONFIG__all_roots__##f6_##_VAL(R_NETWORK_REC_CONFIG_, all_roots_, v6) << R_NETWORK_REC_CONFIG__all_roots__BITNR) | \ - (R_NETWORK_REC_CONFIG__tr_broadcast__##f7_##_VAL(R_NETWORK_REC_CONFIG_, tr_broadcast_, v7) << R_NETWORK_REC_CONFIG__tr_broadcast__BITNR) | \ - (R_NETWORK_REC_CONFIG__broadcast__##f8_##_VAL(R_NETWORK_REC_CONFIG_, broadcast_, v8) << R_NETWORK_REC_CONFIG__broadcast__BITNR) | \ - (R_NETWORK_REC_CONFIG__individual__##f9_##_VAL(R_NETWORK_REC_CONFIG_, individual_, v9) << R_NETWORK_REC_CONFIG__individual__BITNR) | \ - (R_NETWORK_REC_CONFIG__ma1__##f10_##_VAL(R_NETWORK_REC_CONFIG_, ma1_, v10) << R_NETWORK_REC_CONFIG__ma1__BITNR) | \ - (R_NETWORK_REC_CONFIG__ma0__##f11_##_VAL(R_NETWORK_REC_CONFIG_, ma0_, v11) << R_NETWORK_REC_CONFIG__ma0__BITNR) \ -) - -#endif - -/* - * R_NETWORK_SA_0 - * - type: WO - * - addr: 0xb0000080 - * - group: Network interface registers - */ - -#if USE_GROUP__Network_interface_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_NETWORK_SA_0 -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_NETWORK_SA_0. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_NETWORK_SA_0. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_NETWORK_SA_0(f1,v1) ( \ - *R_NETWORK_SA_0__SADDR = ( \ - REG_INITIATED(R_NETWORK_SA_0_) \ - REG_VAL__R_NETWORK_SA_0_(f1##_,v1) \ - ), \ - R_NETWORK_SA_0__WRITE(R_NETWORK_SA_0__ADDR, *R_NETWORK_SA_0__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_NETWORK_SA_0__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_NETWORK_SA_0. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_NETWORK_SA_0. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_NETWORK_SA_0__SHADOW(f1,v1) ( \ - *R_NETWORK_SA_0__SADDR = ( \ - REG_INITIATED(R_NETWORK_SA_0_) \ - REG_VAL__R_NETWORK_SA_0_(f1##_,v1) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_NETWORK_SA_0 -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_NETWORK_SA_0(f1,v1) ( \ - (R_NETWORK_SA_0__ma0_low__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_NETWORK_SA_0 -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_NETWORK_SA_0. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_NETWORK_SA_0(f1,v1) ( \ - (R_NETWORK_SA_0__ma0_low__##f1##__VAL(R_NETWORK_SA_0_, ma0_low_, v1) << R_NETWORK_SA_0__ma0_low__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_NETWORK_SA_0_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_NETWORK_SA_0. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_NETWORK_SA_0_(f1_,v1) ( \ - (R_NETWORK_SA_0__ma0_low__##f1_##_VAL(R_NETWORK_SA_0_, ma0_low_, v1) << R_NETWORK_SA_0__ma0_low__BITNR) \ -) - -#endif - -/* - * R_NETWORK_SA_1 - * - type: WO - * - addr: 0xb0000084 - * - group: Network interface registers - */ - -#if USE_GROUP__Network_interface_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_NETWORK_SA_1 -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_NETWORK_SA_1. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_NETWORK_SA_1. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_NETWORK_SA_1(f1,v1,f2,v2) ( \ - *R_NETWORK_SA_1__SADDR = ( \ - REG_INITIATED(R_NETWORK_SA_1_) \ - REG_VAL__R_NETWORK_SA_1_(f1##_,v1,f2##_,v2) \ - ), \ - R_NETWORK_SA_1__WRITE(R_NETWORK_SA_1__ADDR, *R_NETWORK_SA_1__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_NETWORK_SA_1__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_NETWORK_SA_1. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_NETWORK_SA_1. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_NETWORK_SA_1__SHADOW(f1,v1,f2,v2) ( \ - *R_NETWORK_SA_1__SADDR = ( \ - REG_INITIATED(R_NETWORK_SA_1_) \ - REG_VAL__R_NETWORK_SA_1_(f1##_,v1,f2##_,v2) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_NETWORK_SA_1 -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_NETWORK_SA_1(f1,v1,f2,v2) ( \ - (R_NETWORK_SA_1__ma1_low__##f1##__MASK & REG__##v1) | \ - (R_NETWORK_SA_1__ma0_high__##f2##__MASK & REG__##v2) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_NETWORK_SA_1 -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_NETWORK_SA_1. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_NETWORK_SA_1(f1,v1,f2,v2) ( \ - (R_NETWORK_SA_1__ma1_low__##f1##__VAL(R_NETWORK_SA_1_, ma1_low_, v1) << R_NETWORK_SA_1__ma1_low__BITNR) | \ - (R_NETWORK_SA_1__ma0_high__##f2##__VAL(R_NETWORK_SA_1_, ma0_high_, v2) << R_NETWORK_SA_1__ma0_high__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_NETWORK_SA_1_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_NETWORK_SA_1. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_NETWORK_SA_1_(f1_,v1,f2_,v2) ( \ - (R_NETWORK_SA_1__ma1_low__##f1_##_VAL(R_NETWORK_SA_1_, ma1_low_, v1) << R_NETWORK_SA_1__ma1_low__BITNR) | \ - (R_NETWORK_SA_1__ma0_high__##f2_##_VAL(R_NETWORK_SA_1_, ma0_high_, v2) << R_NETWORK_SA_1__ma0_high__BITNR) \ -) - -#endif - -/* - * R_NETWORK_SA_2 - * - type: WO - * - addr: 0xb0000088 - * - group: Network interface registers - */ - -#if USE_GROUP__Network_interface_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_NETWORK_SA_2 -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_NETWORK_SA_2. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_NETWORK_SA_2. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_NETWORK_SA_2(f1,v1) ( \ - *R_NETWORK_SA_2__SADDR = ( \ - REG_INITIATED(R_NETWORK_SA_2_) \ - REG_VAL__R_NETWORK_SA_2_(f1##_,v1) \ - ), \ - R_NETWORK_SA_2__WRITE(R_NETWORK_SA_2__ADDR, *R_NETWORK_SA_2__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_NETWORK_SA_2__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_NETWORK_SA_2. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_NETWORK_SA_2. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_NETWORK_SA_2__SHADOW(f1,v1) ( \ - *R_NETWORK_SA_2__SADDR = ( \ - REG_INITIATED(R_NETWORK_SA_2_) \ - REG_VAL__R_NETWORK_SA_2_(f1##_,v1) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_NETWORK_SA_2 -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_NETWORK_SA_2(f1,v1) ( \ - (R_NETWORK_SA_2__ma1_high__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_NETWORK_SA_2 -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_NETWORK_SA_2. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_NETWORK_SA_2(f1,v1) ( \ - (R_NETWORK_SA_2__ma1_high__##f1##__VAL(R_NETWORK_SA_2_, ma1_high_, v1) << R_NETWORK_SA_2__ma1_high__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_NETWORK_SA_2_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_NETWORK_SA_2. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_NETWORK_SA_2_(f1_,v1) ( \ - (R_NETWORK_SA_2__ma1_high__##f1_##_VAL(R_NETWORK_SA_2_, ma1_high_, v1) << R_NETWORK_SA_2__ma1_high__BITNR) \ -) - -#endif - -/* - * R_NETWORK_STAT - * - type: RO - * - addr: 0xb00000a0 - * - group: Network interface registers - */ - -#if USE_GROUP__Network_interface_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_NETWORK_STAT -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_NETWORK_STAT(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5) ( \ - (R_NETWORK_STAT__rxd_pins__##f1##__MASK & REG__##v1) | \ - (R_NETWORK_STAT__rxer__##f2##__MASK & REG__##v2) | \ - (R_NETWORK_STAT__underrun__##f3##__MASK & REG__##v3) | \ - (R_NETWORK_STAT__exc_col__##f4##__MASK & REG__##v4) | \ - (R_NETWORK_STAT__mdio__##f5##__MASK & REG__##v5) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_NETWORK_STAT -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_NETWORK_STAT. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_NETWORK_STAT(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5) ( \ - (R_NETWORK_STAT__rxd_pins__##f1##__VAL(R_NETWORK_STAT_, rxd_pins_, v1) << R_NETWORK_STAT__rxd_pins__BITNR) | \ - (R_NETWORK_STAT__rxer__##f2##__VAL(R_NETWORK_STAT_, rxer_, v2) << R_NETWORK_STAT__rxer__BITNR) | \ - (R_NETWORK_STAT__underrun__##f3##__VAL(R_NETWORK_STAT_, underrun_, v3) << R_NETWORK_STAT__underrun__BITNR) | \ - (R_NETWORK_STAT__exc_col__##f4##__VAL(R_NETWORK_STAT_, exc_col_, v4) << R_NETWORK_STAT__exc_col__BITNR) | \ - (R_NETWORK_STAT__mdio__##f5##__VAL(R_NETWORK_STAT_, mdio_, v5) << R_NETWORK_STAT__mdio__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_NETWORK_STAT_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_NETWORK_STAT. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_NETWORK_STAT_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5) ( \ - (R_NETWORK_STAT__rxd_pins__##f1_##_VAL(R_NETWORK_STAT_, rxd_pins_, v1) << R_NETWORK_STAT__rxd_pins__BITNR) | \ - (R_NETWORK_STAT__rxer__##f2_##_VAL(R_NETWORK_STAT_, rxer_, v2) << R_NETWORK_STAT__rxer__BITNR) | \ - (R_NETWORK_STAT__underrun__##f3_##_VAL(R_NETWORK_STAT_, underrun_, v3) << R_NETWORK_STAT__underrun__BITNR) | \ - (R_NETWORK_STAT__exc_col__##f4_##_VAL(R_NETWORK_STAT_, exc_col_, v4) << R_NETWORK_STAT__exc_col__BITNR) | \ - (R_NETWORK_STAT__mdio__##f5_##_VAL(R_NETWORK_STAT_, mdio_, v5) << R_NETWORK_STAT__mdio__BITNR) \ -) - -#endif - -/* - * R_NETWORK_TR_CTRL - * - type: WO - * - addr: 0xb000009c - * - group: Network interface registers - */ - -#if USE_GROUP__Network_interface_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_NETWORK_TR_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_NETWORK_TR_CTRL. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_NETWORK_TR_CTRL. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_NETWORK_TR_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7) ( \ - *R_NETWORK_TR_CTRL__SADDR = ( \ - REG_INITIATED(R_NETWORK_TR_CTRL_) \ - REG_VAL__R_NETWORK_TR_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7) \ - ), \ - R_NETWORK_TR_CTRL__WRITE(R_NETWORK_TR_CTRL__ADDR, *R_NETWORK_TR_CTRL__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_NETWORK_TR_CTRL__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_NETWORK_TR_CTRL. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_NETWORK_TR_CTRL. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_NETWORK_TR_CTRL__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7) ( \ - *R_NETWORK_TR_CTRL__SADDR = ( \ - REG_INITIATED(R_NETWORK_TR_CTRL_) \ - REG_VAL__R_NETWORK_TR_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_NETWORK_TR_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_NETWORK_TR_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7) ( \ - (R_NETWORK_TR_CTRL__clr_error__##f1##__MASK & REG__##v1) | \ - (R_NETWORK_TR_CTRL__delay__##f2##__MASK & REG__##v2) | \ - (R_NETWORK_TR_CTRL__cancel__##f3##__MASK & REG__##v3) | \ - (R_NETWORK_TR_CTRL__cd__##f4##__MASK & REG__##v4) | \ - (R_NETWORK_TR_CTRL__retry__##f5##__MASK & REG__##v5) | \ - (R_NETWORK_TR_CTRL__pad__##f6##__MASK & REG__##v6) | \ - (R_NETWORK_TR_CTRL__crc__##f7##__MASK & REG__##v7) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_NETWORK_TR_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_NETWORK_TR_CTRL. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_NETWORK_TR_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7) ( \ - (R_NETWORK_TR_CTRL__clr_error__##f1##__VAL(R_NETWORK_TR_CTRL_, clr_error_, v1) << R_NETWORK_TR_CTRL__clr_error__BITNR) | \ - (R_NETWORK_TR_CTRL__delay__##f2##__VAL(R_NETWORK_TR_CTRL_, delay_, v2) << R_NETWORK_TR_CTRL__delay__BITNR) | \ - (R_NETWORK_TR_CTRL__cancel__##f3##__VAL(R_NETWORK_TR_CTRL_, cancel_, v3) << R_NETWORK_TR_CTRL__cancel__BITNR) | \ - (R_NETWORK_TR_CTRL__cd__##f4##__VAL(R_NETWORK_TR_CTRL_, cd_, v4) << R_NETWORK_TR_CTRL__cd__BITNR) | \ - (R_NETWORK_TR_CTRL__retry__##f5##__VAL(R_NETWORK_TR_CTRL_, retry_, v5) << R_NETWORK_TR_CTRL__retry__BITNR) | \ - (R_NETWORK_TR_CTRL__pad__##f6##__VAL(R_NETWORK_TR_CTRL_, pad_, v6) << R_NETWORK_TR_CTRL__pad__BITNR) | \ - (R_NETWORK_TR_CTRL__crc__##f7##__VAL(R_NETWORK_TR_CTRL_, crc_, v7) << R_NETWORK_TR_CTRL__crc__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_NETWORK_TR_CTRL_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_NETWORK_TR_CTRL. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_NETWORK_TR_CTRL_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7) ( \ - (R_NETWORK_TR_CTRL__clr_error__##f1_##_VAL(R_NETWORK_TR_CTRL_, clr_error_, v1) << R_NETWORK_TR_CTRL__clr_error__BITNR) | \ - (R_NETWORK_TR_CTRL__delay__##f2_##_VAL(R_NETWORK_TR_CTRL_, delay_, v2) << R_NETWORK_TR_CTRL__delay__BITNR) | \ - (R_NETWORK_TR_CTRL__cancel__##f3_##_VAL(R_NETWORK_TR_CTRL_, cancel_, v3) << R_NETWORK_TR_CTRL__cancel__BITNR) | \ - (R_NETWORK_TR_CTRL__cd__##f4_##_VAL(R_NETWORK_TR_CTRL_, cd_, v4) << R_NETWORK_TR_CTRL__cd__BITNR) | \ - (R_NETWORK_TR_CTRL__retry__##f5_##_VAL(R_NETWORK_TR_CTRL_, retry_, v5) << R_NETWORK_TR_CTRL__retry__BITNR) | \ - (R_NETWORK_TR_CTRL__pad__##f6_##_VAL(R_NETWORK_TR_CTRL_, pad_, v6) << R_NETWORK_TR_CTRL__pad__BITNR) | \ - (R_NETWORK_TR_CTRL__crc__##f7_##_VAL(R_NETWORK_TR_CTRL_, crc_, v7) << R_NETWORK_TR_CTRL__crc__BITNR) \ -) - -#endif - -/* - * R_PAR0_CONFIG - * - type: WO - * - addr: 0xb0000044 - * - group: Parallel printer port registers - */ - -#if USE_GROUP__Parallel_printer_port_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_PAR0_CONFIG -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_PAR0_CONFIG. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_PAR0_CONFIG. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_PAR0_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20) ( \ - *R_PAR0_CONFIG__SADDR = ( \ - REG_INITIATED(R_PAR0_CONFIG_) \ - REG_VAL__R_PAR0_CONFIG_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20) \ - ), \ - R_PAR0_CONFIG__WRITE(R_PAR0_CONFIG__ADDR, *R_PAR0_CONFIG__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_PAR0_CONFIG__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_PAR0_CONFIG. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_PAR0_CONFIG. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_PAR0_CONFIG__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20) ( \ - *R_PAR0_CONFIG__SADDR = ( \ - REG_INITIATED(R_PAR0_CONFIG_) \ - REG_VAL__R_PAR0_CONFIG_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_PAR0_CONFIG -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_PAR0_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20) ( \ - (R_PAR0_CONFIG__ioe__##f1##__MASK & REG__##v1) | \ - (R_PAR0_CONFIG__iseli__##f2##__MASK & REG__##v2) | \ - (R_PAR0_CONFIG__iautofd__##f3##__MASK & REG__##v3) | \ - (R_PAR0_CONFIG__istrb__##f4##__MASK & REG__##v4) | \ - (R_PAR0_CONFIG__iinit__##f5##__MASK & REG__##v5) | \ - (R_PAR0_CONFIG__iperr__##f6##__MASK & REG__##v6) | \ - (R_PAR0_CONFIG__iack__##f7##__MASK & REG__##v7) | \ - (R_PAR0_CONFIG__ibusy__##f8##__MASK & REG__##v8) | \ - (R_PAR0_CONFIG__ifault__##f9##__MASK & REG__##v9) | \ - (R_PAR0_CONFIG__isel__##f10##__MASK & REG__##v10) | \ - (R_PAR0_CONFIG__ext_mode__##f11##__MASK & REG__##v11) | \ - (R_PAR0_CONFIG__wide__##f12##__MASK & REG__##v12) | \ - (R_PAR0_CONFIG__dma__##f13##__MASK & REG__##v13) | \ - (R_PAR0_CONFIG__rle_in__##f14##__MASK & REG__##v14) | \ - (R_PAR0_CONFIG__rle_out__##f15##__MASK & REG__##v15) | \ - (R_PAR0_CONFIG__enable__##f16##__MASK & REG__##v16) | \ - (R_PAR0_CONFIG__force__##f17##__MASK & REG__##v17) | \ - (R_PAR0_CONFIG__ign_ack__##f18##__MASK & REG__##v18) | \ - (R_PAR0_CONFIG__oe_ack__##f19##__MASK & REG__##v19) | \ - (R_PAR0_CONFIG__mode__##f20##__MASK & REG__##v20) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_PAR0_CONFIG -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_PAR0_CONFIG. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_PAR0_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20) ( \ - (R_PAR0_CONFIG__ioe__##f1##__VAL(R_PAR0_CONFIG_, ioe_, v1) << R_PAR0_CONFIG__ioe__BITNR) | \ - (R_PAR0_CONFIG__iseli__##f2##__VAL(R_PAR0_CONFIG_, iseli_, v2) << R_PAR0_CONFIG__iseli__BITNR) | \ - (R_PAR0_CONFIG__iautofd__##f3##__VAL(R_PAR0_CONFIG_, iautofd_, v3) << R_PAR0_CONFIG__iautofd__BITNR) | \ - (R_PAR0_CONFIG__istrb__##f4##__VAL(R_PAR0_CONFIG_, istrb_, v4) << R_PAR0_CONFIG__istrb__BITNR) | \ - (R_PAR0_CONFIG__iinit__##f5##__VAL(R_PAR0_CONFIG_, iinit_, v5) << R_PAR0_CONFIG__iinit__BITNR) | \ - (R_PAR0_CONFIG__iperr__##f6##__VAL(R_PAR0_CONFIG_, iperr_, v6) << R_PAR0_CONFIG__iperr__BITNR) | \ - (R_PAR0_CONFIG__iack__##f7##__VAL(R_PAR0_CONFIG_, iack_, v7) << R_PAR0_CONFIG__iack__BITNR) | \ - (R_PAR0_CONFIG__ibusy__##f8##__VAL(R_PAR0_CONFIG_, ibusy_, v8) << R_PAR0_CONFIG__ibusy__BITNR) | \ - (R_PAR0_CONFIG__ifault__##f9##__VAL(R_PAR0_CONFIG_, ifault_, v9) << R_PAR0_CONFIG__ifault__BITNR) | \ - (R_PAR0_CONFIG__isel__##f10##__VAL(R_PAR0_CONFIG_, isel_, v10) << R_PAR0_CONFIG__isel__BITNR) | \ - (R_PAR0_CONFIG__ext_mode__##f11##__VAL(R_PAR0_CONFIG_, ext_mode_, v11) << R_PAR0_CONFIG__ext_mode__BITNR) | \ - (R_PAR0_CONFIG__wide__##f12##__VAL(R_PAR0_CONFIG_, wide_, v12) << R_PAR0_CONFIG__wide__BITNR) | \ - (R_PAR0_CONFIG__dma__##f13##__VAL(R_PAR0_CONFIG_, dma_, v13) << R_PAR0_CONFIG__dma__BITNR) | \ - (R_PAR0_CONFIG__rle_in__##f14##__VAL(R_PAR0_CONFIG_, rle_in_, v14) << R_PAR0_CONFIG__rle_in__BITNR) | \ - (R_PAR0_CONFIG__rle_out__##f15##__VAL(R_PAR0_CONFIG_, rle_out_, v15) << R_PAR0_CONFIG__rle_out__BITNR) | \ - (R_PAR0_CONFIG__enable__##f16##__VAL(R_PAR0_CONFIG_, enable_, v16) << R_PAR0_CONFIG__enable__BITNR) | \ - (R_PAR0_CONFIG__force__##f17##__VAL(R_PAR0_CONFIG_, force_, v17) << R_PAR0_CONFIG__force__BITNR) | \ - (R_PAR0_CONFIG__ign_ack__##f18##__VAL(R_PAR0_CONFIG_, ign_ack_, v18) << R_PAR0_CONFIG__ign_ack__BITNR) | \ - (R_PAR0_CONFIG__oe_ack__##f19##__VAL(R_PAR0_CONFIG_, oe_ack_, v19) << R_PAR0_CONFIG__oe_ack__BITNR) | \ - (R_PAR0_CONFIG__mode__##f20##__VAL(R_PAR0_CONFIG_, mode_, v20) << R_PAR0_CONFIG__mode__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_PAR0_CONFIG_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_PAR0_CONFIG. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_PAR0_CONFIG_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16,f17_,v17,f18_,v18,f19_,v19,f20_,v20) ( \ - (R_PAR0_CONFIG__ioe__##f1_##_VAL(R_PAR0_CONFIG_, ioe_, v1) << R_PAR0_CONFIG__ioe__BITNR) | \ - (R_PAR0_CONFIG__iseli__##f2_##_VAL(R_PAR0_CONFIG_, iseli_, v2) << R_PAR0_CONFIG__iseli__BITNR) | \ - (R_PAR0_CONFIG__iautofd__##f3_##_VAL(R_PAR0_CONFIG_, iautofd_, v3) << R_PAR0_CONFIG__iautofd__BITNR) | \ - (R_PAR0_CONFIG__istrb__##f4_##_VAL(R_PAR0_CONFIG_, istrb_, v4) << R_PAR0_CONFIG__istrb__BITNR) | \ - (R_PAR0_CONFIG__iinit__##f5_##_VAL(R_PAR0_CONFIG_, iinit_, v5) << R_PAR0_CONFIG__iinit__BITNR) | \ - (R_PAR0_CONFIG__iperr__##f6_##_VAL(R_PAR0_CONFIG_, iperr_, v6) << R_PAR0_CONFIG__iperr__BITNR) | \ - (R_PAR0_CONFIG__iack__##f7_##_VAL(R_PAR0_CONFIG_, iack_, v7) << R_PAR0_CONFIG__iack__BITNR) | \ - (R_PAR0_CONFIG__ibusy__##f8_##_VAL(R_PAR0_CONFIG_, ibusy_, v8) << R_PAR0_CONFIG__ibusy__BITNR) | \ - (R_PAR0_CONFIG__ifault__##f9_##_VAL(R_PAR0_CONFIG_, ifault_, v9) << R_PAR0_CONFIG__ifault__BITNR) | \ - (R_PAR0_CONFIG__isel__##f10_##_VAL(R_PAR0_CONFIG_, isel_, v10) << R_PAR0_CONFIG__isel__BITNR) | \ - (R_PAR0_CONFIG__ext_mode__##f11_##_VAL(R_PAR0_CONFIG_, ext_mode_, v11) << R_PAR0_CONFIG__ext_mode__BITNR) | \ - (R_PAR0_CONFIG__wide__##f12_##_VAL(R_PAR0_CONFIG_, wide_, v12) << R_PAR0_CONFIG__wide__BITNR) | \ - (R_PAR0_CONFIG__dma__##f13_##_VAL(R_PAR0_CONFIG_, dma_, v13) << R_PAR0_CONFIG__dma__BITNR) | \ - (R_PAR0_CONFIG__rle_in__##f14_##_VAL(R_PAR0_CONFIG_, rle_in_, v14) << R_PAR0_CONFIG__rle_in__BITNR) | \ - (R_PAR0_CONFIG__rle_out__##f15_##_VAL(R_PAR0_CONFIG_, rle_out_, v15) << R_PAR0_CONFIG__rle_out__BITNR) | \ - (R_PAR0_CONFIG__enable__##f16_##_VAL(R_PAR0_CONFIG_, enable_, v16) << R_PAR0_CONFIG__enable__BITNR) | \ - (R_PAR0_CONFIG__force__##f17_##_VAL(R_PAR0_CONFIG_, force_, v17) << R_PAR0_CONFIG__force__BITNR) | \ - (R_PAR0_CONFIG__ign_ack__##f18_##_VAL(R_PAR0_CONFIG_, ign_ack_, v18) << R_PAR0_CONFIG__ign_ack__BITNR) | \ - (R_PAR0_CONFIG__oe_ack__##f19_##_VAL(R_PAR0_CONFIG_, oe_ack_, v19) << R_PAR0_CONFIG__oe_ack__BITNR) | \ - (R_PAR0_CONFIG__mode__##f20_##_VAL(R_PAR0_CONFIG_, mode_, v20) << R_PAR0_CONFIG__mode__BITNR) \ -) - -#endif - -/* - * R_PAR0_CTRL - * - type: WO - * - addr: 0xb0000042 - * - group: Parallel printer port registers - */ - -#if USE_GROUP__Parallel_printer_port_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_PAR0_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_PAR0_CTRL. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_PAR0_CTRL. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_PAR0_CTRL(f1,v1) ( \ - *R_PAR0_CTRL__SADDR = ( \ - REG_INITIATED(R_PAR0_CTRL_) \ - REG_VAL__R_PAR0_CTRL_(f1##_,v1) \ - ), \ - R_PAR0_CTRL__WRITE(R_PAR0_CTRL__ADDR, *R_PAR0_CTRL__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_PAR0_CTRL__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_PAR0_CTRL. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_PAR0_CTRL. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_PAR0_CTRL__SHADOW(f1,v1) ( \ - *R_PAR0_CTRL__SADDR = ( \ - REG_INITIATED(R_PAR0_CTRL_) \ - REG_VAL__R_PAR0_CTRL_(f1##_,v1) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_PAR0_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_PAR0_CTRL(f1,v1) ( \ - (R_PAR0_CTRL__ctrl__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_PAR0_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_PAR0_CTRL. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_PAR0_CTRL(f1,v1) ( \ - (R_PAR0_CTRL__ctrl__##f1##__VAL(R_PAR0_CTRL_, ctrl_, v1) << R_PAR0_CTRL__ctrl__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_PAR0_CTRL_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_PAR0_CTRL. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_PAR0_CTRL_(f1_,v1) ( \ - (R_PAR0_CTRL__ctrl__##f1_##_VAL(R_PAR0_CTRL_, ctrl_, v1) << R_PAR0_CTRL__ctrl__BITNR) \ -) - -#endif - -/* - * R_PAR0_CTRL_DATA - * - type: WO - * - addr: 0xb0000040 - * - group: Parallel printer port registers - */ - -#if USE_GROUP__Parallel_printer_port_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_PAR0_CTRL_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_PAR0_CTRL_DATA. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_PAR0_CTRL_DATA. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_PAR0_CTRL_DATA(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - *R_PAR0_CTRL_DATA__SADDR = ( \ - REG_INITIATED(R_PAR0_CTRL_DATA_) \ - REG_VAL__R_PAR0_CTRL_DATA_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \ - ), \ - R_PAR0_CTRL_DATA__WRITE(R_PAR0_CTRL_DATA__ADDR, *R_PAR0_CTRL_DATA__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_PAR0_CTRL_DATA__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_PAR0_CTRL_DATA. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_PAR0_CTRL_DATA. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_PAR0_CTRL_DATA__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - *R_PAR0_CTRL_DATA__SADDR = ( \ - REG_INITIATED(R_PAR0_CTRL_DATA_) \ - REG_VAL__R_PAR0_CTRL_DATA_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_PAR0_CTRL_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_PAR0_CTRL_DATA(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - (R_PAR0_CTRL_DATA__peri_int__##f1##__MASK & REG__##v1) | \ - (R_PAR0_CTRL_DATA__oe__##f2##__MASK & REG__##v2) | \ - (R_PAR0_CTRL_DATA__seli__##f3##__MASK & REG__##v3) | \ - (R_PAR0_CTRL_DATA__autofd__##f4##__MASK & REG__##v4) | \ - (R_PAR0_CTRL_DATA__strb__##f5##__MASK & REG__##v5) | \ - (R_PAR0_CTRL_DATA__init__##f6##__MASK & REG__##v6) | \ - (R_PAR0_CTRL_DATA__ecp_cmd__##f7##__MASK & REG__##v7) | \ - (R_PAR0_CTRL_DATA__data__##f8##__MASK & REG__##v8) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_PAR0_CTRL_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_PAR0_CTRL_DATA. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_PAR0_CTRL_DATA(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - (R_PAR0_CTRL_DATA__peri_int__##f1##__VAL(R_PAR0_CTRL_DATA_, peri_int_, v1) << R_PAR0_CTRL_DATA__peri_int__BITNR) | \ - (R_PAR0_CTRL_DATA__oe__##f2##__VAL(R_PAR0_CTRL_DATA_, oe_, v2) << R_PAR0_CTRL_DATA__oe__BITNR) | \ - (R_PAR0_CTRL_DATA__seli__##f3##__VAL(R_PAR0_CTRL_DATA_, seli_, v3) << R_PAR0_CTRL_DATA__seli__BITNR) | \ - (R_PAR0_CTRL_DATA__autofd__##f4##__VAL(R_PAR0_CTRL_DATA_, autofd_, v4) << R_PAR0_CTRL_DATA__autofd__BITNR) | \ - (R_PAR0_CTRL_DATA__strb__##f5##__VAL(R_PAR0_CTRL_DATA_, strb_, v5) << R_PAR0_CTRL_DATA__strb__BITNR) | \ - (R_PAR0_CTRL_DATA__init__##f6##__VAL(R_PAR0_CTRL_DATA_, init_, v6) << R_PAR0_CTRL_DATA__init__BITNR) | \ - (R_PAR0_CTRL_DATA__ecp_cmd__##f7##__VAL(R_PAR0_CTRL_DATA_, ecp_cmd_, v7) << R_PAR0_CTRL_DATA__ecp_cmd__BITNR) | \ - (R_PAR0_CTRL_DATA__data__##f8##__VAL(R_PAR0_CTRL_DATA_, data_, v8) << R_PAR0_CTRL_DATA__data__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_PAR0_CTRL_DATA_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_PAR0_CTRL_DATA. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_PAR0_CTRL_DATA_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8) ( \ - (R_PAR0_CTRL_DATA__peri_int__##f1_##_VAL(R_PAR0_CTRL_DATA_, peri_int_, v1) << R_PAR0_CTRL_DATA__peri_int__BITNR) | \ - (R_PAR0_CTRL_DATA__oe__##f2_##_VAL(R_PAR0_CTRL_DATA_, oe_, v2) << R_PAR0_CTRL_DATA__oe__BITNR) | \ - (R_PAR0_CTRL_DATA__seli__##f3_##_VAL(R_PAR0_CTRL_DATA_, seli_, v3) << R_PAR0_CTRL_DATA__seli__BITNR) | \ - (R_PAR0_CTRL_DATA__autofd__##f4_##_VAL(R_PAR0_CTRL_DATA_, autofd_, v4) << R_PAR0_CTRL_DATA__autofd__BITNR) | \ - (R_PAR0_CTRL_DATA__strb__##f5_##_VAL(R_PAR0_CTRL_DATA_, strb_, v5) << R_PAR0_CTRL_DATA__strb__BITNR) | \ - (R_PAR0_CTRL_DATA__init__##f6_##_VAL(R_PAR0_CTRL_DATA_, init_, v6) << R_PAR0_CTRL_DATA__init__BITNR) | \ - (R_PAR0_CTRL_DATA__ecp_cmd__##f7_##_VAL(R_PAR0_CTRL_DATA_, ecp_cmd_, v7) << R_PAR0_CTRL_DATA__ecp_cmd__BITNR) | \ - (R_PAR0_CTRL_DATA__data__##f8_##_VAL(R_PAR0_CTRL_DATA_, data_, v8) << R_PAR0_CTRL_DATA__data__BITNR) \ -) - -#endif - -/* - * R_PAR0_DELAY - * - type: WO - * - addr: 0xb0000048 - * - group: Parallel printer port registers - */ - -#if USE_GROUP__Parallel_printer_port_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_PAR0_DELAY -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_PAR0_DELAY. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_PAR0_DELAY. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_PAR0_DELAY(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \ - *R_PAR0_DELAY__SADDR = ( \ - REG_INITIATED(R_PAR0_DELAY_) \ - REG_VAL__R_PAR0_DELAY_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6) \ - ), \ - R_PAR0_DELAY__WRITE(R_PAR0_DELAY__ADDR, *R_PAR0_DELAY__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_PAR0_DELAY__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_PAR0_DELAY. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_PAR0_DELAY. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_PAR0_DELAY__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \ - *R_PAR0_DELAY__SADDR = ( \ - REG_INITIATED(R_PAR0_DELAY_) \ - REG_VAL__R_PAR0_DELAY_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_PAR0_DELAY -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_PAR0_DELAY(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \ - (R_PAR0_DELAY__fine_hold__##f1##__MASK & REG__##v1) | \ - (R_PAR0_DELAY__hold__##f2##__MASK & REG__##v2) | \ - (R_PAR0_DELAY__fine_strb__##f3##__MASK & REG__##v3) | \ - (R_PAR0_DELAY__strobe__##f4##__MASK & REG__##v4) | \ - (R_PAR0_DELAY__fine_setup__##f5##__MASK & REG__##v5) | \ - (R_PAR0_DELAY__setup__##f6##__MASK & REG__##v6) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_PAR0_DELAY -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_PAR0_DELAY. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_PAR0_DELAY(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \ - (R_PAR0_DELAY__fine_hold__##f1##__VAL(R_PAR0_DELAY_, fine_hold_, v1) << R_PAR0_DELAY__fine_hold__BITNR) | \ - (R_PAR0_DELAY__hold__##f2##__VAL(R_PAR0_DELAY_, hold_, v2) << R_PAR0_DELAY__hold__BITNR) | \ - (R_PAR0_DELAY__fine_strb__##f3##__VAL(R_PAR0_DELAY_, fine_strb_, v3) << R_PAR0_DELAY__fine_strb__BITNR) | \ - (R_PAR0_DELAY__strobe__##f4##__VAL(R_PAR0_DELAY_, strobe_, v4) << R_PAR0_DELAY__strobe__BITNR) | \ - (R_PAR0_DELAY__fine_setup__##f5##__VAL(R_PAR0_DELAY_, fine_setup_, v5) << R_PAR0_DELAY__fine_setup__BITNR) | \ - (R_PAR0_DELAY__setup__##f6##__VAL(R_PAR0_DELAY_, setup_, v6) << R_PAR0_DELAY__setup__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_PAR0_DELAY_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_PAR0_DELAY. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_PAR0_DELAY_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6) ( \ - (R_PAR0_DELAY__fine_hold__##f1_##_VAL(R_PAR0_DELAY_, fine_hold_, v1) << R_PAR0_DELAY__fine_hold__BITNR) | \ - (R_PAR0_DELAY__hold__##f2_##_VAL(R_PAR0_DELAY_, hold_, v2) << R_PAR0_DELAY__hold__BITNR) | \ - (R_PAR0_DELAY__fine_strb__##f3_##_VAL(R_PAR0_DELAY_, fine_strb_, v3) << R_PAR0_DELAY__fine_strb__BITNR) | \ - (R_PAR0_DELAY__strobe__##f4_##_VAL(R_PAR0_DELAY_, strobe_, v4) << R_PAR0_DELAY__strobe__BITNR) | \ - (R_PAR0_DELAY__fine_setup__##f5_##_VAL(R_PAR0_DELAY_, fine_setup_, v5) << R_PAR0_DELAY__fine_setup__BITNR) | \ - (R_PAR0_DELAY__setup__##f6_##_VAL(R_PAR0_DELAY_, setup_, v6) << R_PAR0_DELAY__setup__BITNR) \ -) - -#endif - -/* - * R_PAR0_STATUS - * - type: RO - * - addr: 0xb0000042 - * - group: Parallel printer port registers - */ - -#if USE_GROUP__Parallel_printer_port_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_PAR0_STATUS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_PAR0_STATUS(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \ - (R_PAR0_STATUS__mode__##f1##__MASK & REG__##v1) | \ - (R_PAR0_STATUS__perr__##f2##__MASK & REG__##v2) | \ - (R_PAR0_STATUS__ack__##f3##__MASK & REG__##v3) | \ - (R_PAR0_STATUS__busy__##f4##__MASK & REG__##v4) | \ - (R_PAR0_STATUS__fault__##f5##__MASK & REG__##v5) | \ - (R_PAR0_STATUS__sel__##f6##__MASK & REG__##v6) | \ - (R_PAR0_STATUS__ext_mode__##f7##__MASK & REG__##v7) | \ - (R_PAR0_STATUS__ecp_16__##f8##__MASK & REG__##v8) | \ - (R_PAR0_STATUS__tr_rdy__##f9##__MASK & REG__##v9) | \ - (R_PAR0_STATUS__dav__##f10##__MASK & REG__##v10) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_PAR0_STATUS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_PAR0_STATUS. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_PAR0_STATUS(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \ - (R_PAR0_STATUS__mode__##f1##__VAL(R_PAR0_STATUS_, mode_, v1) << R_PAR0_STATUS__mode__BITNR) | \ - (R_PAR0_STATUS__perr__##f2##__VAL(R_PAR0_STATUS_, perr_, v2) << R_PAR0_STATUS__perr__BITNR) | \ - (R_PAR0_STATUS__ack__##f3##__VAL(R_PAR0_STATUS_, ack_, v3) << R_PAR0_STATUS__ack__BITNR) | \ - (R_PAR0_STATUS__busy__##f4##__VAL(R_PAR0_STATUS_, busy_, v4) << R_PAR0_STATUS__busy__BITNR) | \ - (R_PAR0_STATUS__fault__##f5##__VAL(R_PAR0_STATUS_, fault_, v5) << R_PAR0_STATUS__fault__BITNR) | \ - (R_PAR0_STATUS__sel__##f6##__VAL(R_PAR0_STATUS_, sel_, v6) << R_PAR0_STATUS__sel__BITNR) | \ - (R_PAR0_STATUS__ext_mode__##f7##__VAL(R_PAR0_STATUS_, ext_mode_, v7) << R_PAR0_STATUS__ext_mode__BITNR) | \ - (R_PAR0_STATUS__ecp_16__##f8##__VAL(R_PAR0_STATUS_, ecp_16_, v8) << R_PAR0_STATUS__ecp_16__BITNR) | \ - (R_PAR0_STATUS__tr_rdy__##f9##__VAL(R_PAR0_STATUS_, tr_rdy_, v9) << R_PAR0_STATUS__tr_rdy__BITNR) | \ - (R_PAR0_STATUS__dav__##f10##__VAL(R_PAR0_STATUS_, dav_, v10) << R_PAR0_STATUS__dav__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_PAR0_STATUS_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_PAR0_STATUS. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_PAR0_STATUS_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10) ( \ - (R_PAR0_STATUS__mode__##f1_##_VAL(R_PAR0_STATUS_, mode_, v1) << R_PAR0_STATUS__mode__BITNR) | \ - (R_PAR0_STATUS__perr__##f2_##_VAL(R_PAR0_STATUS_, perr_, v2) << R_PAR0_STATUS__perr__BITNR) | \ - (R_PAR0_STATUS__ack__##f3_##_VAL(R_PAR0_STATUS_, ack_, v3) << R_PAR0_STATUS__ack__BITNR) | \ - (R_PAR0_STATUS__busy__##f4_##_VAL(R_PAR0_STATUS_, busy_, v4) << R_PAR0_STATUS__busy__BITNR) | \ - (R_PAR0_STATUS__fault__##f5_##_VAL(R_PAR0_STATUS_, fault_, v5) << R_PAR0_STATUS__fault__BITNR) | \ - (R_PAR0_STATUS__sel__##f6_##_VAL(R_PAR0_STATUS_, sel_, v6) << R_PAR0_STATUS__sel__BITNR) | \ - (R_PAR0_STATUS__ext_mode__##f7_##_VAL(R_PAR0_STATUS_, ext_mode_, v7) << R_PAR0_STATUS__ext_mode__BITNR) | \ - (R_PAR0_STATUS__ecp_16__##f8_##_VAL(R_PAR0_STATUS_, ecp_16_, v8) << R_PAR0_STATUS__ecp_16__BITNR) | \ - (R_PAR0_STATUS__tr_rdy__##f9_##_VAL(R_PAR0_STATUS_, tr_rdy_, v9) << R_PAR0_STATUS__tr_rdy__BITNR) | \ - (R_PAR0_STATUS__dav__##f10_##_VAL(R_PAR0_STATUS_, dav_, v10) << R_PAR0_STATUS__dav__BITNR) \ -) - -#endif - -/* - * R_PAR0_STATUS_DATA - * - type: RO - * - addr: 0xb0000040 - * - group: Parallel printer port registers - */ - -#if USE_GROUP__Parallel_printer_port_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_PAR0_STATUS_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_PAR0_STATUS_DATA(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12) ( \ - (R_PAR0_STATUS_DATA__mode__##f1##__MASK & REG__##v1) | \ - (R_PAR0_STATUS_DATA__perr__##f2##__MASK & REG__##v2) | \ - (R_PAR0_STATUS_DATA__ack__##f3##__MASK & REG__##v3) | \ - (R_PAR0_STATUS_DATA__busy__##f4##__MASK & REG__##v4) | \ - (R_PAR0_STATUS_DATA__fault__##f5##__MASK & REG__##v5) | \ - (R_PAR0_STATUS_DATA__sel__##f6##__MASK & REG__##v6) | \ - (R_PAR0_STATUS_DATA__ext_mode__##f7##__MASK & REG__##v7) | \ - (R_PAR0_STATUS_DATA__ecp_16__##f8##__MASK & REG__##v8) | \ - (R_PAR0_STATUS_DATA__tr_rdy__##f9##__MASK & REG__##v9) | \ - (R_PAR0_STATUS_DATA__dav__##f10##__MASK & REG__##v10) | \ - (R_PAR0_STATUS_DATA__ecp_cmd__##f11##__MASK & REG__##v11) | \ - (R_PAR0_STATUS_DATA__data__##f12##__MASK & REG__##v12) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_PAR0_STATUS_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_PAR0_STATUS_DATA. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_PAR0_STATUS_DATA(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12) ( \ - (R_PAR0_STATUS_DATA__mode__##f1##__VAL(R_PAR0_STATUS_DATA_, mode_, v1) << R_PAR0_STATUS_DATA__mode__BITNR) | \ - (R_PAR0_STATUS_DATA__perr__##f2##__VAL(R_PAR0_STATUS_DATA_, perr_, v2) << R_PAR0_STATUS_DATA__perr__BITNR) | \ - (R_PAR0_STATUS_DATA__ack__##f3##__VAL(R_PAR0_STATUS_DATA_, ack_, v3) << R_PAR0_STATUS_DATA__ack__BITNR) | \ - (R_PAR0_STATUS_DATA__busy__##f4##__VAL(R_PAR0_STATUS_DATA_, busy_, v4) << R_PAR0_STATUS_DATA__busy__BITNR) | \ - (R_PAR0_STATUS_DATA__fault__##f5##__VAL(R_PAR0_STATUS_DATA_, fault_, v5) << R_PAR0_STATUS_DATA__fault__BITNR) | \ - (R_PAR0_STATUS_DATA__sel__##f6##__VAL(R_PAR0_STATUS_DATA_, sel_, v6) << R_PAR0_STATUS_DATA__sel__BITNR) | \ - (R_PAR0_STATUS_DATA__ext_mode__##f7##__VAL(R_PAR0_STATUS_DATA_, ext_mode_, v7) << R_PAR0_STATUS_DATA__ext_mode__BITNR) | \ - (R_PAR0_STATUS_DATA__ecp_16__##f8##__VAL(R_PAR0_STATUS_DATA_, ecp_16_, v8) << R_PAR0_STATUS_DATA__ecp_16__BITNR) | \ - (R_PAR0_STATUS_DATA__tr_rdy__##f9##__VAL(R_PAR0_STATUS_DATA_, tr_rdy_, v9) << R_PAR0_STATUS_DATA__tr_rdy__BITNR) | \ - (R_PAR0_STATUS_DATA__dav__##f10##__VAL(R_PAR0_STATUS_DATA_, dav_, v10) << R_PAR0_STATUS_DATA__dav__BITNR) | \ - (R_PAR0_STATUS_DATA__ecp_cmd__##f11##__VAL(R_PAR0_STATUS_DATA_, ecp_cmd_, v11) << R_PAR0_STATUS_DATA__ecp_cmd__BITNR) | \ - (R_PAR0_STATUS_DATA__data__##f12##__VAL(R_PAR0_STATUS_DATA_, data_, v12) << R_PAR0_STATUS_DATA__data__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_PAR0_STATUS_DATA_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_PAR0_STATUS_DATA. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_PAR0_STATUS_DATA_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12) ( \ - (R_PAR0_STATUS_DATA__mode__##f1_##_VAL(R_PAR0_STATUS_DATA_, mode_, v1) << R_PAR0_STATUS_DATA__mode__BITNR) | \ - (R_PAR0_STATUS_DATA__perr__##f2_##_VAL(R_PAR0_STATUS_DATA_, perr_, v2) << R_PAR0_STATUS_DATA__perr__BITNR) | \ - (R_PAR0_STATUS_DATA__ack__##f3_##_VAL(R_PAR0_STATUS_DATA_, ack_, v3) << R_PAR0_STATUS_DATA__ack__BITNR) | \ - (R_PAR0_STATUS_DATA__busy__##f4_##_VAL(R_PAR0_STATUS_DATA_, busy_, v4) << R_PAR0_STATUS_DATA__busy__BITNR) | \ - (R_PAR0_STATUS_DATA__fault__##f5_##_VAL(R_PAR0_STATUS_DATA_, fault_, v5) << R_PAR0_STATUS_DATA__fault__BITNR) | \ - (R_PAR0_STATUS_DATA__sel__##f6_##_VAL(R_PAR0_STATUS_DATA_, sel_, v6) << R_PAR0_STATUS_DATA__sel__BITNR) | \ - (R_PAR0_STATUS_DATA__ext_mode__##f7_##_VAL(R_PAR0_STATUS_DATA_, ext_mode_, v7) << R_PAR0_STATUS_DATA__ext_mode__BITNR) | \ - (R_PAR0_STATUS_DATA__ecp_16__##f8_##_VAL(R_PAR0_STATUS_DATA_, ecp_16_, v8) << R_PAR0_STATUS_DATA__ecp_16__BITNR) | \ - (R_PAR0_STATUS_DATA__tr_rdy__##f9_##_VAL(R_PAR0_STATUS_DATA_, tr_rdy_, v9) << R_PAR0_STATUS_DATA__tr_rdy__BITNR) | \ - (R_PAR0_STATUS_DATA__dav__##f10_##_VAL(R_PAR0_STATUS_DATA_, dav_, v10) << R_PAR0_STATUS_DATA__dav__BITNR) | \ - (R_PAR0_STATUS_DATA__ecp_cmd__##f11_##_VAL(R_PAR0_STATUS_DATA_, ecp_cmd_, v11) << R_PAR0_STATUS_DATA__ecp_cmd__BITNR) | \ - (R_PAR0_STATUS_DATA__data__##f12_##_VAL(R_PAR0_STATUS_DATA_, data_, v12) << R_PAR0_STATUS_DATA__data__BITNR) \ -) - -#endif - -/* - * R_PAR1_CONFIG - * - type: WO - * - addr: 0xb0000054 - * - group: Parallel printer port registers - */ - -#if USE_GROUP__Parallel_printer_port_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_PAR1_CONFIG -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_PAR1_CONFIG. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_PAR1_CONFIG. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_PAR1_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19) ( \ - *R_PAR1_CONFIG__SADDR = ( \ - REG_INITIATED(R_PAR1_CONFIG_) \ - REG_VAL__R_PAR1_CONFIG_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19) \ - ), \ - R_PAR1_CONFIG__WRITE(R_PAR1_CONFIG__ADDR, *R_PAR1_CONFIG__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_PAR1_CONFIG__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_PAR1_CONFIG. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_PAR1_CONFIG. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_PAR1_CONFIG__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19) ( \ - *R_PAR1_CONFIG__SADDR = ( \ - REG_INITIATED(R_PAR1_CONFIG_) \ - REG_VAL__R_PAR1_CONFIG_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_PAR1_CONFIG -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_PAR1_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19) ( \ - (R_PAR1_CONFIG__ioe__##f1##__MASK & REG__##v1) | \ - (R_PAR1_CONFIG__iseli__##f2##__MASK & REG__##v2) | \ - (R_PAR1_CONFIG__iautofd__##f3##__MASK & REG__##v3) | \ - (R_PAR1_CONFIG__istrb__##f4##__MASK & REG__##v4) | \ - (R_PAR1_CONFIG__iinit__##f5##__MASK & REG__##v5) | \ - (R_PAR1_CONFIG__iperr__##f6##__MASK & REG__##v6) | \ - (R_PAR1_CONFIG__iack__##f7##__MASK & REG__##v7) | \ - (R_PAR1_CONFIG__ibusy__##f8##__MASK & REG__##v8) | \ - (R_PAR1_CONFIG__ifault__##f9##__MASK & REG__##v9) | \ - (R_PAR1_CONFIG__isel__##f10##__MASK & REG__##v10) | \ - (R_PAR1_CONFIG__ext_mode__##f11##__MASK & REG__##v11) | \ - (R_PAR1_CONFIG__dma__##f12##__MASK & REG__##v12) | \ - (R_PAR1_CONFIG__rle_in__##f13##__MASK & REG__##v13) | \ - (R_PAR1_CONFIG__rle_out__##f14##__MASK & REG__##v14) | \ - (R_PAR1_CONFIG__enable__##f15##__MASK & REG__##v15) | \ - (R_PAR1_CONFIG__force__##f16##__MASK & REG__##v16) | \ - (R_PAR1_CONFIG__ign_ack__##f17##__MASK & REG__##v17) | \ - (R_PAR1_CONFIG__oe_ack__##f18##__MASK & REG__##v18) | \ - (R_PAR1_CONFIG__mode__##f19##__MASK & REG__##v19) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_PAR1_CONFIG -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_PAR1_CONFIG. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_PAR1_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19) ( \ - (R_PAR1_CONFIG__ioe__##f1##__VAL(R_PAR1_CONFIG_, ioe_, v1) << R_PAR1_CONFIG__ioe__BITNR) | \ - (R_PAR1_CONFIG__iseli__##f2##__VAL(R_PAR1_CONFIG_, iseli_, v2) << R_PAR1_CONFIG__iseli__BITNR) | \ - (R_PAR1_CONFIG__iautofd__##f3##__VAL(R_PAR1_CONFIG_, iautofd_, v3) << R_PAR1_CONFIG__iautofd__BITNR) | \ - (R_PAR1_CONFIG__istrb__##f4##__VAL(R_PAR1_CONFIG_, istrb_, v4) << R_PAR1_CONFIG__istrb__BITNR) | \ - (R_PAR1_CONFIG__iinit__##f5##__VAL(R_PAR1_CONFIG_, iinit_, v5) << R_PAR1_CONFIG__iinit__BITNR) | \ - (R_PAR1_CONFIG__iperr__##f6##__VAL(R_PAR1_CONFIG_, iperr_, v6) << R_PAR1_CONFIG__iperr__BITNR) | \ - (R_PAR1_CONFIG__iack__##f7##__VAL(R_PAR1_CONFIG_, iack_, v7) << R_PAR1_CONFIG__iack__BITNR) | \ - (R_PAR1_CONFIG__ibusy__##f8##__VAL(R_PAR1_CONFIG_, ibusy_, v8) << R_PAR1_CONFIG__ibusy__BITNR) | \ - (R_PAR1_CONFIG__ifault__##f9##__VAL(R_PAR1_CONFIG_, ifault_, v9) << R_PAR1_CONFIG__ifault__BITNR) | \ - (R_PAR1_CONFIG__isel__##f10##__VAL(R_PAR1_CONFIG_, isel_, v10) << R_PAR1_CONFIG__isel__BITNR) | \ - (R_PAR1_CONFIG__ext_mode__##f11##__VAL(R_PAR1_CONFIG_, ext_mode_, v11) << R_PAR1_CONFIG__ext_mode__BITNR) | \ - (R_PAR1_CONFIG__dma__##f12##__VAL(R_PAR1_CONFIG_, dma_, v12) << R_PAR1_CONFIG__dma__BITNR) | \ - (R_PAR1_CONFIG__rle_in__##f13##__VAL(R_PAR1_CONFIG_, rle_in_, v13) << R_PAR1_CONFIG__rle_in__BITNR) | \ - (R_PAR1_CONFIG__rle_out__##f14##__VAL(R_PAR1_CONFIG_, rle_out_, v14) << R_PAR1_CONFIG__rle_out__BITNR) | \ - (R_PAR1_CONFIG__enable__##f15##__VAL(R_PAR1_CONFIG_, enable_, v15) << R_PAR1_CONFIG__enable__BITNR) | \ - (R_PAR1_CONFIG__force__##f16##__VAL(R_PAR1_CONFIG_, force_, v16) << R_PAR1_CONFIG__force__BITNR) | \ - (R_PAR1_CONFIG__ign_ack__##f17##__VAL(R_PAR1_CONFIG_, ign_ack_, v17) << R_PAR1_CONFIG__ign_ack__BITNR) | \ - (R_PAR1_CONFIG__oe_ack__##f18##__VAL(R_PAR1_CONFIG_, oe_ack_, v18) << R_PAR1_CONFIG__oe_ack__BITNR) | \ - (R_PAR1_CONFIG__mode__##f19##__VAL(R_PAR1_CONFIG_, mode_, v19) << R_PAR1_CONFIG__mode__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_PAR1_CONFIG_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_PAR1_CONFIG. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_PAR1_CONFIG_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16,f17_,v17,f18_,v18,f19_,v19) ( \ - (R_PAR1_CONFIG__ioe__##f1_##_VAL(R_PAR1_CONFIG_, ioe_, v1) << R_PAR1_CONFIG__ioe__BITNR) | \ - (R_PAR1_CONFIG__iseli__##f2_##_VAL(R_PAR1_CONFIG_, iseli_, v2) << R_PAR1_CONFIG__iseli__BITNR) | \ - (R_PAR1_CONFIG__iautofd__##f3_##_VAL(R_PAR1_CONFIG_, iautofd_, v3) << R_PAR1_CONFIG__iautofd__BITNR) | \ - (R_PAR1_CONFIG__istrb__##f4_##_VAL(R_PAR1_CONFIG_, istrb_, v4) << R_PAR1_CONFIG__istrb__BITNR) | \ - (R_PAR1_CONFIG__iinit__##f5_##_VAL(R_PAR1_CONFIG_, iinit_, v5) << R_PAR1_CONFIG__iinit__BITNR) | \ - (R_PAR1_CONFIG__iperr__##f6_##_VAL(R_PAR1_CONFIG_, iperr_, v6) << R_PAR1_CONFIG__iperr__BITNR) | \ - (R_PAR1_CONFIG__iack__##f7_##_VAL(R_PAR1_CONFIG_, iack_, v7) << R_PAR1_CONFIG__iack__BITNR) | \ - (R_PAR1_CONFIG__ibusy__##f8_##_VAL(R_PAR1_CONFIG_, ibusy_, v8) << R_PAR1_CONFIG__ibusy__BITNR) | \ - (R_PAR1_CONFIG__ifault__##f9_##_VAL(R_PAR1_CONFIG_, ifault_, v9) << R_PAR1_CONFIG__ifault__BITNR) | \ - (R_PAR1_CONFIG__isel__##f10_##_VAL(R_PAR1_CONFIG_, isel_, v10) << R_PAR1_CONFIG__isel__BITNR) | \ - (R_PAR1_CONFIG__ext_mode__##f11_##_VAL(R_PAR1_CONFIG_, ext_mode_, v11) << R_PAR1_CONFIG__ext_mode__BITNR) | \ - (R_PAR1_CONFIG__dma__##f12_##_VAL(R_PAR1_CONFIG_, dma_, v12) << R_PAR1_CONFIG__dma__BITNR) | \ - (R_PAR1_CONFIG__rle_in__##f13_##_VAL(R_PAR1_CONFIG_, rle_in_, v13) << R_PAR1_CONFIG__rle_in__BITNR) | \ - (R_PAR1_CONFIG__rle_out__##f14_##_VAL(R_PAR1_CONFIG_, rle_out_, v14) << R_PAR1_CONFIG__rle_out__BITNR) | \ - (R_PAR1_CONFIG__enable__##f15_##_VAL(R_PAR1_CONFIG_, enable_, v15) << R_PAR1_CONFIG__enable__BITNR) | \ - (R_PAR1_CONFIG__force__##f16_##_VAL(R_PAR1_CONFIG_, force_, v16) << R_PAR1_CONFIG__force__BITNR) | \ - (R_PAR1_CONFIG__ign_ack__##f17_##_VAL(R_PAR1_CONFIG_, ign_ack_, v17) << R_PAR1_CONFIG__ign_ack__BITNR) | \ - (R_PAR1_CONFIG__oe_ack__##f18_##_VAL(R_PAR1_CONFIG_, oe_ack_, v18) << R_PAR1_CONFIG__oe_ack__BITNR) | \ - (R_PAR1_CONFIG__mode__##f19_##_VAL(R_PAR1_CONFIG_, mode_, v19) << R_PAR1_CONFIG__mode__BITNR) \ -) - -#endif - -/* - * R_PAR1_CTRL - * - type: WO - * - addr: 0xb0000052 - * - group: Parallel printer port registers - */ - -#if USE_GROUP__Parallel_printer_port_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_PAR1_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_PAR1_CTRL. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_PAR1_CTRL. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_PAR1_CTRL(f1,v1) ( \ - *R_PAR1_CTRL__SADDR = ( \ - REG_INITIATED(R_PAR1_CTRL_) \ - REG_VAL__R_PAR1_CTRL_(f1##_,v1) \ - ), \ - R_PAR1_CTRL__WRITE(R_PAR1_CTRL__ADDR, *R_PAR1_CTRL__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_PAR1_CTRL__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_PAR1_CTRL. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_PAR1_CTRL. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_PAR1_CTRL__SHADOW(f1,v1) ( \ - *R_PAR1_CTRL__SADDR = ( \ - REG_INITIATED(R_PAR1_CTRL_) \ - REG_VAL__R_PAR1_CTRL_(f1##_,v1) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_PAR1_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_PAR1_CTRL(f1,v1) ( \ - (R_PAR1_CTRL__ctrl__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_PAR1_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_PAR1_CTRL. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_PAR1_CTRL(f1,v1) ( \ - (R_PAR1_CTRL__ctrl__##f1##__VAL(R_PAR1_CTRL_, ctrl_, v1) << R_PAR1_CTRL__ctrl__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_PAR1_CTRL_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_PAR1_CTRL. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_PAR1_CTRL_(f1_,v1) ( \ - (R_PAR1_CTRL__ctrl__##f1_##_VAL(R_PAR1_CTRL_, ctrl_, v1) << R_PAR1_CTRL__ctrl__BITNR) \ -) - -#endif - -/* - * R_PAR1_CTRL_DATA - * - type: WO - * - addr: 0xb0000050 - * - group: Parallel printer port registers - */ - -#if USE_GROUP__Parallel_printer_port_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_PAR1_CTRL_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_PAR1_CTRL_DATA. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_PAR1_CTRL_DATA. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_PAR1_CTRL_DATA(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - *R_PAR1_CTRL_DATA__SADDR = ( \ - REG_INITIATED(R_PAR1_CTRL_DATA_) \ - REG_VAL__R_PAR1_CTRL_DATA_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \ - ), \ - R_PAR1_CTRL_DATA__WRITE(R_PAR1_CTRL_DATA__ADDR, *R_PAR1_CTRL_DATA__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_PAR1_CTRL_DATA__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_PAR1_CTRL_DATA. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_PAR1_CTRL_DATA. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_PAR1_CTRL_DATA__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - *R_PAR1_CTRL_DATA__SADDR = ( \ - REG_INITIATED(R_PAR1_CTRL_DATA_) \ - REG_VAL__R_PAR1_CTRL_DATA_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_PAR1_CTRL_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_PAR1_CTRL_DATA(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - (R_PAR1_CTRL_DATA__peri_int__##f1##__MASK & REG__##v1) | \ - (R_PAR1_CTRL_DATA__oe__##f2##__MASK & REG__##v2) | \ - (R_PAR1_CTRL_DATA__seli__##f3##__MASK & REG__##v3) | \ - (R_PAR1_CTRL_DATA__autofd__##f4##__MASK & REG__##v4) | \ - (R_PAR1_CTRL_DATA__strb__##f5##__MASK & REG__##v5) | \ - (R_PAR1_CTRL_DATA__init__##f6##__MASK & REG__##v6) | \ - (R_PAR1_CTRL_DATA__ecp_cmd__##f7##__MASK & REG__##v7) | \ - (R_PAR1_CTRL_DATA__data__##f8##__MASK & REG__##v8) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_PAR1_CTRL_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_PAR1_CTRL_DATA. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_PAR1_CTRL_DATA(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - (R_PAR1_CTRL_DATA__peri_int__##f1##__VAL(R_PAR1_CTRL_DATA_, peri_int_, v1) << R_PAR1_CTRL_DATA__peri_int__BITNR) | \ - (R_PAR1_CTRL_DATA__oe__##f2##__VAL(R_PAR1_CTRL_DATA_, oe_, v2) << R_PAR1_CTRL_DATA__oe__BITNR) | \ - (R_PAR1_CTRL_DATA__seli__##f3##__VAL(R_PAR1_CTRL_DATA_, seli_, v3) << R_PAR1_CTRL_DATA__seli__BITNR) | \ - (R_PAR1_CTRL_DATA__autofd__##f4##__VAL(R_PAR1_CTRL_DATA_, autofd_, v4) << R_PAR1_CTRL_DATA__autofd__BITNR) | \ - (R_PAR1_CTRL_DATA__strb__##f5##__VAL(R_PAR1_CTRL_DATA_, strb_, v5) << R_PAR1_CTRL_DATA__strb__BITNR) | \ - (R_PAR1_CTRL_DATA__init__##f6##__VAL(R_PAR1_CTRL_DATA_, init_, v6) << R_PAR1_CTRL_DATA__init__BITNR) | \ - (R_PAR1_CTRL_DATA__ecp_cmd__##f7##__VAL(R_PAR1_CTRL_DATA_, ecp_cmd_, v7) << R_PAR1_CTRL_DATA__ecp_cmd__BITNR) | \ - (R_PAR1_CTRL_DATA__data__##f8##__VAL(R_PAR1_CTRL_DATA_, data_, v8) << R_PAR1_CTRL_DATA__data__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_PAR1_CTRL_DATA_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_PAR1_CTRL_DATA. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_PAR1_CTRL_DATA_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8) ( \ - (R_PAR1_CTRL_DATA__peri_int__##f1_##_VAL(R_PAR1_CTRL_DATA_, peri_int_, v1) << R_PAR1_CTRL_DATA__peri_int__BITNR) | \ - (R_PAR1_CTRL_DATA__oe__##f2_##_VAL(R_PAR1_CTRL_DATA_, oe_, v2) << R_PAR1_CTRL_DATA__oe__BITNR) | \ - (R_PAR1_CTRL_DATA__seli__##f3_##_VAL(R_PAR1_CTRL_DATA_, seli_, v3) << R_PAR1_CTRL_DATA__seli__BITNR) | \ - (R_PAR1_CTRL_DATA__autofd__##f4_##_VAL(R_PAR1_CTRL_DATA_, autofd_, v4) << R_PAR1_CTRL_DATA__autofd__BITNR) | \ - (R_PAR1_CTRL_DATA__strb__##f5_##_VAL(R_PAR1_CTRL_DATA_, strb_, v5) << R_PAR1_CTRL_DATA__strb__BITNR) | \ - (R_PAR1_CTRL_DATA__init__##f6_##_VAL(R_PAR1_CTRL_DATA_, init_, v6) << R_PAR1_CTRL_DATA__init__BITNR) | \ - (R_PAR1_CTRL_DATA__ecp_cmd__##f7_##_VAL(R_PAR1_CTRL_DATA_, ecp_cmd_, v7) << R_PAR1_CTRL_DATA__ecp_cmd__BITNR) | \ - (R_PAR1_CTRL_DATA__data__##f8_##_VAL(R_PAR1_CTRL_DATA_, data_, v8) << R_PAR1_CTRL_DATA__data__BITNR) \ -) - -#endif - -/* - * R_PAR1_DELAY - * - type: WO - * - addr: 0xb0000058 - * - group: Parallel printer port registers - */ - -#if USE_GROUP__Parallel_printer_port_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_PAR1_DELAY -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_PAR1_DELAY. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_PAR1_DELAY. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_PAR1_DELAY(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \ - *R_PAR1_DELAY__SADDR = ( \ - REG_INITIATED(R_PAR1_DELAY_) \ - REG_VAL__R_PAR1_DELAY_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6) \ - ), \ - R_PAR1_DELAY__WRITE(R_PAR1_DELAY__ADDR, *R_PAR1_DELAY__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_PAR1_DELAY__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_PAR1_DELAY. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_PAR1_DELAY. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_PAR1_DELAY__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \ - *R_PAR1_DELAY__SADDR = ( \ - REG_INITIATED(R_PAR1_DELAY_) \ - REG_VAL__R_PAR1_DELAY_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_PAR1_DELAY -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_PAR1_DELAY(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \ - (R_PAR1_DELAY__fine_hold__##f1##__MASK & REG__##v1) | \ - (R_PAR1_DELAY__hold__##f2##__MASK & REG__##v2) | \ - (R_PAR1_DELAY__fine_strb__##f3##__MASK & REG__##v3) | \ - (R_PAR1_DELAY__strobe__##f4##__MASK & REG__##v4) | \ - (R_PAR1_DELAY__fine_setup__##f5##__MASK & REG__##v5) | \ - (R_PAR1_DELAY__setup__##f6##__MASK & REG__##v6) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_PAR1_DELAY -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_PAR1_DELAY. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_PAR1_DELAY(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \ - (R_PAR1_DELAY__fine_hold__##f1##__VAL(R_PAR1_DELAY_, fine_hold_, v1) << R_PAR1_DELAY__fine_hold__BITNR) | \ - (R_PAR1_DELAY__hold__##f2##__VAL(R_PAR1_DELAY_, hold_, v2) << R_PAR1_DELAY__hold__BITNR) | \ - (R_PAR1_DELAY__fine_strb__##f3##__VAL(R_PAR1_DELAY_, fine_strb_, v3) << R_PAR1_DELAY__fine_strb__BITNR) | \ - (R_PAR1_DELAY__strobe__##f4##__VAL(R_PAR1_DELAY_, strobe_, v4) << R_PAR1_DELAY__strobe__BITNR) | \ - (R_PAR1_DELAY__fine_setup__##f5##__VAL(R_PAR1_DELAY_, fine_setup_, v5) << R_PAR1_DELAY__fine_setup__BITNR) | \ - (R_PAR1_DELAY__setup__##f6##__VAL(R_PAR1_DELAY_, setup_, v6) << R_PAR1_DELAY__setup__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_PAR1_DELAY_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_PAR1_DELAY. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_PAR1_DELAY_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6) ( \ - (R_PAR1_DELAY__fine_hold__##f1_##_VAL(R_PAR1_DELAY_, fine_hold_, v1) << R_PAR1_DELAY__fine_hold__BITNR) | \ - (R_PAR1_DELAY__hold__##f2_##_VAL(R_PAR1_DELAY_, hold_, v2) << R_PAR1_DELAY__hold__BITNR) | \ - (R_PAR1_DELAY__fine_strb__##f3_##_VAL(R_PAR1_DELAY_, fine_strb_, v3) << R_PAR1_DELAY__fine_strb__BITNR) | \ - (R_PAR1_DELAY__strobe__##f4_##_VAL(R_PAR1_DELAY_, strobe_, v4) << R_PAR1_DELAY__strobe__BITNR) | \ - (R_PAR1_DELAY__fine_setup__##f5_##_VAL(R_PAR1_DELAY_, fine_setup_, v5) << R_PAR1_DELAY__fine_setup__BITNR) | \ - (R_PAR1_DELAY__setup__##f6_##_VAL(R_PAR1_DELAY_, setup_, v6) << R_PAR1_DELAY__setup__BITNR) \ -) - -#endif - -/* - * R_PAR1_STATUS - * - type: RO - * - addr: 0xb0000052 - * - group: Parallel printer port registers - */ - -#if USE_GROUP__Parallel_printer_port_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_PAR1_STATUS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_PAR1_STATUS(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \ - (R_PAR1_STATUS__mode__##f1##__MASK & REG__##v1) | \ - (R_PAR1_STATUS__perr__##f2##__MASK & REG__##v2) | \ - (R_PAR1_STATUS__ack__##f3##__MASK & REG__##v3) | \ - (R_PAR1_STATUS__busy__##f4##__MASK & REG__##v4) | \ - (R_PAR1_STATUS__fault__##f5##__MASK & REG__##v5) | \ - (R_PAR1_STATUS__sel__##f6##__MASK & REG__##v6) | \ - (R_PAR1_STATUS__ext_mode__##f7##__MASK & REG__##v7) | \ - (R_PAR1_STATUS__tr_rdy__##f8##__MASK & REG__##v8) | \ - (R_PAR1_STATUS__dav__##f9##__MASK & REG__##v9) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_PAR1_STATUS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_PAR1_STATUS. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_PAR1_STATUS(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \ - (R_PAR1_STATUS__mode__##f1##__VAL(R_PAR1_STATUS_, mode_, v1) << R_PAR1_STATUS__mode__BITNR) | \ - (R_PAR1_STATUS__perr__##f2##__VAL(R_PAR1_STATUS_, perr_, v2) << R_PAR1_STATUS__perr__BITNR) | \ - (R_PAR1_STATUS__ack__##f3##__VAL(R_PAR1_STATUS_, ack_, v3) << R_PAR1_STATUS__ack__BITNR) | \ - (R_PAR1_STATUS__busy__##f4##__VAL(R_PAR1_STATUS_, busy_, v4) << R_PAR1_STATUS__busy__BITNR) | \ - (R_PAR1_STATUS__fault__##f5##__VAL(R_PAR1_STATUS_, fault_, v5) << R_PAR1_STATUS__fault__BITNR) | \ - (R_PAR1_STATUS__sel__##f6##__VAL(R_PAR1_STATUS_, sel_, v6) << R_PAR1_STATUS__sel__BITNR) | \ - (R_PAR1_STATUS__ext_mode__##f7##__VAL(R_PAR1_STATUS_, ext_mode_, v7) << R_PAR1_STATUS__ext_mode__BITNR) | \ - (R_PAR1_STATUS__tr_rdy__##f8##__VAL(R_PAR1_STATUS_, tr_rdy_, v8) << R_PAR1_STATUS__tr_rdy__BITNR) | \ - (R_PAR1_STATUS__dav__##f9##__VAL(R_PAR1_STATUS_, dav_, v9) << R_PAR1_STATUS__dav__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_PAR1_STATUS_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_PAR1_STATUS. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_PAR1_STATUS_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9) ( \ - (R_PAR1_STATUS__mode__##f1_##_VAL(R_PAR1_STATUS_, mode_, v1) << R_PAR1_STATUS__mode__BITNR) | \ - (R_PAR1_STATUS__perr__##f2_##_VAL(R_PAR1_STATUS_, perr_, v2) << R_PAR1_STATUS__perr__BITNR) | \ - (R_PAR1_STATUS__ack__##f3_##_VAL(R_PAR1_STATUS_, ack_, v3) << R_PAR1_STATUS__ack__BITNR) | \ - (R_PAR1_STATUS__busy__##f4_##_VAL(R_PAR1_STATUS_, busy_, v4) << R_PAR1_STATUS__busy__BITNR) | \ - (R_PAR1_STATUS__fault__##f5_##_VAL(R_PAR1_STATUS_, fault_, v5) << R_PAR1_STATUS__fault__BITNR) | \ - (R_PAR1_STATUS__sel__##f6_##_VAL(R_PAR1_STATUS_, sel_, v6) << R_PAR1_STATUS__sel__BITNR) | \ - (R_PAR1_STATUS__ext_mode__##f7_##_VAL(R_PAR1_STATUS_, ext_mode_, v7) << R_PAR1_STATUS__ext_mode__BITNR) | \ - (R_PAR1_STATUS__tr_rdy__##f8_##_VAL(R_PAR1_STATUS_, tr_rdy_, v8) << R_PAR1_STATUS__tr_rdy__BITNR) | \ - (R_PAR1_STATUS__dav__##f9_##_VAL(R_PAR1_STATUS_, dav_, v9) << R_PAR1_STATUS__dav__BITNR) \ -) - -#endif - -/* - * R_PAR1_STATUS_DATA - * - type: RO - * - addr: 0xb0000050 - * - group: Parallel printer port registers - */ - -#if USE_GROUP__Parallel_printer_port_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_PAR1_STATUS_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_PAR1_STATUS_DATA(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11) ( \ - (R_PAR1_STATUS_DATA__mode__##f1##__MASK & REG__##v1) | \ - (R_PAR1_STATUS_DATA__perr__##f2##__MASK & REG__##v2) | \ - (R_PAR1_STATUS_DATA__ack__##f3##__MASK & REG__##v3) | \ - (R_PAR1_STATUS_DATA__busy__##f4##__MASK & REG__##v4) | \ - (R_PAR1_STATUS_DATA__fault__##f5##__MASK & REG__##v5) | \ - (R_PAR1_STATUS_DATA__sel__##f6##__MASK & REG__##v6) | \ - (R_PAR1_STATUS_DATA__ext_mode__##f7##__MASK & REG__##v7) | \ - (R_PAR1_STATUS_DATA__tr_rdy__##f8##__MASK & REG__##v8) | \ - (R_PAR1_STATUS_DATA__dav__##f9##__MASK & REG__##v9) | \ - (R_PAR1_STATUS_DATA__ecp_cmd__##f10##__MASK & REG__##v10) | \ - (R_PAR1_STATUS_DATA__data__##f11##__MASK & REG__##v11) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_PAR1_STATUS_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_PAR1_STATUS_DATA. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_PAR1_STATUS_DATA(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11) ( \ - (R_PAR1_STATUS_DATA__mode__##f1##__VAL(R_PAR1_STATUS_DATA_, mode_, v1) << R_PAR1_STATUS_DATA__mode__BITNR) | \ - (R_PAR1_STATUS_DATA__perr__##f2##__VAL(R_PAR1_STATUS_DATA_, perr_, v2) << R_PAR1_STATUS_DATA__perr__BITNR) | \ - (R_PAR1_STATUS_DATA__ack__##f3##__VAL(R_PAR1_STATUS_DATA_, ack_, v3) << R_PAR1_STATUS_DATA__ack__BITNR) | \ - (R_PAR1_STATUS_DATA__busy__##f4##__VAL(R_PAR1_STATUS_DATA_, busy_, v4) << R_PAR1_STATUS_DATA__busy__BITNR) | \ - (R_PAR1_STATUS_DATA__fault__##f5##__VAL(R_PAR1_STATUS_DATA_, fault_, v5) << R_PAR1_STATUS_DATA__fault__BITNR) | \ - (R_PAR1_STATUS_DATA__sel__##f6##__VAL(R_PAR1_STATUS_DATA_, sel_, v6) << R_PAR1_STATUS_DATA__sel__BITNR) | \ - (R_PAR1_STATUS_DATA__ext_mode__##f7##__VAL(R_PAR1_STATUS_DATA_, ext_mode_, v7) << R_PAR1_STATUS_DATA__ext_mode__BITNR) | \ - (R_PAR1_STATUS_DATA__tr_rdy__##f8##__VAL(R_PAR1_STATUS_DATA_, tr_rdy_, v8) << R_PAR1_STATUS_DATA__tr_rdy__BITNR) | \ - (R_PAR1_STATUS_DATA__dav__##f9##__VAL(R_PAR1_STATUS_DATA_, dav_, v9) << R_PAR1_STATUS_DATA__dav__BITNR) | \ - (R_PAR1_STATUS_DATA__ecp_cmd__##f10##__VAL(R_PAR1_STATUS_DATA_, ecp_cmd_, v10) << R_PAR1_STATUS_DATA__ecp_cmd__BITNR) | \ - (R_PAR1_STATUS_DATA__data__##f11##__VAL(R_PAR1_STATUS_DATA_, data_, v11) << R_PAR1_STATUS_DATA__data__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_PAR1_STATUS_DATA_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_PAR1_STATUS_DATA. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_PAR1_STATUS_DATA_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11) ( \ - (R_PAR1_STATUS_DATA__mode__##f1_##_VAL(R_PAR1_STATUS_DATA_, mode_, v1) << R_PAR1_STATUS_DATA__mode__BITNR) | \ - (R_PAR1_STATUS_DATA__perr__##f2_##_VAL(R_PAR1_STATUS_DATA_, perr_, v2) << R_PAR1_STATUS_DATA__perr__BITNR) | \ - (R_PAR1_STATUS_DATA__ack__##f3_##_VAL(R_PAR1_STATUS_DATA_, ack_, v3) << R_PAR1_STATUS_DATA__ack__BITNR) | \ - (R_PAR1_STATUS_DATA__busy__##f4_##_VAL(R_PAR1_STATUS_DATA_, busy_, v4) << R_PAR1_STATUS_DATA__busy__BITNR) | \ - (R_PAR1_STATUS_DATA__fault__##f5_##_VAL(R_PAR1_STATUS_DATA_, fault_, v5) << R_PAR1_STATUS_DATA__fault__BITNR) | \ - (R_PAR1_STATUS_DATA__sel__##f6_##_VAL(R_PAR1_STATUS_DATA_, sel_, v6) << R_PAR1_STATUS_DATA__sel__BITNR) | \ - (R_PAR1_STATUS_DATA__ext_mode__##f7_##_VAL(R_PAR1_STATUS_DATA_, ext_mode_, v7) << R_PAR1_STATUS_DATA__ext_mode__BITNR) | \ - (R_PAR1_STATUS_DATA__tr_rdy__##f8_##_VAL(R_PAR1_STATUS_DATA_, tr_rdy_, v8) << R_PAR1_STATUS_DATA__tr_rdy__BITNR) | \ - (R_PAR1_STATUS_DATA__dav__##f9_##_VAL(R_PAR1_STATUS_DATA_, dav_, v9) << R_PAR1_STATUS_DATA__dav__BITNR) | \ - (R_PAR1_STATUS_DATA__ecp_cmd__##f10_##_VAL(R_PAR1_STATUS_DATA_, ecp_cmd_, v10) << R_PAR1_STATUS_DATA__ecp_cmd__BITNR) | \ - (R_PAR1_STATUS_DATA__data__##f11_##_VAL(R_PAR1_STATUS_DATA_, data_, v11) << R_PAR1_STATUS_DATA__data__BITNR) \ -) - -#endif - -/* - * R_PAR_ECP16_DATA - * - type: RW - * - addr: 0xb0000040 - * - group: Parallel printer port registers - */ - -#if USE_GROUP__Parallel_printer_port_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_PAR_ECP16_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_PAR_ECP16_DATA. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_PAR_ECP16_DATA. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_PAR_ECP16_DATA(f1,v1) ( \ - R_PAR_ECP16_DATA__WRITE(R_PAR_ECP16_DATA__ADDR, ( \ - REG_VAL__R_PAR_ECP16_DATA_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_PAR_ECP16_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_PAR_ECP16_DATA(f1,v1) ( \ - (R_PAR_ECP16_DATA__data__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_PAR_ECP16_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_PAR_ECP16_DATA. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_PAR_ECP16_DATA(f1,v1) ( \ - (R_PAR_ECP16_DATA__data__##f1##__VAL(R_PAR_ECP16_DATA_, data_, v1) << R_PAR_ECP16_DATA__data__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_PAR_ECP16_DATA_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_PAR_ECP16_DATA. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_PAR_ECP16_DATA_(f1_,v1) ( \ - (R_PAR_ECP16_DATA__data__##f1_##_VAL(R_PAR_ECP16_DATA_, data_, v1) << R_PAR_ECP16_DATA__data__BITNR) \ -) - -#endif - -/* - * R_PHY_COUNTERS - * - type: RO - * - addr: 0xb00000ac - * - group: Network interface registers - */ - -#if USE_GROUP__Network_interface_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_PHY_COUNTERS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_PHY_COUNTERS(f1,v1,f2,v2) ( \ - (R_PHY_COUNTERS__sqe_test_error__##f1##__MASK & REG__##v1) | \ - (R_PHY_COUNTERS__carrier_loss__##f2##__MASK & REG__##v2) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_PHY_COUNTERS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_PHY_COUNTERS. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_PHY_COUNTERS(f1,v1,f2,v2) ( \ - (R_PHY_COUNTERS__sqe_test_error__##f1##__VAL(R_PHY_COUNTERS_, sqe_test_error_, v1) << R_PHY_COUNTERS__sqe_test_error__BITNR) | \ - (R_PHY_COUNTERS__carrier_loss__##f2##__VAL(R_PHY_COUNTERS_, carrier_loss_, v2) << R_PHY_COUNTERS__carrier_loss__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_PHY_COUNTERS_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_PHY_COUNTERS. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_PHY_COUNTERS_(f1_,v1,f2_,v2) ( \ - (R_PHY_COUNTERS__sqe_test_error__##f1_##_VAL(R_PHY_COUNTERS_, sqe_test_error_, v1) << R_PHY_COUNTERS__sqe_test_error__BITNR) | \ - (R_PHY_COUNTERS__carrier_loss__##f2_##_VAL(R_PHY_COUNTERS_, carrier_loss_, v2) << R_PHY_COUNTERS__carrier_loss__BITNR) \ -) - -#endif - -/* - * R_PORT_G_DATA - * - type: RW - * - addr: 0xb0000028 - * - group: General config registers - */ - -#if USE_GROUP__General_config_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_PORT_G_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_PORT_G_DATA. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_PORT_G_DATA. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_PORT_G_DATA(f1,v1) ( \ - R_PORT_G_DATA__WRITE(R_PORT_G_DATA__ADDR, ( \ - REG_VAL__R_PORT_G_DATA_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_PORT_G_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_PORT_G_DATA(f1,v1) ( \ - (R_PORT_G_DATA__data__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_PORT_G_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_PORT_G_DATA. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_PORT_G_DATA(f1,v1) ( \ - (R_PORT_G_DATA__data__##f1##__VAL(R_PORT_G_DATA_, data_, v1) << R_PORT_G_DATA__data__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_PORT_G_DATA_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_PORT_G_DATA. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_PORT_G_DATA_(f1_,v1) ( \ - (R_PORT_G_DATA__data__##f1_##_VAL(R_PORT_G_DATA_, data_, v1) << R_PORT_G_DATA__data__BITNR) \ -) - -#endif - -/* - * R_PORT_PA_DATA - * - type: WO - * - addr: 0xb0000030 - * - group: General port configuration registers - */ - -#if USE_GROUP__General_port_configuration_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_PORT_PA_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_PORT_PA_DATA. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_PORT_PA_DATA. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_PORT_PA_DATA(f1,v1) ( \ - *R_PORT_PA_DATA__SADDR = ( \ - REG_INITIATED(R_PORT_PA_DATA_) \ - REG_VAL__R_PORT_PA_DATA_(f1##_,v1) \ - ), \ - R_PORT_PA_DATA__WRITE(R_PORT_PA_DATA__ADDR, *R_PORT_PA_DATA__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_PORT_PA_DATA__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_PORT_PA_DATA. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_PORT_PA_DATA. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_PORT_PA_DATA__SHADOW(f1,v1) ( \ - *R_PORT_PA_DATA__SADDR = ( \ - REG_INITIATED(R_PORT_PA_DATA_) \ - REG_VAL__R_PORT_PA_DATA_(f1##_,v1) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_PORT_PA_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_PORT_PA_DATA(f1,v1) ( \ - (R_PORT_PA_DATA__data_out__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_PORT_PA_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_PORT_PA_DATA. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_PORT_PA_DATA(f1,v1) ( \ - (R_PORT_PA_DATA__data_out__##f1##__VAL(R_PORT_PA_DATA_, data_out_, v1) << R_PORT_PA_DATA__data_out__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_PORT_PA_DATA_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_PORT_PA_DATA. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_PORT_PA_DATA_(f1_,v1) ( \ - (R_PORT_PA_DATA__data_out__##f1_##_VAL(R_PORT_PA_DATA_, data_out_, v1) << R_PORT_PA_DATA__data_out__BITNR) \ -) - -#endif - -/* - * R_PORT_PA_DIR - * - type: WO - * - addr: 0xb0000031 - * - group: General port configuration registers - */ - -#if USE_GROUP__General_port_configuration_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_PORT_PA_DIR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_PORT_PA_DIR. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_PORT_PA_DIR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_PORT_PA_DIR(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - *R_PORT_PA_DIR__SADDR = ( \ - REG_INITIATED(R_PORT_PA_DIR_) \ - REG_VAL__R_PORT_PA_DIR_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \ - ), \ - R_PORT_PA_DIR__WRITE(R_PORT_PA_DIR__ADDR, *R_PORT_PA_DIR__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_PORT_PA_DIR__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_PORT_PA_DIR. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_PORT_PA_DIR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_PORT_PA_DIR__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - *R_PORT_PA_DIR__SADDR = ( \ - REG_INITIATED(R_PORT_PA_DIR_) \ - REG_VAL__R_PORT_PA_DIR_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_PORT_PA_DIR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_PORT_PA_DIR(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - (R_PORT_PA_DIR__dir7__##f1##__MASK & REG__##v1) | \ - (R_PORT_PA_DIR__dir6__##f2##__MASK & REG__##v2) | \ - (R_PORT_PA_DIR__dir5__##f3##__MASK & REG__##v3) | \ - (R_PORT_PA_DIR__dir4__##f4##__MASK & REG__##v4) | \ - (R_PORT_PA_DIR__dir3__##f5##__MASK & REG__##v5) | \ - (R_PORT_PA_DIR__dir2__##f6##__MASK & REG__##v6) | \ - (R_PORT_PA_DIR__dir1__##f7##__MASK & REG__##v7) | \ - (R_PORT_PA_DIR__dir0__##f8##__MASK & REG__##v8) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_PORT_PA_DIR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_PORT_PA_DIR. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_PORT_PA_DIR(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - (R_PORT_PA_DIR__dir7__##f1##__VAL(R_PORT_PA_DIR_, dir7_, v1) << R_PORT_PA_DIR__dir7__BITNR) | \ - (R_PORT_PA_DIR__dir6__##f2##__VAL(R_PORT_PA_DIR_, dir6_, v2) << R_PORT_PA_DIR__dir6__BITNR) | \ - (R_PORT_PA_DIR__dir5__##f3##__VAL(R_PORT_PA_DIR_, dir5_, v3) << R_PORT_PA_DIR__dir5__BITNR) | \ - (R_PORT_PA_DIR__dir4__##f4##__VAL(R_PORT_PA_DIR_, dir4_, v4) << R_PORT_PA_DIR__dir4__BITNR) | \ - (R_PORT_PA_DIR__dir3__##f5##__VAL(R_PORT_PA_DIR_, dir3_, v5) << R_PORT_PA_DIR__dir3__BITNR) | \ - (R_PORT_PA_DIR__dir2__##f6##__VAL(R_PORT_PA_DIR_, dir2_, v6) << R_PORT_PA_DIR__dir2__BITNR) | \ - (R_PORT_PA_DIR__dir1__##f7##__VAL(R_PORT_PA_DIR_, dir1_, v7) << R_PORT_PA_DIR__dir1__BITNR) | \ - (R_PORT_PA_DIR__dir0__##f8##__VAL(R_PORT_PA_DIR_, dir0_, v8) << R_PORT_PA_DIR__dir0__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_PORT_PA_DIR_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_PORT_PA_DIR. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_PORT_PA_DIR_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8) ( \ - (R_PORT_PA_DIR__dir7__##f1_##_VAL(R_PORT_PA_DIR_, dir7_, v1) << R_PORT_PA_DIR__dir7__BITNR) | \ - (R_PORT_PA_DIR__dir6__##f2_##_VAL(R_PORT_PA_DIR_, dir6_, v2) << R_PORT_PA_DIR__dir6__BITNR) | \ - (R_PORT_PA_DIR__dir5__##f3_##_VAL(R_PORT_PA_DIR_, dir5_, v3) << R_PORT_PA_DIR__dir5__BITNR) | \ - (R_PORT_PA_DIR__dir4__##f4_##_VAL(R_PORT_PA_DIR_, dir4_, v4) << R_PORT_PA_DIR__dir4__BITNR) | \ - (R_PORT_PA_DIR__dir3__##f5_##_VAL(R_PORT_PA_DIR_, dir3_, v5) << R_PORT_PA_DIR__dir3__BITNR) | \ - (R_PORT_PA_DIR__dir2__##f6_##_VAL(R_PORT_PA_DIR_, dir2_, v6) << R_PORT_PA_DIR__dir2__BITNR) | \ - (R_PORT_PA_DIR__dir1__##f7_##_VAL(R_PORT_PA_DIR_, dir1_, v7) << R_PORT_PA_DIR__dir1__BITNR) | \ - (R_PORT_PA_DIR__dir0__##f8_##_VAL(R_PORT_PA_DIR_, dir0_, v8) << R_PORT_PA_DIR__dir0__BITNR) \ -) - -#endif - -/* - * R_PORT_PA_READ - * - type: RO - * - addr: 0xb0000030 - * - group: General port configuration registers - */ - -#if USE_GROUP__General_port_configuration_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_PORT_PA_READ -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_PORT_PA_READ(f1,v1) ( \ - (R_PORT_PA_READ__data_in__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_PORT_PA_READ -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_PORT_PA_READ. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_PORT_PA_READ(f1,v1) ( \ - (R_PORT_PA_READ__data_in__##f1##__VAL(R_PORT_PA_READ_, data_in_, v1) << R_PORT_PA_READ__data_in__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_PORT_PA_READ_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_PORT_PA_READ. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_PORT_PA_READ_(f1_,v1) ( \ - (R_PORT_PA_READ__data_in__##f1_##_VAL(R_PORT_PA_READ_, data_in_, v1) << R_PORT_PA_READ__data_in__BITNR) \ -) - -#endif - -/* - * R_PORT_PA_SET - * - type: WO - * - addr: 0xb0000030 - * - group: General port configuration registers - */ - -#if USE_GROUP__General_port_configuration_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_PORT_PA_SET -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_PORT_PA_SET. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_PORT_PA_SET. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_PORT_PA_SET(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \ - *R_PORT_PA_SET__SADDR = ( \ - REG_INITIATED(R_PORT_PA_SET_) \ - REG_VAL__R_PORT_PA_SET_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9) \ - ), \ - R_PORT_PA_SET__WRITE(R_PORT_PA_SET__ADDR, *R_PORT_PA_SET__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_PORT_PA_SET__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_PORT_PA_SET. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_PORT_PA_SET. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_PORT_PA_SET__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \ - *R_PORT_PA_SET__SADDR = ( \ - REG_INITIATED(R_PORT_PA_SET_) \ - REG_VAL__R_PORT_PA_SET_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_PORT_PA_SET -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_PORT_PA_SET(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \ - (R_PORT_PA_SET__dir7__##f1##__MASK & REG__##v1) | \ - (R_PORT_PA_SET__dir6__##f2##__MASK & REG__##v2) | \ - (R_PORT_PA_SET__dir5__##f3##__MASK & REG__##v3) | \ - (R_PORT_PA_SET__dir4__##f4##__MASK & REG__##v4) | \ - (R_PORT_PA_SET__dir3__##f5##__MASK & REG__##v5) | \ - (R_PORT_PA_SET__dir2__##f6##__MASK & REG__##v6) | \ - (R_PORT_PA_SET__dir1__##f7##__MASK & REG__##v7) | \ - (R_PORT_PA_SET__dir0__##f8##__MASK & REG__##v8) | \ - (R_PORT_PA_SET__data_out__##f9##__MASK & REG__##v9) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_PORT_PA_SET -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_PORT_PA_SET. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_PORT_PA_SET(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \ - (R_PORT_PA_SET__dir7__##f1##__VAL(R_PORT_PA_SET_, dir7_, v1) << R_PORT_PA_SET__dir7__BITNR) | \ - (R_PORT_PA_SET__dir6__##f2##__VAL(R_PORT_PA_SET_, dir6_, v2) << R_PORT_PA_SET__dir6__BITNR) | \ - (R_PORT_PA_SET__dir5__##f3##__VAL(R_PORT_PA_SET_, dir5_, v3) << R_PORT_PA_SET__dir5__BITNR) | \ - (R_PORT_PA_SET__dir4__##f4##__VAL(R_PORT_PA_SET_, dir4_, v4) << R_PORT_PA_SET__dir4__BITNR) | \ - (R_PORT_PA_SET__dir3__##f5##__VAL(R_PORT_PA_SET_, dir3_, v5) << R_PORT_PA_SET__dir3__BITNR) | \ - (R_PORT_PA_SET__dir2__##f6##__VAL(R_PORT_PA_SET_, dir2_, v6) << R_PORT_PA_SET__dir2__BITNR) | \ - (R_PORT_PA_SET__dir1__##f7##__VAL(R_PORT_PA_SET_, dir1_, v7) << R_PORT_PA_SET__dir1__BITNR) | \ - (R_PORT_PA_SET__dir0__##f8##__VAL(R_PORT_PA_SET_, dir0_, v8) << R_PORT_PA_SET__dir0__BITNR) | \ - (R_PORT_PA_SET__data_out__##f9##__VAL(R_PORT_PA_SET_, data_out_, v9) << R_PORT_PA_SET__data_out__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_PORT_PA_SET_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_PORT_PA_SET. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_PORT_PA_SET_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9) ( \ - (R_PORT_PA_SET__dir7__##f1_##_VAL(R_PORT_PA_SET_, dir7_, v1) << R_PORT_PA_SET__dir7__BITNR) | \ - (R_PORT_PA_SET__dir6__##f2_##_VAL(R_PORT_PA_SET_, dir6_, v2) << R_PORT_PA_SET__dir6__BITNR) | \ - (R_PORT_PA_SET__dir5__##f3_##_VAL(R_PORT_PA_SET_, dir5_, v3) << R_PORT_PA_SET__dir5__BITNR) | \ - (R_PORT_PA_SET__dir4__##f4_##_VAL(R_PORT_PA_SET_, dir4_, v4) << R_PORT_PA_SET__dir4__BITNR) | \ - (R_PORT_PA_SET__dir3__##f5_##_VAL(R_PORT_PA_SET_, dir3_, v5) << R_PORT_PA_SET__dir3__BITNR) | \ - (R_PORT_PA_SET__dir2__##f6_##_VAL(R_PORT_PA_SET_, dir2_, v6) << R_PORT_PA_SET__dir2__BITNR) | \ - (R_PORT_PA_SET__dir1__##f7_##_VAL(R_PORT_PA_SET_, dir1_, v7) << R_PORT_PA_SET__dir1__BITNR) | \ - (R_PORT_PA_SET__dir0__##f8_##_VAL(R_PORT_PA_SET_, dir0_, v8) << R_PORT_PA_SET__dir0__BITNR) | \ - (R_PORT_PA_SET__data_out__##f9_##_VAL(R_PORT_PA_SET_, data_out_, v9) << R_PORT_PA_SET__data_out__BITNR) \ -) - -#endif - -/* - * R_PORT_PB_CONFIG - * - type: WO - * - addr: 0xb000003a - * - group: General port configuration registers - */ - -#if USE_GROUP__General_port_configuration_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_PORT_PB_CONFIG -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_PORT_PB_CONFIG. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_PORT_PB_CONFIG. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_PORT_PB_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - *R_PORT_PB_CONFIG__SADDR = ( \ - REG_INITIATED(R_PORT_PB_CONFIG_) \ - REG_VAL__R_PORT_PB_CONFIG_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \ - ), \ - R_PORT_PB_CONFIG__WRITE(R_PORT_PB_CONFIG__ADDR, *R_PORT_PB_CONFIG__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_PORT_PB_CONFIG__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_PORT_PB_CONFIG. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_PORT_PB_CONFIG. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_PORT_PB_CONFIG__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - *R_PORT_PB_CONFIG__SADDR = ( \ - REG_INITIATED(R_PORT_PB_CONFIG_) \ - REG_VAL__R_PORT_PB_CONFIG_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_PORT_PB_CONFIG -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_PORT_PB_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - (R_PORT_PB_CONFIG__cs7__##f1##__MASK & REG__##v1) | \ - (R_PORT_PB_CONFIG__cs6__##f2##__MASK & REG__##v2) | \ - (R_PORT_PB_CONFIG__cs5__##f3##__MASK & REG__##v3) | \ - (R_PORT_PB_CONFIG__cs4__##f4##__MASK & REG__##v4) | \ - (R_PORT_PB_CONFIG__cs3__##f5##__MASK & REG__##v5) | \ - (R_PORT_PB_CONFIG__cs2__##f6##__MASK & REG__##v6) | \ - (R_PORT_PB_CONFIG__scsi1__##f7##__MASK & REG__##v7) | \ - (R_PORT_PB_CONFIG__scsi0__##f8##__MASK & REG__##v8) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_PORT_PB_CONFIG -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_PORT_PB_CONFIG. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_PORT_PB_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - (R_PORT_PB_CONFIG__cs7__##f1##__VAL(R_PORT_PB_CONFIG_, cs7_, v1) << R_PORT_PB_CONFIG__cs7__BITNR) | \ - (R_PORT_PB_CONFIG__cs6__##f2##__VAL(R_PORT_PB_CONFIG_, cs6_, v2) << R_PORT_PB_CONFIG__cs6__BITNR) | \ - (R_PORT_PB_CONFIG__cs5__##f3##__VAL(R_PORT_PB_CONFIG_, cs5_, v3) << R_PORT_PB_CONFIG__cs5__BITNR) | \ - (R_PORT_PB_CONFIG__cs4__##f4##__VAL(R_PORT_PB_CONFIG_, cs4_, v4) << R_PORT_PB_CONFIG__cs4__BITNR) | \ - (R_PORT_PB_CONFIG__cs3__##f5##__VAL(R_PORT_PB_CONFIG_, cs3_, v5) << R_PORT_PB_CONFIG__cs3__BITNR) | \ - (R_PORT_PB_CONFIG__cs2__##f6##__VAL(R_PORT_PB_CONFIG_, cs2_, v6) << R_PORT_PB_CONFIG__cs2__BITNR) | \ - (R_PORT_PB_CONFIG__scsi1__##f7##__VAL(R_PORT_PB_CONFIG_, scsi1_, v7) << R_PORT_PB_CONFIG__scsi1__BITNR) | \ - (R_PORT_PB_CONFIG__scsi0__##f8##__VAL(R_PORT_PB_CONFIG_, scsi0_, v8) << R_PORT_PB_CONFIG__scsi0__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_PORT_PB_CONFIG_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_PORT_PB_CONFIG. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_PORT_PB_CONFIG_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8) ( \ - (R_PORT_PB_CONFIG__cs7__##f1_##_VAL(R_PORT_PB_CONFIG_, cs7_, v1) << R_PORT_PB_CONFIG__cs7__BITNR) | \ - (R_PORT_PB_CONFIG__cs6__##f2_##_VAL(R_PORT_PB_CONFIG_, cs6_, v2) << R_PORT_PB_CONFIG__cs6__BITNR) | \ - (R_PORT_PB_CONFIG__cs5__##f3_##_VAL(R_PORT_PB_CONFIG_, cs5_, v3) << R_PORT_PB_CONFIG__cs5__BITNR) | \ - (R_PORT_PB_CONFIG__cs4__##f4_##_VAL(R_PORT_PB_CONFIG_, cs4_, v4) << R_PORT_PB_CONFIG__cs4__BITNR) | \ - (R_PORT_PB_CONFIG__cs3__##f5_##_VAL(R_PORT_PB_CONFIG_, cs3_, v5) << R_PORT_PB_CONFIG__cs3__BITNR) | \ - (R_PORT_PB_CONFIG__cs2__##f6_##_VAL(R_PORT_PB_CONFIG_, cs2_, v6) << R_PORT_PB_CONFIG__cs2__BITNR) | \ - (R_PORT_PB_CONFIG__scsi1__##f7_##_VAL(R_PORT_PB_CONFIG_, scsi1_, v7) << R_PORT_PB_CONFIG__scsi1__BITNR) | \ - (R_PORT_PB_CONFIG__scsi0__##f8_##_VAL(R_PORT_PB_CONFIG_, scsi0_, v8) << R_PORT_PB_CONFIG__scsi0__BITNR) \ -) - -#endif - -/* - * R_PORT_PB_DATA - * - type: WO - * - addr: 0xb0000038 - * - group: General port configuration registers - */ - -#if USE_GROUP__General_port_configuration_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_PORT_PB_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_PORT_PB_DATA. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_PORT_PB_DATA. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_PORT_PB_DATA(f1,v1) ( \ - *R_PORT_PB_DATA__SADDR = ( \ - REG_INITIATED(R_PORT_PB_DATA_) \ - REG_VAL__R_PORT_PB_DATA_(f1##_,v1) \ - ), \ - R_PORT_PB_DATA__WRITE(R_PORT_PB_DATA__ADDR, *R_PORT_PB_DATA__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_PORT_PB_DATA__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_PORT_PB_DATA. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_PORT_PB_DATA. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_PORT_PB_DATA__SHADOW(f1,v1) ( \ - *R_PORT_PB_DATA__SADDR = ( \ - REG_INITIATED(R_PORT_PB_DATA_) \ - REG_VAL__R_PORT_PB_DATA_(f1##_,v1) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_PORT_PB_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_PORT_PB_DATA(f1,v1) ( \ - (R_PORT_PB_DATA__data_out__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_PORT_PB_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_PORT_PB_DATA. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_PORT_PB_DATA(f1,v1) ( \ - (R_PORT_PB_DATA__data_out__##f1##__VAL(R_PORT_PB_DATA_, data_out_, v1) << R_PORT_PB_DATA__data_out__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_PORT_PB_DATA_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_PORT_PB_DATA. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_PORT_PB_DATA_(f1_,v1) ( \ - (R_PORT_PB_DATA__data_out__##f1_##_VAL(R_PORT_PB_DATA_, data_out_, v1) << R_PORT_PB_DATA__data_out__BITNR) \ -) - -#endif - -/* - * R_PORT_PB_DIR - * - type: WO - * - addr: 0xb0000039 - * - group: General port configuration registers - */ - -#if USE_GROUP__General_port_configuration_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_PORT_PB_DIR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_PORT_PB_DIR. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_PORT_PB_DIR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_PORT_PB_DIR(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - *R_PORT_PB_DIR__SADDR = ( \ - REG_INITIATED(R_PORT_PB_DIR_) \ - REG_VAL__R_PORT_PB_DIR_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \ - ), \ - R_PORT_PB_DIR__WRITE(R_PORT_PB_DIR__ADDR, *R_PORT_PB_DIR__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_PORT_PB_DIR__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_PORT_PB_DIR. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_PORT_PB_DIR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_PORT_PB_DIR__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - *R_PORT_PB_DIR__SADDR = ( \ - REG_INITIATED(R_PORT_PB_DIR_) \ - REG_VAL__R_PORT_PB_DIR_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_PORT_PB_DIR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_PORT_PB_DIR(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - (R_PORT_PB_DIR__dir7__##f1##__MASK & REG__##v1) | \ - (R_PORT_PB_DIR__dir6__##f2##__MASK & REG__##v2) | \ - (R_PORT_PB_DIR__dir5__##f3##__MASK & REG__##v3) | \ - (R_PORT_PB_DIR__dir4__##f4##__MASK & REG__##v4) | \ - (R_PORT_PB_DIR__dir3__##f5##__MASK & REG__##v5) | \ - (R_PORT_PB_DIR__dir2__##f6##__MASK & REG__##v6) | \ - (R_PORT_PB_DIR__dir1__##f7##__MASK & REG__##v7) | \ - (R_PORT_PB_DIR__dir0__##f8##__MASK & REG__##v8) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_PORT_PB_DIR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_PORT_PB_DIR. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_PORT_PB_DIR(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - (R_PORT_PB_DIR__dir7__##f1##__VAL(R_PORT_PB_DIR_, dir7_, v1) << R_PORT_PB_DIR__dir7__BITNR) | \ - (R_PORT_PB_DIR__dir6__##f2##__VAL(R_PORT_PB_DIR_, dir6_, v2) << R_PORT_PB_DIR__dir6__BITNR) | \ - (R_PORT_PB_DIR__dir5__##f3##__VAL(R_PORT_PB_DIR_, dir5_, v3) << R_PORT_PB_DIR__dir5__BITNR) | \ - (R_PORT_PB_DIR__dir4__##f4##__VAL(R_PORT_PB_DIR_, dir4_, v4) << R_PORT_PB_DIR__dir4__BITNR) | \ - (R_PORT_PB_DIR__dir3__##f5##__VAL(R_PORT_PB_DIR_, dir3_, v5) << R_PORT_PB_DIR__dir3__BITNR) | \ - (R_PORT_PB_DIR__dir2__##f6##__VAL(R_PORT_PB_DIR_, dir2_, v6) << R_PORT_PB_DIR__dir2__BITNR) | \ - (R_PORT_PB_DIR__dir1__##f7##__VAL(R_PORT_PB_DIR_, dir1_, v7) << R_PORT_PB_DIR__dir1__BITNR) | \ - (R_PORT_PB_DIR__dir0__##f8##__VAL(R_PORT_PB_DIR_, dir0_, v8) << R_PORT_PB_DIR__dir0__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_PORT_PB_DIR_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_PORT_PB_DIR. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_PORT_PB_DIR_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8) ( \ - (R_PORT_PB_DIR__dir7__##f1_##_VAL(R_PORT_PB_DIR_, dir7_, v1) << R_PORT_PB_DIR__dir7__BITNR) | \ - (R_PORT_PB_DIR__dir6__##f2_##_VAL(R_PORT_PB_DIR_, dir6_, v2) << R_PORT_PB_DIR__dir6__BITNR) | \ - (R_PORT_PB_DIR__dir5__##f3_##_VAL(R_PORT_PB_DIR_, dir5_, v3) << R_PORT_PB_DIR__dir5__BITNR) | \ - (R_PORT_PB_DIR__dir4__##f4_##_VAL(R_PORT_PB_DIR_, dir4_, v4) << R_PORT_PB_DIR__dir4__BITNR) | \ - (R_PORT_PB_DIR__dir3__##f5_##_VAL(R_PORT_PB_DIR_, dir3_, v5) << R_PORT_PB_DIR__dir3__BITNR) | \ - (R_PORT_PB_DIR__dir2__##f6_##_VAL(R_PORT_PB_DIR_, dir2_, v6) << R_PORT_PB_DIR__dir2__BITNR) | \ - (R_PORT_PB_DIR__dir1__##f7_##_VAL(R_PORT_PB_DIR_, dir1_, v7) << R_PORT_PB_DIR__dir1__BITNR) | \ - (R_PORT_PB_DIR__dir0__##f8_##_VAL(R_PORT_PB_DIR_, dir0_, v8) << R_PORT_PB_DIR__dir0__BITNR) \ -) - -#endif - -/* - * R_PORT_PB_I2C - * - type: WO - * - addr: 0xb000003b - * - group: General port configuration registers - */ - -#if USE_GROUP__General_port_configuration_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_PORT_PB_I2C -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_PORT_PB_I2C. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_PORT_PB_I2C. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_PORT_PB_I2C(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \ - *R_PORT_PB_I2C__SADDR = ( \ - REG_INITIATED(R_PORT_PB_I2C_) \ - REG_VAL__R_PORT_PB_I2C_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6) \ - ), \ - R_PORT_PB_I2C__WRITE(R_PORT_PB_I2C__ADDR, *R_PORT_PB_I2C__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_PORT_PB_I2C__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_PORT_PB_I2C. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_PORT_PB_I2C. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_PORT_PB_I2C__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \ - *R_PORT_PB_I2C__SADDR = ( \ - REG_INITIATED(R_PORT_PB_I2C_) \ - REG_VAL__R_PORT_PB_I2C_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_PORT_PB_I2C -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_PORT_PB_I2C(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \ - (R_PORT_PB_I2C__syncser3__##f1##__MASK & REG__##v1) | \ - (R_PORT_PB_I2C__syncser1__##f2##__MASK & REG__##v2) | \ - (R_PORT_PB_I2C__i2c_en__##f3##__MASK & REG__##v3) | \ - (R_PORT_PB_I2C__i2c_d__##f4##__MASK & REG__##v4) | \ - (R_PORT_PB_I2C__i2c_clk__##f5##__MASK & REG__##v5) | \ - (R_PORT_PB_I2C__i2c_oe___##f6##__MASK & REG__##v6) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_PORT_PB_I2C -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_PORT_PB_I2C. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_PORT_PB_I2C(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \ - (R_PORT_PB_I2C__syncser3__##f1##__VAL(R_PORT_PB_I2C_, syncser3_, v1) << R_PORT_PB_I2C__syncser3__BITNR) | \ - (R_PORT_PB_I2C__syncser1__##f2##__VAL(R_PORT_PB_I2C_, syncser1_, v2) << R_PORT_PB_I2C__syncser1__BITNR) | \ - (R_PORT_PB_I2C__i2c_en__##f3##__VAL(R_PORT_PB_I2C_, i2c_en_, v3) << R_PORT_PB_I2C__i2c_en__BITNR) | \ - (R_PORT_PB_I2C__i2c_d__##f4##__VAL(R_PORT_PB_I2C_, i2c_d_, v4) << R_PORT_PB_I2C__i2c_d__BITNR) | \ - (R_PORT_PB_I2C__i2c_clk__##f5##__VAL(R_PORT_PB_I2C_, i2c_clk_, v5) << R_PORT_PB_I2C__i2c_clk__BITNR) | \ - (R_PORT_PB_I2C__i2c_oe___##f6##__VAL(R_PORT_PB_I2C_, i2c_oe__, v6) << R_PORT_PB_I2C__i2c_oe___BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_PORT_PB_I2C_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_PORT_PB_I2C. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_PORT_PB_I2C_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6) ( \ - (R_PORT_PB_I2C__syncser3__##f1_##_VAL(R_PORT_PB_I2C_, syncser3_, v1) << R_PORT_PB_I2C__syncser3__BITNR) | \ - (R_PORT_PB_I2C__syncser1__##f2_##_VAL(R_PORT_PB_I2C_, syncser1_, v2) << R_PORT_PB_I2C__syncser1__BITNR) | \ - (R_PORT_PB_I2C__i2c_en__##f3_##_VAL(R_PORT_PB_I2C_, i2c_en_, v3) << R_PORT_PB_I2C__i2c_en__BITNR) | \ - (R_PORT_PB_I2C__i2c_d__##f4_##_VAL(R_PORT_PB_I2C_, i2c_d_, v4) << R_PORT_PB_I2C__i2c_d__BITNR) | \ - (R_PORT_PB_I2C__i2c_clk__##f5_##_VAL(R_PORT_PB_I2C_, i2c_clk_, v5) << R_PORT_PB_I2C__i2c_clk__BITNR) | \ - (R_PORT_PB_I2C__i2c_oe___##f6_##_VAL(R_PORT_PB_I2C_, i2c_oe__, v6) << R_PORT_PB_I2C__i2c_oe___BITNR) \ -) - -#endif - -/* - * R_PORT_PB_READ - * - type: RO - * - addr: 0xb0000038 - * - group: General port configuration registers - */ - -#if USE_GROUP__General_port_configuration_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_PORT_PB_READ -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_PORT_PB_READ(f1,v1) ( \ - (R_PORT_PB_READ__data_in__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_PORT_PB_READ -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_PORT_PB_READ. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_PORT_PB_READ(f1,v1) ( \ - (R_PORT_PB_READ__data_in__##f1##__VAL(R_PORT_PB_READ_, data_in_, v1) << R_PORT_PB_READ__data_in__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_PORT_PB_READ_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_PORT_PB_READ. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_PORT_PB_READ_(f1_,v1) ( \ - (R_PORT_PB_READ__data_in__##f1_##_VAL(R_PORT_PB_READ_, data_in_, v1) << R_PORT_PB_READ__data_in__BITNR) \ -) - -#endif - -/* - * R_PORT_PB_SET - * - type: WO - * - addr: 0xb0000038 - * - group: General port configuration registers - */ - -#if USE_GROUP__General_port_configuration_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_PORT_PB_SET -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_PORT_PB_SET. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_PORT_PB_SET. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_PORT_PB_SET(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23) ( \ - *R_PORT_PB_SET__SADDR = ( \ - REG_INITIATED(R_PORT_PB_SET_) \ - REG_VAL__R_PORT_PB_SET_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20,f21##_,v21,f22##_,v22,f23##_,v23) \ - ), \ - R_PORT_PB_SET__WRITE(R_PORT_PB_SET__ADDR, *R_PORT_PB_SET__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_PORT_PB_SET__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_PORT_PB_SET. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_PORT_PB_SET. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_PORT_PB_SET__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23) ( \ - *R_PORT_PB_SET__SADDR = ( \ - REG_INITIATED(R_PORT_PB_SET_) \ - REG_VAL__R_PORT_PB_SET_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20,f21##_,v21,f22##_,v22,f23##_,v23) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_PORT_PB_SET -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_PORT_PB_SET(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23) ( \ - (R_PORT_PB_SET__syncser3__##f1##__MASK & REG__##v1) | \ - (R_PORT_PB_SET__syncser1__##f2##__MASK & REG__##v2) | \ - (R_PORT_PB_SET__i2c_en__##f3##__MASK & REG__##v3) | \ - (R_PORT_PB_SET__i2c_d__##f4##__MASK & REG__##v4) | \ - (R_PORT_PB_SET__i2c_clk__##f5##__MASK & REG__##v5) | \ - (R_PORT_PB_SET__i2c_oe___##f6##__MASK & REG__##v6) | \ - (R_PORT_PB_SET__cs7__##f7##__MASK & REG__##v7) | \ - (R_PORT_PB_SET__cs6__##f8##__MASK & REG__##v8) | \ - (R_PORT_PB_SET__cs5__##f9##__MASK & REG__##v9) | \ - (R_PORT_PB_SET__cs4__##f10##__MASK & REG__##v10) | \ - (R_PORT_PB_SET__cs3__##f11##__MASK & REG__##v11) | \ - (R_PORT_PB_SET__cs2__##f12##__MASK & REG__##v12) | \ - (R_PORT_PB_SET__scsi1__##f13##__MASK & REG__##v13) | \ - (R_PORT_PB_SET__scsi0__##f14##__MASK & REG__##v14) | \ - (R_PORT_PB_SET__dir7__##f15##__MASK & REG__##v15) | \ - (R_PORT_PB_SET__dir6__##f16##__MASK & REG__##v16) | \ - (R_PORT_PB_SET__dir5__##f17##__MASK & REG__##v17) | \ - (R_PORT_PB_SET__dir4__##f18##__MASK & REG__##v18) | \ - (R_PORT_PB_SET__dir3__##f19##__MASK & REG__##v19) | \ - (R_PORT_PB_SET__dir2__##f20##__MASK & REG__##v20) | \ - (R_PORT_PB_SET__dir1__##f21##__MASK & REG__##v21) | \ - (R_PORT_PB_SET__dir0__##f22##__MASK & REG__##v22) | \ - (R_PORT_PB_SET__data_out__##f23##__MASK & REG__##v23) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_PORT_PB_SET -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_PORT_PB_SET. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_PORT_PB_SET(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23) ( \ - (R_PORT_PB_SET__syncser3__##f1##__VAL(R_PORT_PB_SET_, syncser3_, v1) << R_PORT_PB_SET__syncser3__BITNR) | \ - (R_PORT_PB_SET__syncser1__##f2##__VAL(R_PORT_PB_SET_, syncser1_, v2) << R_PORT_PB_SET__syncser1__BITNR) | \ - (R_PORT_PB_SET__i2c_en__##f3##__VAL(R_PORT_PB_SET_, i2c_en_, v3) << R_PORT_PB_SET__i2c_en__BITNR) | \ - (R_PORT_PB_SET__i2c_d__##f4##__VAL(R_PORT_PB_SET_, i2c_d_, v4) << R_PORT_PB_SET__i2c_d__BITNR) | \ - (R_PORT_PB_SET__i2c_clk__##f5##__VAL(R_PORT_PB_SET_, i2c_clk_, v5) << R_PORT_PB_SET__i2c_clk__BITNR) | \ - (R_PORT_PB_SET__i2c_oe___##f6##__VAL(R_PORT_PB_SET_, i2c_oe__, v6) << R_PORT_PB_SET__i2c_oe___BITNR) | \ - (R_PORT_PB_SET__cs7__##f7##__VAL(R_PORT_PB_SET_, cs7_, v7) << R_PORT_PB_SET__cs7__BITNR) | \ - (R_PORT_PB_SET__cs6__##f8##__VAL(R_PORT_PB_SET_, cs6_, v8) << R_PORT_PB_SET__cs6__BITNR) | \ - (R_PORT_PB_SET__cs5__##f9##__VAL(R_PORT_PB_SET_, cs5_, v9) << R_PORT_PB_SET__cs5__BITNR) | \ - (R_PORT_PB_SET__cs4__##f10##__VAL(R_PORT_PB_SET_, cs4_, v10) << R_PORT_PB_SET__cs4__BITNR) | \ - (R_PORT_PB_SET__cs3__##f11##__VAL(R_PORT_PB_SET_, cs3_, v11) << R_PORT_PB_SET__cs3__BITNR) | \ - (R_PORT_PB_SET__cs2__##f12##__VAL(R_PORT_PB_SET_, cs2_, v12) << R_PORT_PB_SET__cs2__BITNR) | \ - (R_PORT_PB_SET__scsi1__##f13##__VAL(R_PORT_PB_SET_, scsi1_, v13) << R_PORT_PB_SET__scsi1__BITNR) | \ - (R_PORT_PB_SET__scsi0__##f14##__VAL(R_PORT_PB_SET_, scsi0_, v14) << R_PORT_PB_SET__scsi0__BITNR) | \ - (R_PORT_PB_SET__dir7__##f15##__VAL(R_PORT_PB_SET_, dir7_, v15) << R_PORT_PB_SET__dir7__BITNR) | \ - (R_PORT_PB_SET__dir6__##f16##__VAL(R_PORT_PB_SET_, dir6_, v16) << R_PORT_PB_SET__dir6__BITNR) | \ - (R_PORT_PB_SET__dir5__##f17##__VAL(R_PORT_PB_SET_, dir5_, v17) << R_PORT_PB_SET__dir5__BITNR) | \ - (R_PORT_PB_SET__dir4__##f18##__VAL(R_PORT_PB_SET_, dir4_, v18) << R_PORT_PB_SET__dir4__BITNR) | \ - (R_PORT_PB_SET__dir3__##f19##__VAL(R_PORT_PB_SET_, dir3_, v19) << R_PORT_PB_SET__dir3__BITNR) | \ - (R_PORT_PB_SET__dir2__##f20##__VAL(R_PORT_PB_SET_, dir2_, v20) << R_PORT_PB_SET__dir2__BITNR) | \ - (R_PORT_PB_SET__dir1__##f21##__VAL(R_PORT_PB_SET_, dir1_, v21) << R_PORT_PB_SET__dir1__BITNR) | \ - (R_PORT_PB_SET__dir0__##f22##__VAL(R_PORT_PB_SET_, dir0_, v22) << R_PORT_PB_SET__dir0__BITNR) | \ - (R_PORT_PB_SET__data_out__##f23##__VAL(R_PORT_PB_SET_, data_out_, v23) << R_PORT_PB_SET__data_out__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_PORT_PB_SET_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_PORT_PB_SET. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_PORT_PB_SET_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16,f17_,v17,f18_,v18,f19_,v19,f20_,v20,f21_,v21,f22_,v22,f23_,v23) ( \ - (R_PORT_PB_SET__syncser3__##f1_##_VAL(R_PORT_PB_SET_, syncser3_, v1) << R_PORT_PB_SET__syncser3__BITNR) | \ - (R_PORT_PB_SET__syncser1__##f2_##_VAL(R_PORT_PB_SET_, syncser1_, v2) << R_PORT_PB_SET__syncser1__BITNR) | \ - (R_PORT_PB_SET__i2c_en__##f3_##_VAL(R_PORT_PB_SET_, i2c_en_, v3) << R_PORT_PB_SET__i2c_en__BITNR) | \ - (R_PORT_PB_SET__i2c_d__##f4_##_VAL(R_PORT_PB_SET_, i2c_d_, v4) << R_PORT_PB_SET__i2c_d__BITNR) | \ - (R_PORT_PB_SET__i2c_clk__##f5_##_VAL(R_PORT_PB_SET_, i2c_clk_, v5) << R_PORT_PB_SET__i2c_clk__BITNR) | \ - (R_PORT_PB_SET__i2c_oe___##f6_##_VAL(R_PORT_PB_SET_, i2c_oe__, v6) << R_PORT_PB_SET__i2c_oe___BITNR) | \ - (R_PORT_PB_SET__cs7__##f7_##_VAL(R_PORT_PB_SET_, cs7_, v7) << R_PORT_PB_SET__cs7__BITNR) | \ - (R_PORT_PB_SET__cs6__##f8_##_VAL(R_PORT_PB_SET_, cs6_, v8) << R_PORT_PB_SET__cs6__BITNR) | \ - (R_PORT_PB_SET__cs5__##f9_##_VAL(R_PORT_PB_SET_, cs5_, v9) << R_PORT_PB_SET__cs5__BITNR) | \ - (R_PORT_PB_SET__cs4__##f10_##_VAL(R_PORT_PB_SET_, cs4_, v10) << R_PORT_PB_SET__cs4__BITNR) | \ - (R_PORT_PB_SET__cs3__##f11_##_VAL(R_PORT_PB_SET_, cs3_, v11) << R_PORT_PB_SET__cs3__BITNR) | \ - (R_PORT_PB_SET__cs2__##f12_##_VAL(R_PORT_PB_SET_, cs2_, v12) << R_PORT_PB_SET__cs2__BITNR) | \ - (R_PORT_PB_SET__scsi1__##f13_##_VAL(R_PORT_PB_SET_, scsi1_, v13) << R_PORT_PB_SET__scsi1__BITNR) | \ - (R_PORT_PB_SET__scsi0__##f14_##_VAL(R_PORT_PB_SET_, scsi0_, v14) << R_PORT_PB_SET__scsi0__BITNR) | \ - (R_PORT_PB_SET__dir7__##f15_##_VAL(R_PORT_PB_SET_, dir7_, v15) << R_PORT_PB_SET__dir7__BITNR) | \ - (R_PORT_PB_SET__dir6__##f16_##_VAL(R_PORT_PB_SET_, dir6_, v16) << R_PORT_PB_SET__dir6__BITNR) | \ - (R_PORT_PB_SET__dir5__##f17_##_VAL(R_PORT_PB_SET_, dir5_, v17) << R_PORT_PB_SET__dir5__BITNR) | \ - (R_PORT_PB_SET__dir4__##f18_##_VAL(R_PORT_PB_SET_, dir4_, v18) << R_PORT_PB_SET__dir4__BITNR) | \ - (R_PORT_PB_SET__dir3__##f19_##_VAL(R_PORT_PB_SET_, dir3_, v19) << R_PORT_PB_SET__dir3__BITNR) | \ - (R_PORT_PB_SET__dir2__##f20_##_VAL(R_PORT_PB_SET_, dir2_, v20) << R_PORT_PB_SET__dir2__BITNR) | \ - (R_PORT_PB_SET__dir1__##f21_##_VAL(R_PORT_PB_SET_, dir1_, v21) << R_PORT_PB_SET__dir1__BITNR) | \ - (R_PORT_PB_SET__dir0__##f22_##_VAL(R_PORT_PB_SET_, dir0_, v22) << R_PORT_PB_SET__dir0__BITNR) | \ - (R_PORT_PB_SET__data_out__##f23_##_VAL(R_PORT_PB_SET_, data_out_, v23) << R_PORT_PB_SET__data_out__BITNR) \ -) - -#endif - -/* - * R_PRESCALE_STATUS - * - type: RO - * - addr: 0xb00000f0 - * - group: Timer registers - */ - -#if USE_GROUP__Timer_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_PRESCALE_STATUS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_PRESCALE_STATUS(f1,v1,f2,v2) ( \ - (R_PRESCALE_STATUS__ser_status__##f1##__MASK & REG__##v1) | \ - (R_PRESCALE_STATUS__tim_status__##f2##__MASK & REG__##v2) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_PRESCALE_STATUS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_PRESCALE_STATUS. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_PRESCALE_STATUS(f1,v1,f2,v2) ( \ - (R_PRESCALE_STATUS__ser_status__##f1##__VAL(R_PRESCALE_STATUS_, ser_status_, v1) << R_PRESCALE_STATUS__ser_status__BITNR) | \ - (R_PRESCALE_STATUS__tim_status__##f2##__VAL(R_PRESCALE_STATUS_, tim_status_, v2) << R_PRESCALE_STATUS__tim_status__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_PRESCALE_STATUS_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_PRESCALE_STATUS. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_PRESCALE_STATUS_(f1_,v1,f2_,v2) ( \ - (R_PRESCALE_STATUS__ser_status__##f1_##_VAL(R_PRESCALE_STATUS_, ser_status_, v1) << R_PRESCALE_STATUS__ser_status__BITNR) | \ - (R_PRESCALE_STATUS__tim_status__##f2_##_VAL(R_PRESCALE_STATUS_, tim_status_, v2) << R_PRESCALE_STATUS__tim_status__BITNR) \ -) - -#endif - -/* - * R_REC_COUNTERS - * - type: RO - * - addr: 0xb00000a4 - * - group: Network interface registers - */ - -#if USE_GROUP__Network_interface_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_REC_COUNTERS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_REC_COUNTERS(f1,v1,f2,v2,f3,v3,f4,v4) ( \ - (R_REC_COUNTERS__congestion__##f1##__MASK & REG__##v1) | \ - (R_REC_COUNTERS__oversize__##f2##__MASK & REG__##v2) | \ - (R_REC_COUNTERS__alignment_error__##f3##__MASK & REG__##v3) | \ - (R_REC_COUNTERS__crc_error__##f4##__MASK & REG__##v4) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_REC_COUNTERS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_REC_COUNTERS. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_REC_COUNTERS(f1,v1,f2,v2,f3,v3,f4,v4) ( \ - (R_REC_COUNTERS__congestion__##f1##__VAL(R_REC_COUNTERS_, congestion_, v1) << R_REC_COUNTERS__congestion__BITNR) | \ - (R_REC_COUNTERS__oversize__##f2##__VAL(R_REC_COUNTERS_, oversize_, v2) << R_REC_COUNTERS__oversize__BITNR) | \ - (R_REC_COUNTERS__alignment_error__##f3##__VAL(R_REC_COUNTERS_, alignment_error_, v3) << R_REC_COUNTERS__alignment_error__BITNR) | \ - (R_REC_COUNTERS__crc_error__##f4##__VAL(R_REC_COUNTERS_, crc_error_, v4) << R_REC_COUNTERS__crc_error__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_REC_COUNTERS_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_REC_COUNTERS. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_REC_COUNTERS_(f1_,v1,f2_,v2,f3_,v3,f4_,v4) ( \ - (R_REC_COUNTERS__congestion__##f1_##_VAL(R_REC_COUNTERS_, congestion_, v1) << R_REC_COUNTERS__congestion__BITNR) | \ - (R_REC_COUNTERS__oversize__##f2_##_VAL(R_REC_COUNTERS_, oversize_, v2) << R_REC_COUNTERS__oversize__BITNR) | \ - (R_REC_COUNTERS__alignment_error__##f3_##_VAL(R_REC_COUNTERS_, alignment_error_, v3) << R_REC_COUNTERS__alignment_error__BITNR) | \ - (R_REC_COUNTERS__crc_error__##f4_##_VAL(R_REC_COUNTERS_, crc_error_, v4) << R_REC_COUNTERS__crc_error__BITNR) \ -) - -#endif - -/* - * R_SCSI0_CMD - * - type: WO - * - addr: 0xb0000042 - * - group: SCSI registers - */ - -#if USE_GROUP__SCSI_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SCSI0_CMD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SCSI0_CMD. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_SCSI0_CMD. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SCSI0_CMD(f1,v1,f2,v2) ( \ - *R_SCSI0_CMD__SADDR = ( \ - REG_INITIATED(R_SCSI0_CMD_) \ - REG_VAL__R_SCSI0_CMD_(f1##_,v1,f2##_,v2) \ - ), \ - R_SCSI0_CMD__WRITE(R_SCSI0_CMD__ADDR, *R_SCSI0_CMD__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SCSI0_CMD__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SCSI0_CMD. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_SCSI0_CMD. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SCSI0_CMD__SHADOW(f1,v1,f2,v2) ( \ - *R_SCSI0_CMD__SADDR = ( \ - REG_INITIATED(R_SCSI0_CMD_) \ - REG_VAL__R_SCSI0_CMD_(f1##_,v1,f2##_,v2) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SCSI0_CMD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SCSI0_CMD(f1,v1,f2,v2) ( \ - (R_SCSI0_CMD__asynch_setup__##f1##__MASK & REG__##v1) | \ - (R_SCSI0_CMD__command__##f2##__MASK & REG__##v2) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SCSI0_CMD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SCSI0_CMD. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SCSI0_CMD(f1,v1,f2,v2) ( \ - (R_SCSI0_CMD__asynch_setup__##f1##__VAL(R_SCSI0_CMD_, asynch_setup_, v1) << R_SCSI0_CMD__asynch_setup__BITNR) | \ - (R_SCSI0_CMD__command__##f2##__VAL(R_SCSI0_CMD_, command_, v2) << R_SCSI0_CMD__command__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SCSI0_CMD_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SCSI0_CMD. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SCSI0_CMD_(f1_,v1,f2_,v2) ( \ - (R_SCSI0_CMD__asynch_setup__##f1_##_VAL(R_SCSI0_CMD_, asynch_setup_, v1) << R_SCSI0_CMD__asynch_setup__BITNR) | \ - (R_SCSI0_CMD__command__##f2_##_VAL(R_SCSI0_CMD_, command_, v2) << R_SCSI0_CMD__command__BITNR) \ -) - -#endif - -/* - * R_SCSI0_CMD_DATA - * - type: WO - * - addr: 0xb0000040 - * - group: SCSI registers - */ - -#if USE_GROUP__SCSI_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SCSI0_CMD_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SCSI0_CMD_DATA. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_SCSI0_CMD_DATA. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SCSI0_CMD_DATA(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \ - *R_SCSI0_CMD_DATA__SADDR = ( \ - REG_INITIATED(R_SCSI0_CMD_DATA_) \ - REG_VAL__R_SCSI0_CMD_DATA_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6) \ - ), \ - R_SCSI0_CMD_DATA__WRITE(R_SCSI0_CMD_DATA__ADDR, *R_SCSI0_CMD_DATA__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SCSI0_CMD_DATA__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SCSI0_CMD_DATA. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_SCSI0_CMD_DATA. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SCSI0_CMD_DATA__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \ - *R_SCSI0_CMD_DATA__SADDR = ( \ - REG_INITIATED(R_SCSI0_CMD_DATA_) \ - REG_VAL__R_SCSI0_CMD_DATA_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SCSI0_CMD_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SCSI0_CMD_DATA(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \ - (R_SCSI0_CMD_DATA__parity_in__##f1##__MASK & REG__##v1) | \ - (R_SCSI0_CMD_DATA__skip__##f2##__MASK & REG__##v2) | \ - (R_SCSI0_CMD_DATA__clr_status__##f3##__MASK & REG__##v3) | \ - (R_SCSI0_CMD_DATA__asynch_setup__##f4##__MASK & REG__##v4) | \ - (R_SCSI0_CMD_DATA__command__##f5##__MASK & REG__##v5) | \ - (R_SCSI0_CMD_DATA__data_out__##f6##__MASK & REG__##v6) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SCSI0_CMD_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SCSI0_CMD_DATA. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SCSI0_CMD_DATA(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \ - (R_SCSI0_CMD_DATA__parity_in__##f1##__VAL(R_SCSI0_CMD_DATA_, parity_in_, v1) << R_SCSI0_CMD_DATA__parity_in__BITNR) | \ - (R_SCSI0_CMD_DATA__skip__##f2##__VAL(R_SCSI0_CMD_DATA_, skip_, v2) << R_SCSI0_CMD_DATA__skip__BITNR) | \ - (R_SCSI0_CMD_DATA__clr_status__##f3##__VAL(R_SCSI0_CMD_DATA_, clr_status_, v3) << R_SCSI0_CMD_DATA__clr_status__BITNR) | \ - (R_SCSI0_CMD_DATA__asynch_setup__##f4##__VAL(R_SCSI0_CMD_DATA_, asynch_setup_, v4) << R_SCSI0_CMD_DATA__asynch_setup__BITNR) | \ - (R_SCSI0_CMD_DATA__command__##f5##__VAL(R_SCSI0_CMD_DATA_, command_, v5) << R_SCSI0_CMD_DATA__command__BITNR) | \ - (R_SCSI0_CMD_DATA__data_out__##f6##__VAL(R_SCSI0_CMD_DATA_, data_out_, v6) << R_SCSI0_CMD_DATA__data_out__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SCSI0_CMD_DATA_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SCSI0_CMD_DATA. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SCSI0_CMD_DATA_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6) ( \ - (R_SCSI0_CMD_DATA__parity_in__##f1_##_VAL(R_SCSI0_CMD_DATA_, parity_in_, v1) << R_SCSI0_CMD_DATA__parity_in__BITNR) | \ - (R_SCSI0_CMD_DATA__skip__##f2_##_VAL(R_SCSI0_CMD_DATA_, skip_, v2) << R_SCSI0_CMD_DATA__skip__BITNR) | \ - (R_SCSI0_CMD_DATA__clr_status__##f3_##_VAL(R_SCSI0_CMD_DATA_, clr_status_, v3) << R_SCSI0_CMD_DATA__clr_status__BITNR) | \ - (R_SCSI0_CMD_DATA__asynch_setup__##f4_##_VAL(R_SCSI0_CMD_DATA_, asynch_setup_, v4) << R_SCSI0_CMD_DATA__asynch_setup__BITNR) | \ - (R_SCSI0_CMD_DATA__command__##f5_##_VAL(R_SCSI0_CMD_DATA_, command_, v5) << R_SCSI0_CMD_DATA__command__BITNR) | \ - (R_SCSI0_CMD_DATA__data_out__##f6_##_VAL(R_SCSI0_CMD_DATA_, data_out_, v6) << R_SCSI0_CMD_DATA__data_out__BITNR) \ -) - -#endif - -/* - * R_SCSI0_CTRL - * - type: WO - * - addr: 0xb0000044 - * - group: SCSI registers - */ - -#if USE_GROUP__SCSI_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SCSI0_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SCSI0_CTRL. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_SCSI0_CTRL. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SCSI0_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11) ( \ - *R_SCSI0_CTRL__SADDR = ( \ - REG_INITIATED(R_SCSI0_CTRL_) \ - REG_VAL__R_SCSI0_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11) \ - ), \ - R_SCSI0_CTRL__WRITE(R_SCSI0_CTRL__ADDR, *R_SCSI0_CTRL__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SCSI0_CTRL__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SCSI0_CTRL. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_SCSI0_CTRL. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SCSI0_CTRL__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11) ( \ - *R_SCSI0_CTRL__SADDR = ( \ - REG_INITIATED(R_SCSI0_CTRL_) \ - REG_VAL__R_SCSI0_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SCSI0_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SCSI0_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11) ( \ - (R_SCSI0_CTRL__id_type__##f1##__MASK & REG__##v1) | \ - (R_SCSI0_CTRL__sel_timeout__##f2##__MASK & REG__##v2) | \ - (R_SCSI0_CTRL__synch_per__##f3##__MASK & REG__##v3) | \ - (R_SCSI0_CTRL__rst__##f4##__MASK & REG__##v4) | \ - (R_SCSI0_CTRL__atn__##f5##__MASK & REG__##v5) | \ - (R_SCSI0_CTRL__my_id__##f6##__MASK & REG__##v6) | \ - (R_SCSI0_CTRL__target_id__##f7##__MASK & REG__##v7) | \ - (R_SCSI0_CTRL__fast_20__##f8##__MASK & REG__##v8) | \ - (R_SCSI0_CTRL__bus_width__##f9##__MASK & REG__##v9) | \ - (R_SCSI0_CTRL__synch__##f10##__MASK & REG__##v10) | \ - (R_SCSI0_CTRL__enable__##f11##__MASK & REG__##v11) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SCSI0_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SCSI0_CTRL. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SCSI0_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11) ( \ - (R_SCSI0_CTRL__id_type__##f1##__VAL(R_SCSI0_CTRL_, id_type_, v1) << R_SCSI0_CTRL__id_type__BITNR) | \ - (R_SCSI0_CTRL__sel_timeout__##f2##__VAL(R_SCSI0_CTRL_, sel_timeout_, v2) << R_SCSI0_CTRL__sel_timeout__BITNR) | \ - (R_SCSI0_CTRL__synch_per__##f3##__VAL(R_SCSI0_CTRL_, synch_per_, v3) << R_SCSI0_CTRL__synch_per__BITNR) | \ - (R_SCSI0_CTRL__rst__##f4##__VAL(R_SCSI0_CTRL_, rst_, v4) << R_SCSI0_CTRL__rst__BITNR) | \ - (R_SCSI0_CTRL__atn__##f5##__VAL(R_SCSI0_CTRL_, atn_, v5) << R_SCSI0_CTRL__atn__BITNR) | \ - (R_SCSI0_CTRL__my_id__##f6##__VAL(R_SCSI0_CTRL_, my_id_, v6) << R_SCSI0_CTRL__my_id__BITNR) | \ - (R_SCSI0_CTRL__target_id__##f7##__VAL(R_SCSI0_CTRL_, target_id_, v7) << R_SCSI0_CTRL__target_id__BITNR) | \ - (R_SCSI0_CTRL__fast_20__##f8##__VAL(R_SCSI0_CTRL_, fast_20_, v8) << R_SCSI0_CTRL__fast_20__BITNR) | \ - (R_SCSI0_CTRL__bus_width__##f9##__VAL(R_SCSI0_CTRL_, bus_width_, v9) << R_SCSI0_CTRL__bus_width__BITNR) | \ - (R_SCSI0_CTRL__synch__##f10##__VAL(R_SCSI0_CTRL_, synch_, v10) << R_SCSI0_CTRL__synch__BITNR) | \ - (R_SCSI0_CTRL__enable__##f11##__VAL(R_SCSI0_CTRL_, enable_, v11) << R_SCSI0_CTRL__enable__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SCSI0_CTRL_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SCSI0_CTRL. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SCSI0_CTRL_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11) ( \ - (R_SCSI0_CTRL__id_type__##f1_##_VAL(R_SCSI0_CTRL_, id_type_, v1) << R_SCSI0_CTRL__id_type__BITNR) | \ - (R_SCSI0_CTRL__sel_timeout__##f2_##_VAL(R_SCSI0_CTRL_, sel_timeout_, v2) << R_SCSI0_CTRL__sel_timeout__BITNR) | \ - (R_SCSI0_CTRL__synch_per__##f3_##_VAL(R_SCSI0_CTRL_, synch_per_, v3) << R_SCSI0_CTRL__synch_per__BITNR) | \ - (R_SCSI0_CTRL__rst__##f4_##_VAL(R_SCSI0_CTRL_, rst_, v4) << R_SCSI0_CTRL__rst__BITNR) | \ - (R_SCSI0_CTRL__atn__##f5_##_VAL(R_SCSI0_CTRL_, atn_, v5) << R_SCSI0_CTRL__atn__BITNR) | \ - (R_SCSI0_CTRL__my_id__##f6_##_VAL(R_SCSI0_CTRL_, my_id_, v6) << R_SCSI0_CTRL__my_id__BITNR) | \ - (R_SCSI0_CTRL__target_id__##f7_##_VAL(R_SCSI0_CTRL_, target_id_, v7) << R_SCSI0_CTRL__target_id__BITNR) | \ - (R_SCSI0_CTRL__fast_20__##f8_##_VAL(R_SCSI0_CTRL_, fast_20_, v8) << R_SCSI0_CTRL__fast_20__BITNR) | \ - (R_SCSI0_CTRL__bus_width__##f9_##_VAL(R_SCSI0_CTRL_, bus_width_, v9) << R_SCSI0_CTRL__bus_width__BITNR) | \ - (R_SCSI0_CTRL__synch__##f10_##_VAL(R_SCSI0_CTRL_, synch_, v10) << R_SCSI0_CTRL__synch__BITNR) | \ - (R_SCSI0_CTRL__enable__##f11_##_VAL(R_SCSI0_CTRL_, enable_, v11) << R_SCSI0_CTRL__enable__BITNR) \ -) - -#endif - -/* - * R_SCSI0_DATA - * - type: WO - * - addr: 0xb0000040 - * - group: SCSI registers - */ - -#if USE_GROUP__SCSI_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SCSI0_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SCSI0_DATA. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_SCSI0_DATA. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SCSI0_DATA(f1,v1) ( \ - *R_SCSI0_DATA__SADDR = ( \ - REG_INITIATED(R_SCSI0_DATA_) \ - REG_VAL__R_SCSI0_DATA_(f1##_,v1) \ - ), \ - R_SCSI0_DATA__WRITE(R_SCSI0_DATA__ADDR, *R_SCSI0_DATA__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SCSI0_DATA__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SCSI0_DATA. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_SCSI0_DATA. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SCSI0_DATA__SHADOW(f1,v1) ( \ - *R_SCSI0_DATA__SADDR = ( \ - REG_INITIATED(R_SCSI0_DATA_) \ - REG_VAL__R_SCSI0_DATA_(f1##_,v1) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SCSI0_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SCSI0_DATA(f1,v1) ( \ - (R_SCSI0_DATA__data_out__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SCSI0_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SCSI0_DATA. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SCSI0_DATA(f1,v1) ( \ - (R_SCSI0_DATA__data_out__##f1##__VAL(R_SCSI0_DATA_, data_out_, v1) << R_SCSI0_DATA__data_out__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SCSI0_DATA_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SCSI0_DATA. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SCSI0_DATA_(f1_,v1) ( \ - (R_SCSI0_DATA__data_out__##f1_##_VAL(R_SCSI0_DATA_, data_out_, v1) << R_SCSI0_DATA__data_out__BITNR) \ -) - -#endif - -/* - * R_SCSI0_DATA_IN - * - type: RO - * - addr: 0xb0000040 - * - group: SCSI registers - */ - -#if USE_GROUP__SCSI_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SCSI0_DATA_IN -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SCSI0_DATA_IN(f1,v1) ( \ - (R_SCSI0_DATA_IN__data_in__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SCSI0_DATA_IN -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SCSI0_DATA_IN. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SCSI0_DATA_IN(f1,v1) ( \ - (R_SCSI0_DATA_IN__data_in__##f1##__VAL(R_SCSI0_DATA_IN_, data_in_, v1) << R_SCSI0_DATA_IN__data_in__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SCSI0_DATA_IN_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SCSI0_DATA_IN. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SCSI0_DATA_IN_(f1_,v1) ( \ - (R_SCSI0_DATA_IN__data_in__##f1_##_VAL(R_SCSI0_DATA_IN_, data_in_, v1) << R_SCSI0_DATA_IN__data_in__BITNR) \ -) - -#endif - -/* - * R_SCSI0_STATUS - * - type: RO - * - addr: 0xb0000048 - * - group: SCSI registers - */ - -#if USE_GROUP__SCSI_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SCSI0_STATUS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SCSI0_STATUS(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \ - (R_SCSI0_STATUS__tst_arb_won__##f1##__MASK & REG__##v1) | \ - (R_SCSI0_STATUS__tst_resel__##f2##__MASK & REG__##v2) | \ - (R_SCSI0_STATUS__parity_error__##f3##__MASK & REG__##v3) | \ - (R_SCSI0_STATUS__bus_reset__##f4##__MASK & REG__##v4) | \ - (R_SCSI0_STATUS__resel_target__##f5##__MASK & REG__##v5) | \ - (R_SCSI0_STATUS__resel__##f6##__MASK & REG__##v6) | \ - (R_SCSI0_STATUS__curr_phase__##f7##__MASK & REG__##v7) | \ - (R_SCSI0_STATUS__last_seq_step__##f8##__MASK & REG__##v8) | \ - (R_SCSI0_STATUS__valid_status__##f9##__MASK & REG__##v9) | \ - (R_SCSI0_STATUS__seq_status__##f10##__MASK & REG__##v10) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SCSI0_STATUS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SCSI0_STATUS. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SCSI0_STATUS(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \ - (R_SCSI0_STATUS__tst_arb_won__##f1##__VAL(R_SCSI0_STATUS_, tst_arb_won_, v1) << R_SCSI0_STATUS__tst_arb_won__BITNR) | \ - (R_SCSI0_STATUS__tst_resel__##f2##__VAL(R_SCSI0_STATUS_, tst_resel_, v2) << R_SCSI0_STATUS__tst_resel__BITNR) | \ - (R_SCSI0_STATUS__parity_error__##f3##__VAL(R_SCSI0_STATUS_, parity_error_, v3) << R_SCSI0_STATUS__parity_error__BITNR) | \ - (R_SCSI0_STATUS__bus_reset__##f4##__VAL(R_SCSI0_STATUS_, bus_reset_, v4) << R_SCSI0_STATUS__bus_reset__BITNR) | \ - (R_SCSI0_STATUS__resel_target__##f5##__VAL(R_SCSI0_STATUS_, resel_target_, v5) << R_SCSI0_STATUS__resel_target__BITNR) | \ - (R_SCSI0_STATUS__resel__##f6##__VAL(R_SCSI0_STATUS_, resel_, v6) << R_SCSI0_STATUS__resel__BITNR) | \ - (R_SCSI0_STATUS__curr_phase__##f7##__VAL(R_SCSI0_STATUS_, curr_phase_, v7) << R_SCSI0_STATUS__curr_phase__BITNR) | \ - (R_SCSI0_STATUS__last_seq_step__##f8##__VAL(R_SCSI0_STATUS_, last_seq_step_, v8) << R_SCSI0_STATUS__last_seq_step__BITNR) | \ - (R_SCSI0_STATUS__valid_status__##f9##__VAL(R_SCSI0_STATUS_, valid_status_, v9) << R_SCSI0_STATUS__valid_status__BITNR) | \ - (R_SCSI0_STATUS__seq_status__##f10##__VAL(R_SCSI0_STATUS_, seq_status_, v10) << R_SCSI0_STATUS__seq_status__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SCSI0_STATUS_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SCSI0_STATUS. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SCSI0_STATUS_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10) ( \ - (R_SCSI0_STATUS__tst_arb_won__##f1_##_VAL(R_SCSI0_STATUS_, tst_arb_won_, v1) << R_SCSI0_STATUS__tst_arb_won__BITNR) | \ - (R_SCSI0_STATUS__tst_resel__##f2_##_VAL(R_SCSI0_STATUS_, tst_resel_, v2) << R_SCSI0_STATUS__tst_resel__BITNR) | \ - (R_SCSI0_STATUS__parity_error__##f3_##_VAL(R_SCSI0_STATUS_, parity_error_, v3) << R_SCSI0_STATUS__parity_error__BITNR) | \ - (R_SCSI0_STATUS__bus_reset__##f4_##_VAL(R_SCSI0_STATUS_, bus_reset_, v4) << R_SCSI0_STATUS__bus_reset__BITNR) | \ - (R_SCSI0_STATUS__resel_target__##f5_##_VAL(R_SCSI0_STATUS_, resel_target_, v5) << R_SCSI0_STATUS__resel_target__BITNR) | \ - (R_SCSI0_STATUS__resel__##f6_##_VAL(R_SCSI0_STATUS_, resel_, v6) << R_SCSI0_STATUS__resel__BITNR) | \ - (R_SCSI0_STATUS__curr_phase__##f7_##_VAL(R_SCSI0_STATUS_, curr_phase_, v7) << R_SCSI0_STATUS__curr_phase__BITNR) | \ - (R_SCSI0_STATUS__last_seq_step__##f8_##_VAL(R_SCSI0_STATUS_, last_seq_step_, v8) << R_SCSI0_STATUS__last_seq_step__BITNR) | \ - (R_SCSI0_STATUS__valid_status__##f9_##_VAL(R_SCSI0_STATUS_, valid_status_, v9) << R_SCSI0_STATUS__valid_status__BITNR) | \ - (R_SCSI0_STATUS__seq_status__##f10_##_VAL(R_SCSI0_STATUS_, seq_status_, v10) << R_SCSI0_STATUS__seq_status__BITNR) \ -) - -#endif - -/* - * R_SCSI0_STATUS_CTRL - * - type: WO - * - addr: 0xb0000043 - * - group: SCSI registers - */ - -#if USE_GROUP__SCSI_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SCSI0_STATUS_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SCSI0_STATUS_CTRL. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_SCSI0_STATUS_CTRL. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SCSI0_STATUS_CTRL(f1,v1,f2,v2,f3,v3) ( \ - *R_SCSI0_STATUS_CTRL__SADDR = ( \ - REG_INITIATED(R_SCSI0_STATUS_CTRL_) \ - REG_VAL__R_SCSI0_STATUS_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3) \ - ), \ - R_SCSI0_STATUS_CTRL__WRITE(R_SCSI0_STATUS_CTRL__ADDR, *R_SCSI0_STATUS_CTRL__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SCSI0_STATUS_CTRL__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SCSI0_STATUS_CTRL. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_SCSI0_STATUS_CTRL. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SCSI0_STATUS_CTRL__SHADOW(f1,v1,f2,v2,f3,v3) ( \ - *R_SCSI0_STATUS_CTRL__SADDR = ( \ - REG_INITIATED(R_SCSI0_STATUS_CTRL_) \ - REG_VAL__R_SCSI0_STATUS_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SCSI0_STATUS_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SCSI0_STATUS_CTRL(f1,v1,f2,v2,f3,v3) ( \ - (R_SCSI0_STATUS_CTRL__parity_in__##f1##__MASK & REG__##v1) | \ - (R_SCSI0_STATUS_CTRL__skip__##f2##__MASK & REG__##v2) | \ - (R_SCSI0_STATUS_CTRL__clr_status__##f3##__MASK & REG__##v3) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SCSI0_STATUS_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SCSI0_STATUS_CTRL. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SCSI0_STATUS_CTRL(f1,v1,f2,v2,f3,v3) ( \ - (R_SCSI0_STATUS_CTRL__parity_in__##f1##__VAL(R_SCSI0_STATUS_CTRL_, parity_in_, v1) << R_SCSI0_STATUS_CTRL__parity_in__BITNR) | \ - (R_SCSI0_STATUS_CTRL__skip__##f2##__VAL(R_SCSI0_STATUS_CTRL_, skip_, v2) << R_SCSI0_STATUS_CTRL__skip__BITNR) | \ - (R_SCSI0_STATUS_CTRL__clr_status__##f3##__VAL(R_SCSI0_STATUS_CTRL_, clr_status_, v3) << R_SCSI0_STATUS_CTRL__clr_status__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SCSI0_STATUS_CTRL_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SCSI0_STATUS_CTRL. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SCSI0_STATUS_CTRL_(f1_,v1,f2_,v2,f3_,v3) ( \ - (R_SCSI0_STATUS_CTRL__parity_in__##f1_##_VAL(R_SCSI0_STATUS_CTRL_, parity_in_, v1) << R_SCSI0_STATUS_CTRL__parity_in__BITNR) | \ - (R_SCSI0_STATUS_CTRL__skip__##f2_##_VAL(R_SCSI0_STATUS_CTRL_, skip_, v2) << R_SCSI0_STATUS_CTRL__skip__BITNR) | \ - (R_SCSI0_STATUS_CTRL__clr_status__##f3_##_VAL(R_SCSI0_STATUS_CTRL_, clr_status_, v3) << R_SCSI0_STATUS_CTRL__clr_status__BITNR) \ -) - -#endif - -/* - * R_SCSI1_CMD - * - type: WO - * - addr: 0xb0000052 - * - group: SCSI registers - */ - -#if USE_GROUP__SCSI_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SCSI1_CMD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SCSI1_CMD. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_SCSI1_CMD. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SCSI1_CMD(f1,v1,f2,v2) ( \ - *R_SCSI1_CMD__SADDR = ( \ - REG_INITIATED(R_SCSI1_CMD_) \ - REG_VAL__R_SCSI1_CMD_(f1##_,v1,f2##_,v2) \ - ), \ - R_SCSI1_CMD__WRITE(R_SCSI1_CMD__ADDR, *R_SCSI1_CMD__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SCSI1_CMD__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SCSI1_CMD. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_SCSI1_CMD. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SCSI1_CMD__SHADOW(f1,v1,f2,v2) ( \ - *R_SCSI1_CMD__SADDR = ( \ - REG_INITIATED(R_SCSI1_CMD_) \ - REG_VAL__R_SCSI1_CMD_(f1##_,v1,f2##_,v2) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SCSI1_CMD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SCSI1_CMD(f1,v1,f2,v2) ( \ - (R_SCSI1_CMD__asynch_setup__##f1##__MASK & REG__##v1) | \ - (R_SCSI1_CMD__command__##f2##__MASK & REG__##v2) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SCSI1_CMD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SCSI1_CMD. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SCSI1_CMD(f1,v1,f2,v2) ( \ - (R_SCSI1_CMD__asynch_setup__##f1##__VAL(R_SCSI1_CMD_, asynch_setup_, v1) << R_SCSI1_CMD__asynch_setup__BITNR) | \ - (R_SCSI1_CMD__command__##f2##__VAL(R_SCSI1_CMD_, command_, v2) << R_SCSI1_CMD__command__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SCSI1_CMD_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SCSI1_CMD. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SCSI1_CMD_(f1_,v1,f2_,v2) ( \ - (R_SCSI1_CMD__asynch_setup__##f1_##_VAL(R_SCSI1_CMD_, asynch_setup_, v1) << R_SCSI1_CMD__asynch_setup__BITNR) | \ - (R_SCSI1_CMD__command__##f2_##_VAL(R_SCSI1_CMD_, command_, v2) << R_SCSI1_CMD__command__BITNR) \ -) - -#endif - -/* - * R_SCSI1_CMD_DATA - * - type: WO - * - addr: 0xb0000050 - * - group: SCSI registers - */ - -#if USE_GROUP__SCSI_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SCSI1_CMD_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SCSI1_CMD_DATA. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_SCSI1_CMD_DATA. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SCSI1_CMD_DATA(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \ - *R_SCSI1_CMD_DATA__SADDR = ( \ - REG_INITIATED(R_SCSI1_CMD_DATA_) \ - REG_VAL__R_SCSI1_CMD_DATA_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6) \ - ), \ - R_SCSI1_CMD_DATA__WRITE(R_SCSI1_CMD_DATA__ADDR, *R_SCSI1_CMD_DATA__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SCSI1_CMD_DATA__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SCSI1_CMD_DATA. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_SCSI1_CMD_DATA. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SCSI1_CMD_DATA__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \ - *R_SCSI1_CMD_DATA__SADDR = ( \ - REG_INITIATED(R_SCSI1_CMD_DATA_) \ - REG_VAL__R_SCSI1_CMD_DATA_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SCSI1_CMD_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SCSI1_CMD_DATA(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \ - (R_SCSI1_CMD_DATA__parity_in__##f1##__MASK & REG__##v1) | \ - (R_SCSI1_CMD_DATA__skip__##f2##__MASK & REG__##v2) | \ - (R_SCSI1_CMD_DATA__clr_status__##f3##__MASK & REG__##v3) | \ - (R_SCSI1_CMD_DATA__asynch_setup__##f4##__MASK & REG__##v4) | \ - (R_SCSI1_CMD_DATA__command__##f5##__MASK & REG__##v5) | \ - (R_SCSI1_CMD_DATA__data_out__##f6##__MASK & REG__##v6) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SCSI1_CMD_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SCSI1_CMD_DATA. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SCSI1_CMD_DATA(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \ - (R_SCSI1_CMD_DATA__parity_in__##f1##__VAL(R_SCSI1_CMD_DATA_, parity_in_, v1) << R_SCSI1_CMD_DATA__parity_in__BITNR) | \ - (R_SCSI1_CMD_DATA__skip__##f2##__VAL(R_SCSI1_CMD_DATA_, skip_, v2) << R_SCSI1_CMD_DATA__skip__BITNR) | \ - (R_SCSI1_CMD_DATA__clr_status__##f3##__VAL(R_SCSI1_CMD_DATA_, clr_status_, v3) << R_SCSI1_CMD_DATA__clr_status__BITNR) | \ - (R_SCSI1_CMD_DATA__asynch_setup__##f4##__VAL(R_SCSI1_CMD_DATA_, asynch_setup_, v4) << R_SCSI1_CMD_DATA__asynch_setup__BITNR) | \ - (R_SCSI1_CMD_DATA__command__##f5##__VAL(R_SCSI1_CMD_DATA_, command_, v5) << R_SCSI1_CMD_DATA__command__BITNR) | \ - (R_SCSI1_CMD_DATA__data_out__##f6##__VAL(R_SCSI1_CMD_DATA_, data_out_, v6) << R_SCSI1_CMD_DATA__data_out__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SCSI1_CMD_DATA_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SCSI1_CMD_DATA. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SCSI1_CMD_DATA_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6) ( \ - (R_SCSI1_CMD_DATA__parity_in__##f1_##_VAL(R_SCSI1_CMD_DATA_, parity_in_, v1) << R_SCSI1_CMD_DATA__parity_in__BITNR) | \ - (R_SCSI1_CMD_DATA__skip__##f2_##_VAL(R_SCSI1_CMD_DATA_, skip_, v2) << R_SCSI1_CMD_DATA__skip__BITNR) | \ - (R_SCSI1_CMD_DATA__clr_status__##f3_##_VAL(R_SCSI1_CMD_DATA_, clr_status_, v3) << R_SCSI1_CMD_DATA__clr_status__BITNR) | \ - (R_SCSI1_CMD_DATA__asynch_setup__##f4_##_VAL(R_SCSI1_CMD_DATA_, asynch_setup_, v4) << R_SCSI1_CMD_DATA__asynch_setup__BITNR) | \ - (R_SCSI1_CMD_DATA__command__##f5_##_VAL(R_SCSI1_CMD_DATA_, command_, v5) << R_SCSI1_CMD_DATA__command__BITNR) | \ - (R_SCSI1_CMD_DATA__data_out__##f6_##_VAL(R_SCSI1_CMD_DATA_, data_out_, v6) << R_SCSI1_CMD_DATA__data_out__BITNR) \ -) - -#endif - -/* - * R_SCSI1_CTRL - * - type: WO - * - addr: 0xb0000054 - * - group: SCSI registers - */ - -#if USE_GROUP__SCSI_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SCSI1_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SCSI1_CTRL. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_SCSI1_CTRL. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SCSI1_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11) ( \ - *R_SCSI1_CTRL__SADDR = ( \ - REG_INITIATED(R_SCSI1_CTRL_) \ - REG_VAL__R_SCSI1_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11) \ - ), \ - R_SCSI1_CTRL__WRITE(R_SCSI1_CTRL__ADDR, *R_SCSI1_CTRL__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SCSI1_CTRL__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SCSI1_CTRL. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_SCSI1_CTRL. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SCSI1_CTRL__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11) ( \ - *R_SCSI1_CTRL__SADDR = ( \ - REG_INITIATED(R_SCSI1_CTRL_) \ - REG_VAL__R_SCSI1_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SCSI1_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SCSI1_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11) ( \ - (R_SCSI1_CTRL__id_type__##f1##__MASK & REG__##v1) | \ - (R_SCSI1_CTRL__sel_timeout__##f2##__MASK & REG__##v2) | \ - (R_SCSI1_CTRL__synch_per__##f3##__MASK & REG__##v3) | \ - (R_SCSI1_CTRL__rst__##f4##__MASK & REG__##v4) | \ - (R_SCSI1_CTRL__atn__##f5##__MASK & REG__##v5) | \ - (R_SCSI1_CTRL__my_id__##f6##__MASK & REG__##v6) | \ - (R_SCSI1_CTRL__target_id__##f7##__MASK & REG__##v7) | \ - (R_SCSI1_CTRL__fast_20__##f8##__MASK & REG__##v8) | \ - (R_SCSI1_CTRL__bus_width__##f9##__MASK & REG__##v9) | \ - (R_SCSI1_CTRL__synch__##f10##__MASK & REG__##v10) | \ - (R_SCSI1_CTRL__enable__##f11##__MASK & REG__##v11) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SCSI1_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SCSI1_CTRL. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SCSI1_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11) ( \ - (R_SCSI1_CTRL__id_type__##f1##__VAL(R_SCSI1_CTRL_, id_type_, v1) << R_SCSI1_CTRL__id_type__BITNR) | \ - (R_SCSI1_CTRL__sel_timeout__##f2##__VAL(R_SCSI1_CTRL_, sel_timeout_, v2) << R_SCSI1_CTRL__sel_timeout__BITNR) | \ - (R_SCSI1_CTRL__synch_per__##f3##__VAL(R_SCSI1_CTRL_, synch_per_, v3) << R_SCSI1_CTRL__synch_per__BITNR) | \ - (R_SCSI1_CTRL__rst__##f4##__VAL(R_SCSI1_CTRL_, rst_, v4) << R_SCSI1_CTRL__rst__BITNR) | \ - (R_SCSI1_CTRL__atn__##f5##__VAL(R_SCSI1_CTRL_, atn_, v5) << R_SCSI1_CTRL__atn__BITNR) | \ - (R_SCSI1_CTRL__my_id__##f6##__VAL(R_SCSI1_CTRL_, my_id_, v6) << R_SCSI1_CTRL__my_id__BITNR) | \ - (R_SCSI1_CTRL__target_id__##f7##__VAL(R_SCSI1_CTRL_, target_id_, v7) << R_SCSI1_CTRL__target_id__BITNR) | \ - (R_SCSI1_CTRL__fast_20__##f8##__VAL(R_SCSI1_CTRL_, fast_20_, v8) << R_SCSI1_CTRL__fast_20__BITNR) | \ - (R_SCSI1_CTRL__bus_width__##f9##__VAL(R_SCSI1_CTRL_, bus_width_, v9) << R_SCSI1_CTRL__bus_width__BITNR) | \ - (R_SCSI1_CTRL__synch__##f10##__VAL(R_SCSI1_CTRL_, synch_, v10) << R_SCSI1_CTRL__synch__BITNR) | \ - (R_SCSI1_CTRL__enable__##f11##__VAL(R_SCSI1_CTRL_, enable_, v11) << R_SCSI1_CTRL__enable__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SCSI1_CTRL_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SCSI1_CTRL. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SCSI1_CTRL_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11) ( \ - (R_SCSI1_CTRL__id_type__##f1_##_VAL(R_SCSI1_CTRL_, id_type_, v1) << R_SCSI1_CTRL__id_type__BITNR) | \ - (R_SCSI1_CTRL__sel_timeout__##f2_##_VAL(R_SCSI1_CTRL_, sel_timeout_, v2) << R_SCSI1_CTRL__sel_timeout__BITNR) | \ - (R_SCSI1_CTRL__synch_per__##f3_##_VAL(R_SCSI1_CTRL_, synch_per_, v3) << R_SCSI1_CTRL__synch_per__BITNR) | \ - (R_SCSI1_CTRL__rst__##f4_##_VAL(R_SCSI1_CTRL_, rst_, v4) << R_SCSI1_CTRL__rst__BITNR) | \ - (R_SCSI1_CTRL__atn__##f5_##_VAL(R_SCSI1_CTRL_, atn_, v5) << R_SCSI1_CTRL__atn__BITNR) | \ - (R_SCSI1_CTRL__my_id__##f6_##_VAL(R_SCSI1_CTRL_, my_id_, v6) << R_SCSI1_CTRL__my_id__BITNR) | \ - (R_SCSI1_CTRL__target_id__##f7_##_VAL(R_SCSI1_CTRL_, target_id_, v7) << R_SCSI1_CTRL__target_id__BITNR) | \ - (R_SCSI1_CTRL__fast_20__##f8_##_VAL(R_SCSI1_CTRL_, fast_20_, v8) << R_SCSI1_CTRL__fast_20__BITNR) | \ - (R_SCSI1_CTRL__bus_width__##f9_##_VAL(R_SCSI1_CTRL_, bus_width_, v9) << R_SCSI1_CTRL__bus_width__BITNR) | \ - (R_SCSI1_CTRL__synch__##f10_##_VAL(R_SCSI1_CTRL_, synch_, v10) << R_SCSI1_CTRL__synch__BITNR) | \ - (R_SCSI1_CTRL__enable__##f11_##_VAL(R_SCSI1_CTRL_, enable_, v11) << R_SCSI1_CTRL__enable__BITNR) \ -) - -#endif - -/* - * R_SCSI1_DATA - * - type: WO - * - addr: 0xb0000050 - * - group: SCSI registers - */ - -#if USE_GROUP__SCSI_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SCSI1_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SCSI1_DATA. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_SCSI1_DATA. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SCSI1_DATA(f1,v1) ( \ - *R_SCSI1_DATA__SADDR = ( \ - REG_INITIATED(R_SCSI1_DATA_) \ - REG_VAL__R_SCSI1_DATA_(f1##_,v1) \ - ), \ - R_SCSI1_DATA__WRITE(R_SCSI1_DATA__ADDR, *R_SCSI1_DATA__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SCSI1_DATA__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SCSI1_DATA. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_SCSI1_DATA. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SCSI1_DATA__SHADOW(f1,v1) ( \ - *R_SCSI1_DATA__SADDR = ( \ - REG_INITIATED(R_SCSI1_DATA_) \ - REG_VAL__R_SCSI1_DATA_(f1##_,v1) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SCSI1_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SCSI1_DATA(f1,v1) ( \ - (R_SCSI1_DATA__data_out__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SCSI1_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SCSI1_DATA. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SCSI1_DATA(f1,v1) ( \ - (R_SCSI1_DATA__data_out__##f1##__VAL(R_SCSI1_DATA_, data_out_, v1) << R_SCSI1_DATA__data_out__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SCSI1_DATA_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SCSI1_DATA. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SCSI1_DATA_(f1_,v1) ( \ - (R_SCSI1_DATA__data_out__##f1_##_VAL(R_SCSI1_DATA_, data_out_, v1) << R_SCSI1_DATA__data_out__BITNR) \ -) - -#endif - -/* - * R_SCSI1_DATA_IN - * - type: RO - * - addr: 0xb0000050 - * - group: SCSI registers - */ - -#if USE_GROUP__SCSI_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SCSI1_DATA_IN -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SCSI1_DATA_IN(f1,v1) ( \ - (R_SCSI1_DATA_IN__data_in__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SCSI1_DATA_IN -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SCSI1_DATA_IN. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SCSI1_DATA_IN(f1,v1) ( \ - (R_SCSI1_DATA_IN__data_in__##f1##__VAL(R_SCSI1_DATA_IN_, data_in_, v1) << R_SCSI1_DATA_IN__data_in__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SCSI1_DATA_IN_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SCSI1_DATA_IN. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SCSI1_DATA_IN_(f1_,v1) ( \ - (R_SCSI1_DATA_IN__data_in__##f1_##_VAL(R_SCSI1_DATA_IN_, data_in_, v1) << R_SCSI1_DATA_IN__data_in__BITNR) \ -) - -#endif - -/* - * R_SCSI1_STATUS - * - type: RO - * - addr: 0xb0000058 - * - group: SCSI registers - */ - -#if USE_GROUP__SCSI_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SCSI1_STATUS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SCSI1_STATUS(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \ - (R_SCSI1_STATUS__tst_arb_won__##f1##__MASK & REG__##v1) | \ - (R_SCSI1_STATUS__tst_resel__##f2##__MASK & REG__##v2) | \ - (R_SCSI1_STATUS__parity_error__##f3##__MASK & REG__##v3) | \ - (R_SCSI1_STATUS__bus_reset__##f4##__MASK & REG__##v4) | \ - (R_SCSI1_STATUS__resel_target__##f5##__MASK & REG__##v5) | \ - (R_SCSI1_STATUS__resel__##f6##__MASK & REG__##v6) | \ - (R_SCSI1_STATUS__curr_phase__##f7##__MASK & REG__##v7) | \ - (R_SCSI1_STATUS__last_seq_step__##f8##__MASK & REG__##v8) | \ - (R_SCSI1_STATUS__valid_status__##f9##__MASK & REG__##v9) | \ - (R_SCSI1_STATUS__seq_status__##f10##__MASK & REG__##v10) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SCSI1_STATUS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SCSI1_STATUS. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SCSI1_STATUS(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \ - (R_SCSI1_STATUS__tst_arb_won__##f1##__VAL(R_SCSI1_STATUS_, tst_arb_won_, v1) << R_SCSI1_STATUS__tst_arb_won__BITNR) | \ - (R_SCSI1_STATUS__tst_resel__##f2##__VAL(R_SCSI1_STATUS_, tst_resel_, v2) << R_SCSI1_STATUS__tst_resel__BITNR) | \ - (R_SCSI1_STATUS__parity_error__##f3##__VAL(R_SCSI1_STATUS_, parity_error_, v3) << R_SCSI1_STATUS__parity_error__BITNR) | \ - (R_SCSI1_STATUS__bus_reset__##f4##__VAL(R_SCSI1_STATUS_, bus_reset_, v4) << R_SCSI1_STATUS__bus_reset__BITNR) | \ - (R_SCSI1_STATUS__resel_target__##f5##__VAL(R_SCSI1_STATUS_, resel_target_, v5) << R_SCSI1_STATUS__resel_target__BITNR) | \ - (R_SCSI1_STATUS__resel__##f6##__VAL(R_SCSI1_STATUS_, resel_, v6) << R_SCSI1_STATUS__resel__BITNR) | \ - (R_SCSI1_STATUS__curr_phase__##f7##__VAL(R_SCSI1_STATUS_, curr_phase_, v7) << R_SCSI1_STATUS__curr_phase__BITNR) | \ - (R_SCSI1_STATUS__last_seq_step__##f8##__VAL(R_SCSI1_STATUS_, last_seq_step_, v8) << R_SCSI1_STATUS__last_seq_step__BITNR) | \ - (R_SCSI1_STATUS__valid_status__##f9##__VAL(R_SCSI1_STATUS_, valid_status_, v9) << R_SCSI1_STATUS__valid_status__BITNR) | \ - (R_SCSI1_STATUS__seq_status__##f10##__VAL(R_SCSI1_STATUS_, seq_status_, v10) << R_SCSI1_STATUS__seq_status__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SCSI1_STATUS_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SCSI1_STATUS. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SCSI1_STATUS_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10) ( \ - (R_SCSI1_STATUS__tst_arb_won__##f1_##_VAL(R_SCSI1_STATUS_, tst_arb_won_, v1) << R_SCSI1_STATUS__tst_arb_won__BITNR) | \ - (R_SCSI1_STATUS__tst_resel__##f2_##_VAL(R_SCSI1_STATUS_, tst_resel_, v2) << R_SCSI1_STATUS__tst_resel__BITNR) | \ - (R_SCSI1_STATUS__parity_error__##f3_##_VAL(R_SCSI1_STATUS_, parity_error_, v3) << R_SCSI1_STATUS__parity_error__BITNR) | \ - (R_SCSI1_STATUS__bus_reset__##f4_##_VAL(R_SCSI1_STATUS_, bus_reset_, v4) << R_SCSI1_STATUS__bus_reset__BITNR) | \ - (R_SCSI1_STATUS__resel_target__##f5_##_VAL(R_SCSI1_STATUS_, resel_target_, v5) << R_SCSI1_STATUS__resel_target__BITNR) | \ - (R_SCSI1_STATUS__resel__##f6_##_VAL(R_SCSI1_STATUS_, resel_, v6) << R_SCSI1_STATUS__resel__BITNR) | \ - (R_SCSI1_STATUS__curr_phase__##f7_##_VAL(R_SCSI1_STATUS_, curr_phase_, v7) << R_SCSI1_STATUS__curr_phase__BITNR) | \ - (R_SCSI1_STATUS__last_seq_step__##f8_##_VAL(R_SCSI1_STATUS_, last_seq_step_, v8) << R_SCSI1_STATUS__last_seq_step__BITNR) | \ - (R_SCSI1_STATUS__valid_status__##f9_##_VAL(R_SCSI1_STATUS_, valid_status_, v9) << R_SCSI1_STATUS__valid_status__BITNR) | \ - (R_SCSI1_STATUS__seq_status__##f10_##_VAL(R_SCSI1_STATUS_, seq_status_, v10) << R_SCSI1_STATUS__seq_status__BITNR) \ -) - -#endif - -/* - * R_SCSI1_STATUS_CTRL - * - type: WO - * - addr: 0xb0000053 - * - group: SCSI registers - */ - -#if USE_GROUP__SCSI_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SCSI1_STATUS_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SCSI1_STATUS_CTRL. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_SCSI1_STATUS_CTRL. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SCSI1_STATUS_CTRL(f1,v1,f2,v2,f3,v3) ( \ - *R_SCSI1_STATUS_CTRL__SADDR = ( \ - REG_INITIATED(R_SCSI1_STATUS_CTRL_) \ - REG_VAL__R_SCSI1_STATUS_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3) \ - ), \ - R_SCSI1_STATUS_CTRL__WRITE(R_SCSI1_STATUS_CTRL__ADDR, *R_SCSI1_STATUS_CTRL__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SCSI1_STATUS_CTRL__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SCSI1_STATUS_CTRL. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_SCSI1_STATUS_CTRL. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SCSI1_STATUS_CTRL__SHADOW(f1,v1,f2,v2,f3,v3) ( \ - *R_SCSI1_STATUS_CTRL__SADDR = ( \ - REG_INITIATED(R_SCSI1_STATUS_CTRL_) \ - REG_VAL__R_SCSI1_STATUS_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SCSI1_STATUS_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SCSI1_STATUS_CTRL(f1,v1,f2,v2,f3,v3) ( \ - (R_SCSI1_STATUS_CTRL__parity_in__##f1##__MASK & REG__##v1) | \ - (R_SCSI1_STATUS_CTRL__skip__##f2##__MASK & REG__##v2) | \ - (R_SCSI1_STATUS_CTRL__clr_status__##f3##__MASK & REG__##v3) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SCSI1_STATUS_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SCSI1_STATUS_CTRL. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SCSI1_STATUS_CTRL(f1,v1,f2,v2,f3,v3) ( \ - (R_SCSI1_STATUS_CTRL__parity_in__##f1##__VAL(R_SCSI1_STATUS_CTRL_, parity_in_, v1) << R_SCSI1_STATUS_CTRL__parity_in__BITNR) | \ - (R_SCSI1_STATUS_CTRL__skip__##f2##__VAL(R_SCSI1_STATUS_CTRL_, skip_, v2) << R_SCSI1_STATUS_CTRL__skip__BITNR) | \ - (R_SCSI1_STATUS_CTRL__clr_status__##f3##__VAL(R_SCSI1_STATUS_CTRL_, clr_status_, v3) << R_SCSI1_STATUS_CTRL__clr_status__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SCSI1_STATUS_CTRL_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SCSI1_STATUS_CTRL. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SCSI1_STATUS_CTRL_(f1_,v1,f2_,v2,f3_,v3) ( \ - (R_SCSI1_STATUS_CTRL__parity_in__##f1_##_VAL(R_SCSI1_STATUS_CTRL_, parity_in_, v1) << R_SCSI1_STATUS_CTRL__parity_in__BITNR) | \ - (R_SCSI1_STATUS_CTRL__skip__##f2_##_VAL(R_SCSI1_STATUS_CTRL_, skip_, v2) << R_SCSI1_STATUS_CTRL__skip__BITNR) | \ - (R_SCSI1_STATUS_CTRL__clr_status__##f3_##_VAL(R_SCSI1_STATUS_CTRL_, clr_status_, v3) << R_SCSI1_STATUS_CTRL__clr_status__BITNR) \ -) - -#endif - -/* - * R_SDRAM_CONFIG - * - type: WO - * - addr: 0xb000000c - * - group: Bus interface configuration registers - */ - -#if USE_GROUP__Bus_interface_configuration_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SDRAM_CONFIG -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SDRAM_CONFIG. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_SDRAM_CONFIG. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SDRAM_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12) ( \ - *R_SDRAM_CONFIG__SADDR = ( \ - REG_INITIATED(R_SDRAM_CONFIG_) \ - REG_VAL__R_SDRAM_CONFIG_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12) \ - ), \ - R_SDRAM_CONFIG__WRITE(R_SDRAM_CONFIG__ADDR, *R_SDRAM_CONFIG__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SDRAM_CONFIG__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SDRAM_CONFIG. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_SDRAM_CONFIG. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SDRAM_CONFIG__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12) ( \ - *R_SDRAM_CONFIG__SADDR = ( \ - REG_INITIATED(R_SDRAM_CONFIG_) \ - REG_VAL__R_SDRAM_CONFIG_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SDRAM_CONFIG -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SDRAM_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12) ( \ - (R_SDRAM_CONFIG__wmm1__##f1##__MASK & REG__##v1) | \ - (R_SDRAM_CONFIG__wmm0__##f2##__MASK & REG__##v2) | \ - (R_SDRAM_CONFIG__sh1__##f3##__MASK & REG__##v3) | \ - (R_SDRAM_CONFIG__sh0__##f4##__MASK & REG__##v4) | \ - (R_SDRAM_CONFIG__w__##f5##__MASK & REG__##v5) | \ - (R_SDRAM_CONFIG__type1__##f6##__MASK & REG__##v6) | \ - (R_SDRAM_CONFIG__type0__##f7##__MASK & REG__##v7) | \ - (R_SDRAM_CONFIG__group_sel__##f8##__MASK & REG__##v8) | \ - (R_SDRAM_CONFIG__ca1__##f9##__MASK & REG__##v9) | \ - (R_SDRAM_CONFIG__bank_sel1__##f10##__MASK & REG__##v10) | \ - (R_SDRAM_CONFIG__ca0__##f11##__MASK & REG__##v11) | \ - (R_SDRAM_CONFIG__bank_sel0__##f12##__MASK & REG__##v12) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SDRAM_CONFIG -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SDRAM_CONFIG. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SDRAM_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12) ( \ - (R_SDRAM_CONFIG__wmm1__##f1##__VAL(R_SDRAM_CONFIG_, wmm1_, v1) << R_SDRAM_CONFIG__wmm1__BITNR) | \ - (R_SDRAM_CONFIG__wmm0__##f2##__VAL(R_SDRAM_CONFIG_, wmm0_, v2) << R_SDRAM_CONFIG__wmm0__BITNR) | \ - (R_SDRAM_CONFIG__sh1__##f3##__VAL(R_SDRAM_CONFIG_, sh1_, v3) << R_SDRAM_CONFIG__sh1__BITNR) | \ - (R_SDRAM_CONFIG__sh0__##f4##__VAL(R_SDRAM_CONFIG_, sh0_, v4) << R_SDRAM_CONFIG__sh0__BITNR) | \ - (R_SDRAM_CONFIG__w__##f5##__VAL(R_SDRAM_CONFIG_, w_, v5) << R_SDRAM_CONFIG__w__BITNR) | \ - (R_SDRAM_CONFIG__type1__##f6##__VAL(R_SDRAM_CONFIG_, type1_, v6) << R_SDRAM_CONFIG__type1__BITNR) | \ - (R_SDRAM_CONFIG__type0__##f7##__VAL(R_SDRAM_CONFIG_, type0_, v7) << R_SDRAM_CONFIG__type0__BITNR) | \ - (R_SDRAM_CONFIG__group_sel__##f8##__VAL(R_SDRAM_CONFIG_, group_sel_, v8) << R_SDRAM_CONFIG__group_sel__BITNR) | \ - (R_SDRAM_CONFIG__ca1__##f9##__VAL(R_SDRAM_CONFIG_, ca1_, v9) << R_SDRAM_CONFIG__ca1__BITNR) | \ - (R_SDRAM_CONFIG__bank_sel1__##f10##__VAL(R_SDRAM_CONFIG_, bank_sel1_, v10) << R_SDRAM_CONFIG__bank_sel1__BITNR) | \ - (R_SDRAM_CONFIG__ca0__##f11##__VAL(R_SDRAM_CONFIG_, ca0_, v11) << R_SDRAM_CONFIG__ca0__BITNR) | \ - (R_SDRAM_CONFIG__bank_sel0__##f12##__VAL(R_SDRAM_CONFIG_, bank_sel0_, v12) << R_SDRAM_CONFIG__bank_sel0__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SDRAM_CONFIG_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SDRAM_CONFIG. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SDRAM_CONFIG_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12) ( \ - (R_SDRAM_CONFIG__wmm1__##f1_##_VAL(R_SDRAM_CONFIG_, wmm1_, v1) << R_SDRAM_CONFIG__wmm1__BITNR) | \ - (R_SDRAM_CONFIG__wmm0__##f2_##_VAL(R_SDRAM_CONFIG_, wmm0_, v2) << R_SDRAM_CONFIG__wmm0__BITNR) | \ - (R_SDRAM_CONFIG__sh1__##f3_##_VAL(R_SDRAM_CONFIG_, sh1_, v3) << R_SDRAM_CONFIG__sh1__BITNR) | \ - (R_SDRAM_CONFIG__sh0__##f4_##_VAL(R_SDRAM_CONFIG_, sh0_, v4) << R_SDRAM_CONFIG__sh0__BITNR) | \ - (R_SDRAM_CONFIG__w__##f5_##_VAL(R_SDRAM_CONFIG_, w_, v5) << R_SDRAM_CONFIG__w__BITNR) | \ - (R_SDRAM_CONFIG__type1__##f6_##_VAL(R_SDRAM_CONFIG_, type1_, v6) << R_SDRAM_CONFIG__type1__BITNR) | \ - (R_SDRAM_CONFIG__type0__##f7_##_VAL(R_SDRAM_CONFIG_, type0_, v7) << R_SDRAM_CONFIG__type0__BITNR) | \ - (R_SDRAM_CONFIG__group_sel__##f8_##_VAL(R_SDRAM_CONFIG_, group_sel_, v8) << R_SDRAM_CONFIG__group_sel__BITNR) | \ - (R_SDRAM_CONFIG__ca1__##f9_##_VAL(R_SDRAM_CONFIG_, ca1_, v9) << R_SDRAM_CONFIG__ca1__BITNR) | \ - (R_SDRAM_CONFIG__bank_sel1__##f10_##_VAL(R_SDRAM_CONFIG_, bank_sel1_, v10) << R_SDRAM_CONFIG__bank_sel1__BITNR) | \ - (R_SDRAM_CONFIG__ca0__##f11_##_VAL(R_SDRAM_CONFIG_, ca0_, v11) << R_SDRAM_CONFIG__ca0__BITNR) | \ - (R_SDRAM_CONFIG__bank_sel0__##f12_##_VAL(R_SDRAM_CONFIG_, bank_sel0_, v12) << R_SDRAM_CONFIG__bank_sel0__BITNR) \ -) - -#endif - -/* - * R_SDRAM_TIMING - * - type: WO - * - addr: 0xb0000008 - * - group: Bus interface configuration registers - */ - -#if USE_GROUP__Bus_interface_configuration_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SDRAM_TIMING -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SDRAM_TIMING. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_SDRAM_TIMING. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SDRAM_TIMING(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12) ( \ - *R_SDRAM_TIMING__SADDR = ( \ - REG_INITIATED(R_SDRAM_TIMING_) \ - REG_VAL__R_SDRAM_TIMING_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12) \ - ), \ - R_SDRAM_TIMING__WRITE(R_SDRAM_TIMING__ADDR, *R_SDRAM_TIMING__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SDRAM_TIMING__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SDRAM_TIMING. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_SDRAM_TIMING. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SDRAM_TIMING__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12) ( \ - *R_SDRAM_TIMING__SADDR = ( \ - REG_INITIATED(R_SDRAM_TIMING_) \ - REG_VAL__R_SDRAM_TIMING_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SDRAM_TIMING -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SDRAM_TIMING(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12) ( \ - (R_SDRAM_TIMING__sdram__##f1##__MASK & REG__##v1) | \ - (R_SDRAM_TIMING__mrs_data__##f2##__MASK & REG__##v2) | \ - (R_SDRAM_TIMING__ref__##f3##__MASK & REG__##v3) | \ - (R_SDRAM_TIMING__ddr__##f4##__MASK & REG__##v4) | \ - (R_SDRAM_TIMING__clk100__##f5##__MASK & REG__##v5) | \ - (R_SDRAM_TIMING__ps__##f6##__MASK & REG__##v6) | \ - (R_SDRAM_TIMING__cmd__##f7##__MASK & REG__##v7) | \ - (R_SDRAM_TIMING__pde__##f8##__MASK & REG__##v8) | \ - (R_SDRAM_TIMING__rc__##f9##__MASK & REG__##v9) | \ - (R_SDRAM_TIMING__rp__##f10##__MASK & REG__##v10) | \ - (R_SDRAM_TIMING__rcd__##f11##__MASK & REG__##v11) | \ - (R_SDRAM_TIMING__cl__##f12##__MASK & REG__##v12) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SDRAM_TIMING -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SDRAM_TIMING. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SDRAM_TIMING(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12) ( \ - (R_SDRAM_TIMING__sdram__##f1##__VAL(R_SDRAM_TIMING_, sdram_, v1) << R_SDRAM_TIMING__sdram__BITNR) | \ - (R_SDRAM_TIMING__mrs_data__##f2##__VAL(R_SDRAM_TIMING_, mrs_data_, v2) << R_SDRAM_TIMING__mrs_data__BITNR) | \ - (R_SDRAM_TIMING__ref__##f3##__VAL(R_SDRAM_TIMING_, ref_, v3) << R_SDRAM_TIMING__ref__BITNR) | \ - (R_SDRAM_TIMING__ddr__##f4##__VAL(R_SDRAM_TIMING_, ddr_, v4) << R_SDRAM_TIMING__ddr__BITNR) | \ - (R_SDRAM_TIMING__clk100__##f5##__VAL(R_SDRAM_TIMING_, clk100_, v5) << R_SDRAM_TIMING__clk100__BITNR) | \ - (R_SDRAM_TIMING__ps__##f6##__VAL(R_SDRAM_TIMING_, ps_, v6) << R_SDRAM_TIMING__ps__BITNR) | \ - (R_SDRAM_TIMING__cmd__##f7##__VAL(R_SDRAM_TIMING_, cmd_, v7) << R_SDRAM_TIMING__cmd__BITNR) | \ - (R_SDRAM_TIMING__pde__##f8##__VAL(R_SDRAM_TIMING_, pde_, v8) << R_SDRAM_TIMING__pde__BITNR) | \ - (R_SDRAM_TIMING__rc__##f9##__VAL(R_SDRAM_TIMING_, rc_, v9) << R_SDRAM_TIMING__rc__BITNR) | \ - (R_SDRAM_TIMING__rp__##f10##__VAL(R_SDRAM_TIMING_, rp_, v10) << R_SDRAM_TIMING__rp__BITNR) | \ - (R_SDRAM_TIMING__rcd__##f11##__VAL(R_SDRAM_TIMING_, rcd_, v11) << R_SDRAM_TIMING__rcd__BITNR) | \ - (R_SDRAM_TIMING__cl__##f12##__VAL(R_SDRAM_TIMING_, cl_, v12) << R_SDRAM_TIMING__cl__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SDRAM_TIMING_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SDRAM_TIMING. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SDRAM_TIMING_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12) ( \ - (R_SDRAM_TIMING__sdram__##f1_##_VAL(R_SDRAM_TIMING_, sdram_, v1) << R_SDRAM_TIMING__sdram__BITNR) | \ - (R_SDRAM_TIMING__mrs_data__##f2_##_VAL(R_SDRAM_TIMING_, mrs_data_, v2) << R_SDRAM_TIMING__mrs_data__BITNR) | \ - (R_SDRAM_TIMING__ref__##f3_##_VAL(R_SDRAM_TIMING_, ref_, v3) << R_SDRAM_TIMING__ref__BITNR) | \ - (R_SDRAM_TIMING__ddr__##f4_##_VAL(R_SDRAM_TIMING_, ddr_, v4) << R_SDRAM_TIMING__ddr__BITNR) | \ - (R_SDRAM_TIMING__clk100__##f5_##_VAL(R_SDRAM_TIMING_, clk100_, v5) << R_SDRAM_TIMING__clk100__BITNR) | \ - (R_SDRAM_TIMING__ps__##f6_##_VAL(R_SDRAM_TIMING_, ps_, v6) << R_SDRAM_TIMING__ps__BITNR) | \ - (R_SDRAM_TIMING__cmd__##f7_##_VAL(R_SDRAM_TIMING_, cmd_, v7) << R_SDRAM_TIMING__cmd__BITNR) | \ - (R_SDRAM_TIMING__pde__##f8_##_VAL(R_SDRAM_TIMING_, pde_, v8) << R_SDRAM_TIMING__pde__BITNR) | \ - (R_SDRAM_TIMING__rc__##f9_##_VAL(R_SDRAM_TIMING_, rc_, v9) << R_SDRAM_TIMING__rc__BITNR) | \ - (R_SDRAM_TIMING__rp__##f10_##_VAL(R_SDRAM_TIMING_, rp_, v10) << R_SDRAM_TIMING__rp__BITNR) | \ - (R_SDRAM_TIMING__rcd__##f11_##_VAL(R_SDRAM_TIMING_, rcd_, v11) << R_SDRAM_TIMING__rcd__BITNR) | \ - (R_SDRAM_TIMING__cl__##f12_##_VAL(R_SDRAM_TIMING_, cl_, v12) << R_SDRAM_TIMING__cl__BITNR) \ -) - -#endif - -/* - * R_SERIAL0_BAUD - * - type: WO - * - addr: 0xb0000063 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SERIAL0_BAUD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SERIAL0_BAUD. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_SERIAL0_BAUD. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SERIAL0_BAUD(f1,v1,f2,v2) ( \ - *R_SERIAL0_BAUD__SADDR = ( \ - REG_INITIATED(R_SERIAL0_BAUD_) \ - REG_VAL__R_SERIAL0_BAUD_(f1##_,v1,f2##_,v2) \ - ), \ - R_SERIAL0_BAUD__WRITE(R_SERIAL0_BAUD__ADDR, *R_SERIAL0_BAUD__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SERIAL0_BAUD__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SERIAL0_BAUD. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_SERIAL0_BAUD. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SERIAL0_BAUD__SHADOW(f1,v1,f2,v2) ( \ - *R_SERIAL0_BAUD__SADDR = ( \ - REG_INITIATED(R_SERIAL0_BAUD_) \ - REG_VAL__R_SERIAL0_BAUD_(f1##_,v1,f2##_,v2) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SERIAL0_BAUD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SERIAL0_BAUD(f1,v1,f2,v2) ( \ - (R_SERIAL0_BAUD__tr_baud__##f1##__MASK & REG__##v1) | \ - (R_SERIAL0_BAUD__rec_baud__##f2##__MASK & REG__##v2) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL0_BAUD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL0_BAUD. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL0_BAUD(f1,v1,f2,v2) ( \ - (R_SERIAL0_BAUD__tr_baud__##f1##__VAL(R_SERIAL0_BAUD_, tr_baud_, v1) << R_SERIAL0_BAUD__tr_baud__BITNR) | \ - (R_SERIAL0_BAUD__rec_baud__##f2##__VAL(R_SERIAL0_BAUD_, rec_baud_, v2) << R_SERIAL0_BAUD__rec_baud__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL0_BAUD_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL0_BAUD. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL0_BAUD_(f1_,v1,f2_,v2) ( \ - (R_SERIAL0_BAUD__tr_baud__##f1_##_VAL(R_SERIAL0_BAUD_, tr_baud_, v1) << R_SERIAL0_BAUD__tr_baud__BITNR) | \ - (R_SERIAL0_BAUD__rec_baud__##f2_##_VAL(R_SERIAL0_BAUD_, rec_baud_, v2) << R_SERIAL0_BAUD__rec_baud__BITNR) \ -) - -#endif - -/* - * R_SERIAL0_CTRL - * - type: WO - * - addr: 0xb0000060 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SERIAL0_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SERIAL0_CTRL. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_SERIAL0_CTRL. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SERIAL0_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19) ( \ - *R_SERIAL0_CTRL__SADDR = ( \ - REG_INITIATED(R_SERIAL0_CTRL_) \ - REG_VAL__R_SERIAL0_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19) \ - ), \ - R_SERIAL0_CTRL__WRITE(R_SERIAL0_CTRL__ADDR, *R_SERIAL0_CTRL__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SERIAL0_CTRL__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SERIAL0_CTRL. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_SERIAL0_CTRL. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SERIAL0_CTRL__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19) ( \ - *R_SERIAL0_CTRL__SADDR = ( \ - REG_INITIATED(R_SERIAL0_CTRL_) \ - REG_VAL__R_SERIAL0_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SERIAL0_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SERIAL0_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19) ( \ - (R_SERIAL0_CTRL__tr_baud__##f1##__MASK & REG__##v1) | \ - (R_SERIAL0_CTRL__rec_baud__##f2##__MASK & REG__##v2) | \ - (R_SERIAL0_CTRL__dma_err__##f3##__MASK & REG__##v3) | \ - (R_SERIAL0_CTRL__rec_enable__##f4##__MASK & REG__##v4) | \ - (R_SERIAL0_CTRL__rts___##f5##__MASK & REG__##v5) | \ - (R_SERIAL0_CTRL__sampling__##f6##__MASK & REG__##v6) | \ - (R_SERIAL0_CTRL__rec_stick_par__##f7##__MASK & REG__##v7) | \ - (R_SERIAL0_CTRL__rec_par__##f8##__MASK & REG__##v8) | \ - (R_SERIAL0_CTRL__rec_par_en__##f9##__MASK & REG__##v9) | \ - (R_SERIAL0_CTRL__rec_bitnr__##f10##__MASK & REG__##v10) | \ - (R_SERIAL0_CTRL__txd__##f11##__MASK & REG__##v11) | \ - (R_SERIAL0_CTRL__tr_enable__##f12##__MASK & REG__##v12) | \ - (R_SERIAL0_CTRL__auto_cts__##f13##__MASK & REG__##v13) | \ - (R_SERIAL0_CTRL__stop_bits__##f14##__MASK & REG__##v14) | \ - (R_SERIAL0_CTRL__tr_stick_par__##f15##__MASK & REG__##v15) | \ - (R_SERIAL0_CTRL__tr_par__##f16##__MASK & REG__##v16) | \ - (R_SERIAL0_CTRL__tr_par_en__##f17##__MASK & REG__##v17) | \ - (R_SERIAL0_CTRL__tr_bitnr__##f18##__MASK & REG__##v18) | \ - (R_SERIAL0_CTRL__data_out__##f19##__MASK & REG__##v19) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL0_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL0_CTRL. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL0_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19) ( \ - (R_SERIAL0_CTRL__tr_baud__##f1##__VAL(R_SERIAL0_CTRL_, tr_baud_, v1) << R_SERIAL0_CTRL__tr_baud__BITNR) | \ - (R_SERIAL0_CTRL__rec_baud__##f2##__VAL(R_SERIAL0_CTRL_, rec_baud_, v2) << R_SERIAL0_CTRL__rec_baud__BITNR) | \ - (R_SERIAL0_CTRL__dma_err__##f3##__VAL(R_SERIAL0_CTRL_, dma_err_, v3) << R_SERIAL0_CTRL__dma_err__BITNR) | \ - (R_SERIAL0_CTRL__rec_enable__##f4##__VAL(R_SERIAL0_CTRL_, rec_enable_, v4) << R_SERIAL0_CTRL__rec_enable__BITNR) | \ - (R_SERIAL0_CTRL__rts___##f5##__VAL(R_SERIAL0_CTRL_, rts__, v5) << R_SERIAL0_CTRL__rts___BITNR) | \ - (R_SERIAL0_CTRL__sampling__##f6##__VAL(R_SERIAL0_CTRL_, sampling_, v6) << R_SERIAL0_CTRL__sampling__BITNR) | \ - (R_SERIAL0_CTRL__rec_stick_par__##f7##__VAL(R_SERIAL0_CTRL_, rec_stick_par_, v7) << R_SERIAL0_CTRL__rec_stick_par__BITNR) | \ - (R_SERIAL0_CTRL__rec_par__##f8##__VAL(R_SERIAL0_CTRL_, rec_par_, v8) << R_SERIAL0_CTRL__rec_par__BITNR) | \ - (R_SERIAL0_CTRL__rec_par_en__##f9##__VAL(R_SERIAL0_CTRL_, rec_par_en_, v9) << R_SERIAL0_CTRL__rec_par_en__BITNR) | \ - (R_SERIAL0_CTRL__rec_bitnr__##f10##__VAL(R_SERIAL0_CTRL_, rec_bitnr_, v10) << R_SERIAL0_CTRL__rec_bitnr__BITNR) | \ - (R_SERIAL0_CTRL__txd__##f11##__VAL(R_SERIAL0_CTRL_, txd_, v11) << R_SERIAL0_CTRL__txd__BITNR) | \ - (R_SERIAL0_CTRL__tr_enable__##f12##__VAL(R_SERIAL0_CTRL_, tr_enable_, v12) << R_SERIAL0_CTRL__tr_enable__BITNR) | \ - (R_SERIAL0_CTRL__auto_cts__##f13##__VAL(R_SERIAL0_CTRL_, auto_cts_, v13) << R_SERIAL0_CTRL__auto_cts__BITNR) | \ - (R_SERIAL0_CTRL__stop_bits__##f14##__VAL(R_SERIAL0_CTRL_, stop_bits_, v14) << R_SERIAL0_CTRL__stop_bits__BITNR) | \ - (R_SERIAL0_CTRL__tr_stick_par__##f15##__VAL(R_SERIAL0_CTRL_, tr_stick_par_, v15) << R_SERIAL0_CTRL__tr_stick_par__BITNR) | \ - (R_SERIAL0_CTRL__tr_par__##f16##__VAL(R_SERIAL0_CTRL_, tr_par_, v16) << R_SERIAL0_CTRL__tr_par__BITNR) | \ - (R_SERIAL0_CTRL__tr_par_en__##f17##__VAL(R_SERIAL0_CTRL_, tr_par_en_, v17) << R_SERIAL0_CTRL__tr_par_en__BITNR) | \ - (R_SERIAL0_CTRL__tr_bitnr__##f18##__VAL(R_SERIAL0_CTRL_, tr_bitnr_, v18) << R_SERIAL0_CTRL__tr_bitnr__BITNR) | \ - (R_SERIAL0_CTRL__data_out__##f19##__VAL(R_SERIAL0_CTRL_, data_out_, v19) << R_SERIAL0_CTRL__data_out__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL0_CTRL_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL0_CTRL. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL0_CTRL_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16,f17_,v17,f18_,v18,f19_,v19) ( \ - (R_SERIAL0_CTRL__tr_baud__##f1_##_VAL(R_SERIAL0_CTRL_, tr_baud_, v1) << R_SERIAL0_CTRL__tr_baud__BITNR) | \ - (R_SERIAL0_CTRL__rec_baud__##f2_##_VAL(R_SERIAL0_CTRL_, rec_baud_, v2) << R_SERIAL0_CTRL__rec_baud__BITNR) | \ - (R_SERIAL0_CTRL__dma_err__##f3_##_VAL(R_SERIAL0_CTRL_, dma_err_, v3) << R_SERIAL0_CTRL__dma_err__BITNR) | \ - (R_SERIAL0_CTRL__rec_enable__##f4_##_VAL(R_SERIAL0_CTRL_, rec_enable_, v4) << R_SERIAL0_CTRL__rec_enable__BITNR) | \ - (R_SERIAL0_CTRL__rts___##f5_##_VAL(R_SERIAL0_CTRL_, rts__, v5) << R_SERIAL0_CTRL__rts___BITNR) | \ - (R_SERIAL0_CTRL__sampling__##f6_##_VAL(R_SERIAL0_CTRL_, sampling_, v6) << R_SERIAL0_CTRL__sampling__BITNR) | \ - (R_SERIAL0_CTRL__rec_stick_par__##f7_##_VAL(R_SERIAL0_CTRL_, rec_stick_par_, v7) << R_SERIAL0_CTRL__rec_stick_par__BITNR) | \ - (R_SERIAL0_CTRL__rec_par__##f8_##_VAL(R_SERIAL0_CTRL_, rec_par_, v8) << R_SERIAL0_CTRL__rec_par__BITNR) | \ - (R_SERIAL0_CTRL__rec_par_en__##f9_##_VAL(R_SERIAL0_CTRL_, rec_par_en_, v9) << R_SERIAL0_CTRL__rec_par_en__BITNR) | \ - (R_SERIAL0_CTRL__rec_bitnr__##f10_##_VAL(R_SERIAL0_CTRL_, rec_bitnr_, v10) << R_SERIAL0_CTRL__rec_bitnr__BITNR) | \ - (R_SERIAL0_CTRL__txd__##f11_##_VAL(R_SERIAL0_CTRL_, txd_, v11) << R_SERIAL0_CTRL__txd__BITNR) | \ - (R_SERIAL0_CTRL__tr_enable__##f12_##_VAL(R_SERIAL0_CTRL_, tr_enable_, v12) << R_SERIAL0_CTRL__tr_enable__BITNR) | \ - (R_SERIAL0_CTRL__auto_cts__##f13_##_VAL(R_SERIAL0_CTRL_, auto_cts_, v13) << R_SERIAL0_CTRL__auto_cts__BITNR) | \ - (R_SERIAL0_CTRL__stop_bits__##f14_##_VAL(R_SERIAL0_CTRL_, stop_bits_, v14) << R_SERIAL0_CTRL__stop_bits__BITNR) | \ - (R_SERIAL0_CTRL__tr_stick_par__##f15_##_VAL(R_SERIAL0_CTRL_, tr_stick_par_, v15) << R_SERIAL0_CTRL__tr_stick_par__BITNR) | \ - (R_SERIAL0_CTRL__tr_par__##f16_##_VAL(R_SERIAL0_CTRL_, tr_par_, v16) << R_SERIAL0_CTRL__tr_par__BITNR) | \ - (R_SERIAL0_CTRL__tr_par_en__##f17_##_VAL(R_SERIAL0_CTRL_, tr_par_en_, v17) << R_SERIAL0_CTRL__tr_par_en__BITNR) | \ - (R_SERIAL0_CTRL__tr_bitnr__##f18_##_VAL(R_SERIAL0_CTRL_, tr_bitnr_, v18) << R_SERIAL0_CTRL__tr_bitnr__BITNR) | \ - (R_SERIAL0_CTRL__data_out__##f19_##_VAL(R_SERIAL0_CTRL_, data_out_, v19) << R_SERIAL0_CTRL__data_out__BITNR) \ -) - -#endif - -/* - * R_SERIAL0_READ - * - type: RO - * - addr: 0xb0000060 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SERIAL0_READ -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SERIAL0_READ(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \ - (R_SERIAL0_READ__xoff_detect__##f1##__MASK & REG__##v1) | \ - (R_SERIAL0_READ__cts___##f2##__MASK & REG__##v2) | \ - (R_SERIAL0_READ__tr_ready__##f3##__MASK & REG__##v3) | \ - (R_SERIAL0_READ__rxd__##f4##__MASK & REG__##v4) | \ - (R_SERIAL0_READ__overrun__##f5##__MASK & REG__##v5) | \ - (R_SERIAL0_READ__par_err__##f6##__MASK & REG__##v6) | \ - (R_SERIAL0_READ__framing_err__##f7##__MASK & REG__##v7) | \ - (R_SERIAL0_READ__data_avail__##f8##__MASK & REG__##v8) | \ - (R_SERIAL0_READ__data_in__##f9##__MASK & REG__##v9) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL0_READ -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL0_READ. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL0_READ(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \ - (R_SERIAL0_READ__xoff_detect__##f1##__VAL(R_SERIAL0_READ_, xoff_detect_, v1) << R_SERIAL0_READ__xoff_detect__BITNR) | \ - (R_SERIAL0_READ__cts___##f2##__VAL(R_SERIAL0_READ_, cts__, v2) << R_SERIAL0_READ__cts___BITNR) | \ - (R_SERIAL0_READ__tr_ready__##f3##__VAL(R_SERIAL0_READ_, tr_ready_, v3) << R_SERIAL0_READ__tr_ready__BITNR) | \ - (R_SERIAL0_READ__rxd__##f4##__VAL(R_SERIAL0_READ_, rxd_, v4) << R_SERIAL0_READ__rxd__BITNR) | \ - (R_SERIAL0_READ__overrun__##f5##__VAL(R_SERIAL0_READ_, overrun_, v5) << R_SERIAL0_READ__overrun__BITNR) | \ - (R_SERIAL0_READ__par_err__##f6##__VAL(R_SERIAL0_READ_, par_err_, v6) << R_SERIAL0_READ__par_err__BITNR) | \ - (R_SERIAL0_READ__framing_err__##f7##__VAL(R_SERIAL0_READ_, framing_err_, v7) << R_SERIAL0_READ__framing_err__BITNR) | \ - (R_SERIAL0_READ__data_avail__##f8##__VAL(R_SERIAL0_READ_, data_avail_, v8) << R_SERIAL0_READ__data_avail__BITNR) | \ - (R_SERIAL0_READ__data_in__##f9##__VAL(R_SERIAL0_READ_, data_in_, v9) << R_SERIAL0_READ__data_in__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL0_READ_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL0_READ. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL0_READ_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9) ( \ - (R_SERIAL0_READ__xoff_detect__##f1_##_VAL(R_SERIAL0_READ_, xoff_detect_, v1) << R_SERIAL0_READ__xoff_detect__BITNR) | \ - (R_SERIAL0_READ__cts___##f2_##_VAL(R_SERIAL0_READ_, cts__, v2) << R_SERIAL0_READ__cts___BITNR) | \ - (R_SERIAL0_READ__tr_ready__##f3_##_VAL(R_SERIAL0_READ_, tr_ready_, v3) << R_SERIAL0_READ__tr_ready__BITNR) | \ - (R_SERIAL0_READ__rxd__##f4_##_VAL(R_SERIAL0_READ_, rxd_, v4) << R_SERIAL0_READ__rxd__BITNR) | \ - (R_SERIAL0_READ__overrun__##f5_##_VAL(R_SERIAL0_READ_, overrun_, v5) << R_SERIAL0_READ__overrun__BITNR) | \ - (R_SERIAL0_READ__par_err__##f6_##_VAL(R_SERIAL0_READ_, par_err_, v6) << R_SERIAL0_READ__par_err__BITNR) | \ - (R_SERIAL0_READ__framing_err__##f7_##_VAL(R_SERIAL0_READ_, framing_err_, v7) << R_SERIAL0_READ__framing_err__BITNR) | \ - (R_SERIAL0_READ__data_avail__##f8_##_VAL(R_SERIAL0_READ_, data_avail_, v8) << R_SERIAL0_READ__data_avail__BITNR) | \ - (R_SERIAL0_READ__data_in__##f9_##_VAL(R_SERIAL0_READ_, data_in_, v9) << R_SERIAL0_READ__data_in__BITNR) \ -) - -#endif - -/* - * R_SERIAL0_REC_CTRL - * - type: WO - * - addr: 0xb0000062 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SERIAL0_REC_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SERIAL0_REC_CTRL. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_SERIAL0_REC_CTRL. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SERIAL0_REC_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - *R_SERIAL0_REC_CTRL__SADDR = ( \ - REG_INITIATED(R_SERIAL0_REC_CTRL_) \ - REG_VAL__R_SERIAL0_REC_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \ - ), \ - R_SERIAL0_REC_CTRL__WRITE(R_SERIAL0_REC_CTRL__ADDR, *R_SERIAL0_REC_CTRL__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SERIAL0_REC_CTRL__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SERIAL0_REC_CTRL. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_SERIAL0_REC_CTRL. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SERIAL0_REC_CTRL__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - *R_SERIAL0_REC_CTRL__SADDR = ( \ - REG_INITIATED(R_SERIAL0_REC_CTRL_) \ - REG_VAL__R_SERIAL0_REC_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SERIAL0_REC_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SERIAL0_REC_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - (R_SERIAL0_REC_CTRL__dma_err__##f1##__MASK & REG__##v1) | \ - (R_SERIAL0_REC_CTRL__rec_enable__##f2##__MASK & REG__##v2) | \ - (R_SERIAL0_REC_CTRL__rts___##f3##__MASK & REG__##v3) | \ - (R_SERIAL0_REC_CTRL__sampling__##f4##__MASK & REG__##v4) | \ - (R_SERIAL0_REC_CTRL__rec_stick_par__##f5##__MASK & REG__##v5) | \ - (R_SERIAL0_REC_CTRL__rec_par__##f6##__MASK & REG__##v6) | \ - (R_SERIAL0_REC_CTRL__rec_par_en__##f7##__MASK & REG__##v7) | \ - (R_SERIAL0_REC_CTRL__rec_bitnr__##f8##__MASK & REG__##v8) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL0_REC_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL0_REC_CTRL. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL0_REC_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - (R_SERIAL0_REC_CTRL__dma_err__##f1##__VAL(R_SERIAL0_REC_CTRL_, dma_err_, v1) << R_SERIAL0_REC_CTRL__dma_err__BITNR) | \ - (R_SERIAL0_REC_CTRL__rec_enable__##f2##__VAL(R_SERIAL0_REC_CTRL_, rec_enable_, v2) << R_SERIAL0_REC_CTRL__rec_enable__BITNR) | \ - (R_SERIAL0_REC_CTRL__rts___##f3##__VAL(R_SERIAL0_REC_CTRL_, rts__, v3) << R_SERIAL0_REC_CTRL__rts___BITNR) | \ - (R_SERIAL0_REC_CTRL__sampling__##f4##__VAL(R_SERIAL0_REC_CTRL_, sampling_, v4) << R_SERIAL0_REC_CTRL__sampling__BITNR) | \ - (R_SERIAL0_REC_CTRL__rec_stick_par__##f5##__VAL(R_SERIAL0_REC_CTRL_, rec_stick_par_, v5) << R_SERIAL0_REC_CTRL__rec_stick_par__BITNR) | \ - (R_SERIAL0_REC_CTRL__rec_par__##f6##__VAL(R_SERIAL0_REC_CTRL_, rec_par_, v6) << R_SERIAL0_REC_CTRL__rec_par__BITNR) | \ - (R_SERIAL0_REC_CTRL__rec_par_en__##f7##__VAL(R_SERIAL0_REC_CTRL_, rec_par_en_, v7) << R_SERIAL0_REC_CTRL__rec_par_en__BITNR) | \ - (R_SERIAL0_REC_CTRL__rec_bitnr__##f8##__VAL(R_SERIAL0_REC_CTRL_, rec_bitnr_, v8) << R_SERIAL0_REC_CTRL__rec_bitnr__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL0_REC_CTRL_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL0_REC_CTRL. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL0_REC_CTRL_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8) ( \ - (R_SERIAL0_REC_CTRL__dma_err__##f1_##_VAL(R_SERIAL0_REC_CTRL_, dma_err_, v1) << R_SERIAL0_REC_CTRL__dma_err__BITNR) | \ - (R_SERIAL0_REC_CTRL__rec_enable__##f2_##_VAL(R_SERIAL0_REC_CTRL_, rec_enable_, v2) << R_SERIAL0_REC_CTRL__rec_enable__BITNR) | \ - (R_SERIAL0_REC_CTRL__rts___##f3_##_VAL(R_SERIAL0_REC_CTRL_, rts__, v3) << R_SERIAL0_REC_CTRL__rts___BITNR) | \ - (R_SERIAL0_REC_CTRL__sampling__##f4_##_VAL(R_SERIAL0_REC_CTRL_, sampling_, v4) << R_SERIAL0_REC_CTRL__sampling__BITNR) | \ - (R_SERIAL0_REC_CTRL__rec_stick_par__##f5_##_VAL(R_SERIAL0_REC_CTRL_, rec_stick_par_, v5) << R_SERIAL0_REC_CTRL__rec_stick_par__BITNR) | \ - (R_SERIAL0_REC_CTRL__rec_par__##f6_##_VAL(R_SERIAL0_REC_CTRL_, rec_par_, v6) << R_SERIAL0_REC_CTRL__rec_par__BITNR) | \ - (R_SERIAL0_REC_CTRL__rec_par_en__##f7_##_VAL(R_SERIAL0_REC_CTRL_, rec_par_en_, v7) << R_SERIAL0_REC_CTRL__rec_par_en__BITNR) | \ - (R_SERIAL0_REC_CTRL__rec_bitnr__##f8_##_VAL(R_SERIAL0_REC_CTRL_, rec_bitnr_, v8) << R_SERIAL0_REC_CTRL__rec_bitnr__BITNR) \ -) - -#endif - -/* - * R_SERIAL0_REC_DATA - * - type: RO - * - addr: 0xb0000060 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SERIAL0_REC_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SERIAL0_REC_DATA(f1,v1) ( \ - (R_SERIAL0_REC_DATA__data_in__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL0_REC_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL0_REC_DATA. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL0_REC_DATA(f1,v1) ( \ - (R_SERIAL0_REC_DATA__data_in__##f1##__VAL(R_SERIAL0_REC_DATA_, data_in_, v1) << R_SERIAL0_REC_DATA__data_in__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL0_REC_DATA_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL0_REC_DATA. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL0_REC_DATA_(f1_,v1) ( \ - (R_SERIAL0_REC_DATA__data_in__##f1_##_VAL(R_SERIAL0_REC_DATA_, data_in_, v1) << R_SERIAL0_REC_DATA__data_in__BITNR) \ -) - -#endif - -/* - * R_SERIAL0_STATUS - * - type: RO - * - addr: 0xb0000061 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SERIAL0_STATUS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SERIAL0_STATUS(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - (R_SERIAL0_STATUS__xoff_detect__##f1##__MASK & REG__##v1) | \ - (R_SERIAL0_STATUS__cts___##f2##__MASK & REG__##v2) | \ - (R_SERIAL0_STATUS__tr_ready__##f3##__MASK & REG__##v3) | \ - (R_SERIAL0_STATUS__rxd__##f4##__MASK & REG__##v4) | \ - (R_SERIAL0_STATUS__overrun__##f5##__MASK & REG__##v5) | \ - (R_SERIAL0_STATUS__par_err__##f6##__MASK & REG__##v6) | \ - (R_SERIAL0_STATUS__framing_err__##f7##__MASK & REG__##v7) | \ - (R_SERIAL0_STATUS__data_avail__##f8##__MASK & REG__##v8) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL0_STATUS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL0_STATUS. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL0_STATUS(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - (R_SERIAL0_STATUS__xoff_detect__##f1##__VAL(R_SERIAL0_STATUS_, xoff_detect_, v1) << R_SERIAL0_STATUS__xoff_detect__BITNR) | \ - (R_SERIAL0_STATUS__cts___##f2##__VAL(R_SERIAL0_STATUS_, cts__, v2) << R_SERIAL0_STATUS__cts___BITNR) | \ - (R_SERIAL0_STATUS__tr_ready__##f3##__VAL(R_SERIAL0_STATUS_, tr_ready_, v3) << R_SERIAL0_STATUS__tr_ready__BITNR) | \ - (R_SERIAL0_STATUS__rxd__##f4##__VAL(R_SERIAL0_STATUS_, rxd_, v4) << R_SERIAL0_STATUS__rxd__BITNR) | \ - (R_SERIAL0_STATUS__overrun__##f5##__VAL(R_SERIAL0_STATUS_, overrun_, v5) << R_SERIAL0_STATUS__overrun__BITNR) | \ - (R_SERIAL0_STATUS__par_err__##f6##__VAL(R_SERIAL0_STATUS_, par_err_, v6) << R_SERIAL0_STATUS__par_err__BITNR) | \ - (R_SERIAL0_STATUS__framing_err__##f7##__VAL(R_SERIAL0_STATUS_, framing_err_, v7) << R_SERIAL0_STATUS__framing_err__BITNR) | \ - (R_SERIAL0_STATUS__data_avail__##f8##__VAL(R_SERIAL0_STATUS_, data_avail_, v8) << R_SERIAL0_STATUS__data_avail__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL0_STATUS_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL0_STATUS. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL0_STATUS_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8) ( \ - (R_SERIAL0_STATUS__xoff_detect__##f1_##_VAL(R_SERIAL0_STATUS_, xoff_detect_, v1) << R_SERIAL0_STATUS__xoff_detect__BITNR) | \ - (R_SERIAL0_STATUS__cts___##f2_##_VAL(R_SERIAL0_STATUS_, cts__, v2) << R_SERIAL0_STATUS__cts___BITNR) | \ - (R_SERIAL0_STATUS__tr_ready__##f3_##_VAL(R_SERIAL0_STATUS_, tr_ready_, v3) << R_SERIAL0_STATUS__tr_ready__BITNR) | \ - (R_SERIAL0_STATUS__rxd__##f4_##_VAL(R_SERIAL0_STATUS_, rxd_, v4) << R_SERIAL0_STATUS__rxd__BITNR) | \ - (R_SERIAL0_STATUS__overrun__##f5_##_VAL(R_SERIAL0_STATUS_, overrun_, v5) << R_SERIAL0_STATUS__overrun__BITNR) | \ - (R_SERIAL0_STATUS__par_err__##f6_##_VAL(R_SERIAL0_STATUS_, par_err_, v6) << R_SERIAL0_STATUS__par_err__BITNR) | \ - (R_SERIAL0_STATUS__framing_err__##f7_##_VAL(R_SERIAL0_STATUS_, framing_err_, v7) << R_SERIAL0_STATUS__framing_err__BITNR) | \ - (R_SERIAL0_STATUS__data_avail__##f8_##_VAL(R_SERIAL0_STATUS_, data_avail_, v8) << R_SERIAL0_STATUS__data_avail__BITNR) \ -) - -#endif - -/* - * R_SERIAL0_TR_CTRL - * - type: WO - * - addr: 0xb0000061 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SERIAL0_TR_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SERIAL0_TR_CTRL. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_SERIAL0_TR_CTRL. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SERIAL0_TR_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - *R_SERIAL0_TR_CTRL__SADDR = ( \ - REG_INITIATED(R_SERIAL0_TR_CTRL_) \ - REG_VAL__R_SERIAL0_TR_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \ - ), \ - R_SERIAL0_TR_CTRL__WRITE(R_SERIAL0_TR_CTRL__ADDR, *R_SERIAL0_TR_CTRL__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SERIAL0_TR_CTRL__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SERIAL0_TR_CTRL. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_SERIAL0_TR_CTRL. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SERIAL0_TR_CTRL__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - *R_SERIAL0_TR_CTRL__SADDR = ( \ - REG_INITIATED(R_SERIAL0_TR_CTRL_) \ - REG_VAL__R_SERIAL0_TR_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SERIAL0_TR_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SERIAL0_TR_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - (R_SERIAL0_TR_CTRL__txd__##f1##__MASK & REG__##v1) | \ - (R_SERIAL0_TR_CTRL__tr_enable__##f2##__MASK & REG__##v2) | \ - (R_SERIAL0_TR_CTRL__auto_cts__##f3##__MASK & REG__##v3) | \ - (R_SERIAL0_TR_CTRL__stop_bits__##f4##__MASK & REG__##v4) | \ - (R_SERIAL0_TR_CTRL__tr_stick_par__##f5##__MASK & REG__##v5) | \ - (R_SERIAL0_TR_CTRL__tr_par__##f6##__MASK & REG__##v6) | \ - (R_SERIAL0_TR_CTRL__tr_par_en__##f7##__MASK & REG__##v7) | \ - (R_SERIAL0_TR_CTRL__tr_bitnr__##f8##__MASK & REG__##v8) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL0_TR_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL0_TR_CTRL. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL0_TR_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - (R_SERIAL0_TR_CTRL__txd__##f1##__VAL(R_SERIAL0_TR_CTRL_, txd_, v1) << R_SERIAL0_TR_CTRL__txd__BITNR) | \ - (R_SERIAL0_TR_CTRL__tr_enable__##f2##__VAL(R_SERIAL0_TR_CTRL_, tr_enable_, v2) << R_SERIAL0_TR_CTRL__tr_enable__BITNR) | \ - (R_SERIAL0_TR_CTRL__auto_cts__##f3##__VAL(R_SERIAL0_TR_CTRL_, auto_cts_, v3) << R_SERIAL0_TR_CTRL__auto_cts__BITNR) | \ - (R_SERIAL0_TR_CTRL__stop_bits__##f4##__VAL(R_SERIAL0_TR_CTRL_, stop_bits_, v4) << R_SERIAL0_TR_CTRL__stop_bits__BITNR) | \ - (R_SERIAL0_TR_CTRL__tr_stick_par__##f5##__VAL(R_SERIAL0_TR_CTRL_, tr_stick_par_, v5) << R_SERIAL0_TR_CTRL__tr_stick_par__BITNR) | \ - (R_SERIAL0_TR_CTRL__tr_par__##f6##__VAL(R_SERIAL0_TR_CTRL_, tr_par_, v6) << R_SERIAL0_TR_CTRL__tr_par__BITNR) | \ - (R_SERIAL0_TR_CTRL__tr_par_en__##f7##__VAL(R_SERIAL0_TR_CTRL_, tr_par_en_, v7) << R_SERIAL0_TR_CTRL__tr_par_en__BITNR) | \ - (R_SERIAL0_TR_CTRL__tr_bitnr__##f8##__VAL(R_SERIAL0_TR_CTRL_, tr_bitnr_, v8) << R_SERIAL0_TR_CTRL__tr_bitnr__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL0_TR_CTRL_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL0_TR_CTRL. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL0_TR_CTRL_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8) ( \ - (R_SERIAL0_TR_CTRL__txd__##f1_##_VAL(R_SERIAL0_TR_CTRL_, txd_, v1) << R_SERIAL0_TR_CTRL__txd__BITNR) | \ - (R_SERIAL0_TR_CTRL__tr_enable__##f2_##_VAL(R_SERIAL0_TR_CTRL_, tr_enable_, v2) << R_SERIAL0_TR_CTRL__tr_enable__BITNR) | \ - (R_SERIAL0_TR_CTRL__auto_cts__##f3_##_VAL(R_SERIAL0_TR_CTRL_, auto_cts_, v3) << R_SERIAL0_TR_CTRL__auto_cts__BITNR) | \ - (R_SERIAL0_TR_CTRL__stop_bits__##f4_##_VAL(R_SERIAL0_TR_CTRL_, stop_bits_, v4) << R_SERIAL0_TR_CTRL__stop_bits__BITNR) | \ - (R_SERIAL0_TR_CTRL__tr_stick_par__##f5_##_VAL(R_SERIAL0_TR_CTRL_, tr_stick_par_, v5) << R_SERIAL0_TR_CTRL__tr_stick_par__BITNR) | \ - (R_SERIAL0_TR_CTRL__tr_par__##f6_##_VAL(R_SERIAL0_TR_CTRL_, tr_par_, v6) << R_SERIAL0_TR_CTRL__tr_par__BITNR) | \ - (R_SERIAL0_TR_CTRL__tr_par_en__##f7_##_VAL(R_SERIAL0_TR_CTRL_, tr_par_en_, v7) << R_SERIAL0_TR_CTRL__tr_par_en__BITNR) | \ - (R_SERIAL0_TR_CTRL__tr_bitnr__##f8_##_VAL(R_SERIAL0_TR_CTRL_, tr_bitnr_, v8) << R_SERIAL0_TR_CTRL__tr_bitnr__BITNR) \ -) - -#endif - -/* - * R_SERIAL0_TR_DATA - * - type: WO - * - addr: 0xb0000060 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SERIAL0_TR_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SERIAL0_TR_DATA. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_SERIAL0_TR_DATA. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SERIAL0_TR_DATA(f1,v1) ( \ - *R_SERIAL0_TR_DATA__SADDR = ( \ - REG_INITIATED(R_SERIAL0_TR_DATA_) \ - REG_VAL__R_SERIAL0_TR_DATA_(f1##_,v1) \ - ), \ - R_SERIAL0_TR_DATA__WRITE(R_SERIAL0_TR_DATA__ADDR, *R_SERIAL0_TR_DATA__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SERIAL0_TR_DATA__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SERIAL0_TR_DATA. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_SERIAL0_TR_DATA. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SERIAL0_TR_DATA__SHADOW(f1,v1) ( \ - *R_SERIAL0_TR_DATA__SADDR = ( \ - REG_INITIATED(R_SERIAL0_TR_DATA_) \ - REG_VAL__R_SERIAL0_TR_DATA_(f1##_,v1) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SERIAL0_TR_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SERIAL0_TR_DATA(f1,v1) ( \ - (R_SERIAL0_TR_DATA__data_out__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL0_TR_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL0_TR_DATA. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL0_TR_DATA(f1,v1) ( \ - (R_SERIAL0_TR_DATA__data_out__##f1##__VAL(R_SERIAL0_TR_DATA_, data_out_, v1) << R_SERIAL0_TR_DATA__data_out__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL0_TR_DATA_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL0_TR_DATA. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL0_TR_DATA_(f1_,v1) ( \ - (R_SERIAL0_TR_DATA__data_out__##f1_##_VAL(R_SERIAL0_TR_DATA_, data_out_, v1) << R_SERIAL0_TR_DATA__data_out__BITNR) \ -) - -#endif - -/* - * R_SERIAL0_XOFF - * - type: WO - * - addr: 0xb0000064 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SERIAL0_XOFF -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SERIAL0_XOFF. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_SERIAL0_XOFF. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SERIAL0_XOFF(f1,v1,f2,v2,f3,v3) ( \ - *R_SERIAL0_XOFF__SADDR = ( \ - REG_INITIATED(R_SERIAL0_XOFF_) \ - REG_VAL__R_SERIAL0_XOFF_(f1##_,v1,f2##_,v2,f3##_,v3) \ - ), \ - R_SERIAL0_XOFF__WRITE(R_SERIAL0_XOFF__ADDR, *R_SERIAL0_XOFF__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SERIAL0_XOFF__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SERIAL0_XOFF. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_SERIAL0_XOFF. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SERIAL0_XOFF__SHADOW(f1,v1,f2,v2,f3,v3) ( \ - *R_SERIAL0_XOFF__SADDR = ( \ - REG_INITIATED(R_SERIAL0_XOFF_) \ - REG_VAL__R_SERIAL0_XOFF_(f1##_,v1,f2##_,v2,f3##_,v3) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SERIAL0_XOFF -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SERIAL0_XOFF(f1,v1,f2,v2,f3,v3) ( \ - (R_SERIAL0_XOFF__tx_stop__##f1##__MASK & REG__##v1) | \ - (R_SERIAL0_XOFF__auto_xoff__##f2##__MASK & REG__##v2) | \ - (R_SERIAL0_XOFF__xoff_char__##f3##__MASK & REG__##v3) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL0_XOFF -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL0_XOFF. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL0_XOFF(f1,v1,f2,v2,f3,v3) ( \ - (R_SERIAL0_XOFF__tx_stop__##f1##__VAL(R_SERIAL0_XOFF_, tx_stop_, v1) << R_SERIAL0_XOFF__tx_stop__BITNR) | \ - (R_SERIAL0_XOFF__auto_xoff__##f2##__VAL(R_SERIAL0_XOFF_, auto_xoff_, v2) << R_SERIAL0_XOFF__auto_xoff__BITNR) | \ - (R_SERIAL0_XOFF__xoff_char__##f3##__VAL(R_SERIAL0_XOFF_, xoff_char_, v3) << R_SERIAL0_XOFF__xoff_char__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL0_XOFF_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL0_XOFF. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL0_XOFF_(f1_,v1,f2_,v2,f3_,v3) ( \ - (R_SERIAL0_XOFF__tx_stop__##f1_##_VAL(R_SERIAL0_XOFF_, tx_stop_, v1) << R_SERIAL0_XOFF__tx_stop__BITNR) | \ - (R_SERIAL0_XOFF__auto_xoff__##f2_##_VAL(R_SERIAL0_XOFF_, auto_xoff_, v2) << R_SERIAL0_XOFF__auto_xoff__BITNR) | \ - (R_SERIAL0_XOFF__xoff_char__##f3_##_VAL(R_SERIAL0_XOFF_, xoff_char_, v3) << R_SERIAL0_XOFF__xoff_char__BITNR) \ -) - -#endif - -/* - * R_SERIAL1_BAUD - * - type: WO - * - addr: 0xb000006b - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SERIAL1_BAUD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SERIAL1_BAUD. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_SERIAL1_BAUD. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SERIAL1_BAUD(f1,v1,f2,v2) ( \ - *R_SERIAL1_BAUD__SADDR = ( \ - REG_INITIATED(R_SERIAL1_BAUD_) \ - REG_VAL__R_SERIAL1_BAUD_(f1##_,v1,f2##_,v2) \ - ), \ - R_SERIAL1_BAUD__WRITE(R_SERIAL1_BAUD__ADDR, *R_SERIAL1_BAUD__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SERIAL1_BAUD__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SERIAL1_BAUD. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_SERIAL1_BAUD. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SERIAL1_BAUD__SHADOW(f1,v1,f2,v2) ( \ - *R_SERIAL1_BAUD__SADDR = ( \ - REG_INITIATED(R_SERIAL1_BAUD_) \ - REG_VAL__R_SERIAL1_BAUD_(f1##_,v1,f2##_,v2) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SERIAL1_BAUD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SERIAL1_BAUD(f1,v1,f2,v2) ( \ - (R_SERIAL1_BAUD__tr_baud__##f1##__MASK & REG__##v1) | \ - (R_SERIAL1_BAUD__rec_baud__##f2##__MASK & REG__##v2) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL1_BAUD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL1_BAUD. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL1_BAUD(f1,v1,f2,v2) ( \ - (R_SERIAL1_BAUD__tr_baud__##f1##__VAL(R_SERIAL1_BAUD_, tr_baud_, v1) << R_SERIAL1_BAUD__tr_baud__BITNR) | \ - (R_SERIAL1_BAUD__rec_baud__##f2##__VAL(R_SERIAL1_BAUD_, rec_baud_, v2) << R_SERIAL1_BAUD__rec_baud__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL1_BAUD_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL1_BAUD. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL1_BAUD_(f1_,v1,f2_,v2) ( \ - (R_SERIAL1_BAUD__tr_baud__##f1_##_VAL(R_SERIAL1_BAUD_, tr_baud_, v1) << R_SERIAL1_BAUD__tr_baud__BITNR) | \ - (R_SERIAL1_BAUD__rec_baud__##f2_##_VAL(R_SERIAL1_BAUD_, rec_baud_, v2) << R_SERIAL1_BAUD__rec_baud__BITNR) \ -) - -#endif - -/* - * R_SERIAL1_CTRL - * - type: WO - * - addr: 0xb0000068 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SERIAL1_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SERIAL1_CTRL. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_SERIAL1_CTRL. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SERIAL1_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19) ( \ - *R_SERIAL1_CTRL__SADDR = ( \ - REG_INITIATED(R_SERIAL1_CTRL_) \ - REG_VAL__R_SERIAL1_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19) \ - ), \ - R_SERIAL1_CTRL__WRITE(R_SERIAL1_CTRL__ADDR, *R_SERIAL1_CTRL__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SERIAL1_CTRL__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SERIAL1_CTRL. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_SERIAL1_CTRL. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SERIAL1_CTRL__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19) ( \ - *R_SERIAL1_CTRL__SADDR = ( \ - REG_INITIATED(R_SERIAL1_CTRL_) \ - REG_VAL__R_SERIAL1_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SERIAL1_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SERIAL1_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19) ( \ - (R_SERIAL1_CTRL__tr_baud__##f1##__MASK & REG__##v1) | \ - (R_SERIAL1_CTRL__rec_baud__##f2##__MASK & REG__##v2) | \ - (R_SERIAL1_CTRL__dma_err__##f3##__MASK & REG__##v3) | \ - (R_SERIAL1_CTRL__rec_enable__##f4##__MASK & REG__##v4) | \ - (R_SERIAL1_CTRL__rts___##f5##__MASK & REG__##v5) | \ - (R_SERIAL1_CTRL__sampling__##f6##__MASK & REG__##v6) | \ - (R_SERIAL1_CTRL__rec_stick_par__##f7##__MASK & REG__##v7) | \ - (R_SERIAL1_CTRL__rec_par__##f8##__MASK & REG__##v8) | \ - (R_SERIAL1_CTRL__rec_par_en__##f9##__MASK & REG__##v9) | \ - (R_SERIAL1_CTRL__rec_bitnr__##f10##__MASK & REG__##v10) | \ - (R_SERIAL1_CTRL__txd__##f11##__MASK & REG__##v11) | \ - (R_SERIAL1_CTRL__tr_enable__##f12##__MASK & REG__##v12) | \ - (R_SERIAL1_CTRL__auto_cts__##f13##__MASK & REG__##v13) | \ - (R_SERIAL1_CTRL__stop_bits__##f14##__MASK & REG__##v14) | \ - (R_SERIAL1_CTRL__tr_stick_par__##f15##__MASK & REG__##v15) | \ - (R_SERIAL1_CTRL__tr_par__##f16##__MASK & REG__##v16) | \ - (R_SERIAL1_CTRL__tr_par_en__##f17##__MASK & REG__##v17) | \ - (R_SERIAL1_CTRL__tr_bitnr__##f18##__MASK & REG__##v18) | \ - (R_SERIAL1_CTRL__data_out__##f19##__MASK & REG__##v19) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL1_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL1_CTRL. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL1_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19) ( \ - (R_SERIAL1_CTRL__tr_baud__##f1##__VAL(R_SERIAL1_CTRL_, tr_baud_, v1) << R_SERIAL1_CTRL__tr_baud__BITNR) | \ - (R_SERIAL1_CTRL__rec_baud__##f2##__VAL(R_SERIAL1_CTRL_, rec_baud_, v2) << R_SERIAL1_CTRL__rec_baud__BITNR) | \ - (R_SERIAL1_CTRL__dma_err__##f3##__VAL(R_SERIAL1_CTRL_, dma_err_, v3) << R_SERIAL1_CTRL__dma_err__BITNR) | \ - (R_SERIAL1_CTRL__rec_enable__##f4##__VAL(R_SERIAL1_CTRL_, rec_enable_, v4) << R_SERIAL1_CTRL__rec_enable__BITNR) | \ - (R_SERIAL1_CTRL__rts___##f5##__VAL(R_SERIAL1_CTRL_, rts__, v5) << R_SERIAL1_CTRL__rts___BITNR) | \ - (R_SERIAL1_CTRL__sampling__##f6##__VAL(R_SERIAL1_CTRL_, sampling_, v6) << R_SERIAL1_CTRL__sampling__BITNR) | \ - (R_SERIAL1_CTRL__rec_stick_par__##f7##__VAL(R_SERIAL1_CTRL_, rec_stick_par_, v7) << R_SERIAL1_CTRL__rec_stick_par__BITNR) | \ - (R_SERIAL1_CTRL__rec_par__##f8##__VAL(R_SERIAL1_CTRL_, rec_par_, v8) << R_SERIAL1_CTRL__rec_par__BITNR) | \ - (R_SERIAL1_CTRL__rec_par_en__##f9##__VAL(R_SERIAL1_CTRL_, rec_par_en_, v9) << R_SERIAL1_CTRL__rec_par_en__BITNR) | \ - (R_SERIAL1_CTRL__rec_bitnr__##f10##__VAL(R_SERIAL1_CTRL_, rec_bitnr_, v10) << R_SERIAL1_CTRL__rec_bitnr__BITNR) | \ - (R_SERIAL1_CTRL__txd__##f11##__VAL(R_SERIAL1_CTRL_, txd_, v11) << R_SERIAL1_CTRL__txd__BITNR) | \ - (R_SERIAL1_CTRL__tr_enable__##f12##__VAL(R_SERIAL1_CTRL_, tr_enable_, v12) << R_SERIAL1_CTRL__tr_enable__BITNR) | \ - (R_SERIAL1_CTRL__auto_cts__##f13##__VAL(R_SERIAL1_CTRL_, auto_cts_, v13) << R_SERIAL1_CTRL__auto_cts__BITNR) | \ - (R_SERIAL1_CTRL__stop_bits__##f14##__VAL(R_SERIAL1_CTRL_, stop_bits_, v14) << R_SERIAL1_CTRL__stop_bits__BITNR) | \ - (R_SERIAL1_CTRL__tr_stick_par__##f15##__VAL(R_SERIAL1_CTRL_, tr_stick_par_, v15) << R_SERIAL1_CTRL__tr_stick_par__BITNR) | \ - (R_SERIAL1_CTRL__tr_par__##f16##__VAL(R_SERIAL1_CTRL_, tr_par_, v16) << R_SERIAL1_CTRL__tr_par__BITNR) | \ - (R_SERIAL1_CTRL__tr_par_en__##f17##__VAL(R_SERIAL1_CTRL_, tr_par_en_, v17) << R_SERIAL1_CTRL__tr_par_en__BITNR) | \ - (R_SERIAL1_CTRL__tr_bitnr__##f18##__VAL(R_SERIAL1_CTRL_, tr_bitnr_, v18) << R_SERIAL1_CTRL__tr_bitnr__BITNR) | \ - (R_SERIAL1_CTRL__data_out__##f19##__VAL(R_SERIAL1_CTRL_, data_out_, v19) << R_SERIAL1_CTRL__data_out__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL1_CTRL_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL1_CTRL. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL1_CTRL_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16,f17_,v17,f18_,v18,f19_,v19) ( \ - (R_SERIAL1_CTRL__tr_baud__##f1_##_VAL(R_SERIAL1_CTRL_, tr_baud_, v1) << R_SERIAL1_CTRL__tr_baud__BITNR) | \ - (R_SERIAL1_CTRL__rec_baud__##f2_##_VAL(R_SERIAL1_CTRL_, rec_baud_, v2) << R_SERIAL1_CTRL__rec_baud__BITNR) | \ - (R_SERIAL1_CTRL__dma_err__##f3_##_VAL(R_SERIAL1_CTRL_, dma_err_, v3) << R_SERIAL1_CTRL__dma_err__BITNR) | \ - (R_SERIAL1_CTRL__rec_enable__##f4_##_VAL(R_SERIAL1_CTRL_, rec_enable_, v4) << R_SERIAL1_CTRL__rec_enable__BITNR) | \ - (R_SERIAL1_CTRL__rts___##f5_##_VAL(R_SERIAL1_CTRL_, rts__, v5) << R_SERIAL1_CTRL__rts___BITNR) | \ - (R_SERIAL1_CTRL__sampling__##f6_##_VAL(R_SERIAL1_CTRL_, sampling_, v6) << R_SERIAL1_CTRL__sampling__BITNR) | \ - (R_SERIAL1_CTRL__rec_stick_par__##f7_##_VAL(R_SERIAL1_CTRL_, rec_stick_par_, v7) << R_SERIAL1_CTRL__rec_stick_par__BITNR) | \ - (R_SERIAL1_CTRL__rec_par__##f8_##_VAL(R_SERIAL1_CTRL_, rec_par_, v8) << R_SERIAL1_CTRL__rec_par__BITNR) | \ - (R_SERIAL1_CTRL__rec_par_en__##f9_##_VAL(R_SERIAL1_CTRL_, rec_par_en_, v9) << R_SERIAL1_CTRL__rec_par_en__BITNR) | \ - (R_SERIAL1_CTRL__rec_bitnr__##f10_##_VAL(R_SERIAL1_CTRL_, rec_bitnr_, v10) << R_SERIAL1_CTRL__rec_bitnr__BITNR) | \ - (R_SERIAL1_CTRL__txd__##f11_##_VAL(R_SERIAL1_CTRL_, txd_, v11) << R_SERIAL1_CTRL__txd__BITNR) | \ - (R_SERIAL1_CTRL__tr_enable__##f12_##_VAL(R_SERIAL1_CTRL_, tr_enable_, v12) << R_SERIAL1_CTRL__tr_enable__BITNR) | \ - (R_SERIAL1_CTRL__auto_cts__##f13_##_VAL(R_SERIAL1_CTRL_, auto_cts_, v13) << R_SERIAL1_CTRL__auto_cts__BITNR) | \ - (R_SERIAL1_CTRL__stop_bits__##f14_##_VAL(R_SERIAL1_CTRL_, stop_bits_, v14) << R_SERIAL1_CTRL__stop_bits__BITNR) | \ - (R_SERIAL1_CTRL__tr_stick_par__##f15_##_VAL(R_SERIAL1_CTRL_, tr_stick_par_, v15) << R_SERIAL1_CTRL__tr_stick_par__BITNR) | \ - (R_SERIAL1_CTRL__tr_par__##f16_##_VAL(R_SERIAL1_CTRL_, tr_par_, v16) << R_SERIAL1_CTRL__tr_par__BITNR) | \ - (R_SERIAL1_CTRL__tr_par_en__##f17_##_VAL(R_SERIAL1_CTRL_, tr_par_en_, v17) << R_SERIAL1_CTRL__tr_par_en__BITNR) | \ - (R_SERIAL1_CTRL__tr_bitnr__##f18_##_VAL(R_SERIAL1_CTRL_, tr_bitnr_, v18) << R_SERIAL1_CTRL__tr_bitnr__BITNR) | \ - (R_SERIAL1_CTRL__data_out__##f19_##_VAL(R_SERIAL1_CTRL_, data_out_, v19) << R_SERIAL1_CTRL__data_out__BITNR) \ -) - -#endif - -/* - * R_SERIAL1_READ - * - type: RO - * - addr: 0xb0000068 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SERIAL1_READ -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SERIAL1_READ(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \ - (R_SERIAL1_READ__xoff_detect__##f1##__MASK & REG__##v1) | \ - (R_SERIAL1_READ__cts___##f2##__MASK & REG__##v2) | \ - (R_SERIAL1_READ__tr_ready__##f3##__MASK & REG__##v3) | \ - (R_SERIAL1_READ__rxd__##f4##__MASK & REG__##v4) | \ - (R_SERIAL1_READ__overrun__##f5##__MASK & REG__##v5) | \ - (R_SERIAL1_READ__par_err__##f6##__MASK & REG__##v6) | \ - (R_SERIAL1_READ__framing_err__##f7##__MASK & REG__##v7) | \ - (R_SERIAL1_READ__data_avail__##f8##__MASK & REG__##v8) | \ - (R_SERIAL1_READ__data_in__##f9##__MASK & REG__##v9) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL1_READ -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL1_READ. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL1_READ(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \ - (R_SERIAL1_READ__xoff_detect__##f1##__VAL(R_SERIAL1_READ_, xoff_detect_, v1) << R_SERIAL1_READ__xoff_detect__BITNR) | \ - (R_SERIAL1_READ__cts___##f2##__VAL(R_SERIAL1_READ_, cts__, v2) << R_SERIAL1_READ__cts___BITNR) | \ - (R_SERIAL1_READ__tr_ready__##f3##__VAL(R_SERIAL1_READ_, tr_ready_, v3) << R_SERIAL1_READ__tr_ready__BITNR) | \ - (R_SERIAL1_READ__rxd__##f4##__VAL(R_SERIAL1_READ_, rxd_, v4) << R_SERIAL1_READ__rxd__BITNR) | \ - (R_SERIAL1_READ__overrun__##f5##__VAL(R_SERIAL1_READ_, overrun_, v5) << R_SERIAL1_READ__overrun__BITNR) | \ - (R_SERIAL1_READ__par_err__##f6##__VAL(R_SERIAL1_READ_, par_err_, v6) << R_SERIAL1_READ__par_err__BITNR) | \ - (R_SERIAL1_READ__framing_err__##f7##__VAL(R_SERIAL1_READ_, framing_err_, v7) << R_SERIAL1_READ__framing_err__BITNR) | \ - (R_SERIAL1_READ__data_avail__##f8##__VAL(R_SERIAL1_READ_, data_avail_, v8) << R_SERIAL1_READ__data_avail__BITNR) | \ - (R_SERIAL1_READ__data_in__##f9##__VAL(R_SERIAL1_READ_, data_in_, v9) << R_SERIAL1_READ__data_in__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL1_READ_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL1_READ. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL1_READ_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9) ( \ - (R_SERIAL1_READ__xoff_detect__##f1_##_VAL(R_SERIAL1_READ_, xoff_detect_, v1) << R_SERIAL1_READ__xoff_detect__BITNR) | \ - (R_SERIAL1_READ__cts___##f2_##_VAL(R_SERIAL1_READ_, cts__, v2) << R_SERIAL1_READ__cts___BITNR) | \ - (R_SERIAL1_READ__tr_ready__##f3_##_VAL(R_SERIAL1_READ_, tr_ready_, v3) << R_SERIAL1_READ__tr_ready__BITNR) | \ - (R_SERIAL1_READ__rxd__##f4_##_VAL(R_SERIAL1_READ_, rxd_, v4) << R_SERIAL1_READ__rxd__BITNR) | \ - (R_SERIAL1_READ__overrun__##f5_##_VAL(R_SERIAL1_READ_, overrun_, v5) << R_SERIAL1_READ__overrun__BITNR) | \ - (R_SERIAL1_READ__par_err__##f6_##_VAL(R_SERIAL1_READ_, par_err_, v6) << R_SERIAL1_READ__par_err__BITNR) | \ - (R_SERIAL1_READ__framing_err__##f7_##_VAL(R_SERIAL1_READ_, framing_err_, v7) << R_SERIAL1_READ__framing_err__BITNR) | \ - (R_SERIAL1_READ__data_avail__##f8_##_VAL(R_SERIAL1_READ_, data_avail_, v8) << R_SERIAL1_READ__data_avail__BITNR) | \ - (R_SERIAL1_READ__data_in__##f9_##_VAL(R_SERIAL1_READ_, data_in_, v9) << R_SERIAL1_READ__data_in__BITNR) \ -) - -#endif - -/* - * R_SERIAL1_REC_CTRL - * - type: WO - * - addr: 0xb000006a - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SERIAL1_REC_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SERIAL1_REC_CTRL. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_SERIAL1_REC_CTRL. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SERIAL1_REC_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - *R_SERIAL1_REC_CTRL__SADDR = ( \ - REG_INITIATED(R_SERIAL1_REC_CTRL_) \ - REG_VAL__R_SERIAL1_REC_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \ - ), \ - R_SERIAL1_REC_CTRL__WRITE(R_SERIAL1_REC_CTRL__ADDR, *R_SERIAL1_REC_CTRL__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SERIAL1_REC_CTRL__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SERIAL1_REC_CTRL. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_SERIAL1_REC_CTRL. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SERIAL1_REC_CTRL__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - *R_SERIAL1_REC_CTRL__SADDR = ( \ - REG_INITIATED(R_SERIAL1_REC_CTRL_) \ - REG_VAL__R_SERIAL1_REC_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SERIAL1_REC_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SERIAL1_REC_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - (R_SERIAL1_REC_CTRL__dma_err__##f1##__MASK & REG__##v1) | \ - (R_SERIAL1_REC_CTRL__rec_enable__##f2##__MASK & REG__##v2) | \ - (R_SERIAL1_REC_CTRL__rts___##f3##__MASK & REG__##v3) | \ - (R_SERIAL1_REC_CTRL__sampling__##f4##__MASK & REG__##v4) | \ - (R_SERIAL1_REC_CTRL__rec_stick_par__##f5##__MASK & REG__##v5) | \ - (R_SERIAL1_REC_CTRL__rec_par__##f6##__MASK & REG__##v6) | \ - (R_SERIAL1_REC_CTRL__rec_par_en__##f7##__MASK & REG__##v7) | \ - (R_SERIAL1_REC_CTRL__rec_bitnr__##f8##__MASK & REG__##v8) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL1_REC_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL1_REC_CTRL. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL1_REC_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - (R_SERIAL1_REC_CTRL__dma_err__##f1##__VAL(R_SERIAL1_REC_CTRL_, dma_err_, v1) << R_SERIAL1_REC_CTRL__dma_err__BITNR) | \ - (R_SERIAL1_REC_CTRL__rec_enable__##f2##__VAL(R_SERIAL1_REC_CTRL_, rec_enable_, v2) << R_SERIAL1_REC_CTRL__rec_enable__BITNR) | \ - (R_SERIAL1_REC_CTRL__rts___##f3##__VAL(R_SERIAL1_REC_CTRL_, rts__, v3) << R_SERIAL1_REC_CTRL__rts___BITNR) | \ - (R_SERIAL1_REC_CTRL__sampling__##f4##__VAL(R_SERIAL1_REC_CTRL_, sampling_, v4) << R_SERIAL1_REC_CTRL__sampling__BITNR) | \ - (R_SERIAL1_REC_CTRL__rec_stick_par__##f5##__VAL(R_SERIAL1_REC_CTRL_, rec_stick_par_, v5) << R_SERIAL1_REC_CTRL__rec_stick_par__BITNR) | \ - (R_SERIAL1_REC_CTRL__rec_par__##f6##__VAL(R_SERIAL1_REC_CTRL_, rec_par_, v6) << R_SERIAL1_REC_CTRL__rec_par__BITNR) | \ - (R_SERIAL1_REC_CTRL__rec_par_en__##f7##__VAL(R_SERIAL1_REC_CTRL_, rec_par_en_, v7) << R_SERIAL1_REC_CTRL__rec_par_en__BITNR) | \ - (R_SERIAL1_REC_CTRL__rec_bitnr__##f8##__VAL(R_SERIAL1_REC_CTRL_, rec_bitnr_, v8) << R_SERIAL1_REC_CTRL__rec_bitnr__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL1_REC_CTRL_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL1_REC_CTRL. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL1_REC_CTRL_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8) ( \ - (R_SERIAL1_REC_CTRL__dma_err__##f1_##_VAL(R_SERIAL1_REC_CTRL_, dma_err_, v1) << R_SERIAL1_REC_CTRL__dma_err__BITNR) | \ - (R_SERIAL1_REC_CTRL__rec_enable__##f2_##_VAL(R_SERIAL1_REC_CTRL_, rec_enable_, v2) << R_SERIAL1_REC_CTRL__rec_enable__BITNR) | \ - (R_SERIAL1_REC_CTRL__rts___##f3_##_VAL(R_SERIAL1_REC_CTRL_, rts__, v3) << R_SERIAL1_REC_CTRL__rts___BITNR) | \ - (R_SERIAL1_REC_CTRL__sampling__##f4_##_VAL(R_SERIAL1_REC_CTRL_, sampling_, v4) << R_SERIAL1_REC_CTRL__sampling__BITNR) | \ - (R_SERIAL1_REC_CTRL__rec_stick_par__##f5_##_VAL(R_SERIAL1_REC_CTRL_, rec_stick_par_, v5) << R_SERIAL1_REC_CTRL__rec_stick_par__BITNR) | \ - (R_SERIAL1_REC_CTRL__rec_par__##f6_##_VAL(R_SERIAL1_REC_CTRL_, rec_par_, v6) << R_SERIAL1_REC_CTRL__rec_par__BITNR) | \ - (R_SERIAL1_REC_CTRL__rec_par_en__##f7_##_VAL(R_SERIAL1_REC_CTRL_, rec_par_en_, v7) << R_SERIAL1_REC_CTRL__rec_par_en__BITNR) | \ - (R_SERIAL1_REC_CTRL__rec_bitnr__##f8_##_VAL(R_SERIAL1_REC_CTRL_, rec_bitnr_, v8) << R_SERIAL1_REC_CTRL__rec_bitnr__BITNR) \ -) - -#endif - -/* - * R_SERIAL1_REC_DATA - * - type: RO - * - addr: 0xb0000068 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SERIAL1_REC_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SERIAL1_REC_DATA(f1,v1) ( \ - (R_SERIAL1_REC_DATA__data_in__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL1_REC_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL1_REC_DATA. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL1_REC_DATA(f1,v1) ( \ - (R_SERIAL1_REC_DATA__data_in__##f1##__VAL(R_SERIAL1_REC_DATA_, data_in_, v1) << R_SERIAL1_REC_DATA__data_in__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL1_REC_DATA_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL1_REC_DATA. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL1_REC_DATA_(f1_,v1) ( \ - (R_SERIAL1_REC_DATA__data_in__##f1_##_VAL(R_SERIAL1_REC_DATA_, data_in_, v1) << R_SERIAL1_REC_DATA__data_in__BITNR) \ -) - -#endif - -/* - * R_SERIAL1_STATUS - * - type: RO - * - addr: 0xb0000069 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SERIAL1_STATUS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SERIAL1_STATUS(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - (R_SERIAL1_STATUS__xoff_detect__##f1##__MASK & REG__##v1) | \ - (R_SERIAL1_STATUS__cts___##f2##__MASK & REG__##v2) | \ - (R_SERIAL1_STATUS__tr_ready__##f3##__MASK & REG__##v3) | \ - (R_SERIAL1_STATUS__rxd__##f4##__MASK & REG__##v4) | \ - (R_SERIAL1_STATUS__overrun__##f5##__MASK & REG__##v5) | \ - (R_SERIAL1_STATUS__par_err__##f6##__MASK & REG__##v6) | \ - (R_SERIAL1_STATUS__framing_err__##f7##__MASK & REG__##v7) | \ - (R_SERIAL1_STATUS__data_avail__##f8##__MASK & REG__##v8) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL1_STATUS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL1_STATUS. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL1_STATUS(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - (R_SERIAL1_STATUS__xoff_detect__##f1##__VAL(R_SERIAL1_STATUS_, xoff_detect_, v1) << R_SERIAL1_STATUS__xoff_detect__BITNR) | \ - (R_SERIAL1_STATUS__cts___##f2##__VAL(R_SERIAL1_STATUS_, cts__, v2) << R_SERIAL1_STATUS__cts___BITNR) | \ - (R_SERIAL1_STATUS__tr_ready__##f3##__VAL(R_SERIAL1_STATUS_, tr_ready_, v3) << R_SERIAL1_STATUS__tr_ready__BITNR) | \ - (R_SERIAL1_STATUS__rxd__##f4##__VAL(R_SERIAL1_STATUS_, rxd_, v4) << R_SERIAL1_STATUS__rxd__BITNR) | \ - (R_SERIAL1_STATUS__overrun__##f5##__VAL(R_SERIAL1_STATUS_, overrun_, v5) << R_SERIAL1_STATUS__overrun__BITNR) | \ - (R_SERIAL1_STATUS__par_err__##f6##__VAL(R_SERIAL1_STATUS_, par_err_, v6) << R_SERIAL1_STATUS__par_err__BITNR) | \ - (R_SERIAL1_STATUS__framing_err__##f7##__VAL(R_SERIAL1_STATUS_, framing_err_, v7) << R_SERIAL1_STATUS__framing_err__BITNR) | \ - (R_SERIAL1_STATUS__data_avail__##f8##__VAL(R_SERIAL1_STATUS_, data_avail_, v8) << R_SERIAL1_STATUS__data_avail__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL1_STATUS_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL1_STATUS. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL1_STATUS_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8) ( \ - (R_SERIAL1_STATUS__xoff_detect__##f1_##_VAL(R_SERIAL1_STATUS_, xoff_detect_, v1) << R_SERIAL1_STATUS__xoff_detect__BITNR) | \ - (R_SERIAL1_STATUS__cts___##f2_##_VAL(R_SERIAL1_STATUS_, cts__, v2) << R_SERIAL1_STATUS__cts___BITNR) | \ - (R_SERIAL1_STATUS__tr_ready__##f3_##_VAL(R_SERIAL1_STATUS_, tr_ready_, v3) << R_SERIAL1_STATUS__tr_ready__BITNR) | \ - (R_SERIAL1_STATUS__rxd__##f4_##_VAL(R_SERIAL1_STATUS_, rxd_, v4) << R_SERIAL1_STATUS__rxd__BITNR) | \ - (R_SERIAL1_STATUS__overrun__##f5_##_VAL(R_SERIAL1_STATUS_, overrun_, v5) << R_SERIAL1_STATUS__overrun__BITNR) | \ - (R_SERIAL1_STATUS__par_err__##f6_##_VAL(R_SERIAL1_STATUS_, par_err_, v6) << R_SERIAL1_STATUS__par_err__BITNR) | \ - (R_SERIAL1_STATUS__framing_err__##f7_##_VAL(R_SERIAL1_STATUS_, framing_err_, v7) << R_SERIAL1_STATUS__framing_err__BITNR) | \ - (R_SERIAL1_STATUS__data_avail__##f8_##_VAL(R_SERIAL1_STATUS_, data_avail_, v8) << R_SERIAL1_STATUS__data_avail__BITNR) \ -) - -#endif - -/* - * R_SERIAL1_TR_CTRL - * - type: WO - * - addr: 0xb0000069 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SERIAL1_TR_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SERIAL1_TR_CTRL. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_SERIAL1_TR_CTRL. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SERIAL1_TR_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - *R_SERIAL1_TR_CTRL__SADDR = ( \ - REG_INITIATED(R_SERIAL1_TR_CTRL_) \ - REG_VAL__R_SERIAL1_TR_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \ - ), \ - R_SERIAL1_TR_CTRL__WRITE(R_SERIAL1_TR_CTRL__ADDR, *R_SERIAL1_TR_CTRL__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SERIAL1_TR_CTRL__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SERIAL1_TR_CTRL. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_SERIAL1_TR_CTRL. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SERIAL1_TR_CTRL__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - *R_SERIAL1_TR_CTRL__SADDR = ( \ - REG_INITIATED(R_SERIAL1_TR_CTRL_) \ - REG_VAL__R_SERIAL1_TR_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SERIAL1_TR_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SERIAL1_TR_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - (R_SERIAL1_TR_CTRL__txd__##f1##__MASK & REG__##v1) | \ - (R_SERIAL1_TR_CTRL__tr_enable__##f2##__MASK & REG__##v2) | \ - (R_SERIAL1_TR_CTRL__auto_cts__##f3##__MASK & REG__##v3) | \ - (R_SERIAL1_TR_CTRL__stop_bits__##f4##__MASK & REG__##v4) | \ - (R_SERIAL1_TR_CTRL__tr_stick_par__##f5##__MASK & REG__##v5) | \ - (R_SERIAL1_TR_CTRL__tr_par__##f6##__MASK & REG__##v6) | \ - (R_SERIAL1_TR_CTRL__tr_par_en__##f7##__MASK & REG__##v7) | \ - (R_SERIAL1_TR_CTRL__tr_bitnr__##f8##__MASK & REG__##v8) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL1_TR_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL1_TR_CTRL. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL1_TR_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - (R_SERIAL1_TR_CTRL__txd__##f1##__VAL(R_SERIAL1_TR_CTRL_, txd_, v1) << R_SERIAL1_TR_CTRL__txd__BITNR) | \ - (R_SERIAL1_TR_CTRL__tr_enable__##f2##__VAL(R_SERIAL1_TR_CTRL_, tr_enable_, v2) << R_SERIAL1_TR_CTRL__tr_enable__BITNR) | \ - (R_SERIAL1_TR_CTRL__auto_cts__##f3##__VAL(R_SERIAL1_TR_CTRL_, auto_cts_, v3) << R_SERIAL1_TR_CTRL__auto_cts__BITNR) | \ - (R_SERIAL1_TR_CTRL__stop_bits__##f4##__VAL(R_SERIAL1_TR_CTRL_, stop_bits_, v4) << R_SERIAL1_TR_CTRL__stop_bits__BITNR) | \ - (R_SERIAL1_TR_CTRL__tr_stick_par__##f5##__VAL(R_SERIAL1_TR_CTRL_, tr_stick_par_, v5) << R_SERIAL1_TR_CTRL__tr_stick_par__BITNR) | \ - (R_SERIAL1_TR_CTRL__tr_par__##f6##__VAL(R_SERIAL1_TR_CTRL_, tr_par_, v6) << R_SERIAL1_TR_CTRL__tr_par__BITNR) | \ - (R_SERIAL1_TR_CTRL__tr_par_en__##f7##__VAL(R_SERIAL1_TR_CTRL_, tr_par_en_, v7) << R_SERIAL1_TR_CTRL__tr_par_en__BITNR) | \ - (R_SERIAL1_TR_CTRL__tr_bitnr__##f8##__VAL(R_SERIAL1_TR_CTRL_, tr_bitnr_, v8) << R_SERIAL1_TR_CTRL__tr_bitnr__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL1_TR_CTRL_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL1_TR_CTRL. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL1_TR_CTRL_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8) ( \ - (R_SERIAL1_TR_CTRL__txd__##f1_##_VAL(R_SERIAL1_TR_CTRL_, txd_, v1) << R_SERIAL1_TR_CTRL__txd__BITNR) | \ - (R_SERIAL1_TR_CTRL__tr_enable__##f2_##_VAL(R_SERIAL1_TR_CTRL_, tr_enable_, v2) << R_SERIAL1_TR_CTRL__tr_enable__BITNR) | \ - (R_SERIAL1_TR_CTRL__auto_cts__##f3_##_VAL(R_SERIAL1_TR_CTRL_, auto_cts_, v3) << R_SERIAL1_TR_CTRL__auto_cts__BITNR) | \ - (R_SERIAL1_TR_CTRL__stop_bits__##f4_##_VAL(R_SERIAL1_TR_CTRL_, stop_bits_, v4) << R_SERIAL1_TR_CTRL__stop_bits__BITNR) | \ - (R_SERIAL1_TR_CTRL__tr_stick_par__##f5_##_VAL(R_SERIAL1_TR_CTRL_, tr_stick_par_, v5) << R_SERIAL1_TR_CTRL__tr_stick_par__BITNR) | \ - (R_SERIAL1_TR_CTRL__tr_par__##f6_##_VAL(R_SERIAL1_TR_CTRL_, tr_par_, v6) << R_SERIAL1_TR_CTRL__tr_par__BITNR) | \ - (R_SERIAL1_TR_CTRL__tr_par_en__##f7_##_VAL(R_SERIAL1_TR_CTRL_, tr_par_en_, v7) << R_SERIAL1_TR_CTRL__tr_par_en__BITNR) | \ - (R_SERIAL1_TR_CTRL__tr_bitnr__##f8_##_VAL(R_SERIAL1_TR_CTRL_, tr_bitnr_, v8) << R_SERIAL1_TR_CTRL__tr_bitnr__BITNR) \ -) - -#endif - -/* - * R_SERIAL1_TR_DATA - * - type: WO - * - addr: 0xb0000068 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SERIAL1_TR_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SERIAL1_TR_DATA. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_SERIAL1_TR_DATA. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SERIAL1_TR_DATA(f1,v1) ( \ - *R_SERIAL1_TR_DATA__SADDR = ( \ - REG_INITIATED(R_SERIAL1_TR_DATA_) \ - REG_VAL__R_SERIAL1_TR_DATA_(f1##_,v1) \ - ), \ - R_SERIAL1_TR_DATA__WRITE(R_SERIAL1_TR_DATA__ADDR, *R_SERIAL1_TR_DATA__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SERIAL1_TR_DATA__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SERIAL1_TR_DATA. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_SERIAL1_TR_DATA. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SERIAL1_TR_DATA__SHADOW(f1,v1) ( \ - *R_SERIAL1_TR_DATA__SADDR = ( \ - REG_INITIATED(R_SERIAL1_TR_DATA_) \ - REG_VAL__R_SERIAL1_TR_DATA_(f1##_,v1) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SERIAL1_TR_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SERIAL1_TR_DATA(f1,v1) ( \ - (R_SERIAL1_TR_DATA__data_out__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL1_TR_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL1_TR_DATA. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL1_TR_DATA(f1,v1) ( \ - (R_SERIAL1_TR_DATA__data_out__##f1##__VAL(R_SERIAL1_TR_DATA_, data_out_, v1) << R_SERIAL1_TR_DATA__data_out__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL1_TR_DATA_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL1_TR_DATA. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL1_TR_DATA_(f1_,v1) ( \ - (R_SERIAL1_TR_DATA__data_out__##f1_##_VAL(R_SERIAL1_TR_DATA_, data_out_, v1) << R_SERIAL1_TR_DATA__data_out__BITNR) \ -) - -#endif - -/* - * R_SERIAL1_XOFF - * - type: WO - * - addr: 0xb000006c - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SERIAL1_XOFF -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SERIAL1_XOFF. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_SERIAL1_XOFF. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SERIAL1_XOFF(f1,v1,f2,v2,f3,v3) ( \ - *R_SERIAL1_XOFF__SADDR = ( \ - REG_INITIATED(R_SERIAL1_XOFF_) \ - REG_VAL__R_SERIAL1_XOFF_(f1##_,v1,f2##_,v2,f3##_,v3) \ - ), \ - R_SERIAL1_XOFF__WRITE(R_SERIAL1_XOFF__ADDR, *R_SERIAL1_XOFF__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SERIAL1_XOFF__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SERIAL1_XOFF. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_SERIAL1_XOFF. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SERIAL1_XOFF__SHADOW(f1,v1,f2,v2,f3,v3) ( \ - *R_SERIAL1_XOFF__SADDR = ( \ - REG_INITIATED(R_SERIAL1_XOFF_) \ - REG_VAL__R_SERIAL1_XOFF_(f1##_,v1,f2##_,v2,f3##_,v3) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SERIAL1_XOFF -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SERIAL1_XOFF(f1,v1,f2,v2,f3,v3) ( \ - (R_SERIAL1_XOFF__tx_stop__##f1##__MASK & REG__##v1) | \ - (R_SERIAL1_XOFF__auto_xoff__##f2##__MASK & REG__##v2) | \ - (R_SERIAL1_XOFF__xoff_char__##f3##__MASK & REG__##v3) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL1_XOFF -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL1_XOFF. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL1_XOFF(f1,v1,f2,v2,f3,v3) ( \ - (R_SERIAL1_XOFF__tx_stop__##f1##__VAL(R_SERIAL1_XOFF_, tx_stop_, v1) << R_SERIAL1_XOFF__tx_stop__BITNR) | \ - (R_SERIAL1_XOFF__auto_xoff__##f2##__VAL(R_SERIAL1_XOFF_, auto_xoff_, v2) << R_SERIAL1_XOFF__auto_xoff__BITNR) | \ - (R_SERIAL1_XOFF__xoff_char__##f3##__VAL(R_SERIAL1_XOFF_, xoff_char_, v3) << R_SERIAL1_XOFF__xoff_char__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL1_XOFF_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL1_XOFF. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL1_XOFF_(f1_,v1,f2_,v2,f3_,v3) ( \ - (R_SERIAL1_XOFF__tx_stop__##f1_##_VAL(R_SERIAL1_XOFF_, tx_stop_, v1) << R_SERIAL1_XOFF__tx_stop__BITNR) | \ - (R_SERIAL1_XOFF__auto_xoff__##f2_##_VAL(R_SERIAL1_XOFF_, auto_xoff_, v2) << R_SERIAL1_XOFF__auto_xoff__BITNR) | \ - (R_SERIAL1_XOFF__xoff_char__##f3_##_VAL(R_SERIAL1_XOFF_, xoff_char_, v3) << R_SERIAL1_XOFF__xoff_char__BITNR) \ -) - -#endif - -/* - * R_SERIAL2_BAUD - * - type: WO - * - addr: 0xb0000073 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SERIAL2_BAUD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SERIAL2_BAUD. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_SERIAL2_BAUD. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SERIAL2_BAUD(f1,v1,f2,v2) ( \ - *R_SERIAL2_BAUD__SADDR = ( \ - REG_INITIATED(R_SERIAL2_BAUD_) \ - REG_VAL__R_SERIAL2_BAUD_(f1##_,v1,f2##_,v2) \ - ), \ - R_SERIAL2_BAUD__WRITE(R_SERIAL2_BAUD__ADDR, *R_SERIAL2_BAUD__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SERIAL2_BAUD__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SERIAL2_BAUD. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_SERIAL2_BAUD. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SERIAL2_BAUD__SHADOW(f1,v1,f2,v2) ( \ - *R_SERIAL2_BAUD__SADDR = ( \ - REG_INITIATED(R_SERIAL2_BAUD_) \ - REG_VAL__R_SERIAL2_BAUD_(f1##_,v1,f2##_,v2) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SERIAL2_BAUD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SERIAL2_BAUD(f1,v1,f2,v2) ( \ - (R_SERIAL2_BAUD__tr_baud__##f1##__MASK & REG__##v1) | \ - (R_SERIAL2_BAUD__rec_baud__##f2##__MASK & REG__##v2) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL2_BAUD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL2_BAUD. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL2_BAUD(f1,v1,f2,v2) ( \ - (R_SERIAL2_BAUD__tr_baud__##f1##__VAL(R_SERIAL2_BAUD_, tr_baud_, v1) << R_SERIAL2_BAUD__tr_baud__BITNR) | \ - (R_SERIAL2_BAUD__rec_baud__##f2##__VAL(R_SERIAL2_BAUD_, rec_baud_, v2) << R_SERIAL2_BAUD__rec_baud__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL2_BAUD_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL2_BAUD. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL2_BAUD_(f1_,v1,f2_,v2) ( \ - (R_SERIAL2_BAUD__tr_baud__##f1_##_VAL(R_SERIAL2_BAUD_, tr_baud_, v1) << R_SERIAL2_BAUD__tr_baud__BITNR) | \ - (R_SERIAL2_BAUD__rec_baud__##f2_##_VAL(R_SERIAL2_BAUD_, rec_baud_, v2) << R_SERIAL2_BAUD__rec_baud__BITNR) \ -) - -#endif - -/* - * R_SERIAL2_CTRL - * - type: WO - * - addr: 0xb0000070 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SERIAL2_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SERIAL2_CTRL. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_SERIAL2_CTRL. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SERIAL2_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19) ( \ - *R_SERIAL2_CTRL__SADDR = ( \ - REG_INITIATED(R_SERIAL2_CTRL_) \ - REG_VAL__R_SERIAL2_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19) \ - ), \ - R_SERIAL2_CTRL__WRITE(R_SERIAL2_CTRL__ADDR, *R_SERIAL2_CTRL__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SERIAL2_CTRL__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SERIAL2_CTRL. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_SERIAL2_CTRL. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SERIAL2_CTRL__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19) ( \ - *R_SERIAL2_CTRL__SADDR = ( \ - REG_INITIATED(R_SERIAL2_CTRL_) \ - REG_VAL__R_SERIAL2_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SERIAL2_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SERIAL2_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19) ( \ - (R_SERIAL2_CTRL__tr_baud__##f1##__MASK & REG__##v1) | \ - (R_SERIAL2_CTRL__rec_baud__##f2##__MASK & REG__##v2) | \ - (R_SERIAL2_CTRL__dma_err__##f3##__MASK & REG__##v3) | \ - (R_SERIAL2_CTRL__rec_enable__##f4##__MASK & REG__##v4) | \ - (R_SERIAL2_CTRL__rts___##f5##__MASK & REG__##v5) | \ - (R_SERIAL2_CTRL__sampling__##f6##__MASK & REG__##v6) | \ - (R_SERIAL2_CTRL__rec_stick_par__##f7##__MASK & REG__##v7) | \ - (R_SERIAL2_CTRL__rec_par__##f8##__MASK & REG__##v8) | \ - (R_SERIAL2_CTRL__rec_par_en__##f9##__MASK & REG__##v9) | \ - (R_SERIAL2_CTRL__rec_bitnr__##f10##__MASK & REG__##v10) | \ - (R_SERIAL2_CTRL__txd__##f11##__MASK & REG__##v11) | \ - (R_SERIAL2_CTRL__tr_enable__##f12##__MASK & REG__##v12) | \ - (R_SERIAL2_CTRL__auto_cts__##f13##__MASK & REG__##v13) | \ - (R_SERIAL2_CTRL__stop_bits__##f14##__MASK & REG__##v14) | \ - (R_SERIAL2_CTRL__tr_stick_par__##f15##__MASK & REG__##v15) | \ - (R_SERIAL2_CTRL__tr_par__##f16##__MASK & REG__##v16) | \ - (R_SERIAL2_CTRL__tr_par_en__##f17##__MASK & REG__##v17) | \ - (R_SERIAL2_CTRL__tr_bitnr__##f18##__MASK & REG__##v18) | \ - (R_SERIAL2_CTRL__data_out__##f19##__MASK & REG__##v19) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL2_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL2_CTRL. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL2_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19) ( \ - (R_SERIAL2_CTRL__tr_baud__##f1##__VAL(R_SERIAL2_CTRL_, tr_baud_, v1) << R_SERIAL2_CTRL__tr_baud__BITNR) | \ - (R_SERIAL2_CTRL__rec_baud__##f2##__VAL(R_SERIAL2_CTRL_, rec_baud_, v2) << R_SERIAL2_CTRL__rec_baud__BITNR) | \ - (R_SERIAL2_CTRL__dma_err__##f3##__VAL(R_SERIAL2_CTRL_, dma_err_, v3) << R_SERIAL2_CTRL__dma_err__BITNR) | \ - (R_SERIAL2_CTRL__rec_enable__##f4##__VAL(R_SERIAL2_CTRL_, rec_enable_, v4) << R_SERIAL2_CTRL__rec_enable__BITNR) | \ - (R_SERIAL2_CTRL__rts___##f5##__VAL(R_SERIAL2_CTRL_, rts__, v5) << R_SERIAL2_CTRL__rts___BITNR) | \ - (R_SERIAL2_CTRL__sampling__##f6##__VAL(R_SERIAL2_CTRL_, sampling_, v6) << R_SERIAL2_CTRL__sampling__BITNR) | \ - (R_SERIAL2_CTRL__rec_stick_par__##f7##__VAL(R_SERIAL2_CTRL_, rec_stick_par_, v7) << R_SERIAL2_CTRL__rec_stick_par__BITNR) | \ - (R_SERIAL2_CTRL__rec_par__##f8##__VAL(R_SERIAL2_CTRL_, rec_par_, v8) << R_SERIAL2_CTRL__rec_par__BITNR) | \ - (R_SERIAL2_CTRL__rec_par_en__##f9##__VAL(R_SERIAL2_CTRL_, rec_par_en_, v9) << R_SERIAL2_CTRL__rec_par_en__BITNR) | \ - (R_SERIAL2_CTRL__rec_bitnr__##f10##__VAL(R_SERIAL2_CTRL_, rec_bitnr_, v10) << R_SERIAL2_CTRL__rec_bitnr__BITNR) | \ - (R_SERIAL2_CTRL__txd__##f11##__VAL(R_SERIAL2_CTRL_, txd_, v11) << R_SERIAL2_CTRL__txd__BITNR) | \ - (R_SERIAL2_CTRL__tr_enable__##f12##__VAL(R_SERIAL2_CTRL_, tr_enable_, v12) << R_SERIAL2_CTRL__tr_enable__BITNR) | \ - (R_SERIAL2_CTRL__auto_cts__##f13##__VAL(R_SERIAL2_CTRL_, auto_cts_, v13) << R_SERIAL2_CTRL__auto_cts__BITNR) | \ - (R_SERIAL2_CTRL__stop_bits__##f14##__VAL(R_SERIAL2_CTRL_, stop_bits_, v14) << R_SERIAL2_CTRL__stop_bits__BITNR) | \ - (R_SERIAL2_CTRL__tr_stick_par__##f15##__VAL(R_SERIAL2_CTRL_, tr_stick_par_, v15) << R_SERIAL2_CTRL__tr_stick_par__BITNR) | \ - (R_SERIAL2_CTRL__tr_par__##f16##__VAL(R_SERIAL2_CTRL_, tr_par_, v16) << R_SERIAL2_CTRL__tr_par__BITNR) | \ - (R_SERIAL2_CTRL__tr_par_en__##f17##__VAL(R_SERIAL2_CTRL_, tr_par_en_, v17) << R_SERIAL2_CTRL__tr_par_en__BITNR) | \ - (R_SERIAL2_CTRL__tr_bitnr__##f18##__VAL(R_SERIAL2_CTRL_, tr_bitnr_, v18) << R_SERIAL2_CTRL__tr_bitnr__BITNR) | \ - (R_SERIAL2_CTRL__data_out__##f19##__VAL(R_SERIAL2_CTRL_, data_out_, v19) << R_SERIAL2_CTRL__data_out__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL2_CTRL_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL2_CTRL. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL2_CTRL_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16,f17_,v17,f18_,v18,f19_,v19) ( \ - (R_SERIAL2_CTRL__tr_baud__##f1_##_VAL(R_SERIAL2_CTRL_, tr_baud_, v1) << R_SERIAL2_CTRL__tr_baud__BITNR) | \ - (R_SERIAL2_CTRL__rec_baud__##f2_##_VAL(R_SERIAL2_CTRL_, rec_baud_, v2) << R_SERIAL2_CTRL__rec_baud__BITNR) | \ - (R_SERIAL2_CTRL__dma_err__##f3_##_VAL(R_SERIAL2_CTRL_, dma_err_, v3) << R_SERIAL2_CTRL__dma_err__BITNR) | \ - (R_SERIAL2_CTRL__rec_enable__##f4_##_VAL(R_SERIAL2_CTRL_, rec_enable_, v4) << R_SERIAL2_CTRL__rec_enable__BITNR) | \ - (R_SERIAL2_CTRL__rts___##f5_##_VAL(R_SERIAL2_CTRL_, rts__, v5) << R_SERIAL2_CTRL__rts___BITNR) | \ - (R_SERIAL2_CTRL__sampling__##f6_##_VAL(R_SERIAL2_CTRL_, sampling_, v6) << R_SERIAL2_CTRL__sampling__BITNR) | \ - (R_SERIAL2_CTRL__rec_stick_par__##f7_##_VAL(R_SERIAL2_CTRL_, rec_stick_par_, v7) << R_SERIAL2_CTRL__rec_stick_par__BITNR) | \ - (R_SERIAL2_CTRL__rec_par__##f8_##_VAL(R_SERIAL2_CTRL_, rec_par_, v8) << R_SERIAL2_CTRL__rec_par__BITNR) | \ - (R_SERIAL2_CTRL__rec_par_en__##f9_##_VAL(R_SERIAL2_CTRL_, rec_par_en_, v9) << R_SERIAL2_CTRL__rec_par_en__BITNR) | \ - (R_SERIAL2_CTRL__rec_bitnr__##f10_##_VAL(R_SERIAL2_CTRL_, rec_bitnr_, v10) << R_SERIAL2_CTRL__rec_bitnr__BITNR) | \ - (R_SERIAL2_CTRL__txd__##f11_##_VAL(R_SERIAL2_CTRL_, txd_, v11) << R_SERIAL2_CTRL__txd__BITNR) | \ - (R_SERIAL2_CTRL__tr_enable__##f12_##_VAL(R_SERIAL2_CTRL_, tr_enable_, v12) << R_SERIAL2_CTRL__tr_enable__BITNR) | \ - (R_SERIAL2_CTRL__auto_cts__##f13_##_VAL(R_SERIAL2_CTRL_, auto_cts_, v13) << R_SERIAL2_CTRL__auto_cts__BITNR) | \ - (R_SERIAL2_CTRL__stop_bits__##f14_##_VAL(R_SERIAL2_CTRL_, stop_bits_, v14) << R_SERIAL2_CTRL__stop_bits__BITNR) | \ - (R_SERIAL2_CTRL__tr_stick_par__##f15_##_VAL(R_SERIAL2_CTRL_, tr_stick_par_, v15) << R_SERIAL2_CTRL__tr_stick_par__BITNR) | \ - (R_SERIAL2_CTRL__tr_par__##f16_##_VAL(R_SERIAL2_CTRL_, tr_par_, v16) << R_SERIAL2_CTRL__tr_par__BITNR) | \ - (R_SERIAL2_CTRL__tr_par_en__##f17_##_VAL(R_SERIAL2_CTRL_, tr_par_en_, v17) << R_SERIAL2_CTRL__tr_par_en__BITNR) | \ - (R_SERIAL2_CTRL__tr_bitnr__##f18_##_VAL(R_SERIAL2_CTRL_, tr_bitnr_, v18) << R_SERIAL2_CTRL__tr_bitnr__BITNR) | \ - (R_SERIAL2_CTRL__data_out__##f19_##_VAL(R_SERIAL2_CTRL_, data_out_, v19) << R_SERIAL2_CTRL__data_out__BITNR) \ -) - -#endif - -/* - * R_SERIAL2_READ - * - type: RO - * - addr: 0xb0000070 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SERIAL2_READ -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SERIAL2_READ(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \ - (R_SERIAL2_READ__xoff_detect__##f1##__MASK & REG__##v1) | \ - (R_SERIAL2_READ__cts___##f2##__MASK & REG__##v2) | \ - (R_SERIAL2_READ__tr_ready__##f3##__MASK & REG__##v3) | \ - (R_SERIAL2_READ__rxd__##f4##__MASK & REG__##v4) | \ - (R_SERIAL2_READ__overrun__##f5##__MASK & REG__##v5) | \ - (R_SERIAL2_READ__par_err__##f6##__MASK & REG__##v6) | \ - (R_SERIAL2_READ__framing_err__##f7##__MASK & REG__##v7) | \ - (R_SERIAL2_READ__data_avail__##f8##__MASK & REG__##v8) | \ - (R_SERIAL2_READ__data_in__##f9##__MASK & REG__##v9) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL2_READ -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL2_READ. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL2_READ(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \ - (R_SERIAL2_READ__xoff_detect__##f1##__VAL(R_SERIAL2_READ_, xoff_detect_, v1) << R_SERIAL2_READ__xoff_detect__BITNR) | \ - (R_SERIAL2_READ__cts___##f2##__VAL(R_SERIAL2_READ_, cts__, v2) << R_SERIAL2_READ__cts___BITNR) | \ - (R_SERIAL2_READ__tr_ready__##f3##__VAL(R_SERIAL2_READ_, tr_ready_, v3) << R_SERIAL2_READ__tr_ready__BITNR) | \ - (R_SERIAL2_READ__rxd__##f4##__VAL(R_SERIAL2_READ_, rxd_, v4) << R_SERIAL2_READ__rxd__BITNR) | \ - (R_SERIAL2_READ__overrun__##f5##__VAL(R_SERIAL2_READ_, overrun_, v5) << R_SERIAL2_READ__overrun__BITNR) | \ - (R_SERIAL2_READ__par_err__##f6##__VAL(R_SERIAL2_READ_, par_err_, v6) << R_SERIAL2_READ__par_err__BITNR) | \ - (R_SERIAL2_READ__framing_err__##f7##__VAL(R_SERIAL2_READ_, framing_err_, v7) << R_SERIAL2_READ__framing_err__BITNR) | \ - (R_SERIAL2_READ__data_avail__##f8##__VAL(R_SERIAL2_READ_, data_avail_, v8) << R_SERIAL2_READ__data_avail__BITNR) | \ - (R_SERIAL2_READ__data_in__##f9##__VAL(R_SERIAL2_READ_, data_in_, v9) << R_SERIAL2_READ__data_in__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL2_READ_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL2_READ. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL2_READ_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9) ( \ - (R_SERIAL2_READ__xoff_detect__##f1_##_VAL(R_SERIAL2_READ_, xoff_detect_, v1) << R_SERIAL2_READ__xoff_detect__BITNR) | \ - (R_SERIAL2_READ__cts___##f2_##_VAL(R_SERIAL2_READ_, cts__, v2) << R_SERIAL2_READ__cts___BITNR) | \ - (R_SERIAL2_READ__tr_ready__##f3_##_VAL(R_SERIAL2_READ_, tr_ready_, v3) << R_SERIAL2_READ__tr_ready__BITNR) | \ - (R_SERIAL2_READ__rxd__##f4_##_VAL(R_SERIAL2_READ_, rxd_, v4) << R_SERIAL2_READ__rxd__BITNR) | \ - (R_SERIAL2_READ__overrun__##f5_##_VAL(R_SERIAL2_READ_, overrun_, v5) << R_SERIAL2_READ__overrun__BITNR) | \ - (R_SERIAL2_READ__par_err__##f6_##_VAL(R_SERIAL2_READ_, par_err_, v6) << R_SERIAL2_READ__par_err__BITNR) | \ - (R_SERIAL2_READ__framing_err__##f7_##_VAL(R_SERIAL2_READ_, framing_err_, v7) << R_SERIAL2_READ__framing_err__BITNR) | \ - (R_SERIAL2_READ__data_avail__##f8_##_VAL(R_SERIAL2_READ_, data_avail_, v8) << R_SERIAL2_READ__data_avail__BITNR) | \ - (R_SERIAL2_READ__data_in__##f9_##_VAL(R_SERIAL2_READ_, data_in_, v9) << R_SERIAL2_READ__data_in__BITNR) \ -) - -#endif - -/* - * R_SERIAL2_REC_CTRL - * - type: WO - * - addr: 0xb0000072 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SERIAL2_REC_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SERIAL2_REC_CTRL. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_SERIAL2_REC_CTRL. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SERIAL2_REC_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - *R_SERIAL2_REC_CTRL__SADDR = ( \ - REG_INITIATED(R_SERIAL2_REC_CTRL_) \ - REG_VAL__R_SERIAL2_REC_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \ - ), \ - R_SERIAL2_REC_CTRL__WRITE(R_SERIAL2_REC_CTRL__ADDR, *R_SERIAL2_REC_CTRL__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SERIAL2_REC_CTRL__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SERIAL2_REC_CTRL. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_SERIAL2_REC_CTRL. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SERIAL2_REC_CTRL__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - *R_SERIAL2_REC_CTRL__SADDR = ( \ - REG_INITIATED(R_SERIAL2_REC_CTRL_) \ - REG_VAL__R_SERIAL2_REC_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SERIAL2_REC_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SERIAL2_REC_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - (R_SERIAL2_REC_CTRL__dma_err__##f1##__MASK & REG__##v1) | \ - (R_SERIAL2_REC_CTRL__rec_enable__##f2##__MASK & REG__##v2) | \ - (R_SERIAL2_REC_CTRL__rts___##f3##__MASK & REG__##v3) | \ - (R_SERIAL2_REC_CTRL__sampling__##f4##__MASK & REG__##v4) | \ - (R_SERIAL2_REC_CTRL__rec_stick_par__##f5##__MASK & REG__##v5) | \ - (R_SERIAL2_REC_CTRL__rec_par__##f6##__MASK & REG__##v6) | \ - (R_SERIAL2_REC_CTRL__rec_par_en__##f7##__MASK & REG__##v7) | \ - (R_SERIAL2_REC_CTRL__rec_bitnr__##f8##__MASK & REG__##v8) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL2_REC_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL2_REC_CTRL. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL2_REC_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - (R_SERIAL2_REC_CTRL__dma_err__##f1##__VAL(R_SERIAL2_REC_CTRL_, dma_err_, v1) << R_SERIAL2_REC_CTRL__dma_err__BITNR) | \ - (R_SERIAL2_REC_CTRL__rec_enable__##f2##__VAL(R_SERIAL2_REC_CTRL_, rec_enable_, v2) << R_SERIAL2_REC_CTRL__rec_enable__BITNR) | \ - (R_SERIAL2_REC_CTRL__rts___##f3##__VAL(R_SERIAL2_REC_CTRL_, rts__, v3) << R_SERIAL2_REC_CTRL__rts___BITNR) | \ - (R_SERIAL2_REC_CTRL__sampling__##f4##__VAL(R_SERIAL2_REC_CTRL_, sampling_, v4) << R_SERIAL2_REC_CTRL__sampling__BITNR) | \ - (R_SERIAL2_REC_CTRL__rec_stick_par__##f5##__VAL(R_SERIAL2_REC_CTRL_, rec_stick_par_, v5) << R_SERIAL2_REC_CTRL__rec_stick_par__BITNR) | \ - (R_SERIAL2_REC_CTRL__rec_par__##f6##__VAL(R_SERIAL2_REC_CTRL_, rec_par_, v6) << R_SERIAL2_REC_CTRL__rec_par__BITNR) | \ - (R_SERIAL2_REC_CTRL__rec_par_en__##f7##__VAL(R_SERIAL2_REC_CTRL_, rec_par_en_, v7) << R_SERIAL2_REC_CTRL__rec_par_en__BITNR) | \ - (R_SERIAL2_REC_CTRL__rec_bitnr__##f8##__VAL(R_SERIAL2_REC_CTRL_, rec_bitnr_, v8) << R_SERIAL2_REC_CTRL__rec_bitnr__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL2_REC_CTRL_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL2_REC_CTRL. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL2_REC_CTRL_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8) ( \ - (R_SERIAL2_REC_CTRL__dma_err__##f1_##_VAL(R_SERIAL2_REC_CTRL_, dma_err_, v1) << R_SERIAL2_REC_CTRL__dma_err__BITNR) | \ - (R_SERIAL2_REC_CTRL__rec_enable__##f2_##_VAL(R_SERIAL2_REC_CTRL_, rec_enable_, v2) << R_SERIAL2_REC_CTRL__rec_enable__BITNR) | \ - (R_SERIAL2_REC_CTRL__rts___##f3_##_VAL(R_SERIAL2_REC_CTRL_, rts__, v3) << R_SERIAL2_REC_CTRL__rts___BITNR) | \ - (R_SERIAL2_REC_CTRL__sampling__##f4_##_VAL(R_SERIAL2_REC_CTRL_, sampling_, v4) << R_SERIAL2_REC_CTRL__sampling__BITNR) | \ - (R_SERIAL2_REC_CTRL__rec_stick_par__##f5_##_VAL(R_SERIAL2_REC_CTRL_, rec_stick_par_, v5) << R_SERIAL2_REC_CTRL__rec_stick_par__BITNR) | \ - (R_SERIAL2_REC_CTRL__rec_par__##f6_##_VAL(R_SERIAL2_REC_CTRL_, rec_par_, v6) << R_SERIAL2_REC_CTRL__rec_par__BITNR) | \ - (R_SERIAL2_REC_CTRL__rec_par_en__##f7_##_VAL(R_SERIAL2_REC_CTRL_, rec_par_en_, v7) << R_SERIAL2_REC_CTRL__rec_par_en__BITNR) | \ - (R_SERIAL2_REC_CTRL__rec_bitnr__##f8_##_VAL(R_SERIAL2_REC_CTRL_, rec_bitnr_, v8) << R_SERIAL2_REC_CTRL__rec_bitnr__BITNR) \ -) - -#endif - -/* - * R_SERIAL2_REC_DATA - * - type: RO - * - addr: 0xb0000070 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SERIAL2_REC_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SERIAL2_REC_DATA(f1,v1) ( \ - (R_SERIAL2_REC_DATA__data_in__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL2_REC_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL2_REC_DATA. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL2_REC_DATA(f1,v1) ( \ - (R_SERIAL2_REC_DATA__data_in__##f1##__VAL(R_SERIAL2_REC_DATA_, data_in_, v1) << R_SERIAL2_REC_DATA__data_in__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL2_REC_DATA_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL2_REC_DATA. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL2_REC_DATA_(f1_,v1) ( \ - (R_SERIAL2_REC_DATA__data_in__##f1_##_VAL(R_SERIAL2_REC_DATA_, data_in_, v1) << R_SERIAL2_REC_DATA__data_in__BITNR) \ -) - -#endif - -/* - * R_SERIAL2_STATUS - * - type: RO - * - addr: 0xb0000071 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SERIAL2_STATUS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SERIAL2_STATUS(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - (R_SERIAL2_STATUS__xoff_detect__##f1##__MASK & REG__##v1) | \ - (R_SERIAL2_STATUS__cts___##f2##__MASK & REG__##v2) | \ - (R_SERIAL2_STATUS__tr_ready__##f3##__MASK & REG__##v3) | \ - (R_SERIAL2_STATUS__rxd__##f4##__MASK & REG__##v4) | \ - (R_SERIAL2_STATUS__overrun__##f5##__MASK & REG__##v5) | \ - (R_SERIAL2_STATUS__par_err__##f6##__MASK & REG__##v6) | \ - (R_SERIAL2_STATUS__framing_err__##f7##__MASK & REG__##v7) | \ - (R_SERIAL2_STATUS__data_avail__##f8##__MASK & REG__##v8) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL2_STATUS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL2_STATUS. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL2_STATUS(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - (R_SERIAL2_STATUS__xoff_detect__##f1##__VAL(R_SERIAL2_STATUS_, xoff_detect_, v1) << R_SERIAL2_STATUS__xoff_detect__BITNR) | \ - (R_SERIAL2_STATUS__cts___##f2##__VAL(R_SERIAL2_STATUS_, cts__, v2) << R_SERIAL2_STATUS__cts___BITNR) | \ - (R_SERIAL2_STATUS__tr_ready__##f3##__VAL(R_SERIAL2_STATUS_, tr_ready_, v3) << R_SERIAL2_STATUS__tr_ready__BITNR) | \ - (R_SERIAL2_STATUS__rxd__##f4##__VAL(R_SERIAL2_STATUS_, rxd_, v4) << R_SERIAL2_STATUS__rxd__BITNR) | \ - (R_SERIAL2_STATUS__overrun__##f5##__VAL(R_SERIAL2_STATUS_, overrun_, v5) << R_SERIAL2_STATUS__overrun__BITNR) | \ - (R_SERIAL2_STATUS__par_err__##f6##__VAL(R_SERIAL2_STATUS_, par_err_, v6) << R_SERIAL2_STATUS__par_err__BITNR) | \ - (R_SERIAL2_STATUS__framing_err__##f7##__VAL(R_SERIAL2_STATUS_, framing_err_, v7) << R_SERIAL2_STATUS__framing_err__BITNR) | \ - (R_SERIAL2_STATUS__data_avail__##f8##__VAL(R_SERIAL2_STATUS_, data_avail_, v8) << R_SERIAL2_STATUS__data_avail__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL2_STATUS_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL2_STATUS. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL2_STATUS_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8) ( \ - (R_SERIAL2_STATUS__xoff_detect__##f1_##_VAL(R_SERIAL2_STATUS_, xoff_detect_, v1) << R_SERIAL2_STATUS__xoff_detect__BITNR) | \ - (R_SERIAL2_STATUS__cts___##f2_##_VAL(R_SERIAL2_STATUS_, cts__, v2) << R_SERIAL2_STATUS__cts___BITNR) | \ - (R_SERIAL2_STATUS__tr_ready__##f3_##_VAL(R_SERIAL2_STATUS_, tr_ready_, v3) << R_SERIAL2_STATUS__tr_ready__BITNR) | \ - (R_SERIAL2_STATUS__rxd__##f4_##_VAL(R_SERIAL2_STATUS_, rxd_, v4) << R_SERIAL2_STATUS__rxd__BITNR) | \ - (R_SERIAL2_STATUS__overrun__##f5_##_VAL(R_SERIAL2_STATUS_, overrun_, v5) << R_SERIAL2_STATUS__overrun__BITNR) | \ - (R_SERIAL2_STATUS__par_err__##f6_##_VAL(R_SERIAL2_STATUS_, par_err_, v6) << R_SERIAL2_STATUS__par_err__BITNR) | \ - (R_SERIAL2_STATUS__framing_err__##f7_##_VAL(R_SERIAL2_STATUS_, framing_err_, v7) << R_SERIAL2_STATUS__framing_err__BITNR) | \ - (R_SERIAL2_STATUS__data_avail__##f8_##_VAL(R_SERIAL2_STATUS_, data_avail_, v8) << R_SERIAL2_STATUS__data_avail__BITNR) \ -) - -#endif - -/* - * R_SERIAL2_TR_CTRL - * - type: WO - * - addr: 0xb0000071 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SERIAL2_TR_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SERIAL2_TR_CTRL. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_SERIAL2_TR_CTRL. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SERIAL2_TR_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - *R_SERIAL2_TR_CTRL__SADDR = ( \ - REG_INITIATED(R_SERIAL2_TR_CTRL_) \ - REG_VAL__R_SERIAL2_TR_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \ - ), \ - R_SERIAL2_TR_CTRL__WRITE(R_SERIAL2_TR_CTRL__ADDR, *R_SERIAL2_TR_CTRL__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SERIAL2_TR_CTRL__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SERIAL2_TR_CTRL. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_SERIAL2_TR_CTRL. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SERIAL2_TR_CTRL__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - *R_SERIAL2_TR_CTRL__SADDR = ( \ - REG_INITIATED(R_SERIAL2_TR_CTRL_) \ - REG_VAL__R_SERIAL2_TR_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SERIAL2_TR_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SERIAL2_TR_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - (R_SERIAL2_TR_CTRL__txd__##f1##__MASK & REG__##v1) | \ - (R_SERIAL2_TR_CTRL__tr_enable__##f2##__MASK & REG__##v2) | \ - (R_SERIAL2_TR_CTRL__auto_cts__##f3##__MASK & REG__##v3) | \ - (R_SERIAL2_TR_CTRL__stop_bits__##f4##__MASK & REG__##v4) | \ - (R_SERIAL2_TR_CTRL__tr_stick_par__##f5##__MASK & REG__##v5) | \ - (R_SERIAL2_TR_CTRL__tr_par__##f6##__MASK & REG__##v6) | \ - (R_SERIAL2_TR_CTRL__tr_par_en__##f7##__MASK & REG__##v7) | \ - (R_SERIAL2_TR_CTRL__tr_bitnr__##f8##__MASK & REG__##v8) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL2_TR_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL2_TR_CTRL. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL2_TR_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - (R_SERIAL2_TR_CTRL__txd__##f1##__VAL(R_SERIAL2_TR_CTRL_, txd_, v1) << R_SERIAL2_TR_CTRL__txd__BITNR) | \ - (R_SERIAL2_TR_CTRL__tr_enable__##f2##__VAL(R_SERIAL2_TR_CTRL_, tr_enable_, v2) << R_SERIAL2_TR_CTRL__tr_enable__BITNR) | \ - (R_SERIAL2_TR_CTRL__auto_cts__##f3##__VAL(R_SERIAL2_TR_CTRL_, auto_cts_, v3) << R_SERIAL2_TR_CTRL__auto_cts__BITNR) | \ - (R_SERIAL2_TR_CTRL__stop_bits__##f4##__VAL(R_SERIAL2_TR_CTRL_, stop_bits_, v4) << R_SERIAL2_TR_CTRL__stop_bits__BITNR) | \ - (R_SERIAL2_TR_CTRL__tr_stick_par__##f5##__VAL(R_SERIAL2_TR_CTRL_, tr_stick_par_, v5) << R_SERIAL2_TR_CTRL__tr_stick_par__BITNR) | \ - (R_SERIAL2_TR_CTRL__tr_par__##f6##__VAL(R_SERIAL2_TR_CTRL_, tr_par_, v6) << R_SERIAL2_TR_CTRL__tr_par__BITNR) | \ - (R_SERIAL2_TR_CTRL__tr_par_en__##f7##__VAL(R_SERIAL2_TR_CTRL_, tr_par_en_, v7) << R_SERIAL2_TR_CTRL__tr_par_en__BITNR) | \ - (R_SERIAL2_TR_CTRL__tr_bitnr__##f8##__VAL(R_SERIAL2_TR_CTRL_, tr_bitnr_, v8) << R_SERIAL2_TR_CTRL__tr_bitnr__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL2_TR_CTRL_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL2_TR_CTRL. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL2_TR_CTRL_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8) ( \ - (R_SERIAL2_TR_CTRL__txd__##f1_##_VAL(R_SERIAL2_TR_CTRL_, txd_, v1) << R_SERIAL2_TR_CTRL__txd__BITNR) | \ - (R_SERIAL2_TR_CTRL__tr_enable__##f2_##_VAL(R_SERIAL2_TR_CTRL_, tr_enable_, v2) << R_SERIAL2_TR_CTRL__tr_enable__BITNR) | \ - (R_SERIAL2_TR_CTRL__auto_cts__##f3_##_VAL(R_SERIAL2_TR_CTRL_, auto_cts_, v3) << R_SERIAL2_TR_CTRL__auto_cts__BITNR) | \ - (R_SERIAL2_TR_CTRL__stop_bits__##f4_##_VAL(R_SERIAL2_TR_CTRL_, stop_bits_, v4) << R_SERIAL2_TR_CTRL__stop_bits__BITNR) | \ - (R_SERIAL2_TR_CTRL__tr_stick_par__##f5_##_VAL(R_SERIAL2_TR_CTRL_, tr_stick_par_, v5) << R_SERIAL2_TR_CTRL__tr_stick_par__BITNR) | \ - (R_SERIAL2_TR_CTRL__tr_par__##f6_##_VAL(R_SERIAL2_TR_CTRL_, tr_par_, v6) << R_SERIAL2_TR_CTRL__tr_par__BITNR) | \ - (R_SERIAL2_TR_CTRL__tr_par_en__##f7_##_VAL(R_SERIAL2_TR_CTRL_, tr_par_en_, v7) << R_SERIAL2_TR_CTRL__tr_par_en__BITNR) | \ - (R_SERIAL2_TR_CTRL__tr_bitnr__##f8_##_VAL(R_SERIAL2_TR_CTRL_, tr_bitnr_, v8) << R_SERIAL2_TR_CTRL__tr_bitnr__BITNR) \ -) - -#endif - -/* - * R_SERIAL2_TR_DATA - * - type: WO - * - addr: 0xb0000070 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SERIAL2_TR_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SERIAL2_TR_DATA. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_SERIAL2_TR_DATA. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SERIAL2_TR_DATA(f1,v1) ( \ - *R_SERIAL2_TR_DATA__SADDR = ( \ - REG_INITIATED(R_SERIAL2_TR_DATA_) \ - REG_VAL__R_SERIAL2_TR_DATA_(f1##_,v1) \ - ), \ - R_SERIAL2_TR_DATA__WRITE(R_SERIAL2_TR_DATA__ADDR, *R_SERIAL2_TR_DATA__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SERIAL2_TR_DATA__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SERIAL2_TR_DATA. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_SERIAL2_TR_DATA. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SERIAL2_TR_DATA__SHADOW(f1,v1) ( \ - *R_SERIAL2_TR_DATA__SADDR = ( \ - REG_INITIATED(R_SERIAL2_TR_DATA_) \ - REG_VAL__R_SERIAL2_TR_DATA_(f1##_,v1) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SERIAL2_TR_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SERIAL2_TR_DATA(f1,v1) ( \ - (R_SERIAL2_TR_DATA__data_out__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL2_TR_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL2_TR_DATA. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL2_TR_DATA(f1,v1) ( \ - (R_SERIAL2_TR_DATA__data_out__##f1##__VAL(R_SERIAL2_TR_DATA_, data_out_, v1) << R_SERIAL2_TR_DATA__data_out__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL2_TR_DATA_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL2_TR_DATA. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL2_TR_DATA_(f1_,v1) ( \ - (R_SERIAL2_TR_DATA__data_out__##f1_##_VAL(R_SERIAL2_TR_DATA_, data_out_, v1) << R_SERIAL2_TR_DATA__data_out__BITNR) \ -) - -#endif - -/* - * R_SERIAL2_XOFF - * - type: WO - * - addr: 0xb0000074 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SERIAL2_XOFF -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SERIAL2_XOFF. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_SERIAL2_XOFF. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SERIAL2_XOFF(f1,v1,f2,v2,f3,v3) ( \ - *R_SERIAL2_XOFF__SADDR = ( \ - REG_INITIATED(R_SERIAL2_XOFF_) \ - REG_VAL__R_SERIAL2_XOFF_(f1##_,v1,f2##_,v2,f3##_,v3) \ - ), \ - R_SERIAL2_XOFF__WRITE(R_SERIAL2_XOFF__ADDR, *R_SERIAL2_XOFF__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SERIAL2_XOFF__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SERIAL2_XOFF. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_SERIAL2_XOFF. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SERIAL2_XOFF__SHADOW(f1,v1,f2,v2,f3,v3) ( \ - *R_SERIAL2_XOFF__SADDR = ( \ - REG_INITIATED(R_SERIAL2_XOFF_) \ - REG_VAL__R_SERIAL2_XOFF_(f1##_,v1,f2##_,v2,f3##_,v3) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SERIAL2_XOFF -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SERIAL2_XOFF(f1,v1,f2,v2,f3,v3) ( \ - (R_SERIAL2_XOFF__tx_stop__##f1##__MASK & REG__##v1) | \ - (R_SERIAL2_XOFF__auto_xoff__##f2##__MASK & REG__##v2) | \ - (R_SERIAL2_XOFF__xoff_char__##f3##__MASK & REG__##v3) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL2_XOFF -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL2_XOFF. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL2_XOFF(f1,v1,f2,v2,f3,v3) ( \ - (R_SERIAL2_XOFF__tx_stop__##f1##__VAL(R_SERIAL2_XOFF_, tx_stop_, v1) << R_SERIAL2_XOFF__tx_stop__BITNR) | \ - (R_SERIAL2_XOFF__auto_xoff__##f2##__VAL(R_SERIAL2_XOFF_, auto_xoff_, v2) << R_SERIAL2_XOFF__auto_xoff__BITNR) | \ - (R_SERIAL2_XOFF__xoff_char__##f3##__VAL(R_SERIAL2_XOFF_, xoff_char_, v3) << R_SERIAL2_XOFF__xoff_char__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL2_XOFF_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL2_XOFF. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL2_XOFF_(f1_,v1,f2_,v2,f3_,v3) ( \ - (R_SERIAL2_XOFF__tx_stop__##f1_##_VAL(R_SERIAL2_XOFF_, tx_stop_, v1) << R_SERIAL2_XOFF__tx_stop__BITNR) | \ - (R_SERIAL2_XOFF__auto_xoff__##f2_##_VAL(R_SERIAL2_XOFF_, auto_xoff_, v2) << R_SERIAL2_XOFF__auto_xoff__BITNR) | \ - (R_SERIAL2_XOFF__xoff_char__##f3_##_VAL(R_SERIAL2_XOFF_, xoff_char_, v3) << R_SERIAL2_XOFF__xoff_char__BITNR) \ -) - -#endif - -/* - * R_SERIAL3_BAUD - * - type: WO - * - addr: 0xb000007b - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SERIAL3_BAUD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SERIAL3_BAUD. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_SERIAL3_BAUD. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SERIAL3_BAUD(f1,v1,f2,v2) ( \ - *R_SERIAL3_BAUD__SADDR = ( \ - REG_INITIATED(R_SERIAL3_BAUD_) \ - REG_VAL__R_SERIAL3_BAUD_(f1##_,v1,f2##_,v2) \ - ), \ - R_SERIAL3_BAUD__WRITE(R_SERIAL3_BAUD__ADDR, *R_SERIAL3_BAUD__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SERIAL3_BAUD__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SERIAL3_BAUD. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_SERIAL3_BAUD. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SERIAL3_BAUD__SHADOW(f1,v1,f2,v2) ( \ - *R_SERIAL3_BAUD__SADDR = ( \ - REG_INITIATED(R_SERIAL3_BAUD_) \ - REG_VAL__R_SERIAL3_BAUD_(f1##_,v1,f2##_,v2) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SERIAL3_BAUD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SERIAL3_BAUD(f1,v1,f2,v2) ( \ - (R_SERIAL3_BAUD__tr_baud__##f1##__MASK & REG__##v1) | \ - (R_SERIAL3_BAUD__rec_baud__##f2##__MASK & REG__##v2) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL3_BAUD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL3_BAUD. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL3_BAUD(f1,v1,f2,v2) ( \ - (R_SERIAL3_BAUD__tr_baud__##f1##__VAL(R_SERIAL3_BAUD_, tr_baud_, v1) << R_SERIAL3_BAUD__tr_baud__BITNR) | \ - (R_SERIAL3_BAUD__rec_baud__##f2##__VAL(R_SERIAL3_BAUD_, rec_baud_, v2) << R_SERIAL3_BAUD__rec_baud__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL3_BAUD_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL3_BAUD. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL3_BAUD_(f1_,v1,f2_,v2) ( \ - (R_SERIAL3_BAUD__tr_baud__##f1_##_VAL(R_SERIAL3_BAUD_, tr_baud_, v1) << R_SERIAL3_BAUD__tr_baud__BITNR) | \ - (R_SERIAL3_BAUD__rec_baud__##f2_##_VAL(R_SERIAL3_BAUD_, rec_baud_, v2) << R_SERIAL3_BAUD__rec_baud__BITNR) \ -) - -#endif - -/* - * R_SERIAL3_CTRL - * - type: WO - * - addr: 0xb0000078 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SERIAL3_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SERIAL3_CTRL. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_SERIAL3_CTRL. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SERIAL3_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19) ( \ - *R_SERIAL3_CTRL__SADDR = ( \ - REG_INITIATED(R_SERIAL3_CTRL_) \ - REG_VAL__R_SERIAL3_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19) \ - ), \ - R_SERIAL3_CTRL__WRITE(R_SERIAL3_CTRL__ADDR, *R_SERIAL3_CTRL__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SERIAL3_CTRL__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SERIAL3_CTRL. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_SERIAL3_CTRL. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SERIAL3_CTRL__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19) ( \ - *R_SERIAL3_CTRL__SADDR = ( \ - REG_INITIATED(R_SERIAL3_CTRL_) \ - REG_VAL__R_SERIAL3_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SERIAL3_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SERIAL3_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19) ( \ - (R_SERIAL3_CTRL__tr_baud__##f1##__MASK & REG__##v1) | \ - (R_SERIAL3_CTRL__rec_baud__##f2##__MASK & REG__##v2) | \ - (R_SERIAL3_CTRL__dma_err__##f3##__MASK & REG__##v3) | \ - (R_SERIAL3_CTRL__rec_enable__##f4##__MASK & REG__##v4) | \ - (R_SERIAL3_CTRL__rts___##f5##__MASK & REG__##v5) | \ - (R_SERIAL3_CTRL__sampling__##f6##__MASK & REG__##v6) | \ - (R_SERIAL3_CTRL__rec_stick_par__##f7##__MASK & REG__##v7) | \ - (R_SERIAL3_CTRL__rec_par__##f8##__MASK & REG__##v8) | \ - (R_SERIAL3_CTRL__rec_par_en__##f9##__MASK & REG__##v9) | \ - (R_SERIAL3_CTRL__rec_bitnr__##f10##__MASK & REG__##v10) | \ - (R_SERIAL3_CTRL__txd__##f11##__MASK & REG__##v11) | \ - (R_SERIAL3_CTRL__tr_enable__##f12##__MASK & REG__##v12) | \ - (R_SERIAL3_CTRL__auto_cts__##f13##__MASK & REG__##v13) | \ - (R_SERIAL3_CTRL__stop_bits__##f14##__MASK & REG__##v14) | \ - (R_SERIAL3_CTRL__tr_stick_par__##f15##__MASK & REG__##v15) | \ - (R_SERIAL3_CTRL__tr_par__##f16##__MASK & REG__##v16) | \ - (R_SERIAL3_CTRL__tr_par_en__##f17##__MASK & REG__##v17) | \ - (R_SERIAL3_CTRL__tr_bitnr__##f18##__MASK & REG__##v18) | \ - (R_SERIAL3_CTRL__data_out__##f19##__MASK & REG__##v19) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL3_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL3_CTRL. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL3_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19) ( \ - (R_SERIAL3_CTRL__tr_baud__##f1##__VAL(R_SERIAL3_CTRL_, tr_baud_, v1) << R_SERIAL3_CTRL__tr_baud__BITNR) | \ - (R_SERIAL3_CTRL__rec_baud__##f2##__VAL(R_SERIAL3_CTRL_, rec_baud_, v2) << R_SERIAL3_CTRL__rec_baud__BITNR) | \ - (R_SERIAL3_CTRL__dma_err__##f3##__VAL(R_SERIAL3_CTRL_, dma_err_, v3) << R_SERIAL3_CTRL__dma_err__BITNR) | \ - (R_SERIAL3_CTRL__rec_enable__##f4##__VAL(R_SERIAL3_CTRL_, rec_enable_, v4) << R_SERIAL3_CTRL__rec_enable__BITNR) | \ - (R_SERIAL3_CTRL__rts___##f5##__VAL(R_SERIAL3_CTRL_, rts__, v5) << R_SERIAL3_CTRL__rts___BITNR) | \ - (R_SERIAL3_CTRL__sampling__##f6##__VAL(R_SERIAL3_CTRL_, sampling_, v6) << R_SERIAL3_CTRL__sampling__BITNR) | \ - (R_SERIAL3_CTRL__rec_stick_par__##f7##__VAL(R_SERIAL3_CTRL_, rec_stick_par_, v7) << R_SERIAL3_CTRL__rec_stick_par__BITNR) | \ - (R_SERIAL3_CTRL__rec_par__##f8##__VAL(R_SERIAL3_CTRL_, rec_par_, v8) << R_SERIAL3_CTRL__rec_par__BITNR) | \ - (R_SERIAL3_CTRL__rec_par_en__##f9##__VAL(R_SERIAL3_CTRL_, rec_par_en_, v9) << R_SERIAL3_CTRL__rec_par_en__BITNR) | \ - (R_SERIAL3_CTRL__rec_bitnr__##f10##__VAL(R_SERIAL3_CTRL_, rec_bitnr_, v10) << R_SERIAL3_CTRL__rec_bitnr__BITNR) | \ - (R_SERIAL3_CTRL__txd__##f11##__VAL(R_SERIAL3_CTRL_, txd_, v11) << R_SERIAL3_CTRL__txd__BITNR) | \ - (R_SERIAL3_CTRL__tr_enable__##f12##__VAL(R_SERIAL3_CTRL_, tr_enable_, v12) << R_SERIAL3_CTRL__tr_enable__BITNR) | \ - (R_SERIAL3_CTRL__auto_cts__##f13##__VAL(R_SERIAL3_CTRL_, auto_cts_, v13) << R_SERIAL3_CTRL__auto_cts__BITNR) | \ - (R_SERIAL3_CTRL__stop_bits__##f14##__VAL(R_SERIAL3_CTRL_, stop_bits_, v14) << R_SERIAL3_CTRL__stop_bits__BITNR) | \ - (R_SERIAL3_CTRL__tr_stick_par__##f15##__VAL(R_SERIAL3_CTRL_, tr_stick_par_, v15) << R_SERIAL3_CTRL__tr_stick_par__BITNR) | \ - (R_SERIAL3_CTRL__tr_par__##f16##__VAL(R_SERIAL3_CTRL_, tr_par_, v16) << R_SERIAL3_CTRL__tr_par__BITNR) | \ - (R_SERIAL3_CTRL__tr_par_en__##f17##__VAL(R_SERIAL3_CTRL_, tr_par_en_, v17) << R_SERIAL3_CTRL__tr_par_en__BITNR) | \ - (R_SERIAL3_CTRL__tr_bitnr__##f18##__VAL(R_SERIAL3_CTRL_, tr_bitnr_, v18) << R_SERIAL3_CTRL__tr_bitnr__BITNR) | \ - (R_SERIAL3_CTRL__data_out__##f19##__VAL(R_SERIAL3_CTRL_, data_out_, v19) << R_SERIAL3_CTRL__data_out__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL3_CTRL_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL3_CTRL. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL3_CTRL_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16,f17_,v17,f18_,v18,f19_,v19) ( \ - (R_SERIAL3_CTRL__tr_baud__##f1_##_VAL(R_SERIAL3_CTRL_, tr_baud_, v1) << R_SERIAL3_CTRL__tr_baud__BITNR) | \ - (R_SERIAL3_CTRL__rec_baud__##f2_##_VAL(R_SERIAL3_CTRL_, rec_baud_, v2) << R_SERIAL3_CTRL__rec_baud__BITNR) | \ - (R_SERIAL3_CTRL__dma_err__##f3_##_VAL(R_SERIAL3_CTRL_, dma_err_, v3) << R_SERIAL3_CTRL__dma_err__BITNR) | \ - (R_SERIAL3_CTRL__rec_enable__##f4_##_VAL(R_SERIAL3_CTRL_, rec_enable_, v4) << R_SERIAL3_CTRL__rec_enable__BITNR) | \ - (R_SERIAL3_CTRL__rts___##f5_##_VAL(R_SERIAL3_CTRL_, rts__, v5) << R_SERIAL3_CTRL__rts___BITNR) | \ - (R_SERIAL3_CTRL__sampling__##f6_##_VAL(R_SERIAL3_CTRL_, sampling_, v6) << R_SERIAL3_CTRL__sampling__BITNR) | \ - (R_SERIAL3_CTRL__rec_stick_par__##f7_##_VAL(R_SERIAL3_CTRL_, rec_stick_par_, v7) << R_SERIAL3_CTRL__rec_stick_par__BITNR) | \ - (R_SERIAL3_CTRL__rec_par__##f8_##_VAL(R_SERIAL3_CTRL_, rec_par_, v8) << R_SERIAL3_CTRL__rec_par__BITNR) | \ - (R_SERIAL3_CTRL__rec_par_en__##f9_##_VAL(R_SERIAL3_CTRL_, rec_par_en_, v9) << R_SERIAL3_CTRL__rec_par_en__BITNR) | \ - (R_SERIAL3_CTRL__rec_bitnr__##f10_##_VAL(R_SERIAL3_CTRL_, rec_bitnr_, v10) << R_SERIAL3_CTRL__rec_bitnr__BITNR) | \ - (R_SERIAL3_CTRL__txd__##f11_##_VAL(R_SERIAL3_CTRL_, txd_, v11) << R_SERIAL3_CTRL__txd__BITNR) | \ - (R_SERIAL3_CTRL__tr_enable__##f12_##_VAL(R_SERIAL3_CTRL_, tr_enable_, v12) << R_SERIAL3_CTRL__tr_enable__BITNR) | \ - (R_SERIAL3_CTRL__auto_cts__##f13_##_VAL(R_SERIAL3_CTRL_, auto_cts_, v13) << R_SERIAL3_CTRL__auto_cts__BITNR) | \ - (R_SERIAL3_CTRL__stop_bits__##f14_##_VAL(R_SERIAL3_CTRL_, stop_bits_, v14) << R_SERIAL3_CTRL__stop_bits__BITNR) | \ - (R_SERIAL3_CTRL__tr_stick_par__##f15_##_VAL(R_SERIAL3_CTRL_, tr_stick_par_, v15) << R_SERIAL3_CTRL__tr_stick_par__BITNR) | \ - (R_SERIAL3_CTRL__tr_par__##f16_##_VAL(R_SERIAL3_CTRL_, tr_par_, v16) << R_SERIAL3_CTRL__tr_par__BITNR) | \ - (R_SERIAL3_CTRL__tr_par_en__##f17_##_VAL(R_SERIAL3_CTRL_, tr_par_en_, v17) << R_SERIAL3_CTRL__tr_par_en__BITNR) | \ - (R_SERIAL3_CTRL__tr_bitnr__##f18_##_VAL(R_SERIAL3_CTRL_, tr_bitnr_, v18) << R_SERIAL3_CTRL__tr_bitnr__BITNR) | \ - (R_SERIAL3_CTRL__data_out__##f19_##_VAL(R_SERIAL3_CTRL_, data_out_, v19) << R_SERIAL3_CTRL__data_out__BITNR) \ -) - -#endif - -/* - * R_SERIAL3_READ - * - type: RO - * - addr: 0xb0000078 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SERIAL3_READ -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SERIAL3_READ(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \ - (R_SERIAL3_READ__xoff_detect__##f1##__MASK & REG__##v1) | \ - (R_SERIAL3_READ__cts___##f2##__MASK & REG__##v2) | \ - (R_SERIAL3_READ__tr_ready__##f3##__MASK & REG__##v3) | \ - (R_SERIAL3_READ__rxd__##f4##__MASK & REG__##v4) | \ - (R_SERIAL3_READ__overrun__##f5##__MASK & REG__##v5) | \ - (R_SERIAL3_READ__par_err__##f6##__MASK & REG__##v6) | \ - (R_SERIAL3_READ__framing_err__##f7##__MASK & REG__##v7) | \ - (R_SERIAL3_READ__data_avail__##f8##__MASK & REG__##v8) | \ - (R_SERIAL3_READ__data_in__##f9##__MASK & REG__##v9) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL3_READ -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL3_READ. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL3_READ(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \ - (R_SERIAL3_READ__xoff_detect__##f1##__VAL(R_SERIAL3_READ_, xoff_detect_, v1) << R_SERIAL3_READ__xoff_detect__BITNR) | \ - (R_SERIAL3_READ__cts___##f2##__VAL(R_SERIAL3_READ_, cts__, v2) << R_SERIAL3_READ__cts___BITNR) | \ - (R_SERIAL3_READ__tr_ready__##f3##__VAL(R_SERIAL3_READ_, tr_ready_, v3) << R_SERIAL3_READ__tr_ready__BITNR) | \ - (R_SERIAL3_READ__rxd__##f4##__VAL(R_SERIAL3_READ_, rxd_, v4) << R_SERIAL3_READ__rxd__BITNR) | \ - (R_SERIAL3_READ__overrun__##f5##__VAL(R_SERIAL3_READ_, overrun_, v5) << R_SERIAL3_READ__overrun__BITNR) | \ - (R_SERIAL3_READ__par_err__##f6##__VAL(R_SERIAL3_READ_, par_err_, v6) << R_SERIAL3_READ__par_err__BITNR) | \ - (R_SERIAL3_READ__framing_err__##f7##__VAL(R_SERIAL3_READ_, framing_err_, v7) << R_SERIAL3_READ__framing_err__BITNR) | \ - (R_SERIAL3_READ__data_avail__##f8##__VAL(R_SERIAL3_READ_, data_avail_, v8) << R_SERIAL3_READ__data_avail__BITNR) | \ - (R_SERIAL3_READ__data_in__##f9##__VAL(R_SERIAL3_READ_, data_in_, v9) << R_SERIAL3_READ__data_in__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL3_READ_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL3_READ. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL3_READ_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9) ( \ - (R_SERIAL3_READ__xoff_detect__##f1_##_VAL(R_SERIAL3_READ_, xoff_detect_, v1) << R_SERIAL3_READ__xoff_detect__BITNR) | \ - (R_SERIAL3_READ__cts___##f2_##_VAL(R_SERIAL3_READ_, cts__, v2) << R_SERIAL3_READ__cts___BITNR) | \ - (R_SERIAL3_READ__tr_ready__##f3_##_VAL(R_SERIAL3_READ_, tr_ready_, v3) << R_SERIAL3_READ__tr_ready__BITNR) | \ - (R_SERIAL3_READ__rxd__##f4_##_VAL(R_SERIAL3_READ_, rxd_, v4) << R_SERIAL3_READ__rxd__BITNR) | \ - (R_SERIAL3_READ__overrun__##f5_##_VAL(R_SERIAL3_READ_, overrun_, v5) << R_SERIAL3_READ__overrun__BITNR) | \ - (R_SERIAL3_READ__par_err__##f6_##_VAL(R_SERIAL3_READ_, par_err_, v6) << R_SERIAL3_READ__par_err__BITNR) | \ - (R_SERIAL3_READ__framing_err__##f7_##_VAL(R_SERIAL3_READ_, framing_err_, v7) << R_SERIAL3_READ__framing_err__BITNR) | \ - (R_SERIAL3_READ__data_avail__##f8_##_VAL(R_SERIAL3_READ_, data_avail_, v8) << R_SERIAL3_READ__data_avail__BITNR) | \ - (R_SERIAL3_READ__data_in__##f9_##_VAL(R_SERIAL3_READ_, data_in_, v9) << R_SERIAL3_READ__data_in__BITNR) \ -) - -#endif - -/* - * R_SERIAL3_REC_CTRL - * - type: WO - * - addr: 0xb000007a - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SERIAL3_REC_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SERIAL3_REC_CTRL. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_SERIAL3_REC_CTRL. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SERIAL3_REC_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - *R_SERIAL3_REC_CTRL__SADDR = ( \ - REG_INITIATED(R_SERIAL3_REC_CTRL_) \ - REG_VAL__R_SERIAL3_REC_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \ - ), \ - R_SERIAL3_REC_CTRL__WRITE(R_SERIAL3_REC_CTRL__ADDR, *R_SERIAL3_REC_CTRL__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SERIAL3_REC_CTRL__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SERIAL3_REC_CTRL. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_SERIAL3_REC_CTRL. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SERIAL3_REC_CTRL__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - *R_SERIAL3_REC_CTRL__SADDR = ( \ - REG_INITIATED(R_SERIAL3_REC_CTRL_) \ - REG_VAL__R_SERIAL3_REC_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SERIAL3_REC_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SERIAL3_REC_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - (R_SERIAL3_REC_CTRL__dma_err__##f1##__MASK & REG__##v1) | \ - (R_SERIAL3_REC_CTRL__rec_enable__##f2##__MASK & REG__##v2) | \ - (R_SERIAL3_REC_CTRL__rts___##f3##__MASK & REG__##v3) | \ - (R_SERIAL3_REC_CTRL__sampling__##f4##__MASK & REG__##v4) | \ - (R_SERIAL3_REC_CTRL__rec_stick_par__##f5##__MASK & REG__##v5) | \ - (R_SERIAL3_REC_CTRL__rec_par__##f6##__MASK & REG__##v6) | \ - (R_SERIAL3_REC_CTRL__rec_par_en__##f7##__MASK & REG__##v7) | \ - (R_SERIAL3_REC_CTRL__rec_bitnr__##f8##__MASK & REG__##v8) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL3_REC_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL3_REC_CTRL. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL3_REC_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - (R_SERIAL3_REC_CTRL__dma_err__##f1##__VAL(R_SERIAL3_REC_CTRL_, dma_err_, v1) << R_SERIAL3_REC_CTRL__dma_err__BITNR) | \ - (R_SERIAL3_REC_CTRL__rec_enable__##f2##__VAL(R_SERIAL3_REC_CTRL_, rec_enable_, v2) << R_SERIAL3_REC_CTRL__rec_enable__BITNR) | \ - (R_SERIAL3_REC_CTRL__rts___##f3##__VAL(R_SERIAL3_REC_CTRL_, rts__, v3) << R_SERIAL3_REC_CTRL__rts___BITNR) | \ - (R_SERIAL3_REC_CTRL__sampling__##f4##__VAL(R_SERIAL3_REC_CTRL_, sampling_, v4) << R_SERIAL3_REC_CTRL__sampling__BITNR) | \ - (R_SERIAL3_REC_CTRL__rec_stick_par__##f5##__VAL(R_SERIAL3_REC_CTRL_, rec_stick_par_, v5) << R_SERIAL3_REC_CTRL__rec_stick_par__BITNR) | \ - (R_SERIAL3_REC_CTRL__rec_par__##f6##__VAL(R_SERIAL3_REC_CTRL_, rec_par_, v6) << R_SERIAL3_REC_CTRL__rec_par__BITNR) | \ - (R_SERIAL3_REC_CTRL__rec_par_en__##f7##__VAL(R_SERIAL3_REC_CTRL_, rec_par_en_, v7) << R_SERIAL3_REC_CTRL__rec_par_en__BITNR) | \ - (R_SERIAL3_REC_CTRL__rec_bitnr__##f8##__VAL(R_SERIAL3_REC_CTRL_, rec_bitnr_, v8) << R_SERIAL3_REC_CTRL__rec_bitnr__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL3_REC_CTRL_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL3_REC_CTRL. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL3_REC_CTRL_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8) ( \ - (R_SERIAL3_REC_CTRL__dma_err__##f1_##_VAL(R_SERIAL3_REC_CTRL_, dma_err_, v1) << R_SERIAL3_REC_CTRL__dma_err__BITNR) | \ - (R_SERIAL3_REC_CTRL__rec_enable__##f2_##_VAL(R_SERIAL3_REC_CTRL_, rec_enable_, v2) << R_SERIAL3_REC_CTRL__rec_enable__BITNR) | \ - (R_SERIAL3_REC_CTRL__rts___##f3_##_VAL(R_SERIAL3_REC_CTRL_, rts__, v3) << R_SERIAL3_REC_CTRL__rts___BITNR) | \ - (R_SERIAL3_REC_CTRL__sampling__##f4_##_VAL(R_SERIAL3_REC_CTRL_, sampling_, v4) << R_SERIAL3_REC_CTRL__sampling__BITNR) | \ - (R_SERIAL3_REC_CTRL__rec_stick_par__##f5_##_VAL(R_SERIAL3_REC_CTRL_, rec_stick_par_, v5) << R_SERIAL3_REC_CTRL__rec_stick_par__BITNR) | \ - (R_SERIAL3_REC_CTRL__rec_par__##f6_##_VAL(R_SERIAL3_REC_CTRL_, rec_par_, v6) << R_SERIAL3_REC_CTRL__rec_par__BITNR) | \ - (R_SERIAL3_REC_CTRL__rec_par_en__##f7_##_VAL(R_SERIAL3_REC_CTRL_, rec_par_en_, v7) << R_SERIAL3_REC_CTRL__rec_par_en__BITNR) | \ - (R_SERIAL3_REC_CTRL__rec_bitnr__##f8_##_VAL(R_SERIAL3_REC_CTRL_, rec_bitnr_, v8) << R_SERIAL3_REC_CTRL__rec_bitnr__BITNR) \ -) - -#endif - -/* - * R_SERIAL3_REC_DATA - * - type: RO - * - addr: 0xb0000078 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SERIAL3_REC_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SERIAL3_REC_DATA(f1,v1) ( \ - (R_SERIAL3_REC_DATA__data_in__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL3_REC_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL3_REC_DATA. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL3_REC_DATA(f1,v1) ( \ - (R_SERIAL3_REC_DATA__data_in__##f1##__VAL(R_SERIAL3_REC_DATA_, data_in_, v1) << R_SERIAL3_REC_DATA__data_in__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL3_REC_DATA_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL3_REC_DATA. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL3_REC_DATA_(f1_,v1) ( \ - (R_SERIAL3_REC_DATA__data_in__##f1_##_VAL(R_SERIAL3_REC_DATA_, data_in_, v1) << R_SERIAL3_REC_DATA__data_in__BITNR) \ -) - -#endif - -/* - * R_SERIAL3_STATUS - * - type: RO - * - addr: 0xb0000079 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SERIAL3_STATUS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SERIAL3_STATUS(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - (R_SERIAL3_STATUS__xoff_detect__##f1##__MASK & REG__##v1) | \ - (R_SERIAL3_STATUS__cts___##f2##__MASK & REG__##v2) | \ - (R_SERIAL3_STATUS__tr_ready__##f3##__MASK & REG__##v3) | \ - (R_SERIAL3_STATUS__rxd__##f4##__MASK & REG__##v4) | \ - (R_SERIAL3_STATUS__overrun__##f5##__MASK & REG__##v5) | \ - (R_SERIAL3_STATUS__par_err__##f6##__MASK & REG__##v6) | \ - (R_SERIAL3_STATUS__framing_err__##f7##__MASK & REG__##v7) | \ - (R_SERIAL3_STATUS__data_avail__##f8##__MASK & REG__##v8) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL3_STATUS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL3_STATUS. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL3_STATUS(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - (R_SERIAL3_STATUS__xoff_detect__##f1##__VAL(R_SERIAL3_STATUS_, xoff_detect_, v1) << R_SERIAL3_STATUS__xoff_detect__BITNR) | \ - (R_SERIAL3_STATUS__cts___##f2##__VAL(R_SERIAL3_STATUS_, cts__, v2) << R_SERIAL3_STATUS__cts___BITNR) | \ - (R_SERIAL3_STATUS__tr_ready__##f3##__VAL(R_SERIAL3_STATUS_, tr_ready_, v3) << R_SERIAL3_STATUS__tr_ready__BITNR) | \ - (R_SERIAL3_STATUS__rxd__##f4##__VAL(R_SERIAL3_STATUS_, rxd_, v4) << R_SERIAL3_STATUS__rxd__BITNR) | \ - (R_SERIAL3_STATUS__overrun__##f5##__VAL(R_SERIAL3_STATUS_, overrun_, v5) << R_SERIAL3_STATUS__overrun__BITNR) | \ - (R_SERIAL3_STATUS__par_err__##f6##__VAL(R_SERIAL3_STATUS_, par_err_, v6) << R_SERIAL3_STATUS__par_err__BITNR) | \ - (R_SERIAL3_STATUS__framing_err__##f7##__VAL(R_SERIAL3_STATUS_, framing_err_, v7) << R_SERIAL3_STATUS__framing_err__BITNR) | \ - (R_SERIAL3_STATUS__data_avail__##f8##__VAL(R_SERIAL3_STATUS_, data_avail_, v8) << R_SERIAL3_STATUS__data_avail__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL3_STATUS_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL3_STATUS. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL3_STATUS_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8) ( \ - (R_SERIAL3_STATUS__xoff_detect__##f1_##_VAL(R_SERIAL3_STATUS_, xoff_detect_, v1) << R_SERIAL3_STATUS__xoff_detect__BITNR) | \ - (R_SERIAL3_STATUS__cts___##f2_##_VAL(R_SERIAL3_STATUS_, cts__, v2) << R_SERIAL3_STATUS__cts___BITNR) | \ - (R_SERIAL3_STATUS__tr_ready__##f3_##_VAL(R_SERIAL3_STATUS_, tr_ready_, v3) << R_SERIAL3_STATUS__tr_ready__BITNR) | \ - (R_SERIAL3_STATUS__rxd__##f4_##_VAL(R_SERIAL3_STATUS_, rxd_, v4) << R_SERIAL3_STATUS__rxd__BITNR) | \ - (R_SERIAL3_STATUS__overrun__##f5_##_VAL(R_SERIAL3_STATUS_, overrun_, v5) << R_SERIAL3_STATUS__overrun__BITNR) | \ - (R_SERIAL3_STATUS__par_err__##f6_##_VAL(R_SERIAL3_STATUS_, par_err_, v6) << R_SERIAL3_STATUS__par_err__BITNR) | \ - (R_SERIAL3_STATUS__framing_err__##f7_##_VAL(R_SERIAL3_STATUS_, framing_err_, v7) << R_SERIAL3_STATUS__framing_err__BITNR) | \ - (R_SERIAL3_STATUS__data_avail__##f8_##_VAL(R_SERIAL3_STATUS_, data_avail_, v8) << R_SERIAL3_STATUS__data_avail__BITNR) \ -) - -#endif - -/* - * R_SERIAL3_TR_CTRL - * - type: WO - * - addr: 0xb0000079 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SERIAL3_TR_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SERIAL3_TR_CTRL. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_SERIAL3_TR_CTRL. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SERIAL3_TR_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - *R_SERIAL3_TR_CTRL__SADDR = ( \ - REG_INITIATED(R_SERIAL3_TR_CTRL_) \ - REG_VAL__R_SERIAL3_TR_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \ - ), \ - R_SERIAL3_TR_CTRL__WRITE(R_SERIAL3_TR_CTRL__ADDR, *R_SERIAL3_TR_CTRL__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SERIAL3_TR_CTRL__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SERIAL3_TR_CTRL. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_SERIAL3_TR_CTRL. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SERIAL3_TR_CTRL__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - *R_SERIAL3_TR_CTRL__SADDR = ( \ - REG_INITIATED(R_SERIAL3_TR_CTRL_) \ - REG_VAL__R_SERIAL3_TR_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SERIAL3_TR_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SERIAL3_TR_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - (R_SERIAL3_TR_CTRL__txd__##f1##__MASK & REG__##v1) | \ - (R_SERIAL3_TR_CTRL__tr_enable__##f2##__MASK & REG__##v2) | \ - (R_SERIAL3_TR_CTRL__auto_cts__##f3##__MASK & REG__##v3) | \ - (R_SERIAL3_TR_CTRL__stop_bits__##f4##__MASK & REG__##v4) | \ - (R_SERIAL3_TR_CTRL__tr_stick_par__##f5##__MASK & REG__##v5) | \ - (R_SERIAL3_TR_CTRL__tr_par__##f6##__MASK & REG__##v6) | \ - (R_SERIAL3_TR_CTRL__tr_par_en__##f7##__MASK & REG__##v7) | \ - (R_SERIAL3_TR_CTRL__tr_bitnr__##f8##__MASK & REG__##v8) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL3_TR_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL3_TR_CTRL. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL3_TR_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - (R_SERIAL3_TR_CTRL__txd__##f1##__VAL(R_SERIAL3_TR_CTRL_, txd_, v1) << R_SERIAL3_TR_CTRL__txd__BITNR) | \ - (R_SERIAL3_TR_CTRL__tr_enable__##f2##__VAL(R_SERIAL3_TR_CTRL_, tr_enable_, v2) << R_SERIAL3_TR_CTRL__tr_enable__BITNR) | \ - (R_SERIAL3_TR_CTRL__auto_cts__##f3##__VAL(R_SERIAL3_TR_CTRL_, auto_cts_, v3) << R_SERIAL3_TR_CTRL__auto_cts__BITNR) | \ - (R_SERIAL3_TR_CTRL__stop_bits__##f4##__VAL(R_SERIAL3_TR_CTRL_, stop_bits_, v4) << R_SERIAL3_TR_CTRL__stop_bits__BITNR) | \ - (R_SERIAL3_TR_CTRL__tr_stick_par__##f5##__VAL(R_SERIAL3_TR_CTRL_, tr_stick_par_, v5) << R_SERIAL3_TR_CTRL__tr_stick_par__BITNR) | \ - (R_SERIAL3_TR_CTRL__tr_par__##f6##__VAL(R_SERIAL3_TR_CTRL_, tr_par_, v6) << R_SERIAL3_TR_CTRL__tr_par__BITNR) | \ - (R_SERIAL3_TR_CTRL__tr_par_en__##f7##__VAL(R_SERIAL3_TR_CTRL_, tr_par_en_, v7) << R_SERIAL3_TR_CTRL__tr_par_en__BITNR) | \ - (R_SERIAL3_TR_CTRL__tr_bitnr__##f8##__VAL(R_SERIAL3_TR_CTRL_, tr_bitnr_, v8) << R_SERIAL3_TR_CTRL__tr_bitnr__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL3_TR_CTRL_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL3_TR_CTRL. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL3_TR_CTRL_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8) ( \ - (R_SERIAL3_TR_CTRL__txd__##f1_##_VAL(R_SERIAL3_TR_CTRL_, txd_, v1) << R_SERIAL3_TR_CTRL__txd__BITNR) | \ - (R_SERIAL3_TR_CTRL__tr_enable__##f2_##_VAL(R_SERIAL3_TR_CTRL_, tr_enable_, v2) << R_SERIAL3_TR_CTRL__tr_enable__BITNR) | \ - (R_SERIAL3_TR_CTRL__auto_cts__##f3_##_VAL(R_SERIAL3_TR_CTRL_, auto_cts_, v3) << R_SERIAL3_TR_CTRL__auto_cts__BITNR) | \ - (R_SERIAL3_TR_CTRL__stop_bits__##f4_##_VAL(R_SERIAL3_TR_CTRL_, stop_bits_, v4) << R_SERIAL3_TR_CTRL__stop_bits__BITNR) | \ - (R_SERIAL3_TR_CTRL__tr_stick_par__##f5_##_VAL(R_SERIAL3_TR_CTRL_, tr_stick_par_, v5) << R_SERIAL3_TR_CTRL__tr_stick_par__BITNR) | \ - (R_SERIAL3_TR_CTRL__tr_par__##f6_##_VAL(R_SERIAL3_TR_CTRL_, tr_par_, v6) << R_SERIAL3_TR_CTRL__tr_par__BITNR) | \ - (R_SERIAL3_TR_CTRL__tr_par_en__##f7_##_VAL(R_SERIAL3_TR_CTRL_, tr_par_en_, v7) << R_SERIAL3_TR_CTRL__tr_par_en__BITNR) | \ - (R_SERIAL3_TR_CTRL__tr_bitnr__##f8_##_VAL(R_SERIAL3_TR_CTRL_, tr_bitnr_, v8) << R_SERIAL3_TR_CTRL__tr_bitnr__BITNR) \ -) - -#endif - -/* - * R_SERIAL3_TR_DATA - * - type: WO - * - addr: 0xb0000078 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SERIAL3_TR_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SERIAL3_TR_DATA. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_SERIAL3_TR_DATA. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SERIAL3_TR_DATA(f1,v1) ( \ - *R_SERIAL3_TR_DATA__SADDR = ( \ - REG_INITIATED(R_SERIAL3_TR_DATA_) \ - REG_VAL__R_SERIAL3_TR_DATA_(f1##_,v1) \ - ), \ - R_SERIAL3_TR_DATA__WRITE(R_SERIAL3_TR_DATA__ADDR, *R_SERIAL3_TR_DATA__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SERIAL3_TR_DATA__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SERIAL3_TR_DATA. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_SERIAL3_TR_DATA. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SERIAL3_TR_DATA__SHADOW(f1,v1) ( \ - *R_SERIAL3_TR_DATA__SADDR = ( \ - REG_INITIATED(R_SERIAL3_TR_DATA_) \ - REG_VAL__R_SERIAL3_TR_DATA_(f1##_,v1) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SERIAL3_TR_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SERIAL3_TR_DATA(f1,v1) ( \ - (R_SERIAL3_TR_DATA__data_out__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL3_TR_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL3_TR_DATA. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL3_TR_DATA(f1,v1) ( \ - (R_SERIAL3_TR_DATA__data_out__##f1##__VAL(R_SERIAL3_TR_DATA_, data_out_, v1) << R_SERIAL3_TR_DATA__data_out__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL3_TR_DATA_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL3_TR_DATA. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL3_TR_DATA_(f1_,v1) ( \ - (R_SERIAL3_TR_DATA__data_out__##f1_##_VAL(R_SERIAL3_TR_DATA_, data_out_, v1) << R_SERIAL3_TR_DATA__data_out__BITNR) \ -) - -#endif - -/* - * R_SERIAL3_XOFF - * - type: WO - * - addr: 0xb000007c - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SERIAL3_XOFF -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SERIAL3_XOFF. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_SERIAL3_XOFF. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SERIAL3_XOFF(f1,v1,f2,v2,f3,v3) ( \ - *R_SERIAL3_XOFF__SADDR = ( \ - REG_INITIATED(R_SERIAL3_XOFF_) \ - REG_VAL__R_SERIAL3_XOFF_(f1##_,v1,f2##_,v2,f3##_,v3) \ - ), \ - R_SERIAL3_XOFF__WRITE(R_SERIAL3_XOFF__ADDR, *R_SERIAL3_XOFF__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SERIAL3_XOFF__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SERIAL3_XOFF. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_SERIAL3_XOFF. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SERIAL3_XOFF__SHADOW(f1,v1,f2,v2,f3,v3) ( \ - *R_SERIAL3_XOFF__SADDR = ( \ - REG_INITIATED(R_SERIAL3_XOFF_) \ - REG_VAL__R_SERIAL3_XOFF_(f1##_,v1,f2##_,v2,f3##_,v3) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SERIAL3_XOFF -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SERIAL3_XOFF(f1,v1,f2,v2,f3,v3) ( \ - (R_SERIAL3_XOFF__tx_stop__##f1##__MASK & REG__##v1) | \ - (R_SERIAL3_XOFF__auto_xoff__##f2##__MASK & REG__##v2) | \ - (R_SERIAL3_XOFF__xoff_char__##f3##__MASK & REG__##v3) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL3_XOFF -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL3_XOFF. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL3_XOFF(f1,v1,f2,v2,f3,v3) ( \ - (R_SERIAL3_XOFF__tx_stop__##f1##__VAL(R_SERIAL3_XOFF_, tx_stop_, v1) << R_SERIAL3_XOFF__tx_stop__BITNR) | \ - (R_SERIAL3_XOFF__auto_xoff__##f2##__VAL(R_SERIAL3_XOFF_, auto_xoff_, v2) << R_SERIAL3_XOFF__auto_xoff__BITNR) | \ - (R_SERIAL3_XOFF__xoff_char__##f3##__VAL(R_SERIAL3_XOFF_, xoff_char_, v3) << R_SERIAL3_XOFF__xoff_char__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL3_XOFF_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL3_XOFF. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL3_XOFF_(f1_,v1,f2_,v2,f3_,v3) ( \ - (R_SERIAL3_XOFF__tx_stop__##f1_##_VAL(R_SERIAL3_XOFF_, tx_stop_, v1) << R_SERIAL3_XOFF__tx_stop__BITNR) | \ - (R_SERIAL3_XOFF__auto_xoff__##f2_##_VAL(R_SERIAL3_XOFF_, auto_xoff_, v2) << R_SERIAL3_XOFF__auto_xoff__BITNR) | \ - (R_SERIAL3_XOFF__xoff_char__##f3_##_VAL(R_SERIAL3_XOFF_, xoff_char_, v3) << R_SERIAL3_XOFF__xoff_char__BITNR) \ -) - -#endif - -/* - * R_SERIAL_PRESCALE - * - type: WO - * - addr: 0xb00000f2 - * - group: Timer registers - */ - -#if USE_GROUP__Timer_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SERIAL_PRESCALE -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SERIAL_PRESCALE. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_SERIAL_PRESCALE. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SERIAL_PRESCALE(f1,v1) ( \ - *R_SERIAL_PRESCALE__SADDR = ( \ - REG_INITIATED(R_SERIAL_PRESCALE_) \ - REG_VAL__R_SERIAL_PRESCALE_(f1##_,v1) \ - ), \ - R_SERIAL_PRESCALE__WRITE(R_SERIAL_PRESCALE__ADDR, *R_SERIAL_PRESCALE__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SERIAL_PRESCALE__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SERIAL_PRESCALE. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_SERIAL_PRESCALE. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SERIAL_PRESCALE__SHADOW(f1,v1) ( \ - *R_SERIAL_PRESCALE__SADDR = ( \ - REG_INITIATED(R_SERIAL_PRESCALE_) \ - REG_VAL__R_SERIAL_PRESCALE_(f1##_,v1) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SERIAL_PRESCALE -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SERIAL_PRESCALE(f1,v1) ( \ - (R_SERIAL_PRESCALE__ser_presc__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL_PRESCALE -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL_PRESCALE. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL_PRESCALE(f1,v1) ( \ - (R_SERIAL_PRESCALE__ser_presc__##f1##__VAL(R_SERIAL_PRESCALE_, ser_presc_, v1) << R_SERIAL_PRESCALE__ser_presc__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SERIAL_PRESCALE_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SERIAL_PRESCALE. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SERIAL_PRESCALE_(f1_,v1) ( \ - (R_SERIAL_PRESCALE__ser_presc__##f1_##_VAL(R_SERIAL_PRESCALE_, ser_presc_, v1) << R_SERIAL_PRESCALE__ser_presc__BITNR) \ -) - -#endif - -/* - * R_SER_PRESC_STATUS - * - type: RO - * - addr: 0xb00000f2 - * - group: Timer registers - */ - -#if USE_GROUP__Timer_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SER_PRESC_STATUS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SER_PRESC_STATUS(f1,v1) ( \ - (R_SER_PRESC_STATUS__ser_status__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SER_PRESC_STATUS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SER_PRESC_STATUS. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SER_PRESC_STATUS(f1,v1) ( \ - (R_SER_PRESC_STATUS__ser_status__##f1##__VAL(R_SER_PRESC_STATUS_, ser_status_, v1) << R_SER_PRESC_STATUS__ser_status__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SER_PRESC_STATUS_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SER_PRESC_STATUS. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SER_PRESC_STATUS_(f1_,v1) ( \ - (R_SER_PRESC_STATUS__ser_status__##f1_##_VAL(R_SER_PRESC_STATUS_, ser_status_, v1) << R_SER_PRESC_STATUS__ser_status__BITNR) \ -) - -#endif - -/* - * R_SET_EOP - * - type: WO - * - addr: 0xb000003c - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SET_EOP -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SET_EOP. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_SET_EOP. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SET_EOP(f1,v1,f2,v2,f3,v3,f4,v4) ( \ - *R_SET_EOP__SADDR = ( \ - REG_INITIATED(R_SET_EOP_) \ - REG_VAL__R_SET_EOP_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4) \ - ), \ - R_SET_EOP__WRITE(R_SET_EOP__ADDR, *R_SET_EOP__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SET_EOP__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SET_EOP. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_SET_EOP. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SET_EOP__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4) ( \ - *R_SET_EOP__SADDR = ( \ - REG_INITIATED(R_SET_EOP_) \ - REG_VAL__R_SET_EOP_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SET_EOP -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SET_EOP(f1,v1,f2,v2,f3,v3,f4,v4) ( \ - (R_SET_EOP__ch9_eop__##f1##__MASK & REG__##v1) | \ - (R_SET_EOP__ch7_eop__##f2##__MASK & REG__##v2) | \ - (R_SET_EOP__ch5_eop__##f3##__MASK & REG__##v3) | \ - (R_SET_EOP__ch3_eop__##f4##__MASK & REG__##v4) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SET_EOP -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SET_EOP. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SET_EOP(f1,v1,f2,v2,f3,v3,f4,v4) ( \ - (R_SET_EOP__ch9_eop__##f1##__VAL(R_SET_EOP_, ch9_eop_, v1) << R_SET_EOP__ch9_eop__BITNR) | \ - (R_SET_EOP__ch7_eop__##f2##__VAL(R_SET_EOP_, ch7_eop_, v2) << R_SET_EOP__ch7_eop__BITNR) | \ - (R_SET_EOP__ch5_eop__##f3##__VAL(R_SET_EOP_, ch5_eop_, v3) << R_SET_EOP__ch5_eop__BITNR) | \ - (R_SET_EOP__ch3_eop__##f4##__VAL(R_SET_EOP_, ch3_eop_, v4) << R_SET_EOP__ch3_eop__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SET_EOP_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SET_EOP. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SET_EOP_(f1_,v1,f2_,v2,f3_,v3,f4_,v4) ( \ - (R_SET_EOP__ch9_eop__##f1_##_VAL(R_SET_EOP_, ch9_eop_, v1) << R_SET_EOP__ch9_eop__BITNR) | \ - (R_SET_EOP__ch7_eop__##f2_##_VAL(R_SET_EOP_, ch7_eop_, v2) << R_SET_EOP__ch7_eop__BITNR) | \ - (R_SET_EOP__ch5_eop__##f3_##_VAL(R_SET_EOP_, ch5_eop_, v3) << R_SET_EOP__ch5_eop__BITNR) | \ - (R_SET_EOP__ch3_eop__##f4_##_VAL(R_SET_EOP_, ch3_eop_, v4) << R_SET_EOP__ch3_eop__BITNR) \ -) - -#endif - -/* - * R_SHARED_RAM_ADDR - * - type: WO - * - addr: 0xb0000044 - * - group: Shared RAM interface registers - */ - -#if USE_GROUP__Shared_RAM_interface_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SHARED_RAM_ADDR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SHARED_RAM_ADDR. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_SHARED_RAM_ADDR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SHARED_RAM_ADDR(f1,v1) ( \ - *R_SHARED_RAM_ADDR__SADDR = ( \ - REG_INITIATED(R_SHARED_RAM_ADDR_) \ - REG_VAL__R_SHARED_RAM_ADDR_(f1##_,v1) \ - ), \ - R_SHARED_RAM_ADDR__WRITE(R_SHARED_RAM_ADDR__ADDR, *R_SHARED_RAM_ADDR__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SHARED_RAM_ADDR__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SHARED_RAM_ADDR. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_SHARED_RAM_ADDR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SHARED_RAM_ADDR__SHADOW(f1,v1) ( \ - *R_SHARED_RAM_ADDR__SADDR = ( \ - REG_INITIATED(R_SHARED_RAM_ADDR_) \ - REG_VAL__R_SHARED_RAM_ADDR_(f1##_,v1) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SHARED_RAM_ADDR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SHARED_RAM_ADDR(f1,v1) ( \ - (R_SHARED_RAM_ADDR__base_addr__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SHARED_RAM_ADDR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SHARED_RAM_ADDR. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SHARED_RAM_ADDR(f1,v1) ( \ - (R_SHARED_RAM_ADDR__base_addr__##f1##__VAL(R_SHARED_RAM_ADDR_, base_addr_, v1) << R_SHARED_RAM_ADDR__base_addr__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SHARED_RAM_ADDR_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SHARED_RAM_ADDR. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SHARED_RAM_ADDR_(f1_,v1) ( \ - (R_SHARED_RAM_ADDR__base_addr__##f1_##_VAL(R_SHARED_RAM_ADDR_, base_addr_, v1) << R_SHARED_RAM_ADDR__base_addr__BITNR) \ -) - -#endif - -/* - * R_SHARED_RAM_CONFIG - * - type: WO - * - addr: 0xb0000040 - * - group: Shared RAM interface registers - */ - -#if USE_GROUP__Shared_RAM_interface_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SHARED_RAM_CONFIG -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SHARED_RAM_CONFIG. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_SHARED_RAM_CONFIG. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SHARED_RAM_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4) ( \ - *R_SHARED_RAM_CONFIG__SADDR = ( \ - REG_INITIATED(R_SHARED_RAM_CONFIG_) \ - REG_VAL__R_SHARED_RAM_CONFIG_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4) \ - ), \ - R_SHARED_RAM_CONFIG__WRITE(R_SHARED_RAM_CONFIG__ADDR, *R_SHARED_RAM_CONFIG__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SHARED_RAM_CONFIG__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SHARED_RAM_CONFIG. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_SHARED_RAM_CONFIG. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SHARED_RAM_CONFIG__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4) ( \ - *R_SHARED_RAM_CONFIG__SADDR = ( \ - REG_INITIATED(R_SHARED_RAM_CONFIG_) \ - REG_VAL__R_SHARED_RAM_CONFIG_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SHARED_RAM_CONFIG -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SHARED_RAM_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4) ( \ - (R_SHARED_RAM_CONFIG__width__##f1##__MASK & REG__##v1) | \ - (R_SHARED_RAM_CONFIG__enable__##f2##__MASK & REG__##v2) | \ - (R_SHARED_RAM_CONFIG__pint__##f3##__MASK & REG__##v3) | \ - (R_SHARED_RAM_CONFIG__clri__##f4##__MASK & REG__##v4) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SHARED_RAM_CONFIG -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SHARED_RAM_CONFIG. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SHARED_RAM_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4) ( \ - (R_SHARED_RAM_CONFIG__width__##f1##__VAL(R_SHARED_RAM_CONFIG_, width_, v1) << R_SHARED_RAM_CONFIG__width__BITNR) | \ - (R_SHARED_RAM_CONFIG__enable__##f2##__VAL(R_SHARED_RAM_CONFIG_, enable_, v2) << R_SHARED_RAM_CONFIG__enable__BITNR) | \ - (R_SHARED_RAM_CONFIG__pint__##f3##__VAL(R_SHARED_RAM_CONFIG_, pint_, v3) << R_SHARED_RAM_CONFIG__pint__BITNR) | \ - (R_SHARED_RAM_CONFIG__clri__##f4##__VAL(R_SHARED_RAM_CONFIG_, clri_, v4) << R_SHARED_RAM_CONFIG__clri__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SHARED_RAM_CONFIG_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SHARED_RAM_CONFIG. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SHARED_RAM_CONFIG_(f1_,v1,f2_,v2,f3_,v3,f4_,v4) ( \ - (R_SHARED_RAM_CONFIG__width__##f1_##_VAL(R_SHARED_RAM_CONFIG_, width_, v1) << R_SHARED_RAM_CONFIG__width__BITNR) | \ - (R_SHARED_RAM_CONFIG__enable__##f2_##_VAL(R_SHARED_RAM_CONFIG_, enable_, v2) << R_SHARED_RAM_CONFIG__enable__BITNR) | \ - (R_SHARED_RAM_CONFIG__pint__##f3_##_VAL(R_SHARED_RAM_CONFIG_, pint_, v3) << R_SHARED_RAM_CONFIG__pint__BITNR) | \ - (R_SHARED_RAM_CONFIG__clri__##f4_##_VAL(R_SHARED_RAM_CONFIG_, clri_, v4) << R_SHARED_RAM_CONFIG__clri__BITNR) \ -) - -#endif - -/* - * R_SINGLE_STEP - * - type: WO - * - addr: 0xb00000fe - * - group: Test mode registers - */ - -#if USE_GROUP__Test_mode_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SINGLE_STEP -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SINGLE_STEP. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_SINGLE_STEP. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SINGLE_STEP(f1,v1,f2,v2,f3,v3,f4,v4) ( \ - *R_SINGLE_STEP__SADDR = ( \ - REG_INITIATED(R_SINGLE_STEP_) \ - REG_VAL__R_SINGLE_STEP_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4) \ - ), \ - R_SINGLE_STEP__WRITE(R_SINGLE_STEP__ADDR, *R_SINGLE_STEP__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SINGLE_STEP__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SINGLE_STEP. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_SINGLE_STEP. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SINGLE_STEP__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4) ( \ - *R_SINGLE_STEP__SADDR = ( \ - REG_INITIATED(R_SINGLE_STEP_) \ - REG_VAL__R_SINGLE_STEP_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SINGLE_STEP -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SINGLE_STEP(f1,v1,f2,v2,f3,v3,f4,v4) ( \ - (R_SINGLE_STEP__single_step__##f1##__MASK & REG__##v1) | \ - (R_SINGLE_STEP__step_wr__##f2##__MASK & REG__##v2) | \ - (R_SINGLE_STEP__step_rd__##f3##__MASK & REG__##v3) | \ - (R_SINGLE_STEP__step_fetch__##f4##__MASK & REG__##v4) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SINGLE_STEP -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SINGLE_STEP. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SINGLE_STEP(f1,v1,f2,v2,f3,v3,f4,v4) ( \ - (R_SINGLE_STEP__single_step__##f1##__VAL(R_SINGLE_STEP_, single_step_, v1) << R_SINGLE_STEP__single_step__BITNR) | \ - (R_SINGLE_STEP__step_wr__##f2##__VAL(R_SINGLE_STEP_, step_wr_, v2) << R_SINGLE_STEP__step_wr__BITNR) | \ - (R_SINGLE_STEP__step_rd__##f3##__VAL(R_SINGLE_STEP_, step_rd_, v3) << R_SINGLE_STEP__step_rd__BITNR) | \ - (R_SINGLE_STEP__step_fetch__##f4##__VAL(R_SINGLE_STEP_, step_fetch_, v4) << R_SINGLE_STEP__step_fetch__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SINGLE_STEP_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SINGLE_STEP. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SINGLE_STEP_(f1_,v1,f2_,v2,f3_,v3,f4_,v4) ( \ - (R_SINGLE_STEP__single_step__##f1_##_VAL(R_SINGLE_STEP_, single_step_, v1) << R_SINGLE_STEP__single_step__BITNR) | \ - (R_SINGLE_STEP__step_wr__##f2_##_VAL(R_SINGLE_STEP_, step_wr_, v2) << R_SINGLE_STEP__step_wr__BITNR) | \ - (R_SINGLE_STEP__step_rd__##f3_##_VAL(R_SINGLE_STEP_, step_rd_, v3) << R_SINGLE_STEP__step_rd__BITNR) | \ - (R_SINGLE_STEP__step_fetch__##f4_##_VAL(R_SINGLE_STEP_, step_fetch_, v4) << R_SINGLE_STEP__step_fetch__BITNR) \ -) - -#endif - -/* - * R_SYNC_SERIAL1_CTRL - * - type: WO - * - addr: 0xb0000068 - * - group: Syncrounous serial port registers - */ - -#if USE_GROUP__Syncrounous_serial_port_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SYNC_SERIAL1_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SYNC_SERIAL1_CTRL. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_SYNC_SERIAL1_CTRL. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SYNC_SERIAL1_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23) ( \ - *R_SYNC_SERIAL1_CTRL__SADDR = ( \ - REG_INITIATED(R_SYNC_SERIAL1_CTRL_) \ - REG_VAL__R_SYNC_SERIAL1_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20,f21##_,v21,f22##_,v22,f23##_,v23) \ - ), \ - R_SYNC_SERIAL1_CTRL__WRITE(R_SYNC_SERIAL1_CTRL__ADDR, *R_SYNC_SERIAL1_CTRL__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SYNC_SERIAL1_CTRL__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SYNC_SERIAL1_CTRL. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_SYNC_SERIAL1_CTRL. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SYNC_SERIAL1_CTRL__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23) ( \ - *R_SYNC_SERIAL1_CTRL__SADDR = ( \ - REG_INITIATED(R_SYNC_SERIAL1_CTRL_) \ - REG_VAL__R_SYNC_SERIAL1_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20,f21##_,v21,f22##_,v22,f23##_,v23) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SYNC_SERIAL1_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SYNC_SERIAL1_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23) ( \ - (R_SYNC_SERIAL1_CTRL__tr_baud__##f1##__MASK & REG__##v1) | \ - (R_SYNC_SERIAL1_CTRL__dma_enable__##f2##__MASK & REG__##v2) | \ - (R_SYNC_SERIAL1_CTRL__mode__##f3##__MASK & REG__##v3) | \ - (R_SYNC_SERIAL1_CTRL__error__##f4##__MASK & REG__##v4) | \ - (R_SYNC_SERIAL1_CTRL__rec_enable__##f5##__MASK & REG__##v5) | \ - (R_SYNC_SERIAL1_CTRL__f_synctype__##f6##__MASK & REG__##v6) | \ - (R_SYNC_SERIAL1_CTRL__f_syncsize__##f7##__MASK & REG__##v7) | \ - (R_SYNC_SERIAL1_CTRL__f_sync__##f8##__MASK & REG__##v8) | \ - (R_SYNC_SERIAL1_CTRL__clk_mode__##f9##__MASK & REG__##v9) | \ - (R_SYNC_SERIAL1_CTRL__clk_halt__##f10##__MASK & REG__##v10) | \ - (R_SYNC_SERIAL1_CTRL__bitorder__##f11##__MASK & REG__##v11) | \ - (R_SYNC_SERIAL1_CTRL__tr_enable__##f12##__MASK & REG__##v12) | \ - (R_SYNC_SERIAL1_CTRL__wordsize__##f13##__MASK & REG__##v13) | \ - (R_SYNC_SERIAL1_CTRL__buf_empty__##f14##__MASK & REG__##v14) | \ - (R_SYNC_SERIAL1_CTRL__buf_full__##f15##__MASK & REG__##v15) | \ - (R_SYNC_SERIAL1_CTRL__flow_ctrl__##f16##__MASK & REG__##v16) | \ - (R_SYNC_SERIAL1_CTRL__clk_polarity__##f17##__MASK & REG__##v17) | \ - (R_SYNC_SERIAL1_CTRL__frame_polarity__##f18##__MASK & REG__##v18) | \ - (R_SYNC_SERIAL1_CTRL__status_polarity__##f19##__MASK & REG__##v19) | \ - (R_SYNC_SERIAL1_CTRL__clk_driver__##f20##__MASK & REG__##v20) | \ - (R_SYNC_SERIAL1_CTRL__frame_driver__##f21##__MASK & REG__##v21) | \ - (R_SYNC_SERIAL1_CTRL__status_driver__##f22##__MASK & REG__##v22) | \ - (R_SYNC_SERIAL1_CTRL__def_out0__##f23##__MASK & REG__##v23) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SYNC_SERIAL1_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SYNC_SERIAL1_CTRL. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SYNC_SERIAL1_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23) ( \ - (R_SYNC_SERIAL1_CTRL__tr_baud__##f1##__VAL(R_SYNC_SERIAL1_CTRL_, tr_baud_, v1) << R_SYNC_SERIAL1_CTRL__tr_baud__BITNR) | \ - (R_SYNC_SERIAL1_CTRL__dma_enable__##f2##__VAL(R_SYNC_SERIAL1_CTRL_, dma_enable_, v2) << R_SYNC_SERIAL1_CTRL__dma_enable__BITNR) | \ - (R_SYNC_SERIAL1_CTRL__mode__##f3##__VAL(R_SYNC_SERIAL1_CTRL_, mode_, v3) << R_SYNC_SERIAL1_CTRL__mode__BITNR) | \ - (R_SYNC_SERIAL1_CTRL__error__##f4##__VAL(R_SYNC_SERIAL1_CTRL_, error_, v4) << R_SYNC_SERIAL1_CTRL__error__BITNR) | \ - (R_SYNC_SERIAL1_CTRL__rec_enable__##f5##__VAL(R_SYNC_SERIAL1_CTRL_, rec_enable_, v5) << R_SYNC_SERIAL1_CTRL__rec_enable__BITNR) | \ - (R_SYNC_SERIAL1_CTRL__f_synctype__##f6##__VAL(R_SYNC_SERIAL1_CTRL_, f_synctype_, v6) << R_SYNC_SERIAL1_CTRL__f_synctype__BITNR) | \ - (R_SYNC_SERIAL1_CTRL__f_syncsize__##f7##__VAL(R_SYNC_SERIAL1_CTRL_, f_syncsize_, v7) << R_SYNC_SERIAL1_CTRL__f_syncsize__BITNR) | \ - (R_SYNC_SERIAL1_CTRL__f_sync__##f8##__VAL(R_SYNC_SERIAL1_CTRL_, f_sync_, v8) << R_SYNC_SERIAL1_CTRL__f_sync__BITNR) | \ - (R_SYNC_SERIAL1_CTRL__clk_mode__##f9##__VAL(R_SYNC_SERIAL1_CTRL_, clk_mode_, v9) << R_SYNC_SERIAL1_CTRL__clk_mode__BITNR) | \ - (R_SYNC_SERIAL1_CTRL__clk_halt__##f10##__VAL(R_SYNC_SERIAL1_CTRL_, clk_halt_, v10) << R_SYNC_SERIAL1_CTRL__clk_halt__BITNR) | \ - (R_SYNC_SERIAL1_CTRL__bitorder__##f11##__VAL(R_SYNC_SERIAL1_CTRL_, bitorder_, v11) << R_SYNC_SERIAL1_CTRL__bitorder__BITNR) | \ - (R_SYNC_SERIAL1_CTRL__tr_enable__##f12##__VAL(R_SYNC_SERIAL1_CTRL_, tr_enable_, v12) << R_SYNC_SERIAL1_CTRL__tr_enable__BITNR) | \ - (R_SYNC_SERIAL1_CTRL__wordsize__##f13##__VAL(R_SYNC_SERIAL1_CTRL_, wordsize_, v13) << R_SYNC_SERIAL1_CTRL__wordsize__BITNR) | \ - (R_SYNC_SERIAL1_CTRL__buf_empty__##f14##__VAL(R_SYNC_SERIAL1_CTRL_, buf_empty_, v14) << R_SYNC_SERIAL1_CTRL__buf_empty__BITNR) | \ - (R_SYNC_SERIAL1_CTRL__buf_full__##f15##__VAL(R_SYNC_SERIAL1_CTRL_, buf_full_, v15) << R_SYNC_SERIAL1_CTRL__buf_full__BITNR) | \ - (R_SYNC_SERIAL1_CTRL__flow_ctrl__##f16##__VAL(R_SYNC_SERIAL1_CTRL_, flow_ctrl_, v16) << R_SYNC_SERIAL1_CTRL__flow_ctrl__BITNR) | \ - (R_SYNC_SERIAL1_CTRL__clk_polarity__##f17##__VAL(R_SYNC_SERIAL1_CTRL_, clk_polarity_, v17) << R_SYNC_SERIAL1_CTRL__clk_polarity__BITNR) | \ - (R_SYNC_SERIAL1_CTRL__frame_polarity__##f18##__VAL(R_SYNC_SERIAL1_CTRL_, frame_polarity_, v18) << R_SYNC_SERIAL1_CTRL__frame_polarity__BITNR) | \ - (R_SYNC_SERIAL1_CTRL__status_polarity__##f19##__VAL(R_SYNC_SERIAL1_CTRL_, status_polarity_, v19) << R_SYNC_SERIAL1_CTRL__status_polarity__BITNR) | \ - (R_SYNC_SERIAL1_CTRL__clk_driver__##f20##__VAL(R_SYNC_SERIAL1_CTRL_, clk_driver_, v20) << R_SYNC_SERIAL1_CTRL__clk_driver__BITNR) | \ - (R_SYNC_SERIAL1_CTRL__frame_driver__##f21##__VAL(R_SYNC_SERIAL1_CTRL_, frame_driver_, v21) << R_SYNC_SERIAL1_CTRL__frame_driver__BITNR) | \ - (R_SYNC_SERIAL1_CTRL__status_driver__##f22##__VAL(R_SYNC_SERIAL1_CTRL_, status_driver_, v22) << R_SYNC_SERIAL1_CTRL__status_driver__BITNR) | \ - (R_SYNC_SERIAL1_CTRL__def_out0__##f23##__VAL(R_SYNC_SERIAL1_CTRL_, def_out0_, v23) << R_SYNC_SERIAL1_CTRL__def_out0__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SYNC_SERIAL1_CTRL_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SYNC_SERIAL1_CTRL. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SYNC_SERIAL1_CTRL_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16,f17_,v17,f18_,v18,f19_,v19,f20_,v20,f21_,v21,f22_,v22,f23_,v23) ( \ - (R_SYNC_SERIAL1_CTRL__tr_baud__##f1_##_VAL(R_SYNC_SERIAL1_CTRL_, tr_baud_, v1) << R_SYNC_SERIAL1_CTRL__tr_baud__BITNR) | \ - (R_SYNC_SERIAL1_CTRL__dma_enable__##f2_##_VAL(R_SYNC_SERIAL1_CTRL_, dma_enable_, v2) << R_SYNC_SERIAL1_CTRL__dma_enable__BITNR) | \ - (R_SYNC_SERIAL1_CTRL__mode__##f3_##_VAL(R_SYNC_SERIAL1_CTRL_, mode_, v3) << R_SYNC_SERIAL1_CTRL__mode__BITNR) | \ - (R_SYNC_SERIAL1_CTRL__error__##f4_##_VAL(R_SYNC_SERIAL1_CTRL_, error_, v4) << R_SYNC_SERIAL1_CTRL__error__BITNR) | \ - (R_SYNC_SERIAL1_CTRL__rec_enable__##f5_##_VAL(R_SYNC_SERIAL1_CTRL_, rec_enable_, v5) << R_SYNC_SERIAL1_CTRL__rec_enable__BITNR) | \ - (R_SYNC_SERIAL1_CTRL__f_synctype__##f6_##_VAL(R_SYNC_SERIAL1_CTRL_, f_synctype_, v6) << R_SYNC_SERIAL1_CTRL__f_synctype__BITNR) | \ - (R_SYNC_SERIAL1_CTRL__f_syncsize__##f7_##_VAL(R_SYNC_SERIAL1_CTRL_, f_syncsize_, v7) << R_SYNC_SERIAL1_CTRL__f_syncsize__BITNR) | \ - (R_SYNC_SERIAL1_CTRL__f_sync__##f8_##_VAL(R_SYNC_SERIAL1_CTRL_, f_sync_, v8) << R_SYNC_SERIAL1_CTRL__f_sync__BITNR) | \ - (R_SYNC_SERIAL1_CTRL__clk_mode__##f9_##_VAL(R_SYNC_SERIAL1_CTRL_, clk_mode_, v9) << R_SYNC_SERIAL1_CTRL__clk_mode__BITNR) | \ - (R_SYNC_SERIAL1_CTRL__clk_halt__##f10_##_VAL(R_SYNC_SERIAL1_CTRL_, clk_halt_, v10) << R_SYNC_SERIAL1_CTRL__clk_halt__BITNR) | \ - (R_SYNC_SERIAL1_CTRL__bitorder__##f11_##_VAL(R_SYNC_SERIAL1_CTRL_, bitorder_, v11) << R_SYNC_SERIAL1_CTRL__bitorder__BITNR) | \ - (R_SYNC_SERIAL1_CTRL__tr_enable__##f12_##_VAL(R_SYNC_SERIAL1_CTRL_, tr_enable_, v12) << R_SYNC_SERIAL1_CTRL__tr_enable__BITNR) | \ - (R_SYNC_SERIAL1_CTRL__wordsize__##f13_##_VAL(R_SYNC_SERIAL1_CTRL_, wordsize_, v13) << R_SYNC_SERIAL1_CTRL__wordsize__BITNR) | \ - (R_SYNC_SERIAL1_CTRL__buf_empty__##f14_##_VAL(R_SYNC_SERIAL1_CTRL_, buf_empty_, v14) << R_SYNC_SERIAL1_CTRL__buf_empty__BITNR) | \ - (R_SYNC_SERIAL1_CTRL__buf_full__##f15_##_VAL(R_SYNC_SERIAL1_CTRL_, buf_full_, v15) << R_SYNC_SERIAL1_CTRL__buf_full__BITNR) | \ - (R_SYNC_SERIAL1_CTRL__flow_ctrl__##f16_##_VAL(R_SYNC_SERIAL1_CTRL_, flow_ctrl_, v16) << R_SYNC_SERIAL1_CTRL__flow_ctrl__BITNR) | \ - (R_SYNC_SERIAL1_CTRL__clk_polarity__##f17_##_VAL(R_SYNC_SERIAL1_CTRL_, clk_polarity_, v17) << R_SYNC_SERIAL1_CTRL__clk_polarity__BITNR) | \ - (R_SYNC_SERIAL1_CTRL__frame_polarity__##f18_##_VAL(R_SYNC_SERIAL1_CTRL_, frame_polarity_, v18) << R_SYNC_SERIAL1_CTRL__frame_polarity__BITNR) | \ - (R_SYNC_SERIAL1_CTRL__status_polarity__##f19_##_VAL(R_SYNC_SERIAL1_CTRL_, status_polarity_, v19) << R_SYNC_SERIAL1_CTRL__status_polarity__BITNR) | \ - (R_SYNC_SERIAL1_CTRL__clk_driver__##f20_##_VAL(R_SYNC_SERIAL1_CTRL_, clk_driver_, v20) << R_SYNC_SERIAL1_CTRL__clk_driver__BITNR) | \ - (R_SYNC_SERIAL1_CTRL__frame_driver__##f21_##_VAL(R_SYNC_SERIAL1_CTRL_, frame_driver_, v21) << R_SYNC_SERIAL1_CTRL__frame_driver__BITNR) | \ - (R_SYNC_SERIAL1_CTRL__status_driver__##f22_##_VAL(R_SYNC_SERIAL1_CTRL_, status_driver_, v22) << R_SYNC_SERIAL1_CTRL__status_driver__BITNR) | \ - (R_SYNC_SERIAL1_CTRL__def_out0__##f23_##_VAL(R_SYNC_SERIAL1_CTRL_, def_out0_, v23) << R_SYNC_SERIAL1_CTRL__def_out0__BITNR) \ -) - -#endif - -/* - * R_SYNC_SERIAL1_REC_BYTE - * - type: RO - * - addr: 0xb000006c - * - group: Syncrounous serial port registers - */ - -#if USE_GROUP__Syncrounous_serial_port_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SYNC_SERIAL1_REC_BYTE -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SYNC_SERIAL1_REC_BYTE(f1,v1) ( \ - (R_SYNC_SERIAL1_REC_BYTE__data_in__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SYNC_SERIAL1_REC_BYTE -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SYNC_SERIAL1_REC_BYTE. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SYNC_SERIAL1_REC_BYTE(f1,v1) ( \ - (R_SYNC_SERIAL1_REC_BYTE__data_in__##f1##__VAL(R_SYNC_SERIAL1_REC_BYTE_, data_in_, v1) << R_SYNC_SERIAL1_REC_BYTE__data_in__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SYNC_SERIAL1_REC_BYTE_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SYNC_SERIAL1_REC_BYTE. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SYNC_SERIAL1_REC_BYTE_(f1_,v1) ( \ - (R_SYNC_SERIAL1_REC_BYTE__data_in__##f1_##_VAL(R_SYNC_SERIAL1_REC_BYTE_, data_in_, v1) << R_SYNC_SERIAL1_REC_BYTE__data_in__BITNR) \ -) - -#endif - -/* - * R_SYNC_SERIAL1_REC_DATA - * - type: RO - * - addr: 0xb000006c - * - group: Syncrounous serial port registers - */ - -#if USE_GROUP__Syncrounous_serial_port_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SYNC_SERIAL1_REC_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SYNC_SERIAL1_REC_DATA(f1,v1) ( \ - (R_SYNC_SERIAL1_REC_DATA__data_in__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SYNC_SERIAL1_REC_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SYNC_SERIAL1_REC_DATA. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SYNC_SERIAL1_REC_DATA(f1,v1) ( \ - (R_SYNC_SERIAL1_REC_DATA__data_in__##f1##__VAL(R_SYNC_SERIAL1_REC_DATA_, data_in_, v1) << R_SYNC_SERIAL1_REC_DATA__data_in__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SYNC_SERIAL1_REC_DATA_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SYNC_SERIAL1_REC_DATA. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SYNC_SERIAL1_REC_DATA_(f1_,v1) ( \ - (R_SYNC_SERIAL1_REC_DATA__data_in__##f1_##_VAL(R_SYNC_SERIAL1_REC_DATA_, data_in_, v1) << R_SYNC_SERIAL1_REC_DATA__data_in__BITNR) \ -) - -#endif - -/* - * R_SYNC_SERIAL1_REC_WORD - * - type: RO - * - addr: 0xb000006c - * - group: Syncrounous serial port registers - */ - -#if USE_GROUP__Syncrounous_serial_port_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SYNC_SERIAL1_REC_WORD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SYNC_SERIAL1_REC_WORD(f1,v1) ( \ - (R_SYNC_SERIAL1_REC_WORD__data_in__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SYNC_SERIAL1_REC_WORD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SYNC_SERIAL1_REC_WORD. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SYNC_SERIAL1_REC_WORD(f1,v1) ( \ - (R_SYNC_SERIAL1_REC_WORD__data_in__##f1##__VAL(R_SYNC_SERIAL1_REC_WORD_, data_in_, v1) << R_SYNC_SERIAL1_REC_WORD__data_in__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SYNC_SERIAL1_REC_WORD_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SYNC_SERIAL1_REC_WORD. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SYNC_SERIAL1_REC_WORD_(f1_,v1) ( \ - (R_SYNC_SERIAL1_REC_WORD__data_in__##f1_##_VAL(R_SYNC_SERIAL1_REC_WORD_, data_in_, v1) << R_SYNC_SERIAL1_REC_WORD__data_in__BITNR) \ -) - -#endif - -/* - * R_SYNC_SERIAL1_STATUS - * - type: RO - * - addr: 0xb0000068 - * - group: Syncrounous serial port registers - */ - -#if USE_GROUP__Syncrounous_serial_port_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SYNC_SERIAL1_STATUS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SYNC_SERIAL1_STATUS(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \ - (R_SYNC_SERIAL1_STATUS__rec_status__##f1##__MASK & REG__##v1) | \ - (R_SYNC_SERIAL1_STATUS__tr_empty__##f2##__MASK & REG__##v2) | \ - (R_SYNC_SERIAL1_STATUS__tr_ready__##f3##__MASK & REG__##v3) | \ - (R_SYNC_SERIAL1_STATUS__pin_1__##f4##__MASK & REG__##v4) | \ - (R_SYNC_SERIAL1_STATUS__pin_0__##f5##__MASK & REG__##v5) | \ - (R_SYNC_SERIAL1_STATUS__underflow__##f6##__MASK & REG__##v6) | \ - (R_SYNC_SERIAL1_STATUS__overrun__##f7##__MASK & REG__##v7) | \ - (R_SYNC_SERIAL1_STATUS__data_avail__##f8##__MASK & REG__##v8) | \ - (R_SYNC_SERIAL1_STATUS__data__##f9##__MASK & REG__##v9) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SYNC_SERIAL1_STATUS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SYNC_SERIAL1_STATUS. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SYNC_SERIAL1_STATUS(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \ - (R_SYNC_SERIAL1_STATUS__rec_status__##f1##__VAL(R_SYNC_SERIAL1_STATUS_, rec_status_, v1) << R_SYNC_SERIAL1_STATUS__rec_status__BITNR) | \ - (R_SYNC_SERIAL1_STATUS__tr_empty__##f2##__VAL(R_SYNC_SERIAL1_STATUS_, tr_empty_, v2) << R_SYNC_SERIAL1_STATUS__tr_empty__BITNR) | \ - (R_SYNC_SERIAL1_STATUS__tr_ready__##f3##__VAL(R_SYNC_SERIAL1_STATUS_, tr_ready_, v3) << R_SYNC_SERIAL1_STATUS__tr_ready__BITNR) | \ - (R_SYNC_SERIAL1_STATUS__pin_1__##f4##__VAL(R_SYNC_SERIAL1_STATUS_, pin_1_, v4) << R_SYNC_SERIAL1_STATUS__pin_1__BITNR) | \ - (R_SYNC_SERIAL1_STATUS__pin_0__##f5##__VAL(R_SYNC_SERIAL1_STATUS_, pin_0_, v5) << R_SYNC_SERIAL1_STATUS__pin_0__BITNR) | \ - (R_SYNC_SERIAL1_STATUS__underflow__##f6##__VAL(R_SYNC_SERIAL1_STATUS_, underflow_, v6) << R_SYNC_SERIAL1_STATUS__underflow__BITNR) | \ - (R_SYNC_SERIAL1_STATUS__overrun__##f7##__VAL(R_SYNC_SERIAL1_STATUS_, overrun_, v7) << R_SYNC_SERIAL1_STATUS__overrun__BITNR) | \ - (R_SYNC_SERIAL1_STATUS__data_avail__##f8##__VAL(R_SYNC_SERIAL1_STATUS_, data_avail_, v8) << R_SYNC_SERIAL1_STATUS__data_avail__BITNR) | \ - (R_SYNC_SERIAL1_STATUS__data__##f9##__VAL(R_SYNC_SERIAL1_STATUS_, data_, v9) << R_SYNC_SERIAL1_STATUS__data__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SYNC_SERIAL1_STATUS_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SYNC_SERIAL1_STATUS. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SYNC_SERIAL1_STATUS_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9) ( \ - (R_SYNC_SERIAL1_STATUS__rec_status__##f1_##_VAL(R_SYNC_SERIAL1_STATUS_, rec_status_, v1) << R_SYNC_SERIAL1_STATUS__rec_status__BITNR) | \ - (R_SYNC_SERIAL1_STATUS__tr_empty__##f2_##_VAL(R_SYNC_SERIAL1_STATUS_, tr_empty_, v2) << R_SYNC_SERIAL1_STATUS__tr_empty__BITNR) | \ - (R_SYNC_SERIAL1_STATUS__tr_ready__##f3_##_VAL(R_SYNC_SERIAL1_STATUS_, tr_ready_, v3) << R_SYNC_SERIAL1_STATUS__tr_ready__BITNR) | \ - (R_SYNC_SERIAL1_STATUS__pin_1__##f4_##_VAL(R_SYNC_SERIAL1_STATUS_, pin_1_, v4) << R_SYNC_SERIAL1_STATUS__pin_1__BITNR) | \ - (R_SYNC_SERIAL1_STATUS__pin_0__##f5_##_VAL(R_SYNC_SERIAL1_STATUS_, pin_0_, v5) << R_SYNC_SERIAL1_STATUS__pin_0__BITNR) | \ - (R_SYNC_SERIAL1_STATUS__underflow__##f6_##_VAL(R_SYNC_SERIAL1_STATUS_, underflow_, v6) << R_SYNC_SERIAL1_STATUS__underflow__BITNR) | \ - (R_SYNC_SERIAL1_STATUS__overrun__##f7_##_VAL(R_SYNC_SERIAL1_STATUS_, overrun_, v7) << R_SYNC_SERIAL1_STATUS__overrun__BITNR) | \ - (R_SYNC_SERIAL1_STATUS__data_avail__##f8_##_VAL(R_SYNC_SERIAL1_STATUS_, data_avail_, v8) << R_SYNC_SERIAL1_STATUS__data_avail__BITNR) | \ - (R_SYNC_SERIAL1_STATUS__data__##f9_##_VAL(R_SYNC_SERIAL1_STATUS_, data_, v9) << R_SYNC_SERIAL1_STATUS__data__BITNR) \ -) - -#endif - -/* - * R_SYNC_SERIAL1_TR_BYTE - * - type: WO - * - addr: 0xb000006c - * - group: Syncrounous serial port registers - */ - -#if USE_GROUP__Syncrounous_serial_port_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SYNC_SERIAL1_TR_BYTE -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SYNC_SERIAL1_TR_BYTE. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_SYNC_SERIAL1_TR_BYTE. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SYNC_SERIAL1_TR_BYTE(f1,v1) ( \ - *R_SYNC_SERIAL1_TR_BYTE__SADDR = ( \ - REG_INITIATED(R_SYNC_SERIAL1_TR_BYTE_) \ - REG_VAL__R_SYNC_SERIAL1_TR_BYTE_(f1##_,v1) \ - ), \ - R_SYNC_SERIAL1_TR_BYTE__WRITE(R_SYNC_SERIAL1_TR_BYTE__ADDR, *R_SYNC_SERIAL1_TR_BYTE__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SYNC_SERIAL1_TR_BYTE__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SYNC_SERIAL1_TR_BYTE. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_SYNC_SERIAL1_TR_BYTE. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SYNC_SERIAL1_TR_BYTE__SHADOW(f1,v1) ( \ - *R_SYNC_SERIAL1_TR_BYTE__SADDR = ( \ - REG_INITIATED(R_SYNC_SERIAL1_TR_BYTE_) \ - REG_VAL__R_SYNC_SERIAL1_TR_BYTE_(f1##_,v1) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SYNC_SERIAL1_TR_BYTE -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SYNC_SERIAL1_TR_BYTE(f1,v1) ( \ - (R_SYNC_SERIAL1_TR_BYTE__data_out__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SYNC_SERIAL1_TR_BYTE -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SYNC_SERIAL1_TR_BYTE. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SYNC_SERIAL1_TR_BYTE(f1,v1) ( \ - (R_SYNC_SERIAL1_TR_BYTE__data_out__##f1##__VAL(R_SYNC_SERIAL1_TR_BYTE_, data_out_, v1) << R_SYNC_SERIAL1_TR_BYTE__data_out__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SYNC_SERIAL1_TR_BYTE_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SYNC_SERIAL1_TR_BYTE. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SYNC_SERIAL1_TR_BYTE_(f1_,v1) ( \ - (R_SYNC_SERIAL1_TR_BYTE__data_out__##f1_##_VAL(R_SYNC_SERIAL1_TR_BYTE_, data_out_, v1) << R_SYNC_SERIAL1_TR_BYTE__data_out__BITNR) \ -) - -#endif - -/* - * R_SYNC_SERIAL1_TR_DATA - * - type: WO - * - addr: 0xb000006c - * - group: Syncrounous serial port registers - */ - -#if USE_GROUP__Syncrounous_serial_port_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SYNC_SERIAL1_TR_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SYNC_SERIAL1_TR_DATA. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_SYNC_SERIAL1_TR_DATA. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SYNC_SERIAL1_TR_DATA(f1,v1) ( \ - *R_SYNC_SERIAL1_TR_DATA__SADDR = ( \ - REG_INITIATED(R_SYNC_SERIAL1_TR_DATA_) \ - REG_VAL__R_SYNC_SERIAL1_TR_DATA_(f1##_,v1) \ - ), \ - R_SYNC_SERIAL1_TR_DATA__WRITE(R_SYNC_SERIAL1_TR_DATA__ADDR, *R_SYNC_SERIAL1_TR_DATA__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SYNC_SERIAL1_TR_DATA__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SYNC_SERIAL1_TR_DATA. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_SYNC_SERIAL1_TR_DATA. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SYNC_SERIAL1_TR_DATA__SHADOW(f1,v1) ( \ - *R_SYNC_SERIAL1_TR_DATA__SADDR = ( \ - REG_INITIATED(R_SYNC_SERIAL1_TR_DATA_) \ - REG_VAL__R_SYNC_SERIAL1_TR_DATA_(f1##_,v1) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SYNC_SERIAL1_TR_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SYNC_SERIAL1_TR_DATA(f1,v1) ( \ - (R_SYNC_SERIAL1_TR_DATA__data_out__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SYNC_SERIAL1_TR_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SYNC_SERIAL1_TR_DATA. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SYNC_SERIAL1_TR_DATA(f1,v1) ( \ - (R_SYNC_SERIAL1_TR_DATA__data_out__##f1##__VAL(R_SYNC_SERIAL1_TR_DATA_, data_out_, v1) << R_SYNC_SERIAL1_TR_DATA__data_out__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SYNC_SERIAL1_TR_DATA_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SYNC_SERIAL1_TR_DATA. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SYNC_SERIAL1_TR_DATA_(f1_,v1) ( \ - (R_SYNC_SERIAL1_TR_DATA__data_out__##f1_##_VAL(R_SYNC_SERIAL1_TR_DATA_, data_out_, v1) << R_SYNC_SERIAL1_TR_DATA__data_out__BITNR) \ -) - -#endif - -/* - * R_SYNC_SERIAL1_TR_WORD - * - type: WO - * - addr: 0xb000006c - * - group: Syncrounous serial port registers - */ - -#if USE_GROUP__Syncrounous_serial_port_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SYNC_SERIAL1_TR_WORD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SYNC_SERIAL1_TR_WORD. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_SYNC_SERIAL1_TR_WORD. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SYNC_SERIAL1_TR_WORD(f1,v1) ( \ - *R_SYNC_SERIAL1_TR_WORD__SADDR = ( \ - REG_INITIATED(R_SYNC_SERIAL1_TR_WORD_) \ - REG_VAL__R_SYNC_SERIAL1_TR_WORD_(f1##_,v1) \ - ), \ - R_SYNC_SERIAL1_TR_WORD__WRITE(R_SYNC_SERIAL1_TR_WORD__ADDR, *R_SYNC_SERIAL1_TR_WORD__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SYNC_SERIAL1_TR_WORD__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SYNC_SERIAL1_TR_WORD. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_SYNC_SERIAL1_TR_WORD. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SYNC_SERIAL1_TR_WORD__SHADOW(f1,v1) ( \ - *R_SYNC_SERIAL1_TR_WORD__SADDR = ( \ - REG_INITIATED(R_SYNC_SERIAL1_TR_WORD_) \ - REG_VAL__R_SYNC_SERIAL1_TR_WORD_(f1##_,v1) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SYNC_SERIAL1_TR_WORD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SYNC_SERIAL1_TR_WORD(f1,v1) ( \ - (R_SYNC_SERIAL1_TR_WORD__data_out__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SYNC_SERIAL1_TR_WORD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SYNC_SERIAL1_TR_WORD. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SYNC_SERIAL1_TR_WORD(f1,v1) ( \ - (R_SYNC_SERIAL1_TR_WORD__data_out__##f1##__VAL(R_SYNC_SERIAL1_TR_WORD_, data_out_, v1) << R_SYNC_SERIAL1_TR_WORD__data_out__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SYNC_SERIAL1_TR_WORD_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SYNC_SERIAL1_TR_WORD. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SYNC_SERIAL1_TR_WORD_(f1_,v1) ( \ - (R_SYNC_SERIAL1_TR_WORD__data_out__##f1_##_VAL(R_SYNC_SERIAL1_TR_WORD_, data_out_, v1) << R_SYNC_SERIAL1_TR_WORD__data_out__BITNR) \ -) - -#endif - -/* - * R_SYNC_SERIAL3_CTRL - * - type: WO - * - addr: 0xb0000078 - * - group: Syncrounous serial port registers - */ - -#if USE_GROUP__Syncrounous_serial_port_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SYNC_SERIAL3_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SYNC_SERIAL3_CTRL. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_SYNC_SERIAL3_CTRL. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SYNC_SERIAL3_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23) ( \ - *R_SYNC_SERIAL3_CTRL__SADDR = ( \ - REG_INITIATED(R_SYNC_SERIAL3_CTRL_) \ - REG_VAL__R_SYNC_SERIAL3_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20,f21##_,v21,f22##_,v22,f23##_,v23) \ - ), \ - R_SYNC_SERIAL3_CTRL__WRITE(R_SYNC_SERIAL3_CTRL__ADDR, *R_SYNC_SERIAL3_CTRL__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SYNC_SERIAL3_CTRL__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SYNC_SERIAL3_CTRL. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_SYNC_SERIAL3_CTRL. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SYNC_SERIAL3_CTRL__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23) ( \ - *R_SYNC_SERIAL3_CTRL__SADDR = ( \ - REG_INITIATED(R_SYNC_SERIAL3_CTRL_) \ - REG_VAL__R_SYNC_SERIAL3_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20,f21##_,v21,f22##_,v22,f23##_,v23) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SYNC_SERIAL3_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SYNC_SERIAL3_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23) ( \ - (R_SYNC_SERIAL3_CTRL__tr_baud__##f1##__MASK & REG__##v1) | \ - (R_SYNC_SERIAL3_CTRL__dma_enable__##f2##__MASK & REG__##v2) | \ - (R_SYNC_SERIAL3_CTRL__mode__##f3##__MASK & REG__##v3) | \ - (R_SYNC_SERIAL3_CTRL__error__##f4##__MASK & REG__##v4) | \ - (R_SYNC_SERIAL3_CTRL__rec_enable__##f5##__MASK & REG__##v5) | \ - (R_SYNC_SERIAL3_CTRL__f_synctype__##f6##__MASK & REG__##v6) | \ - (R_SYNC_SERIAL3_CTRL__f_syncsize__##f7##__MASK & REG__##v7) | \ - (R_SYNC_SERIAL3_CTRL__f_sync__##f8##__MASK & REG__##v8) | \ - (R_SYNC_SERIAL3_CTRL__clk_mode__##f9##__MASK & REG__##v9) | \ - (R_SYNC_SERIAL3_CTRL__clk_halt__##f10##__MASK & REG__##v10) | \ - (R_SYNC_SERIAL3_CTRL__bitorder__##f11##__MASK & REG__##v11) | \ - (R_SYNC_SERIAL3_CTRL__tr_enable__##f12##__MASK & REG__##v12) | \ - (R_SYNC_SERIAL3_CTRL__wordsize__##f13##__MASK & REG__##v13) | \ - (R_SYNC_SERIAL3_CTRL__buf_empty__##f14##__MASK & REG__##v14) | \ - (R_SYNC_SERIAL3_CTRL__buf_full__##f15##__MASK & REG__##v15) | \ - (R_SYNC_SERIAL3_CTRL__flow_ctrl__##f16##__MASK & REG__##v16) | \ - (R_SYNC_SERIAL3_CTRL__clk_polarity__##f17##__MASK & REG__##v17) | \ - (R_SYNC_SERIAL3_CTRL__frame_polarity__##f18##__MASK & REG__##v18) | \ - (R_SYNC_SERIAL3_CTRL__status_polarity__##f19##__MASK & REG__##v19) | \ - (R_SYNC_SERIAL3_CTRL__clk_driver__##f20##__MASK & REG__##v20) | \ - (R_SYNC_SERIAL3_CTRL__frame_driver__##f21##__MASK & REG__##v21) | \ - (R_SYNC_SERIAL3_CTRL__status_driver__##f22##__MASK & REG__##v22) | \ - (R_SYNC_SERIAL3_CTRL__def_out0__##f23##__MASK & REG__##v23) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SYNC_SERIAL3_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SYNC_SERIAL3_CTRL. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SYNC_SERIAL3_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23) ( \ - (R_SYNC_SERIAL3_CTRL__tr_baud__##f1##__VAL(R_SYNC_SERIAL3_CTRL_, tr_baud_, v1) << R_SYNC_SERIAL3_CTRL__tr_baud__BITNR) | \ - (R_SYNC_SERIAL3_CTRL__dma_enable__##f2##__VAL(R_SYNC_SERIAL3_CTRL_, dma_enable_, v2) << R_SYNC_SERIAL3_CTRL__dma_enable__BITNR) | \ - (R_SYNC_SERIAL3_CTRL__mode__##f3##__VAL(R_SYNC_SERIAL3_CTRL_, mode_, v3) << R_SYNC_SERIAL3_CTRL__mode__BITNR) | \ - (R_SYNC_SERIAL3_CTRL__error__##f4##__VAL(R_SYNC_SERIAL3_CTRL_, error_, v4) << R_SYNC_SERIAL3_CTRL__error__BITNR) | \ - (R_SYNC_SERIAL3_CTRL__rec_enable__##f5##__VAL(R_SYNC_SERIAL3_CTRL_, rec_enable_, v5) << R_SYNC_SERIAL3_CTRL__rec_enable__BITNR) | \ - (R_SYNC_SERIAL3_CTRL__f_synctype__##f6##__VAL(R_SYNC_SERIAL3_CTRL_, f_synctype_, v6) << R_SYNC_SERIAL3_CTRL__f_synctype__BITNR) | \ - (R_SYNC_SERIAL3_CTRL__f_syncsize__##f7##__VAL(R_SYNC_SERIAL3_CTRL_, f_syncsize_, v7) << R_SYNC_SERIAL3_CTRL__f_syncsize__BITNR) | \ - (R_SYNC_SERIAL3_CTRL__f_sync__##f8##__VAL(R_SYNC_SERIAL3_CTRL_, f_sync_, v8) << R_SYNC_SERIAL3_CTRL__f_sync__BITNR) | \ - (R_SYNC_SERIAL3_CTRL__clk_mode__##f9##__VAL(R_SYNC_SERIAL3_CTRL_, clk_mode_, v9) << R_SYNC_SERIAL3_CTRL__clk_mode__BITNR) | \ - (R_SYNC_SERIAL3_CTRL__clk_halt__##f10##__VAL(R_SYNC_SERIAL3_CTRL_, clk_halt_, v10) << R_SYNC_SERIAL3_CTRL__clk_halt__BITNR) | \ - (R_SYNC_SERIAL3_CTRL__bitorder__##f11##__VAL(R_SYNC_SERIAL3_CTRL_, bitorder_, v11) << R_SYNC_SERIAL3_CTRL__bitorder__BITNR) | \ - (R_SYNC_SERIAL3_CTRL__tr_enable__##f12##__VAL(R_SYNC_SERIAL3_CTRL_, tr_enable_, v12) << R_SYNC_SERIAL3_CTRL__tr_enable__BITNR) | \ - (R_SYNC_SERIAL3_CTRL__wordsize__##f13##__VAL(R_SYNC_SERIAL3_CTRL_, wordsize_, v13) << R_SYNC_SERIAL3_CTRL__wordsize__BITNR) | \ - (R_SYNC_SERIAL3_CTRL__buf_empty__##f14##__VAL(R_SYNC_SERIAL3_CTRL_, buf_empty_, v14) << R_SYNC_SERIAL3_CTRL__buf_empty__BITNR) | \ - (R_SYNC_SERIAL3_CTRL__buf_full__##f15##__VAL(R_SYNC_SERIAL3_CTRL_, buf_full_, v15) << R_SYNC_SERIAL3_CTRL__buf_full__BITNR) | \ - (R_SYNC_SERIAL3_CTRL__flow_ctrl__##f16##__VAL(R_SYNC_SERIAL3_CTRL_, flow_ctrl_, v16) << R_SYNC_SERIAL3_CTRL__flow_ctrl__BITNR) | \ - (R_SYNC_SERIAL3_CTRL__clk_polarity__##f17##__VAL(R_SYNC_SERIAL3_CTRL_, clk_polarity_, v17) << R_SYNC_SERIAL3_CTRL__clk_polarity__BITNR) | \ - (R_SYNC_SERIAL3_CTRL__frame_polarity__##f18##__VAL(R_SYNC_SERIAL3_CTRL_, frame_polarity_, v18) << R_SYNC_SERIAL3_CTRL__frame_polarity__BITNR) | \ - (R_SYNC_SERIAL3_CTRL__status_polarity__##f19##__VAL(R_SYNC_SERIAL3_CTRL_, status_polarity_, v19) << R_SYNC_SERIAL3_CTRL__status_polarity__BITNR) | \ - (R_SYNC_SERIAL3_CTRL__clk_driver__##f20##__VAL(R_SYNC_SERIAL3_CTRL_, clk_driver_, v20) << R_SYNC_SERIAL3_CTRL__clk_driver__BITNR) | \ - (R_SYNC_SERIAL3_CTRL__frame_driver__##f21##__VAL(R_SYNC_SERIAL3_CTRL_, frame_driver_, v21) << R_SYNC_SERIAL3_CTRL__frame_driver__BITNR) | \ - (R_SYNC_SERIAL3_CTRL__status_driver__##f22##__VAL(R_SYNC_SERIAL3_CTRL_, status_driver_, v22) << R_SYNC_SERIAL3_CTRL__status_driver__BITNR) | \ - (R_SYNC_SERIAL3_CTRL__def_out0__##f23##__VAL(R_SYNC_SERIAL3_CTRL_, def_out0_, v23) << R_SYNC_SERIAL3_CTRL__def_out0__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SYNC_SERIAL3_CTRL_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SYNC_SERIAL3_CTRL. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SYNC_SERIAL3_CTRL_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16,f17_,v17,f18_,v18,f19_,v19,f20_,v20,f21_,v21,f22_,v22,f23_,v23) ( \ - (R_SYNC_SERIAL3_CTRL__tr_baud__##f1_##_VAL(R_SYNC_SERIAL3_CTRL_, tr_baud_, v1) << R_SYNC_SERIAL3_CTRL__tr_baud__BITNR) | \ - (R_SYNC_SERIAL3_CTRL__dma_enable__##f2_##_VAL(R_SYNC_SERIAL3_CTRL_, dma_enable_, v2) << R_SYNC_SERIAL3_CTRL__dma_enable__BITNR) | \ - (R_SYNC_SERIAL3_CTRL__mode__##f3_##_VAL(R_SYNC_SERIAL3_CTRL_, mode_, v3) << R_SYNC_SERIAL3_CTRL__mode__BITNR) | \ - (R_SYNC_SERIAL3_CTRL__error__##f4_##_VAL(R_SYNC_SERIAL3_CTRL_, error_, v4) << R_SYNC_SERIAL3_CTRL__error__BITNR) | \ - (R_SYNC_SERIAL3_CTRL__rec_enable__##f5_##_VAL(R_SYNC_SERIAL3_CTRL_, rec_enable_, v5) << R_SYNC_SERIAL3_CTRL__rec_enable__BITNR) | \ - (R_SYNC_SERIAL3_CTRL__f_synctype__##f6_##_VAL(R_SYNC_SERIAL3_CTRL_, f_synctype_, v6) << R_SYNC_SERIAL3_CTRL__f_synctype__BITNR) | \ - (R_SYNC_SERIAL3_CTRL__f_syncsize__##f7_##_VAL(R_SYNC_SERIAL3_CTRL_, f_syncsize_, v7) << R_SYNC_SERIAL3_CTRL__f_syncsize__BITNR) | \ - (R_SYNC_SERIAL3_CTRL__f_sync__##f8_##_VAL(R_SYNC_SERIAL3_CTRL_, f_sync_, v8) << R_SYNC_SERIAL3_CTRL__f_sync__BITNR) | \ - (R_SYNC_SERIAL3_CTRL__clk_mode__##f9_##_VAL(R_SYNC_SERIAL3_CTRL_, clk_mode_, v9) << R_SYNC_SERIAL3_CTRL__clk_mode__BITNR) | \ - (R_SYNC_SERIAL3_CTRL__clk_halt__##f10_##_VAL(R_SYNC_SERIAL3_CTRL_, clk_halt_, v10) << R_SYNC_SERIAL3_CTRL__clk_halt__BITNR) | \ - (R_SYNC_SERIAL3_CTRL__bitorder__##f11_##_VAL(R_SYNC_SERIAL3_CTRL_, bitorder_, v11) << R_SYNC_SERIAL3_CTRL__bitorder__BITNR) | \ - (R_SYNC_SERIAL3_CTRL__tr_enable__##f12_##_VAL(R_SYNC_SERIAL3_CTRL_, tr_enable_, v12) << R_SYNC_SERIAL3_CTRL__tr_enable__BITNR) | \ - (R_SYNC_SERIAL3_CTRL__wordsize__##f13_##_VAL(R_SYNC_SERIAL3_CTRL_, wordsize_, v13) << R_SYNC_SERIAL3_CTRL__wordsize__BITNR) | \ - (R_SYNC_SERIAL3_CTRL__buf_empty__##f14_##_VAL(R_SYNC_SERIAL3_CTRL_, buf_empty_, v14) << R_SYNC_SERIAL3_CTRL__buf_empty__BITNR) | \ - (R_SYNC_SERIAL3_CTRL__buf_full__##f15_##_VAL(R_SYNC_SERIAL3_CTRL_, buf_full_, v15) << R_SYNC_SERIAL3_CTRL__buf_full__BITNR) | \ - (R_SYNC_SERIAL3_CTRL__flow_ctrl__##f16_##_VAL(R_SYNC_SERIAL3_CTRL_, flow_ctrl_, v16) << R_SYNC_SERIAL3_CTRL__flow_ctrl__BITNR) | \ - (R_SYNC_SERIAL3_CTRL__clk_polarity__##f17_##_VAL(R_SYNC_SERIAL3_CTRL_, clk_polarity_, v17) << R_SYNC_SERIAL3_CTRL__clk_polarity__BITNR) | \ - (R_SYNC_SERIAL3_CTRL__frame_polarity__##f18_##_VAL(R_SYNC_SERIAL3_CTRL_, frame_polarity_, v18) << R_SYNC_SERIAL3_CTRL__frame_polarity__BITNR) | \ - (R_SYNC_SERIAL3_CTRL__status_polarity__##f19_##_VAL(R_SYNC_SERIAL3_CTRL_, status_polarity_, v19) << R_SYNC_SERIAL3_CTRL__status_polarity__BITNR) | \ - (R_SYNC_SERIAL3_CTRL__clk_driver__##f20_##_VAL(R_SYNC_SERIAL3_CTRL_, clk_driver_, v20) << R_SYNC_SERIAL3_CTRL__clk_driver__BITNR) | \ - (R_SYNC_SERIAL3_CTRL__frame_driver__##f21_##_VAL(R_SYNC_SERIAL3_CTRL_, frame_driver_, v21) << R_SYNC_SERIAL3_CTRL__frame_driver__BITNR) | \ - (R_SYNC_SERIAL3_CTRL__status_driver__##f22_##_VAL(R_SYNC_SERIAL3_CTRL_, status_driver_, v22) << R_SYNC_SERIAL3_CTRL__status_driver__BITNR) | \ - (R_SYNC_SERIAL3_CTRL__def_out0__##f23_##_VAL(R_SYNC_SERIAL3_CTRL_, def_out0_, v23) << R_SYNC_SERIAL3_CTRL__def_out0__BITNR) \ -) - -#endif - -/* - * R_SYNC_SERIAL3_REC_BYTE - * - type: RO - * - addr: 0xb000007c - * - group: Syncrounous serial port registers - */ - -#if USE_GROUP__Syncrounous_serial_port_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SYNC_SERIAL3_REC_BYTE -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SYNC_SERIAL3_REC_BYTE(f1,v1) ( \ - (R_SYNC_SERIAL3_REC_BYTE__data_in__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SYNC_SERIAL3_REC_BYTE -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SYNC_SERIAL3_REC_BYTE. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SYNC_SERIAL3_REC_BYTE(f1,v1) ( \ - (R_SYNC_SERIAL3_REC_BYTE__data_in__##f1##__VAL(R_SYNC_SERIAL3_REC_BYTE_, data_in_, v1) << R_SYNC_SERIAL3_REC_BYTE__data_in__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SYNC_SERIAL3_REC_BYTE_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SYNC_SERIAL3_REC_BYTE. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SYNC_SERIAL3_REC_BYTE_(f1_,v1) ( \ - (R_SYNC_SERIAL3_REC_BYTE__data_in__##f1_##_VAL(R_SYNC_SERIAL3_REC_BYTE_, data_in_, v1) << R_SYNC_SERIAL3_REC_BYTE__data_in__BITNR) \ -) - -#endif - -/* - * R_SYNC_SERIAL3_REC_DATA - * - type: RO - * - addr: 0xb000007c - * - group: Syncrounous serial port registers - */ - -#if USE_GROUP__Syncrounous_serial_port_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SYNC_SERIAL3_REC_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SYNC_SERIAL3_REC_DATA(f1,v1) ( \ - (R_SYNC_SERIAL3_REC_DATA__data_in__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SYNC_SERIAL3_REC_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SYNC_SERIAL3_REC_DATA. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SYNC_SERIAL3_REC_DATA(f1,v1) ( \ - (R_SYNC_SERIAL3_REC_DATA__data_in__##f1##__VAL(R_SYNC_SERIAL3_REC_DATA_, data_in_, v1) << R_SYNC_SERIAL3_REC_DATA__data_in__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SYNC_SERIAL3_REC_DATA_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SYNC_SERIAL3_REC_DATA. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SYNC_SERIAL3_REC_DATA_(f1_,v1) ( \ - (R_SYNC_SERIAL3_REC_DATA__data_in__##f1_##_VAL(R_SYNC_SERIAL3_REC_DATA_, data_in_, v1) << R_SYNC_SERIAL3_REC_DATA__data_in__BITNR) \ -) - -#endif - -/* - * R_SYNC_SERIAL3_REC_WORD - * - type: RO - * - addr: 0xb000007c - * - group: Syncrounous serial port registers - */ - -#if USE_GROUP__Syncrounous_serial_port_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SYNC_SERIAL3_REC_WORD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SYNC_SERIAL3_REC_WORD(f1,v1) ( \ - (R_SYNC_SERIAL3_REC_WORD__data_in__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SYNC_SERIAL3_REC_WORD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SYNC_SERIAL3_REC_WORD. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SYNC_SERIAL3_REC_WORD(f1,v1) ( \ - (R_SYNC_SERIAL3_REC_WORD__data_in__##f1##__VAL(R_SYNC_SERIAL3_REC_WORD_, data_in_, v1) << R_SYNC_SERIAL3_REC_WORD__data_in__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SYNC_SERIAL3_REC_WORD_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SYNC_SERIAL3_REC_WORD. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SYNC_SERIAL3_REC_WORD_(f1_,v1) ( \ - (R_SYNC_SERIAL3_REC_WORD__data_in__##f1_##_VAL(R_SYNC_SERIAL3_REC_WORD_, data_in_, v1) << R_SYNC_SERIAL3_REC_WORD__data_in__BITNR) \ -) - -#endif - -/* - * R_SYNC_SERIAL3_STATUS - * - type: RO - * - addr: 0xb0000078 - * - group: Syncrounous serial port registers - */ - -#if USE_GROUP__Syncrounous_serial_port_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SYNC_SERIAL3_STATUS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SYNC_SERIAL3_STATUS(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \ - (R_SYNC_SERIAL3_STATUS__rec_status__##f1##__MASK & REG__##v1) | \ - (R_SYNC_SERIAL3_STATUS__tr_empty__##f2##__MASK & REG__##v2) | \ - (R_SYNC_SERIAL3_STATUS__tr_ready__##f3##__MASK & REG__##v3) | \ - (R_SYNC_SERIAL3_STATUS__pin_1__##f4##__MASK & REG__##v4) | \ - (R_SYNC_SERIAL3_STATUS__pin_0__##f5##__MASK & REG__##v5) | \ - (R_SYNC_SERIAL3_STATUS__underflow__##f6##__MASK & REG__##v6) | \ - (R_SYNC_SERIAL3_STATUS__overrun__##f7##__MASK & REG__##v7) | \ - (R_SYNC_SERIAL3_STATUS__data_avail__##f8##__MASK & REG__##v8) | \ - (R_SYNC_SERIAL3_STATUS__data__##f9##__MASK & REG__##v9) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SYNC_SERIAL3_STATUS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SYNC_SERIAL3_STATUS. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SYNC_SERIAL3_STATUS(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \ - (R_SYNC_SERIAL3_STATUS__rec_status__##f1##__VAL(R_SYNC_SERIAL3_STATUS_, rec_status_, v1) << R_SYNC_SERIAL3_STATUS__rec_status__BITNR) | \ - (R_SYNC_SERIAL3_STATUS__tr_empty__##f2##__VAL(R_SYNC_SERIAL3_STATUS_, tr_empty_, v2) << R_SYNC_SERIAL3_STATUS__tr_empty__BITNR) | \ - (R_SYNC_SERIAL3_STATUS__tr_ready__##f3##__VAL(R_SYNC_SERIAL3_STATUS_, tr_ready_, v3) << R_SYNC_SERIAL3_STATUS__tr_ready__BITNR) | \ - (R_SYNC_SERIAL3_STATUS__pin_1__##f4##__VAL(R_SYNC_SERIAL3_STATUS_, pin_1_, v4) << R_SYNC_SERIAL3_STATUS__pin_1__BITNR) | \ - (R_SYNC_SERIAL3_STATUS__pin_0__##f5##__VAL(R_SYNC_SERIAL3_STATUS_, pin_0_, v5) << R_SYNC_SERIAL3_STATUS__pin_0__BITNR) | \ - (R_SYNC_SERIAL3_STATUS__underflow__##f6##__VAL(R_SYNC_SERIAL3_STATUS_, underflow_, v6) << R_SYNC_SERIAL3_STATUS__underflow__BITNR) | \ - (R_SYNC_SERIAL3_STATUS__overrun__##f7##__VAL(R_SYNC_SERIAL3_STATUS_, overrun_, v7) << R_SYNC_SERIAL3_STATUS__overrun__BITNR) | \ - (R_SYNC_SERIAL3_STATUS__data_avail__##f8##__VAL(R_SYNC_SERIAL3_STATUS_, data_avail_, v8) << R_SYNC_SERIAL3_STATUS__data_avail__BITNR) | \ - (R_SYNC_SERIAL3_STATUS__data__##f9##__VAL(R_SYNC_SERIAL3_STATUS_, data_, v9) << R_SYNC_SERIAL3_STATUS__data__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SYNC_SERIAL3_STATUS_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SYNC_SERIAL3_STATUS. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SYNC_SERIAL3_STATUS_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9) ( \ - (R_SYNC_SERIAL3_STATUS__rec_status__##f1_##_VAL(R_SYNC_SERIAL3_STATUS_, rec_status_, v1) << R_SYNC_SERIAL3_STATUS__rec_status__BITNR) | \ - (R_SYNC_SERIAL3_STATUS__tr_empty__##f2_##_VAL(R_SYNC_SERIAL3_STATUS_, tr_empty_, v2) << R_SYNC_SERIAL3_STATUS__tr_empty__BITNR) | \ - (R_SYNC_SERIAL3_STATUS__tr_ready__##f3_##_VAL(R_SYNC_SERIAL3_STATUS_, tr_ready_, v3) << R_SYNC_SERIAL3_STATUS__tr_ready__BITNR) | \ - (R_SYNC_SERIAL3_STATUS__pin_1__##f4_##_VAL(R_SYNC_SERIAL3_STATUS_, pin_1_, v4) << R_SYNC_SERIAL3_STATUS__pin_1__BITNR) | \ - (R_SYNC_SERIAL3_STATUS__pin_0__##f5_##_VAL(R_SYNC_SERIAL3_STATUS_, pin_0_, v5) << R_SYNC_SERIAL3_STATUS__pin_0__BITNR) | \ - (R_SYNC_SERIAL3_STATUS__underflow__##f6_##_VAL(R_SYNC_SERIAL3_STATUS_, underflow_, v6) << R_SYNC_SERIAL3_STATUS__underflow__BITNR) | \ - (R_SYNC_SERIAL3_STATUS__overrun__##f7_##_VAL(R_SYNC_SERIAL3_STATUS_, overrun_, v7) << R_SYNC_SERIAL3_STATUS__overrun__BITNR) | \ - (R_SYNC_SERIAL3_STATUS__data_avail__##f8_##_VAL(R_SYNC_SERIAL3_STATUS_, data_avail_, v8) << R_SYNC_SERIAL3_STATUS__data_avail__BITNR) | \ - (R_SYNC_SERIAL3_STATUS__data__##f9_##_VAL(R_SYNC_SERIAL3_STATUS_, data_, v9) << R_SYNC_SERIAL3_STATUS__data__BITNR) \ -) - -#endif - -/* - * R_SYNC_SERIAL3_TR_BYTE - * - type: WO - * - addr: 0xb000007c - * - group: Syncrounous serial port registers - */ - -#if USE_GROUP__Syncrounous_serial_port_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SYNC_SERIAL3_TR_BYTE -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SYNC_SERIAL3_TR_BYTE. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_SYNC_SERIAL3_TR_BYTE. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SYNC_SERIAL3_TR_BYTE(f1,v1) ( \ - *R_SYNC_SERIAL3_TR_BYTE__SADDR = ( \ - REG_INITIATED(R_SYNC_SERIAL3_TR_BYTE_) \ - REG_VAL__R_SYNC_SERIAL3_TR_BYTE_(f1##_,v1) \ - ), \ - R_SYNC_SERIAL3_TR_BYTE__WRITE(R_SYNC_SERIAL3_TR_BYTE__ADDR, *R_SYNC_SERIAL3_TR_BYTE__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SYNC_SERIAL3_TR_BYTE__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SYNC_SERIAL3_TR_BYTE. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_SYNC_SERIAL3_TR_BYTE. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SYNC_SERIAL3_TR_BYTE__SHADOW(f1,v1) ( \ - *R_SYNC_SERIAL3_TR_BYTE__SADDR = ( \ - REG_INITIATED(R_SYNC_SERIAL3_TR_BYTE_) \ - REG_VAL__R_SYNC_SERIAL3_TR_BYTE_(f1##_,v1) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SYNC_SERIAL3_TR_BYTE -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SYNC_SERIAL3_TR_BYTE(f1,v1) ( \ - (R_SYNC_SERIAL3_TR_BYTE__data_out__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SYNC_SERIAL3_TR_BYTE -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SYNC_SERIAL3_TR_BYTE. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SYNC_SERIAL3_TR_BYTE(f1,v1) ( \ - (R_SYNC_SERIAL3_TR_BYTE__data_out__##f1##__VAL(R_SYNC_SERIAL3_TR_BYTE_, data_out_, v1) << R_SYNC_SERIAL3_TR_BYTE__data_out__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SYNC_SERIAL3_TR_BYTE_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SYNC_SERIAL3_TR_BYTE. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SYNC_SERIAL3_TR_BYTE_(f1_,v1) ( \ - (R_SYNC_SERIAL3_TR_BYTE__data_out__##f1_##_VAL(R_SYNC_SERIAL3_TR_BYTE_, data_out_, v1) << R_SYNC_SERIAL3_TR_BYTE__data_out__BITNR) \ -) - -#endif - -/* - * R_SYNC_SERIAL3_TR_DATA - * - type: WO - * - addr: 0xb000007c - * - group: Syncrounous serial port registers - */ - -#if USE_GROUP__Syncrounous_serial_port_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SYNC_SERIAL3_TR_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SYNC_SERIAL3_TR_DATA. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_SYNC_SERIAL3_TR_DATA. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SYNC_SERIAL3_TR_DATA(f1,v1) ( \ - *R_SYNC_SERIAL3_TR_DATA__SADDR = ( \ - REG_INITIATED(R_SYNC_SERIAL3_TR_DATA_) \ - REG_VAL__R_SYNC_SERIAL3_TR_DATA_(f1##_,v1) \ - ), \ - R_SYNC_SERIAL3_TR_DATA__WRITE(R_SYNC_SERIAL3_TR_DATA__ADDR, *R_SYNC_SERIAL3_TR_DATA__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SYNC_SERIAL3_TR_DATA__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SYNC_SERIAL3_TR_DATA. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_SYNC_SERIAL3_TR_DATA. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SYNC_SERIAL3_TR_DATA__SHADOW(f1,v1) ( \ - *R_SYNC_SERIAL3_TR_DATA__SADDR = ( \ - REG_INITIATED(R_SYNC_SERIAL3_TR_DATA_) \ - REG_VAL__R_SYNC_SERIAL3_TR_DATA_(f1##_,v1) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SYNC_SERIAL3_TR_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SYNC_SERIAL3_TR_DATA(f1,v1) ( \ - (R_SYNC_SERIAL3_TR_DATA__data_out__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SYNC_SERIAL3_TR_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SYNC_SERIAL3_TR_DATA. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SYNC_SERIAL3_TR_DATA(f1,v1) ( \ - (R_SYNC_SERIAL3_TR_DATA__data_out__##f1##__VAL(R_SYNC_SERIAL3_TR_DATA_, data_out_, v1) << R_SYNC_SERIAL3_TR_DATA__data_out__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SYNC_SERIAL3_TR_DATA_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SYNC_SERIAL3_TR_DATA. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SYNC_SERIAL3_TR_DATA_(f1_,v1) ( \ - (R_SYNC_SERIAL3_TR_DATA__data_out__##f1_##_VAL(R_SYNC_SERIAL3_TR_DATA_, data_out_, v1) << R_SYNC_SERIAL3_TR_DATA__data_out__BITNR) \ -) - -#endif - -/* - * R_SYNC_SERIAL3_TR_WORD - * - type: WO - * - addr: 0xb000007c - * - group: Syncrounous serial port registers - */ - -#if USE_GROUP__Syncrounous_serial_port_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SYNC_SERIAL3_TR_WORD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SYNC_SERIAL3_TR_WORD. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_SYNC_SERIAL3_TR_WORD. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SYNC_SERIAL3_TR_WORD(f1,v1) ( \ - *R_SYNC_SERIAL3_TR_WORD__SADDR = ( \ - REG_INITIATED(R_SYNC_SERIAL3_TR_WORD_) \ - REG_VAL__R_SYNC_SERIAL3_TR_WORD_(f1##_,v1) \ - ), \ - R_SYNC_SERIAL3_TR_WORD__WRITE(R_SYNC_SERIAL3_TR_WORD__ADDR, *R_SYNC_SERIAL3_TR_WORD__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SYNC_SERIAL3_TR_WORD__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SYNC_SERIAL3_TR_WORD. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_SYNC_SERIAL3_TR_WORD. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SYNC_SERIAL3_TR_WORD__SHADOW(f1,v1) ( \ - *R_SYNC_SERIAL3_TR_WORD__SADDR = ( \ - REG_INITIATED(R_SYNC_SERIAL3_TR_WORD_) \ - REG_VAL__R_SYNC_SERIAL3_TR_WORD_(f1##_,v1) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SYNC_SERIAL3_TR_WORD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SYNC_SERIAL3_TR_WORD(f1,v1) ( \ - (R_SYNC_SERIAL3_TR_WORD__data_out__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SYNC_SERIAL3_TR_WORD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SYNC_SERIAL3_TR_WORD. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SYNC_SERIAL3_TR_WORD(f1,v1) ( \ - (R_SYNC_SERIAL3_TR_WORD__data_out__##f1##__VAL(R_SYNC_SERIAL3_TR_WORD_, data_out_, v1) << R_SYNC_SERIAL3_TR_WORD__data_out__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SYNC_SERIAL3_TR_WORD_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SYNC_SERIAL3_TR_WORD. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SYNC_SERIAL3_TR_WORD_(f1_,v1) ( \ - (R_SYNC_SERIAL3_TR_WORD__data_out__##f1_##_VAL(R_SYNC_SERIAL3_TR_WORD_, data_out_, v1) << R_SYNC_SERIAL3_TR_WORD__data_out__BITNR) \ -) - -#endif - -/* - * R_SYNC_SERIAL_PRESCALE - * - type: WO - * - addr: 0xb00000f4 - * - group: Timer registers - */ - -#if USE_GROUP__Timer_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SYNC_SERIAL_PRESCALE -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SYNC_SERIAL_PRESCALE. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_SYNC_SERIAL_PRESCALE. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SYNC_SERIAL_PRESCALE(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - *R_SYNC_SERIAL_PRESCALE__SADDR = ( \ - REG_INITIATED(R_SYNC_SERIAL_PRESCALE_) \ - REG_VAL__R_SYNC_SERIAL_PRESCALE_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \ - ), \ - R_SYNC_SERIAL_PRESCALE__WRITE(R_SYNC_SERIAL_PRESCALE__ADDR, *R_SYNC_SERIAL_PRESCALE__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_SYNC_SERIAL_PRESCALE__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_SYNC_SERIAL_PRESCALE. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_SYNC_SERIAL_PRESCALE. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_SYNC_SERIAL_PRESCALE__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - *R_SYNC_SERIAL_PRESCALE__SADDR = ( \ - REG_INITIATED(R_SYNC_SERIAL_PRESCALE_) \ - REG_VAL__R_SYNC_SERIAL_PRESCALE_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_SYNC_SERIAL_PRESCALE -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_SYNC_SERIAL_PRESCALE(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - (R_SYNC_SERIAL_PRESCALE__clk_sel_u3__##f1##__MASK & REG__##v1) | \ - (R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__##f2##__MASK & REG__##v2) | \ - (R_SYNC_SERIAL_PRESCALE__clk_sel_u1__##f3##__MASK & REG__##v3) | \ - (R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__##f4##__MASK & REG__##v4) | \ - (R_SYNC_SERIAL_PRESCALE__prescaler__##f5##__MASK & REG__##v5) | \ - (R_SYNC_SERIAL_PRESCALE__warp_mode__##f6##__MASK & REG__##v6) | \ - (R_SYNC_SERIAL_PRESCALE__frame_rate__##f7##__MASK & REG__##v7) | \ - (R_SYNC_SERIAL_PRESCALE__word_rate__##f8##__MASK & REG__##v8) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SYNC_SERIAL_PRESCALE -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SYNC_SERIAL_PRESCALE. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_SYNC_SERIAL_PRESCALE(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \ - (R_SYNC_SERIAL_PRESCALE__clk_sel_u3__##f1##__VAL(R_SYNC_SERIAL_PRESCALE_, clk_sel_u3_, v1) << R_SYNC_SERIAL_PRESCALE__clk_sel_u3__BITNR) | \ - (R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__##f2##__VAL(R_SYNC_SERIAL_PRESCALE_, word_stb_sel_u3_, v2) << R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__BITNR) | \ - (R_SYNC_SERIAL_PRESCALE__clk_sel_u1__##f3##__VAL(R_SYNC_SERIAL_PRESCALE_, clk_sel_u1_, v3) << R_SYNC_SERIAL_PRESCALE__clk_sel_u1__BITNR) | \ - (R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__##f4##__VAL(R_SYNC_SERIAL_PRESCALE_, word_stb_sel_u1_, v4) << R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__BITNR) | \ - (R_SYNC_SERIAL_PRESCALE__prescaler__##f5##__VAL(R_SYNC_SERIAL_PRESCALE_, prescaler_, v5) << R_SYNC_SERIAL_PRESCALE__prescaler__BITNR) | \ - (R_SYNC_SERIAL_PRESCALE__warp_mode__##f6##__VAL(R_SYNC_SERIAL_PRESCALE_, warp_mode_, v6) << R_SYNC_SERIAL_PRESCALE__warp_mode__BITNR) | \ - (R_SYNC_SERIAL_PRESCALE__frame_rate__##f7##__VAL(R_SYNC_SERIAL_PRESCALE_, frame_rate_, v7) << R_SYNC_SERIAL_PRESCALE__frame_rate__BITNR) | \ - (R_SYNC_SERIAL_PRESCALE__word_rate__##f8##__VAL(R_SYNC_SERIAL_PRESCALE_, word_rate_, v8) << R_SYNC_SERIAL_PRESCALE__word_rate__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_SYNC_SERIAL_PRESCALE_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_SYNC_SERIAL_PRESCALE. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_SYNC_SERIAL_PRESCALE_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8) ( \ - (R_SYNC_SERIAL_PRESCALE__clk_sel_u3__##f1_##_VAL(R_SYNC_SERIAL_PRESCALE_, clk_sel_u3_, v1) << R_SYNC_SERIAL_PRESCALE__clk_sel_u3__BITNR) | \ - (R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__##f2_##_VAL(R_SYNC_SERIAL_PRESCALE_, word_stb_sel_u3_, v2) << R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__BITNR) | \ - (R_SYNC_SERIAL_PRESCALE__clk_sel_u1__##f3_##_VAL(R_SYNC_SERIAL_PRESCALE_, clk_sel_u1_, v3) << R_SYNC_SERIAL_PRESCALE__clk_sel_u1__BITNR) | \ - (R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__##f4_##_VAL(R_SYNC_SERIAL_PRESCALE_, word_stb_sel_u1_, v4) << R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__BITNR) | \ - (R_SYNC_SERIAL_PRESCALE__prescaler__##f5_##_VAL(R_SYNC_SERIAL_PRESCALE_, prescaler_, v5) << R_SYNC_SERIAL_PRESCALE__prescaler__BITNR) | \ - (R_SYNC_SERIAL_PRESCALE__warp_mode__##f6_##_VAL(R_SYNC_SERIAL_PRESCALE_, warp_mode_, v6) << R_SYNC_SERIAL_PRESCALE__warp_mode__BITNR) | \ - (R_SYNC_SERIAL_PRESCALE__frame_rate__##f7_##_VAL(R_SYNC_SERIAL_PRESCALE_, frame_rate_, v7) << R_SYNC_SERIAL_PRESCALE__frame_rate__BITNR) | \ - (R_SYNC_SERIAL_PRESCALE__word_rate__##f8_##_VAL(R_SYNC_SERIAL_PRESCALE_, word_rate_, v8) << R_SYNC_SERIAL_PRESCALE__word_rate__BITNR) \ -) - -#endif - -/* - * R_TEST_MODE - * - type: WO - * - addr: 0xb00000fc - * - group: Test mode registers - */ - -#if USE_GROUP__Test_mode_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_TEST_MODE -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_TEST_MODE. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_TEST_MODE. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_TEST_MODE(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16) ( \ - *R_TEST_MODE__SADDR = ( \ - REG_INITIATED(R_TEST_MODE_) \ - REG_VAL__R_TEST_MODE_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16) \ - ), \ - R_TEST_MODE__WRITE(R_TEST_MODE__ADDR, *R_TEST_MODE__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_TEST_MODE__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_TEST_MODE. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_TEST_MODE. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_TEST_MODE__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16) ( \ - *R_TEST_MODE__SADDR = ( \ - REG_INITIATED(R_TEST_MODE_) \ - REG_VAL__R_TEST_MODE_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_TEST_MODE -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_TEST_MODE(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16) ( \ - (R_TEST_MODE__single_step__##f1##__MASK & REG__##v1) | \ - (R_TEST_MODE__step_wr__##f2##__MASK & REG__##v2) | \ - (R_TEST_MODE__step_rd__##f3##__MASK & REG__##v3) | \ - (R_TEST_MODE__step_fetch__##f4##__MASK & REG__##v4) | \ - (R_TEST_MODE__mmu_test__##f5##__MASK & REG__##v5) | \ - (R_TEST_MODE__usb_test__##f6##__MASK & REG__##v6) | \ - (R_TEST_MODE__scsi_timer_test__##f7##__MASK & REG__##v7) | \ - (R_TEST_MODE__backoff__##f8##__MASK & REG__##v8) | \ - (R_TEST_MODE__snmp_test__##f9##__MASK & REG__##v9) | \ - (R_TEST_MODE__snmp_inc__##f10##__MASK & REG__##v10) | \ - (R_TEST_MODE__ser_loop__##f11##__MASK & REG__##v11) | \ - (R_TEST_MODE__baudrate__##f12##__MASK & REG__##v12) | \ - (R_TEST_MODE__timer__##f13##__MASK & REG__##v13) | \ - (R_TEST_MODE__cache_test__##f14##__MASK & REG__##v14) | \ - (R_TEST_MODE__tag_test__##f15##__MASK & REG__##v15) | \ - (R_TEST_MODE__cache_enable__##f16##__MASK & REG__##v16) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_TEST_MODE -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_TEST_MODE. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_TEST_MODE(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16) ( \ - (R_TEST_MODE__single_step__##f1##__VAL(R_TEST_MODE_, single_step_, v1) << R_TEST_MODE__single_step__BITNR) | \ - (R_TEST_MODE__step_wr__##f2##__VAL(R_TEST_MODE_, step_wr_, v2) << R_TEST_MODE__step_wr__BITNR) | \ - (R_TEST_MODE__step_rd__##f3##__VAL(R_TEST_MODE_, step_rd_, v3) << R_TEST_MODE__step_rd__BITNR) | \ - (R_TEST_MODE__step_fetch__##f4##__VAL(R_TEST_MODE_, step_fetch_, v4) << R_TEST_MODE__step_fetch__BITNR) | \ - (R_TEST_MODE__mmu_test__##f5##__VAL(R_TEST_MODE_, mmu_test_, v5) << R_TEST_MODE__mmu_test__BITNR) | \ - (R_TEST_MODE__usb_test__##f6##__VAL(R_TEST_MODE_, usb_test_, v6) << R_TEST_MODE__usb_test__BITNR) | \ - (R_TEST_MODE__scsi_timer_test__##f7##__VAL(R_TEST_MODE_, scsi_timer_test_, v7) << R_TEST_MODE__scsi_timer_test__BITNR) | \ - (R_TEST_MODE__backoff__##f8##__VAL(R_TEST_MODE_, backoff_, v8) << R_TEST_MODE__backoff__BITNR) | \ - (R_TEST_MODE__snmp_test__##f9##__VAL(R_TEST_MODE_, snmp_test_, v9) << R_TEST_MODE__snmp_test__BITNR) | \ - (R_TEST_MODE__snmp_inc__##f10##__VAL(R_TEST_MODE_, snmp_inc_, v10) << R_TEST_MODE__snmp_inc__BITNR) | \ - (R_TEST_MODE__ser_loop__##f11##__VAL(R_TEST_MODE_, ser_loop_, v11) << R_TEST_MODE__ser_loop__BITNR) | \ - (R_TEST_MODE__baudrate__##f12##__VAL(R_TEST_MODE_, baudrate_, v12) << R_TEST_MODE__baudrate__BITNR) | \ - (R_TEST_MODE__timer__##f13##__VAL(R_TEST_MODE_, timer_, v13) << R_TEST_MODE__timer__BITNR) | \ - (R_TEST_MODE__cache_test__##f14##__VAL(R_TEST_MODE_, cache_test_, v14) << R_TEST_MODE__cache_test__BITNR) | \ - (R_TEST_MODE__tag_test__##f15##__VAL(R_TEST_MODE_, tag_test_, v15) << R_TEST_MODE__tag_test__BITNR) | \ - (R_TEST_MODE__cache_enable__##f16##__VAL(R_TEST_MODE_, cache_enable_, v16) << R_TEST_MODE__cache_enable__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_TEST_MODE_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_TEST_MODE. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_TEST_MODE_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16) ( \ - (R_TEST_MODE__single_step__##f1_##_VAL(R_TEST_MODE_, single_step_, v1) << R_TEST_MODE__single_step__BITNR) | \ - (R_TEST_MODE__step_wr__##f2_##_VAL(R_TEST_MODE_, step_wr_, v2) << R_TEST_MODE__step_wr__BITNR) | \ - (R_TEST_MODE__step_rd__##f3_##_VAL(R_TEST_MODE_, step_rd_, v3) << R_TEST_MODE__step_rd__BITNR) | \ - (R_TEST_MODE__step_fetch__##f4_##_VAL(R_TEST_MODE_, step_fetch_, v4) << R_TEST_MODE__step_fetch__BITNR) | \ - (R_TEST_MODE__mmu_test__##f5_##_VAL(R_TEST_MODE_, mmu_test_, v5) << R_TEST_MODE__mmu_test__BITNR) | \ - (R_TEST_MODE__usb_test__##f6_##_VAL(R_TEST_MODE_, usb_test_, v6) << R_TEST_MODE__usb_test__BITNR) | \ - (R_TEST_MODE__scsi_timer_test__##f7_##_VAL(R_TEST_MODE_, scsi_timer_test_, v7) << R_TEST_MODE__scsi_timer_test__BITNR) | \ - (R_TEST_MODE__backoff__##f8_##_VAL(R_TEST_MODE_, backoff_, v8) << R_TEST_MODE__backoff__BITNR) | \ - (R_TEST_MODE__snmp_test__##f9_##_VAL(R_TEST_MODE_, snmp_test_, v9) << R_TEST_MODE__snmp_test__BITNR) | \ - (R_TEST_MODE__snmp_inc__##f10_##_VAL(R_TEST_MODE_, snmp_inc_, v10) << R_TEST_MODE__snmp_inc__BITNR) | \ - (R_TEST_MODE__ser_loop__##f11_##_VAL(R_TEST_MODE_, ser_loop_, v11) << R_TEST_MODE__ser_loop__BITNR) | \ - (R_TEST_MODE__baudrate__##f12_##_VAL(R_TEST_MODE_, baudrate_, v12) << R_TEST_MODE__baudrate__BITNR) | \ - (R_TEST_MODE__timer__##f13_##_VAL(R_TEST_MODE_, timer_, v13) << R_TEST_MODE__timer__BITNR) | \ - (R_TEST_MODE__cache_test__##f14_##_VAL(R_TEST_MODE_, cache_test_, v14) << R_TEST_MODE__cache_test__BITNR) | \ - (R_TEST_MODE__tag_test__##f15_##_VAL(R_TEST_MODE_, tag_test_, v15) << R_TEST_MODE__tag_test__BITNR) | \ - (R_TEST_MODE__cache_enable__##f16_##_VAL(R_TEST_MODE_, cache_enable_, v16) << R_TEST_MODE__cache_enable__BITNR) \ -) - -#endif - -/* - * R_TIMER01_DATA - * - type: RO - * - addr: 0xb0000022 - * - group: Timer registers - */ - -#if USE_GROUP__Timer_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_TIMER01_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_TIMER01_DATA(f1,v1) ( \ - (R_TIMER01_DATA__count__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_TIMER01_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_TIMER01_DATA. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_TIMER01_DATA(f1,v1) ( \ - (R_TIMER01_DATA__count__##f1##__VAL(R_TIMER01_DATA_, count_, v1) << R_TIMER01_DATA__count__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_TIMER01_DATA_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_TIMER01_DATA. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_TIMER01_DATA_(f1_,v1) ( \ - (R_TIMER01_DATA__count__##f1_##_VAL(R_TIMER01_DATA_, count_, v1) << R_TIMER01_DATA__count__BITNR) \ -) - -#endif - -/* - * R_TIMER0_DATA - * - type: RO - * - addr: 0xb0000022 - * - group: Timer registers - */ - -#if USE_GROUP__Timer_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_TIMER0_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_TIMER0_DATA(f1,v1) ( \ - (R_TIMER0_DATA__count__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_TIMER0_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_TIMER0_DATA. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_TIMER0_DATA(f1,v1) ( \ - (R_TIMER0_DATA__count__##f1##__VAL(R_TIMER0_DATA_, count_, v1) << R_TIMER0_DATA__count__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_TIMER0_DATA_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_TIMER0_DATA. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_TIMER0_DATA_(f1_,v1) ( \ - (R_TIMER0_DATA__count__##f1_##_VAL(R_TIMER0_DATA_, count_, v1) << R_TIMER0_DATA__count__BITNR) \ -) - -#endif - -/* - * R_TIMER1_DATA - * - type: RO - * - addr: 0xb0000023 - * - group: Timer registers - */ - -#if USE_GROUP__Timer_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_TIMER1_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_TIMER1_DATA(f1,v1) ( \ - (R_TIMER1_DATA__count__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_TIMER1_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_TIMER1_DATA. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_TIMER1_DATA(f1,v1) ( \ - (R_TIMER1_DATA__count__##f1##__VAL(R_TIMER1_DATA_, count_, v1) << R_TIMER1_DATA__count__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_TIMER1_DATA_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_TIMER1_DATA. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_TIMER1_DATA_(f1_,v1) ( \ - (R_TIMER1_DATA__count__##f1_##_VAL(R_TIMER1_DATA_, count_, v1) << R_TIMER1_DATA__count__BITNR) \ -) - -#endif - -/* - * R_TIMER_CTRL - * - type: WO - * - addr: 0xb0000020 - * - group: Timer registers - */ - -#if USE_GROUP__Timer_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_TIMER_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_TIMER_CTRL. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_TIMER_CTRL. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_TIMER_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \ - *R_TIMER_CTRL__SADDR = ( \ - REG_INITIATED(R_TIMER_CTRL_) \ - REG_VAL__R_TIMER_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10) \ - ), \ - R_TIMER_CTRL__WRITE(R_TIMER_CTRL__ADDR, *R_TIMER_CTRL__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_TIMER_CTRL__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_TIMER_CTRL. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_TIMER_CTRL. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_TIMER_CTRL__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \ - *R_TIMER_CTRL__SADDR = ( \ - REG_INITIATED(R_TIMER_CTRL_) \ - REG_VAL__R_TIMER_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_TIMER_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_TIMER_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \ - (R_TIMER_CTRL__timerdiv1__##f1##__MASK & REG__##v1) | \ - (R_TIMER_CTRL__timerdiv0__##f2##__MASK & REG__##v2) | \ - (R_TIMER_CTRL__presc_timer1__##f3##__MASK & REG__##v3) | \ - (R_TIMER_CTRL__i1__##f4##__MASK & REG__##v4) | \ - (R_TIMER_CTRL__tm1__##f5##__MASK & REG__##v5) | \ - (R_TIMER_CTRL__clksel1__##f6##__MASK & REG__##v6) | \ - (R_TIMER_CTRL__presc_ext__##f7##__MASK & REG__##v7) | \ - (R_TIMER_CTRL__i0__##f8##__MASK & REG__##v8) | \ - (R_TIMER_CTRL__tm0__##f9##__MASK & REG__##v9) | \ - (R_TIMER_CTRL__clksel0__##f10##__MASK & REG__##v10) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_TIMER_CTRL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_TIMER_CTRL. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_TIMER_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \ - (R_TIMER_CTRL__timerdiv1__##f1##__VAL(R_TIMER_CTRL_, timerdiv1_, v1) << R_TIMER_CTRL__timerdiv1__BITNR) | \ - (R_TIMER_CTRL__timerdiv0__##f2##__VAL(R_TIMER_CTRL_, timerdiv0_, v2) << R_TIMER_CTRL__timerdiv0__BITNR) | \ - (R_TIMER_CTRL__presc_timer1__##f3##__VAL(R_TIMER_CTRL_, presc_timer1_, v3) << R_TIMER_CTRL__presc_timer1__BITNR) | \ - (R_TIMER_CTRL__i1__##f4##__VAL(R_TIMER_CTRL_, i1_, v4) << R_TIMER_CTRL__i1__BITNR) | \ - (R_TIMER_CTRL__tm1__##f5##__VAL(R_TIMER_CTRL_, tm1_, v5) << R_TIMER_CTRL__tm1__BITNR) | \ - (R_TIMER_CTRL__clksel1__##f6##__VAL(R_TIMER_CTRL_, clksel1_, v6) << R_TIMER_CTRL__clksel1__BITNR) | \ - (R_TIMER_CTRL__presc_ext__##f7##__VAL(R_TIMER_CTRL_, presc_ext_, v7) << R_TIMER_CTRL__presc_ext__BITNR) | \ - (R_TIMER_CTRL__i0__##f8##__VAL(R_TIMER_CTRL_, i0_, v8) << R_TIMER_CTRL__i0__BITNR) | \ - (R_TIMER_CTRL__tm0__##f9##__VAL(R_TIMER_CTRL_, tm0_, v9) << R_TIMER_CTRL__tm0__BITNR) | \ - (R_TIMER_CTRL__clksel0__##f10##__VAL(R_TIMER_CTRL_, clksel0_, v10) << R_TIMER_CTRL__clksel0__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_TIMER_CTRL_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_TIMER_CTRL. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_TIMER_CTRL_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10) ( \ - (R_TIMER_CTRL__timerdiv1__##f1_##_VAL(R_TIMER_CTRL_, timerdiv1_, v1) << R_TIMER_CTRL__timerdiv1__BITNR) | \ - (R_TIMER_CTRL__timerdiv0__##f2_##_VAL(R_TIMER_CTRL_, timerdiv0_, v2) << R_TIMER_CTRL__timerdiv0__BITNR) | \ - (R_TIMER_CTRL__presc_timer1__##f3_##_VAL(R_TIMER_CTRL_, presc_timer1_, v3) << R_TIMER_CTRL__presc_timer1__BITNR) | \ - (R_TIMER_CTRL__i1__##f4_##_VAL(R_TIMER_CTRL_, i1_, v4) << R_TIMER_CTRL__i1__BITNR) | \ - (R_TIMER_CTRL__tm1__##f5_##_VAL(R_TIMER_CTRL_, tm1_, v5) << R_TIMER_CTRL__tm1__BITNR) | \ - (R_TIMER_CTRL__clksel1__##f6_##_VAL(R_TIMER_CTRL_, clksel1_, v6) << R_TIMER_CTRL__clksel1__BITNR) | \ - (R_TIMER_CTRL__presc_ext__##f7_##_VAL(R_TIMER_CTRL_, presc_ext_, v7) << R_TIMER_CTRL__presc_ext__BITNR) | \ - (R_TIMER_CTRL__i0__##f8_##_VAL(R_TIMER_CTRL_, i0_, v8) << R_TIMER_CTRL__i0__BITNR) | \ - (R_TIMER_CTRL__tm0__##f9_##_VAL(R_TIMER_CTRL_, tm0_, v9) << R_TIMER_CTRL__tm0__BITNR) | \ - (R_TIMER_CTRL__clksel0__##f10_##_VAL(R_TIMER_CTRL_, clksel0_, v10) << R_TIMER_CTRL__clksel0__BITNR) \ -) - -#endif - -/* - * R_TIMER_DATA - * - type: RO - * - addr: 0xb0000020 - * - group: Timer registers - */ - -#if USE_GROUP__Timer_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_TIMER_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_TIMER_DATA(f1,v1,f2,v2,f3,v3,f4,v4) ( \ - (R_TIMER_DATA__timer1__##f1##__MASK & REG__##v1) | \ - (R_TIMER_DATA__timer0__##f2##__MASK & REG__##v2) | \ - (R_TIMER_DATA__clkdiv_high__##f3##__MASK & REG__##v3) | \ - (R_TIMER_DATA__clkdiv_low__##f4##__MASK & REG__##v4) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_TIMER_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_TIMER_DATA. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_TIMER_DATA(f1,v1,f2,v2,f3,v3,f4,v4) ( \ - (R_TIMER_DATA__timer1__##f1##__VAL(R_TIMER_DATA_, timer1_, v1) << R_TIMER_DATA__timer1__BITNR) | \ - (R_TIMER_DATA__timer0__##f2##__VAL(R_TIMER_DATA_, timer0_, v2) << R_TIMER_DATA__timer0__BITNR) | \ - (R_TIMER_DATA__clkdiv_high__##f3##__VAL(R_TIMER_DATA_, clkdiv_high_, v3) << R_TIMER_DATA__clkdiv_high__BITNR) | \ - (R_TIMER_DATA__clkdiv_low__##f4##__VAL(R_TIMER_DATA_, clkdiv_low_, v4) << R_TIMER_DATA__clkdiv_low__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_TIMER_DATA_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_TIMER_DATA. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_TIMER_DATA_(f1_,v1,f2_,v2,f3_,v3,f4_,v4) ( \ - (R_TIMER_DATA__timer1__##f1_##_VAL(R_TIMER_DATA_, timer1_, v1) << R_TIMER_DATA__timer1__BITNR) | \ - (R_TIMER_DATA__timer0__##f2_##_VAL(R_TIMER_DATA_, timer0_, v2) << R_TIMER_DATA__timer0__BITNR) | \ - (R_TIMER_DATA__clkdiv_high__##f3_##_VAL(R_TIMER_DATA_, clkdiv_high_, v3) << R_TIMER_DATA__clkdiv_high__BITNR) | \ - (R_TIMER_DATA__clkdiv_low__##f4_##_VAL(R_TIMER_DATA_, clkdiv_low_, v4) << R_TIMER_DATA__clkdiv_low__BITNR) \ -) - -#endif - -/* - * R_TIMER_PRESCALE - * - type: WO - * - addr: 0xb00000f0 - * - group: Timer registers - */ - -#if USE_GROUP__Timer_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_TIMER_PRESCALE -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_TIMER_PRESCALE. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_TIMER_PRESCALE. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_TIMER_PRESCALE(f1,v1) ( \ - *R_TIMER_PRESCALE__SADDR = ( \ - REG_INITIATED(R_TIMER_PRESCALE_) \ - REG_VAL__R_TIMER_PRESCALE_(f1##_,v1) \ - ), \ - R_TIMER_PRESCALE__WRITE(R_TIMER_PRESCALE__ADDR, *R_TIMER_PRESCALE__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_TIMER_PRESCALE__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_TIMER_PRESCALE. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_TIMER_PRESCALE. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_TIMER_PRESCALE__SHADOW(f1,v1) ( \ - *R_TIMER_PRESCALE__SADDR = ( \ - REG_INITIATED(R_TIMER_PRESCALE_) \ - REG_VAL__R_TIMER_PRESCALE_(f1##_,v1) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_TIMER_PRESCALE -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_TIMER_PRESCALE(f1,v1) ( \ - (R_TIMER_PRESCALE__tim_presc__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_TIMER_PRESCALE -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_TIMER_PRESCALE. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_TIMER_PRESCALE(f1,v1) ( \ - (R_TIMER_PRESCALE__tim_presc__##f1##__VAL(R_TIMER_PRESCALE_, tim_presc_, v1) << R_TIMER_PRESCALE__tim_presc__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_TIMER_PRESCALE_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_TIMER_PRESCALE. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_TIMER_PRESCALE_(f1_,v1) ( \ - (R_TIMER_PRESCALE__tim_presc__##f1_##_VAL(R_TIMER_PRESCALE_, tim_presc_, v1) << R_TIMER_PRESCALE__tim_presc__BITNR) \ -) - -#endif - -/* - * R_TIM_PRESC_STATUS - * - type: RO - * - addr: 0xb00000f0 - * - group: Timer registers - */ - -#if USE_GROUP__Timer_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_TIM_PRESC_STATUS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_TIM_PRESC_STATUS(f1,v1) ( \ - (R_TIM_PRESC_STATUS__tim_status__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_TIM_PRESC_STATUS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_TIM_PRESC_STATUS. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_TIM_PRESC_STATUS(f1,v1) ( \ - (R_TIM_PRESC_STATUS__tim_status__##f1##__VAL(R_TIM_PRESC_STATUS_, tim_status_, v1) << R_TIM_PRESC_STATUS__tim_status__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_TIM_PRESC_STATUS_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_TIM_PRESC_STATUS. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_TIM_PRESC_STATUS_(f1_,v1) ( \ - (R_TIM_PRESC_STATUS__tim_status__##f1_##_VAL(R_TIM_PRESC_STATUS_, tim_status_, v1) << R_TIM_PRESC_STATUS__tim_status__BITNR) \ -) - -#endif - -/* - * R_TLB_HI - * - type: RW - * - addr: 0xb000025c - * - group: MMU registers - */ - -#if USE_GROUP__MMU_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_TLB_HI -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_TLB_HI. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_TLB_HI. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_TLB_HI(f1,v1,f2,v2) ( \ - R_TLB_HI__WRITE(R_TLB_HI__ADDR, ( \ - REG_VAL__R_TLB_HI_(f1##_,v1,f2##_,v2) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_TLB_HI -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_TLB_HI(f1,v1,f2,v2) ( \ - (R_TLB_HI__vpn__##f1##__MASK & REG__##v1) | \ - (R_TLB_HI__page_id__##f2##__MASK & REG__##v2) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_TLB_HI -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_TLB_HI. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_TLB_HI(f1,v1,f2,v2) ( \ - (R_TLB_HI__vpn__##f1##__VAL(R_TLB_HI_, vpn_, v1) << R_TLB_HI__vpn__BITNR) | \ - (R_TLB_HI__page_id__##f2##__VAL(R_TLB_HI_, page_id_, v2) << R_TLB_HI__page_id__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_TLB_HI_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_TLB_HI. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_TLB_HI_(f1_,v1,f2_,v2) ( \ - (R_TLB_HI__vpn__##f1_##_VAL(R_TLB_HI_, vpn_, v1) << R_TLB_HI__vpn__BITNR) | \ - (R_TLB_HI__page_id__##f2_##_VAL(R_TLB_HI_, page_id_, v2) << R_TLB_HI__page_id__BITNR) \ -) - -#endif - -/* - * R_TLB_LO - * - type: RW - * - addr: 0xb0000258 - * - group: MMU registers - */ - -#if USE_GROUP__MMU_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_TLB_LO -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_TLB_LO. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_TLB_LO. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_TLB_LO(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5) ( \ - R_TLB_LO__WRITE(R_TLB_LO__ADDR, ( \ - REG_VAL__R_TLB_LO_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_TLB_LO -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_TLB_LO(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5) ( \ - (R_TLB_LO__pfn__##f1##__MASK & REG__##v1) | \ - (R_TLB_LO__global__##f2##__MASK & REG__##v2) | \ - (R_TLB_LO__valid__##f3##__MASK & REG__##v3) | \ - (R_TLB_LO__kernel__##f4##__MASK & REG__##v4) | \ - (R_TLB_LO__we__##f5##__MASK & REG__##v5) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_TLB_LO -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_TLB_LO. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_TLB_LO(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5) ( \ - (R_TLB_LO__pfn__##f1##__VAL(R_TLB_LO_, pfn_, v1) << R_TLB_LO__pfn__BITNR) | \ - (R_TLB_LO__global__##f2##__VAL(R_TLB_LO_, global_, v2) << R_TLB_LO__global__BITNR) | \ - (R_TLB_LO__valid__##f3##__VAL(R_TLB_LO_, valid_, v3) << R_TLB_LO__valid__BITNR) | \ - (R_TLB_LO__kernel__##f4##__VAL(R_TLB_LO_, kernel_, v4) << R_TLB_LO__kernel__BITNR) | \ - (R_TLB_LO__we__##f5##__VAL(R_TLB_LO_, we_, v5) << R_TLB_LO__we__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_TLB_LO_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_TLB_LO. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_TLB_LO_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5) ( \ - (R_TLB_LO__pfn__##f1_##_VAL(R_TLB_LO_, pfn_, v1) << R_TLB_LO__pfn__BITNR) | \ - (R_TLB_LO__global__##f2_##_VAL(R_TLB_LO_, global_, v2) << R_TLB_LO__global__BITNR) | \ - (R_TLB_LO__valid__##f3_##_VAL(R_TLB_LO_, valid_, v3) << R_TLB_LO__valid__BITNR) | \ - (R_TLB_LO__kernel__##f4_##_VAL(R_TLB_LO_, kernel_, v4) << R_TLB_LO__kernel__BITNR) | \ - (R_TLB_LO__we__##f5_##_VAL(R_TLB_LO_, we_, v5) << R_TLB_LO__we__BITNR) \ -) - -#endif - -/* - * R_TLB_SELECT - * - type: RW - * - addr: 0xb0000254 - * - group: MMU registers - */ - -#if USE_GROUP__MMU_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_TLB_SELECT -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_TLB_SELECT. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_TLB_SELECT. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_TLB_SELECT(f1,v1) ( \ - R_TLB_SELECT__WRITE(R_TLB_SELECT__ADDR, ( \ - REG_VAL__R_TLB_SELECT_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_TLB_SELECT -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_TLB_SELECT(f1,v1) ( \ - (R_TLB_SELECT__index__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_TLB_SELECT -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_TLB_SELECT. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_TLB_SELECT(f1,v1) ( \ - (R_TLB_SELECT__index__##f1##__VAL(R_TLB_SELECT_, index_, v1) << R_TLB_SELECT__index__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_TLB_SELECT_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_TLB_SELECT. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_TLB_SELECT_(f1_,v1) ( \ - (R_TLB_SELECT__index__##f1_##_VAL(R_TLB_SELECT_, index_, v1) << R_TLB_SELECT__index__BITNR) \ -) - -#endif - -/* - * R_TR_COUNTERS - * - type: RO - * - addr: 0xb00000a8 - * - group: Network interface registers - */ - -#if USE_GROUP__Network_interface_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_TR_COUNTERS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_TR_COUNTERS(f1,v1,f2,v2,f3,v3,f4,v4) ( \ - (R_TR_COUNTERS__deferred__##f1##__MASK & REG__##v1) | \ - (R_TR_COUNTERS__late_col__##f2##__MASK & REG__##v2) | \ - (R_TR_COUNTERS__multiple_col__##f3##__MASK & REG__##v3) | \ - (R_TR_COUNTERS__single_col__##f4##__MASK & REG__##v4) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_TR_COUNTERS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_TR_COUNTERS. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_TR_COUNTERS(f1,v1,f2,v2,f3,v3,f4,v4) ( \ - (R_TR_COUNTERS__deferred__##f1##__VAL(R_TR_COUNTERS_, deferred_, v1) << R_TR_COUNTERS__deferred__BITNR) | \ - (R_TR_COUNTERS__late_col__##f2##__VAL(R_TR_COUNTERS_, late_col_, v2) << R_TR_COUNTERS__late_col__BITNR) | \ - (R_TR_COUNTERS__multiple_col__##f3##__VAL(R_TR_COUNTERS_, multiple_col_, v3) << R_TR_COUNTERS__multiple_col__BITNR) | \ - (R_TR_COUNTERS__single_col__##f4##__VAL(R_TR_COUNTERS_, single_col_, v4) << R_TR_COUNTERS__single_col__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_TR_COUNTERS_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_TR_COUNTERS. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_TR_COUNTERS_(f1_,v1,f2_,v2,f3_,v3,f4_,v4) ( \ - (R_TR_COUNTERS__deferred__##f1_##_VAL(R_TR_COUNTERS_, deferred_, v1) << R_TR_COUNTERS__deferred__BITNR) | \ - (R_TR_COUNTERS__late_col__##f2_##_VAL(R_TR_COUNTERS_, late_col_, v2) << R_TR_COUNTERS__late_col__BITNR) | \ - (R_TR_COUNTERS__multiple_col__##f3_##_VAL(R_TR_COUNTERS_, multiple_col_, v3) << R_TR_COUNTERS__multiple_col__BITNR) | \ - (R_TR_COUNTERS__single_col__##f4_##_VAL(R_TR_COUNTERS_, single_col_, v4) << R_TR_COUNTERS__single_col__BITNR) \ -) - -#endif - -/* - * R_USB_COMMAND - * - type: RW - * - addr: 0xb0000201 - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_USB_COMMAND -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_USB_COMMAND. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_USB_COMMAND. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_USB_COMMAND(f1,v1,f2,v2,f3,v3,f4,v4) ( \ - R_USB_COMMAND__WRITE(R_USB_COMMAND__ADDR, ( \ - REG_VAL__R_USB_COMMAND_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_USB_COMMAND -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_USB_COMMAND(f1,v1,f2,v2,f3,v3,f4,v4) ( \ - (R_USB_COMMAND__port_sel__##f1##__MASK & REG__##v1) | \ - (R_USB_COMMAND__port_cmd__##f2##__MASK & REG__##v2) | \ - (R_USB_COMMAND__busy__##f3##__MASK & REG__##v3) | \ - (R_USB_COMMAND__ctrl_cmd__##f4##__MASK & REG__##v4) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_COMMAND -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_COMMAND. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_USB_COMMAND(f1,v1,f2,v2,f3,v3,f4,v4) ( \ - (R_USB_COMMAND__port_sel__##f1##__VAL(R_USB_COMMAND_, port_sel_, v1) << R_USB_COMMAND__port_sel__BITNR) | \ - (R_USB_COMMAND__port_cmd__##f2##__VAL(R_USB_COMMAND_, port_cmd_, v2) << R_USB_COMMAND__port_cmd__BITNR) | \ - (R_USB_COMMAND__busy__##f3##__VAL(R_USB_COMMAND_, busy_, v3) << R_USB_COMMAND__busy__BITNR) | \ - (R_USB_COMMAND__ctrl_cmd__##f4##__VAL(R_USB_COMMAND_, ctrl_cmd_, v4) << R_USB_COMMAND__ctrl_cmd__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_COMMAND_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_COMMAND. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_USB_COMMAND_(f1_,v1,f2_,v2,f3_,v3,f4_,v4) ( \ - (R_USB_COMMAND__port_sel__##f1_##_VAL(R_USB_COMMAND_, port_sel_, v1) << R_USB_COMMAND__port_sel__BITNR) | \ - (R_USB_COMMAND__port_cmd__##f2_##_VAL(R_USB_COMMAND_, port_cmd_, v2) << R_USB_COMMAND__port_cmd__BITNR) | \ - (R_USB_COMMAND__busy__##f3_##_VAL(R_USB_COMMAND_, busy_, v3) << R_USB_COMMAND__busy__BITNR) | \ - (R_USB_COMMAND__ctrl_cmd__##f4_##_VAL(R_USB_COMMAND_, ctrl_cmd_, v4) << R_USB_COMMAND__ctrl_cmd__BITNR) \ -) - -#endif - -/* - * R_USB_COMMAND_DEV - * - type: RW - * - addr: 0xb0000201 - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_USB_COMMAND_DEV -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_USB_COMMAND_DEV. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_USB_COMMAND_DEV. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_USB_COMMAND_DEV(f1,v1,f2,v2,f3,v3,f4,v4) ( \ - R_USB_COMMAND_DEV__WRITE(R_USB_COMMAND_DEV__ADDR, ( \ - REG_VAL__R_USB_COMMAND_DEV_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_USB_COMMAND_DEV -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_USB_COMMAND_DEV(f1,v1,f2,v2,f3,v3,f4,v4) ( \ - (R_USB_COMMAND_DEV__port_sel__##f1##__MASK & REG__##v1) | \ - (R_USB_COMMAND_DEV__port_cmd__##f2##__MASK & REG__##v2) | \ - (R_USB_COMMAND_DEV__busy__##f3##__MASK & REG__##v3) | \ - (R_USB_COMMAND_DEV__ctrl_cmd__##f4##__MASK & REG__##v4) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_COMMAND_DEV -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_COMMAND_DEV. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_USB_COMMAND_DEV(f1,v1,f2,v2,f3,v3,f4,v4) ( \ - (R_USB_COMMAND_DEV__port_sel__##f1##__VAL(R_USB_COMMAND_DEV_, port_sel_, v1) << R_USB_COMMAND_DEV__port_sel__BITNR) | \ - (R_USB_COMMAND_DEV__port_cmd__##f2##__VAL(R_USB_COMMAND_DEV_, port_cmd_, v2) << R_USB_COMMAND_DEV__port_cmd__BITNR) | \ - (R_USB_COMMAND_DEV__busy__##f3##__VAL(R_USB_COMMAND_DEV_, busy_, v3) << R_USB_COMMAND_DEV__busy__BITNR) | \ - (R_USB_COMMAND_DEV__ctrl_cmd__##f4##__VAL(R_USB_COMMAND_DEV_, ctrl_cmd_, v4) << R_USB_COMMAND_DEV__ctrl_cmd__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_COMMAND_DEV_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_COMMAND_DEV. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_USB_COMMAND_DEV_(f1_,v1,f2_,v2,f3_,v3,f4_,v4) ( \ - (R_USB_COMMAND_DEV__port_sel__##f1_##_VAL(R_USB_COMMAND_DEV_, port_sel_, v1) << R_USB_COMMAND_DEV__port_sel__BITNR) | \ - (R_USB_COMMAND_DEV__port_cmd__##f2_##_VAL(R_USB_COMMAND_DEV_, port_cmd_, v2) << R_USB_COMMAND_DEV__port_cmd__BITNR) | \ - (R_USB_COMMAND_DEV__busy__##f3_##_VAL(R_USB_COMMAND_DEV_, busy_, v3) << R_USB_COMMAND_DEV__busy__BITNR) | \ - (R_USB_COMMAND_DEV__ctrl_cmd__##f4_##_VAL(R_USB_COMMAND_DEV_, ctrl_cmd_, v4) << R_USB_COMMAND_DEV__ctrl_cmd__BITNR) \ -) - -#endif - -/* - * R_USB_EPID_ATTN - * - type: RO - * - addr: 0xb0000224 - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_USB_EPID_ATTN -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_USB_EPID_ATTN(f1,v1) ( \ - (R_USB_EPID_ATTN__value__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_EPID_ATTN -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_EPID_ATTN. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_USB_EPID_ATTN(f1,v1) ( \ - (R_USB_EPID_ATTN__value__##f1##__VAL(R_USB_EPID_ATTN_, value_, v1) << R_USB_EPID_ATTN__value__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_EPID_ATTN_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_EPID_ATTN. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_USB_EPID_ATTN_(f1_,v1) ( \ - (R_USB_EPID_ATTN__value__##f1_##_VAL(R_USB_EPID_ATTN_, value_, v1) << R_USB_EPID_ATTN__value__BITNR) \ -) - -#endif - -/* - * R_USB_EPT_DATA - * - type: RW - * - addr: 0xb000021c - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_USB_EPT_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_USB_EPT_DATA. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_USB_EPT_DATA. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_USB_EPT_DATA(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12) ( \ - R_USB_EPT_DATA__WRITE(R_USB_EPT_DATA__ADDR, ( \ - REG_VAL__R_USB_EPT_DATA_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_USB_EPT_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_USB_EPT_DATA(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12) ( \ - (R_USB_EPT_DATA__valid__##f1##__MASK & REG__##v1) | \ - (R_USB_EPT_DATA__hold__##f2##__MASK & REG__##v2) | \ - (R_USB_EPT_DATA__error_count_in__##f3##__MASK & REG__##v3) | \ - (R_USB_EPT_DATA__t_in__##f4##__MASK & REG__##v4) | \ - (R_USB_EPT_DATA__low_speed__##f5##__MASK & REG__##v5) | \ - (R_USB_EPT_DATA__port__##f6##__MASK & REG__##v6) | \ - (R_USB_EPT_DATA__error_code__##f7##__MASK & REG__##v7) | \ - (R_USB_EPT_DATA__t_out__##f8##__MASK & REG__##v8) | \ - (R_USB_EPT_DATA__error_count_out__##f9##__MASK & REG__##v9) | \ - (R_USB_EPT_DATA__max_len__##f10##__MASK & REG__##v10) | \ - (R_USB_EPT_DATA__ep__##f11##__MASK & REG__##v11) | \ - (R_USB_EPT_DATA__dev__##f12##__MASK & REG__##v12) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_EPT_DATA -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_EPT_DATA. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_USB_EPT_DATA(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12) ( \ - (R_USB_EPT_DATA__valid__##f1##__VAL(R_USB_EPT_DATA_, valid_, v1) << R_USB_EPT_DATA__valid__BITNR) | \ - (R_USB_EPT_DATA__hold__##f2##__VAL(R_USB_EPT_DATA_, hold_, v2) << R_USB_EPT_DATA__hold__BITNR) | \ - (R_USB_EPT_DATA__error_count_in__##f3##__VAL(R_USB_EPT_DATA_, error_count_in_, v3) << R_USB_EPT_DATA__error_count_in__BITNR) | \ - (R_USB_EPT_DATA__t_in__##f4##__VAL(R_USB_EPT_DATA_, t_in_, v4) << R_USB_EPT_DATA__t_in__BITNR) | \ - (R_USB_EPT_DATA__low_speed__##f5##__VAL(R_USB_EPT_DATA_, low_speed_, v5) << R_USB_EPT_DATA__low_speed__BITNR) | \ - (R_USB_EPT_DATA__port__##f6##__VAL(R_USB_EPT_DATA_, port_, v6) << R_USB_EPT_DATA__port__BITNR) | \ - (R_USB_EPT_DATA__error_code__##f7##__VAL(R_USB_EPT_DATA_, error_code_, v7) << R_USB_EPT_DATA__error_code__BITNR) | \ - (R_USB_EPT_DATA__t_out__##f8##__VAL(R_USB_EPT_DATA_, t_out_, v8) << R_USB_EPT_DATA__t_out__BITNR) | \ - (R_USB_EPT_DATA__error_count_out__##f9##__VAL(R_USB_EPT_DATA_, error_count_out_, v9) << R_USB_EPT_DATA__error_count_out__BITNR) | \ - (R_USB_EPT_DATA__max_len__##f10##__VAL(R_USB_EPT_DATA_, max_len_, v10) << R_USB_EPT_DATA__max_len__BITNR) | \ - (R_USB_EPT_DATA__ep__##f11##__VAL(R_USB_EPT_DATA_, ep_, v11) << R_USB_EPT_DATA__ep__BITNR) | \ - (R_USB_EPT_DATA__dev__##f12##__VAL(R_USB_EPT_DATA_, dev_, v12) << R_USB_EPT_DATA__dev__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_EPT_DATA_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_EPT_DATA. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_USB_EPT_DATA_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12) ( \ - (R_USB_EPT_DATA__valid__##f1_##_VAL(R_USB_EPT_DATA_, valid_, v1) << R_USB_EPT_DATA__valid__BITNR) | \ - (R_USB_EPT_DATA__hold__##f2_##_VAL(R_USB_EPT_DATA_, hold_, v2) << R_USB_EPT_DATA__hold__BITNR) | \ - (R_USB_EPT_DATA__error_count_in__##f3_##_VAL(R_USB_EPT_DATA_, error_count_in_, v3) << R_USB_EPT_DATA__error_count_in__BITNR) | \ - (R_USB_EPT_DATA__t_in__##f4_##_VAL(R_USB_EPT_DATA_, t_in_, v4) << R_USB_EPT_DATA__t_in__BITNR) | \ - (R_USB_EPT_DATA__low_speed__##f5_##_VAL(R_USB_EPT_DATA_, low_speed_, v5) << R_USB_EPT_DATA__low_speed__BITNR) | \ - (R_USB_EPT_DATA__port__##f6_##_VAL(R_USB_EPT_DATA_, port_, v6) << R_USB_EPT_DATA__port__BITNR) | \ - (R_USB_EPT_DATA__error_code__##f7_##_VAL(R_USB_EPT_DATA_, error_code_, v7) << R_USB_EPT_DATA__error_code__BITNR) | \ - (R_USB_EPT_DATA__t_out__##f8_##_VAL(R_USB_EPT_DATA_, t_out_, v8) << R_USB_EPT_DATA__t_out__BITNR) | \ - (R_USB_EPT_DATA__error_count_out__##f9_##_VAL(R_USB_EPT_DATA_, error_count_out_, v9) << R_USB_EPT_DATA__error_count_out__BITNR) | \ - (R_USB_EPT_DATA__max_len__##f10_##_VAL(R_USB_EPT_DATA_, max_len_, v10) << R_USB_EPT_DATA__max_len__BITNR) | \ - (R_USB_EPT_DATA__ep__##f11_##_VAL(R_USB_EPT_DATA_, ep_, v11) << R_USB_EPT_DATA__ep__BITNR) | \ - (R_USB_EPT_DATA__dev__##f12_##_VAL(R_USB_EPT_DATA_, dev_, v12) << R_USB_EPT_DATA__dev__BITNR) \ -) - -#endif - -/* - * R_USB_EPT_DATA_DEV - * - type: RW - * - addr: 0xb000021c - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_USB_EPT_DATA_DEV -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_USB_EPT_DATA_DEV. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_USB_EPT_DATA_DEV. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_USB_EPT_DATA_DEV(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12) ( \ - R_USB_EPT_DATA_DEV__WRITE(R_USB_EPT_DATA_DEV__ADDR, ( \ - REG_VAL__R_USB_EPT_DATA_DEV_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_USB_EPT_DATA_DEV -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_USB_EPT_DATA_DEV(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12) ( \ - (R_USB_EPT_DATA_DEV__valid__##f1##__MASK & REG__##v1) | \ - (R_USB_EPT_DATA_DEV__hold__##f2##__MASK & REG__##v2) | \ - (R_USB_EPT_DATA_DEV__stall__##f3##__MASK & REG__##v3) | \ - (R_USB_EPT_DATA_DEV__iso_resp__##f4##__MASK & REG__##v4) | \ - (R_USB_EPT_DATA_DEV__ctrl__##f5##__MASK & REG__##v5) | \ - (R_USB_EPT_DATA_DEV__iso__##f6##__MASK & REG__##v6) | \ - (R_USB_EPT_DATA_DEV__port__##f7##__MASK & REG__##v7) | \ - (R_USB_EPT_DATA_DEV__control_phase__##f8##__MASK & REG__##v8) | \ - (R_USB_EPT_DATA_DEV__t__##f9##__MASK & REG__##v9) | \ - (R_USB_EPT_DATA_DEV__max_len__##f10##__MASK & REG__##v10) | \ - (R_USB_EPT_DATA_DEV__ep__##f11##__MASK & REG__##v11) | \ - (R_USB_EPT_DATA_DEV__dev__##f12##__MASK & REG__##v12) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_EPT_DATA_DEV -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_EPT_DATA_DEV. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_USB_EPT_DATA_DEV(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12) ( \ - (R_USB_EPT_DATA_DEV__valid__##f1##__VAL(R_USB_EPT_DATA_DEV_, valid_, v1) << R_USB_EPT_DATA_DEV__valid__BITNR) | \ - (R_USB_EPT_DATA_DEV__hold__##f2##__VAL(R_USB_EPT_DATA_DEV_, hold_, v2) << R_USB_EPT_DATA_DEV__hold__BITNR) | \ - (R_USB_EPT_DATA_DEV__stall__##f3##__VAL(R_USB_EPT_DATA_DEV_, stall_, v3) << R_USB_EPT_DATA_DEV__stall__BITNR) | \ - (R_USB_EPT_DATA_DEV__iso_resp__##f4##__VAL(R_USB_EPT_DATA_DEV_, iso_resp_, v4) << R_USB_EPT_DATA_DEV__iso_resp__BITNR) | \ - (R_USB_EPT_DATA_DEV__ctrl__##f5##__VAL(R_USB_EPT_DATA_DEV_, ctrl_, v5) << R_USB_EPT_DATA_DEV__ctrl__BITNR) | \ - (R_USB_EPT_DATA_DEV__iso__##f6##__VAL(R_USB_EPT_DATA_DEV_, iso_, v6) << R_USB_EPT_DATA_DEV__iso__BITNR) | \ - (R_USB_EPT_DATA_DEV__port__##f7##__VAL(R_USB_EPT_DATA_DEV_, port_, v7) << R_USB_EPT_DATA_DEV__port__BITNR) | \ - (R_USB_EPT_DATA_DEV__control_phase__##f8##__VAL(R_USB_EPT_DATA_DEV_, control_phase_, v8) << R_USB_EPT_DATA_DEV__control_phase__BITNR) | \ - (R_USB_EPT_DATA_DEV__t__##f9##__VAL(R_USB_EPT_DATA_DEV_, t_, v9) << R_USB_EPT_DATA_DEV__t__BITNR) | \ - (R_USB_EPT_DATA_DEV__max_len__##f10##__VAL(R_USB_EPT_DATA_DEV_, max_len_, v10) << R_USB_EPT_DATA_DEV__max_len__BITNR) | \ - (R_USB_EPT_DATA_DEV__ep__##f11##__VAL(R_USB_EPT_DATA_DEV_, ep_, v11) << R_USB_EPT_DATA_DEV__ep__BITNR) | \ - (R_USB_EPT_DATA_DEV__dev__##f12##__VAL(R_USB_EPT_DATA_DEV_, dev_, v12) << R_USB_EPT_DATA_DEV__dev__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_EPT_DATA_DEV_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_EPT_DATA_DEV. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_USB_EPT_DATA_DEV_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12) ( \ - (R_USB_EPT_DATA_DEV__valid__##f1_##_VAL(R_USB_EPT_DATA_DEV_, valid_, v1) << R_USB_EPT_DATA_DEV__valid__BITNR) | \ - (R_USB_EPT_DATA_DEV__hold__##f2_##_VAL(R_USB_EPT_DATA_DEV_, hold_, v2) << R_USB_EPT_DATA_DEV__hold__BITNR) | \ - (R_USB_EPT_DATA_DEV__stall__##f3_##_VAL(R_USB_EPT_DATA_DEV_, stall_, v3) << R_USB_EPT_DATA_DEV__stall__BITNR) | \ - (R_USB_EPT_DATA_DEV__iso_resp__##f4_##_VAL(R_USB_EPT_DATA_DEV_, iso_resp_, v4) << R_USB_EPT_DATA_DEV__iso_resp__BITNR) | \ - (R_USB_EPT_DATA_DEV__ctrl__##f5_##_VAL(R_USB_EPT_DATA_DEV_, ctrl_, v5) << R_USB_EPT_DATA_DEV__ctrl__BITNR) | \ - (R_USB_EPT_DATA_DEV__iso__##f6_##_VAL(R_USB_EPT_DATA_DEV_, iso_, v6) << R_USB_EPT_DATA_DEV__iso__BITNR) | \ - (R_USB_EPT_DATA_DEV__port__##f7_##_VAL(R_USB_EPT_DATA_DEV_, port_, v7) << R_USB_EPT_DATA_DEV__port__BITNR) | \ - (R_USB_EPT_DATA_DEV__control_phase__##f8_##_VAL(R_USB_EPT_DATA_DEV_, control_phase_, v8) << R_USB_EPT_DATA_DEV__control_phase__BITNR) | \ - (R_USB_EPT_DATA_DEV__t__##f9_##_VAL(R_USB_EPT_DATA_DEV_, t_, v9) << R_USB_EPT_DATA_DEV__t__BITNR) | \ - (R_USB_EPT_DATA_DEV__max_len__##f10_##_VAL(R_USB_EPT_DATA_DEV_, max_len_, v10) << R_USB_EPT_DATA_DEV__max_len__BITNR) | \ - (R_USB_EPT_DATA_DEV__ep__##f11_##_VAL(R_USB_EPT_DATA_DEV_, ep_, v11) << R_USB_EPT_DATA_DEV__ep__BITNR) | \ - (R_USB_EPT_DATA_DEV__dev__##f12_##_VAL(R_USB_EPT_DATA_DEV_, dev_, v12) << R_USB_EPT_DATA_DEV__dev__BITNR) \ -) - -#endif - -/* - * R_USB_EPT_DATA_ISO - * - type: RW - * - addr: 0xb000021c - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_USB_EPT_DATA_ISO -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_USB_EPT_DATA_ISO. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_USB_EPT_DATA_ISO. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_USB_EPT_DATA_ISO(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \ - R_USB_EPT_DATA_ISO__WRITE(R_USB_EPT_DATA_ISO__ADDR, ( \ - REG_VAL__R_USB_EPT_DATA_ISO_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_USB_EPT_DATA_ISO -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_USB_EPT_DATA_ISO(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \ - (R_USB_EPT_DATA_ISO__valid__##f1##__MASK & REG__##v1) | \ - (R_USB_EPT_DATA_ISO__port__##f2##__MASK & REG__##v2) | \ - (R_USB_EPT_DATA_ISO__error_code__##f3##__MASK & REG__##v3) | \ - (R_USB_EPT_DATA_ISO__max_len__##f4##__MASK & REG__##v4) | \ - (R_USB_EPT_DATA_ISO__ep__##f5##__MASK & REG__##v5) | \ - (R_USB_EPT_DATA_ISO__dev__##f6##__MASK & REG__##v6) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_EPT_DATA_ISO -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_EPT_DATA_ISO. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_USB_EPT_DATA_ISO(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \ - (R_USB_EPT_DATA_ISO__valid__##f1##__VAL(R_USB_EPT_DATA_ISO_, valid_, v1) << R_USB_EPT_DATA_ISO__valid__BITNR) | \ - (R_USB_EPT_DATA_ISO__port__##f2##__VAL(R_USB_EPT_DATA_ISO_, port_, v2) << R_USB_EPT_DATA_ISO__port__BITNR) | \ - (R_USB_EPT_DATA_ISO__error_code__##f3##__VAL(R_USB_EPT_DATA_ISO_, error_code_, v3) << R_USB_EPT_DATA_ISO__error_code__BITNR) | \ - (R_USB_EPT_DATA_ISO__max_len__##f4##__VAL(R_USB_EPT_DATA_ISO_, max_len_, v4) << R_USB_EPT_DATA_ISO__max_len__BITNR) | \ - (R_USB_EPT_DATA_ISO__ep__##f5##__VAL(R_USB_EPT_DATA_ISO_, ep_, v5) << R_USB_EPT_DATA_ISO__ep__BITNR) | \ - (R_USB_EPT_DATA_ISO__dev__##f6##__VAL(R_USB_EPT_DATA_ISO_, dev_, v6) << R_USB_EPT_DATA_ISO__dev__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_EPT_DATA_ISO_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_EPT_DATA_ISO. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_USB_EPT_DATA_ISO_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6) ( \ - (R_USB_EPT_DATA_ISO__valid__##f1_##_VAL(R_USB_EPT_DATA_ISO_, valid_, v1) << R_USB_EPT_DATA_ISO__valid__BITNR) | \ - (R_USB_EPT_DATA_ISO__port__##f2_##_VAL(R_USB_EPT_DATA_ISO_, port_, v2) << R_USB_EPT_DATA_ISO__port__BITNR) | \ - (R_USB_EPT_DATA_ISO__error_code__##f3_##_VAL(R_USB_EPT_DATA_ISO_, error_code_, v3) << R_USB_EPT_DATA_ISO__error_code__BITNR) | \ - (R_USB_EPT_DATA_ISO__max_len__##f4_##_VAL(R_USB_EPT_DATA_ISO_, max_len_, v4) << R_USB_EPT_DATA_ISO__max_len__BITNR) | \ - (R_USB_EPT_DATA_ISO__ep__##f5_##_VAL(R_USB_EPT_DATA_ISO_, ep_, v5) << R_USB_EPT_DATA_ISO__ep__BITNR) | \ - (R_USB_EPT_DATA_ISO__dev__##f6_##_VAL(R_USB_EPT_DATA_ISO_, dev_, v6) << R_USB_EPT_DATA_ISO__dev__BITNR) \ -) - -#endif - -/* - * R_USB_EPT_INDEX - * - type: RW - * - addr: 0xb0000208 - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_USB_EPT_INDEX -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_USB_EPT_INDEX. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_USB_EPT_INDEX. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_USB_EPT_INDEX(f1,v1) ( \ - R_USB_EPT_INDEX__WRITE(R_USB_EPT_INDEX__ADDR, ( \ - REG_VAL__R_USB_EPT_INDEX_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_USB_EPT_INDEX -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_USB_EPT_INDEX(f1,v1) ( \ - (R_USB_EPT_INDEX__value__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_EPT_INDEX -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_EPT_INDEX. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_USB_EPT_INDEX(f1,v1) ( \ - (R_USB_EPT_INDEX__value__##f1##__VAL(R_USB_EPT_INDEX_, value_, v1) << R_USB_EPT_INDEX__value__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_EPT_INDEX_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_EPT_INDEX. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_USB_EPT_INDEX_(f1_,v1) ( \ - (R_USB_EPT_INDEX__value__##f1_##_VAL(R_USB_EPT_INDEX_, value_, v1) << R_USB_EPT_INDEX__value__BITNR) \ -) - -#endif - -/* - * R_USB_FM_INTERVAL - * - type: RW - * - addr: 0xb0000210 - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_USB_FM_INTERVAL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_USB_FM_INTERVAL. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_USB_FM_INTERVAL. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_USB_FM_INTERVAL(f1,v1,f2,v2) ( \ - R_USB_FM_INTERVAL__WRITE(R_USB_FM_INTERVAL__ADDR, ( \ - REG_VAL__R_USB_FM_INTERVAL_(f1##_,v1,f2##_,v2) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_USB_FM_INTERVAL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_USB_FM_INTERVAL(f1,v1,f2,v2) ( \ - (R_USB_FM_INTERVAL__fixed__##f1##__MASK & REG__##v1) | \ - (R_USB_FM_INTERVAL__adj__##f2##__MASK & REG__##v2) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_FM_INTERVAL -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_FM_INTERVAL. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_USB_FM_INTERVAL(f1,v1,f2,v2) ( \ - (R_USB_FM_INTERVAL__fixed__##f1##__VAL(R_USB_FM_INTERVAL_, fixed_, v1) << R_USB_FM_INTERVAL__fixed__BITNR) | \ - (R_USB_FM_INTERVAL__adj__##f2##__VAL(R_USB_FM_INTERVAL_, adj_, v2) << R_USB_FM_INTERVAL__adj__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_FM_INTERVAL_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_FM_INTERVAL. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_USB_FM_INTERVAL_(f1_,v1,f2_,v2) ( \ - (R_USB_FM_INTERVAL__fixed__##f1_##_VAL(R_USB_FM_INTERVAL_, fixed_, v1) << R_USB_FM_INTERVAL__fixed__BITNR) | \ - (R_USB_FM_INTERVAL__adj__##f2_##_VAL(R_USB_FM_INTERVAL_, adj_, v2) << R_USB_FM_INTERVAL__adj__BITNR) \ -) - -#endif - -/* - * R_USB_FM_NUMBER - * - type: RW - * - addr: 0xb000020c - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_USB_FM_NUMBER -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_USB_FM_NUMBER. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_USB_FM_NUMBER. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_USB_FM_NUMBER(f1,v1) ( \ - R_USB_FM_NUMBER__WRITE(R_USB_FM_NUMBER__ADDR, ( \ - REG_VAL__R_USB_FM_NUMBER_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_USB_FM_NUMBER -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_USB_FM_NUMBER(f1,v1) ( \ - (R_USB_FM_NUMBER__value__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_FM_NUMBER -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_FM_NUMBER. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_USB_FM_NUMBER(f1,v1) ( \ - (R_USB_FM_NUMBER__value__##f1##__VAL(R_USB_FM_NUMBER_, value_, v1) << R_USB_FM_NUMBER__value__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_FM_NUMBER_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_FM_NUMBER. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_USB_FM_NUMBER_(f1_,v1) ( \ - (R_USB_FM_NUMBER__value__##f1_##_VAL(R_USB_FM_NUMBER_, value_, v1) << R_USB_FM_NUMBER__value__BITNR) \ -) - -#endif - -/* - * R_USB_FM_NUMBER_DEV - * - type: RW - * - addr: 0xb000020c - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_USB_FM_NUMBER_DEV -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_USB_FM_NUMBER_DEV. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_USB_FM_NUMBER_DEV. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_USB_FM_NUMBER_DEV(f1,v1,f2,v2,f3,v3) ( \ - R_USB_FM_NUMBER_DEV__WRITE(R_USB_FM_NUMBER_DEV__ADDR, ( \ - REG_VAL__R_USB_FM_NUMBER_DEV_(f1##_,v1,f2##_,v2,f3##_,v3) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_USB_FM_NUMBER_DEV -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_USB_FM_NUMBER_DEV(f1,v1,f2,v2,f3,v3) ( \ - (R_USB_FM_NUMBER_DEV__sign__##f1##__MASK & REG__##v1) | \ - (R_USB_FM_NUMBER_DEV__deviation__##f2##__MASK & REG__##v2) | \ - (R_USB_FM_NUMBER_DEV__fm_number__##f3##__MASK & REG__##v3) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_FM_NUMBER_DEV -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_FM_NUMBER_DEV. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_USB_FM_NUMBER_DEV(f1,v1,f2,v2,f3,v3) ( \ - (R_USB_FM_NUMBER_DEV__sign__##f1##__VAL(R_USB_FM_NUMBER_DEV_, sign_, v1) << R_USB_FM_NUMBER_DEV__sign__BITNR) | \ - (R_USB_FM_NUMBER_DEV__deviation__##f2##__VAL(R_USB_FM_NUMBER_DEV_, deviation_, v2) << R_USB_FM_NUMBER_DEV__deviation__BITNR) | \ - (R_USB_FM_NUMBER_DEV__fm_number__##f3##__VAL(R_USB_FM_NUMBER_DEV_, fm_number_, v3) << R_USB_FM_NUMBER_DEV__fm_number__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_FM_NUMBER_DEV_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_FM_NUMBER_DEV. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_USB_FM_NUMBER_DEV_(f1_,v1,f2_,v2,f3_,v3) ( \ - (R_USB_FM_NUMBER_DEV__sign__##f1_##_VAL(R_USB_FM_NUMBER_DEV_, sign_, v1) << R_USB_FM_NUMBER_DEV__sign__BITNR) | \ - (R_USB_FM_NUMBER_DEV__deviation__##f2_##_VAL(R_USB_FM_NUMBER_DEV_, deviation_, v2) << R_USB_FM_NUMBER_DEV__deviation__BITNR) | \ - (R_USB_FM_NUMBER_DEV__fm_number__##f3_##_VAL(R_USB_FM_NUMBER_DEV_, fm_number_, v3) << R_USB_FM_NUMBER_DEV__fm_number__BITNR) \ -) - -#endif - -/* - * R_USB_FM_PSTART - * - type: RW - * - addr: 0xb0000214 - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_USB_FM_PSTART -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_USB_FM_PSTART. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_USB_FM_PSTART. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_USB_FM_PSTART(f1,v1) ( \ - R_USB_FM_PSTART__WRITE(R_USB_FM_PSTART__ADDR, ( \ - REG_VAL__R_USB_FM_PSTART_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_USB_FM_PSTART -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_USB_FM_PSTART(f1,v1) ( \ - (R_USB_FM_PSTART__value__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_FM_PSTART -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_FM_PSTART. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_USB_FM_PSTART(f1,v1) ( \ - (R_USB_FM_PSTART__value__##f1##__VAL(R_USB_FM_PSTART_, value_, v1) << R_USB_FM_PSTART__value__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_FM_PSTART_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_FM_PSTART. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_USB_FM_PSTART_(f1_,v1) ( \ - (R_USB_FM_PSTART__value__##f1_##_VAL(R_USB_FM_PSTART_, value_, v1) << R_USB_FM_PSTART__value__BITNR) \ -) - -#endif - -/* - * R_USB_FM_REMAINING - * - type: RO - * - addr: 0xb0000212 - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_USB_FM_REMAINING -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_USB_FM_REMAINING(f1,v1) ( \ - (R_USB_FM_REMAINING__value__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_FM_REMAINING -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_FM_REMAINING. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_USB_FM_REMAINING(f1,v1) ( \ - (R_USB_FM_REMAINING__value__##f1##__VAL(R_USB_FM_REMAINING_, value_, v1) << R_USB_FM_REMAINING__value__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_FM_REMAINING_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_FM_REMAINING. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_USB_FM_REMAINING_(f1_,v1) ( \ - (R_USB_FM_REMAINING__value__##f1_##_VAL(R_USB_FM_REMAINING_, value_, v1) << R_USB_FM_REMAINING__value__BITNR) \ -) - -#endif - -/* - * R_USB_IRQ_MASK_CLR - * - type: WO - * - addr: 0xb0000206 - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_USB_IRQ_MASK_CLR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_USB_IRQ_MASK_CLR. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_USB_IRQ_MASK_CLR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_USB_IRQ_MASK_CLR(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \ - *R_USB_IRQ_MASK_CLR__SADDR = ( \ - REG_INITIATED(R_USB_IRQ_MASK_CLR_) \ - REG_VAL__R_USB_IRQ_MASK_CLR_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10) \ - ), \ - R_USB_IRQ_MASK_CLR__WRITE(R_USB_IRQ_MASK_CLR__ADDR, *R_USB_IRQ_MASK_CLR__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_USB_IRQ_MASK_CLR__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_USB_IRQ_MASK_CLR. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_USB_IRQ_MASK_CLR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_USB_IRQ_MASK_CLR__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \ - *R_USB_IRQ_MASK_CLR__SADDR = ( \ - REG_INITIATED(R_USB_IRQ_MASK_CLR_) \ - REG_VAL__R_USB_IRQ_MASK_CLR_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_USB_IRQ_MASK_CLR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_USB_IRQ_MASK_CLR(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \ - (R_USB_IRQ_MASK_CLR__iso_eof__##f1##__MASK & REG__##v1) | \ - (R_USB_IRQ_MASK_CLR__intr_eof__##f2##__MASK & REG__##v2) | \ - (R_USB_IRQ_MASK_CLR__iso_eot__##f3##__MASK & REG__##v3) | \ - (R_USB_IRQ_MASK_CLR__intr_eot__##f4##__MASK & REG__##v4) | \ - (R_USB_IRQ_MASK_CLR__ctl_eot__##f5##__MASK & REG__##v5) | \ - (R_USB_IRQ_MASK_CLR__bulk_eot__##f6##__MASK & REG__##v6) | \ - (R_USB_IRQ_MASK_CLR__epid_attn__##f7##__MASK & REG__##v7) | \ - (R_USB_IRQ_MASK_CLR__sof__##f8##__MASK & REG__##v8) | \ - (R_USB_IRQ_MASK_CLR__port_status__##f9##__MASK & REG__##v9) | \ - (R_USB_IRQ_MASK_CLR__ctl_status__##f10##__MASK & REG__##v10) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_IRQ_MASK_CLR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_IRQ_MASK_CLR. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_USB_IRQ_MASK_CLR(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \ - (R_USB_IRQ_MASK_CLR__iso_eof__##f1##__VAL(R_USB_IRQ_MASK_CLR_, iso_eof_, v1) << R_USB_IRQ_MASK_CLR__iso_eof__BITNR) | \ - (R_USB_IRQ_MASK_CLR__intr_eof__##f2##__VAL(R_USB_IRQ_MASK_CLR_, intr_eof_, v2) << R_USB_IRQ_MASK_CLR__intr_eof__BITNR) | \ - (R_USB_IRQ_MASK_CLR__iso_eot__##f3##__VAL(R_USB_IRQ_MASK_CLR_, iso_eot_, v3) << R_USB_IRQ_MASK_CLR__iso_eot__BITNR) | \ - (R_USB_IRQ_MASK_CLR__intr_eot__##f4##__VAL(R_USB_IRQ_MASK_CLR_, intr_eot_, v4) << R_USB_IRQ_MASK_CLR__intr_eot__BITNR) | \ - (R_USB_IRQ_MASK_CLR__ctl_eot__##f5##__VAL(R_USB_IRQ_MASK_CLR_, ctl_eot_, v5) << R_USB_IRQ_MASK_CLR__ctl_eot__BITNR) | \ - (R_USB_IRQ_MASK_CLR__bulk_eot__##f6##__VAL(R_USB_IRQ_MASK_CLR_, bulk_eot_, v6) << R_USB_IRQ_MASK_CLR__bulk_eot__BITNR) | \ - (R_USB_IRQ_MASK_CLR__epid_attn__##f7##__VAL(R_USB_IRQ_MASK_CLR_, epid_attn_, v7) << R_USB_IRQ_MASK_CLR__epid_attn__BITNR) | \ - (R_USB_IRQ_MASK_CLR__sof__##f8##__VAL(R_USB_IRQ_MASK_CLR_, sof_, v8) << R_USB_IRQ_MASK_CLR__sof__BITNR) | \ - (R_USB_IRQ_MASK_CLR__port_status__##f9##__VAL(R_USB_IRQ_MASK_CLR_, port_status_, v9) << R_USB_IRQ_MASK_CLR__port_status__BITNR) | \ - (R_USB_IRQ_MASK_CLR__ctl_status__##f10##__VAL(R_USB_IRQ_MASK_CLR_, ctl_status_, v10) << R_USB_IRQ_MASK_CLR__ctl_status__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_IRQ_MASK_CLR_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_IRQ_MASK_CLR. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_USB_IRQ_MASK_CLR_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10) ( \ - (R_USB_IRQ_MASK_CLR__iso_eof__##f1_##_VAL(R_USB_IRQ_MASK_CLR_, iso_eof_, v1) << R_USB_IRQ_MASK_CLR__iso_eof__BITNR) | \ - (R_USB_IRQ_MASK_CLR__intr_eof__##f2_##_VAL(R_USB_IRQ_MASK_CLR_, intr_eof_, v2) << R_USB_IRQ_MASK_CLR__intr_eof__BITNR) | \ - (R_USB_IRQ_MASK_CLR__iso_eot__##f3_##_VAL(R_USB_IRQ_MASK_CLR_, iso_eot_, v3) << R_USB_IRQ_MASK_CLR__iso_eot__BITNR) | \ - (R_USB_IRQ_MASK_CLR__intr_eot__##f4_##_VAL(R_USB_IRQ_MASK_CLR_, intr_eot_, v4) << R_USB_IRQ_MASK_CLR__intr_eot__BITNR) | \ - (R_USB_IRQ_MASK_CLR__ctl_eot__##f5_##_VAL(R_USB_IRQ_MASK_CLR_, ctl_eot_, v5) << R_USB_IRQ_MASK_CLR__ctl_eot__BITNR) | \ - (R_USB_IRQ_MASK_CLR__bulk_eot__##f6_##_VAL(R_USB_IRQ_MASK_CLR_, bulk_eot_, v6) << R_USB_IRQ_MASK_CLR__bulk_eot__BITNR) | \ - (R_USB_IRQ_MASK_CLR__epid_attn__##f7_##_VAL(R_USB_IRQ_MASK_CLR_, epid_attn_, v7) << R_USB_IRQ_MASK_CLR__epid_attn__BITNR) | \ - (R_USB_IRQ_MASK_CLR__sof__##f8_##_VAL(R_USB_IRQ_MASK_CLR_, sof_, v8) << R_USB_IRQ_MASK_CLR__sof__BITNR) | \ - (R_USB_IRQ_MASK_CLR__port_status__##f9_##_VAL(R_USB_IRQ_MASK_CLR_, port_status_, v9) << R_USB_IRQ_MASK_CLR__port_status__BITNR) | \ - (R_USB_IRQ_MASK_CLR__ctl_status__##f10_##_VAL(R_USB_IRQ_MASK_CLR_, ctl_status_, v10) << R_USB_IRQ_MASK_CLR__ctl_status__BITNR) \ -) - -#endif - -/* - * R_USB_IRQ_MASK_CLR_DEV - * - type: WO - * - addr: 0xb0000206 - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_USB_IRQ_MASK_CLR_DEV -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_USB_IRQ_MASK_CLR_DEV. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_USB_IRQ_MASK_CLR_DEV. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_USB_IRQ_MASK_CLR_DEV(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \ - *R_USB_IRQ_MASK_CLR_DEV__SADDR = ( \ - REG_INITIATED(R_USB_IRQ_MASK_CLR_DEV_) \ - REG_VAL__R_USB_IRQ_MASK_CLR_DEV_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9) \ - ), \ - R_USB_IRQ_MASK_CLR_DEV__WRITE(R_USB_IRQ_MASK_CLR_DEV__ADDR, *R_USB_IRQ_MASK_CLR_DEV__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_USB_IRQ_MASK_CLR_DEV__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_USB_IRQ_MASK_CLR_DEV. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_USB_IRQ_MASK_CLR_DEV. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_USB_IRQ_MASK_CLR_DEV__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \ - *R_USB_IRQ_MASK_CLR_DEV__SADDR = ( \ - REG_INITIATED(R_USB_IRQ_MASK_CLR_DEV_) \ - REG_VAL__R_USB_IRQ_MASK_CLR_DEV_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_USB_IRQ_MASK_CLR_DEV -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_USB_IRQ_MASK_CLR_DEV(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \ - (R_USB_IRQ_MASK_CLR_DEV__out_eot__##f1##__MASK & REG__##v1) | \ - (R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__##f2##__MASK & REG__##v2) | \ - (R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__##f3##__MASK & REG__##v3) | \ - (R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__##f4##__MASK & REG__##v4) | \ - (R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__##f5##__MASK & REG__##v5) | \ - (R_USB_IRQ_MASK_CLR_DEV__epid_attn__##f6##__MASK & REG__##v6) | \ - (R_USB_IRQ_MASK_CLR_DEV__sof__##f7##__MASK & REG__##v7) | \ - (R_USB_IRQ_MASK_CLR_DEV__port_status__##f8##__MASK & REG__##v8) | \ - (R_USB_IRQ_MASK_CLR_DEV__ctl_status__##f9##__MASK & REG__##v9) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_IRQ_MASK_CLR_DEV -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_IRQ_MASK_CLR_DEV. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_USB_IRQ_MASK_CLR_DEV(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \ - (R_USB_IRQ_MASK_CLR_DEV__out_eot__##f1##__VAL(R_USB_IRQ_MASK_CLR_DEV_, out_eot_, v1) << R_USB_IRQ_MASK_CLR_DEV__out_eot__BITNR) | \ - (R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__##f2##__VAL(R_USB_IRQ_MASK_CLR_DEV_, ep3_in_eot_, v2) << R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__BITNR) | \ - (R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__##f3##__VAL(R_USB_IRQ_MASK_CLR_DEV_, ep2_in_eot_, v3) << R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__BITNR) | \ - (R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__##f4##__VAL(R_USB_IRQ_MASK_CLR_DEV_, ep1_in_eot_, v4) << R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__BITNR) | \ - (R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__##f5##__VAL(R_USB_IRQ_MASK_CLR_DEV_, ep0_in_eot_, v5) << R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__BITNR) | \ - (R_USB_IRQ_MASK_CLR_DEV__epid_attn__##f6##__VAL(R_USB_IRQ_MASK_CLR_DEV_, epid_attn_, v6) << R_USB_IRQ_MASK_CLR_DEV__epid_attn__BITNR) | \ - (R_USB_IRQ_MASK_CLR_DEV__sof__##f7##__VAL(R_USB_IRQ_MASK_CLR_DEV_, sof_, v7) << R_USB_IRQ_MASK_CLR_DEV__sof__BITNR) | \ - (R_USB_IRQ_MASK_CLR_DEV__port_status__##f8##__VAL(R_USB_IRQ_MASK_CLR_DEV_, port_status_, v8) << R_USB_IRQ_MASK_CLR_DEV__port_status__BITNR) | \ - (R_USB_IRQ_MASK_CLR_DEV__ctl_status__##f9##__VAL(R_USB_IRQ_MASK_CLR_DEV_, ctl_status_, v9) << R_USB_IRQ_MASK_CLR_DEV__ctl_status__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_IRQ_MASK_CLR_DEV_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_IRQ_MASK_CLR_DEV. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_USB_IRQ_MASK_CLR_DEV_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9) ( \ - (R_USB_IRQ_MASK_CLR_DEV__out_eot__##f1_##_VAL(R_USB_IRQ_MASK_CLR_DEV_, out_eot_, v1) << R_USB_IRQ_MASK_CLR_DEV__out_eot__BITNR) | \ - (R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__##f2_##_VAL(R_USB_IRQ_MASK_CLR_DEV_, ep3_in_eot_, v2) << R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__BITNR) | \ - (R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__##f3_##_VAL(R_USB_IRQ_MASK_CLR_DEV_, ep2_in_eot_, v3) << R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__BITNR) | \ - (R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__##f4_##_VAL(R_USB_IRQ_MASK_CLR_DEV_, ep1_in_eot_, v4) << R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__BITNR) | \ - (R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__##f5_##_VAL(R_USB_IRQ_MASK_CLR_DEV_, ep0_in_eot_, v5) << R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__BITNR) | \ - (R_USB_IRQ_MASK_CLR_DEV__epid_attn__##f6_##_VAL(R_USB_IRQ_MASK_CLR_DEV_, epid_attn_, v6) << R_USB_IRQ_MASK_CLR_DEV__epid_attn__BITNR) | \ - (R_USB_IRQ_MASK_CLR_DEV__sof__##f7_##_VAL(R_USB_IRQ_MASK_CLR_DEV_, sof_, v7) << R_USB_IRQ_MASK_CLR_DEV__sof__BITNR) | \ - (R_USB_IRQ_MASK_CLR_DEV__port_status__##f8_##_VAL(R_USB_IRQ_MASK_CLR_DEV_, port_status_, v8) << R_USB_IRQ_MASK_CLR_DEV__port_status__BITNR) | \ - (R_USB_IRQ_MASK_CLR_DEV__ctl_status__##f9_##_VAL(R_USB_IRQ_MASK_CLR_DEV_, ctl_status_, v9) << R_USB_IRQ_MASK_CLR_DEV__ctl_status__BITNR) \ -) - -#endif - -/* - * R_USB_IRQ_MASK_READ - * - type: RO - * - addr: 0xb0000204 - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_USB_IRQ_MASK_READ -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_USB_IRQ_MASK_READ(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \ - (R_USB_IRQ_MASK_READ__iso_eof__##f1##__MASK & REG__##v1) | \ - (R_USB_IRQ_MASK_READ__intr_eof__##f2##__MASK & REG__##v2) | \ - (R_USB_IRQ_MASK_READ__iso_eot__##f3##__MASK & REG__##v3) | \ - (R_USB_IRQ_MASK_READ__intr_eot__##f4##__MASK & REG__##v4) | \ - (R_USB_IRQ_MASK_READ__ctl_eot__##f5##__MASK & REG__##v5) | \ - (R_USB_IRQ_MASK_READ__bulk_eot__##f6##__MASK & REG__##v6) | \ - (R_USB_IRQ_MASK_READ__epid_attn__##f7##__MASK & REG__##v7) | \ - (R_USB_IRQ_MASK_READ__sof__##f8##__MASK & REG__##v8) | \ - (R_USB_IRQ_MASK_READ__port_status__##f9##__MASK & REG__##v9) | \ - (R_USB_IRQ_MASK_READ__ctl_status__##f10##__MASK & REG__##v10) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_IRQ_MASK_READ -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_IRQ_MASK_READ. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_USB_IRQ_MASK_READ(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \ - (R_USB_IRQ_MASK_READ__iso_eof__##f1##__VAL(R_USB_IRQ_MASK_READ_, iso_eof_, v1) << R_USB_IRQ_MASK_READ__iso_eof__BITNR) | \ - (R_USB_IRQ_MASK_READ__intr_eof__##f2##__VAL(R_USB_IRQ_MASK_READ_, intr_eof_, v2) << R_USB_IRQ_MASK_READ__intr_eof__BITNR) | \ - (R_USB_IRQ_MASK_READ__iso_eot__##f3##__VAL(R_USB_IRQ_MASK_READ_, iso_eot_, v3) << R_USB_IRQ_MASK_READ__iso_eot__BITNR) | \ - (R_USB_IRQ_MASK_READ__intr_eot__##f4##__VAL(R_USB_IRQ_MASK_READ_, intr_eot_, v4) << R_USB_IRQ_MASK_READ__intr_eot__BITNR) | \ - (R_USB_IRQ_MASK_READ__ctl_eot__##f5##__VAL(R_USB_IRQ_MASK_READ_, ctl_eot_, v5) << R_USB_IRQ_MASK_READ__ctl_eot__BITNR) | \ - (R_USB_IRQ_MASK_READ__bulk_eot__##f6##__VAL(R_USB_IRQ_MASK_READ_, bulk_eot_, v6) << R_USB_IRQ_MASK_READ__bulk_eot__BITNR) | \ - (R_USB_IRQ_MASK_READ__epid_attn__##f7##__VAL(R_USB_IRQ_MASK_READ_, epid_attn_, v7) << R_USB_IRQ_MASK_READ__epid_attn__BITNR) | \ - (R_USB_IRQ_MASK_READ__sof__##f8##__VAL(R_USB_IRQ_MASK_READ_, sof_, v8) << R_USB_IRQ_MASK_READ__sof__BITNR) | \ - (R_USB_IRQ_MASK_READ__port_status__##f9##__VAL(R_USB_IRQ_MASK_READ_, port_status_, v9) << R_USB_IRQ_MASK_READ__port_status__BITNR) | \ - (R_USB_IRQ_MASK_READ__ctl_status__##f10##__VAL(R_USB_IRQ_MASK_READ_, ctl_status_, v10) << R_USB_IRQ_MASK_READ__ctl_status__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_IRQ_MASK_READ_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_IRQ_MASK_READ. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_USB_IRQ_MASK_READ_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10) ( \ - (R_USB_IRQ_MASK_READ__iso_eof__##f1_##_VAL(R_USB_IRQ_MASK_READ_, iso_eof_, v1) << R_USB_IRQ_MASK_READ__iso_eof__BITNR) | \ - (R_USB_IRQ_MASK_READ__intr_eof__##f2_##_VAL(R_USB_IRQ_MASK_READ_, intr_eof_, v2) << R_USB_IRQ_MASK_READ__intr_eof__BITNR) | \ - (R_USB_IRQ_MASK_READ__iso_eot__##f3_##_VAL(R_USB_IRQ_MASK_READ_, iso_eot_, v3) << R_USB_IRQ_MASK_READ__iso_eot__BITNR) | \ - (R_USB_IRQ_MASK_READ__intr_eot__##f4_##_VAL(R_USB_IRQ_MASK_READ_, intr_eot_, v4) << R_USB_IRQ_MASK_READ__intr_eot__BITNR) | \ - (R_USB_IRQ_MASK_READ__ctl_eot__##f5_##_VAL(R_USB_IRQ_MASK_READ_, ctl_eot_, v5) << R_USB_IRQ_MASK_READ__ctl_eot__BITNR) | \ - (R_USB_IRQ_MASK_READ__bulk_eot__##f6_##_VAL(R_USB_IRQ_MASK_READ_, bulk_eot_, v6) << R_USB_IRQ_MASK_READ__bulk_eot__BITNR) | \ - (R_USB_IRQ_MASK_READ__epid_attn__##f7_##_VAL(R_USB_IRQ_MASK_READ_, epid_attn_, v7) << R_USB_IRQ_MASK_READ__epid_attn__BITNR) | \ - (R_USB_IRQ_MASK_READ__sof__##f8_##_VAL(R_USB_IRQ_MASK_READ_, sof_, v8) << R_USB_IRQ_MASK_READ__sof__BITNR) | \ - (R_USB_IRQ_MASK_READ__port_status__##f9_##_VAL(R_USB_IRQ_MASK_READ_, port_status_, v9) << R_USB_IRQ_MASK_READ__port_status__BITNR) | \ - (R_USB_IRQ_MASK_READ__ctl_status__##f10_##_VAL(R_USB_IRQ_MASK_READ_, ctl_status_, v10) << R_USB_IRQ_MASK_READ__ctl_status__BITNR) \ -) - -#endif - -/* - * R_USB_IRQ_MASK_READ_DEV - * - type: RO - * - addr: 0xb0000204 - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_USB_IRQ_MASK_READ_DEV -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_USB_IRQ_MASK_READ_DEV(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \ - (R_USB_IRQ_MASK_READ_DEV__out_eot__##f1##__MASK & REG__##v1) | \ - (R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__##f2##__MASK & REG__##v2) | \ - (R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__##f3##__MASK & REG__##v3) | \ - (R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__##f4##__MASK & REG__##v4) | \ - (R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__##f5##__MASK & REG__##v5) | \ - (R_USB_IRQ_MASK_READ_DEV__epid_attn__##f6##__MASK & REG__##v6) | \ - (R_USB_IRQ_MASK_READ_DEV__sof__##f7##__MASK & REG__##v7) | \ - (R_USB_IRQ_MASK_READ_DEV__port_status__##f8##__MASK & REG__##v8) | \ - (R_USB_IRQ_MASK_READ_DEV__ctl_status__##f9##__MASK & REG__##v9) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_IRQ_MASK_READ_DEV -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_IRQ_MASK_READ_DEV. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_USB_IRQ_MASK_READ_DEV(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \ - (R_USB_IRQ_MASK_READ_DEV__out_eot__##f1##__VAL(R_USB_IRQ_MASK_READ_DEV_, out_eot_, v1) << R_USB_IRQ_MASK_READ_DEV__out_eot__BITNR) | \ - (R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__##f2##__VAL(R_USB_IRQ_MASK_READ_DEV_, ep3_in_eot_, v2) << R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__BITNR) | \ - (R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__##f3##__VAL(R_USB_IRQ_MASK_READ_DEV_, ep2_in_eot_, v3) << R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__BITNR) | \ - (R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__##f4##__VAL(R_USB_IRQ_MASK_READ_DEV_, ep1_in_eot_, v4) << R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__BITNR) | \ - (R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__##f5##__VAL(R_USB_IRQ_MASK_READ_DEV_, ep0_in_eot_, v5) << R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__BITNR) | \ - (R_USB_IRQ_MASK_READ_DEV__epid_attn__##f6##__VAL(R_USB_IRQ_MASK_READ_DEV_, epid_attn_, v6) << R_USB_IRQ_MASK_READ_DEV__epid_attn__BITNR) | \ - (R_USB_IRQ_MASK_READ_DEV__sof__##f7##__VAL(R_USB_IRQ_MASK_READ_DEV_, sof_, v7) << R_USB_IRQ_MASK_READ_DEV__sof__BITNR) | \ - (R_USB_IRQ_MASK_READ_DEV__port_status__##f8##__VAL(R_USB_IRQ_MASK_READ_DEV_, port_status_, v8) << R_USB_IRQ_MASK_READ_DEV__port_status__BITNR) | \ - (R_USB_IRQ_MASK_READ_DEV__ctl_status__##f9##__VAL(R_USB_IRQ_MASK_READ_DEV_, ctl_status_, v9) << R_USB_IRQ_MASK_READ_DEV__ctl_status__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_IRQ_MASK_READ_DEV_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_IRQ_MASK_READ_DEV. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_USB_IRQ_MASK_READ_DEV_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9) ( \ - (R_USB_IRQ_MASK_READ_DEV__out_eot__##f1_##_VAL(R_USB_IRQ_MASK_READ_DEV_, out_eot_, v1) << R_USB_IRQ_MASK_READ_DEV__out_eot__BITNR) | \ - (R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__##f2_##_VAL(R_USB_IRQ_MASK_READ_DEV_, ep3_in_eot_, v2) << R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__BITNR) | \ - (R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__##f3_##_VAL(R_USB_IRQ_MASK_READ_DEV_, ep2_in_eot_, v3) << R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__BITNR) | \ - (R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__##f4_##_VAL(R_USB_IRQ_MASK_READ_DEV_, ep1_in_eot_, v4) << R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__BITNR) | \ - (R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__##f5_##_VAL(R_USB_IRQ_MASK_READ_DEV_, ep0_in_eot_, v5) << R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__BITNR) | \ - (R_USB_IRQ_MASK_READ_DEV__epid_attn__##f6_##_VAL(R_USB_IRQ_MASK_READ_DEV_, epid_attn_, v6) << R_USB_IRQ_MASK_READ_DEV__epid_attn__BITNR) | \ - (R_USB_IRQ_MASK_READ_DEV__sof__##f7_##_VAL(R_USB_IRQ_MASK_READ_DEV_, sof_, v7) << R_USB_IRQ_MASK_READ_DEV__sof__BITNR) | \ - (R_USB_IRQ_MASK_READ_DEV__port_status__##f8_##_VAL(R_USB_IRQ_MASK_READ_DEV_, port_status_, v8) << R_USB_IRQ_MASK_READ_DEV__port_status__BITNR) | \ - (R_USB_IRQ_MASK_READ_DEV__ctl_status__##f9_##_VAL(R_USB_IRQ_MASK_READ_DEV_, ctl_status_, v9) << R_USB_IRQ_MASK_READ_DEV__ctl_status__BITNR) \ -) - -#endif - -/* - * R_USB_IRQ_MASK_SET - * - type: WO - * - addr: 0xb0000204 - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_USB_IRQ_MASK_SET -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_USB_IRQ_MASK_SET. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_USB_IRQ_MASK_SET. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_USB_IRQ_MASK_SET(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \ - *R_USB_IRQ_MASK_SET__SADDR = ( \ - REG_INITIATED(R_USB_IRQ_MASK_SET_) \ - REG_VAL__R_USB_IRQ_MASK_SET_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10) \ - ), \ - R_USB_IRQ_MASK_SET__WRITE(R_USB_IRQ_MASK_SET__ADDR, *R_USB_IRQ_MASK_SET__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_USB_IRQ_MASK_SET__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_USB_IRQ_MASK_SET. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_USB_IRQ_MASK_SET. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_USB_IRQ_MASK_SET__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \ - *R_USB_IRQ_MASK_SET__SADDR = ( \ - REG_INITIATED(R_USB_IRQ_MASK_SET_) \ - REG_VAL__R_USB_IRQ_MASK_SET_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_USB_IRQ_MASK_SET -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_USB_IRQ_MASK_SET(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \ - (R_USB_IRQ_MASK_SET__iso_eof__##f1##__MASK & REG__##v1) | \ - (R_USB_IRQ_MASK_SET__intr_eof__##f2##__MASK & REG__##v2) | \ - (R_USB_IRQ_MASK_SET__iso_eot__##f3##__MASK & REG__##v3) | \ - (R_USB_IRQ_MASK_SET__intr_eot__##f4##__MASK & REG__##v4) | \ - (R_USB_IRQ_MASK_SET__ctl_eot__##f5##__MASK & REG__##v5) | \ - (R_USB_IRQ_MASK_SET__bulk_eot__##f6##__MASK & REG__##v6) | \ - (R_USB_IRQ_MASK_SET__epid_attn__##f7##__MASK & REG__##v7) | \ - (R_USB_IRQ_MASK_SET__sof__##f8##__MASK & REG__##v8) | \ - (R_USB_IRQ_MASK_SET__port_status__##f9##__MASK & REG__##v9) | \ - (R_USB_IRQ_MASK_SET__ctl_status__##f10##__MASK & REG__##v10) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_IRQ_MASK_SET -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_IRQ_MASK_SET. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_USB_IRQ_MASK_SET(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \ - (R_USB_IRQ_MASK_SET__iso_eof__##f1##__VAL(R_USB_IRQ_MASK_SET_, iso_eof_, v1) << R_USB_IRQ_MASK_SET__iso_eof__BITNR) | \ - (R_USB_IRQ_MASK_SET__intr_eof__##f2##__VAL(R_USB_IRQ_MASK_SET_, intr_eof_, v2) << R_USB_IRQ_MASK_SET__intr_eof__BITNR) | \ - (R_USB_IRQ_MASK_SET__iso_eot__##f3##__VAL(R_USB_IRQ_MASK_SET_, iso_eot_, v3) << R_USB_IRQ_MASK_SET__iso_eot__BITNR) | \ - (R_USB_IRQ_MASK_SET__intr_eot__##f4##__VAL(R_USB_IRQ_MASK_SET_, intr_eot_, v4) << R_USB_IRQ_MASK_SET__intr_eot__BITNR) | \ - (R_USB_IRQ_MASK_SET__ctl_eot__##f5##__VAL(R_USB_IRQ_MASK_SET_, ctl_eot_, v5) << R_USB_IRQ_MASK_SET__ctl_eot__BITNR) | \ - (R_USB_IRQ_MASK_SET__bulk_eot__##f6##__VAL(R_USB_IRQ_MASK_SET_, bulk_eot_, v6) << R_USB_IRQ_MASK_SET__bulk_eot__BITNR) | \ - (R_USB_IRQ_MASK_SET__epid_attn__##f7##__VAL(R_USB_IRQ_MASK_SET_, epid_attn_, v7) << R_USB_IRQ_MASK_SET__epid_attn__BITNR) | \ - (R_USB_IRQ_MASK_SET__sof__##f8##__VAL(R_USB_IRQ_MASK_SET_, sof_, v8) << R_USB_IRQ_MASK_SET__sof__BITNR) | \ - (R_USB_IRQ_MASK_SET__port_status__##f9##__VAL(R_USB_IRQ_MASK_SET_, port_status_, v9) << R_USB_IRQ_MASK_SET__port_status__BITNR) | \ - (R_USB_IRQ_MASK_SET__ctl_status__##f10##__VAL(R_USB_IRQ_MASK_SET_, ctl_status_, v10) << R_USB_IRQ_MASK_SET__ctl_status__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_IRQ_MASK_SET_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_IRQ_MASK_SET. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_USB_IRQ_MASK_SET_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10) ( \ - (R_USB_IRQ_MASK_SET__iso_eof__##f1_##_VAL(R_USB_IRQ_MASK_SET_, iso_eof_, v1) << R_USB_IRQ_MASK_SET__iso_eof__BITNR) | \ - (R_USB_IRQ_MASK_SET__intr_eof__##f2_##_VAL(R_USB_IRQ_MASK_SET_, intr_eof_, v2) << R_USB_IRQ_MASK_SET__intr_eof__BITNR) | \ - (R_USB_IRQ_MASK_SET__iso_eot__##f3_##_VAL(R_USB_IRQ_MASK_SET_, iso_eot_, v3) << R_USB_IRQ_MASK_SET__iso_eot__BITNR) | \ - (R_USB_IRQ_MASK_SET__intr_eot__##f4_##_VAL(R_USB_IRQ_MASK_SET_, intr_eot_, v4) << R_USB_IRQ_MASK_SET__intr_eot__BITNR) | \ - (R_USB_IRQ_MASK_SET__ctl_eot__##f5_##_VAL(R_USB_IRQ_MASK_SET_, ctl_eot_, v5) << R_USB_IRQ_MASK_SET__ctl_eot__BITNR) | \ - (R_USB_IRQ_MASK_SET__bulk_eot__##f6_##_VAL(R_USB_IRQ_MASK_SET_, bulk_eot_, v6) << R_USB_IRQ_MASK_SET__bulk_eot__BITNR) | \ - (R_USB_IRQ_MASK_SET__epid_attn__##f7_##_VAL(R_USB_IRQ_MASK_SET_, epid_attn_, v7) << R_USB_IRQ_MASK_SET__epid_attn__BITNR) | \ - (R_USB_IRQ_MASK_SET__sof__##f8_##_VAL(R_USB_IRQ_MASK_SET_, sof_, v8) << R_USB_IRQ_MASK_SET__sof__BITNR) | \ - (R_USB_IRQ_MASK_SET__port_status__##f9_##_VAL(R_USB_IRQ_MASK_SET_, port_status_, v9) << R_USB_IRQ_MASK_SET__port_status__BITNR) | \ - (R_USB_IRQ_MASK_SET__ctl_status__##f10_##_VAL(R_USB_IRQ_MASK_SET_, ctl_status_, v10) << R_USB_IRQ_MASK_SET__ctl_status__BITNR) \ -) - -#endif - -/* - * R_USB_IRQ_MASK_SET_DEV - * - type: WO - * - addr: 0xb0000204 - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_USB_IRQ_MASK_SET_DEV -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_USB_IRQ_MASK_SET_DEV. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_USB_IRQ_MASK_SET_DEV. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_USB_IRQ_MASK_SET_DEV(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \ - *R_USB_IRQ_MASK_SET_DEV__SADDR = ( \ - REG_INITIATED(R_USB_IRQ_MASK_SET_DEV_) \ - REG_VAL__R_USB_IRQ_MASK_SET_DEV_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9) \ - ), \ - R_USB_IRQ_MASK_SET_DEV__WRITE(R_USB_IRQ_MASK_SET_DEV__ADDR, *R_USB_IRQ_MASK_SET_DEV__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_USB_IRQ_MASK_SET_DEV__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_USB_IRQ_MASK_SET_DEV. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_USB_IRQ_MASK_SET_DEV. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_USB_IRQ_MASK_SET_DEV__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \ - *R_USB_IRQ_MASK_SET_DEV__SADDR = ( \ - REG_INITIATED(R_USB_IRQ_MASK_SET_DEV_) \ - REG_VAL__R_USB_IRQ_MASK_SET_DEV_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_USB_IRQ_MASK_SET_DEV -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_USB_IRQ_MASK_SET_DEV(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \ - (R_USB_IRQ_MASK_SET_DEV__out_eot__##f1##__MASK & REG__##v1) | \ - (R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__##f2##__MASK & REG__##v2) | \ - (R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__##f3##__MASK & REG__##v3) | \ - (R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__##f4##__MASK & REG__##v4) | \ - (R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__##f5##__MASK & REG__##v5) | \ - (R_USB_IRQ_MASK_SET_DEV__epid_attn__##f6##__MASK & REG__##v6) | \ - (R_USB_IRQ_MASK_SET_DEV__sof__##f7##__MASK & REG__##v7) | \ - (R_USB_IRQ_MASK_SET_DEV__port_status__##f8##__MASK & REG__##v8) | \ - (R_USB_IRQ_MASK_SET_DEV__ctl_status__##f9##__MASK & REG__##v9) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_IRQ_MASK_SET_DEV -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_IRQ_MASK_SET_DEV. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_USB_IRQ_MASK_SET_DEV(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \ - (R_USB_IRQ_MASK_SET_DEV__out_eot__##f1##__VAL(R_USB_IRQ_MASK_SET_DEV_, out_eot_, v1) << R_USB_IRQ_MASK_SET_DEV__out_eot__BITNR) | \ - (R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__##f2##__VAL(R_USB_IRQ_MASK_SET_DEV_, ep3_in_eot_, v2) << R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__BITNR) | \ - (R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__##f3##__VAL(R_USB_IRQ_MASK_SET_DEV_, ep2_in_eot_, v3) << R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__BITNR) | \ - (R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__##f4##__VAL(R_USB_IRQ_MASK_SET_DEV_, ep1_in_eot_, v4) << R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__BITNR) | \ - (R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__##f5##__VAL(R_USB_IRQ_MASK_SET_DEV_, ep0_in_eot_, v5) << R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__BITNR) | \ - (R_USB_IRQ_MASK_SET_DEV__epid_attn__##f6##__VAL(R_USB_IRQ_MASK_SET_DEV_, epid_attn_, v6) << R_USB_IRQ_MASK_SET_DEV__epid_attn__BITNR) | \ - (R_USB_IRQ_MASK_SET_DEV__sof__##f7##__VAL(R_USB_IRQ_MASK_SET_DEV_, sof_, v7) << R_USB_IRQ_MASK_SET_DEV__sof__BITNR) | \ - (R_USB_IRQ_MASK_SET_DEV__port_status__##f8##__VAL(R_USB_IRQ_MASK_SET_DEV_, port_status_, v8) << R_USB_IRQ_MASK_SET_DEV__port_status__BITNR) | \ - (R_USB_IRQ_MASK_SET_DEV__ctl_status__##f9##__VAL(R_USB_IRQ_MASK_SET_DEV_, ctl_status_, v9) << R_USB_IRQ_MASK_SET_DEV__ctl_status__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_IRQ_MASK_SET_DEV_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_IRQ_MASK_SET_DEV. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_USB_IRQ_MASK_SET_DEV_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9) ( \ - (R_USB_IRQ_MASK_SET_DEV__out_eot__##f1_##_VAL(R_USB_IRQ_MASK_SET_DEV_, out_eot_, v1) << R_USB_IRQ_MASK_SET_DEV__out_eot__BITNR) | \ - (R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__##f2_##_VAL(R_USB_IRQ_MASK_SET_DEV_, ep3_in_eot_, v2) << R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__BITNR) | \ - (R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__##f3_##_VAL(R_USB_IRQ_MASK_SET_DEV_, ep2_in_eot_, v3) << R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__BITNR) | \ - (R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__##f4_##_VAL(R_USB_IRQ_MASK_SET_DEV_, ep1_in_eot_, v4) << R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__BITNR) | \ - (R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__##f5_##_VAL(R_USB_IRQ_MASK_SET_DEV_, ep0_in_eot_, v5) << R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__BITNR) | \ - (R_USB_IRQ_MASK_SET_DEV__epid_attn__##f6_##_VAL(R_USB_IRQ_MASK_SET_DEV_, epid_attn_, v6) << R_USB_IRQ_MASK_SET_DEV__epid_attn__BITNR) | \ - (R_USB_IRQ_MASK_SET_DEV__sof__##f7_##_VAL(R_USB_IRQ_MASK_SET_DEV_, sof_, v7) << R_USB_IRQ_MASK_SET_DEV__sof__BITNR) | \ - (R_USB_IRQ_MASK_SET_DEV__port_status__##f8_##_VAL(R_USB_IRQ_MASK_SET_DEV_, port_status_, v8) << R_USB_IRQ_MASK_SET_DEV__port_status__BITNR) | \ - (R_USB_IRQ_MASK_SET_DEV__ctl_status__##f9_##_VAL(R_USB_IRQ_MASK_SET_DEV_, ctl_status_, v9) << R_USB_IRQ_MASK_SET_DEV__ctl_status__BITNR) \ -) - -#endif - -/* - * R_USB_IRQ_READ - * - type: RO - * - addr: 0xb0000206 - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_USB_IRQ_READ -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_USB_IRQ_READ(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \ - (R_USB_IRQ_READ__iso_eof__##f1##__MASK & REG__##v1) | \ - (R_USB_IRQ_READ__intr_eof__##f2##__MASK & REG__##v2) | \ - (R_USB_IRQ_READ__iso_eot__##f3##__MASK & REG__##v3) | \ - (R_USB_IRQ_READ__intr_eot__##f4##__MASK & REG__##v4) | \ - (R_USB_IRQ_READ__ctl_eot__##f5##__MASK & REG__##v5) | \ - (R_USB_IRQ_READ__bulk_eot__##f6##__MASK & REG__##v6) | \ - (R_USB_IRQ_READ__epid_attn__##f7##__MASK & REG__##v7) | \ - (R_USB_IRQ_READ__sof__##f8##__MASK & REG__##v8) | \ - (R_USB_IRQ_READ__port_status__##f9##__MASK & REG__##v9) | \ - (R_USB_IRQ_READ__ctl_status__##f10##__MASK & REG__##v10) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_IRQ_READ -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_IRQ_READ. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_USB_IRQ_READ(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \ - (R_USB_IRQ_READ__iso_eof__##f1##__VAL(R_USB_IRQ_READ_, iso_eof_, v1) << R_USB_IRQ_READ__iso_eof__BITNR) | \ - (R_USB_IRQ_READ__intr_eof__##f2##__VAL(R_USB_IRQ_READ_, intr_eof_, v2) << R_USB_IRQ_READ__intr_eof__BITNR) | \ - (R_USB_IRQ_READ__iso_eot__##f3##__VAL(R_USB_IRQ_READ_, iso_eot_, v3) << R_USB_IRQ_READ__iso_eot__BITNR) | \ - (R_USB_IRQ_READ__intr_eot__##f4##__VAL(R_USB_IRQ_READ_, intr_eot_, v4) << R_USB_IRQ_READ__intr_eot__BITNR) | \ - (R_USB_IRQ_READ__ctl_eot__##f5##__VAL(R_USB_IRQ_READ_, ctl_eot_, v5) << R_USB_IRQ_READ__ctl_eot__BITNR) | \ - (R_USB_IRQ_READ__bulk_eot__##f6##__VAL(R_USB_IRQ_READ_, bulk_eot_, v6) << R_USB_IRQ_READ__bulk_eot__BITNR) | \ - (R_USB_IRQ_READ__epid_attn__##f7##__VAL(R_USB_IRQ_READ_, epid_attn_, v7) << R_USB_IRQ_READ__epid_attn__BITNR) | \ - (R_USB_IRQ_READ__sof__##f8##__VAL(R_USB_IRQ_READ_, sof_, v8) << R_USB_IRQ_READ__sof__BITNR) | \ - (R_USB_IRQ_READ__port_status__##f9##__VAL(R_USB_IRQ_READ_, port_status_, v9) << R_USB_IRQ_READ__port_status__BITNR) | \ - (R_USB_IRQ_READ__ctl_status__##f10##__VAL(R_USB_IRQ_READ_, ctl_status_, v10) << R_USB_IRQ_READ__ctl_status__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_IRQ_READ_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_IRQ_READ. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_USB_IRQ_READ_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10) ( \ - (R_USB_IRQ_READ__iso_eof__##f1_##_VAL(R_USB_IRQ_READ_, iso_eof_, v1) << R_USB_IRQ_READ__iso_eof__BITNR) | \ - (R_USB_IRQ_READ__intr_eof__##f2_##_VAL(R_USB_IRQ_READ_, intr_eof_, v2) << R_USB_IRQ_READ__intr_eof__BITNR) | \ - (R_USB_IRQ_READ__iso_eot__##f3_##_VAL(R_USB_IRQ_READ_, iso_eot_, v3) << R_USB_IRQ_READ__iso_eot__BITNR) | \ - (R_USB_IRQ_READ__intr_eot__##f4_##_VAL(R_USB_IRQ_READ_, intr_eot_, v4) << R_USB_IRQ_READ__intr_eot__BITNR) | \ - (R_USB_IRQ_READ__ctl_eot__##f5_##_VAL(R_USB_IRQ_READ_, ctl_eot_, v5) << R_USB_IRQ_READ__ctl_eot__BITNR) | \ - (R_USB_IRQ_READ__bulk_eot__##f6_##_VAL(R_USB_IRQ_READ_, bulk_eot_, v6) << R_USB_IRQ_READ__bulk_eot__BITNR) | \ - (R_USB_IRQ_READ__epid_attn__##f7_##_VAL(R_USB_IRQ_READ_, epid_attn_, v7) << R_USB_IRQ_READ__epid_attn__BITNR) | \ - (R_USB_IRQ_READ__sof__##f8_##_VAL(R_USB_IRQ_READ_, sof_, v8) << R_USB_IRQ_READ__sof__BITNR) | \ - (R_USB_IRQ_READ__port_status__##f9_##_VAL(R_USB_IRQ_READ_, port_status_, v9) << R_USB_IRQ_READ__port_status__BITNR) | \ - (R_USB_IRQ_READ__ctl_status__##f10_##_VAL(R_USB_IRQ_READ_, ctl_status_, v10) << R_USB_IRQ_READ__ctl_status__BITNR) \ -) - -#endif - -/* - * R_USB_IRQ_READ_DEV - * - type: RO - * - addr: 0xb0000206 - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_USB_IRQ_READ_DEV -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_USB_IRQ_READ_DEV(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \ - (R_USB_IRQ_READ_DEV__out_eot__##f1##__MASK & REG__##v1) | \ - (R_USB_IRQ_READ_DEV__ep3_in_eot__##f2##__MASK & REG__##v2) | \ - (R_USB_IRQ_READ_DEV__ep2_in_eot__##f3##__MASK & REG__##v3) | \ - (R_USB_IRQ_READ_DEV__ep1_in_eot__##f4##__MASK & REG__##v4) | \ - (R_USB_IRQ_READ_DEV__ep0_in_eot__##f5##__MASK & REG__##v5) | \ - (R_USB_IRQ_READ_DEV__epid_attn__##f6##__MASK & REG__##v6) | \ - (R_USB_IRQ_READ_DEV__sof__##f7##__MASK & REG__##v7) | \ - (R_USB_IRQ_READ_DEV__port_status__##f8##__MASK & REG__##v8) | \ - (R_USB_IRQ_READ_DEV__ctl_status__##f9##__MASK & REG__##v9) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_IRQ_READ_DEV -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_IRQ_READ_DEV. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_USB_IRQ_READ_DEV(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \ - (R_USB_IRQ_READ_DEV__out_eot__##f1##__VAL(R_USB_IRQ_READ_DEV_, out_eot_, v1) << R_USB_IRQ_READ_DEV__out_eot__BITNR) | \ - (R_USB_IRQ_READ_DEV__ep3_in_eot__##f2##__VAL(R_USB_IRQ_READ_DEV_, ep3_in_eot_, v2) << R_USB_IRQ_READ_DEV__ep3_in_eot__BITNR) | \ - (R_USB_IRQ_READ_DEV__ep2_in_eot__##f3##__VAL(R_USB_IRQ_READ_DEV_, ep2_in_eot_, v3) << R_USB_IRQ_READ_DEV__ep2_in_eot__BITNR) | \ - (R_USB_IRQ_READ_DEV__ep1_in_eot__##f4##__VAL(R_USB_IRQ_READ_DEV_, ep1_in_eot_, v4) << R_USB_IRQ_READ_DEV__ep1_in_eot__BITNR) | \ - (R_USB_IRQ_READ_DEV__ep0_in_eot__##f5##__VAL(R_USB_IRQ_READ_DEV_, ep0_in_eot_, v5) << R_USB_IRQ_READ_DEV__ep0_in_eot__BITNR) | \ - (R_USB_IRQ_READ_DEV__epid_attn__##f6##__VAL(R_USB_IRQ_READ_DEV_, epid_attn_, v6) << R_USB_IRQ_READ_DEV__epid_attn__BITNR) | \ - (R_USB_IRQ_READ_DEV__sof__##f7##__VAL(R_USB_IRQ_READ_DEV_, sof_, v7) << R_USB_IRQ_READ_DEV__sof__BITNR) | \ - (R_USB_IRQ_READ_DEV__port_status__##f8##__VAL(R_USB_IRQ_READ_DEV_, port_status_, v8) << R_USB_IRQ_READ_DEV__port_status__BITNR) | \ - (R_USB_IRQ_READ_DEV__ctl_status__##f9##__VAL(R_USB_IRQ_READ_DEV_, ctl_status_, v9) << R_USB_IRQ_READ_DEV__ctl_status__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_IRQ_READ_DEV_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_IRQ_READ_DEV. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_USB_IRQ_READ_DEV_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9) ( \ - (R_USB_IRQ_READ_DEV__out_eot__##f1_##_VAL(R_USB_IRQ_READ_DEV_, out_eot_, v1) << R_USB_IRQ_READ_DEV__out_eot__BITNR) | \ - (R_USB_IRQ_READ_DEV__ep3_in_eot__##f2_##_VAL(R_USB_IRQ_READ_DEV_, ep3_in_eot_, v2) << R_USB_IRQ_READ_DEV__ep3_in_eot__BITNR) | \ - (R_USB_IRQ_READ_DEV__ep2_in_eot__##f3_##_VAL(R_USB_IRQ_READ_DEV_, ep2_in_eot_, v3) << R_USB_IRQ_READ_DEV__ep2_in_eot__BITNR) | \ - (R_USB_IRQ_READ_DEV__ep1_in_eot__##f4_##_VAL(R_USB_IRQ_READ_DEV_, ep1_in_eot_, v4) << R_USB_IRQ_READ_DEV__ep1_in_eot__BITNR) | \ - (R_USB_IRQ_READ_DEV__ep0_in_eot__##f5_##_VAL(R_USB_IRQ_READ_DEV_, ep0_in_eot_, v5) << R_USB_IRQ_READ_DEV__ep0_in_eot__BITNR) | \ - (R_USB_IRQ_READ_DEV__epid_attn__##f6_##_VAL(R_USB_IRQ_READ_DEV_, epid_attn_, v6) << R_USB_IRQ_READ_DEV__epid_attn__BITNR) | \ - (R_USB_IRQ_READ_DEV__sof__##f7_##_VAL(R_USB_IRQ_READ_DEV_, sof_, v7) << R_USB_IRQ_READ_DEV__sof__BITNR) | \ - (R_USB_IRQ_READ_DEV__port_status__##f8_##_VAL(R_USB_IRQ_READ_DEV_, port_status_, v8) << R_USB_IRQ_READ_DEV__port_status__BITNR) | \ - (R_USB_IRQ_READ_DEV__ctl_status__##f9_##_VAL(R_USB_IRQ_READ_DEV_, ctl_status_, v9) << R_USB_IRQ_READ_DEV__ctl_status__BITNR) \ -) - -#endif - -/* - * R_USB_PORT1_DISABLE - * - type: WO - * - addr: 0xb000006a - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_USB_PORT1_DISABLE -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_USB_PORT1_DISABLE. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_USB_PORT1_DISABLE. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_USB_PORT1_DISABLE(f1,v1) ( \ - *R_USB_PORT1_DISABLE__SADDR = ( \ - REG_INITIATED(R_USB_PORT1_DISABLE_) \ - REG_VAL__R_USB_PORT1_DISABLE_(f1##_,v1) \ - ), \ - R_USB_PORT1_DISABLE__WRITE(R_USB_PORT1_DISABLE__ADDR, *R_USB_PORT1_DISABLE__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_USB_PORT1_DISABLE__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_USB_PORT1_DISABLE. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_USB_PORT1_DISABLE. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_USB_PORT1_DISABLE__SHADOW(f1,v1) ( \ - *R_USB_PORT1_DISABLE__SADDR = ( \ - REG_INITIATED(R_USB_PORT1_DISABLE_) \ - REG_VAL__R_USB_PORT1_DISABLE_(f1##_,v1) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_USB_PORT1_DISABLE -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_USB_PORT1_DISABLE(f1,v1) ( \ - (R_USB_PORT1_DISABLE__disable__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_PORT1_DISABLE -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_PORT1_DISABLE. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_USB_PORT1_DISABLE(f1,v1) ( \ - (R_USB_PORT1_DISABLE__disable__##f1##__VAL(R_USB_PORT1_DISABLE_, disable_, v1) << R_USB_PORT1_DISABLE__disable__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_PORT1_DISABLE_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_PORT1_DISABLE. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_USB_PORT1_DISABLE_(f1_,v1) ( \ - (R_USB_PORT1_DISABLE__disable__##f1_##_VAL(R_USB_PORT1_DISABLE_, disable_, v1) << R_USB_PORT1_DISABLE__disable__BITNR) \ -) - -#endif - -/* - * R_USB_PORT2_DISABLE - * - type: WO - * - addr: 0xb0000052 - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_USB_PORT2_DISABLE -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_USB_PORT2_DISABLE. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_USB_PORT2_DISABLE. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_USB_PORT2_DISABLE(f1,v1) ( \ - *R_USB_PORT2_DISABLE__SADDR = ( \ - REG_INITIATED(R_USB_PORT2_DISABLE_) \ - REG_VAL__R_USB_PORT2_DISABLE_(f1##_,v1) \ - ), \ - R_USB_PORT2_DISABLE__WRITE(R_USB_PORT2_DISABLE__ADDR, *R_USB_PORT2_DISABLE__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_USB_PORT2_DISABLE__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_USB_PORT2_DISABLE. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_USB_PORT2_DISABLE. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_USB_PORT2_DISABLE__SHADOW(f1,v1) ( \ - *R_USB_PORT2_DISABLE__SADDR = ( \ - REG_INITIATED(R_USB_PORT2_DISABLE_) \ - REG_VAL__R_USB_PORT2_DISABLE_(f1##_,v1) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_USB_PORT2_DISABLE -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_USB_PORT2_DISABLE(f1,v1) ( \ - (R_USB_PORT2_DISABLE__disable__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_PORT2_DISABLE -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_PORT2_DISABLE. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_USB_PORT2_DISABLE(f1,v1) ( \ - (R_USB_PORT2_DISABLE__disable__##f1##__VAL(R_USB_PORT2_DISABLE_, disable_, v1) << R_USB_PORT2_DISABLE__disable__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_PORT2_DISABLE_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_PORT2_DISABLE. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_USB_PORT2_DISABLE_(f1_,v1) ( \ - (R_USB_PORT2_DISABLE__disable__##f1_##_VAL(R_USB_PORT2_DISABLE_, disable_, v1) << R_USB_PORT2_DISABLE__disable__BITNR) \ -) - -#endif - -/* - * R_USB_REVISION - * - type: RO - * - addr: 0xb0000200 - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_USB_REVISION -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_USB_REVISION(f1,v1,f2,v2) ( \ - (R_USB_REVISION__major__##f1##__MASK & REG__##v1) | \ - (R_USB_REVISION__minor__##f2##__MASK & REG__##v2) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_REVISION -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_REVISION. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_USB_REVISION(f1,v1,f2,v2) ( \ - (R_USB_REVISION__major__##f1##__VAL(R_USB_REVISION_, major_, v1) << R_USB_REVISION__major__BITNR) | \ - (R_USB_REVISION__minor__##f2##__VAL(R_USB_REVISION_, minor_, v2) << R_USB_REVISION__minor__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_REVISION_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_REVISION. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_USB_REVISION_(f1_,v1,f2_,v2) ( \ - (R_USB_REVISION__major__##f1_##_VAL(R_USB_REVISION_, major_, v1) << R_USB_REVISION__major__BITNR) | \ - (R_USB_REVISION__minor__##f2_##_VAL(R_USB_REVISION_, minor_, v2) << R_USB_REVISION__minor__BITNR) \ -) - -#endif - -/* - * R_USB_RH_PORT_STATUS_1 - * - type: RO - * - addr: 0xb0000218 - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_USB_RH_PORT_STATUS_1 -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_USB_RH_PORT_STATUS_1(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7) ( \ - (R_USB_RH_PORT_STATUS_1__speed__##f1##__MASK & REG__##v1) | \ - (R_USB_RH_PORT_STATUS_1__power__##f2##__MASK & REG__##v2) | \ - (R_USB_RH_PORT_STATUS_1__reset__##f3##__MASK & REG__##v3) | \ - (R_USB_RH_PORT_STATUS_1__overcurrent__##f4##__MASK & REG__##v4) | \ - (R_USB_RH_PORT_STATUS_1__suspended__##f5##__MASK & REG__##v5) | \ - (R_USB_RH_PORT_STATUS_1__enabled__##f6##__MASK & REG__##v6) | \ - (R_USB_RH_PORT_STATUS_1__connected__##f7##__MASK & REG__##v7) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_RH_PORT_STATUS_1 -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_RH_PORT_STATUS_1. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_USB_RH_PORT_STATUS_1(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7) ( \ - (R_USB_RH_PORT_STATUS_1__speed__##f1##__VAL(R_USB_RH_PORT_STATUS_1_, speed_, v1) << R_USB_RH_PORT_STATUS_1__speed__BITNR) | \ - (R_USB_RH_PORT_STATUS_1__power__##f2##__VAL(R_USB_RH_PORT_STATUS_1_, power_, v2) << R_USB_RH_PORT_STATUS_1__power__BITNR) | \ - (R_USB_RH_PORT_STATUS_1__reset__##f3##__VAL(R_USB_RH_PORT_STATUS_1_, reset_, v3) << R_USB_RH_PORT_STATUS_1__reset__BITNR) | \ - (R_USB_RH_PORT_STATUS_1__overcurrent__##f4##__VAL(R_USB_RH_PORT_STATUS_1_, overcurrent_, v4) << R_USB_RH_PORT_STATUS_1__overcurrent__BITNR) | \ - (R_USB_RH_PORT_STATUS_1__suspended__##f5##__VAL(R_USB_RH_PORT_STATUS_1_, suspended_, v5) << R_USB_RH_PORT_STATUS_1__suspended__BITNR) | \ - (R_USB_RH_PORT_STATUS_1__enabled__##f6##__VAL(R_USB_RH_PORT_STATUS_1_, enabled_, v6) << R_USB_RH_PORT_STATUS_1__enabled__BITNR) | \ - (R_USB_RH_PORT_STATUS_1__connected__##f7##__VAL(R_USB_RH_PORT_STATUS_1_, connected_, v7) << R_USB_RH_PORT_STATUS_1__connected__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_RH_PORT_STATUS_1_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_RH_PORT_STATUS_1. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_USB_RH_PORT_STATUS_1_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7) ( \ - (R_USB_RH_PORT_STATUS_1__speed__##f1_##_VAL(R_USB_RH_PORT_STATUS_1_, speed_, v1) << R_USB_RH_PORT_STATUS_1__speed__BITNR) | \ - (R_USB_RH_PORT_STATUS_1__power__##f2_##_VAL(R_USB_RH_PORT_STATUS_1_, power_, v2) << R_USB_RH_PORT_STATUS_1__power__BITNR) | \ - (R_USB_RH_PORT_STATUS_1__reset__##f3_##_VAL(R_USB_RH_PORT_STATUS_1_, reset_, v3) << R_USB_RH_PORT_STATUS_1__reset__BITNR) | \ - (R_USB_RH_PORT_STATUS_1__overcurrent__##f4_##_VAL(R_USB_RH_PORT_STATUS_1_, overcurrent_, v4) << R_USB_RH_PORT_STATUS_1__overcurrent__BITNR) | \ - (R_USB_RH_PORT_STATUS_1__suspended__##f5_##_VAL(R_USB_RH_PORT_STATUS_1_, suspended_, v5) << R_USB_RH_PORT_STATUS_1__suspended__BITNR) | \ - (R_USB_RH_PORT_STATUS_1__enabled__##f6_##_VAL(R_USB_RH_PORT_STATUS_1_, enabled_, v6) << R_USB_RH_PORT_STATUS_1__enabled__BITNR) | \ - (R_USB_RH_PORT_STATUS_1__connected__##f7_##_VAL(R_USB_RH_PORT_STATUS_1_, connected_, v7) << R_USB_RH_PORT_STATUS_1__connected__BITNR) \ -) - -#endif - -/* - * R_USB_RH_PORT_STATUS_2 - * - type: RO - * - addr: 0xb000021a - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_USB_RH_PORT_STATUS_2 -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_USB_RH_PORT_STATUS_2(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7) ( \ - (R_USB_RH_PORT_STATUS_2__speed__##f1##__MASK & REG__##v1) | \ - (R_USB_RH_PORT_STATUS_2__power__##f2##__MASK & REG__##v2) | \ - (R_USB_RH_PORT_STATUS_2__reset__##f3##__MASK & REG__##v3) | \ - (R_USB_RH_PORT_STATUS_2__overcurrent__##f4##__MASK & REG__##v4) | \ - (R_USB_RH_PORT_STATUS_2__suspended__##f5##__MASK & REG__##v5) | \ - (R_USB_RH_PORT_STATUS_2__enabled__##f6##__MASK & REG__##v6) | \ - (R_USB_RH_PORT_STATUS_2__connected__##f7##__MASK & REG__##v7) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_RH_PORT_STATUS_2 -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_RH_PORT_STATUS_2. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_USB_RH_PORT_STATUS_2(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7) ( \ - (R_USB_RH_PORT_STATUS_2__speed__##f1##__VAL(R_USB_RH_PORT_STATUS_2_, speed_, v1) << R_USB_RH_PORT_STATUS_2__speed__BITNR) | \ - (R_USB_RH_PORT_STATUS_2__power__##f2##__VAL(R_USB_RH_PORT_STATUS_2_, power_, v2) << R_USB_RH_PORT_STATUS_2__power__BITNR) | \ - (R_USB_RH_PORT_STATUS_2__reset__##f3##__VAL(R_USB_RH_PORT_STATUS_2_, reset_, v3) << R_USB_RH_PORT_STATUS_2__reset__BITNR) | \ - (R_USB_RH_PORT_STATUS_2__overcurrent__##f4##__VAL(R_USB_RH_PORT_STATUS_2_, overcurrent_, v4) << R_USB_RH_PORT_STATUS_2__overcurrent__BITNR) | \ - (R_USB_RH_PORT_STATUS_2__suspended__##f5##__VAL(R_USB_RH_PORT_STATUS_2_, suspended_, v5) << R_USB_RH_PORT_STATUS_2__suspended__BITNR) | \ - (R_USB_RH_PORT_STATUS_2__enabled__##f6##__VAL(R_USB_RH_PORT_STATUS_2_, enabled_, v6) << R_USB_RH_PORT_STATUS_2__enabled__BITNR) | \ - (R_USB_RH_PORT_STATUS_2__connected__##f7##__VAL(R_USB_RH_PORT_STATUS_2_, connected_, v7) << R_USB_RH_PORT_STATUS_2__connected__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_RH_PORT_STATUS_2_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_RH_PORT_STATUS_2. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_USB_RH_PORT_STATUS_2_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7) ( \ - (R_USB_RH_PORT_STATUS_2__speed__##f1_##_VAL(R_USB_RH_PORT_STATUS_2_, speed_, v1) << R_USB_RH_PORT_STATUS_2__speed__BITNR) | \ - (R_USB_RH_PORT_STATUS_2__power__##f2_##_VAL(R_USB_RH_PORT_STATUS_2_, power_, v2) << R_USB_RH_PORT_STATUS_2__power__BITNR) | \ - (R_USB_RH_PORT_STATUS_2__reset__##f3_##_VAL(R_USB_RH_PORT_STATUS_2_, reset_, v3) << R_USB_RH_PORT_STATUS_2__reset__BITNR) | \ - (R_USB_RH_PORT_STATUS_2__overcurrent__##f4_##_VAL(R_USB_RH_PORT_STATUS_2_, overcurrent_, v4) << R_USB_RH_PORT_STATUS_2__overcurrent__BITNR) | \ - (R_USB_RH_PORT_STATUS_2__suspended__##f5_##_VAL(R_USB_RH_PORT_STATUS_2_, suspended_, v5) << R_USB_RH_PORT_STATUS_2__suspended__BITNR) | \ - (R_USB_RH_PORT_STATUS_2__enabled__##f6_##_VAL(R_USB_RH_PORT_STATUS_2_, enabled_, v6) << R_USB_RH_PORT_STATUS_2__enabled__BITNR) | \ - (R_USB_RH_PORT_STATUS_2__connected__##f7_##_VAL(R_USB_RH_PORT_STATUS_2_, connected_, v7) << R_USB_RH_PORT_STATUS_2__connected__BITNR) \ -) - -#endif - -/* - * R_USB_RH_STATUS - * - type: RO - * - addr: 0xb0000203 - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_USB_RH_STATUS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_USB_RH_STATUS(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5) ( \ - (R_USB_RH_STATUS__babble2__##f1##__MASK & REG__##v1) | \ - (R_USB_RH_STATUS__babble1__##f2##__MASK & REG__##v2) | \ - (R_USB_RH_STATUS__bus1__##f3##__MASK & REG__##v3) | \ - (R_USB_RH_STATUS__bus2__##f4##__MASK & REG__##v4) | \ - (R_USB_RH_STATUS__nports__##f5##__MASK & REG__##v5) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_RH_STATUS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_RH_STATUS. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_USB_RH_STATUS(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5) ( \ - (R_USB_RH_STATUS__babble2__##f1##__VAL(R_USB_RH_STATUS_, babble2_, v1) << R_USB_RH_STATUS__babble2__BITNR) | \ - (R_USB_RH_STATUS__babble1__##f2##__VAL(R_USB_RH_STATUS_, babble1_, v2) << R_USB_RH_STATUS__babble1__BITNR) | \ - (R_USB_RH_STATUS__bus1__##f3##__VAL(R_USB_RH_STATUS_, bus1_, v3) << R_USB_RH_STATUS__bus1__BITNR) | \ - (R_USB_RH_STATUS__bus2__##f4##__VAL(R_USB_RH_STATUS_, bus2_, v4) << R_USB_RH_STATUS__bus2__BITNR) | \ - (R_USB_RH_STATUS__nports__##f5##__VAL(R_USB_RH_STATUS_, nports_, v5) << R_USB_RH_STATUS__nports__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_RH_STATUS_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_RH_STATUS. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_USB_RH_STATUS_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5) ( \ - (R_USB_RH_STATUS__babble2__##f1_##_VAL(R_USB_RH_STATUS_, babble2_, v1) << R_USB_RH_STATUS__babble2__BITNR) | \ - (R_USB_RH_STATUS__babble1__##f2_##_VAL(R_USB_RH_STATUS_, babble1_, v2) << R_USB_RH_STATUS__babble1__BITNR) | \ - (R_USB_RH_STATUS__bus1__##f3_##_VAL(R_USB_RH_STATUS_, bus1_, v3) << R_USB_RH_STATUS__bus1__BITNR) | \ - (R_USB_RH_STATUS__bus2__##f4_##_VAL(R_USB_RH_STATUS_, bus2_, v4) << R_USB_RH_STATUS__bus2__BITNR) | \ - (R_USB_RH_STATUS__nports__##f5_##_VAL(R_USB_RH_STATUS_, nports_, v5) << R_USB_RH_STATUS__nports__BITNR) \ -) - -#endif - -/* - * R_USB_SNMP_TERROR - * - type: RW - * - addr: 0xb0000220 - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_USB_SNMP_TERROR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_USB_SNMP_TERROR. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_USB_SNMP_TERROR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_USB_SNMP_TERROR(f1,v1) ( \ - R_USB_SNMP_TERROR__WRITE(R_USB_SNMP_TERROR__ADDR, ( \ - REG_VAL__R_USB_SNMP_TERROR_(f1##_,v1) ) \ - ) \ -) - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_USB_SNMP_TERROR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_USB_SNMP_TERROR(f1,v1) ( \ - (R_USB_SNMP_TERROR__value__##f1##__MASK & REG__##v1) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_SNMP_TERROR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_SNMP_TERROR. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_USB_SNMP_TERROR(f1,v1) ( \ - (R_USB_SNMP_TERROR__value__##f1##__VAL(R_USB_SNMP_TERROR_, value_, v1) << R_USB_SNMP_TERROR__value__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_SNMP_TERROR_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_SNMP_TERROR. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_USB_SNMP_TERROR_(f1_,v1) ( \ - (R_USB_SNMP_TERROR__value__##f1_##_VAL(R_USB_SNMP_TERROR_, value_, v1) << R_USB_SNMP_TERROR__value__BITNR) \ -) - -#endif - -/* - * R_USB_STATUS - * - type: RO - * - addr: 0xb0000202 - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_USB_STATUS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_USB_STATUS(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \ - (R_USB_STATUS__ourun__##f1##__MASK & REG__##v1) | \ - (R_USB_STATUS__perror__##f2##__MASK & REG__##v2) | \ - (R_USB_STATUS__device_mode__##f3##__MASK & REG__##v3) | \ - (R_USB_STATUS__host_mode__##f4##__MASK & REG__##v4) | \ - (R_USB_STATUS__started__##f5##__MASK & REG__##v5) | \ - (R_USB_STATUS__running__##f6##__MASK & REG__##v6) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_STATUS -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_STATUS. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_USB_STATUS(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \ - (R_USB_STATUS__ourun__##f1##__VAL(R_USB_STATUS_, ourun_, v1) << R_USB_STATUS__ourun__BITNR) | \ - (R_USB_STATUS__perror__##f2##__VAL(R_USB_STATUS_, perror_, v2) << R_USB_STATUS__perror__BITNR) | \ - (R_USB_STATUS__device_mode__##f3##__VAL(R_USB_STATUS_, device_mode_, v3) << R_USB_STATUS__device_mode__BITNR) | \ - (R_USB_STATUS__host_mode__##f4##__VAL(R_USB_STATUS_, host_mode_, v4) << R_USB_STATUS__host_mode__BITNR) | \ - (R_USB_STATUS__started__##f5##__VAL(R_USB_STATUS_, started_, v5) << R_USB_STATUS__started__BITNR) | \ - (R_USB_STATUS__running__##f6##__VAL(R_USB_STATUS_, running_, v6) << R_USB_STATUS__running__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_USB_STATUS_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_USB_STATUS. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_USB_STATUS_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6) ( \ - (R_USB_STATUS__ourun__##f1_##_VAL(R_USB_STATUS_, ourun_, v1) << R_USB_STATUS__ourun__BITNR) | \ - (R_USB_STATUS__perror__##f2_##_VAL(R_USB_STATUS_, perror_, v2) << R_USB_STATUS__perror__BITNR) | \ - (R_USB_STATUS__device_mode__##f3_##_VAL(R_USB_STATUS_, device_mode_, v3) << R_USB_STATUS__device_mode__BITNR) | \ - (R_USB_STATUS__host_mode__##f4_##_VAL(R_USB_STATUS_, host_mode_, v4) << R_USB_STATUS__host_mode__BITNR) | \ - (R_USB_STATUS__started__##f5_##_VAL(R_USB_STATUS_, started_, v5) << R_USB_STATUS__started__BITNR) | \ - (R_USB_STATUS__running__##f6_##_VAL(R_USB_STATUS_, running_, v6) << R_USB_STATUS__running__BITNR) \ -) - -#endif - -/* - * R_VECT_MASK_CLR - * - type: WO - * - addr: 0xb00000d8 - * - group: Interrupt mask and status registers - */ - -#if USE_GROUP__Interrupt_mask_and_status_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_VECT_MASK_CLR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_VECT_MASK_CLR. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_VECT_MASK_CLR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_VECT_MASK_CLR(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25) ( \ - *R_VECT_MASK_CLR__SADDR = ( \ - REG_INITIATED(R_VECT_MASK_CLR_) \ - REG_VAL__R_VECT_MASK_CLR_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20,f21##_,v21,f22##_,v22,f23##_,v23,f24##_,v24,f25##_,v25) \ - ), \ - R_VECT_MASK_CLR__WRITE(R_VECT_MASK_CLR__ADDR, *R_VECT_MASK_CLR__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_VECT_MASK_CLR__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_VECT_MASK_CLR. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_VECT_MASK_CLR. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_VECT_MASK_CLR__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25) ( \ - *R_VECT_MASK_CLR__SADDR = ( \ - REG_INITIATED(R_VECT_MASK_CLR_) \ - REG_VAL__R_VECT_MASK_CLR_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20,f21##_,v21,f22##_,v22,f23##_,v23,f24##_,v24,f25##_,v25) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_VECT_MASK_CLR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_VECT_MASK_CLR(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25) ( \ - (R_VECT_MASK_CLR__usb__##f1##__MASK & REG__##v1) | \ - (R_VECT_MASK_CLR__dma9__##f2##__MASK & REG__##v2) | \ - (R_VECT_MASK_CLR__dma8__##f3##__MASK & REG__##v3) | \ - (R_VECT_MASK_CLR__dma7__##f4##__MASK & REG__##v4) | \ - (R_VECT_MASK_CLR__dma6__##f5##__MASK & REG__##v5) | \ - (R_VECT_MASK_CLR__dma5__##f6##__MASK & REG__##v6) | \ - (R_VECT_MASK_CLR__dma4__##f7##__MASK & REG__##v7) | \ - (R_VECT_MASK_CLR__dma3__##f8##__MASK & REG__##v8) | \ - (R_VECT_MASK_CLR__dma2__##f9##__MASK & REG__##v9) | \ - (R_VECT_MASK_CLR__dma1__##f10##__MASK & REG__##v10) | \ - (R_VECT_MASK_CLR__dma0__##f11##__MASK & REG__##v11) | \ - (R_VECT_MASK_CLR__ext_dma1__##f12##__MASK & REG__##v12) | \ - (R_VECT_MASK_CLR__ext_dma0__##f13##__MASK & REG__##v13) | \ - (R_VECT_MASK_CLR__pa__##f14##__MASK & REG__##v14) | \ - (R_VECT_MASK_CLR__irq_intnr__##f15##__MASK & REG__##v15) | \ - (R_VECT_MASK_CLR__sw__##f16##__MASK & REG__##v16) | \ - (R_VECT_MASK_CLR__serial__##f17##__MASK & REG__##v17) | \ - (R_VECT_MASK_CLR__snmp__##f18##__MASK & REG__##v18) | \ - (R_VECT_MASK_CLR__network__##f19##__MASK & REG__##v19) | \ - (R_VECT_MASK_CLR__scsi1__##f20##__MASK & REG__##v20) | \ - (R_VECT_MASK_CLR__scsi0__##f21##__MASK & REG__##v21) | \ - (R_VECT_MASK_CLR__timer1__##f22##__MASK & REG__##v22) | \ - (R_VECT_MASK_CLR__timer0__##f23##__MASK & REG__##v23) | \ - (R_VECT_MASK_CLR__nmi__##f24##__MASK & REG__##v24) | \ - (R_VECT_MASK_CLR__some__##f25##__MASK & REG__##v25) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_VECT_MASK_CLR -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_VECT_MASK_CLR. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_VECT_MASK_CLR(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25) ( \ - (R_VECT_MASK_CLR__usb__##f1##__VAL(R_VECT_MASK_CLR_, usb_, v1) << R_VECT_MASK_CLR__usb__BITNR) | \ - (R_VECT_MASK_CLR__dma9__##f2##__VAL(R_VECT_MASK_CLR_, dma9_, v2) << R_VECT_MASK_CLR__dma9__BITNR) | \ - (R_VECT_MASK_CLR__dma8__##f3##__VAL(R_VECT_MASK_CLR_, dma8_, v3) << R_VECT_MASK_CLR__dma8__BITNR) | \ - (R_VECT_MASK_CLR__dma7__##f4##__VAL(R_VECT_MASK_CLR_, dma7_, v4) << R_VECT_MASK_CLR__dma7__BITNR) | \ - (R_VECT_MASK_CLR__dma6__##f5##__VAL(R_VECT_MASK_CLR_, dma6_, v5) << R_VECT_MASK_CLR__dma6__BITNR) | \ - (R_VECT_MASK_CLR__dma5__##f6##__VAL(R_VECT_MASK_CLR_, dma5_, v6) << R_VECT_MASK_CLR__dma5__BITNR) | \ - (R_VECT_MASK_CLR__dma4__##f7##__VAL(R_VECT_MASK_CLR_, dma4_, v7) << R_VECT_MASK_CLR__dma4__BITNR) | \ - (R_VECT_MASK_CLR__dma3__##f8##__VAL(R_VECT_MASK_CLR_, dma3_, v8) << R_VECT_MASK_CLR__dma3__BITNR) | \ - (R_VECT_MASK_CLR__dma2__##f9##__VAL(R_VECT_MASK_CLR_, dma2_, v9) << R_VECT_MASK_CLR__dma2__BITNR) | \ - (R_VECT_MASK_CLR__dma1__##f10##__VAL(R_VECT_MASK_CLR_, dma1_, v10) << R_VECT_MASK_CLR__dma1__BITNR) | \ - (R_VECT_MASK_CLR__dma0__##f11##__VAL(R_VECT_MASK_CLR_, dma0_, v11) << R_VECT_MASK_CLR__dma0__BITNR) | \ - (R_VECT_MASK_CLR__ext_dma1__##f12##__VAL(R_VECT_MASK_CLR_, ext_dma1_, v12) << R_VECT_MASK_CLR__ext_dma1__BITNR) | \ - (R_VECT_MASK_CLR__ext_dma0__##f13##__VAL(R_VECT_MASK_CLR_, ext_dma0_, v13) << R_VECT_MASK_CLR__ext_dma0__BITNR) | \ - (R_VECT_MASK_CLR__pa__##f14##__VAL(R_VECT_MASK_CLR_, pa_, v14) << R_VECT_MASK_CLR__pa__BITNR) | \ - (R_VECT_MASK_CLR__irq_intnr__##f15##__VAL(R_VECT_MASK_CLR_, irq_intnr_, v15) << R_VECT_MASK_CLR__irq_intnr__BITNR) | \ - (R_VECT_MASK_CLR__sw__##f16##__VAL(R_VECT_MASK_CLR_, sw_, v16) << R_VECT_MASK_CLR__sw__BITNR) | \ - (R_VECT_MASK_CLR__serial__##f17##__VAL(R_VECT_MASK_CLR_, serial_, v17) << R_VECT_MASK_CLR__serial__BITNR) | \ - (R_VECT_MASK_CLR__snmp__##f18##__VAL(R_VECT_MASK_CLR_, snmp_, v18) << R_VECT_MASK_CLR__snmp__BITNR) | \ - (R_VECT_MASK_CLR__network__##f19##__VAL(R_VECT_MASK_CLR_, network_, v19) << R_VECT_MASK_CLR__network__BITNR) | \ - (R_VECT_MASK_CLR__scsi1__##f20##__VAL(R_VECT_MASK_CLR_, scsi1_, v20) << R_VECT_MASK_CLR__scsi1__BITNR) | \ - (R_VECT_MASK_CLR__scsi0__##f21##__VAL(R_VECT_MASK_CLR_, scsi0_, v21) << R_VECT_MASK_CLR__scsi0__BITNR) | \ - (R_VECT_MASK_CLR__timer1__##f22##__VAL(R_VECT_MASK_CLR_, timer1_, v22) << R_VECT_MASK_CLR__timer1__BITNR) | \ - (R_VECT_MASK_CLR__timer0__##f23##__VAL(R_VECT_MASK_CLR_, timer0_, v23) << R_VECT_MASK_CLR__timer0__BITNR) | \ - (R_VECT_MASK_CLR__nmi__##f24##__VAL(R_VECT_MASK_CLR_, nmi_, v24) << R_VECT_MASK_CLR__nmi__BITNR) | \ - (R_VECT_MASK_CLR__some__##f25##__VAL(R_VECT_MASK_CLR_, some_, v25) << R_VECT_MASK_CLR__some__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_VECT_MASK_CLR_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_VECT_MASK_CLR. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_VECT_MASK_CLR_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16,f17_,v17,f18_,v18,f19_,v19,f20_,v20,f21_,v21,f22_,v22,f23_,v23,f24_,v24,f25_,v25) ( \ - (R_VECT_MASK_CLR__usb__##f1_##_VAL(R_VECT_MASK_CLR_, usb_, v1) << R_VECT_MASK_CLR__usb__BITNR) | \ - (R_VECT_MASK_CLR__dma9__##f2_##_VAL(R_VECT_MASK_CLR_, dma9_, v2) << R_VECT_MASK_CLR__dma9__BITNR) | \ - (R_VECT_MASK_CLR__dma8__##f3_##_VAL(R_VECT_MASK_CLR_, dma8_, v3) << R_VECT_MASK_CLR__dma8__BITNR) | \ - (R_VECT_MASK_CLR__dma7__##f4_##_VAL(R_VECT_MASK_CLR_, dma7_, v4) << R_VECT_MASK_CLR__dma7__BITNR) | \ - (R_VECT_MASK_CLR__dma6__##f5_##_VAL(R_VECT_MASK_CLR_, dma6_, v5) << R_VECT_MASK_CLR__dma6__BITNR) | \ - (R_VECT_MASK_CLR__dma5__##f6_##_VAL(R_VECT_MASK_CLR_, dma5_, v6) << R_VECT_MASK_CLR__dma5__BITNR) | \ - (R_VECT_MASK_CLR__dma4__##f7_##_VAL(R_VECT_MASK_CLR_, dma4_, v7) << R_VECT_MASK_CLR__dma4__BITNR) | \ - (R_VECT_MASK_CLR__dma3__##f8_##_VAL(R_VECT_MASK_CLR_, dma3_, v8) << R_VECT_MASK_CLR__dma3__BITNR) | \ - (R_VECT_MASK_CLR__dma2__##f9_##_VAL(R_VECT_MASK_CLR_, dma2_, v9) << R_VECT_MASK_CLR__dma2__BITNR) | \ - (R_VECT_MASK_CLR__dma1__##f10_##_VAL(R_VECT_MASK_CLR_, dma1_, v10) << R_VECT_MASK_CLR__dma1__BITNR) | \ - (R_VECT_MASK_CLR__dma0__##f11_##_VAL(R_VECT_MASK_CLR_, dma0_, v11) << R_VECT_MASK_CLR__dma0__BITNR) | \ - (R_VECT_MASK_CLR__ext_dma1__##f12_##_VAL(R_VECT_MASK_CLR_, ext_dma1_, v12) << R_VECT_MASK_CLR__ext_dma1__BITNR) | \ - (R_VECT_MASK_CLR__ext_dma0__##f13_##_VAL(R_VECT_MASK_CLR_, ext_dma0_, v13) << R_VECT_MASK_CLR__ext_dma0__BITNR) | \ - (R_VECT_MASK_CLR__pa__##f14_##_VAL(R_VECT_MASK_CLR_, pa_, v14) << R_VECT_MASK_CLR__pa__BITNR) | \ - (R_VECT_MASK_CLR__irq_intnr__##f15_##_VAL(R_VECT_MASK_CLR_, irq_intnr_, v15) << R_VECT_MASK_CLR__irq_intnr__BITNR) | \ - (R_VECT_MASK_CLR__sw__##f16_##_VAL(R_VECT_MASK_CLR_, sw_, v16) << R_VECT_MASK_CLR__sw__BITNR) | \ - (R_VECT_MASK_CLR__serial__##f17_##_VAL(R_VECT_MASK_CLR_, serial_, v17) << R_VECT_MASK_CLR__serial__BITNR) | \ - (R_VECT_MASK_CLR__snmp__##f18_##_VAL(R_VECT_MASK_CLR_, snmp_, v18) << R_VECT_MASK_CLR__snmp__BITNR) | \ - (R_VECT_MASK_CLR__network__##f19_##_VAL(R_VECT_MASK_CLR_, network_, v19) << R_VECT_MASK_CLR__network__BITNR) | \ - (R_VECT_MASK_CLR__scsi1__##f20_##_VAL(R_VECT_MASK_CLR_, scsi1_, v20) << R_VECT_MASK_CLR__scsi1__BITNR) | \ - (R_VECT_MASK_CLR__scsi0__##f21_##_VAL(R_VECT_MASK_CLR_, scsi0_, v21) << R_VECT_MASK_CLR__scsi0__BITNR) | \ - (R_VECT_MASK_CLR__timer1__##f22_##_VAL(R_VECT_MASK_CLR_, timer1_, v22) << R_VECT_MASK_CLR__timer1__BITNR) | \ - (R_VECT_MASK_CLR__timer0__##f23_##_VAL(R_VECT_MASK_CLR_, timer0_, v23) << R_VECT_MASK_CLR__timer0__BITNR) | \ - (R_VECT_MASK_CLR__nmi__##f24_##_VAL(R_VECT_MASK_CLR_, nmi_, v24) << R_VECT_MASK_CLR__nmi__BITNR) | \ - (R_VECT_MASK_CLR__some__##f25_##_VAL(R_VECT_MASK_CLR_, some_, v25) << R_VECT_MASK_CLR__some__BITNR) \ -) - -#endif - -/* - * R_VECT_MASK_RD - * - type: RO - * - addr: 0xb00000d8 - * - group: Interrupt mask and status registers - */ - -#if USE_GROUP__Interrupt_mask_and_status_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_VECT_MASK_RD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_VECT_MASK_RD(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25) ( \ - (R_VECT_MASK_RD__usb__##f1##__MASK & REG__##v1) | \ - (R_VECT_MASK_RD__dma9__##f2##__MASK & REG__##v2) | \ - (R_VECT_MASK_RD__dma8__##f3##__MASK & REG__##v3) | \ - (R_VECT_MASK_RD__dma7__##f4##__MASK & REG__##v4) | \ - (R_VECT_MASK_RD__dma6__##f5##__MASK & REG__##v5) | \ - (R_VECT_MASK_RD__dma5__##f6##__MASK & REG__##v6) | \ - (R_VECT_MASK_RD__dma4__##f7##__MASK & REG__##v7) | \ - (R_VECT_MASK_RD__dma3__##f8##__MASK & REG__##v8) | \ - (R_VECT_MASK_RD__dma2__##f9##__MASK & REG__##v9) | \ - (R_VECT_MASK_RD__dma1__##f10##__MASK & REG__##v10) | \ - (R_VECT_MASK_RD__dma0__##f11##__MASK & REG__##v11) | \ - (R_VECT_MASK_RD__ext_dma1__##f12##__MASK & REG__##v12) | \ - (R_VECT_MASK_RD__ext_dma0__##f13##__MASK & REG__##v13) | \ - (R_VECT_MASK_RD__pa__##f14##__MASK & REG__##v14) | \ - (R_VECT_MASK_RD__irq_intnr__##f15##__MASK & REG__##v15) | \ - (R_VECT_MASK_RD__sw__##f16##__MASK & REG__##v16) | \ - (R_VECT_MASK_RD__serial__##f17##__MASK & REG__##v17) | \ - (R_VECT_MASK_RD__snmp__##f18##__MASK & REG__##v18) | \ - (R_VECT_MASK_RD__network__##f19##__MASK & REG__##v19) | \ - (R_VECT_MASK_RD__scsi1__##f20##__MASK & REG__##v20) | \ - (R_VECT_MASK_RD__scsi0__##f21##__MASK & REG__##v21) | \ - (R_VECT_MASK_RD__timer1__##f22##__MASK & REG__##v22) | \ - (R_VECT_MASK_RD__timer0__##f23##__MASK & REG__##v23) | \ - (R_VECT_MASK_RD__nmi__##f24##__MASK & REG__##v24) | \ - (R_VECT_MASK_RD__some__##f25##__MASK & REG__##v25) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_VECT_MASK_RD -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_VECT_MASK_RD. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_VECT_MASK_RD(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25) ( \ - (R_VECT_MASK_RD__usb__##f1##__VAL(R_VECT_MASK_RD_, usb_, v1) << R_VECT_MASK_RD__usb__BITNR) | \ - (R_VECT_MASK_RD__dma9__##f2##__VAL(R_VECT_MASK_RD_, dma9_, v2) << R_VECT_MASK_RD__dma9__BITNR) | \ - (R_VECT_MASK_RD__dma8__##f3##__VAL(R_VECT_MASK_RD_, dma8_, v3) << R_VECT_MASK_RD__dma8__BITNR) | \ - (R_VECT_MASK_RD__dma7__##f4##__VAL(R_VECT_MASK_RD_, dma7_, v4) << R_VECT_MASK_RD__dma7__BITNR) | \ - (R_VECT_MASK_RD__dma6__##f5##__VAL(R_VECT_MASK_RD_, dma6_, v5) << R_VECT_MASK_RD__dma6__BITNR) | \ - (R_VECT_MASK_RD__dma5__##f6##__VAL(R_VECT_MASK_RD_, dma5_, v6) << R_VECT_MASK_RD__dma5__BITNR) | \ - (R_VECT_MASK_RD__dma4__##f7##__VAL(R_VECT_MASK_RD_, dma4_, v7) << R_VECT_MASK_RD__dma4__BITNR) | \ - (R_VECT_MASK_RD__dma3__##f8##__VAL(R_VECT_MASK_RD_, dma3_, v8) << R_VECT_MASK_RD__dma3__BITNR) | \ - (R_VECT_MASK_RD__dma2__##f9##__VAL(R_VECT_MASK_RD_, dma2_, v9) << R_VECT_MASK_RD__dma2__BITNR) | \ - (R_VECT_MASK_RD__dma1__##f10##__VAL(R_VECT_MASK_RD_, dma1_, v10) << R_VECT_MASK_RD__dma1__BITNR) | \ - (R_VECT_MASK_RD__dma0__##f11##__VAL(R_VECT_MASK_RD_, dma0_, v11) << R_VECT_MASK_RD__dma0__BITNR) | \ - (R_VECT_MASK_RD__ext_dma1__##f12##__VAL(R_VECT_MASK_RD_, ext_dma1_, v12) << R_VECT_MASK_RD__ext_dma1__BITNR) | \ - (R_VECT_MASK_RD__ext_dma0__##f13##__VAL(R_VECT_MASK_RD_, ext_dma0_, v13) << R_VECT_MASK_RD__ext_dma0__BITNR) | \ - (R_VECT_MASK_RD__pa__##f14##__VAL(R_VECT_MASK_RD_, pa_, v14) << R_VECT_MASK_RD__pa__BITNR) | \ - (R_VECT_MASK_RD__irq_intnr__##f15##__VAL(R_VECT_MASK_RD_, irq_intnr_, v15) << R_VECT_MASK_RD__irq_intnr__BITNR) | \ - (R_VECT_MASK_RD__sw__##f16##__VAL(R_VECT_MASK_RD_, sw_, v16) << R_VECT_MASK_RD__sw__BITNR) | \ - (R_VECT_MASK_RD__serial__##f17##__VAL(R_VECT_MASK_RD_, serial_, v17) << R_VECT_MASK_RD__serial__BITNR) | \ - (R_VECT_MASK_RD__snmp__##f18##__VAL(R_VECT_MASK_RD_, snmp_, v18) << R_VECT_MASK_RD__snmp__BITNR) | \ - (R_VECT_MASK_RD__network__##f19##__VAL(R_VECT_MASK_RD_, network_, v19) << R_VECT_MASK_RD__network__BITNR) | \ - (R_VECT_MASK_RD__scsi1__##f20##__VAL(R_VECT_MASK_RD_, scsi1_, v20) << R_VECT_MASK_RD__scsi1__BITNR) | \ - (R_VECT_MASK_RD__scsi0__##f21##__VAL(R_VECT_MASK_RD_, scsi0_, v21) << R_VECT_MASK_RD__scsi0__BITNR) | \ - (R_VECT_MASK_RD__timer1__##f22##__VAL(R_VECT_MASK_RD_, timer1_, v22) << R_VECT_MASK_RD__timer1__BITNR) | \ - (R_VECT_MASK_RD__timer0__##f23##__VAL(R_VECT_MASK_RD_, timer0_, v23) << R_VECT_MASK_RD__timer0__BITNR) | \ - (R_VECT_MASK_RD__nmi__##f24##__VAL(R_VECT_MASK_RD_, nmi_, v24) << R_VECT_MASK_RD__nmi__BITNR) | \ - (R_VECT_MASK_RD__some__##f25##__VAL(R_VECT_MASK_RD_, some_, v25) << R_VECT_MASK_RD__some__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_VECT_MASK_RD_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_VECT_MASK_RD. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_VECT_MASK_RD_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16,f17_,v17,f18_,v18,f19_,v19,f20_,v20,f21_,v21,f22_,v22,f23_,v23,f24_,v24,f25_,v25) ( \ - (R_VECT_MASK_RD__usb__##f1_##_VAL(R_VECT_MASK_RD_, usb_, v1) << R_VECT_MASK_RD__usb__BITNR) | \ - (R_VECT_MASK_RD__dma9__##f2_##_VAL(R_VECT_MASK_RD_, dma9_, v2) << R_VECT_MASK_RD__dma9__BITNR) | \ - (R_VECT_MASK_RD__dma8__##f3_##_VAL(R_VECT_MASK_RD_, dma8_, v3) << R_VECT_MASK_RD__dma8__BITNR) | \ - (R_VECT_MASK_RD__dma7__##f4_##_VAL(R_VECT_MASK_RD_, dma7_, v4) << R_VECT_MASK_RD__dma7__BITNR) | \ - (R_VECT_MASK_RD__dma6__##f5_##_VAL(R_VECT_MASK_RD_, dma6_, v5) << R_VECT_MASK_RD__dma6__BITNR) | \ - (R_VECT_MASK_RD__dma5__##f6_##_VAL(R_VECT_MASK_RD_, dma5_, v6) << R_VECT_MASK_RD__dma5__BITNR) | \ - (R_VECT_MASK_RD__dma4__##f7_##_VAL(R_VECT_MASK_RD_, dma4_, v7) << R_VECT_MASK_RD__dma4__BITNR) | \ - (R_VECT_MASK_RD__dma3__##f8_##_VAL(R_VECT_MASK_RD_, dma3_, v8) << R_VECT_MASK_RD__dma3__BITNR) | \ - (R_VECT_MASK_RD__dma2__##f9_##_VAL(R_VECT_MASK_RD_, dma2_, v9) << R_VECT_MASK_RD__dma2__BITNR) | \ - (R_VECT_MASK_RD__dma1__##f10_##_VAL(R_VECT_MASK_RD_, dma1_, v10) << R_VECT_MASK_RD__dma1__BITNR) | \ - (R_VECT_MASK_RD__dma0__##f11_##_VAL(R_VECT_MASK_RD_, dma0_, v11) << R_VECT_MASK_RD__dma0__BITNR) | \ - (R_VECT_MASK_RD__ext_dma1__##f12_##_VAL(R_VECT_MASK_RD_, ext_dma1_, v12) << R_VECT_MASK_RD__ext_dma1__BITNR) | \ - (R_VECT_MASK_RD__ext_dma0__##f13_##_VAL(R_VECT_MASK_RD_, ext_dma0_, v13) << R_VECT_MASK_RD__ext_dma0__BITNR) | \ - (R_VECT_MASK_RD__pa__##f14_##_VAL(R_VECT_MASK_RD_, pa_, v14) << R_VECT_MASK_RD__pa__BITNR) | \ - (R_VECT_MASK_RD__irq_intnr__##f15_##_VAL(R_VECT_MASK_RD_, irq_intnr_, v15) << R_VECT_MASK_RD__irq_intnr__BITNR) | \ - (R_VECT_MASK_RD__sw__##f16_##_VAL(R_VECT_MASK_RD_, sw_, v16) << R_VECT_MASK_RD__sw__BITNR) | \ - (R_VECT_MASK_RD__serial__##f17_##_VAL(R_VECT_MASK_RD_, serial_, v17) << R_VECT_MASK_RD__serial__BITNR) | \ - (R_VECT_MASK_RD__snmp__##f18_##_VAL(R_VECT_MASK_RD_, snmp_, v18) << R_VECT_MASK_RD__snmp__BITNR) | \ - (R_VECT_MASK_RD__network__##f19_##_VAL(R_VECT_MASK_RD_, network_, v19) << R_VECT_MASK_RD__network__BITNR) | \ - (R_VECT_MASK_RD__scsi1__##f20_##_VAL(R_VECT_MASK_RD_, scsi1_, v20) << R_VECT_MASK_RD__scsi1__BITNR) | \ - (R_VECT_MASK_RD__scsi0__##f21_##_VAL(R_VECT_MASK_RD_, scsi0_, v21) << R_VECT_MASK_RD__scsi0__BITNR) | \ - (R_VECT_MASK_RD__timer1__##f22_##_VAL(R_VECT_MASK_RD_, timer1_, v22) << R_VECT_MASK_RD__timer1__BITNR) | \ - (R_VECT_MASK_RD__timer0__##f23_##_VAL(R_VECT_MASK_RD_, timer0_, v23) << R_VECT_MASK_RD__timer0__BITNR) | \ - (R_VECT_MASK_RD__nmi__##f24_##_VAL(R_VECT_MASK_RD_, nmi_, v24) << R_VECT_MASK_RD__nmi__BITNR) | \ - (R_VECT_MASK_RD__some__##f25_##_VAL(R_VECT_MASK_RD_, some_, v25) << R_VECT_MASK_RD__some__BITNR) \ -) - -#endif - -/* - * R_VECT_MASK_SET - * - type: WO - * - addr: 0xb00000dc - * - group: Interrupt mask and status registers - */ - -#if USE_GROUP__Interrupt_mask_and_status_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_VECT_MASK_SET -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_VECT_MASK_SET. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_VECT_MASK_SET. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_VECT_MASK_SET(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25) ( \ - *R_VECT_MASK_SET__SADDR = ( \ - REG_INITIATED(R_VECT_MASK_SET_) \ - REG_VAL__R_VECT_MASK_SET_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20,f21##_,v21,f22##_,v22,f23##_,v23,f24##_,v24,f25##_,v25) \ - ), \ - R_VECT_MASK_SET__WRITE(R_VECT_MASK_SET__ADDR, *R_VECT_MASK_SET__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_VECT_MASK_SET__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_VECT_MASK_SET. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_VECT_MASK_SET. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_VECT_MASK_SET__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25) ( \ - *R_VECT_MASK_SET__SADDR = ( \ - REG_INITIATED(R_VECT_MASK_SET_) \ - REG_VAL__R_VECT_MASK_SET_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20,f21##_,v21,f22##_,v22,f23##_,v23,f24##_,v24,f25##_,v25) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_VECT_MASK_SET -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_VECT_MASK_SET(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25) ( \ - (R_VECT_MASK_SET__usb__##f1##__MASK & REG__##v1) | \ - (R_VECT_MASK_SET__dma9__##f2##__MASK & REG__##v2) | \ - (R_VECT_MASK_SET__dma8__##f3##__MASK & REG__##v3) | \ - (R_VECT_MASK_SET__dma7__##f4##__MASK & REG__##v4) | \ - (R_VECT_MASK_SET__dma6__##f5##__MASK & REG__##v5) | \ - (R_VECT_MASK_SET__dma5__##f6##__MASK & REG__##v6) | \ - (R_VECT_MASK_SET__dma4__##f7##__MASK & REG__##v7) | \ - (R_VECT_MASK_SET__dma3__##f8##__MASK & REG__##v8) | \ - (R_VECT_MASK_SET__dma2__##f9##__MASK & REG__##v9) | \ - (R_VECT_MASK_SET__dma1__##f10##__MASK & REG__##v10) | \ - (R_VECT_MASK_SET__dma0__##f11##__MASK & REG__##v11) | \ - (R_VECT_MASK_SET__ext_dma1__##f12##__MASK & REG__##v12) | \ - (R_VECT_MASK_SET__ext_dma0__##f13##__MASK & REG__##v13) | \ - (R_VECT_MASK_SET__pa__##f14##__MASK & REG__##v14) | \ - (R_VECT_MASK_SET__irq_intnr__##f15##__MASK & REG__##v15) | \ - (R_VECT_MASK_SET__sw__##f16##__MASK & REG__##v16) | \ - (R_VECT_MASK_SET__serial__##f17##__MASK & REG__##v17) | \ - (R_VECT_MASK_SET__snmp__##f18##__MASK & REG__##v18) | \ - (R_VECT_MASK_SET__network__##f19##__MASK & REG__##v19) | \ - (R_VECT_MASK_SET__scsi1__##f20##__MASK & REG__##v20) | \ - (R_VECT_MASK_SET__scsi0__##f21##__MASK & REG__##v21) | \ - (R_VECT_MASK_SET__timer1__##f22##__MASK & REG__##v22) | \ - (R_VECT_MASK_SET__timer0__##f23##__MASK & REG__##v23) | \ - (R_VECT_MASK_SET__nmi__##f24##__MASK & REG__##v24) | \ - (R_VECT_MASK_SET__some__##f25##__MASK & REG__##v25) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_VECT_MASK_SET -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_VECT_MASK_SET. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_VECT_MASK_SET(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25) ( \ - (R_VECT_MASK_SET__usb__##f1##__VAL(R_VECT_MASK_SET_, usb_, v1) << R_VECT_MASK_SET__usb__BITNR) | \ - (R_VECT_MASK_SET__dma9__##f2##__VAL(R_VECT_MASK_SET_, dma9_, v2) << R_VECT_MASK_SET__dma9__BITNR) | \ - (R_VECT_MASK_SET__dma8__##f3##__VAL(R_VECT_MASK_SET_, dma8_, v3) << R_VECT_MASK_SET__dma8__BITNR) | \ - (R_VECT_MASK_SET__dma7__##f4##__VAL(R_VECT_MASK_SET_, dma7_, v4) << R_VECT_MASK_SET__dma7__BITNR) | \ - (R_VECT_MASK_SET__dma6__##f5##__VAL(R_VECT_MASK_SET_, dma6_, v5) << R_VECT_MASK_SET__dma6__BITNR) | \ - (R_VECT_MASK_SET__dma5__##f6##__VAL(R_VECT_MASK_SET_, dma5_, v6) << R_VECT_MASK_SET__dma5__BITNR) | \ - (R_VECT_MASK_SET__dma4__##f7##__VAL(R_VECT_MASK_SET_, dma4_, v7) << R_VECT_MASK_SET__dma4__BITNR) | \ - (R_VECT_MASK_SET__dma3__##f8##__VAL(R_VECT_MASK_SET_, dma3_, v8) << R_VECT_MASK_SET__dma3__BITNR) | \ - (R_VECT_MASK_SET__dma2__##f9##__VAL(R_VECT_MASK_SET_, dma2_, v9) << R_VECT_MASK_SET__dma2__BITNR) | \ - (R_VECT_MASK_SET__dma1__##f10##__VAL(R_VECT_MASK_SET_, dma1_, v10) << R_VECT_MASK_SET__dma1__BITNR) | \ - (R_VECT_MASK_SET__dma0__##f11##__VAL(R_VECT_MASK_SET_, dma0_, v11) << R_VECT_MASK_SET__dma0__BITNR) | \ - (R_VECT_MASK_SET__ext_dma1__##f12##__VAL(R_VECT_MASK_SET_, ext_dma1_, v12) << R_VECT_MASK_SET__ext_dma1__BITNR) | \ - (R_VECT_MASK_SET__ext_dma0__##f13##__VAL(R_VECT_MASK_SET_, ext_dma0_, v13) << R_VECT_MASK_SET__ext_dma0__BITNR) | \ - (R_VECT_MASK_SET__pa__##f14##__VAL(R_VECT_MASK_SET_, pa_, v14) << R_VECT_MASK_SET__pa__BITNR) | \ - (R_VECT_MASK_SET__irq_intnr__##f15##__VAL(R_VECT_MASK_SET_, irq_intnr_, v15) << R_VECT_MASK_SET__irq_intnr__BITNR) | \ - (R_VECT_MASK_SET__sw__##f16##__VAL(R_VECT_MASK_SET_, sw_, v16) << R_VECT_MASK_SET__sw__BITNR) | \ - (R_VECT_MASK_SET__serial__##f17##__VAL(R_VECT_MASK_SET_, serial_, v17) << R_VECT_MASK_SET__serial__BITNR) | \ - (R_VECT_MASK_SET__snmp__##f18##__VAL(R_VECT_MASK_SET_, snmp_, v18) << R_VECT_MASK_SET__snmp__BITNR) | \ - (R_VECT_MASK_SET__network__##f19##__VAL(R_VECT_MASK_SET_, network_, v19) << R_VECT_MASK_SET__network__BITNR) | \ - (R_VECT_MASK_SET__scsi1__##f20##__VAL(R_VECT_MASK_SET_, scsi1_, v20) << R_VECT_MASK_SET__scsi1__BITNR) | \ - (R_VECT_MASK_SET__scsi0__##f21##__VAL(R_VECT_MASK_SET_, scsi0_, v21) << R_VECT_MASK_SET__scsi0__BITNR) | \ - (R_VECT_MASK_SET__timer1__##f22##__VAL(R_VECT_MASK_SET_, timer1_, v22) << R_VECT_MASK_SET__timer1__BITNR) | \ - (R_VECT_MASK_SET__timer0__##f23##__VAL(R_VECT_MASK_SET_, timer0_, v23) << R_VECT_MASK_SET__timer0__BITNR) | \ - (R_VECT_MASK_SET__nmi__##f24##__VAL(R_VECT_MASK_SET_, nmi_, v24) << R_VECT_MASK_SET__nmi__BITNR) | \ - (R_VECT_MASK_SET__some__##f25##__VAL(R_VECT_MASK_SET_, some_, v25) << R_VECT_MASK_SET__some__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_VECT_MASK_SET_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_VECT_MASK_SET. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_VECT_MASK_SET_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16,f17_,v17,f18_,v18,f19_,v19,f20_,v20,f21_,v21,f22_,v22,f23_,v23,f24_,v24,f25_,v25) ( \ - (R_VECT_MASK_SET__usb__##f1_##_VAL(R_VECT_MASK_SET_, usb_, v1) << R_VECT_MASK_SET__usb__BITNR) | \ - (R_VECT_MASK_SET__dma9__##f2_##_VAL(R_VECT_MASK_SET_, dma9_, v2) << R_VECT_MASK_SET__dma9__BITNR) | \ - (R_VECT_MASK_SET__dma8__##f3_##_VAL(R_VECT_MASK_SET_, dma8_, v3) << R_VECT_MASK_SET__dma8__BITNR) | \ - (R_VECT_MASK_SET__dma7__##f4_##_VAL(R_VECT_MASK_SET_, dma7_, v4) << R_VECT_MASK_SET__dma7__BITNR) | \ - (R_VECT_MASK_SET__dma6__##f5_##_VAL(R_VECT_MASK_SET_, dma6_, v5) << R_VECT_MASK_SET__dma6__BITNR) | \ - (R_VECT_MASK_SET__dma5__##f6_##_VAL(R_VECT_MASK_SET_, dma5_, v6) << R_VECT_MASK_SET__dma5__BITNR) | \ - (R_VECT_MASK_SET__dma4__##f7_##_VAL(R_VECT_MASK_SET_, dma4_, v7) << R_VECT_MASK_SET__dma4__BITNR) | \ - (R_VECT_MASK_SET__dma3__##f8_##_VAL(R_VECT_MASK_SET_, dma3_, v8) << R_VECT_MASK_SET__dma3__BITNR) | \ - (R_VECT_MASK_SET__dma2__##f9_##_VAL(R_VECT_MASK_SET_, dma2_, v9) << R_VECT_MASK_SET__dma2__BITNR) | \ - (R_VECT_MASK_SET__dma1__##f10_##_VAL(R_VECT_MASK_SET_, dma1_, v10) << R_VECT_MASK_SET__dma1__BITNR) | \ - (R_VECT_MASK_SET__dma0__##f11_##_VAL(R_VECT_MASK_SET_, dma0_, v11) << R_VECT_MASK_SET__dma0__BITNR) | \ - (R_VECT_MASK_SET__ext_dma1__##f12_##_VAL(R_VECT_MASK_SET_, ext_dma1_, v12) << R_VECT_MASK_SET__ext_dma1__BITNR) | \ - (R_VECT_MASK_SET__ext_dma0__##f13_##_VAL(R_VECT_MASK_SET_, ext_dma0_, v13) << R_VECT_MASK_SET__ext_dma0__BITNR) | \ - (R_VECT_MASK_SET__pa__##f14_##_VAL(R_VECT_MASK_SET_, pa_, v14) << R_VECT_MASK_SET__pa__BITNR) | \ - (R_VECT_MASK_SET__irq_intnr__##f15_##_VAL(R_VECT_MASK_SET_, irq_intnr_, v15) << R_VECT_MASK_SET__irq_intnr__BITNR) | \ - (R_VECT_MASK_SET__sw__##f16_##_VAL(R_VECT_MASK_SET_, sw_, v16) << R_VECT_MASK_SET__sw__BITNR) | \ - (R_VECT_MASK_SET__serial__##f17_##_VAL(R_VECT_MASK_SET_, serial_, v17) << R_VECT_MASK_SET__serial__BITNR) | \ - (R_VECT_MASK_SET__snmp__##f18_##_VAL(R_VECT_MASK_SET_, snmp_, v18) << R_VECT_MASK_SET__snmp__BITNR) | \ - (R_VECT_MASK_SET__network__##f19_##_VAL(R_VECT_MASK_SET_, network_, v19) << R_VECT_MASK_SET__network__BITNR) | \ - (R_VECT_MASK_SET__scsi1__##f20_##_VAL(R_VECT_MASK_SET_, scsi1_, v20) << R_VECT_MASK_SET__scsi1__BITNR) | \ - (R_VECT_MASK_SET__scsi0__##f21_##_VAL(R_VECT_MASK_SET_, scsi0_, v21) << R_VECT_MASK_SET__scsi0__BITNR) | \ - (R_VECT_MASK_SET__timer1__##f22_##_VAL(R_VECT_MASK_SET_, timer1_, v22) << R_VECT_MASK_SET__timer1__BITNR) | \ - (R_VECT_MASK_SET__timer0__##f23_##_VAL(R_VECT_MASK_SET_, timer0_, v23) << R_VECT_MASK_SET__timer0__BITNR) | \ - (R_VECT_MASK_SET__nmi__##f24_##_VAL(R_VECT_MASK_SET_, nmi_, v24) << R_VECT_MASK_SET__nmi__BITNR) | \ - (R_VECT_MASK_SET__some__##f25_##_VAL(R_VECT_MASK_SET_, some_, v25) << R_VECT_MASK_SET__some__BITNR) \ -) - -#endif - -/* - * R_VECT_READ - * - type: RO - * - addr: 0xb00000dc - * - group: Interrupt mask and status registers - */ - -#if USE_GROUP__Interrupt_mask_and_status_registers - -/* No REG_SET__register-name for read only registers. */ - -/* No REG_SET__register-name__SHADOW for read only and read write registers. */ - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_VECT_READ -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_VECT_READ(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25) ( \ - (R_VECT_READ__usb__##f1##__MASK & REG__##v1) | \ - (R_VECT_READ__dma9__##f2##__MASK & REG__##v2) | \ - (R_VECT_READ__dma8__##f3##__MASK & REG__##v3) | \ - (R_VECT_READ__dma7__##f4##__MASK & REG__##v4) | \ - (R_VECT_READ__dma6__##f5##__MASK & REG__##v5) | \ - (R_VECT_READ__dma5__##f6##__MASK & REG__##v6) | \ - (R_VECT_READ__dma4__##f7##__MASK & REG__##v7) | \ - (R_VECT_READ__dma3__##f8##__MASK & REG__##v8) | \ - (R_VECT_READ__dma2__##f9##__MASK & REG__##v9) | \ - (R_VECT_READ__dma1__##f10##__MASK & REG__##v10) | \ - (R_VECT_READ__dma0__##f11##__MASK & REG__##v11) | \ - (R_VECT_READ__ext_dma1__##f12##__MASK & REG__##v12) | \ - (R_VECT_READ__ext_dma0__##f13##__MASK & REG__##v13) | \ - (R_VECT_READ__pa__##f14##__MASK & REG__##v14) | \ - (R_VECT_READ__irq_intnr__##f15##__MASK & REG__##v15) | \ - (R_VECT_READ__sw__##f16##__MASK & REG__##v16) | \ - (R_VECT_READ__serial__##f17##__MASK & REG__##v17) | \ - (R_VECT_READ__snmp__##f18##__MASK & REG__##v18) | \ - (R_VECT_READ__network__##f19##__MASK & REG__##v19) | \ - (R_VECT_READ__scsi1__##f20##__MASK & REG__##v20) | \ - (R_VECT_READ__scsi0__##f21##__MASK & REG__##v21) | \ - (R_VECT_READ__timer1__##f22##__MASK & REG__##v22) | \ - (R_VECT_READ__timer0__##f23##__MASK & REG__##v23) | \ - (R_VECT_READ__nmi__##f24##__MASK & REG__##v24) | \ - (R_VECT_READ__some__##f25##__MASK & REG__##v25) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_VECT_READ -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_VECT_READ. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_VECT_READ(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25) ( \ - (R_VECT_READ__usb__##f1##__VAL(R_VECT_READ_, usb_, v1) << R_VECT_READ__usb__BITNR) | \ - (R_VECT_READ__dma9__##f2##__VAL(R_VECT_READ_, dma9_, v2) << R_VECT_READ__dma9__BITNR) | \ - (R_VECT_READ__dma8__##f3##__VAL(R_VECT_READ_, dma8_, v3) << R_VECT_READ__dma8__BITNR) | \ - (R_VECT_READ__dma7__##f4##__VAL(R_VECT_READ_, dma7_, v4) << R_VECT_READ__dma7__BITNR) | \ - (R_VECT_READ__dma6__##f5##__VAL(R_VECT_READ_, dma6_, v5) << R_VECT_READ__dma6__BITNR) | \ - (R_VECT_READ__dma5__##f6##__VAL(R_VECT_READ_, dma5_, v6) << R_VECT_READ__dma5__BITNR) | \ - (R_VECT_READ__dma4__##f7##__VAL(R_VECT_READ_, dma4_, v7) << R_VECT_READ__dma4__BITNR) | \ - (R_VECT_READ__dma3__##f8##__VAL(R_VECT_READ_, dma3_, v8) << R_VECT_READ__dma3__BITNR) | \ - (R_VECT_READ__dma2__##f9##__VAL(R_VECT_READ_, dma2_, v9) << R_VECT_READ__dma2__BITNR) | \ - (R_VECT_READ__dma1__##f10##__VAL(R_VECT_READ_, dma1_, v10) << R_VECT_READ__dma1__BITNR) | \ - (R_VECT_READ__dma0__##f11##__VAL(R_VECT_READ_, dma0_, v11) << R_VECT_READ__dma0__BITNR) | \ - (R_VECT_READ__ext_dma1__##f12##__VAL(R_VECT_READ_, ext_dma1_, v12) << R_VECT_READ__ext_dma1__BITNR) | \ - (R_VECT_READ__ext_dma0__##f13##__VAL(R_VECT_READ_, ext_dma0_, v13) << R_VECT_READ__ext_dma0__BITNR) | \ - (R_VECT_READ__pa__##f14##__VAL(R_VECT_READ_, pa_, v14) << R_VECT_READ__pa__BITNR) | \ - (R_VECT_READ__irq_intnr__##f15##__VAL(R_VECT_READ_, irq_intnr_, v15) << R_VECT_READ__irq_intnr__BITNR) | \ - (R_VECT_READ__sw__##f16##__VAL(R_VECT_READ_, sw_, v16) << R_VECT_READ__sw__BITNR) | \ - (R_VECT_READ__serial__##f17##__VAL(R_VECT_READ_, serial_, v17) << R_VECT_READ__serial__BITNR) | \ - (R_VECT_READ__snmp__##f18##__VAL(R_VECT_READ_, snmp_, v18) << R_VECT_READ__snmp__BITNR) | \ - (R_VECT_READ__network__##f19##__VAL(R_VECT_READ_, network_, v19) << R_VECT_READ__network__BITNR) | \ - (R_VECT_READ__scsi1__##f20##__VAL(R_VECT_READ_, scsi1_, v20) << R_VECT_READ__scsi1__BITNR) | \ - (R_VECT_READ__scsi0__##f21##__VAL(R_VECT_READ_, scsi0_, v21) << R_VECT_READ__scsi0__BITNR) | \ - (R_VECT_READ__timer1__##f22##__VAL(R_VECT_READ_, timer1_, v22) << R_VECT_READ__timer1__BITNR) | \ - (R_VECT_READ__timer0__##f23##__VAL(R_VECT_READ_, timer0_, v23) << R_VECT_READ__timer0__BITNR) | \ - (R_VECT_READ__nmi__##f24##__VAL(R_VECT_READ_, nmi_, v24) << R_VECT_READ__nmi__BITNR) | \ - (R_VECT_READ__some__##f25##__VAL(R_VECT_READ_, some_, v25) << R_VECT_READ__some__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_VECT_READ_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_VECT_READ. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_VECT_READ_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16,f17_,v17,f18_,v18,f19_,v19,f20_,v20,f21_,v21,f22_,v22,f23_,v23,f24_,v24,f25_,v25) ( \ - (R_VECT_READ__usb__##f1_##_VAL(R_VECT_READ_, usb_, v1) << R_VECT_READ__usb__BITNR) | \ - (R_VECT_READ__dma9__##f2_##_VAL(R_VECT_READ_, dma9_, v2) << R_VECT_READ__dma9__BITNR) | \ - (R_VECT_READ__dma8__##f3_##_VAL(R_VECT_READ_, dma8_, v3) << R_VECT_READ__dma8__BITNR) | \ - (R_VECT_READ__dma7__##f4_##_VAL(R_VECT_READ_, dma7_, v4) << R_VECT_READ__dma7__BITNR) | \ - (R_VECT_READ__dma6__##f5_##_VAL(R_VECT_READ_, dma6_, v5) << R_VECT_READ__dma6__BITNR) | \ - (R_VECT_READ__dma5__##f6_##_VAL(R_VECT_READ_, dma5_, v6) << R_VECT_READ__dma5__BITNR) | \ - (R_VECT_READ__dma4__##f7_##_VAL(R_VECT_READ_, dma4_, v7) << R_VECT_READ__dma4__BITNR) | \ - (R_VECT_READ__dma3__##f8_##_VAL(R_VECT_READ_, dma3_, v8) << R_VECT_READ__dma3__BITNR) | \ - (R_VECT_READ__dma2__##f9_##_VAL(R_VECT_READ_, dma2_, v9) << R_VECT_READ__dma2__BITNR) | \ - (R_VECT_READ__dma1__##f10_##_VAL(R_VECT_READ_, dma1_, v10) << R_VECT_READ__dma1__BITNR) | \ - (R_VECT_READ__dma0__##f11_##_VAL(R_VECT_READ_, dma0_, v11) << R_VECT_READ__dma0__BITNR) | \ - (R_VECT_READ__ext_dma1__##f12_##_VAL(R_VECT_READ_, ext_dma1_, v12) << R_VECT_READ__ext_dma1__BITNR) | \ - (R_VECT_READ__ext_dma0__##f13_##_VAL(R_VECT_READ_, ext_dma0_, v13) << R_VECT_READ__ext_dma0__BITNR) | \ - (R_VECT_READ__pa__##f14_##_VAL(R_VECT_READ_, pa_, v14) << R_VECT_READ__pa__BITNR) | \ - (R_VECT_READ__irq_intnr__##f15_##_VAL(R_VECT_READ_, irq_intnr_, v15) << R_VECT_READ__irq_intnr__BITNR) | \ - (R_VECT_READ__sw__##f16_##_VAL(R_VECT_READ_, sw_, v16) << R_VECT_READ__sw__BITNR) | \ - (R_VECT_READ__serial__##f17_##_VAL(R_VECT_READ_, serial_, v17) << R_VECT_READ__serial__BITNR) | \ - (R_VECT_READ__snmp__##f18_##_VAL(R_VECT_READ_, snmp_, v18) << R_VECT_READ__snmp__BITNR) | \ - (R_VECT_READ__network__##f19_##_VAL(R_VECT_READ_, network_, v19) << R_VECT_READ__network__BITNR) | \ - (R_VECT_READ__scsi1__##f20_##_VAL(R_VECT_READ_, scsi1_, v20) << R_VECT_READ__scsi1__BITNR) | \ - (R_VECT_READ__scsi0__##f21_##_VAL(R_VECT_READ_, scsi0_, v21) << R_VECT_READ__scsi0__BITNR) | \ - (R_VECT_READ__timer1__##f22_##_VAL(R_VECT_READ_, timer1_, v22) << R_VECT_READ__timer1__BITNR) | \ - (R_VECT_READ__timer0__##f23_##_VAL(R_VECT_READ_, timer0_, v23) << R_VECT_READ__timer0__BITNR) | \ - (R_VECT_READ__nmi__##f24_##_VAL(R_VECT_READ_, nmi_, v24) << R_VECT_READ__nmi__BITNR) | \ - (R_VECT_READ__some__##f25_##_VAL(R_VECT_READ_, some_, v25) << R_VECT_READ__some__BITNR) \ -) - -#endif - -/* - * R_WAITSTATES - * - type: WO - * - addr: 0xb0000000 - * - group: Bus interface configuration registers - */ - -#if USE_GROUP__Bus_interface_configuration_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_WAITSTATES -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_WAITSTATES. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_WAITSTATES. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_WAITSTATES(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12) ( \ - *R_WAITSTATES__SADDR = ( \ - REG_INITIATED(R_WAITSTATES_) \ - REG_VAL__R_WAITSTATES_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12) \ - ), \ - R_WAITSTATES__WRITE(R_WAITSTATES__ADDR, *R_WAITSTATES__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_WAITSTATES__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_WAITSTATES. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_WAITSTATES. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_WAITSTATES__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12) ( \ - *R_WAITSTATES__SADDR = ( \ - REG_INITIATED(R_WAITSTATES_) \ - REG_VAL__R_WAITSTATES_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_WAITSTATES -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_WAITSTATES(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12) ( \ - (R_WAITSTATES__pcs4_7_zw__##f1##__MASK & REG__##v1) | \ - (R_WAITSTATES__pcs4_7_ew__##f2##__MASK & REG__##v2) | \ - (R_WAITSTATES__pcs4_7_lw__##f3##__MASK & REG__##v3) | \ - (R_WAITSTATES__pcs0_3_zw__##f4##__MASK & REG__##v4) | \ - (R_WAITSTATES__pcs0_3_ew__##f5##__MASK & REG__##v5) | \ - (R_WAITSTATES__pcs0_3_lw__##f6##__MASK & REG__##v6) | \ - (R_WAITSTATES__sram_zw__##f7##__MASK & REG__##v7) | \ - (R_WAITSTATES__sram_ew__##f8##__MASK & REG__##v8) | \ - (R_WAITSTATES__sram_lw__##f9##__MASK & REG__##v9) | \ - (R_WAITSTATES__flash_zw__##f10##__MASK & REG__##v10) | \ - (R_WAITSTATES__flash_ew__##f11##__MASK & REG__##v11) | \ - (R_WAITSTATES__flash_lw__##f12##__MASK & REG__##v12) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_WAITSTATES -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_WAITSTATES. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_WAITSTATES(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12) ( \ - (R_WAITSTATES__pcs4_7_zw__##f1##__VAL(R_WAITSTATES_, pcs4_7_zw_, v1) << R_WAITSTATES__pcs4_7_zw__BITNR) | \ - (R_WAITSTATES__pcs4_7_ew__##f2##__VAL(R_WAITSTATES_, pcs4_7_ew_, v2) << R_WAITSTATES__pcs4_7_ew__BITNR) | \ - (R_WAITSTATES__pcs4_7_lw__##f3##__VAL(R_WAITSTATES_, pcs4_7_lw_, v3) << R_WAITSTATES__pcs4_7_lw__BITNR) | \ - (R_WAITSTATES__pcs0_3_zw__##f4##__VAL(R_WAITSTATES_, pcs0_3_zw_, v4) << R_WAITSTATES__pcs0_3_zw__BITNR) | \ - (R_WAITSTATES__pcs0_3_ew__##f5##__VAL(R_WAITSTATES_, pcs0_3_ew_, v5) << R_WAITSTATES__pcs0_3_ew__BITNR) | \ - (R_WAITSTATES__pcs0_3_lw__##f6##__VAL(R_WAITSTATES_, pcs0_3_lw_, v6) << R_WAITSTATES__pcs0_3_lw__BITNR) | \ - (R_WAITSTATES__sram_zw__##f7##__VAL(R_WAITSTATES_, sram_zw_, v7) << R_WAITSTATES__sram_zw__BITNR) | \ - (R_WAITSTATES__sram_ew__##f8##__VAL(R_WAITSTATES_, sram_ew_, v8) << R_WAITSTATES__sram_ew__BITNR) | \ - (R_WAITSTATES__sram_lw__##f9##__VAL(R_WAITSTATES_, sram_lw_, v9) << R_WAITSTATES__sram_lw__BITNR) | \ - (R_WAITSTATES__flash_zw__##f10##__VAL(R_WAITSTATES_, flash_zw_, v10) << R_WAITSTATES__flash_zw__BITNR) | \ - (R_WAITSTATES__flash_ew__##f11##__VAL(R_WAITSTATES_, flash_ew_, v11) << R_WAITSTATES__flash_ew__BITNR) | \ - (R_WAITSTATES__flash_lw__##f12##__VAL(R_WAITSTATES_, flash_lw_, v12) << R_WAITSTATES__flash_lw__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_WAITSTATES_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_WAITSTATES. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_WAITSTATES_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12) ( \ - (R_WAITSTATES__pcs4_7_zw__##f1_##_VAL(R_WAITSTATES_, pcs4_7_zw_, v1) << R_WAITSTATES__pcs4_7_zw__BITNR) | \ - (R_WAITSTATES__pcs4_7_ew__##f2_##_VAL(R_WAITSTATES_, pcs4_7_ew_, v2) << R_WAITSTATES__pcs4_7_ew__BITNR) | \ - (R_WAITSTATES__pcs4_7_lw__##f3_##_VAL(R_WAITSTATES_, pcs4_7_lw_, v3) << R_WAITSTATES__pcs4_7_lw__BITNR) | \ - (R_WAITSTATES__pcs0_3_zw__##f4_##_VAL(R_WAITSTATES_, pcs0_3_zw_, v4) << R_WAITSTATES__pcs0_3_zw__BITNR) | \ - (R_WAITSTATES__pcs0_3_ew__##f5_##_VAL(R_WAITSTATES_, pcs0_3_ew_, v5) << R_WAITSTATES__pcs0_3_ew__BITNR) | \ - (R_WAITSTATES__pcs0_3_lw__##f6_##_VAL(R_WAITSTATES_, pcs0_3_lw_, v6) << R_WAITSTATES__pcs0_3_lw__BITNR) | \ - (R_WAITSTATES__sram_zw__##f7_##_VAL(R_WAITSTATES_, sram_zw_, v7) << R_WAITSTATES__sram_zw__BITNR) | \ - (R_WAITSTATES__sram_ew__##f8_##_VAL(R_WAITSTATES_, sram_ew_, v8) << R_WAITSTATES__sram_ew__BITNR) | \ - (R_WAITSTATES__sram_lw__##f9_##_VAL(R_WAITSTATES_, sram_lw_, v9) << R_WAITSTATES__sram_lw__BITNR) | \ - (R_WAITSTATES__flash_zw__##f10_##_VAL(R_WAITSTATES_, flash_zw_, v10) << R_WAITSTATES__flash_zw__BITNR) | \ - (R_WAITSTATES__flash_ew__##f11_##_VAL(R_WAITSTATES_, flash_ew_, v11) << R_WAITSTATES__flash_ew__BITNR) | \ - (R_WAITSTATES__flash_lw__##f12_##_VAL(R_WAITSTATES_, flash_lw_, v12) << R_WAITSTATES__flash_lw__BITNR) \ -) - -#endif - -/* - * R_WATCHDOG - * - type: WO - * - addr: 0xb0000024 - * - group: Timer registers - */ - -#if USE_GROUP__Timer_registers - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_WATCHDOG -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_WATCHDOG. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in register -*# R_WATCHDOG. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_WATCHDOG(f1,v1,f2,v2) ( \ - *R_WATCHDOG__SADDR = ( \ - REG_INITIATED(R_WATCHDOG_) \ - REG_VAL__R_WATCHDOG_(f1##_,v1,f2##_,v2) \ - ), \ - R_WATCHDOG__WRITE(R_WATCHDOG__ADDR, *R_WATCHDOG__SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET__R_WATCHDOG__SHADOW -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Integer value to write to field N. -*# -*# RETURNS : integer value written to register R_WATCHDOG. -*# -*# SIDE EFFECTS: REG_INITIATED evaluated. -*# -*# DESCRIPTION : Write value of vn parameters to fields fn in the -*# shadow register for R_WATCHDOG. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_SET__R_WATCHDOG__SHADOW(f1,v1,f2,v2) ( \ - *R_WATCHDOG__SADDR = ( \ - REG_INITIATED(R_WATCHDOG_) \ - REG_VAL__R_WATCHDOG_(f1##_,v1,f2##_,v2) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_MASK__R_WATCHDOG -*# -*# PARAMETERS : fn : Name of field N. -*# vn : REG__on, or REG__off -*# -*# RETURNS : Integer value with 1s in all on-fields, -*# and 0s in all off-fields. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on, -*# and 0s in fields with vn == REG_off. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop -*# premature macro evaluation. -*#**********************************************************************/ - -#define REG_MASK__R_WATCHDOG(f1,v1,f2,v2) ( \ - (R_WATCHDOG__key__##f1##__MASK & REG__##v1) | \ - (R_WATCHDOG__enable__##f2##__MASK & REG__##v2) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_WATCHDOG -*# -*# PARAMETERS : fn : Name of field N. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_WATCHDOG. -*# Parameters vn are checked for validity. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append -*# _ to fn parameters when passing -*# on to other macros. -*#**********************************************************************/ - -#define REG_VAL__R_WATCHDOG(f1,v1,f2,v2) ( \ - (R_WATCHDOG__key__##f1##__VAL(R_WATCHDOG_, key_, v1) << R_WATCHDOG__key__BITNR) | \ - (R_WATCHDOG__enable__##f2##__VAL(R_WATCHDOG_, enable_, v2) << R_WATCHDOG__enable__BITNR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL__R_WATCHDOG_ -*# -*# PARAMETERS : fn_ : Name of field N, with "_" appended. -*# vn : Value in field N. -*# -*# RETURNS : Integer value. -*# -*# SIDE EFFECTS: REG_VERROR may be evaluated. -*# -*# DESCRIPTION : Create a value by combining the vn parameters according -*# to the fields in register R_WATCHDOG. -*# Parameters vn are checked for validity. -*# INTERNAL: for use by other macros in this file only. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Sep 30 2002 Hans-Peter Nilsson Initial version -*#**********************************************************************/ - -#define REG_VAL__R_WATCHDOG_(f1_,v1,f2_,v2) ( \ - (R_WATCHDOG__key__##f1_##_VAL(R_WATCHDOG_, key_, v1) << R_WATCHDOG__key__BITNR) | \ - (R_WATCHDOG__enable__##f2_##_VAL(R_WATCHDOG_, enable_, v2) << R_WATCHDOG__enable__BITNR) \ -) - -#endif - -#endif diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/src/hwregs_def.h b/target/linux/etrax-2.6/image/e100boot/src/cbl/src/hwregs_def.h deleted file mode 100644 index 75077cfa85..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/cbl/src/hwregs_def.h +++ /dev/null @@ -1,5435 +0,0 @@ -/*!********************************************************************** -*! -*! FILE NAME: hwregs_def.h -*! -*! DESCRIPTION: Template file for register field default values used by -*! the init_shadow() function defined in hwregs.c -*! For each field in each register select a default value -*! from the listed set of valid values. -*! Only write only registers need default values. -*! This file is included in hwregs.h -*! -*! FUNCTIONS: none -*! -*! NOTE: This file is automatically generated, do _not_ edit. -*! Created: Thu Oct 3 01:21:27 2002 -*! By: Id: shadow_gen,v 1.14 2002/10/02 20:31:22 hp Exp -*! From: /n/asic/projects/etrax_ng/doc/work/etrax_ng_regs.rd 1.168 -*! /n/asic/projects/etrax_ng/include//hwregs.ctrl 1.3 -*! -*! NOTE: There are default constants for all write only registers described -*! in /n/asic/projects/etrax_ng/doc/work/etrax_ng_regs.rd. -*! Since one physical register may have several logical names you -*! only need default constants for those registers that are -*! initiated in init_shadow(). This is done by the -*! 'USE_GROUP__group-name' macros in this file. -*! -*! As an example, in Etrax100 the following logical registers are -*! all the same physical register at address 0xb0000044: -*! -*! R_ATA_CONFIG -*! R_PAR0_CONFIG -*! R_SCSI0_CTRL -*! R_SHARED_RAM_ADDR -*! -*!---------------------------------------------------------------------- -*! HISTORY -*! -*! DATE NAME CHANGES -*! ---- ---- ------- -*! Apr 01 1998 Jan Bengtsson Initial version -*!---------------------------------------------------------------------- -*! -*! (C) Copyright 1998, Axis Communications AB, LUND, SWEDEN -*! -*!**********************************************************************/ -/* %Z% %M% %I% %G% */ - -#ifndef __HWREGS_DEF_H__ -#define __HWREGS_DEF_H__ - -/********************** INCLUDE FILES SECTION **************************/ - -/********************** CONSTANT AND MACRO SECTION *********************/ - -/* -** To use shadow registers for a register_group, define the following -** macros to TRUE in a project specific file. -*/ - -#ifndef USE_GROUP__Serial_port_registers -#define USE_GROUP__Serial_port_registers 1 -#endif - -#ifndef USE_GROUP__ATA_interface_registers -#define USE_GROUP__ATA_interface_registers 1 -#endif - -#ifndef USE_GROUP__Bus_interface_configuration_registers -#define USE_GROUP__Bus_interface_configuration_registers 1 -#endif - -#ifndef USE_GROUP__Timer_registers -#define USE_GROUP__Timer_registers 1 -#endif - -#ifndef USE_GROUP__DMA_registers -#define USE_GROUP__DMA_registers 1 -#endif - -#ifndef USE_GROUP__External_DMA_registers -#define USE_GROUP__External_DMA_registers 1 -#endif - -#ifndef USE_GROUP__General_config_registers -#define USE_GROUP__General_config_registers 1 -#endif - -#ifndef USE_GROUP__Interrupt_mask_and_status_registers -#define USE_GROUP__Interrupt_mask_and_status_registers 1 -#endif - -#ifndef USE_GROUP__MMU_registers -#define USE_GROUP__MMU_registers 1 -#endif - -#ifndef USE_GROUP__Network_interface_registers -#define USE_GROUP__Network_interface_registers 1 -#endif - -#ifndef USE_GROUP__Parallel_printer_port_registers -#define USE_GROUP__Parallel_printer_port_registers 1 -#endif - -#ifndef USE_GROUP__General_port_configuration_registers -#define USE_GROUP__General_port_configuration_registers 1 -#endif - -#ifndef USE_GROUP__SCSI_registers -#define USE_GROUP__SCSI_registers 1 -#endif - -#ifndef USE_GROUP__Shared_RAM_interface_registers -#define USE_GROUP__Shared_RAM_interface_registers 1 -#endif - -#ifndef USE_GROUP__Test_mode_registers -#define USE_GROUP__Test_mode_registers 1 -#endif - -#ifndef USE_GROUP__Syncrounous_serial_port_registers -#define USE_GROUP__Syncrounous_serial_port_registers 1 -#endif - -#ifndef USE_GROUP__USB_interface_control_registers -#define USE_GROUP__USB_interface_control_registers 1 -#endif - - -/* -** Default values for register R_ALT_SER_BAUDRATE -*/ - -/* timer normal extern prescale */ -#ifndef R_ALT_SER_BAUDRATE__ser3_tr__DEFAULT -#define R_ALT_SER_BAUDRATE__ser3_tr__DEFAULT timer -#endif - -/* timer normal extern prescale */ -#ifndef R_ALT_SER_BAUDRATE__ser3_rec__DEFAULT -#define R_ALT_SER_BAUDRATE__ser3_rec__DEFAULT timer -#endif - -/* timer normal extern prescale */ -#ifndef R_ALT_SER_BAUDRATE__ser2_tr__DEFAULT -#define R_ALT_SER_BAUDRATE__ser2_tr__DEFAULT timer -#endif - -/* timer normal extern prescale */ -#ifndef R_ALT_SER_BAUDRATE__ser2_rec__DEFAULT -#define R_ALT_SER_BAUDRATE__ser2_rec__DEFAULT timer -#endif - -/* timer normal extern prescale */ -#ifndef R_ALT_SER_BAUDRATE__ser1_tr__DEFAULT -#define R_ALT_SER_BAUDRATE__ser1_tr__DEFAULT timer -#endif - -/* timer normal extern prescale */ -#ifndef R_ALT_SER_BAUDRATE__ser1_rec__DEFAULT -#define R_ALT_SER_BAUDRATE__ser1_rec__DEFAULT timer -#endif - -/* timer normal extern prescale */ -#ifndef R_ALT_SER_BAUDRATE__ser0_tr__DEFAULT -#define R_ALT_SER_BAUDRATE__ser0_tr__DEFAULT timer -#endif - -/* timer normal extern prescale */ -#ifndef R_ALT_SER_BAUDRATE__ser0_rec__DEFAULT -#define R_ALT_SER_BAUDRATE__ser0_rec__DEFAULT timer -#endif - -/* -** Default values for register R_ATA_CONFIG -*/ - -/* off on */ -#ifndef R_ATA_CONFIG__enable__DEFAULT -#define R_ATA_CONFIG__enable__DEFAULT off -#endif - -/* 0 - 31 */ -#ifndef R_ATA_CONFIG__dma_strobe__DEFAULT -#define R_ATA_CONFIG__dma_strobe__DEFAULT 0 -#endif - -/* 0 - 31 */ -#ifndef R_ATA_CONFIG__dma_hold__DEFAULT -#define R_ATA_CONFIG__dma_hold__DEFAULT 0 -#endif - -/* 0 - 31 */ -#ifndef R_ATA_CONFIG__pio_setup__DEFAULT -#define R_ATA_CONFIG__pio_setup__DEFAULT 0 -#endif - -/* 0 - 31 */ -#ifndef R_ATA_CONFIG__pio_strobe__DEFAULT -#define R_ATA_CONFIG__pio_strobe__DEFAULT 0 -#endif - -/* 0 - 31 */ -#ifndef R_ATA_CONFIG__pio_hold__DEFAULT -#define R_ATA_CONFIG__pio_hold__DEFAULT 0 -#endif - -/* -** Default values for register R_ATA_CTRL_DATA -*/ - -/* 0 - 3 */ -#ifndef R_ATA_CTRL_DATA__sel__DEFAULT -#define R_ATA_CTRL_DATA__sel__DEFAULT 0 -#endif - -/* inactive active */ -#ifndef R_ATA_CTRL_DATA__cs1__DEFAULT -#define R_ATA_CTRL_DATA__cs1__DEFAULT inactive -#endif - -/* inactive active */ -#ifndef R_ATA_CTRL_DATA__cs0__DEFAULT -#define R_ATA_CTRL_DATA__cs0__DEFAULT inactive -#endif - -/* 0 - 7 */ -#ifndef R_ATA_CTRL_DATA__addr__DEFAULT -#define R_ATA_CTRL_DATA__addr__DEFAULT 0 -#endif - -/* write read */ -#ifndef R_ATA_CTRL_DATA__rw__DEFAULT -#define R_ATA_CTRL_DATA__rw__DEFAULT write -#endif - -/* dma register */ -#ifndef R_ATA_CTRL_DATA__src_dst__DEFAULT -#define R_ATA_CTRL_DATA__src_dst__DEFAULT dma -#endif - -/* pio dma */ -#ifndef R_ATA_CTRL_DATA__handsh__DEFAULT -#define R_ATA_CTRL_DATA__handsh__DEFAULT pio -#endif - -/* off on */ -#ifndef R_ATA_CTRL_DATA__multi__DEFAULT -#define R_ATA_CTRL_DATA__multi__DEFAULT off -#endif - -/* word byte */ -#ifndef R_ATA_CTRL_DATA__dma_size__DEFAULT -#define R_ATA_CTRL_DATA__dma_size__DEFAULT word -#endif - -/* 0 - 0xffff */ -#ifndef R_ATA_CTRL_DATA__data__DEFAULT -#define R_ATA_CTRL_DATA__data__DEFAULT 0 -#endif - -/* -** Default values for register R_BUS_CONFIG -*/ - -/* bwe cwe */ -#ifndef R_BUS_CONFIG__sram_type__DEFAULT -#define R_BUS_CONFIG__sram_type__DEFAULT bwe -#endif - -/* burst32 burst16 */ -#ifndef R_BUS_CONFIG__dma_burst__DEFAULT -#define R_BUS_CONFIG__dma_burst__DEFAULT burst32 -#endif - -/* ext norm */ -#ifndef R_BUS_CONFIG__pcs4_7_wr__DEFAULT -#define R_BUS_CONFIG__pcs4_7_wr__DEFAULT ext -#endif - -/* ext norm */ -#ifndef R_BUS_CONFIG__pcs0_3_wr__DEFAULT -#define R_BUS_CONFIG__pcs0_3_wr__DEFAULT ext -#endif - -/* ext norm */ -#ifndef R_BUS_CONFIG__sram_wr__DEFAULT -#define R_BUS_CONFIG__sram_wr__DEFAULT ext -#endif - -/* ext norm */ -#ifndef R_BUS_CONFIG__flash_wr__DEFAULT -#define R_BUS_CONFIG__flash_wr__DEFAULT ext -#endif - -/* bw16 bw32 */ -#ifndef R_BUS_CONFIG__pcs4_7_bw__DEFAULT -#define R_BUS_CONFIG__pcs4_7_bw__DEFAULT bw16 -#endif - -/* bw16 bw32 */ -#ifndef R_BUS_CONFIG__pcs0_3_bw__DEFAULT -#define R_BUS_CONFIG__pcs0_3_bw__DEFAULT bw16 -#endif - -/* bw16 bw32 */ -#ifndef R_BUS_CONFIG__sram_bw__DEFAULT -#define R_BUS_CONFIG__sram_bw__DEFAULT bw16 -#endif - -/* bw16 bw32 */ -#ifndef R_BUS_CONFIG__flash_bw__DEFAULT -#define R_BUS_CONFIG__flash_bw__DEFAULT bw16 -#endif - -/* -** Default values for register R_CLOCK_PRESCALE -*/ - -/* 0 - 0xffff */ -#ifndef R_CLOCK_PRESCALE__ser_presc__DEFAULT -#define R_CLOCK_PRESCALE__ser_presc__DEFAULT 0 -#endif - -/* 0 - 0xffff */ -#ifndef R_CLOCK_PRESCALE__tim_presc__DEFAULT -#define R_CLOCK_PRESCALE__tim_presc__DEFAULT 0 -#endif - -/* -** Default values for register R_DMA_CH0_CLR_INTR -*/ - -/* do dont */ -#ifndef R_DMA_CH0_CLR_INTR__clr_eop__DEFAULT -#define R_DMA_CH0_CLR_INTR__clr_eop__DEFAULT do -#endif - -/* do dont */ -#ifndef R_DMA_CH0_CLR_INTR__clr_descr__DEFAULT -#define R_DMA_CH0_CLR_INTR__clr_descr__DEFAULT do -#endif - -/* -** Default values for register R_DMA_CH1_CLR_INTR -*/ - -/* do dont */ -#ifndef R_DMA_CH1_CLR_INTR__clr_eop__DEFAULT -#define R_DMA_CH1_CLR_INTR__clr_eop__DEFAULT do -#endif - -/* do dont */ -#ifndef R_DMA_CH1_CLR_INTR__clr_descr__DEFAULT -#define R_DMA_CH1_CLR_INTR__clr_descr__DEFAULT do -#endif - -/* -** Default values for register R_DMA_CH2_CLR_INTR -*/ - -/* do dont */ -#ifndef R_DMA_CH2_CLR_INTR__clr_eop__DEFAULT -#define R_DMA_CH2_CLR_INTR__clr_eop__DEFAULT do -#endif - -/* do dont */ -#ifndef R_DMA_CH2_CLR_INTR__clr_descr__DEFAULT -#define R_DMA_CH2_CLR_INTR__clr_descr__DEFAULT do -#endif - -/* -** Default values for register R_DMA_CH3_CLR_INTR -*/ - -/* do dont */ -#ifndef R_DMA_CH3_CLR_INTR__clr_eop__DEFAULT -#define R_DMA_CH3_CLR_INTR__clr_eop__DEFAULT do -#endif - -/* do dont */ -#ifndef R_DMA_CH3_CLR_INTR__clr_descr__DEFAULT -#define R_DMA_CH3_CLR_INTR__clr_descr__DEFAULT do -#endif - -/* -** Default values for register R_DMA_CH4_CLR_INTR -*/ - -/* do dont */ -#ifndef R_DMA_CH4_CLR_INTR__clr_eop__DEFAULT -#define R_DMA_CH4_CLR_INTR__clr_eop__DEFAULT do -#endif - -/* do dont */ -#ifndef R_DMA_CH4_CLR_INTR__clr_descr__DEFAULT -#define R_DMA_CH4_CLR_INTR__clr_descr__DEFAULT do -#endif - -/* -** Default values for register R_DMA_CH5_CLR_INTR -*/ - -/* do dont */ -#ifndef R_DMA_CH5_CLR_INTR__clr_eop__DEFAULT -#define R_DMA_CH5_CLR_INTR__clr_eop__DEFAULT do -#endif - -/* do dont */ -#ifndef R_DMA_CH5_CLR_INTR__clr_descr__DEFAULT -#define R_DMA_CH5_CLR_INTR__clr_descr__DEFAULT do -#endif - -/* -** Default values for register R_DMA_CH6_CLR_INTR -*/ - -/* do dont */ -#ifndef R_DMA_CH6_CLR_INTR__clr_eop__DEFAULT -#define R_DMA_CH6_CLR_INTR__clr_eop__DEFAULT do -#endif - -/* do dont */ -#ifndef R_DMA_CH6_CLR_INTR__clr_descr__DEFAULT -#define R_DMA_CH6_CLR_INTR__clr_descr__DEFAULT do -#endif - -/* -** Default values for register R_DMA_CH7_CLR_INTR -*/ - -/* do dont */ -#ifndef R_DMA_CH7_CLR_INTR__clr_eop__DEFAULT -#define R_DMA_CH7_CLR_INTR__clr_eop__DEFAULT do -#endif - -/* do dont */ -#ifndef R_DMA_CH7_CLR_INTR__clr_descr__DEFAULT -#define R_DMA_CH7_CLR_INTR__clr_descr__DEFAULT do -#endif - -/* -** Default values for register R_DMA_CH8_CLR_INTR -*/ - -/* do dont */ -#ifndef R_DMA_CH8_CLR_INTR__clr_eop__DEFAULT -#define R_DMA_CH8_CLR_INTR__clr_eop__DEFAULT do -#endif - -/* do dont */ -#ifndef R_DMA_CH8_CLR_INTR__clr_descr__DEFAULT -#define R_DMA_CH8_CLR_INTR__clr_descr__DEFAULT do -#endif - -/* -** Default values for register R_DMA_CH8_SUB0_CLR_INTR -*/ - -/* do dont */ -#ifndef R_DMA_CH8_SUB0_CLR_INTR__clr_descr__DEFAULT -#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__DEFAULT do -#endif - -/* -** Default values for register R_DMA_CH8_SUB1_CLR_INTR -*/ - -/* do dont */ -#ifndef R_DMA_CH8_SUB1_CLR_INTR__clr_descr__DEFAULT -#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__DEFAULT do -#endif - -/* -** Default values for register R_DMA_CH8_SUB2_CLR_INTR -*/ - -/* do dont */ -#ifndef R_DMA_CH8_SUB2_CLR_INTR__clr_descr__DEFAULT -#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__DEFAULT do -#endif - -/* -** Default values for register R_DMA_CH8_SUB3_CLR_INTR -*/ - -/* do dont */ -#ifndef R_DMA_CH8_SUB3_CLR_INTR__clr_descr__DEFAULT -#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__DEFAULT do -#endif - -/* -** Default values for register R_DMA_CH9_CLR_INTR -*/ - -/* do dont */ -#ifndef R_DMA_CH9_CLR_INTR__clr_eop__DEFAULT -#define R_DMA_CH9_CLR_INTR__clr_eop__DEFAULT do -#endif - -/* do dont */ -#ifndef R_DMA_CH9_CLR_INTR__clr_descr__DEFAULT -#define R_DMA_CH9_CLR_INTR__clr_descr__DEFAULT do -#endif - -/* -** Default values for register R_DRAM_CONFIG -*/ - -/* wmm norm */ -#ifndef R_DRAM_CONFIG__wmm1__DEFAULT -#define R_DRAM_CONFIG__wmm1__DEFAULT wmm -#endif - -/* wmm norm */ -#ifndef R_DRAM_CONFIG__wmm0__DEFAULT -#define R_DRAM_CONFIG__wmm0__DEFAULT wmm -#endif - -/* 0 - 7 */ -#ifndef R_DRAM_CONFIG__sh1__DEFAULT -#define R_DRAM_CONFIG__sh1__DEFAULT 0 -#endif - -/* 0 - 7 */ -#ifndef R_DRAM_CONFIG__sh0__DEFAULT -#define R_DRAM_CONFIG__sh0__DEFAULT 0 -#endif - -/* bw16 bw32 */ -#ifndef R_DRAM_CONFIG__w__DEFAULT -#define R_DRAM_CONFIG__w__DEFAULT bw16 -#endif - -/* bank byte */ -#ifndef R_DRAM_CONFIG__c__DEFAULT -#define R_DRAM_CONFIG__c__DEFAULT bank -#endif - -/* edo fast */ -#ifndef R_DRAM_CONFIG__e__DEFAULT -#define R_DRAM_CONFIG__e__DEFAULT edo -#endif - -/* bit10 bit20 bit11 bit21 bit12 bit22 bit13 bit23 bit14 bit24 bit15 bit25 bit16 bit26 bit17 bit27 bit18 bit9 bit28 bit19 grp0 bit29 grp1 */ -#ifndef R_DRAM_CONFIG__group_sel__DEFAULT -#define R_DRAM_CONFIG__group_sel__DEFAULT bit10 -#endif - -/* 0 - 7 */ -#ifndef R_DRAM_CONFIG__ca1__DEFAULT -#define R_DRAM_CONFIG__ca1__DEFAULT 0 -#endif - -/* bit10 bit20 bit11 bit21 bit12 bit22 bit13 bit23 bit14 bit24 bit15 bit25 bit16 bit26 bit17 bit27 bit18 bit28 bit19 bit29 bank0 bank1 bit9 */ -#ifndef R_DRAM_CONFIG__bank23sel__DEFAULT -#define R_DRAM_CONFIG__bank23sel__DEFAULT bit10 -#endif - -/* 0 - 7 */ -#ifndef R_DRAM_CONFIG__ca0__DEFAULT -#define R_DRAM_CONFIG__ca0__DEFAULT 0 -#endif - -/* bit10 bit20 bit11 bit21 bit12 bit22 bit13 bit23 bit14 bit24 bit15 bit25 bit16 bit26 bit17 bit27 bit18 bit28 bit19 bit29 bank0 bank1 bit9 */ -#ifndef R_DRAM_CONFIG__bank01sel__DEFAULT -#define R_DRAM_CONFIG__bank01sel__DEFAULT bit10 -#endif - -/* -** Default values for register R_DRAM_TIMING -*/ - -/* disable enable */ -#ifndef R_DRAM_TIMING__sdram__DEFAULT -#define R_DRAM_TIMING__sdram__DEFAULT disable -#endif - -/* e13us disable e52us e8700ns */ -#ifndef R_DRAM_TIMING__ref__DEFAULT -#define R_DRAM_TIMING__ref__DEFAULT e13us -#endif - -/* 0 - 3 */ -#ifndef R_DRAM_TIMING__rp__DEFAULT -#define R_DRAM_TIMING__rp__DEFAULT 0 -#endif - -/* 0 - 3 */ -#ifndef R_DRAM_TIMING__rs__DEFAULT -#define R_DRAM_TIMING__rs__DEFAULT 0 -#endif - -/* 0 - 3 */ -#ifndef R_DRAM_TIMING__rh__DEFAULT -#define R_DRAM_TIMING__rh__DEFAULT 0 -#endif - -/* ext norm */ -#ifndef R_DRAM_TIMING__w__DEFAULT -#define R_DRAM_TIMING__w__DEFAULT ext -#endif - -/* ext norm */ -#ifndef R_DRAM_TIMING__c__DEFAULT -#define R_DRAM_TIMING__c__DEFAULT ext -#endif - -/* 0 - 3 */ -#ifndef R_DRAM_TIMING__cz__DEFAULT -#define R_DRAM_TIMING__cz__DEFAULT 0 -#endif - -/* 0 - 3 */ -#ifndef R_DRAM_TIMING__cp__DEFAULT -#define R_DRAM_TIMING__cp__DEFAULT 0 -#endif - -/* 0 - 3 */ -#ifndef R_DRAM_TIMING__cw__DEFAULT -#define R_DRAM_TIMING__cw__DEFAULT 0 -#endif - -/* -** Default values for register R_EXT_DMA_0_ADDR -*/ - -/* 0 - 0xfffffff */ -#ifndef R_EXT_DMA_0_ADDR__ext0_addr__DEFAULT -#define R_EXT_DMA_0_ADDR__ext0_addr__DEFAULT 0 -#endif - -/* -** Default values for register R_EXT_DMA_0_CMD -*/ - -/* disable enable */ -#ifndef R_EXT_DMA_0_CMD__cnt__DEFAULT -#define R_EXT_DMA_0_CMD__cnt__DEFAULT disable -#endif - -/* ahigh alow */ -#ifndef R_EXT_DMA_0_CMD__rqpol__DEFAULT -#define R_EXT_DMA_0_CMD__rqpol__DEFAULT ahigh -#endif - -/* ahigh alow */ -#ifndef R_EXT_DMA_0_CMD__apol__DEFAULT -#define R_EXT_DMA_0_CMD__apol__DEFAULT ahigh -#endif - -/* burst handsh */ -#ifndef R_EXT_DMA_0_CMD__rq_ack__DEFAULT -#define R_EXT_DMA_0_CMD__rq_ack__DEFAULT burst -#endif - -/* dword word byte */ -#ifndef R_EXT_DMA_0_CMD__wid__DEFAULT -#define R_EXT_DMA_0_CMD__wid__DEFAULT dword -#endif - -/* input output */ -#ifndef R_EXT_DMA_0_CMD__dir__DEFAULT -#define R_EXT_DMA_0_CMD__dir__DEFAULT input -#endif - -/* stop start */ -#ifndef R_EXT_DMA_0_CMD__run__DEFAULT -#define R_EXT_DMA_0_CMD__run__DEFAULT stop -#endif - -/* 0 - 0xffff */ -#ifndef R_EXT_DMA_0_CMD__trf_count__DEFAULT -#define R_EXT_DMA_0_CMD__trf_count__DEFAULT 0 -#endif - -/* -** Default values for register R_EXT_DMA_1_ADDR -*/ - -/* 0 - 0xfffffff */ -#ifndef R_EXT_DMA_1_ADDR__ext0_addr__DEFAULT -#define R_EXT_DMA_1_ADDR__ext0_addr__DEFAULT 0 -#endif - -/* -** Default values for register R_EXT_DMA_1_CMD -*/ - -/* disable enable */ -#ifndef R_EXT_DMA_1_CMD__cnt__DEFAULT -#define R_EXT_DMA_1_CMD__cnt__DEFAULT disable -#endif - -/* ahigh alow */ -#ifndef R_EXT_DMA_1_CMD__rqpol__DEFAULT -#define R_EXT_DMA_1_CMD__rqpol__DEFAULT ahigh -#endif - -/* ahigh alow */ -#ifndef R_EXT_DMA_1_CMD__apol__DEFAULT -#define R_EXT_DMA_1_CMD__apol__DEFAULT ahigh -#endif - -/* burst handsh */ -#ifndef R_EXT_DMA_1_CMD__rq_ack__DEFAULT -#define R_EXT_DMA_1_CMD__rq_ack__DEFAULT burst -#endif - -/* dword word byte */ -#ifndef R_EXT_DMA_1_CMD__wid__DEFAULT -#define R_EXT_DMA_1_CMD__wid__DEFAULT dword -#endif - -/* input output */ -#ifndef R_EXT_DMA_1_CMD__dir__DEFAULT -#define R_EXT_DMA_1_CMD__dir__DEFAULT input -#endif - -/* stop start */ -#ifndef R_EXT_DMA_1_CMD__run__DEFAULT -#define R_EXT_DMA_1_CMD__run__DEFAULT stop -#endif - -/* 0 - 0xffff */ -#ifndef R_EXT_DMA_1_CMD__trf_count__DEFAULT -#define R_EXT_DMA_1_CMD__trf_count__DEFAULT 0 -#endif - -/* -** Default values for register R_GEN_CONFIG -*/ - -/* select disable */ -#ifndef R_GEN_CONFIG__par_w__DEFAULT -#define R_GEN_CONFIG__par_w__DEFAULT select -#endif - -/* select disable */ -#ifndef R_GEN_CONFIG__usb2__DEFAULT -#define R_GEN_CONFIG__usb2__DEFAULT select -#endif - -/* select disable */ -#ifndef R_GEN_CONFIG__usb1__DEFAULT -#define R_GEN_CONFIG__usb1__DEFAULT select -#endif - -/* out in */ -#ifndef R_GEN_CONFIG__g24dir__DEFAULT -#define R_GEN_CONFIG__g24dir__DEFAULT out -#endif - -/* out in */ -#ifndef R_GEN_CONFIG__g16_23dir__DEFAULT -#define R_GEN_CONFIG__g16_23dir__DEFAULT out -#endif - -/* out in */ -#ifndef R_GEN_CONFIG__g8_15dir__DEFAULT -#define R_GEN_CONFIG__g8_15dir__DEFAULT out -#endif - -/* out in */ -#ifndef R_GEN_CONFIG__g0dir__DEFAULT -#define R_GEN_CONFIG__g0dir__DEFAULT out -#endif - -/* serial1 usb */ -#ifndef R_GEN_CONFIG__dma9__DEFAULT -#define R_GEN_CONFIG__dma9__DEFAULT serial1 -#endif - -/* serial1 usb */ -#ifndef R_GEN_CONFIG__dma8__DEFAULT -#define R_GEN_CONFIG__dma8__DEFAULT serial1 -#endif - -/* serial0 intdma6 extdma1 unused */ -#ifndef R_GEN_CONFIG__dma7__DEFAULT -#define R_GEN_CONFIG__dma7__DEFAULT serial0 -#endif - -/* serial0 intdma7 extdma1 unused */ -#ifndef R_GEN_CONFIG__dma6__DEFAULT -#define R_GEN_CONFIG__dma6__DEFAULT serial0 -#endif - -/* extdma0 serial3 scsi1 par1 */ -#ifndef R_GEN_CONFIG__dma5__DEFAULT -#define R_GEN_CONFIG__dma5__DEFAULT extdma0 -#endif - -/* extdma0 serial3 scsi1 par1 */ -#ifndef R_GEN_CONFIG__dma4__DEFAULT -#define R_GEN_CONFIG__dma4__DEFAULT extdma0 -#endif - -/* serial2 scsi0 par0 ata */ -#ifndef R_GEN_CONFIG__dma3__DEFAULT -#define R_GEN_CONFIG__dma3__DEFAULT serial2 -#endif - -/* serial2 scsi0 par0 ata */ -#ifndef R_GEN_CONFIG__dma2__DEFAULT -#define R_GEN_CONFIG__dma2__DEFAULT serial2 -#endif - -/* select disable */ -#ifndef R_GEN_CONFIG__mio_w__DEFAULT -#define R_GEN_CONFIG__mio_w__DEFAULT select -#endif - -/* select disable */ -#ifndef R_GEN_CONFIG__ser3__DEFAULT -#define R_GEN_CONFIG__ser3__DEFAULT select -#endif - -/* select disable */ -#ifndef R_GEN_CONFIG__par1__DEFAULT -#define R_GEN_CONFIG__par1__DEFAULT select -#endif - -/* select disable */ -#ifndef R_GEN_CONFIG__scsi0w__DEFAULT -#define R_GEN_CONFIG__scsi0w__DEFAULT select -#endif - -/* select disable */ -#ifndef R_GEN_CONFIG__scsi1__DEFAULT -#define R_GEN_CONFIG__scsi1__DEFAULT select -#endif - -/* select disable */ -#ifndef R_GEN_CONFIG__mio__DEFAULT -#define R_GEN_CONFIG__mio__DEFAULT select -#endif - -/* select disable */ -#ifndef R_GEN_CONFIG__ser2__DEFAULT -#define R_GEN_CONFIG__ser2__DEFAULT select -#endif - -/* select disable */ -#ifndef R_GEN_CONFIG__par0__DEFAULT -#define R_GEN_CONFIG__par0__DEFAULT select -#endif - -/* select disable */ -#ifndef R_GEN_CONFIG__ata__DEFAULT -#define R_GEN_CONFIG__ata__DEFAULT select -#endif - -/* select disable */ -#ifndef R_GEN_CONFIG__scsi0__DEFAULT -#define R_GEN_CONFIG__scsi0__DEFAULT select -#endif - -/* -** Default values for register R_GEN_CONFIG_II -*/ - -/* sync async */ -#ifndef R_GEN_CONFIG_II__sermode3__DEFAULT -#define R_GEN_CONFIG_II__sermode3__DEFAULT sync -#endif - -/* sync async */ -#ifndef R_GEN_CONFIG_II__sermode1__DEFAULT -#define R_GEN_CONFIG_II__sermode1__DEFAULT sync -#endif - -/* select disable */ -#ifndef R_GEN_CONFIG_II__ext_clk__DEFAULT -#define R_GEN_CONFIG_II__ext_clk__DEFAULT select -#endif - -/* select disable */ -#ifndef R_GEN_CONFIG_II__ser3__DEFAULT -#define R_GEN_CONFIG_II__ser3__DEFAULT select -#endif - -/* select disable */ -#ifndef R_GEN_CONFIG_II__ser2__DEFAULT -#define R_GEN_CONFIG_II__ser2__DEFAULT select -#endif - -/* -** Default values for register R_IRQ_MASK0_CLR -*/ - -/* clr nop */ -#ifndef R_IRQ_MASK0_CLR__nmi_pin__DEFAULT -#define R_IRQ_MASK0_CLR__nmi_pin__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK0_CLR__watchdog_nmi__DEFAULT -#define R_IRQ_MASK0_CLR__watchdog_nmi__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK0_CLR__sqe_test_error__DEFAULT -#define R_IRQ_MASK0_CLR__sqe_test_error__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK0_CLR__carrier_loss__DEFAULT -#define R_IRQ_MASK0_CLR__carrier_loss__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK0_CLR__deferred__DEFAULT -#define R_IRQ_MASK0_CLR__deferred__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK0_CLR__late_col__DEFAULT -#define R_IRQ_MASK0_CLR__late_col__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK0_CLR__multiple_col__DEFAULT -#define R_IRQ_MASK0_CLR__multiple_col__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK0_CLR__single_col__DEFAULT -#define R_IRQ_MASK0_CLR__single_col__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK0_CLR__congestion__DEFAULT -#define R_IRQ_MASK0_CLR__congestion__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK0_CLR__oversize__DEFAULT -#define R_IRQ_MASK0_CLR__oversize__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK0_CLR__alignment_error__DEFAULT -#define R_IRQ_MASK0_CLR__alignment_error__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK0_CLR__crc_error__DEFAULT -#define R_IRQ_MASK0_CLR__crc_error__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK0_CLR__overrun__DEFAULT -#define R_IRQ_MASK0_CLR__overrun__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK0_CLR__underrun__DEFAULT -#define R_IRQ_MASK0_CLR__underrun__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK0_CLR__excessive_col__DEFAULT -#define R_IRQ_MASK0_CLR__excessive_col__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK0_CLR__mdio__DEFAULT -#define R_IRQ_MASK0_CLR__mdio__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK0_CLR__ata_drq3__DEFAULT -#define R_IRQ_MASK0_CLR__ata_drq3__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK0_CLR__ata_drq2__DEFAULT -#define R_IRQ_MASK0_CLR__ata_drq2__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK0_CLR__ata_drq1__DEFAULT -#define R_IRQ_MASK0_CLR__ata_drq1__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK0_CLR__ata_drq0__DEFAULT -#define R_IRQ_MASK0_CLR__ata_drq0__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK0_CLR__par0_ecp_cmd__DEFAULT -#define R_IRQ_MASK0_CLR__par0_ecp_cmd__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK0_CLR__par0_peri__DEFAULT -#define R_IRQ_MASK0_CLR__par0_peri__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK0_CLR__par0_data__DEFAULT -#define R_IRQ_MASK0_CLR__par0_data__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK0_CLR__par0_ready__DEFAULT -#define R_IRQ_MASK0_CLR__par0_ready__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK0_CLR__ata_dmaend__DEFAULT -#define R_IRQ_MASK0_CLR__ata_dmaend__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK0_CLR__irq_ext_vector_nr__DEFAULT -#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK0_CLR__irq_int_vector_nr__DEFAULT -#define R_IRQ_MASK0_CLR__irq_int_vector_nr__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK0_CLR__ext_dma1__DEFAULT -#define R_IRQ_MASK0_CLR__ext_dma1__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK0_CLR__ext_dma0__DEFAULT -#define R_IRQ_MASK0_CLR__ext_dma0__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK0_CLR__timer1__DEFAULT -#define R_IRQ_MASK0_CLR__timer1__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK0_CLR__timer0__DEFAULT -#define R_IRQ_MASK0_CLR__timer0__DEFAULT clr -#endif - -/* -** Default values for register R_IRQ_MASK0_SET -*/ - -/* set nop */ -#ifndef R_IRQ_MASK0_SET__nmi_pin__DEFAULT -#define R_IRQ_MASK0_SET__nmi_pin__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK0_SET__watchdog_nmi__DEFAULT -#define R_IRQ_MASK0_SET__watchdog_nmi__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK0_SET__sqe_test_error__DEFAULT -#define R_IRQ_MASK0_SET__sqe_test_error__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK0_SET__carrier_loss__DEFAULT -#define R_IRQ_MASK0_SET__carrier_loss__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK0_SET__deferred__DEFAULT -#define R_IRQ_MASK0_SET__deferred__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK0_SET__late_col__DEFAULT -#define R_IRQ_MASK0_SET__late_col__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK0_SET__multiple_col__DEFAULT -#define R_IRQ_MASK0_SET__multiple_col__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK0_SET__single_col__DEFAULT -#define R_IRQ_MASK0_SET__single_col__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK0_SET__congestion__DEFAULT -#define R_IRQ_MASK0_SET__congestion__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK0_SET__oversize__DEFAULT -#define R_IRQ_MASK0_SET__oversize__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK0_SET__alignment_error__DEFAULT -#define R_IRQ_MASK0_SET__alignment_error__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK0_SET__crc_error__DEFAULT -#define R_IRQ_MASK0_SET__crc_error__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK0_SET__overrun__DEFAULT -#define R_IRQ_MASK0_SET__overrun__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK0_SET__underrun__DEFAULT -#define R_IRQ_MASK0_SET__underrun__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK0_SET__excessive_col__DEFAULT -#define R_IRQ_MASK0_SET__excessive_col__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK0_SET__mdio__DEFAULT -#define R_IRQ_MASK0_SET__mdio__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK0_SET__ata_drq3__DEFAULT -#define R_IRQ_MASK0_SET__ata_drq3__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK0_SET__ata_drq2__DEFAULT -#define R_IRQ_MASK0_SET__ata_drq2__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK0_SET__ata_drq1__DEFAULT -#define R_IRQ_MASK0_SET__ata_drq1__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK0_SET__ata_drq0__DEFAULT -#define R_IRQ_MASK0_SET__ata_drq0__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK0_SET__par0_ecp_cmd__DEFAULT -#define R_IRQ_MASK0_SET__par0_ecp_cmd__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK0_SET__par0_peri__DEFAULT -#define R_IRQ_MASK0_SET__par0_peri__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK0_SET__par0_data__DEFAULT -#define R_IRQ_MASK0_SET__par0_data__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK0_SET__par0_ready__DEFAULT -#define R_IRQ_MASK0_SET__par0_ready__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK0_SET__ata_dmaend__DEFAULT -#define R_IRQ_MASK0_SET__ata_dmaend__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK0_SET__irq_ext_vector_nr__DEFAULT -#define R_IRQ_MASK0_SET__irq_ext_vector_nr__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK0_SET__irq_int_vector_nr__DEFAULT -#define R_IRQ_MASK0_SET__irq_int_vector_nr__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK0_SET__ext_dma1__DEFAULT -#define R_IRQ_MASK0_SET__ext_dma1__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK0_SET__ext_dma0__DEFAULT -#define R_IRQ_MASK0_SET__ext_dma0__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK0_SET__timer1__DEFAULT -#define R_IRQ_MASK0_SET__timer1__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK0_SET__timer0__DEFAULT -#define R_IRQ_MASK0_SET__timer0__DEFAULT set -#endif - -/* -** Default values for register R_IRQ_MASK1_CLR -*/ - -/* clr nop */ -#ifndef R_IRQ_MASK1_CLR__sw_int7__DEFAULT -#define R_IRQ_MASK1_CLR__sw_int7__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK1_CLR__sw_int6__DEFAULT -#define R_IRQ_MASK1_CLR__sw_int6__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK1_CLR__sw_int5__DEFAULT -#define R_IRQ_MASK1_CLR__sw_int5__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK1_CLR__sw_int4__DEFAULT -#define R_IRQ_MASK1_CLR__sw_int4__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK1_CLR__sw_int3__DEFAULT -#define R_IRQ_MASK1_CLR__sw_int3__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK1_CLR__sw_int2__DEFAULT -#define R_IRQ_MASK1_CLR__sw_int2__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK1_CLR__sw_int1__DEFAULT -#define R_IRQ_MASK1_CLR__sw_int1__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK1_CLR__sw_int0__DEFAULT -#define R_IRQ_MASK1_CLR__sw_int0__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK1_CLR__par1_ecp_cmd__DEFAULT -#define R_IRQ_MASK1_CLR__par1_ecp_cmd__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK1_CLR__par1_peri__DEFAULT -#define R_IRQ_MASK1_CLR__par1_peri__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK1_CLR__par1_data__DEFAULT -#define R_IRQ_MASK1_CLR__par1_data__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK1_CLR__par1_ready__DEFAULT -#define R_IRQ_MASK1_CLR__par1_ready__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK1_CLR__ser3_ready__DEFAULT -#define R_IRQ_MASK1_CLR__ser3_ready__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK1_CLR__ser3_data__DEFAULT -#define R_IRQ_MASK1_CLR__ser3_data__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK1_CLR__ser2_ready__DEFAULT -#define R_IRQ_MASK1_CLR__ser2_ready__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK1_CLR__ser2_data__DEFAULT -#define R_IRQ_MASK1_CLR__ser2_data__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK1_CLR__ser1_ready__DEFAULT -#define R_IRQ_MASK1_CLR__ser1_ready__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK1_CLR__ser1_data__DEFAULT -#define R_IRQ_MASK1_CLR__ser1_data__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK1_CLR__ser0_ready__DEFAULT -#define R_IRQ_MASK1_CLR__ser0_ready__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK1_CLR__ser0_data__DEFAULT -#define R_IRQ_MASK1_CLR__ser0_data__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK1_CLR__pa7__DEFAULT -#define R_IRQ_MASK1_CLR__pa7__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK1_CLR__pa6__DEFAULT -#define R_IRQ_MASK1_CLR__pa6__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK1_CLR__pa5__DEFAULT -#define R_IRQ_MASK1_CLR__pa5__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK1_CLR__pa4__DEFAULT -#define R_IRQ_MASK1_CLR__pa4__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK1_CLR__pa3__DEFAULT -#define R_IRQ_MASK1_CLR__pa3__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK1_CLR__pa2__DEFAULT -#define R_IRQ_MASK1_CLR__pa2__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK1_CLR__pa1__DEFAULT -#define R_IRQ_MASK1_CLR__pa1__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK1_CLR__pa0__DEFAULT -#define R_IRQ_MASK1_CLR__pa0__DEFAULT clr -#endif - -/* -** Default values for register R_IRQ_MASK1_SET -*/ - -/* set nop */ -#ifndef R_IRQ_MASK1_SET__sw_int7__DEFAULT -#define R_IRQ_MASK1_SET__sw_int7__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK1_SET__sw_int6__DEFAULT -#define R_IRQ_MASK1_SET__sw_int6__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK1_SET__sw_int5__DEFAULT -#define R_IRQ_MASK1_SET__sw_int5__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK1_SET__sw_int4__DEFAULT -#define R_IRQ_MASK1_SET__sw_int4__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK1_SET__sw_int3__DEFAULT -#define R_IRQ_MASK1_SET__sw_int3__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK1_SET__sw_int2__DEFAULT -#define R_IRQ_MASK1_SET__sw_int2__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK1_SET__sw_int1__DEFAULT -#define R_IRQ_MASK1_SET__sw_int1__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK1_SET__sw_int0__DEFAULT -#define R_IRQ_MASK1_SET__sw_int0__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK1_SET__par1_ecp_cmd__DEFAULT -#define R_IRQ_MASK1_SET__par1_ecp_cmd__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK1_SET__par1_peri__DEFAULT -#define R_IRQ_MASK1_SET__par1_peri__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK1_SET__par1_data__DEFAULT -#define R_IRQ_MASK1_SET__par1_data__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK1_SET__par1_ready__DEFAULT -#define R_IRQ_MASK1_SET__par1_ready__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK1_SET__ser3_ready__DEFAULT -#define R_IRQ_MASK1_SET__ser3_ready__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK1_SET__ser3_data__DEFAULT -#define R_IRQ_MASK1_SET__ser3_data__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK1_SET__ser2_ready__DEFAULT -#define R_IRQ_MASK1_SET__ser2_ready__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK1_SET__ser2_data__DEFAULT -#define R_IRQ_MASK1_SET__ser2_data__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK1_SET__ser1_ready__DEFAULT -#define R_IRQ_MASK1_SET__ser1_ready__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK1_SET__ser1_data__DEFAULT -#define R_IRQ_MASK1_SET__ser1_data__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK1_SET__ser0_ready__DEFAULT -#define R_IRQ_MASK1_SET__ser0_ready__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK1_SET__ser0_data__DEFAULT -#define R_IRQ_MASK1_SET__ser0_data__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK1_SET__pa7__DEFAULT -#define R_IRQ_MASK1_SET__pa7__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK1_SET__pa6__DEFAULT -#define R_IRQ_MASK1_SET__pa6__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK1_SET__pa5__DEFAULT -#define R_IRQ_MASK1_SET__pa5__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK1_SET__pa4__DEFAULT -#define R_IRQ_MASK1_SET__pa4__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK1_SET__pa3__DEFAULT -#define R_IRQ_MASK1_SET__pa3__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK1_SET__pa2__DEFAULT -#define R_IRQ_MASK1_SET__pa2__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK1_SET__pa1__DEFAULT -#define R_IRQ_MASK1_SET__pa1__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK1_SET__pa0__DEFAULT -#define R_IRQ_MASK1_SET__pa0__DEFAULT set -#endif - -/* -** Default values for register R_IRQ_MASK2_CLR -*/ - -/* clr nop */ -#ifndef R_IRQ_MASK2_CLR__dma8_sub3_descr__DEFAULT -#define R_IRQ_MASK2_CLR__dma8_sub3_descr__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK2_CLR__dma8_sub2_descr__DEFAULT -#define R_IRQ_MASK2_CLR__dma8_sub2_descr__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK2_CLR__dma8_sub1_descr__DEFAULT -#define R_IRQ_MASK2_CLR__dma8_sub1_descr__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK2_CLR__dma8_sub0_descr__DEFAULT -#define R_IRQ_MASK2_CLR__dma8_sub0_descr__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK2_CLR__dma9_eop__DEFAULT -#define R_IRQ_MASK2_CLR__dma9_eop__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK2_CLR__dma9_descr__DEFAULT -#define R_IRQ_MASK2_CLR__dma9_descr__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK2_CLR__dma8_eop__DEFAULT -#define R_IRQ_MASK2_CLR__dma8_eop__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK2_CLR__dma8_descr__DEFAULT -#define R_IRQ_MASK2_CLR__dma8_descr__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK2_CLR__dma7_eop__DEFAULT -#define R_IRQ_MASK2_CLR__dma7_eop__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK2_CLR__dma7_descr__DEFAULT -#define R_IRQ_MASK2_CLR__dma7_descr__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK2_CLR__dma6_eop__DEFAULT -#define R_IRQ_MASK2_CLR__dma6_eop__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK2_CLR__dma6_descr__DEFAULT -#define R_IRQ_MASK2_CLR__dma6_descr__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK2_CLR__dma5_eop__DEFAULT -#define R_IRQ_MASK2_CLR__dma5_eop__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK2_CLR__dma5_descr__DEFAULT -#define R_IRQ_MASK2_CLR__dma5_descr__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK2_CLR__dma4_eop__DEFAULT -#define R_IRQ_MASK2_CLR__dma4_eop__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK2_CLR__dma4_descr__DEFAULT -#define R_IRQ_MASK2_CLR__dma4_descr__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK2_CLR__dma3_eop__DEFAULT -#define R_IRQ_MASK2_CLR__dma3_eop__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK2_CLR__dma3_descr__DEFAULT -#define R_IRQ_MASK2_CLR__dma3_descr__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK2_CLR__dma2_eop__DEFAULT -#define R_IRQ_MASK2_CLR__dma2_eop__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK2_CLR__dma2_descr__DEFAULT -#define R_IRQ_MASK2_CLR__dma2_descr__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK2_CLR__dma1_eop__DEFAULT -#define R_IRQ_MASK2_CLR__dma1_eop__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK2_CLR__dma1_descr__DEFAULT -#define R_IRQ_MASK2_CLR__dma1_descr__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK2_CLR__dma0_eop__DEFAULT -#define R_IRQ_MASK2_CLR__dma0_eop__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_IRQ_MASK2_CLR__dma0_descr__DEFAULT -#define R_IRQ_MASK2_CLR__dma0_descr__DEFAULT clr -#endif - -/* -** Default values for register R_IRQ_MASK2_SET -*/ - -/* set nop */ -#ifndef R_IRQ_MASK2_SET__dma8_sub3_descr__DEFAULT -#define R_IRQ_MASK2_SET__dma8_sub3_descr__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK2_SET__dma8_sub2_descr__DEFAULT -#define R_IRQ_MASK2_SET__dma8_sub2_descr__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK2_SET__dma8_sub1_descr__DEFAULT -#define R_IRQ_MASK2_SET__dma8_sub1_descr__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK2_SET__dma8_sub0_descr__DEFAULT -#define R_IRQ_MASK2_SET__dma8_sub0_descr__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK2_SET__dma9_eop__DEFAULT -#define R_IRQ_MASK2_SET__dma9_eop__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK2_SET__dma9_descr__DEFAULT -#define R_IRQ_MASK2_SET__dma9_descr__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK2_SET__dma8_eop__DEFAULT -#define R_IRQ_MASK2_SET__dma8_eop__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK2_SET__dma8_descr__DEFAULT -#define R_IRQ_MASK2_SET__dma8_descr__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK2_SET__dma7_eop__DEFAULT -#define R_IRQ_MASK2_SET__dma7_eop__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK2_SET__dma7_descr__DEFAULT -#define R_IRQ_MASK2_SET__dma7_descr__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK2_SET__dma6_eop__DEFAULT -#define R_IRQ_MASK2_SET__dma6_eop__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK2_SET__dma6_descr__DEFAULT -#define R_IRQ_MASK2_SET__dma6_descr__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK2_SET__dma5_eop__DEFAULT -#define R_IRQ_MASK2_SET__dma5_eop__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK2_SET__dma5_descr__DEFAULT -#define R_IRQ_MASK2_SET__dma5_descr__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK2_SET__dma4_eop__DEFAULT -#define R_IRQ_MASK2_SET__dma4_eop__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK2_SET__dma4_descr__DEFAULT -#define R_IRQ_MASK2_SET__dma4_descr__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK2_SET__dma3_eop__DEFAULT -#define R_IRQ_MASK2_SET__dma3_eop__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK2_SET__dma3_descr__DEFAULT -#define R_IRQ_MASK2_SET__dma3_descr__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK2_SET__dma2_eop__DEFAULT -#define R_IRQ_MASK2_SET__dma2_eop__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK2_SET__dma2_descr__DEFAULT -#define R_IRQ_MASK2_SET__dma2_descr__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK2_SET__dma1_eop__DEFAULT -#define R_IRQ_MASK2_SET__dma1_eop__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK2_SET__dma1_descr__DEFAULT -#define R_IRQ_MASK2_SET__dma1_descr__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK2_SET__dma0_eop__DEFAULT -#define R_IRQ_MASK2_SET__dma0_eop__DEFAULT set -#endif - -/* set nop */ -#ifndef R_IRQ_MASK2_SET__dma0_descr__DEFAULT -#define R_IRQ_MASK2_SET__dma0_descr__DEFAULT set -#endif - -/* -** Default values for register R_MMU_CONFIG -*/ - -/* disable enable */ -#ifndef R_MMU_CONFIG__mmu_enable__DEFAULT -#define R_MMU_CONFIG__mmu_enable__DEFAULT disable -#endif - -/* disable enable */ -#ifndef R_MMU_CONFIG__inv_excp__DEFAULT -#define R_MMU_CONFIG__inv_excp__DEFAULT disable -#endif - -/* disable enable */ -#ifndef R_MMU_CONFIG__acc_excp__DEFAULT -#define R_MMU_CONFIG__acc_excp__DEFAULT disable -#endif - -/* disable enable */ -#ifndef R_MMU_CONFIG__we_excp__DEFAULT -#define R_MMU_CONFIG__we_excp__DEFAULT disable -#endif - -/* page seg */ -#ifndef R_MMU_CONFIG__seg_f__DEFAULT -#define R_MMU_CONFIG__seg_f__DEFAULT page -#endif - -/* page seg */ -#ifndef R_MMU_CONFIG__seg_e__DEFAULT -#define R_MMU_CONFIG__seg_e__DEFAULT page -#endif - -/* page seg */ -#ifndef R_MMU_CONFIG__seg_d__DEFAULT -#define R_MMU_CONFIG__seg_d__DEFAULT page -#endif - -/* page seg */ -#ifndef R_MMU_CONFIG__seg_c__DEFAULT -#define R_MMU_CONFIG__seg_c__DEFAULT page -#endif - -/* page seg */ -#ifndef R_MMU_CONFIG__seg_b__DEFAULT -#define R_MMU_CONFIG__seg_b__DEFAULT page -#endif - -/* page seg */ -#ifndef R_MMU_CONFIG__seg_a__DEFAULT -#define R_MMU_CONFIG__seg_a__DEFAULT page -#endif - -/* page seg */ -#ifndef R_MMU_CONFIG__seg_9__DEFAULT -#define R_MMU_CONFIG__seg_9__DEFAULT page -#endif - -/* page seg */ -#ifndef R_MMU_CONFIG__seg_8__DEFAULT -#define R_MMU_CONFIG__seg_8__DEFAULT page -#endif - -/* page seg */ -#ifndef R_MMU_CONFIG__seg_7__DEFAULT -#define R_MMU_CONFIG__seg_7__DEFAULT page -#endif - -/* page seg */ -#ifndef R_MMU_CONFIG__seg_6__DEFAULT -#define R_MMU_CONFIG__seg_6__DEFAULT page -#endif - -/* page seg */ -#ifndef R_MMU_CONFIG__seg_5__DEFAULT -#define R_MMU_CONFIG__seg_5__DEFAULT page -#endif - -/* page seg */ -#ifndef R_MMU_CONFIG__seg_4__DEFAULT -#define R_MMU_CONFIG__seg_4__DEFAULT page -#endif - -/* page seg */ -#ifndef R_MMU_CONFIG__seg_3__DEFAULT -#define R_MMU_CONFIG__seg_3__DEFAULT page -#endif - -/* page seg */ -#ifndef R_MMU_CONFIG__seg_2__DEFAULT -#define R_MMU_CONFIG__seg_2__DEFAULT page -#endif - -/* page seg */ -#ifndef R_MMU_CONFIG__seg_1__DEFAULT -#define R_MMU_CONFIG__seg_1__DEFAULT page -#endif - -/* page seg */ -#ifndef R_MMU_CONFIG__seg_0__DEFAULT -#define R_MMU_CONFIG__seg_0__DEFAULT page -#endif - -/* -** Default values for register R_MMU_CTRL -*/ - -/* disable enable */ -#ifndef R_MMU_CTRL__inv_excp__DEFAULT -#define R_MMU_CTRL__inv_excp__DEFAULT disable -#endif - -/* disable enable */ -#ifndef R_MMU_CTRL__acc_excp__DEFAULT -#define R_MMU_CTRL__acc_excp__DEFAULT disable -#endif - -/* disable enable */ -#ifndef R_MMU_CTRL__we_excp__DEFAULT -#define R_MMU_CTRL__we_excp__DEFAULT disable -#endif - -/* -** Default values for register R_MMU_ENABLE -*/ - -/* disable enable */ -#ifndef R_MMU_ENABLE__mmu_enable__DEFAULT -#define R_MMU_ENABLE__mmu_enable__DEFAULT disable -#endif - -/* -** Default values for register R_MMU_KBASE_HI -*/ - -/* 0 - 15 */ -#ifndef R_MMU_KBASE_HI__base_f__DEFAULT -#define R_MMU_KBASE_HI__base_f__DEFAULT 0 -#endif - -/* 0 - 15 */ -#ifndef R_MMU_KBASE_HI__base_e__DEFAULT -#define R_MMU_KBASE_HI__base_e__DEFAULT 0 -#endif - -/* 0 - 15 */ -#ifndef R_MMU_KBASE_HI__base_d__DEFAULT -#define R_MMU_KBASE_HI__base_d__DEFAULT 0 -#endif - -/* 0 - 15 */ -#ifndef R_MMU_KBASE_HI__base_c__DEFAULT -#define R_MMU_KBASE_HI__base_c__DEFAULT 0 -#endif - -/* 0 - 15 */ -#ifndef R_MMU_KBASE_HI__base_b__DEFAULT -#define R_MMU_KBASE_HI__base_b__DEFAULT 0 -#endif - -/* 0 - 15 */ -#ifndef R_MMU_KBASE_HI__base_a__DEFAULT -#define R_MMU_KBASE_HI__base_a__DEFAULT 0 -#endif - -/* 0 - 15 */ -#ifndef R_MMU_KBASE_HI__base_9__DEFAULT -#define R_MMU_KBASE_HI__base_9__DEFAULT 0 -#endif - -/* 0 - 15 */ -#ifndef R_MMU_KBASE_HI__base_8__DEFAULT -#define R_MMU_KBASE_HI__base_8__DEFAULT 0 -#endif - -/* -** Default values for register R_MMU_KBASE_LO -*/ - -/* 0 - 15 */ -#ifndef R_MMU_KBASE_LO__base_7__DEFAULT -#define R_MMU_KBASE_LO__base_7__DEFAULT 0 -#endif - -/* 0 - 15 */ -#ifndef R_MMU_KBASE_LO__base_6__DEFAULT -#define R_MMU_KBASE_LO__base_6__DEFAULT 0 -#endif - -/* 0 - 15 */ -#ifndef R_MMU_KBASE_LO__base_5__DEFAULT -#define R_MMU_KBASE_LO__base_5__DEFAULT 0 -#endif - -/* 0 - 15 */ -#ifndef R_MMU_KBASE_LO__base_4__DEFAULT -#define R_MMU_KBASE_LO__base_4__DEFAULT 0 -#endif - -/* 0 - 15 */ -#ifndef R_MMU_KBASE_LO__base_3__DEFAULT -#define R_MMU_KBASE_LO__base_3__DEFAULT 0 -#endif - -/* 0 - 15 */ -#ifndef R_MMU_KBASE_LO__base_2__DEFAULT -#define R_MMU_KBASE_LO__base_2__DEFAULT 0 -#endif - -/* 0 - 15 */ -#ifndef R_MMU_KBASE_LO__base_1__DEFAULT -#define R_MMU_KBASE_LO__base_1__DEFAULT 0 -#endif - -/* 0 - 15 */ -#ifndef R_MMU_KBASE_LO__base_0__DEFAULT -#define R_MMU_KBASE_LO__base_0__DEFAULT 0 -#endif - -/* -** Default values for register R_MMU_KSEG -*/ - -/* page seg */ -#ifndef R_MMU_KSEG__seg_f__DEFAULT -#define R_MMU_KSEG__seg_f__DEFAULT page -#endif - -/* page seg */ -#ifndef R_MMU_KSEG__seg_e__DEFAULT -#define R_MMU_KSEG__seg_e__DEFAULT page -#endif - -/* page seg */ -#ifndef R_MMU_KSEG__seg_d__DEFAULT -#define R_MMU_KSEG__seg_d__DEFAULT page -#endif - -/* page seg */ -#ifndef R_MMU_KSEG__seg_c__DEFAULT -#define R_MMU_KSEG__seg_c__DEFAULT page -#endif - -/* page seg */ -#ifndef R_MMU_KSEG__seg_b__DEFAULT -#define R_MMU_KSEG__seg_b__DEFAULT page -#endif - -/* page seg */ -#ifndef R_MMU_KSEG__seg_a__DEFAULT -#define R_MMU_KSEG__seg_a__DEFAULT page -#endif - -/* page seg */ -#ifndef R_MMU_KSEG__seg_9__DEFAULT -#define R_MMU_KSEG__seg_9__DEFAULT page -#endif - -/* page seg */ -#ifndef R_MMU_KSEG__seg_8__DEFAULT -#define R_MMU_KSEG__seg_8__DEFAULT page -#endif - -/* page seg */ -#ifndef R_MMU_KSEG__seg_7__DEFAULT -#define R_MMU_KSEG__seg_7__DEFAULT page -#endif - -/* page seg */ -#ifndef R_MMU_KSEG__seg_6__DEFAULT -#define R_MMU_KSEG__seg_6__DEFAULT page -#endif - -/* page seg */ -#ifndef R_MMU_KSEG__seg_5__DEFAULT -#define R_MMU_KSEG__seg_5__DEFAULT page -#endif - -/* page seg */ -#ifndef R_MMU_KSEG__seg_4__DEFAULT -#define R_MMU_KSEG__seg_4__DEFAULT page -#endif - -/* page seg */ -#ifndef R_MMU_KSEG__seg_3__DEFAULT -#define R_MMU_KSEG__seg_3__DEFAULT page -#endif - -/* page seg */ -#ifndef R_MMU_KSEG__seg_2__DEFAULT -#define R_MMU_KSEG__seg_2__DEFAULT page -#endif - -/* page seg */ -#ifndef R_MMU_KSEG__seg_1__DEFAULT -#define R_MMU_KSEG__seg_1__DEFAULT page -#endif - -/* page seg */ -#ifndef R_MMU_KSEG__seg_0__DEFAULT -#define R_MMU_KSEG__seg_0__DEFAULT page -#endif - -/* -** Default values for register R_NETWORK_GA_0 -*/ - -/* 0 - 0xffffffff */ -#ifndef R_NETWORK_GA_0__ga_low__DEFAULT -#define R_NETWORK_GA_0__ga_low__DEFAULT 0 -#endif - -/* -** Default values for register R_NETWORK_GA_1 -*/ - -/* 0 - 0xffffffff */ -#ifndef R_NETWORK_GA_1__ga_high__DEFAULT -#define R_NETWORK_GA_1__ga_high__DEFAULT 0 -#endif - -/* -** Default values for register R_NETWORK_GEN_CONFIG -*/ - -/* off on */ -#ifndef R_NETWORK_GEN_CONFIG__loopback__DEFAULT -#define R_NETWORK_GEN_CONFIG__loopback__DEFAULT off -#endif - -/* ether tokenr */ -#ifndef R_NETWORK_GEN_CONFIG__frame__DEFAULT -#define R_NETWORK_GEN_CONFIG__frame__DEFAULT ether -#endif - -/* off on */ -#ifndef R_NETWORK_GEN_CONFIG__vg__DEFAULT -#define R_NETWORK_GEN_CONFIG__vg__DEFAULT off -#endif - -/* mii_clk sni mii_req mii_err */ -#ifndef R_NETWORK_GEN_CONFIG__phy__DEFAULT -#define R_NETWORK_GEN_CONFIG__phy__DEFAULT mii_clk -#endif - -/* off on */ -#ifndef R_NETWORK_GEN_CONFIG__enable__DEFAULT -#define R_NETWORK_GEN_CONFIG__enable__DEFAULT off -#endif - -/* -** Default values for register R_NETWORK_MGM_CTRL -*/ - -/* 0 - 0xf */ -#ifndef R_NETWORK_MGM_CTRL__txd_pins__DEFAULT -#define R_NETWORK_MGM_CTRL__txd_pins__DEFAULT 0 -#endif - -/* 0 - 0x1 */ -#ifndef R_NETWORK_MGM_CTRL__txer_pin__DEFAULT -#define R_NETWORK_MGM_CTRL__txer_pin__DEFAULT 0 -#endif - -/* 0 - 0x1 */ -#ifndef R_NETWORK_MGM_CTRL__mdck__DEFAULT -#define R_NETWORK_MGM_CTRL__mdck__DEFAULT 0 -#endif - -/* disable enable */ -#ifndef R_NETWORK_MGM_CTRL__mdoe__DEFAULT -#define R_NETWORK_MGM_CTRL__mdoe__DEFAULT disable -#endif - -/* 0 - 0x1 */ -#ifndef R_NETWORK_MGM_CTRL__mdio__DEFAULT -#define R_NETWORK_MGM_CTRL__mdio__DEFAULT 0 -#endif - -/* -** Default values for register R_NETWORK_REC_CONFIG -*/ - -/* size1518 size1522 */ -#ifndef R_NETWORK_REC_CONFIG__max_size__DEFAULT -#define R_NETWORK_REC_CONFIG__max_size__DEFAULT size1518 -#endif - -/* half full */ -#ifndef R_NETWORK_REC_CONFIG__duplex__DEFAULT -#define R_NETWORK_REC_CONFIG__duplex__DEFAULT half -#endif - -/* discard receive */ -#ifndef R_NETWORK_REC_CONFIG__bad_crc__DEFAULT -#define R_NETWORK_REC_CONFIG__bad_crc__DEFAULT discard -#endif - -/* discard receive */ -#ifndef R_NETWORK_REC_CONFIG__oversize__DEFAULT -#define R_NETWORK_REC_CONFIG__oversize__DEFAULT discard -#endif - -/* discard receive */ -#ifndef R_NETWORK_REC_CONFIG__undersize__DEFAULT -#define R_NETWORK_REC_CONFIG__undersize__DEFAULT discard -#endif - -/* discard receive */ -#ifndef R_NETWORK_REC_CONFIG__all_roots__DEFAULT -#define R_NETWORK_REC_CONFIG__all_roots__DEFAULT discard -#endif - -/* discard receive */ -#ifndef R_NETWORK_REC_CONFIG__tr_broadcast__DEFAULT -#define R_NETWORK_REC_CONFIG__tr_broadcast__DEFAULT discard -#endif - -/* discard receive */ -#ifndef R_NETWORK_REC_CONFIG__broadcast__DEFAULT -#define R_NETWORK_REC_CONFIG__broadcast__DEFAULT discard -#endif - -/* discard receive */ -#ifndef R_NETWORK_REC_CONFIG__individual__DEFAULT -#define R_NETWORK_REC_CONFIG__individual__DEFAULT discard -#endif - -/* disable enable */ -#ifndef R_NETWORK_REC_CONFIG__ma1__DEFAULT -#define R_NETWORK_REC_CONFIG__ma1__DEFAULT disable -#endif - -/* disable enable */ -#ifndef R_NETWORK_REC_CONFIG__ma0__DEFAULT -#define R_NETWORK_REC_CONFIG__ma0__DEFAULT disable -#endif - -/* -** Default values for register R_NETWORK_SA_0 -*/ - -/* 0 - 0xffffffff */ -#ifndef R_NETWORK_SA_0__ma0_low__DEFAULT -#define R_NETWORK_SA_0__ma0_low__DEFAULT 0 -#endif - -/* -** Default values for register R_NETWORK_SA_1 -*/ - -/* 0 - 0xffff */ -#ifndef R_NETWORK_SA_1__ma1_low__DEFAULT -#define R_NETWORK_SA_1__ma1_low__DEFAULT 0 -#endif - -/* 0 - 0xffff */ -#ifndef R_NETWORK_SA_1__ma0_high__DEFAULT -#define R_NETWORK_SA_1__ma0_high__DEFAULT 0 -#endif - -/* -** Default values for register R_NETWORK_SA_2 -*/ - -/* 0 - 0xffffffff */ -#ifndef R_NETWORK_SA_2__ma1_high__DEFAULT -#define R_NETWORK_SA_2__ma1_high__DEFAULT 0 -#endif - -/* -** Default values for register R_NETWORK_TR_CTRL -*/ - -/* clr nop */ -#ifndef R_NETWORK_TR_CTRL__clr_error__DEFAULT -#define R_NETWORK_TR_CTRL__clr_error__DEFAULT clr -#endif - -/* none d2us */ -#ifndef R_NETWORK_TR_CTRL__delay__DEFAULT -#define R_NETWORK_TR_CTRL__delay__DEFAULT none -#endif - -/* do dont */ -#ifndef R_NETWORK_TR_CTRL__cancel__DEFAULT -#define R_NETWORK_TR_CTRL__cancel__DEFAULT do -#endif - -/* ack_col disable ack_crs enable */ -#ifndef R_NETWORK_TR_CTRL__cd__DEFAULT -#define R_NETWORK_TR_CTRL__cd__DEFAULT ack_col -#endif - -/* disable enable */ -#ifndef R_NETWORK_TR_CTRL__retry__DEFAULT -#define R_NETWORK_TR_CTRL__retry__DEFAULT disable -#endif - -/* disable enable */ -#ifndef R_NETWORK_TR_CTRL__pad__DEFAULT -#define R_NETWORK_TR_CTRL__pad__DEFAULT disable -#endif - -/* disable enable */ -#ifndef R_NETWORK_TR_CTRL__crc__DEFAULT -#define R_NETWORK_TR_CTRL__crc__DEFAULT disable -#endif - -/* -** Default values for register R_PAR0_CONFIG -*/ - -/* noninv inv */ -#ifndef R_PAR0_CONFIG__ioe__DEFAULT -#define R_PAR0_CONFIG__ioe__DEFAULT noninv -#endif - -/* noninv inv */ -#ifndef R_PAR0_CONFIG__iseli__DEFAULT -#define R_PAR0_CONFIG__iseli__DEFAULT noninv -#endif - -/* noninv inv */ -#ifndef R_PAR0_CONFIG__iautofd__DEFAULT -#define R_PAR0_CONFIG__iautofd__DEFAULT noninv -#endif - -/* noninv inv */ -#ifndef R_PAR0_CONFIG__istrb__DEFAULT -#define R_PAR0_CONFIG__istrb__DEFAULT noninv -#endif - -/* noninv inv */ -#ifndef R_PAR0_CONFIG__iinit__DEFAULT -#define R_PAR0_CONFIG__iinit__DEFAULT noninv -#endif - -/* noninv inv */ -#ifndef R_PAR0_CONFIG__iperr__DEFAULT -#define R_PAR0_CONFIG__iperr__DEFAULT noninv -#endif - -/* noninv inv */ -#ifndef R_PAR0_CONFIG__iack__DEFAULT -#define R_PAR0_CONFIG__iack__DEFAULT noninv -#endif - -/* noninv inv */ -#ifndef R_PAR0_CONFIG__ibusy__DEFAULT -#define R_PAR0_CONFIG__ibusy__DEFAULT noninv -#endif - -/* noninv inv */ -#ifndef R_PAR0_CONFIG__ifault__DEFAULT -#define R_PAR0_CONFIG__ifault__DEFAULT noninv -#endif - -/* noninv inv */ -#ifndef R_PAR0_CONFIG__isel__DEFAULT -#define R_PAR0_CONFIG__isel__DEFAULT noninv -#endif - -/* disable enable */ -#ifndef R_PAR0_CONFIG__ext_mode__DEFAULT -#define R_PAR0_CONFIG__ext_mode__DEFAULT disable -#endif - -/* disable enable */ -#ifndef R_PAR0_CONFIG__wide__DEFAULT -#define R_PAR0_CONFIG__wide__DEFAULT disable -#endif - -/* disable enable */ -#ifndef R_PAR0_CONFIG__dma__DEFAULT -#define R_PAR0_CONFIG__dma__DEFAULT disable -#endif - -/* disable enable */ -#ifndef R_PAR0_CONFIG__rle_in__DEFAULT -#define R_PAR0_CONFIG__rle_in__DEFAULT disable -#endif - -/* disable enable */ -#ifndef R_PAR0_CONFIG__rle_out__DEFAULT -#define R_PAR0_CONFIG__rle_out__DEFAULT disable -#endif - -/* reset on */ -#ifndef R_PAR0_CONFIG__enable__DEFAULT -#define R_PAR0_CONFIG__enable__DEFAULT reset -#endif - -/* off on */ -#ifndef R_PAR0_CONFIG__force__DEFAULT -#define R_PAR0_CONFIG__force__DEFAULT off -#endif - -/* ignore wait */ -#ifndef R_PAR0_CONFIG__ign_ack__DEFAULT -#define R_PAR0_CONFIG__ign_ack__DEFAULT ignore -#endif - -/* wait_oe dont_wait epp_data epp_addr */ -#ifndef R_PAR0_CONFIG__oe_ack__DEFAULT -#define R_PAR0_CONFIG__oe_ack__DEFAULT wait_oe -#endif - -/* epp_wr3 fastbyte ecp_rev byte centronics ecp_fwd epp_rd off nibble epp_wr1 manual epp_wr2 */ -#ifndef R_PAR0_CONFIG__mode__DEFAULT -#define R_PAR0_CONFIG__mode__DEFAULT epp_wr3 -#endif - -/* -** Default values for register R_PAR0_CTRL -*/ - -/* 0 - 31 */ -#ifndef R_PAR0_CTRL__ctrl__DEFAULT -#define R_PAR0_CTRL__ctrl__DEFAULT 0 -#endif - -/* -** Default values for register R_PAR0_CTRL_DATA -*/ - -/* nop ack */ -#ifndef R_PAR0_CTRL_DATA__peri_int__DEFAULT -#define R_PAR0_CTRL_DATA__peri_int__DEFAULT nop -#endif - -/* disable enable */ -#ifndef R_PAR0_CTRL_DATA__oe__DEFAULT -#define R_PAR0_CTRL_DATA__oe__DEFAULT disable -#endif - -/* inactive active */ -#ifndef R_PAR0_CTRL_DATA__seli__DEFAULT -#define R_PAR0_CTRL_DATA__seli__DEFAULT inactive -#endif - -/* inactive active */ -#ifndef R_PAR0_CTRL_DATA__autofd__DEFAULT -#define R_PAR0_CTRL_DATA__autofd__DEFAULT inactive -#endif - -/* inactive active */ -#ifndef R_PAR0_CTRL_DATA__strb__DEFAULT -#define R_PAR0_CTRL_DATA__strb__DEFAULT inactive -#endif - -/* inactive active */ -#ifndef R_PAR0_CTRL_DATA__init__DEFAULT -#define R_PAR0_CTRL_DATA__init__DEFAULT inactive -#endif - -/* data command */ -#ifndef R_PAR0_CTRL_DATA__ecp_cmd__DEFAULT -#define R_PAR0_CTRL_DATA__ecp_cmd__DEFAULT data -#endif - -/* 0 - 0xff */ -#ifndef R_PAR0_CTRL_DATA__data__DEFAULT -#define R_PAR0_CTRL_DATA__data__DEFAULT 0 -#endif - -/* -** Default values for register R_PAR0_DELAY -*/ - -/* 0 - 0x7 */ -#ifndef R_PAR0_DELAY__fine_hold__DEFAULT -#define R_PAR0_DELAY__fine_hold__DEFAULT 0 -#endif - -/* 0 - 0x1f */ -#ifndef R_PAR0_DELAY__hold__DEFAULT -#define R_PAR0_DELAY__hold__DEFAULT 0 -#endif - -/* 0 - 0x7 */ -#ifndef R_PAR0_DELAY__fine_strb__DEFAULT -#define R_PAR0_DELAY__fine_strb__DEFAULT 0 -#endif - -/* 0 - 0x1f */ -#ifndef R_PAR0_DELAY__strobe__DEFAULT -#define R_PAR0_DELAY__strobe__DEFAULT 0 -#endif - -/* 0 - 0x7 */ -#ifndef R_PAR0_DELAY__fine_setup__DEFAULT -#define R_PAR0_DELAY__fine_setup__DEFAULT 0 -#endif - -/* 0 - 0x1f */ -#ifndef R_PAR0_DELAY__setup__DEFAULT -#define R_PAR0_DELAY__setup__DEFAULT 0 -#endif - -/* -** Default values for register R_PAR1_CONFIG -*/ - -/* noninv inv */ -#ifndef R_PAR1_CONFIG__ioe__DEFAULT -#define R_PAR1_CONFIG__ioe__DEFAULT noninv -#endif - -/* noninv inv */ -#ifndef R_PAR1_CONFIG__iseli__DEFAULT -#define R_PAR1_CONFIG__iseli__DEFAULT noninv -#endif - -/* noninv inv */ -#ifndef R_PAR1_CONFIG__iautofd__DEFAULT -#define R_PAR1_CONFIG__iautofd__DEFAULT noninv -#endif - -/* noninv inv */ -#ifndef R_PAR1_CONFIG__istrb__DEFAULT -#define R_PAR1_CONFIG__istrb__DEFAULT noninv -#endif - -/* noninv inv */ -#ifndef R_PAR1_CONFIG__iinit__DEFAULT -#define R_PAR1_CONFIG__iinit__DEFAULT noninv -#endif - -/* noninv inv */ -#ifndef R_PAR1_CONFIG__iperr__DEFAULT -#define R_PAR1_CONFIG__iperr__DEFAULT noninv -#endif - -/* noninv inv */ -#ifndef R_PAR1_CONFIG__iack__DEFAULT -#define R_PAR1_CONFIG__iack__DEFAULT noninv -#endif - -/* noninv inv */ -#ifndef R_PAR1_CONFIG__ibusy__DEFAULT -#define R_PAR1_CONFIG__ibusy__DEFAULT noninv -#endif - -/* noninv inv */ -#ifndef R_PAR1_CONFIG__ifault__DEFAULT -#define R_PAR1_CONFIG__ifault__DEFAULT noninv -#endif - -/* noninv inv */ -#ifndef R_PAR1_CONFIG__isel__DEFAULT -#define R_PAR1_CONFIG__isel__DEFAULT noninv -#endif - -/* disable enable */ -#ifndef R_PAR1_CONFIG__ext_mode__DEFAULT -#define R_PAR1_CONFIG__ext_mode__DEFAULT disable -#endif - -/* disable enable */ -#ifndef R_PAR1_CONFIG__dma__DEFAULT -#define R_PAR1_CONFIG__dma__DEFAULT disable -#endif - -/* disable enable */ -#ifndef R_PAR1_CONFIG__rle_in__DEFAULT -#define R_PAR1_CONFIG__rle_in__DEFAULT disable -#endif - -/* disable enable */ -#ifndef R_PAR1_CONFIG__rle_out__DEFAULT -#define R_PAR1_CONFIG__rle_out__DEFAULT disable -#endif - -/* reset on */ -#ifndef R_PAR1_CONFIG__enable__DEFAULT -#define R_PAR1_CONFIG__enable__DEFAULT reset -#endif - -/* off on */ -#ifndef R_PAR1_CONFIG__force__DEFAULT -#define R_PAR1_CONFIG__force__DEFAULT off -#endif - -/* ignore wait */ -#ifndef R_PAR1_CONFIG__ign_ack__DEFAULT -#define R_PAR1_CONFIG__ign_ack__DEFAULT ignore -#endif - -/* wait_oe dont_wait epp_data epp_addr */ -#ifndef R_PAR1_CONFIG__oe_ack__DEFAULT -#define R_PAR1_CONFIG__oe_ack__DEFAULT wait_oe -#endif - -/* epp_wr3 fastbyte ecp_rev byte centronics ecp_fwd epp_rd off nibble epp_wr1 manual epp_wr2 */ -#ifndef R_PAR1_CONFIG__mode__DEFAULT -#define R_PAR1_CONFIG__mode__DEFAULT epp_wr3 -#endif - -/* -** Default values for register R_PAR1_CTRL -*/ - -/* 0 - 31 */ -#ifndef R_PAR1_CTRL__ctrl__DEFAULT -#define R_PAR1_CTRL__ctrl__DEFAULT 0 -#endif - -/* -** Default values for register R_PAR1_CTRL_DATA -*/ - -/* nop ack */ -#ifndef R_PAR1_CTRL_DATA__peri_int__DEFAULT -#define R_PAR1_CTRL_DATA__peri_int__DEFAULT nop -#endif - -/* disable enable */ -#ifndef R_PAR1_CTRL_DATA__oe__DEFAULT -#define R_PAR1_CTRL_DATA__oe__DEFAULT disable -#endif - -/* inactive active */ -#ifndef R_PAR1_CTRL_DATA__seli__DEFAULT -#define R_PAR1_CTRL_DATA__seli__DEFAULT inactive -#endif - -/* inactive active */ -#ifndef R_PAR1_CTRL_DATA__autofd__DEFAULT -#define R_PAR1_CTRL_DATA__autofd__DEFAULT inactive -#endif - -/* inactive active */ -#ifndef R_PAR1_CTRL_DATA__strb__DEFAULT -#define R_PAR1_CTRL_DATA__strb__DEFAULT inactive -#endif - -/* inactive active */ -#ifndef R_PAR1_CTRL_DATA__init__DEFAULT -#define R_PAR1_CTRL_DATA__init__DEFAULT inactive -#endif - -/* data command */ -#ifndef R_PAR1_CTRL_DATA__ecp_cmd__DEFAULT -#define R_PAR1_CTRL_DATA__ecp_cmd__DEFAULT data -#endif - -/* 0 - 0xff */ -#ifndef R_PAR1_CTRL_DATA__data__DEFAULT -#define R_PAR1_CTRL_DATA__data__DEFAULT 0 -#endif - -/* -** Default values for register R_PAR1_DELAY -*/ - -/* 0 - 0x7 */ -#ifndef R_PAR1_DELAY__fine_hold__DEFAULT -#define R_PAR1_DELAY__fine_hold__DEFAULT 0 -#endif - -/* 0 - 0x1f */ -#ifndef R_PAR1_DELAY__hold__DEFAULT -#define R_PAR1_DELAY__hold__DEFAULT 0 -#endif - -/* 0 - 0x7 */ -#ifndef R_PAR1_DELAY__fine_strb__DEFAULT -#define R_PAR1_DELAY__fine_strb__DEFAULT 0 -#endif - -/* 0 - 0x1f */ -#ifndef R_PAR1_DELAY__strobe__DEFAULT -#define R_PAR1_DELAY__strobe__DEFAULT 0 -#endif - -/* 0 - 0x7 */ -#ifndef R_PAR1_DELAY__fine_setup__DEFAULT -#define R_PAR1_DELAY__fine_setup__DEFAULT 0 -#endif - -/* 0 - 0x1f */ -#ifndef R_PAR1_DELAY__setup__DEFAULT -#define R_PAR1_DELAY__setup__DEFAULT 0 -#endif - -/* -** Default values for register R_PORT_PA_DATA -*/ - -/* 0 - 255 */ -#ifndef R_PORT_PA_DATA__data_out__DEFAULT -#define R_PORT_PA_DATA__data_out__DEFAULT 0 -#endif - -/* -** Default values for register R_PORT_PA_DIR -*/ - -/* input output */ -#ifndef R_PORT_PA_DIR__dir7__DEFAULT -#define R_PORT_PA_DIR__dir7__DEFAULT input -#endif - -/* input output */ -#ifndef R_PORT_PA_DIR__dir6__DEFAULT -#define R_PORT_PA_DIR__dir6__DEFAULT input -#endif - -/* input output */ -#ifndef R_PORT_PA_DIR__dir5__DEFAULT -#define R_PORT_PA_DIR__dir5__DEFAULT input -#endif - -/* input output */ -#ifndef R_PORT_PA_DIR__dir4__DEFAULT -#define R_PORT_PA_DIR__dir4__DEFAULT input -#endif - -/* input output */ -#ifndef R_PORT_PA_DIR__dir3__DEFAULT -#define R_PORT_PA_DIR__dir3__DEFAULT input -#endif - -/* input output */ -#ifndef R_PORT_PA_DIR__dir2__DEFAULT -#define R_PORT_PA_DIR__dir2__DEFAULT input -#endif - -/* input output */ -#ifndef R_PORT_PA_DIR__dir1__DEFAULT -#define R_PORT_PA_DIR__dir1__DEFAULT input -#endif - -/* input output */ -#ifndef R_PORT_PA_DIR__dir0__DEFAULT -#define R_PORT_PA_DIR__dir0__DEFAULT input -#endif - -/* -** Default values for register R_PORT_PA_SET -*/ - -/* input output */ -#ifndef R_PORT_PA_SET__dir7__DEFAULT -#define R_PORT_PA_SET__dir7__DEFAULT input -#endif - -/* input output */ -#ifndef R_PORT_PA_SET__dir6__DEFAULT -#define R_PORT_PA_SET__dir6__DEFAULT input -#endif - -/* input output */ -#ifndef R_PORT_PA_SET__dir5__DEFAULT -#define R_PORT_PA_SET__dir5__DEFAULT input -#endif - -/* input output */ -#ifndef R_PORT_PA_SET__dir4__DEFAULT -#define R_PORT_PA_SET__dir4__DEFAULT input -#endif - -/* input output */ -#ifndef R_PORT_PA_SET__dir3__DEFAULT -#define R_PORT_PA_SET__dir3__DEFAULT input -#endif - -/* input output */ -#ifndef R_PORT_PA_SET__dir2__DEFAULT -#define R_PORT_PA_SET__dir2__DEFAULT input -#endif - -/* input output */ -#ifndef R_PORT_PA_SET__dir1__DEFAULT -#define R_PORT_PA_SET__dir1__DEFAULT input -#endif - -/* input output */ -#ifndef R_PORT_PA_SET__dir0__DEFAULT -#define R_PORT_PA_SET__dir0__DEFAULT input -#endif - -/* 0 - 255 */ -#ifndef R_PORT_PA_SET__data_out__DEFAULT -#define R_PORT_PA_SET__data_out__DEFAULT 0 -#endif - -/* -** Default values for register R_PORT_PB_CONFIG -*/ - -/* port cs */ -#ifndef R_PORT_PB_CONFIG__cs7__DEFAULT -#define R_PORT_PB_CONFIG__cs7__DEFAULT port -#endif - -/* port cs */ -#ifndef R_PORT_PB_CONFIG__cs6__DEFAULT -#define R_PORT_PB_CONFIG__cs6__DEFAULT port -#endif - -/* port cs */ -#ifndef R_PORT_PB_CONFIG__cs5__DEFAULT -#define R_PORT_PB_CONFIG__cs5__DEFAULT port -#endif - -/* port cs */ -#ifndef R_PORT_PB_CONFIG__cs4__DEFAULT -#define R_PORT_PB_CONFIG__cs4__DEFAULT port -#endif - -/* port cs */ -#ifndef R_PORT_PB_CONFIG__cs3__DEFAULT -#define R_PORT_PB_CONFIG__cs3__DEFAULT port -#endif - -/* port cs */ -#ifndef R_PORT_PB_CONFIG__cs2__DEFAULT -#define R_PORT_PB_CONFIG__cs2__DEFAULT port -#endif - -/* port_cs enph */ -#ifndef R_PORT_PB_CONFIG__scsi1__DEFAULT -#define R_PORT_PB_CONFIG__scsi1__DEFAULT port_cs -#endif - -/* port_cs enph */ -#ifndef R_PORT_PB_CONFIG__scsi0__DEFAULT -#define R_PORT_PB_CONFIG__scsi0__DEFAULT port_cs -#endif - -/* -** Default values for register R_PORT_PB_DATA -*/ - -/* 0 - 255 */ -#ifndef R_PORT_PB_DATA__data_out__DEFAULT -#define R_PORT_PB_DATA__data_out__DEFAULT 0 -#endif - -/* -** Default values for register R_PORT_PB_DIR -*/ - -/* input output */ -#ifndef R_PORT_PB_DIR__dir7__DEFAULT -#define R_PORT_PB_DIR__dir7__DEFAULT input -#endif - -/* input output */ -#ifndef R_PORT_PB_DIR__dir6__DEFAULT -#define R_PORT_PB_DIR__dir6__DEFAULT input -#endif - -/* input output */ -#ifndef R_PORT_PB_DIR__dir5__DEFAULT -#define R_PORT_PB_DIR__dir5__DEFAULT input -#endif - -/* input output */ -#ifndef R_PORT_PB_DIR__dir4__DEFAULT -#define R_PORT_PB_DIR__dir4__DEFAULT input -#endif - -/* input output */ -#ifndef R_PORT_PB_DIR__dir3__DEFAULT -#define R_PORT_PB_DIR__dir3__DEFAULT input -#endif - -/* input output */ -#ifndef R_PORT_PB_DIR__dir2__DEFAULT -#define R_PORT_PB_DIR__dir2__DEFAULT input -#endif - -/* input output */ -#ifndef R_PORT_PB_DIR__dir1__DEFAULT -#define R_PORT_PB_DIR__dir1__DEFAULT input -#endif - -/* input output */ -#ifndef R_PORT_PB_DIR__dir0__DEFAULT -#define R_PORT_PB_DIR__dir0__DEFAULT input -#endif - -/* -** Default values for register R_PORT_PB_I2C -*/ - -/* port_cs ss3extra */ -#ifndef R_PORT_PB_I2C__syncser3__DEFAULT -#define R_PORT_PB_I2C__syncser3__DEFAULT port_cs -#endif - -/* port_cs ss1extra */ -#ifndef R_PORT_PB_I2C__syncser1__DEFAULT -#define R_PORT_PB_I2C__syncser1__DEFAULT port_cs -#endif - -/* off on */ -#ifndef R_PORT_PB_I2C__i2c_en__DEFAULT -#define R_PORT_PB_I2C__i2c_en__DEFAULT off -#endif - -/* 0 - 1 */ -#ifndef R_PORT_PB_I2C__i2c_d__DEFAULT -#define R_PORT_PB_I2C__i2c_d__DEFAULT 0 -#endif - -/* 0 - 1 */ -#ifndef R_PORT_PB_I2C__i2c_clk__DEFAULT -#define R_PORT_PB_I2C__i2c_clk__DEFAULT 0 -#endif - -/* disable enable */ -#ifndef R_PORT_PB_I2C__i2c_oe___DEFAULT -#define R_PORT_PB_I2C__i2c_oe___DEFAULT disable -#endif - -/* -** Default values for register R_PORT_PB_SET -*/ - -/* port_cs ss3extra */ -#ifndef R_PORT_PB_SET__syncser3__DEFAULT -#define R_PORT_PB_SET__syncser3__DEFAULT port_cs -#endif - -/* port_cs ss1extra */ -#ifndef R_PORT_PB_SET__syncser1__DEFAULT -#define R_PORT_PB_SET__syncser1__DEFAULT port_cs -#endif - -/* off on */ -#ifndef R_PORT_PB_SET__i2c_en__DEFAULT -#define R_PORT_PB_SET__i2c_en__DEFAULT off -#endif - -/* 0 - 1 */ -#ifndef R_PORT_PB_SET__i2c_d__DEFAULT -#define R_PORT_PB_SET__i2c_d__DEFAULT 0 -#endif - -/* 0 - 1 */ -#ifndef R_PORT_PB_SET__i2c_clk__DEFAULT -#define R_PORT_PB_SET__i2c_clk__DEFAULT 0 -#endif - -/* disable enable */ -#ifndef R_PORT_PB_SET__i2c_oe___DEFAULT -#define R_PORT_PB_SET__i2c_oe___DEFAULT disable -#endif - -/* port cs */ -#ifndef R_PORT_PB_SET__cs7__DEFAULT -#define R_PORT_PB_SET__cs7__DEFAULT port -#endif - -/* port cs */ -#ifndef R_PORT_PB_SET__cs6__DEFAULT -#define R_PORT_PB_SET__cs6__DEFAULT port -#endif - -/* port cs */ -#ifndef R_PORT_PB_SET__cs5__DEFAULT -#define R_PORT_PB_SET__cs5__DEFAULT port -#endif - -/* port cs */ -#ifndef R_PORT_PB_SET__cs4__DEFAULT -#define R_PORT_PB_SET__cs4__DEFAULT port -#endif - -/* port cs */ -#ifndef R_PORT_PB_SET__cs3__DEFAULT -#define R_PORT_PB_SET__cs3__DEFAULT port -#endif - -/* port cs */ -#ifndef R_PORT_PB_SET__cs2__DEFAULT -#define R_PORT_PB_SET__cs2__DEFAULT port -#endif - -/* port_cs enph */ -#ifndef R_PORT_PB_SET__scsi1__DEFAULT -#define R_PORT_PB_SET__scsi1__DEFAULT port_cs -#endif - -/* port_cs enph */ -#ifndef R_PORT_PB_SET__scsi0__DEFAULT -#define R_PORT_PB_SET__scsi0__DEFAULT port_cs -#endif - -/* input output */ -#ifndef R_PORT_PB_SET__dir7__DEFAULT -#define R_PORT_PB_SET__dir7__DEFAULT input -#endif - -/* input output */ -#ifndef R_PORT_PB_SET__dir6__DEFAULT -#define R_PORT_PB_SET__dir6__DEFAULT input -#endif - -/* input output */ -#ifndef R_PORT_PB_SET__dir5__DEFAULT -#define R_PORT_PB_SET__dir5__DEFAULT input -#endif - -/* input output */ -#ifndef R_PORT_PB_SET__dir4__DEFAULT -#define R_PORT_PB_SET__dir4__DEFAULT input -#endif - -/* input output */ -#ifndef R_PORT_PB_SET__dir3__DEFAULT -#define R_PORT_PB_SET__dir3__DEFAULT input -#endif - -/* input output */ -#ifndef R_PORT_PB_SET__dir2__DEFAULT -#define R_PORT_PB_SET__dir2__DEFAULT input -#endif - -/* input output */ -#ifndef R_PORT_PB_SET__dir1__DEFAULT -#define R_PORT_PB_SET__dir1__DEFAULT input -#endif - -/* input output */ -#ifndef R_PORT_PB_SET__dir0__DEFAULT -#define R_PORT_PB_SET__dir0__DEFAULT input -#endif - -/* 0 - 255 */ -#ifndef R_PORT_PB_SET__data_out__DEFAULT -#define R_PORT_PB_SET__data_out__DEFAULT 0 -#endif - -/* -** Default values for register R_SCSI0_CMD -*/ - -/* 0 - 0xf */ -#ifndef R_SCSI0_CMD__asynch_setup__DEFAULT -#define R_SCSI0_CMD__asynch_setup__DEFAULT 0 -#endif - -/* full_stat_3 full_dout_3 man_rat resel_din arb_only resel_stat resel_dout man_data_in man_data_out full_din_1 full_dout_1 full_stat_1 full_din_3 */ -#ifndef R_SCSI0_CMD__command__DEFAULT -#define R_SCSI0_CMD__command__DEFAULT full_stat_3 -#endif - -/* -** Default values for register R_SCSI0_CMD_DATA -*/ - -/* off on */ -#ifndef R_SCSI0_CMD_DATA__parity_in__DEFAULT -#define R_SCSI0_CMD_DATA__parity_in__DEFAULT off -#endif - -/* off on */ -#ifndef R_SCSI0_CMD_DATA__skip__DEFAULT -#define R_SCSI0_CMD_DATA__skip__DEFAULT off -#endif - -/* yes nop */ -#ifndef R_SCSI0_CMD_DATA__clr_status__DEFAULT -#define R_SCSI0_CMD_DATA__clr_status__DEFAULT yes -#endif - -/* 0 - 0xf */ -#ifndef R_SCSI0_CMD_DATA__asynch_setup__DEFAULT -#define R_SCSI0_CMD_DATA__asynch_setup__DEFAULT 0 -#endif - -/* full_stat_3 full_dout_3 man_rat resel_din arb_only resel_stat resel_dout man_data_in man_data_out full_din_1 full_dout_1 full_stat_1 full_din_3 */ -#ifndef R_SCSI0_CMD_DATA__command__DEFAULT -#define R_SCSI0_CMD_DATA__command__DEFAULT full_stat_3 -#endif - -/* 0 - 0xffff */ -#ifndef R_SCSI0_CMD_DATA__data_out__DEFAULT -#define R_SCSI0_CMD_DATA__data_out__DEFAULT 0 -#endif - -/* -** Default values for register R_SCSI0_CTRL -*/ - -/* software hardware */ -#ifndef R_SCSI0_CTRL__id_type__DEFAULT -#define R_SCSI0_CTRL__id_type__DEFAULT software -#endif - -/* 0 - 0x7f */ -#ifndef R_SCSI0_CTRL__sel_timeout__DEFAULT -#define R_SCSI0_CTRL__sel_timeout__DEFAULT 0 -#endif - -/* 0 - 0xff */ -#ifndef R_SCSI0_CTRL__synch_per__DEFAULT -#define R_SCSI0_CTRL__synch_per__DEFAULT 0 -#endif - -/* yes no */ -#ifndef R_SCSI0_CTRL__rst__DEFAULT -#define R_SCSI0_CTRL__rst__DEFAULT yes -#endif - -/* yes no */ -#ifndef R_SCSI0_CTRL__atn__DEFAULT -#define R_SCSI0_CTRL__atn__DEFAULT yes -#endif - -/* 0 - 0xf */ -#ifndef R_SCSI0_CTRL__my_id__DEFAULT -#define R_SCSI0_CTRL__my_id__DEFAULT 0 -#endif - -/* 0 - 0xf */ -#ifndef R_SCSI0_CTRL__target_id__DEFAULT -#define R_SCSI0_CTRL__target_id__DEFAULT 0 -#endif - -/* yes no */ -#ifndef R_SCSI0_CTRL__fast_20__DEFAULT -#define R_SCSI0_CTRL__fast_20__DEFAULT yes -#endif - -/* narrow wide */ -#ifndef R_SCSI0_CTRL__bus_width__DEFAULT -#define R_SCSI0_CTRL__bus_width__DEFAULT narrow -#endif - -/* synch asynch */ -#ifndef R_SCSI0_CTRL__synch__DEFAULT -#define R_SCSI0_CTRL__synch__DEFAULT synch -#endif - -/* off on */ -#ifndef R_SCSI0_CTRL__enable__DEFAULT -#define R_SCSI0_CTRL__enable__DEFAULT off -#endif - -/* -** Default values for register R_SCSI0_DATA -*/ - -/* 0 - 0xffff */ -#ifndef R_SCSI0_DATA__data_out__DEFAULT -#define R_SCSI0_DATA__data_out__DEFAULT 0 -#endif - -/* -** Default values for register R_SCSI0_STATUS_CTRL -*/ - -/* off on */ -#ifndef R_SCSI0_STATUS_CTRL__parity_in__DEFAULT -#define R_SCSI0_STATUS_CTRL__parity_in__DEFAULT off -#endif - -/* off on */ -#ifndef R_SCSI0_STATUS_CTRL__skip__DEFAULT -#define R_SCSI0_STATUS_CTRL__skip__DEFAULT off -#endif - -/* yes nop */ -#ifndef R_SCSI0_STATUS_CTRL__clr_status__DEFAULT -#define R_SCSI0_STATUS_CTRL__clr_status__DEFAULT yes -#endif - -/* -** Default values for register R_SCSI1_CMD -*/ - -/* 0 - 0xf */ -#ifndef R_SCSI1_CMD__asynch_setup__DEFAULT -#define R_SCSI1_CMD__asynch_setup__DEFAULT 0 -#endif - -/* full_stat_3 full_dout_3 man_rat resel_din arb_only resel_stat resel_dout man_data_in man_data_out full_din_1 full_dout_1 full_stat_1 full_din_3 */ -#ifndef R_SCSI1_CMD__command__DEFAULT -#define R_SCSI1_CMD__command__DEFAULT full_stat_3 -#endif - -/* -** Default values for register R_SCSI1_CMD_DATA -*/ - -/* off on */ -#ifndef R_SCSI1_CMD_DATA__parity_in__DEFAULT -#define R_SCSI1_CMD_DATA__parity_in__DEFAULT off -#endif - -/* off on */ -#ifndef R_SCSI1_CMD_DATA__skip__DEFAULT -#define R_SCSI1_CMD_DATA__skip__DEFAULT off -#endif - -/* yes nop */ -#ifndef R_SCSI1_CMD_DATA__clr_status__DEFAULT -#define R_SCSI1_CMD_DATA__clr_status__DEFAULT yes -#endif - -/* 0 - 0xf */ -#ifndef R_SCSI1_CMD_DATA__asynch_setup__DEFAULT -#define R_SCSI1_CMD_DATA__asynch_setup__DEFAULT 0 -#endif - -/* full_stat_3 full_dout_3 man_rat resel_din arb_only resel_stat resel_dout man_data_in man_data_out full_din_1 full_dout_1 full_stat_1 full_din_3 */ -#ifndef R_SCSI1_CMD_DATA__command__DEFAULT -#define R_SCSI1_CMD_DATA__command__DEFAULT full_stat_3 -#endif - -/* 0 - 0xffff */ -#ifndef R_SCSI1_CMD_DATA__data_out__DEFAULT -#define R_SCSI1_CMD_DATA__data_out__DEFAULT 0 -#endif - -/* -** Default values for register R_SCSI1_CTRL -*/ - -/* software hardware */ -#ifndef R_SCSI1_CTRL__id_type__DEFAULT -#define R_SCSI1_CTRL__id_type__DEFAULT software -#endif - -/* 0 - 0x7f */ -#ifndef R_SCSI1_CTRL__sel_timeout__DEFAULT -#define R_SCSI1_CTRL__sel_timeout__DEFAULT 0 -#endif - -/* 0 - 0xff */ -#ifndef R_SCSI1_CTRL__synch_per__DEFAULT -#define R_SCSI1_CTRL__synch_per__DEFAULT 0 -#endif - -/* yes no */ -#ifndef R_SCSI1_CTRL__rst__DEFAULT -#define R_SCSI1_CTRL__rst__DEFAULT yes -#endif - -/* yes no */ -#ifndef R_SCSI1_CTRL__atn__DEFAULT -#define R_SCSI1_CTRL__atn__DEFAULT yes -#endif - -/* 0 - 0xf */ -#ifndef R_SCSI1_CTRL__my_id__DEFAULT -#define R_SCSI1_CTRL__my_id__DEFAULT 0 -#endif - -/* 0 - 0xf */ -#ifndef R_SCSI1_CTRL__target_id__DEFAULT -#define R_SCSI1_CTRL__target_id__DEFAULT 0 -#endif - -/* yes no */ -#ifndef R_SCSI1_CTRL__fast_20__DEFAULT -#define R_SCSI1_CTRL__fast_20__DEFAULT yes -#endif - -/* narrow wide */ -#ifndef R_SCSI1_CTRL__bus_width__DEFAULT -#define R_SCSI1_CTRL__bus_width__DEFAULT narrow -#endif - -/* synch asynch */ -#ifndef R_SCSI1_CTRL__synch__DEFAULT -#define R_SCSI1_CTRL__synch__DEFAULT synch -#endif - -/* off on */ -#ifndef R_SCSI1_CTRL__enable__DEFAULT -#define R_SCSI1_CTRL__enable__DEFAULT off -#endif - -/* -** Default values for register R_SCSI1_DATA -*/ - -/* 0 - 0xffff */ -#ifndef R_SCSI1_DATA__data_out__DEFAULT -#define R_SCSI1_DATA__data_out__DEFAULT 0 -#endif - -/* -** Default values for register R_SCSI1_STATUS_CTRL -*/ - -/* off on */ -#ifndef R_SCSI1_STATUS_CTRL__parity_in__DEFAULT -#define R_SCSI1_STATUS_CTRL__parity_in__DEFAULT off -#endif - -/* off on */ -#ifndef R_SCSI1_STATUS_CTRL__skip__DEFAULT -#define R_SCSI1_STATUS_CTRL__skip__DEFAULT off -#endif - -/* yes nop */ -#ifndef R_SCSI1_STATUS_CTRL__clr_status__DEFAULT -#define R_SCSI1_STATUS_CTRL__clr_status__DEFAULT yes -#endif - -/* -** Default values for register R_SDRAM_CONFIG -*/ - -/* wmm norm */ -#ifndef R_SDRAM_CONFIG__wmm1__DEFAULT -#define R_SDRAM_CONFIG__wmm1__DEFAULT wmm -#endif - -/* wmm norm */ -#ifndef R_SDRAM_CONFIG__wmm0__DEFAULT -#define R_SDRAM_CONFIG__wmm0__DEFAULT wmm -#endif - -/* 0 - 7 */ -#ifndef R_SDRAM_CONFIG__sh1__DEFAULT -#define R_SDRAM_CONFIG__sh1__DEFAULT 0 -#endif - -/* 0 - 7 */ -#ifndef R_SDRAM_CONFIG__sh0__DEFAULT -#define R_SDRAM_CONFIG__sh0__DEFAULT 0 -#endif - -/* bw16 bw32 */ -#ifndef R_SDRAM_CONFIG__w__DEFAULT -#define R_SDRAM_CONFIG__w__DEFAULT bw16 -#endif - -/* bank4 bank2 */ -#ifndef R_SDRAM_CONFIG__type1__DEFAULT -#define R_SDRAM_CONFIG__type1__DEFAULT bank4 -#endif - -/* bank4 bank2 */ -#ifndef R_SDRAM_CONFIG__type0__DEFAULT -#define R_SDRAM_CONFIG__type0__DEFAULT bank4 -#endif - -/* bit10 bit20 bit11 bit21 bit12 bit22 bit13 bit23 bit14 bit24 bit15 bit25 bit16 bit26 bit17 bit27 bit18 bit9 bit28 bit19 grp0 bit29 grp1 */ -#ifndef R_SDRAM_CONFIG__group_sel__DEFAULT -#define R_SDRAM_CONFIG__group_sel__DEFAULT bit10 -#endif - -/* 0 - 7 */ -#ifndef R_SDRAM_CONFIG__ca1__DEFAULT -#define R_SDRAM_CONFIG__ca1__DEFAULT 0 -#endif - -/* bit10 bit20 bit11 bit21 bit12 bit22 bit13 bit23 bit14 bit24 bit15 bit25 bit16 bit26 bit17 bit27 bit18 bit28 bit19 bit29 bit9 */ -#ifndef R_SDRAM_CONFIG__bank_sel1__DEFAULT -#define R_SDRAM_CONFIG__bank_sel1__DEFAULT bit10 -#endif - -/* 0 - 7 */ -#ifndef R_SDRAM_CONFIG__ca0__DEFAULT -#define R_SDRAM_CONFIG__ca0__DEFAULT 0 -#endif - -/* bit10 bit20 bit11 bit21 bit12 bit22 bit13 bit23 bit14 bit24 bit15 bit25 bit16 bit26 bit17 bit27 bit18 bit28 bit19 bit29 bit9 */ -#ifndef R_SDRAM_CONFIG__bank_sel0__DEFAULT -#define R_SDRAM_CONFIG__bank_sel0__DEFAULT bit10 -#endif - -/* -** Default values for register R_SDRAM_TIMING -*/ - -/* disable enable */ -#ifndef R_SDRAM_TIMING__sdram__DEFAULT -#define R_SDRAM_TIMING__sdram__DEFAULT disable -#endif - -/* 0 - 0x7fff */ -#ifndef R_SDRAM_TIMING__mrs_data__DEFAULT -#define R_SDRAM_TIMING__mrs_data__DEFAULT 0 -#endif - -/* e6500ns e13us disable e52us */ -#ifndef R_SDRAM_TIMING__ref__DEFAULT -#define R_SDRAM_TIMING__ref__DEFAULT e6500ns -#endif - -/* off on */ -#ifndef R_SDRAM_TIMING__ddr__DEFAULT -#define R_SDRAM_TIMING__ddr__DEFAULT off -#endif - -/* off on */ -#ifndef R_SDRAM_TIMING__clk100__DEFAULT -#define R_SDRAM_TIMING__clk100__DEFAULT off -#endif - -/* off on */ -#ifndef R_SDRAM_TIMING__ps__DEFAULT -#define R_SDRAM_TIMING__ps__DEFAULT off -#endif - -/* mrs nop ref pre */ -#ifndef R_SDRAM_TIMING__cmd__DEFAULT -#define R_SDRAM_TIMING__cmd__DEFAULT mrs -#endif - -/* 0 - 1 */ -#ifndef R_SDRAM_TIMING__pde__DEFAULT -#define R_SDRAM_TIMING__pde__DEFAULT 0 -#endif - -/* 0 - 3 */ -#ifndef R_SDRAM_TIMING__rc__DEFAULT -#define R_SDRAM_TIMING__rc__DEFAULT 0 -#endif - -/* 0 - 3 */ -#ifndef R_SDRAM_TIMING__rp__DEFAULT -#define R_SDRAM_TIMING__rp__DEFAULT 0 -#endif - -/* 0 - 3 */ -#ifndef R_SDRAM_TIMING__rcd__DEFAULT -#define R_SDRAM_TIMING__rcd__DEFAULT 0 -#endif - -/* 0 - 2 */ -#ifndef R_SDRAM_TIMING__cl__DEFAULT -#define R_SDRAM_TIMING__cl__DEFAULT 0 -#endif - -/* -** Default values for register R_SERIAL0_BAUD -*/ - -/* c4800Hz c1843k2Hz c921k6Hz c460k8Hz c57k6Hz c9600Hz c300Hz c1200Hz c230k4Hz c115k2Hz c600Hz c2400Hz c19k2Hz c6250kHz c38k4Hz */ -#ifndef R_SERIAL0_BAUD__tr_baud__DEFAULT -#define R_SERIAL0_BAUD__tr_baud__DEFAULT c4800Hz -#endif - -/* c4800Hz c1843k2Hz c921k6Hz c460k8Hz c57k6Hz c9600Hz c300Hz c1200Hz c230k4Hz c115k2Hz c600Hz c2400Hz c19k2Hz c6250kHz c38k4Hz */ -#ifndef R_SERIAL0_BAUD__rec_baud__DEFAULT -#define R_SERIAL0_BAUD__rec_baud__DEFAULT c4800Hz -#endif - -/* -** Default values for register R_SERIAL0_CTRL -*/ - -/* c4800Hz c1843k2Hz c921k6Hz c460k8Hz c57k6Hz c9600Hz c300Hz c1200Hz c230k4Hz c115k2Hz c600Hz c2400Hz c19k2Hz c6250kHz c38k4Hz */ -#ifndef R_SERIAL0_CTRL__tr_baud__DEFAULT -#define R_SERIAL0_CTRL__tr_baud__DEFAULT c4800Hz -#endif - -/* c4800Hz c1843k2Hz c921k6Hz c460k8Hz c57k6Hz c9600Hz c300Hz c1200Hz c230k4Hz c115k2Hz c600Hz c2400Hz c19k2Hz c6250kHz c38k4Hz */ -#ifndef R_SERIAL0_CTRL__rec_baud__DEFAULT -#define R_SERIAL0_CTRL__rec_baud__DEFAULT c4800Hz -#endif - -/* ignore stop */ -#ifndef R_SERIAL0_CTRL__dma_err__DEFAULT -#define R_SERIAL0_CTRL__dma_err__DEFAULT ignore -#endif - -/* disable enable */ -#ifndef R_SERIAL0_CTRL__rec_enable__DEFAULT -#define R_SERIAL0_CTRL__rec_enable__DEFAULT disable -#endif - -/* inactive active */ -#ifndef R_SERIAL0_CTRL__rts___DEFAULT -#define R_SERIAL0_CTRL__rts___DEFAULT inactive -#endif - -/* majority middle */ -#ifndef R_SERIAL0_CTRL__sampling__DEFAULT -#define R_SERIAL0_CTRL__sampling__DEFAULT majority -#endif - -/* normal stick */ -#ifndef R_SERIAL0_CTRL__rec_stick_par__DEFAULT -#define R_SERIAL0_CTRL__rec_stick_par__DEFAULT normal -#endif - -/* even odd */ -#ifndef R_SERIAL0_CTRL__rec_par__DEFAULT -#define R_SERIAL0_CTRL__rec_par__DEFAULT even -#endif - -/* disable enable */ -#ifndef R_SERIAL0_CTRL__rec_par_en__DEFAULT -#define R_SERIAL0_CTRL__rec_par_en__DEFAULT disable -#endif - -/* rec_8bit rec_7bit */ -#ifndef R_SERIAL0_CTRL__rec_bitnr__DEFAULT -#define R_SERIAL0_CTRL__rec_bitnr__DEFAULT rec_8bit -#endif - -/* 0 - 0x1 */ -#ifndef R_SERIAL0_CTRL__txd__DEFAULT -#define R_SERIAL0_CTRL__txd__DEFAULT 0 -#endif - -/* disable enable */ -#ifndef R_SERIAL0_CTRL__tr_enable__DEFAULT -#define R_SERIAL0_CTRL__tr_enable__DEFAULT disable -#endif - -/* disabled active */ -#ifndef R_SERIAL0_CTRL__auto_cts__DEFAULT -#define R_SERIAL0_CTRL__auto_cts__DEFAULT disabled -#endif - -/* one_bit two_bits */ -#ifndef R_SERIAL0_CTRL__stop_bits__DEFAULT -#define R_SERIAL0_CTRL__stop_bits__DEFAULT one_bit -#endif - -/* normal stick */ -#ifndef R_SERIAL0_CTRL__tr_stick_par__DEFAULT -#define R_SERIAL0_CTRL__tr_stick_par__DEFAULT normal -#endif - -/* even odd */ -#ifndef R_SERIAL0_CTRL__tr_par__DEFAULT -#define R_SERIAL0_CTRL__tr_par__DEFAULT even -#endif - -/* disable enable */ -#ifndef R_SERIAL0_CTRL__tr_par_en__DEFAULT -#define R_SERIAL0_CTRL__tr_par_en__DEFAULT disable -#endif - -/* tr_7bit tr_8bit */ -#ifndef R_SERIAL0_CTRL__tr_bitnr__DEFAULT -#define R_SERIAL0_CTRL__tr_bitnr__DEFAULT tr_7bit -#endif - -/* 0 - 0xff */ -#ifndef R_SERIAL0_CTRL__data_out__DEFAULT -#define R_SERIAL0_CTRL__data_out__DEFAULT 0 -#endif - -/* -** Default values for register R_SERIAL0_REC_CTRL -*/ - -/* ignore stop */ -#ifndef R_SERIAL0_REC_CTRL__dma_err__DEFAULT -#define R_SERIAL0_REC_CTRL__dma_err__DEFAULT ignore -#endif - -/* disable enable */ -#ifndef R_SERIAL0_REC_CTRL__rec_enable__DEFAULT -#define R_SERIAL0_REC_CTRL__rec_enable__DEFAULT disable -#endif - -/* inactive active */ -#ifndef R_SERIAL0_REC_CTRL__rts___DEFAULT -#define R_SERIAL0_REC_CTRL__rts___DEFAULT inactive -#endif - -/* majority middle */ -#ifndef R_SERIAL0_REC_CTRL__sampling__DEFAULT -#define R_SERIAL0_REC_CTRL__sampling__DEFAULT majority -#endif - -/* normal stick */ -#ifndef R_SERIAL0_REC_CTRL__rec_stick_par__DEFAULT -#define R_SERIAL0_REC_CTRL__rec_stick_par__DEFAULT normal -#endif - -/* even odd */ -#ifndef R_SERIAL0_REC_CTRL__rec_par__DEFAULT -#define R_SERIAL0_REC_CTRL__rec_par__DEFAULT even -#endif - -/* disable enable */ -#ifndef R_SERIAL0_REC_CTRL__rec_par_en__DEFAULT -#define R_SERIAL0_REC_CTRL__rec_par_en__DEFAULT disable -#endif - -/* rec_8bit rec_7bit */ -#ifndef R_SERIAL0_REC_CTRL__rec_bitnr__DEFAULT -#define R_SERIAL0_REC_CTRL__rec_bitnr__DEFAULT rec_8bit -#endif - -/* -** Default values for register R_SERIAL0_TR_CTRL -*/ - -/* 0 - 0x1 */ -#ifndef R_SERIAL0_TR_CTRL__txd__DEFAULT -#define R_SERIAL0_TR_CTRL__txd__DEFAULT 0 -#endif - -/* disable enable */ -#ifndef R_SERIAL0_TR_CTRL__tr_enable__DEFAULT -#define R_SERIAL0_TR_CTRL__tr_enable__DEFAULT disable -#endif - -/* disabled active */ -#ifndef R_SERIAL0_TR_CTRL__auto_cts__DEFAULT -#define R_SERIAL0_TR_CTRL__auto_cts__DEFAULT disabled -#endif - -/* one_bit two_bits */ -#ifndef R_SERIAL0_TR_CTRL__stop_bits__DEFAULT -#define R_SERIAL0_TR_CTRL__stop_bits__DEFAULT one_bit -#endif - -/* normal stick */ -#ifndef R_SERIAL0_TR_CTRL__tr_stick_par__DEFAULT -#define R_SERIAL0_TR_CTRL__tr_stick_par__DEFAULT normal -#endif - -/* even odd */ -#ifndef R_SERIAL0_TR_CTRL__tr_par__DEFAULT -#define R_SERIAL0_TR_CTRL__tr_par__DEFAULT even -#endif - -/* disable enable */ -#ifndef R_SERIAL0_TR_CTRL__tr_par_en__DEFAULT -#define R_SERIAL0_TR_CTRL__tr_par_en__DEFAULT disable -#endif - -/* tr_7bit tr_8bit */ -#ifndef R_SERIAL0_TR_CTRL__tr_bitnr__DEFAULT -#define R_SERIAL0_TR_CTRL__tr_bitnr__DEFAULT tr_7bit -#endif - -/* -** Default values for register R_SERIAL0_TR_DATA -*/ - -/* 0 - 0xff */ -#ifndef R_SERIAL0_TR_DATA__data_out__DEFAULT -#define R_SERIAL0_TR_DATA__data_out__DEFAULT 0 -#endif - -/* -** Default values for register R_SERIAL0_XOFF -*/ - -/* stop enable */ -#ifndef R_SERIAL0_XOFF__tx_stop__DEFAULT -#define R_SERIAL0_XOFF__tx_stop__DEFAULT stop -#endif - -/* disable enable */ -#ifndef R_SERIAL0_XOFF__auto_xoff__DEFAULT -#define R_SERIAL0_XOFF__auto_xoff__DEFAULT disable -#endif - -/* 0 - 0xff */ -#ifndef R_SERIAL0_XOFF__xoff_char__DEFAULT -#define R_SERIAL0_XOFF__xoff_char__DEFAULT 0 -#endif - -/* -** Default values for register R_SERIAL1_BAUD -*/ - -/* c4800Hz c1843k2Hz c921k6Hz c460k8Hz c57k6Hz c9600Hz c300Hz c1200Hz c230k4Hz c115k2Hz c600Hz c2400Hz c19k2Hz c6250kHz c38k4Hz */ -#ifndef R_SERIAL1_BAUD__tr_baud__DEFAULT -#define R_SERIAL1_BAUD__tr_baud__DEFAULT c4800Hz -#endif - -/* c4800Hz c1843k2Hz c921k6Hz c460k8Hz c57k6Hz c9600Hz c300Hz c1200Hz c230k4Hz c115k2Hz c600Hz c2400Hz c19k2Hz c6250kHz c38k4Hz */ -#ifndef R_SERIAL1_BAUD__rec_baud__DEFAULT -#define R_SERIAL1_BAUD__rec_baud__DEFAULT c4800Hz -#endif - -/* -** Default values for register R_SERIAL1_CTRL -*/ - -/* c4800Hz c1843k2Hz c921k6Hz c460k8Hz c57k6Hz c9600Hz c300Hz c1200Hz c230k4Hz c115k2Hz c600Hz c2400Hz c19k2Hz c6250kHz c38k4Hz */ -#ifndef R_SERIAL1_CTRL__tr_baud__DEFAULT -#define R_SERIAL1_CTRL__tr_baud__DEFAULT c4800Hz -#endif - -/* c4800Hz c1843k2Hz c921k6Hz c460k8Hz c57k6Hz c9600Hz c300Hz c1200Hz c230k4Hz c115k2Hz c600Hz c2400Hz c19k2Hz c6250kHz c38k4Hz */ -#ifndef R_SERIAL1_CTRL__rec_baud__DEFAULT -#define R_SERIAL1_CTRL__rec_baud__DEFAULT c4800Hz -#endif - -/* ignore stop */ -#ifndef R_SERIAL1_CTRL__dma_err__DEFAULT -#define R_SERIAL1_CTRL__dma_err__DEFAULT ignore -#endif - -/* disable enable */ -#ifndef R_SERIAL1_CTRL__rec_enable__DEFAULT -#define R_SERIAL1_CTRL__rec_enable__DEFAULT disable -#endif - -/* inactive active */ -#ifndef R_SERIAL1_CTRL__rts___DEFAULT -#define R_SERIAL1_CTRL__rts___DEFAULT inactive -#endif - -/* majority middle */ -#ifndef R_SERIAL1_CTRL__sampling__DEFAULT -#define R_SERIAL1_CTRL__sampling__DEFAULT majority -#endif - -/* normal stick */ -#ifndef R_SERIAL1_CTRL__rec_stick_par__DEFAULT -#define R_SERIAL1_CTRL__rec_stick_par__DEFAULT normal -#endif - -/* even odd */ -#ifndef R_SERIAL1_CTRL__rec_par__DEFAULT -#define R_SERIAL1_CTRL__rec_par__DEFAULT even -#endif - -/* disable enable */ -#ifndef R_SERIAL1_CTRL__rec_par_en__DEFAULT -#define R_SERIAL1_CTRL__rec_par_en__DEFAULT disable -#endif - -/* rec_8bit rec_7bit */ -#ifndef R_SERIAL1_CTRL__rec_bitnr__DEFAULT -#define R_SERIAL1_CTRL__rec_bitnr__DEFAULT rec_8bit -#endif - -/* 0 - 0x1 */ -#ifndef R_SERIAL1_CTRL__txd__DEFAULT -#define R_SERIAL1_CTRL__txd__DEFAULT 0 -#endif - -/* disable enable */ -#ifndef R_SERIAL1_CTRL__tr_enable__DEFAULT -#define R_SERIAL1_CTRL__tr_enable__DEFAULT disable -#endif - -/* disabled active */ -#ifndef R_SERIAL1_CTRL__auto_cts__DEFAULT -#define R_SERIAL1_CTRL__auto_cts__DEFAULT disabled -#endif - -/* one_bit two_bits */ -#ifndef R_SERIAL1_CTRL__stop_bits__DEFAULT -#define R_SERIAL1_CTRL__stop_bits__DEFAULT one_bit -#endif - -/* normal stick */ -#ifndef R_SERIAL1_CTRL__tr_stick_par__DEFAULT -#define R_SERIAL1_CTRL__tr_stick_par__DEFAULT normal -#endif - -/* even odd */ -#ifndef R_SERIAL1_CTRL__tr_par__DEFAULT -#define R_SERIAL1_CTRL__tr_par__DEFAULT even -#endif - -/* disable enable */ -#ifndef R_SERIAL1_CTRL__tr_par_en__DEFAULT -#define R_SERIAL1_CTRL__tr_par_en__DEFAULT disable -#endif - -/* tr_7bit tr_8bit */ -#ifndef R_SERIAL1_CTRL__tr_bitnr__DEFAULT -#define R_SERIAL1_CTRL__tr_bitnr__DEFAULT tr_7bit -#endif - -/* 0 - 0xff */ -#ifndef R_SERIAL1_CTRL__data_out__DEFAULT -#define R_SERIAL1_CTRL__data_out__DEFAULT 0 -#endif - -/* -** Default values for register R_SERIAL1_REC_CTRL -*/ - -/* ignore stop */ -#ifndef R_SERIAL1_REC_CTRL__dma_err__DEFAULT -#define R_SERIAL1_REC_CTRL__dma_err__DEFAULT ignore -#endif - -/* disable enable */ -#ifndef R_SERIAL1_REC_CTRL__rec_enable__DEFAULT -#define R_SERIAL1_REC_CTRL__rec_enable__DEFAULT disable -#endif - -/* inactive active */ -#ifndef R_SERIAL1_REC_CTRL__rts___DEFAULT -#define R_SERIAL1_REC_CTRL__rts___DEFAULT inactive -#endif - -/* majority middle */ -#ifndef R_SERIAL1_REC_CTRL__sampling__DEFAULT -#define R_SERIAL1_REC_CTRL__sampling__DEFAULT majority -#endif - -/* normal stick */ -#ifndef R_SERIAL1_REC_CTRL__rec_stick_par__DEFAULT -#define R_SERIAL1_REC_CTRL__rec_stick_par__DEFAULT normal -#endif - -/* even odd */ -#ifndef R_SERIAL1_REC_CTRL__rec_par__DEFAULT -#define R_SERIAL1_REC_CTRL__rec_par__DEFAULT even -#endif - -/* disable enable */ -#ifndef R_SERIAL1_REC_CTRL__rec_par_en__DEFAULT -#define R_SERIAL1_REC_CTRL__rec_par_en__DEFAULT disable -#endif - -/* rec_8bit rec_7bit */ -#ifndef R_SERIAL1_REC_CTRL__rec_bitnr__DEFAULT -#define R_SERIAL1_REC_CTRL__rec_bitnr__DEFAULT rec_8bit -#endif - -/* -** Default values for register R_SERIAL1_TR_CTRL -*/ - -/* 0 - 0x1 */ -#ifndef R_SERIAL1_TR_CTRL__txd__DEFAULT -#define R_SERIAL1_TR_CTRL__txd__DEFAULT 0 -#endif - -/* disable enable */ -#ifndef R_SERIAL1_TR_CTRL__tr_enable__DEFAULT -#define R_SERIAL1_TR_CTRL__tr_enable__DEFAULT disable -#endif - -/* disabled active */ -#ifndef R_SERIAL1_TR_CTRL__auto_cts__DEFAULT -#define R_SERIAL1_TR_CTRL__auto_cts__DEFAULT disabled -#endif - -/* one_bit two_bits */ -#ifndef R_SERIAL1_TR_CTRL__stop_bits__DEFAULT -#define R_SERIAL1_TR_CTRL__stop_bits__DEFAULT one_bit -#endif - -/* normal stick */ -#ifndef R_SERIAL1_TR_CTRL__tr_stick_par__DEFAULT -#define R_SERIAL1_TR_CTRL__tr_stick_par__DEFAULT normal -#endif - -/* even odd */ -#ifndef R_SERIAL1_TR_CTRL__tr_par__DEFAULT -#define R_SERIAL1_TR_CTRL__tr_par__DEFAULT even -#endif - -/* disable enable */ -#ifndef R_SERIAL1_TR_CTRL__tr_par_en__DEFAULT -#define R_SERIAL1_TR_CTRL__tr_par_en__DEFAULT disable -#endif - -/* tr_7bit tr_8bit */ -#ifndef R_SERIAL1_TR_CTRL__tr_bitnr__DEFAULT -#define R_SERIAL1_TR_CTRL__tr_bitnr__DEFAULT tr_7bit -#endif - -/* -** Default values for register R_SERIAL1_TR_DATA -*/ - -/* 0 - 0xff */ -#ifndef R_SERIAL1_TR_DATA__data_out__DEFAULT -#define R_SERIAL1_TR_DATA__data_out__DEFAULT 0 -#endif - -/* -** Default values for register R_SERIAL1_XOFF -*/ - -/* stop enable */ -#ifndef R_SERIAL1_XOFF__tx_stop__DEFAULT -#define R_SERIAL1_XOFF__tx_stop__DEFAULT stop -#endif - -/* disable enable */ -#ifndef R_SERIAL1_XOFF__auto_xoff__DEFAULT -#define R_SERIAL1_XOFF__auto_xoff__DEFAULT disable -#endif - -/* 0 - 0xff */ -#ifndef R_SERIAL1_XOFF__xoff_char__DEFAULT -#define R_SERIAL1_XOFF__xoff_char__DEFAULT 0 -#endif - -/* -** Default values for register R_SERIAL2_BAUD -*/ - -/* c4800Hz c1843k2Hz c921k6Hz c460k8Hz c57k6Hz c9600Hz c300Hz c1200Hz c230k4Hz c115k2Hz c600Hz c2400Hz c19k2Hz c6250kHz c38k4Hz */ -#ifndef R_SERIAL2_BAUD__tr_baud__DEFAULT -#define R_SERIAL2_BAUD__tr_baud__DEFAULT c4800Hz -#endif - -/* c4800Hz c1843k2Hz c921k6Hz c460k8Hz c57k6Hz c9600Hz c300Hz c1200Hz c230k4Hz c115k2Hz c600Hz c2400Hz c19k2Hz c6250kHz c38k4Hz */ -#ifndef R_SERIAL2_BAUD__rec_baud__DEFAULT -#define R_SERIAL2_BAUD__rec_baud__DEFAULT c4800Hz -#endif - -/* -** Default values for register R_SERIAL2_CTRL -*/ - -/* c4800Hz c1843k2Hz c921k6Hz c460k8Hz c57k6Hz c9600Hz c300Hz c1200Hz c230k4Hz c115k2Hz c600Hz c2400Hz c19k2Hz c6250kHz c38k4Hz */ -#ifndef R_SERIAL2_CTRL__tr_baud__DEFAULT -#define R_SERIAL2_CTRL__tr_baud__DEFAULT c4800Hz -#endif - -/* c4800Hz c1843k2Hz c921k6Hz c460k8Hz c57k6Hz c9600Hz c300Hz c1200Hz c230k4Hz c115k2Hz c600Hz c2400Hz c19k2Hz c6250kHz c38k4Hz */ -#ifndef R_SERIAL2_CTRL__rec_baud__DEFAULT -#define R_SERIAL2_CTRL__rec_baud__DEFAULT c4800Hz -#endif - -/* ignore stop */ -#ifndef R_SERIAL2_CTRL__dma_err__DEFAULT -#define R_SERIAL2_CTRL__dma_err__DEFAULT ignore -#endif - -/* disable enable */ -#ifndef R_SERIAL2_CTRL__rec_enable__DEFAULT -#define R_SERIAL2_CTRL__rec_enable__DEFAULT disable -#endif - -/* inactive active */ -#ifndef R_SERIAL2_CTRL__rts___DEFAULT -#define R_SERIAL2_CTRL__rts___DEFAULT inactive -#endif - -/* majority middle */ -#ifndef R_SERIAL2_CTRL__sampling__DEFAULT -#define R_SERIAL2_CTRL__sampling__DEFAULT majority -#endif - -/* normal stick */ -#ifndef R_SERIAL2_CTRL__rec_stick_par__DEFAULT -#define R_SERIAL2_CTRL__rec_stick_par__DEFAULT normal -#endif - -/* even odd */ -#ifndef R_SERIAL2_CTRL__rec_par__DEFAULT -#define R_SERIAL2_CTRL__rec_par__DEFAULT even -#endif - -/* disable enable */ -#ifndef R_SERIAL2_CTRL__rec_par_en__DEFAULT -#define R_SERIAL2_CTRL__rec_par_en__DEFAULT disable -#endif - -/* rec_8bit rec_7bit */ -#ifndef R_SERIAL2_CTRL__rec_bitnr__DEFAULT -#define R_SERIAL2_CTRL__rec_bitnr__DEFAULT rec_8bit -#endif - -/* 0 - 0x1 */ -#ifndef R_SERIAL2_CTRL__txd__DEFAULT -#define R_SERIAL2_CTRL__txd__DEFAULT 0 -#endif - -/* disable enable */ -#ifndef R_SERIAL2_CTRL__tr_enable__DEFAULT -#define R_SERIAL2_CTRL__tr_enable__DEFAULT disable -#endif - -/* disabled active */ -#ifndef R_SERIAL2_CTRL__auto_cts__DEFAULT -#define R_SERIAL2_CTRL__auto_cts__DEFAULT disabled -#endif - -/* one_bit two_bits */ -#ifndef R_SERIAL2_CTRL__stop_bits__DEFAULT -#define R_SERIAL2_CTRL__stop_bits__DEFAULT one_bit -#endif - -/* normal stick */ -#ifndef R_SERIAL2_CTRL__tr_stick_par__DEFAULT -#define R_SERIAL2_CTRL__tr_stick_par__DEFAULT normal -#endif - -/* even odd */ -#ifndef R_SERIAL2_CTRL__tr_par__DEFAULT -#define R_SERIAL2_CTRL__tr_par__DEFAULT even -#endif - -/* disable enable */ -#ifndef R_SERIAL2_CTRL__tr_par_en__DEFAULT -#define R_SERIAL2_CTRL__tr_par_en__DEFAULT disable -#endif - -/* tr_7bit tr_8bit */ -#ifndef R_SERIAL2_CTRL__tr_bitnr__DEFAULT -#define R_SERIAL2_CTRL__tr_bitnr__DEFAULT tr_7bit -#endif - -/* 0 - 0xff */ -#ifndef R_SERIAL2_CTRL__data_out__DEFAULT -#define R_SERIAL2_CTRL__data_out__DEFAULT 0 -#endif - -/* -** Default values for register R_SERIAL2_REC_CTRL -*/ - -/* ignore stop */ -#ifndef R_SERIAL2_REC_CTRL__dma_err__DEFAULT -#define R_SERIAL2_REC_CTRL__dma_err__DEFAULT ignore -#endif - -/* disable enable */ -#ifndef R_SERIAL2_REC_CTRL__rec_enable__DEFAULT -#define R_SERIAL2_REC_CTRL__rec_enable__DEFAULT disable -#endif - -/* inactive active */ -#ifndef R_SERIAL2_REC_CTRL__rts___DEFAULT -#define R_SERIAL2_REC_CTRL__rts___DEFAULT inactive -#endif - -/* majority middle */ -#ifndef R_SERIAL2_REC_CTRL__sampling__DEFAULT -#define R_SERIAL2_REC_CTRL__sampling__DEFAULT majority -#endif - -/* normal stick */ -#ifndef R_SERIAL2_REC_CTRL__rec_stick_par__DEFAULT -#define R_SERIAL2_REC_CTRL__rec_stick_par__DEFAULT normal -#endif - -/* even odd */ -#ifndef R_SERIAL2_REC_CTRL__rec_par__DEFAULT -#define R_SERIAL2_REC_CTRL__rec_par__DEFAULT even -#endif - -/* disable enable */ -#ifndef R_SERIAL2_REC_CTRL__rec_par_en__DEFAULT -#define R_SERIAL2_REC_CTRL__rec_par_en__DEFAULT disable -#endif - -/* rec_8bit rec_7bit */ -#ifndef R_SERIAL2_REC_CTRL__rec_bitnr__DEFAULT -#define R_SERIAL2_REC_CTRL__rec_bitnr__DEFAULT rec_8bit -#endif - -/* -** Default values for register R_SERIAL2_TR_CTRL -*/ - -/* 0 - 0x1 */ -#ifndef R_SERIAL2_TR_CTRL__txd__DEFAULT -#define R_SERIAL2_TR_CTRL__txd__DEFAULT 0 -#endif - -/* disable enable */ -#ifndef R_SERIAL2_TR_CTRL__tr_enable__DEFAULT -#define R_SERIAL2_TR_CTRL__tr_enable__DEFAULT disable -#endif - -/* disabled active */ -#ifndef R_SERIAL2_TR_CTRL__auto_cts__DEFAULT -#define R_SERIAL2_TR_CTRL__auto_cts__DEFAULT disabled -#endif - -/* one_bit two_bits */ -#ifndef R_SERIAL2_TR_CTRL__stop_bits__DEFAULT -#define R_SERIAL2_TR_CTRL__stop_bits__DEFAULT one_bit -#endif - -/* normal stick */ -#ifndef R_SERIAL2_TR_CTRL__tr_stick_par__DEFAULT -#define R_SERIAL2_TR_CTRL__tr_stick_par__DEFAULT normal -#endif - -/* even odd */ -#ifndef R_SERIAL2_TR_CTRL__tr_par__DEFAULT -#define R_SERIAL2_TR_CTRL__tr_par__DEFAULT even -#endif - -/* disable enable */ -#ifndef R_SERIAL2_TR_CTRL__tr_par_en__DEFAULT -#define R_SERIAL2_TR_CTRL__tr_par_en__DEFAULT disable -#endif - -/* tr_7bit tr_8bit */ -#ifndef R_SERIAL2_TR_CTRL__tr_bitnr__DEFAULT -#define R_SERIAL2_TR_CTRL__tr_bitnr__DEFAULT tr_7bit -#endif - -/* -** Default values for register R_SERIAL2_TR_DATA -*/ - -/* 0 - 0xff */ -#ifndef R_SERIAL2_TR_DATA__data_out__DEFAULT -#define R_SERIAL2_TR_DATA__data_out__DEFAULT 0 -#endif - -/* -** Default values for register R_SERIAL2_XOFF -*/ - -/* stop enable */ -#ifndef R_SERIAL2_XOFF__tx_stop__DEFAULT -#define R_SERIAL2_XOFF__tx_stop__DEFAULT stop -#endif - -/* disable enable */ -#ifndef R_SERIAL2_XOFF__auto_xoff__DEFAULT -#define R_SERIAL2_XOFF__auto_xoff__DEFAULT disable -#endif - -/* 0 - 0xff */ -#ifndef R_SERIAL2_XOFF__xoff_char__DEFAULT -#define R_SERIAL2_XOFF__xoff_char__DEFAULT 0 -#endif - -/* -** Default values for register R_SERIAL3_BAUD -*/ - -/* c4800Hz c1843k2Hz c921k6Hz c460k8Hz c57k6Hz c9600Hz c300Hz c1200Hz c230k4Hz c115k2Hz c600Hz c2400Hz c19k2Hz c6250kHz c38k4Hz */ -#ifndef R_SERIAL3_BAUD__tr_baud__DEFAULT -#define R_SERIAL3_BAUD__tr_baud__DEFAULT c4800Hz -#endif - -/* c4800Hz c1843k2Hz c921k6Hz c460k8Hz c57k6Hz c9600Hz c300Hz c1200Hz c230k4Hz c115k2Hz c600Hz c2400Hz c19k2Hz c6250kHz c38k4Hz */ -#ifndef R_SERIAL3_BAUD__rec_baud__DEFAULT -#define R_SERIAL3_BAUD__rec_baud__DEFAULT c4800Hz -#endif - -/* -** Default values for register R_SERIAL3_CTRL -*/ - -/* c4800Hz c1843k2Hz c921k6Hz c460k8Hz c57k6Hz c9600Hz c300Hz c1200Hz c230k4Hz c115k2Hz c600Hz c2400Hz c19k2Hz c6250kHz c38k4Hz */ -#ifndef R_SERIAL3_CTRL__tr_baud__DEFAULT -#define R_SERIAL3_CTRL__tr_baud__DEFAULT c4800Hz -#endif - -/* c4800Hz c1843k2Hz c921k6Hz c460k8Hz c57k6Hz c9600Hz c300Hz c1200Hz c230k4Hz c115k2Hz c600Hz c2400Hz c19k2Hz c6250kHz c38k4Hz */ -#ifndef R_SERIAL3_CTRL__rec_baud__DEFAULT -#define R_SERIAL3_CTRL__rec_baud__DEFAULT c4800Hz -#endif - -/* ignore stop */ -#ifndef R_SERIAL3_CTRL__dma_err__DEFAULT -#define R_SERIAL3_CTRL__dma_err__DEFAULT ignore -#endif - -/* disable enable */ -#ifndef R_SERIAL3_CTRL__rec_enable__DEFAULT -#define R_SERIAL3_CTRL__rec_enable__DEFAULT disable -#endif - -/* inactive active */ -#ifndef R_SERIAL3_CTRL__rts___DEFAULT -#define R_SERIAL3_CTRL__rts___DEFAULT inactive -#endif - -/* majority middle */ -#ifndef R_SERIAL3_CTRL__sampling__DEFAULT -#define R_SERIAL3_CTRL__sampling__DEFAULT majority -#endif - -/* normal stick */ -#ifndef R_SERIAL3_CTRL__rec_stick_par__DEFAULT -#define R_SERIAL3_CTRL__rec_stick_par__DEFAULT normal -#endif - -/* even odd */ -#ifndef R_SERIAL3_CTRL__rec_par__DEFAULT -#define R_SERIAL3_CTRL__rec_par__DEFAULT even -#endif - -/* disable enable */ -#ifndef R_SERIAL3_CTRL__rec_par_en__DEFAULT -#define R_SERIAL3_CTRL__rec_par_en__DEFAULT disable -#endif - -/* rec_8bit rec_7bit */ -#ifndef R_SERIAL3_CTRL__rec_bitnr__DEFAULT -#define R_SERIAL3_CTRL__rec_bitnr__DEFAULT rec_8bit -#endif - -/* 0 - 0x1 */ -#ifndef R_SERIAL3_CTRL__txd__DEFAULT -#define R_SERIAL3_CTRL__txd__DEFAULT 0 -#endif - -/* disable enable */ -#ifndef R_SERIAL3_CTRL__tr_enable__DEFAULT -#define R_SERIAL3_CTRL__tr_enable__DEFAULT disable -#endif - -/* disabled active */ -#ifndef R_SERIAL3_CTRL__auto_cts__DEFAULT -#define R_SERIAL3_CTRL__auto_cts__DEFAULT disabled -#endif - -/* one_bit two_bits */ -#ifndef R_SERIAL3_CTRL__stop_bits__DEFAULT -#define R_SERIAL3_CTRL__stop_bits__DEFAULT one_bit -#endif - -/* normal stick */ -#ifndef R_SERIAL3_CTRL__tr_stick_par__DEFAULT -#define R_SERIAL3_CTRL__tr_stick_par__DEFAULT normal -#endif - -/* even odd */ -#ifndef R_SERIAL3_CTRL__tr_par__DEFAULT -#define R_SERIAL3_CTRL__tr_par__DEFAULT even -#endif - -/* disable enable */ -#ifndef R_SERIAL3_CTRL__tr_par_en__DEFAULT -#define R_SERIAL3_CTRL__tr_par_en__DEFAULT disable -#endif - -/* tr_7bit tr_8bit */ -#ifndef R_SERIAL3_CTRL__tr_bitnr__DEFAULT -#define R_SERIAL3_CTRL__tr_bitnr__DEFAULT tr_7bit -#endif - -/* 0 - 0xff */ -#ifndef R_SERIAL3_CTRL__data_out__DEFAULT -#define R_SERIAL3_CTRL__data_out__DEFAULT 0 -#endif - -/* -** Default values for register R_SERIAL3_REC_CTRL -*/ - -/* ignore stop */ -#ifndef R_SERIAL3_REC_CTRL__dma_err__DEFAULT -#define R_SERIAL3_REC_CTRL__dma_err__DEFAULT ignore -#endif - -/* disable enable */ -#ifndef R_SERIAL3_REC_CTRL__rec_enable__DEFAULT -#define R_SERIAL3_REC_CTRL__rec_enable__DEFAULT disable -#endif - -/* inactive active */ -#ifndef R_SERIAL3_REC_CTRL__rts___DEFAULT -#define R_SERIAL3_REC_CTRL__rts___DEFAULT inactive -#endif - -/* majority middle */ -#ifndef R_SERIAL3_REC_CTRL__sampling__DEFAULT -#define R_SERIAL3_REC_CTRL__sampling__DEFAULT majority -#endif - -/* normal stick */ -#ifndef R_SERIAL3_REC_CTRL__rec_stick_par__DEFAULT -#define R_SERIAL3_REC_CTRL__rec_stick_par__DEFAULT normal -#endif - -/* even odd */ -#ifndef R_SERIAL3_REC_CTRL__rec_par__DEFAULT -#define R_SERIAL3_REC_CTRL__rec_par__DEFAULT even -#endif - -/* disable enable */ -#ifndef R_SERIAL3_REC_CTRL__rec_par_en__DEFAULT -#define R_SERIAL3_REC_CTRL__rec_par_en__DEFAULT disable -#endif - -/* rec_8bit rec_7bit */ -#ifndef R_SERIAL3_REC_CTRL__rec_bitnr__DEFAULT -#define R_SERIAL3_REC_CTRL__rec_bitnr__DEFAULT rec_8bit -#endif - -/* -** Default values for register R_SERIAL3_TR_CTRL -*/ - -/* 0 - 0x1 */ -#ifndef R_SERIAL3_TR_CTRL__txd__DEFAULT -#define R_SERIAL3_TR_CTRL__txd__DEFAULT 0 -#endif - -/* disable enable */ -#ifndef R_SERIAL3_TR_CTRL__tr_enable__DEFAULT -#define R_SERIAL3_TR_CTRL__tr_enable__DEFAULT disable -#endif - -/* disabled active */ -#ifndef R_SERIAL3_TR_CTRL__auto_cts__DEFAULT -#define R_SERIAL3_TR_CTRL__auto_cts__DEFAULT disabled -#endif - -/* one_bit two_bits */ -#ifndef R_SERIAL3_TR_CTRL__stop_bits__DEFAULT -#define R_SERIAL3_TR_CTRL__stop_bits__DEFAULT one_bit -#endif - -/* normal stick */ -#ifndef R_SERIAL3_TR_CTRL__tr_stick_par__DEFAULT -#define R_SERIAL3_TR_CTRL__tr_stick_par__DEFAULT normal -#endif - -/* even odd */ -#ifndef R_SERIAL3_TR_CTRL__tr_par__DEFAULT -#define R_SERIAL3_TR_CTRL__tr_par__DEFAULT even -#endif - -/* disable enable */ -#ifndef R_SERIAL3_TR_CTRL__tr_par_en__DEFAULT -#define R_SERIAL3_TR_CTRL__tr_par_en__DEFAULT disable -#endif - -/* tr_7bit tr_8bit */ -#ifndef R_SERIAL3_TR_CTRL__tr_bitnr__DEFAULT -#define R_SERIAL3_TR_CTRL__tr_bitnr__DEFAULT tr_7bit -#endif - -/* -** Default values for register R_SERIAL3_TR_DATA -*/ - -/* 0 - 0xff */ -#ifndef R_SERIAL3_TR_DATA__data_out__DEFAULT -#define R_SERIAL3_TR_DATA__data_out__DEFAULT 0 -#endif - -/* -** Default values for register R_SERIAL3_XOFF -*/ - -/* stop enable */ -#ifndef R_SERIAL3_XOFF__tx_stop__DEFAULT -#define R_SERIAL3_XOFF__tx_stop__DEFAULT stop -#endif - -/* disable enable */ -#ifndef R_SERIAL3_XOFF__auto_xoff__DEFAULT -#define R_SERIAL3_XOFF__auto_xoff__DEFAULT disable -#endif - -/* 0 - 0xff */ -#ifndef R_SERIAL3_XOFF__xoff_char__DEFAULT -#define R_SERIAL3_XOFF__xoff_char__DEFAULT 0 -#endif - -/* -** Default values for register R_SERIAL_PRESCALE -*/ - -/* 0 - 0xffff */ -#ifndef R_SERIAL_PRESCALE__ser_presc__DEFAULT -#define R_SERIAL_PRESCALE__ser_presc__DEFAULT 0 -#endif - -/* -** Default values for register R_SET_EOP -*/ - -/* set nop */ -#ifndef R_SET_EOP__ch9_eop__DEFAULT -#define R_SET_EOP__ch9_eop__DEFAULT set -#endif - -/* set nop */ -#ifndef R_SET_EOP__ch7_eop__DEFAULT -#define R_SET_EOP__ch7_eop__DEFAULT set -#endif - -/* set nop */ -#ifndef R_SET_EOP__ch5_eop__DEFAULT -#define R_SET_EOP__ch5_eop__DEFAULT set -#endif - -/* set nop */ -#ifndef R_SET_EOP__ch3_eop__DEFAULT -#define R_SET_EOP__ch3_eop__DEFAULT set -#endif - -/* -** Default values for register R_SHARED_RAM_ADDR -*/ - -/* 0 - 0x3fffff */ -#ifndef R_SHARED_RAM_ADDR__base_addr__DEFAULT -#define R_SHARED_RAM_ADDR__base_addr__DEFAULT 0 -#endif - -/* -** Default values for register R_SHARED_RAM_CONFIG -*/ - -/* word byte */ -#ifndef R_SHARED_RAM_CONFIG__width__DEFAULT -#define R_SHARED_RAM_CONFIG__width__DEFAULT word -#endif - -/* yes no */ -#ifndef R_SHARED_RAM_CONFIG__enable__DEFAULT -#define R_SHARED_RAM_CONFIG__enable__DEFAULT yes -#endif - -/* int nop */ -#ifndef R_SHARED_RAM_CONFIG__pint__DEFAULT -#define R_SHARED_RAM_CONFIG__pint__DEFAULT int -#endif - -/* clr nop */ -#ifndef R_SHARED_RAM_CONFIG__clri__DEFAULT -#define R_SHARED_RAM_CONFIG__clri__DEFAULT clr -#endif - -/* -** Default values for register R_SINGLE_STEP -*/ - -/* off on */ -#ifndef R_SINGLE_STEP__single_step__DEFAULT -#define R_SINGLE_STEP__single_step__DEFAULT off -#endif - -/* off on */ -#ifndef R_SINGLE_STEP__step_wr__DEFAULT -#define R_SINGLE_STEP__step_wr__DEFAULT off -#endif - -/* off on */ -#ifndef R_SINGLE_STEP__step_rd__DEFAULT -#define R_SINGLE_STEP__step_rd__DEFAULT off -#endif - -/* off on */ -#ifndef R_SINGLE_STEP__step_fetch__DEFAULT -#define R_SINGLE_STEP__step_fetch__DEFAULT off -#endif - -/* -** Default values for register R_SYNC_SERIAL1_CTRL -*/ - -/* c4800Hz c921k6Hz c460k8Hz c57k6Hz c28k8Hz c9600Hz c300Hz c1200Hz c230k4Hz c115k2Hz c3125kHz c150Hz c600Hz c2400Hz c19k2Hz */ -#ifndef R_SYNC_SERIAL1_CTRL__tr_baud__DEFAULT -#define R_SYNC_SERIAL1_CTRL__tr_baud__DEFAULT c4800Hz -#endif - -/* off on */ -#ifndef R_SYNC_SERIAL1_CTRL__dma_enable__DEFAULT -#define R_SYNC_SERIAL1_CTRL__dma_enable__DEFAULT off -#endif - -/* slave_input master_input slave_output slave_bidir master_output master_bidir */ -#ifndef R_SYNC_SERIAL1_CTRL__mode__DEFAULT -#define R_SYNC_SERIAL1_CTRL__mode__DEFAULT slave_input -#endif - -/* normal ignore */ -#ifndef R_SYNC_SERIAL1_CTRL__error__DEFAULT -#define R_SYNC_SERIAL1_CTRL__error__DEFAULT normal -#endif - -/* disable enable */ -#ifndef R_SYNC_SERIAL1_CTRL__rec_enable__DEFAULT -#define R_SYNC_SERIAL1_CTRL__rec_enable__DEFAULT disable -#endif - -/* normal early */ -#ifndef R_SYNC_SERIAL1_CTRL__f_synctype__DEFAULT -#define R_SYNC_SERIAL1_CTRL__f_synctype__DEFAULT normal -#endif - -/* extended word bit */ -#ifndef R_SYNC_SERIAL1_CTRL__f_syncsize__DEFAULT -#define R_SYNC_SERIAL1_CTRL__f_syncsize__DEFAULT extended -#endif - -/* off on */ -#ifndef R_SYNC_SERIAL1_CTRL__f_sync__DEFAULT -#define R_SYNC_SERIAL1_CTRL__f_sync__DEFAULT off -#endif - -/* normal gated */ -#ifndef R_SYNC_SERIAL1_CTRL__clk_mode__DEFAULT -#define R_SYNC_SERIAL1_CTRL__clk_mode__DEFAULT normal -#endif - -/* running stopped */ -#ifndef R_SYNC_SERIAL1_CTRL__clk_halt__DEFAULT -#define R_SYNC_SERIAL1_CTRL__clk_halt__DEFAULT running -#endif - -/* lsb msb */ -#ifndef R_SYNC_SERIAL1_CTRL__bitorder__DEFAULT -#define R_SYNC_SERIAL1_CTRL__bitorder__DEFAULT lsb -#endif - -/* disable enable */ -#ifndef R_SYNC_SERIAL1_CTRL__tr_enable__DEFAULT -#define R_SYNC_SERIAL1_CTRL__tr_enable__DEFAULT disable -#endif - -/* size24bit size16bit size8bit size12bit size32bit */ -#ifndef R_SYNC_SERIAL1_CTRL__wordsize__DEFAULT -#define R_SYNC_SERIAL1_CTRL__wordsize__DEFAULT size24bit -#endif - -/* lmt_0 lmt_8 */ -#ifndef R_SYNC_SERIAL1_CTRL__buf_empty__DEFAULT -#define R_SYNC_SERIAL1_CTRL__buf_empty__DEFAULT lmt_0 -#endif - -/* lmt_32 lmt_8 */ -#ifndef R_SYNC_SERIAL1_CTRL__buf_full__DEFAULT -#define R_SYNC_SERIAL1_CTRL__buf_full__DEFAULT lmt_32 -#endif - -/* disabled enabled */ -#ifndef R_SYNC_SERIAL1_CTRL__flow_ctrl__DEFAULT -#define R_SYNC_SERIAL1_CTRL__flow_ctrl__DEFAULT disabled -#endif - -/* neg pos */ -#ifndef R_SYNC_SERIAL1_CTRL__clk_polarity__DEFAULT -#define R_SYNC_SERIAL1_CTRL__clk_polarity__DEFAULT neg -#endif - -/* inverted normal */ -#ifndef R_SYNC_SERIAL1_CTRL__frame_polarity__DEFAULT -#define R_SYNC_SERIAL1_CTRL__frame_polarity__DEFAULT inverted -#endif - -/* inverted normal */ -#ifndef R_SYNC_SERIAL1_CTRL__status_polarity__DEFAULT -#define R_SYNC_SERIAL1_CTRL__status_polarity__DEFAULT inverted -#endif - -/* inverted normal */ -#ifndef R_SYNC_SERIAL1_CTRL__clk_driver__DEFAULT -#define R_SYNC_SERIAL1_CTRL__clk_driver__DEFAULT inverted -#endif - -/* inverted normal */ -#ifndef R_SYNC_SERIAL1_CTRL__frame_driver__DEFAULT -#define R_SYNC_SERIAL1_CTRL__frame_driver__DEFAULT inverted -#endif - -/* inverted normal */ -#ifndef R_SYNC_SERIAL1_CTRL__status_driver__DEFAULT -#define R_SYNC_SERIAL1_CTRL__status_driver__DEFAULT inverted -#endif - -/* high low */ -#ifndef R_SYNC_SERIAL1_CTRL__def_out0__DEFAULT -#define R_SYNC_SERIAL1_CTRL__def_out0__DEFAULT high -#endif - -/* -** Default values for register R_SYNC_SERIAL1_TR_BYTE -*/ - -/* 0 - 0xff */ -#ifndef R_SYNC_SERIAL1_TR_BYTE__data_out__DEFAULT -#define R_SYNC_SERIAL1_TR_BYTE__data_out__DEFAULT 0 -#endif - -/* -** Default values for register R_SYNC_SERIAL1_TR_DATA -*/ - -/* 0 - 0xffffffff */ -#ifndef R_SYNC_SERIAL1_TR_DATA__data_out__DEFAULT -#define R_SYNC_SERIAL1_TR_DATA__data_out__DEFAULT 0 -#endif - -/* -** Default values for register R_SYNC_SERIAL1_TR_WORD -*/ - -/* 0 - 0xffff */ -#ifndef R_SYNC_SERIAL1_TR_WORD__data_out__DEFAULT -#define R_SYNC_SERIAL1_TR_WORD__data_out__DEFAULT 0 -#endif - -/* -** Default values for register R_SYNC_SERIAL3_CTRL -*/ - -/* c4800Hz c921k6Hz c460k8Hz c57k6Hz c28k8Hz c9600Hz c300Hz c1200Hz c230k4Hz c115k2Hz c3125kHz c150Hz c600Hz c2400Hz c19k2Hz */ -#ifndef R_SYNC_SERIAL3_CTRL__tr_baud__DEFAULT -#define R_SYNC_SERIAL3_CTRL__tr_baud__DEFAULT c4800Hz -#endif - -/* off on */ -#ifndef R_SYNC_SERIAL3_CTRL__dma_enable__DEFAULT -#define R_SYNC_SERIAL3_CTRL__dma_enable__DEFAULT off -#endif - -/* slave_input master_input slave_output slave_bidir master_output master_bidir */ -#ifndef R_SYNC_SERIAL3_CTRL__mode__DEFAULT -#define R_SYNC_SERIAL3_CTRL__mode__DEFAULT slave_input -#endif - -/* normal ignore */ -#ifndef R_SYNC_SERIAL3_CTRL__error__DEFAULT -#define R_SYNC_SERIAL3_CTRL__error__DEFAULT normal -#endif - -/* disable enable */ -#ifndef R_SYNC_SERIAL3_CTRL__rec_enable__DEFAULT -#define R_SYNC_SERIAL3_CTRL__rec_enable__DEFAULT disable -#endif - -/* normal early */ -#ifndef R_SYNC_SERIAL3_CTRL__f_synctype__DEFAULT -#define R_SYNC_SERIAL3_CTRL__f_synctype__DEFAULT normal -#endif - -/* extended word bit */ -#ifndef R_SYNC_SERIAL3_CTRL__f_syncsize__DEFAULT -#define R_SYNC_SERIAL3_CTRL__f_syncsize__DEFAULT extended -#endif - -/* off on */ -#ifndef R_SYNC_SERIAL3_CTRL__f_sync__DEFAULT -#define R_SYNC_SERIAL3_CTRL__f_sync__DEFAULT off -#endif - -/* normal gated */ -#ifndef R_SYNC_SERIAL3_CTRL__clk_mode__DEFAULT -#define R_SYNC_SERIAL3_CTRL__clk_mode__DEFAULT normal -#endif - -/* running stopped */ -#ifndef R_SYNC_SERIAL3_CTRL__clk_halt__DEFAULT -#define R_SYNC_SERIAL3_CTRL__clk_halt__DEFAULT running -#endif - -/* lsb msb */ -#ifndef R_SYNC_SERIAL3_CTRL__bitorder__DEFAULT -#define R_SYNC_SERIAL3_CTRL__bitorder__DEFAULT lsb -#endif - -/* disable enable */ -#ifndef R_SYNC_SERIAL3_CTRL__tr_enable__DEFAULT -#define R_SYNC_SERIAL3_CTRL__tr_enable__DEFAULT disable -#endif - -/* size24bit size16bit size8bit size12bit size32bit */ -#ifndef R_SYNC_SERIAL3_CTRL__wordsize__DEFAULT -#define R_SYNC_SERIAL3_CTRL__wordsize__DEFAULT size24bit -#endif - -/* lmt_0 lmt_8 */ -#ifndef R_SYNC_SERIAL3_CTRL__buf_empty__DEFAULT -#define R_SYNC_SERIAL3_CTRL__buf_empty__DEFAULT lmt_0 -#endif - -/* lmt_32 lmt_8 */ -#ifndef R_SYNC_SERIAL3_CTRL__buf_full__DEFAULT -#define R_SYNC_SERIAL3_CTRL__buf_full__DEFAULT lmt_32 -#endif - -/* disabled enabled */ -#ifndef R_SYNC_SERIAL3_CTRL__flow_ctrl__DEFAULT -#define R_SYNC_SERIAL3_CTRL__flow_ctrl__DEFAULT disabled -#endif - -/* neg pos */ -#ifndef R_SYNC_SERIAL3_CTRL__clk_polarity__DEFAULT -#define R_SYNC_SERIAL3_CTRL__clk_polarity__DEFAULT neg -#endif - -/* inverted normal */ -#ifndef R_SYNC_SERIAL3_CTRL__frame_polarity__DEFAULT -#define R_SYNC_SERIAL3_CTRL__frame_polarity__DEFAULT inverted -#endif - -/* inverted normal */ -#ifndef R_SYNC_SERIAL3_CTRL__status_polarity__DEFAULT -#define R_SYNC_SERIAL3_CTRL__status_polarity__DEFAULT inverted -#endif - -/* inverted normal */ -#ifndef R_SYNC_SERIAL3_CTRL__clk_driver__DEFAULT -#define R_SYNC_SERIAL3_CTRL__clk_driver__DEFAULT inverted -#endif - -/* inverted normal */ -#ifndef R_SYNC_SERIAL3_CTRL__frame_driver__DEFAULT -#define R_SYNC_SERIAL3_CTRL__frame_driver__DEFAULT inverted -#endif - -/* inverted normal */ -#ifndef R_SYNC_SERIAL3_CTRL__status_driver__DEFAULT -#define R_SYNC_SERIAL3_CTRL__status_driver__DEFAULT inverted -#endif - -/* high low */ -#ifndef R_SYNC_SERIAL3_CTRL__def_out0__DEFAULT -#define R_SYNC_SERIAL3_CTRL__def_out0__DEFAULT high -#endif - -/* -** Default values for register R_SYNC_SERIAL3_TR_BYTE -*/ - -/* 0 - 0xff */ -#ifndef R_SYNC_SERIAL3_TR_BYTE__data_out__DEFAULT -#define R_SYNC_SERIAL3_TR_BYTE__data_out__DEFAULT 0 -#endif - -/* -** Default values for register R_SYNC_SERIAL3_TR_DATA -*/ - -/* 0 - 0xffffffff */ -#ifndef R_SYNC_SERIAL3_TR_DATA__data_out__DEFAULT -#define R_SYNC_SERIAL3_TR_DATA__data_out__DEFAULT 0 -#endif - -/* -** Default values for register R_SYNC_SERIAL3_TR_WORD -*/ - -/* 0 - 0xffff */ -#ifndef R_SYNC_SERIAL3_TR_WORD__data_out__DEFAULT -#define R_SYNC_SERIAL3_TR_WORD__data_out__DEFAULT 0 -#endif - -/* -** Default values for register R_SYNC_SERIAL_PRESCALE -*/ - -/* baudrate codec */ -#ifndef R_SYNC_SERIAL_PRESCALE__clk_sel_u3__DEFAULT -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__DEFAULT baudrate -#endif - -/* external internal */ -#ifndef R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__DEFAULT -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__DEFAULT external -#endif - -/* baudrate codec */ -#ifndef R_SYNC_SERIAL_PRESCALE__clk_sel_u1__DEFAULT -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__DEFAULT baudrate -#endif - -/* external internal */ -#ifndef R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__DEFAULT -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__DEFAULT external -#endif - -/* div1 div2 div4 div32 div16 div8 div64 div128 */ -#ifndef R_SYNC_SERIAL_PRESCALE__prescaler__DEFAULT -#define R_SYNC_SERIAL_PRESCALE__prescaler__DEFAULT div1 -#endif - -/* normal enabled */ -#ifndef R_SYNC_SERIAL_PRESCALE__warp_mode__DEFAULT -#define R_SYNC_SERIAL_PRESCALE__warp_mode__DEFAULT normal -#endif - -/* 0 - 0xf */ -#ifndef R_SYNC_SERIAL_PRESCALE__frame_rate__DEFAULT -#define R_SYNC_SERIAL_PRESCALE__frame_rate__DEFAULT 0 -#endif - -/* 0 - 0x3ff */ -#ifndef R_SYNC_SERIAL_PRESCALE__word_rate__DEFAULT -#define R_SYNC_SERIAL_PRESCALE__word_rate__DEFAULT 0 -#endif - -/* -** Default values for register R_TEST_MODE -*/ - -/* off on */ -#ifndef R_TEST_MODE__single_step__DEFAULT -#define R_TEST_MODE__single_step__DEFAULT off -#endif - -/* off on */ -#ifndef R_TEST_MODE__step_wr__DEFAULT -#define R_TEST_MODE__step_wr__DEFAULT off -#endif - -/* off on */ -#ifndef R_TEST_MODE__step_rd__DEFAULT -#define R_TEST_MODE__step_rd__DEFAULT off -#endif - -/* off on */ -#ifndef R_TEST_MODE__step_fetch__DEFAULT -#define R_TEST_MODE__step_fetch__DEFAULT off -#endif - -/* off on */ -#ifndef R_TEST_MODE__mmu_test__DEFAULT -#define R_TEST_MODE__mmu_test__DEFAULT off -#endif - -/* off on */ -#ifndef R_TEST_MODE__usb_test__DEFAULT -#define R_TEST_MODE__usb_test__DEFAULT off -#endif - -/* off on */ -#ifndef R_TEST_MODE__scsi_timer_test__DEFAULT -#define R_TEST_MODE__scsi_timer_test__DEFAULT off -#endif - -/* off on */ -#ifndef R_TEST_MODE__backoff__DEFAULT -#define R_TEST_MODE__backoff__DEFAULT off -#endif - -/* off on */ -#ifndef R_TEST_MODE__snmp_test__DEFAULT -#define R_TEST_MODE__snmp_test__DEFAULT off -#endif - -/* do dont */ -#ifndef R_TEST_MODE__snmp_inc__DEFAULT -#define R_TEST_MODE__snmp_inc__DEFAULT do -#endif - -/* off on */ -#ifndef R_TEST_MODE__ser_loop__DEFAULT -#define R_TEST_MODE__ser_loop__DEFAULT off -#endif - -/* off on */ -#ifndef R_TEST_MODE__baudrate__DEFAULT -#define R_TEST_MODE__baudrate__DEFAULT off -#endif - -/* all off even odd */ -#ifndef R_TEST_MODE__timer__DEFAULT -#define R_TEST_MODE__timer__DEFAULT all -#endif - -/* test normal */ -#ifndef R_TEST_MODE__cache_test__DEFAULT -#define R_TEST_MODE__cache_test__DEFAULT test -#endif - -/* test normal */ -#ifndef R_TEST_MODE__tag_test__DEFAULT -#define R_TEST_MODE__tag_test__DEFAULT test -#endif - -/* disable enable */ -#ifndef R_TEST_MODE__cache_enable__DEFAULT -#define R_TEST_MODE__cache_enable__DEFAULT disable -#endif - -/* -** Default values for register R_TIMER_CTRL -*/ - -/* 0 - 0xff */ -#ifndef R_TIMER_CTRL__timerdiv1__DEFAULT -#define R_TIMER_CTRL__timerdiv1__DEFAULT 0 -#endif - -/* 0 - 0xff */ -#ifndef R_TIMER_CTRL__timerdiv0__DEFAULT -#define R_TIMER_CTRL__timerdiv0__DEFAULT 0 -#endif - -/* normal prescale */ -#ifndef R_TIMER_CTRL__presc_timer1__DEFAULT -#define R_TIMER_CTRL__presc_timer1__DEFAULT normal -#endif - -/* clr nop */ -#ifndef R_TIMER_CTRL__i1__DEFAULT -#define R_TIMER_CTRL__i1__DEFAULT clr -#endif - -/* freeze run stop_ld */ -#ifndef R_TIMER_CTRL__tm1__DEFAULT -#define R_TIMER_CTRL__tm1__DEFAULT freeze -#endif - -/* c4800Hz c1843k2Hz c921k6Hz c460k8Hz c57k6Hz cascade0 c9600Hz c300Hz c1200Hz c230k4Hz c115k2Hz c600Hz c2400Hz c19k2Hz c6250kHz c38k4Hz */ -#ifndef R_TIMER_CTRL__clksel1__DEFAULT -#define R_TIMER_CTRL__clksel1__DEFAULT c4800Hz -#endif - -/* external prescale */ -#ifndef R_TIMER_CTRL__presc_ext__DEFAULT -#define R_TIMER_CTRL__presc_ext__DEFAULT external -#endif - -/* clr nop */ -#ifndef R_TIMER_CTRL__i0__DEFAULT -#define R_TIMER_CTRL__i0__DEFAULT clr -#endif - -/* freeze run stop_ld */ -#ifndef R_TIMER_CTRL__tm0__DEFAULT -#define R_TIMER_CTRL__tm0__DEFAULT freeze -#endif - -/* c4800Hz c1843k2Hz c921k6Hz c460k8Hz c57k6Hz c9600Hz c300Hz c1200Hz c230k4Hz c115k2Hz flexible c600Hz c2400Hz c19k2Hz c6250kHz c38k4Hz */ -#ifndef R_TIMER_CTRL__clksel0__DEFAULT -#define R_TIMER_CTRL__clksel0__DEFAULT c4800Hz -#endif - -/* -** Default values for register R_TIMER_PRESCALE -*/ - -/* 0 - 0xffff */ -#ifndef R_TIMER_PRESCALE__tim_presc__DEFAULT -#define R_TIMER_PRESCALE__tim_presc__DEFAULT 0 -#endif - -/* -** Default values for register R_USB_IRQ_MASK_CLR -*/ - -/* clr nop */ -#ifndef R_USB_IRQ_MASK_CLR__iso_eof__DEFAULT -#define R_USB_IRQ_MASK_CLR__iso_eof__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_USB_IRQ_MASK_CLR__intr_eof__DEFAULT -#define R_USB_IRQ_MASK_CLR__intr_eof__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_USB_IRQ_MASK_CLR__iso_eot__DEFAULT -#define R_USB_IRQ_MASK_CLR__iso_eot__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_USB_IRQ_MASK_CLR__intr_eot__DEFAULT -#define R_USB_IRQ_MASK_CLR__intr_eot__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_USB_IRQ_MASK_CLR__ctl_eot__DEFAULT -#define R_USB_IRQ_MASK_CLR__ctl_eot__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_USB_IRQ_MASK_CLR__bulk_eot__DEFAULT -#define R_USB_IRQ_MASK_CLR__bulk_eot__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_USB_IRQ_MASK_CLR__epid_attn__DEFAULT -#define R_USB_IRQ_MASK_CLR__epid_attn__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_USB_IRQ_MASK_CLR__sof__DEFAULT -#define R_USB_IRQ_MASK_CLR__sof__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_USB_IRQ_MASK_CLR__port_status__DEFAULT -#define R_USB_IRQ_MASK_CLR__port_status__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_USB_IRQ_MASK_CLR__ctl_status__DEFAULT -#define R_USB_IRQ_MASK_CLR__ctl_status__DEFAULT clr -#endif - -/* -** Default values for register R_USB_IRQ_MASK_CLR_DEV -*/ - -/* clr nop */ -#ifndef R_USB_IRQ_MASK_CLR_DEV__out_eot__DEFAULT -#define R_USB_IRQ_MASK_CLR_DEV__out_eot__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__DEFAULT -#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__DEFAULT -#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__DEFAULT -#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__DEFAULT -#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_USB_IRQ_MASK_CLR_DEV__epid_attn__DEFAULT -#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_USB_IRQ_MASK_CLR_DEV__sof__DEFAULT -#define R_USB_IRQ_MASK_CLR_DEV__sof__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_USB_IRQ_MASK_CLR_DEV__port_status__DEFAULT -#define R_USB_IRQ_MASK_CLR_DEV__port_status__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_USB_IRQ_MASK_CLR_DEV__ctl_status__DEFAULT -#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__DEFAULT clr -#endif - -/* -** Default values for register R_USB_IRQ_MASK_SET -*/ - -/* set nop */ -#ifndef R_USB_IRQ_MASK_SET__iso_eof__DEFAULT -#define R_USB_IRQ_MASK_SET__iso_eof__DEFAULT set -#endif - -/* set nop */ -#ifndef R_USB_IRQ_MASK_SET__intr_eof__DEFAULT -#define R_USB_IRQ_MASK_SET__intr_eof__DEFAULT set -#endif - -/* set nop */ -#ifndef R_USB_IRQ_MASK_SET__iso_eot__DEFAULT -#define R_USB_IRQ_MASK_SET__iso_eot__DEFAULT set -#endif - -/* set nop */ -#ifndef R_USB_IRQ_MASK_SET__intr_eot__DEFAULT -#define R_USB_IRQ_MASK_SET__intr_eot__DEFAULT set -#endif - -/* set nop */ -#ifndef R_USB_IRQ_MASK_SET__ctl_eot__DEFAULT -#define R_USB_IRQ_MASK_SET__ctl_eot__DEFAULT set -#endif - -/* set nop */ -#ifndef R_USB_IRQ_MASK_SET__bulk_eot__DEFAULT -#define R_USB_IRQ_MASK_SET__bulk_eot__DEFAULT set -#endif - -/* set nop */ -#ifndef R_USB_IRQ_MASK_SET__epid_attn__DEFAULT -#define R_USB_IRQ_MASK_SET__epid_attn__DEFAULT set -#endif - -/* set nop */ -#ifndef R_USB_IRQ_MASK_SET__sof__DEFAULT -#define R_USB_IRQ_MASK_SET__sof__DEFAULT set -#endif - -/* set nop */ -#ifndef R_USB_IRQ_MASK_SET__port_status__DEFAULT -#define R_USB_IRQ_MASK_SET__port_status__DEFAULT set -#endif - -/* set nop */ -#ifndef R_USB_IRQ_MASK_SET__ctl_status__DEFAULT -#define R_USB_IRQ_MASK_SET__ctl_status__DEFAULT set -#endif - -/* -** Default values for register R_USB_IRQ_MASK_SET_DEV -*/ - -/* set nop */ -#ifndef R_USB_IRQ_MASK_SET_DEV__out_eot__DEFAULT -#define R_USB_IRQ_MASK_SET_DEV__out_eot__DEFAULT set -#endif - -/* set nop */ -#ifndef R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__DEFAULT -#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__DEFAULT set -#endif - -/* set nop */ -#ifndef R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__DEFAULT -#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__DEFAULT set -#endif - -/* set nop */ -#ifndef R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__DEFAULT -#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__DEFAULT set -#endif - -/* set nop */ -#ifndef R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__DEFAULT -#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__DEFAULT set -#endif - -/* set nop */ -#ifndef R_USB_IRQ_MASK_SET_DEV__epid_attn__DEFAULT -#define R_USB_IRQ_MASK_SET_DEV__epid_attn__DEFAULT set -#endif - -/* set nop */ -#ifndef R_USB_IRQ_MASK_SET_DEV__sof__DEFAULT -#define R_USB_IRQ_MASK_SET_DEV__sof__DEFAULT set -#endif - -/* set nop */ -#ifndef R_USB_IRQ_MASK_SET_DEV__port_status__DEFAULT -#define R_USB_IRQ_MASK_SET_DEV__port_status__DEFAULT set -#endif - -/* set nop */ -#ifndef R_USB_IRQ_MASK_SET_DEV__ctl_status__DEFAULT -#define R_USB_IRQ_MASK_SET_DEV__ctl_status__DEFAULT set -#endif - -/* -** Default values for register R_USB_PORT1_DISABLE -*/ - -/* yes no */ -#ifndef R_USB_PORT1_DISABLE__disable__DEFAULT -#define R_USB_PORT1_DISABLE__disable__DEFAULT yes -#endif - -/* -** Default values for register R_USB_PORT2_DISABLE -*/ - -/* yes no */ -#ifndef R_USB_PORT2_DISABLE__disable__DEFAULT -#define R_USB_PORT2_DISABLE__disable__DEFAULT yes -#endif - -/* -** Default values for register R_VECT_MASK_CLR -*/ - -/* clr nop */ -#ifndef R_VECT_MASK_CLR__usb__DEFAULT -#define R_VECT_MASK_CLR__usb__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_VECT_MASK_CLR__dma9__DEFAULT -#define R_VECT_MASK_CLR__dma9__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_VECT_MASK_CLR__dma8__DEFAULT -#define R_VECT_MASK_CLR__dma8__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_VECT_MASK_CLR__dma7__DEFAULT -#define R_VECT_MASK_CLR__dma7__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_VECT_MASK_CLR__dma6__DEFAULT -#define R_VECT_MASK_CLR__dma6__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_VECT_MASK_CLR__dma5__DEFAULT -#define R_VECT_MASK_CLR__dma5__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_VECT_MASK_CLR__dma4__DEFAULT -#define R_VECT_MASK_CLR__dma4__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_VECT_MASK_CLR__dma3__DEFAULT -#define R_VECT_MASK_CLR__dma3__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_VECT_MASK_CLR__dma2__DEFAULT -#define R_VECT_MASK_CLR__dma2__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_VECT_MASK_CLR__dma1__DEFAULT -#define R_VECT_MASK_CLR__dma1__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_VECT_MASK_CLR__dma0__DEFAULT -#define R_VECT_MASK_CLR__dma0__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_VECT_MASK_CLR__ext_dma1__DEFAULT -#define R_VECT_MASK_CLR__ext_dma1__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_VECT_MASK_CLR__ext_dma0__DEFAULT -#define R_VECT_MASK_CLR__ext_dma0__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_VECT_MASK_CLR__pa__DEFAULT -#define R_VECT_MASK_CLR__pa__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_VECT_MASK_CLR__irq_intnr__DEFAULT -#define R_VECT_MASK_CLR__irq_intnr__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_VECT_MASK_CLR__sw__DEFAULT -#define R_VECT_MASK_CLR__sw__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_VECT_MASK_CLR__serial__DEFAULT -#define R_VECT_MASK_CLR__serial__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_VECT_MASK_CLR__snmp__DEFAULT -#define R_VECT_MASK_CLR__snmp__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_VECT_MASK_CLR__network__DEFAULT -#define R_VECT_MASK_CLR__network__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_VECT_MASK_CLR__scsi1__DEFAULT -#define R_VECT_MASK_CLR__scsi1__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_VECT_MASK_CLR__scsi0__DEFAULT -#define R_VECT_MASK_CLR__scsi0__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_VECT_MASK_CLR__timer1__DEFAULT -#define R_VECT_MASK_CLR__timer1__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_VECT_MASK_CLR__timer0__DEFAULT -#define R_VECT_MASK_CLR__timer0__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_VECT_MASK_CLR__nmi__DEFAULT -#define R_VECT_MASK_CLR__nmi__DEFAULT clr -#endif - -/* clr nop */ -#ifndef R_VECT_MASK_CLR__some__DEFAULT -#define R_VECT_MASK_CLR__some__DEFAULT clr -#endif - -/* -** Default values for register R_VECT_MASK_SET -*/ - -/* set nop */ -#ifndef R_VECT_MASK_SET__usb__DEFAULT -#define R_VECT_MASK_SET__usb__DEFAULT set -#endif - -/* set nop */ -#ifndef R_VECT_MASK_SET__dma9__DEFAULT -#define R_VECT_MASK_SET__dma9__DEFAULT set -#endif - -/* set nop */ -#ifndef R_VECT_MASK_SET__dma8__DEFAULT -#define R_VECT_MASK_SET__dma8__DEFAULT set -#endif - -/* set nop */ -#ifndef R_VECT_MASK_SET__dma7__DEFAULT -#define R_VECT_MASK_SET__dma7__DEFAULT set -#endif - -/* set nop */ -#ifndef R_VECT_MASK_SET__dma6__DEFAULT -#define R_VECT_MASK_SET__dma6__DEFAULT set -#endif - -/* set nop */ -#ifndef R_VECT_MASK_SET__dma5__DEFAULT -#define R_VECT_MASK_SET__dma5__DEFAULT set -#endif - -/* set nop */ -#ifndef R_VECT_MASK_SET__dma4__DEFAULT -#define R_VECT_MASK_SET__dma4__DEFAULT set -#endif - -/* set nop */ -#ifndef R_VECT_MASK_SET__dma3__DEFAULT -#define R_VECT_MASK_SET__dma3__DEFAULT set -#endif - -/* set nop */ -#ifndef R_VECT_MASK_SET__dma2__DEFAULT -#define R_VECT_MASK_SET__dma2__DEFAULT set -#endif - -/* set nop */ -#ifndef R_VECT_MASK_SET__dma1__DEFAULT -#define R_VECT_MASK_SET__dma1__DEFAULT set -#endif - -/* set nop */ -#ifndef R_VECT_MASK_SET__dma0__DEFAULT -#define R_VECT_MASK_SET__dma0__DEFAULT set -#endif - -/* set nop */ -#ifndef R_VECT_MASK_SET__ext_dma1__DEFAULT -#define R_VECT_MASK_SET__ext_dma1__DEFAULT set -#endif - -/* set nop */ -#ifndef R_VECT_MASK_SET__ext_dma0__DEFAULT -#define R_VECT_MASK_SET__ext_dma0__DEFAULT set -#endif - -/* set nop */ -#ifndef R_VECT_MASK_SET__pa__DEFAULT -#define R_VECT_MASK_SET__pa__DEFAULT set -#endif - -/* set nop */ -#ifndef R_VECT_MASK_SET__irq_intnr__DEFAULT -#define R_VECT_MASK_SET__irq_intnr__DEFAULT set -#endif - -/* set nop */ -#ifndef R_VECT_MASK_SET__sw__DEFAULT -#define R_VECT_MASK_SET__sw__DEFAULT set -#endif - -/* set nop */ -#ifndef R_VECT_MASK_SET__serial__DEFAULT -#define R_VECT_MASK_SET__serial__DEFAULT set -#endif - -/* set nop */ -#ifndef R_VECT_MASK_SET__snmp__DEFAULT -#define R_VECT_MASK_SET__snmp__DEFAULT set -#endif - -/* set nop */ -#ifndef R_VECT_MASK_SET__network__DEFAULT -#define R_VECT_MASK_SET__network__DEFAULT set -#endif - -/* set nop */ -#ifndef R_VECT_MASK_SET__scsi1__DEFAULT -#define R_VECT_MASK_SET__scsi1__DEFAULT set -#endif - -/* set nop */ -#ifndef R_VECT_MASK_SET__scsi0__DEFAULT -#define R_VECT_MASK_SET__scsi0__DEFAULT set -#endif - -/* set nop */ -#ifndef R_VECT_MASK_SET__timer1__DEFAULT -#define R_VECT_MASK_SET__timer1__DEFAULT set -#endif - -/* set nop */ -#ifndef R_VECT_MASK_SET__timer0__DEFAULT -#define R_VECT_MASK_SET__timer0__DEFAULT set -#endif - -/* set nop */ -#ifndef R_VECT_MASK_SET__nmi__DEFAULT -#define R_VECT_MASK_SET__nmi__DEFAULT set -#endif - -/* set nop */ -#ifndef R_VECT_MASK_SET__some__DEFAULT -#define R_VECT_MASK_SET__some__DEFAULT set -#endif - -/* -** Default values for register R_WAITSTATES -*/ - -/* 0 - 3 */ -#ifndef R_WAITSTATES__pcs4_7_zw__DEFAULT -#define R_WAITSTATES__pcs4_7_zw__DEFAULT 0 -#endif - -/* 0 - 3 */ -#ifndef R_WAITSTATES__pcs4_7_ew__DEFAULT -#define R_WAITSTATES__pcs4_7_ew__DEFAULT 0 -#endif - -/* 0 - 15 */ -#ifndef R_WAITSTATES__pcs4_7_lw__DEFAULT -#define R_WAITSTATES__pcs4_7_lw__DEFAULT 0 -#endif - -/* 0 - 3 */ -#ifndef R_WAITSTATES__pcs0_3_zw__DEFAULT -#define R_WAITSTATES__pcs0_3_zw__DEFAULT 0 -#endif - -/* 0 - 3 */ -#ifndef R_WAITSTATES__pcs0_3_ew__DEFAULT -#define R_WAITSTATES__pcs0_3_ew__DEFAULT 0 -#endif - -/* 0 - 15 */ -#ifndef R_WAITSTATES__pcs0_3_lw__DEFAULT -#define R_WAITSTATES__pcs0_3_lw__DEFAULT 0 -#endif - -/* 0 - 3 */ -#ifndef R_WAITSTATES__sram_zw__DEFAULT -#define R_WAITSTATES__sram_zw__DEFAULT 0 -#endif - -/* 0 - 3 */ -#ifndef R_WAITSTATES__sram_ew__DEFAULT -#define R_WAITSTATES__sram_ew__DEFAULT 0 -#endif - -/* 0 - 15 */ -#ifndef R_WAITSTATES__sram_lw__DEFAULT -#define R_WAITSTATES__sram_lw__DEFAULT 0 -#endif - -/* 0 - 3 */ -#ifndef R_WAITSTATES__flash_zw__DEFAULT -#define R_WAITSTATES__flash_zw__DEFAULT 0 -#endif - -/* 0 - 3 */ -#ifndef R_WAITSTATES__flash_ew__DEFAULT -#define R_WAITSTATES__flash_ew__DEFAULT 0 -#endif - -/* 0 - 15 */ -#ifndef R_WAITSTATES__flash_lw__DEFAULT -#define R_WAITSTATES__flash_lw__DEFAULT 0 -#endif - -/* -** Default values for register R_WATCHDOG -*/ - -/* 0 - 7 */ -#ifndef R_WATCHDOG__key__DEFAULT -#define R_WATCHDOG__key__DEFAULT 0 -#endif - -/* start stop */ -#ifndef R_WATCHDOG__enable__DEFAULT -#define R_WATCHDOG__enable__DEFAULT start -#endif - -/********************** TYPE DEFINITION SECTION ************************/ - -/********************** LOCAL FUNCTION DECLARATION SECTION *************/ - -/********************** GLOBAL VARIABLE DECLARATION SECTION ************/ - -/********************** FUNCTION DEFINITION SECTION ********************/ - -#endif diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/src/hwregs_int.h b/target/linux/etrax-2.6/image/e100boot/src/cbl/src/hwregs_int.h deleted file mode 100644 index 5688a76a81..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/cbl/src/hwregs_int.h +++ /dev/null @@ -1,25386 +0,0 @@ -/*!********************************************************************** -*! -*! FILE NAME: hwregs_int.h -*! -*! DESCRIPTION: Internal shadow register implementation. -*! Not intended for general use. -*! This file is include in hwregs.h -*! -*! FUNCTIONS: none -*! -*! NOTE: This file is automatically generated, do _not_ edit. -*! Created: Thu Oct 3 01:21:27 2002 -*! By: Id: shadow_gen,v 1.14 2002/10/02 20:31:22 hp Exp -*! From: /n/asic/projects/etrax_ng/doc/work/etrax_ng_regs.rd 1.168 -*! /n/asic/projects/etrax_ng/include//hwregs.ctrl 1.3 -*! -*! MACROS: REG_INITIATED -*! REG_CHECK_INIT -*! REG_ICHECK_INIT -*! REG_CHECK_INR -*! REG_VAL_VAL -*! REG_SVAL -*! REG_SVAL_ZERO -*! REG_SVAL_SHADOW -*! REG_SVAL_I -*! REG_SVAL_I_ZERO -*! REG_SVAL_I_SHADOW -*! -*! REG_IMASK -*! REG_ADDR_I -*! REG_SADDR_I -*! REG_IADDR_I -*! REG_VAL_ENUM -*! REG_GET_WO -*! REG_GET_RO -*! REG_GET_RW -*! REG_IGET_WO -*! REG_IGET_RO -*! REG_IGET_RW -*! REG_SET_WO -*! REG_ISET_WO -*! REG_SET_VAL_WO -*! REG_SET_RW -*! REG_ISET_RW -*! REG_SET_VAL_RW -*! REG_EQL_WO -*! REG_EQL_RO -*! REG_EQL_RW -*! REG_IEQL_WO -*! REG_IEQL_RO -*! REG_IEQL_RW -*! REG_RD_WO -*! REG_RD_RO -*! REG_RD_RW -*! REG_IRD_WO -*! REG_IRD_RO -*! REG_IRD_RW -*! REG_WR_WO -*! REG_WR_RW -*! REG_IWR_WO -*! REG_IWR_RW -*! -*!---------------------------------------------------------------------- -*! HISTORY -*! -*! DATE NAME CHANGES -*! ---- ---- ------- -*! Apr 01 1998 Jan Bengtsson Initial version -*! Oct 01 2002 Hans-Peter Nilsson Large mechanical changes to correct -*! use of the ## operator. -*!---------------------------------------------------------------------- -*! -*! (C) Copyright 1998, 2002 Axis Communications AB, LUND, SWEDEN -*! -*!**********************************************************************/ -/* %Z% %M% %I% %G% */ - -#ifndef __HWREGS_INT_H__ -#define __HWREGS_INT_H__ - -/********************** INCLUDE FILES SECTION **************************/ - -/********************** CONSTANT AND MACRO SECTION *********************/ -#ifndef __REG_GENERAL_INT_H__ -#define __REG_GENERAL_INT_H__ - -/* -** The first part of hwregs_int.h is common to all shadow -** register modules, and should therefore only be included once to -** avoid macro redefinitions. -*/ - -#if REG_DEBUG && !defined(__ASSEMBLER__) - -#ifndef REG_SERROR -#define REG_SERROR(ok,reg) \ - assert( ok ), -#endif - -#ifndef REG_VERROR -#define REG_VERROR(ok,val) \ - assert( ok ), -#endif - -#ifndef REG_IERROR -#define REG_IERROR(ok,i,reg) \ - assert( ok ), -#endif - -/*#********************************************************************** -*# -*# MACRO NAME : REG_INITIATED -*# -*# PARAMETERS : reg_ : Name of a register, with "_" appended. -*# -*# RETURNS : 0 -*# -*# SIDE EFFECTS: Clears initiated flag in reg_initiated_type struct. -*# -*# DESCRIPTION : Clears initiated flag in reg_initiated_type struct. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Parameter now has "_" appended. -*#**********************************************************************/ - -#define REG_INITIATED(reg_) \ - *reg_##_IADDR = 0, - -/*#********************************************************************** -*# -*# MACRO NAME : REG_CHECK_INIT -*# -*# PARAMETERS : reg_ : Name of a register, with "_" appended. -*# -*# RETURNS : Value of REG_SERROR macro. -*# -*# SIDE EFFECTS: Evaluates REG_SERROR macro. -*# -*# DESCRIPTION : Check that shadow is initiated, by -*# evaluating REG_SERROR macro. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Parameter now has "_" appended. -*# Correct stringization. -*#**********************************************************************/ - -#define REG_CHECK_INIT(reg_) \ - REG_SERROR(*reg_##_IADDR == 0, #reg_) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_ICHECK_INIT -*# -*# PARAMETERS : i : Interface number. -*# reg_: Name of a register, with "_" appended. -*# -*# RETURNS : Value of REG_SERROR macro. -*# -*# SIDE EFFECTS: Evaluates REG_SERROR macro. -*# -*# DESCRIPTION : Check that shadow is initiated, by -*# evaluating REG_SERROR macro. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Reg parameter now has "_" appended. -*# Correct stringization. -*#**********************************************************************/ - -#define REG_ICHECK_INIT(i, reg_) \ - REG_SERROR(*REG_IADDR_I(i, reg_) == 0, #reg_) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_CHECK_INR -*# -*# PARAMETERS : i : Interface number. -*# reg_: Name of a register, with "_" appended. -*# -*# RETURNS : Value of REG_IERROR macro. -*# -*# SIDE EFFECTS: Evaluates REG_IERROR macro. -*# -*# DESCRIPTION : Check that interface number is valid. -*# If an invalid interface number is found at compile -*# time gcc report the following warning: -*# 'warning: right shift count >= width of type' -*# If an invalid interface number is found at run time -*# the REG_IERROR macro is evaluated. -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Reg parameter now has "_" appended. -*# Correct stringization. -*#**********************************************************************/ - -#define REG_CHECK_INR(i, reg_) \ - REG_IERROR( \ - 1 >> ( \ - ( \ - (udword)(~(i)) > (udword)(~(reg_##_FIRST)) || \ - (udword)(i) > (udword)(reg_##_LAST) \ - ) ? 32 : 0 \ - ), \ - i, #reg_ \ - ) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL_VAL -*# -*# PARAMETERS : reg_ : Name of a register, with "_" appended. -*# field_: Name of a field, with "_" appended. -*# val : Integer value -*# -*# RETURNS : val -*# -*# SIDE EFFECTS: Evaluate REG_VERROR macro. -*# -*# DESCRIPTION : Check that an integer value is within field range. -*# If val parameter is found to be out of range at compile -*# time gcc report the following warning: -*# 'left shift count >= width of type' -*# If an invalid integer value is found at run time -*# the REG_VERROR macro is evaluated. -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Reg and field name parameters now -*# have "_" appended. -*#**********************************************************************/ - -#define REG_VAL_VAL(reg_, field_, val) ( \ - REG_VERROR( \ - 1 << ( \ - ( \ - (udword)(~(val)) > (udword)(~(reg_##_##field_##_MIN)) || \ - (udword)(val) > (udword)(reg_##_##field_##_MAX) \ - ) ? 32 : 0 \ - ), \ - val \ - ) \ - val \ -) - -#else /* ! REG_DEBUG || __ASSEMBER__ */ - -/* Checks only done in debug mode. */ -/* No need for REG_VERROR, REG_SERROR, and REG_IERROR. */ - -#define REG_INITIATED(reg) -#define REG_CHECK_INIT(reg) -#define REG_ICHECK_INIT(i,reg) -#define REG_CHECK_INR(i,reg) -#define REG_VAL_VAL(reg,field,val) (val) - -#endif - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SVAL -*# -*# PARAMETERS : reg_ : Name of a register, with "_" appended. -*# -*# RETURNS : Value of shadow register associated with a WO register, -*# or 0. -*# -*# SIDE EFFECTS: None -*# -*# DESCRIPTION : Read contents of a shadow register. By using this macro -*# it's possible to force special values for some registers, -*# e.g. zero for set/clr registers. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Reg parameter now has "_" appended. -*#**********************************************************************/ -#define REG_SVAL(reg_) ( \ - reg_##_SVAL(reg_) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SVAL_ZERO -*# -*# PARAMETERS : reg : Name of a register. -*# -*# RETURNS : Zero. -*# -*# SIDE EFFECTS: None -*# -*# DESCRIPTION : Force contents of shadow register to zero, used by -*# the set/clr registers. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*#**********************************************************************/ -#define REG_SVAL_ZERO(reg) ( \ - 0 \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SVAL_SHADOW -*# -*# PARAMETERS : reg_ : Name of a register, with "_" appended. -*# -*# RETURNS : Value of shadow register associated with a WO register. -*# -*# SIDE EFFECTS: None -*# -*# DESCRIPTION : Read shadow register contents. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Reg parameter now has "_" appended. -*#**********************************************************************/ -#define REG_SVAL_SHADOW(reg_) ( \ - *reg_##_SADDR \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SVAL_I -*# -*# PARAMETERS : reg_ : Name of a register, with "_" appended. -*# i : Interface number. -*# -*# RETURNS : Value of shadow register associated with a WO register, -*# or 0, for interface i. -*# -*# SIDE EFFECTS: None -*# -*# DESCRIPTION : Read contents of a shadow register. By using this macro -*# it's possible to force special values for some registers, -*# e.g. zero for set/clr registers. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Reg parameter now has "_" appended. -*#**********************************************************************/ -#define REG_SVAL_I(i, reg_) ( \ - reg_##_SVAL_I(i, reg_) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SVAL_I_ZERO -*# -*# PARAMETERS : reg_ : Name of a register, with "_" appended. -*# i : Interface number. -*# -*# RETURNS : Zero. -*# -*# SIDE EFFECTS: None -*# -*# DESCRIPTION : Force contents of shadow register to zero, used by -*# the set/clr registers, for interface i. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Reg parameter now has "_" appended. -*#**********************************************************************/ -#define REG_SVAL_I_ZERO(i,reg) ( \ - 0 \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SVAL_I_SHADOW -*# -*# PARAMETERS : reg_ : Name of a register. -*# i : Interface number. -*# -*# RETURNS : Value of shadow register associated with a WO register, -*# for interface i. -*# -*# SIDE EFFECTS: None -*# -*# DESCRIPTION : Read shadow register contents, of interface i. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Reg parameter now has "_" appended. -*#**********************************************************************/ -#define REG_SVAL_I_SHADOW(i, reg_) ( \ - *REG_SADDR_I(i, reg_) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_IMASK -*# -*# PARAMETERS : reg_ : Name of a register, with "_" appended. -*# field_ : Name of a field, with "_" appended. -*# -*# RETURNS : Inverse of field mask. -*# -*# SIDE EFFECTS: none -*# -*# DESCRIPTION : Create a mask with zeros matching the field, -*# and ones matching the rest. -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Reg and field name parameters now -*# have "_" appended. -*#**********************************************************************/ - -#define REG_IMASK(reg_, field_) ( \ - ~reg_##_##field_##_##field_##_MASK \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_ADDR_I -*# -*# PARAMETERS : i : interface number. -*# reg_ : Name of a register, with "_" appended. -*# -*# RETURNS : Address to reg for interface i. -*# -*# SIDE EFFECTS: May evaluate REG_IERROR. -*# -*# DESCRIPTION : Calculate address to reg for interface i. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Reg parameter now has "_" appended. -*#**********************************************************************/ - -#define REG_ADDR_I(i, reg_) ( \ - reg_##_TYPECAST ( \ - REG_CHECK_INR(i, reg_) \ - ((udword) reg_##_ADDR) + reg_##_OFFSET * (i) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SADDR_I -*# -*# PARAMETERS : i : interface number. -*# reg_ : Name of a register, with "_" appended. -*# -*# RETURNS : Address to shadow register for interface i. -*# -*# SIDE EFFECTS: May evaluate REG_IERROR. -*# -*# DESCRIPTION : Calculate address to shadow register for interface i. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Reg parameter now has "_" appended. -*#**********************************************************************/ - -#define REG_SADDR_I(i, reg_) ( \ - reg_##_STYPECAST ( \ - REG_CHECK_INR(i, reg_) \ - ((udword) reg_##_SADDR) + reg_##_SOFFSET * (i) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_IADDR_I -*# -*# PARAMETERS : i : interface number. -*# reg_ : Name of a register, with "_" appended. -*# -*# RETURNS : Address to initiated flag for interface i. -*# -*# SIDE EFFECTS: May evaluate REG_IERROR. -*# -*# DESCRIPTION : Calculate address to initiated flag for interface i. -*# The reg_initiated_type struct has the same layout as -*# the reg_shadow_type struct, i.e. it's possible to use -*# __SOFFSET here to. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Reg parameter now has "_" appended. -*#**********************************************************************/ - -#define REG_IADDR_I(i, reg_) ( \ - reg_##_STYPECAST ( \ - REG_CHECK_INR(i, reg_) \ - ((udword) reg_##_IADDR) + reg_##_SOFFSET * (i) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_VAL_ENUM -*# -*# PARAMETERS : reg_ : Name of a register, with "_" appended. -*# field_: Name of a field, with "_" appended. -*# sym : Symbolic value. -*# -*# RETURNS : Integer value for sym. -*# -*# SIDE EFFECTS: none -*# -*# DESCRIPTION : Convert symbolic value to an integer value. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Reg and field name parameters now -*# have "_" appended. -*#**********************************************************************/ - -#define REG_VAL_ENUM(reg_, field_, sym) ( \ - reg_##_##field_##_##field_##_##sym \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_GET_WO -*# -*# PARAMETERS : reg_ : Name of a register, with "_" appended. -*# field_ : Name of a field, with "_" appended. -*# -*# RETURNS : Value of field field in register reg. -*# -*# SIDE EFFECTS: May evaluate REG_SERROR. -*# -*# DESCRIPTION : Read a field in a write only shadow register, -*# i.e. from the shadow register. If the shadow register -*# isn't initiated the REG_SERROR macro is evaluated. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Reg and field name parameters now -*# have "_" appended. -*#**********************************************************************/ - -#define REG_GET_WO(reg_, field_) ( \ - REG_CHECK_INIT(reg_) \ - (REG_SVAL(reg_) & reg_##_##field_##_##field_##_MASK) >> \ - reg_##_##field_##_BITNR \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_GET_RO, REG_GET_RW -*# -*# PARAMETERS : reg_ : Name of a register, with "_" appended. -*# field_ : Name of a field, with "_" appended. -*# -*# RETURNS : Value of field field in register reg. -*# -*# SIDE EFFECTS: none -*# -*# DESCRIPTION : Read a field in a read only or read write shadow register. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Reg and field name parameters now -*# have "_" appended. -*#**********************************************************************/ - -#define REG_GET_RO(reg_, field_) ( \ - (reg_##_READ(reg_##_ADDR) & reg_##_##field_##_##field_##_MASK) >> \ - reg_##_##field_##_BITNR \ -) - -#define REG_GET_RW REG_GET_RO - -/*#********************************************************************** -*# -*# MACRO NAME : REG_IGET_WO -*# -*# PARAMETERS : i : Interface number. -*# reg_ : Name of a register, with "_" appended. -*# field_: Name of a field, with "_" appended. -*# -*# RETURNS : Value of field field in register reg. -*# -*# SIDE EFFECTS: May evaluate REG_SERROR, and REG_IERROR. -*# -*# DESCRIPTION : Read a field in a write only register for interface i, -*# i.e. from the shadow register. If the shadow register -*# isn't initiated the REG_SERROR macro is evaluated, -*# and if i is out of range REG_IERROR is evaluated. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Reg and field name parameters now -*# have "_" appended. -*#**********************************************************************/ - -#define REG_IGET_WO(i, reg_, field_) ( \ - REG_ICHECK_INIT(i, reg_) \ - (REG_SVAL_I(i, reg_) & reg_##_##field_##_##field_##_MASK) >> \ - reg_##_##field_##_BITNR \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_IGET_RO, REG_IGET_RW -*# -*# PARAMETERS : i : Interface number. -*# reg_ : Name of a register, with "_" appended. -*# field_: Name of a field, with "_" appended. -*# -*# RETURNS : Value of field field in register reg. -*# -*# SIDE EFFECTS: May evaluate REG_IERROR. -*# -*# DESCRIPTION : Read a field in a read only or read write register for -*# interface i. If i is out of range REG_IERROR is evaluated. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Reg and field name parameters now -*# have "_" appended. -*#**********************************************************************/ - -#define REG_IGET_RO(i, reg_, field_) ( \ - (reg_##_READ(REG_ADDR_I(i, reg_) ) & \ - reg_##_##field_##_##field_##_MASK) >> reg_##_##field_##_BITNR \ -) - -#define REG_IGET_RW REG_IGET_RO - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET_WO -*# -*# PARAMETERS : reg_ : Name of a register, with "_" appended. -*# field_: Name of a field, with "_" appended. -*# val : Value to write to field. -*# -*# RETURNS : Integer value written to complete register. -*# -*# SIDE EFFECTS: May evaluate REG_SERROR and REG_VERROR. -*# -*# DESCRIPTION : Write val parameter to field field in write only register -*# reg and in the shadow register. If the shadow register -*# isn't initiated REG_SERROR is evaluated, and if the -*# val parameter is out of range REG_VERROR is evaluated. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Reg and field name parameters now -*# have "_" appended. -*#**********************************************************************/ - -#define REG_SET_WO(reg_, field_, val) ( \ - *reg_##_SADDR = ( \ - REG_CHECK_INIT(reg_) \ - (REG_SVAL(reg_) & REG_IMASK(reg_, field_)) | \ - (reg_##_##field_##_##field_##_VAL(reg_, field_, val) << \ - reg_##_##field_##_BITNR) \ - ), \ - reg_##_WRITE(reg_##_ADDR, *reg_##_SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_ISET_WO -*# -*# PARAMETERS : i : Interface number. -*# reg_ : Name of a register, with "_" appended. -*# field_: Name of a field, with "_" appended. -*# val : Value to write to field. -*# -*# RETURNS : Integer value written to complete register. -*# -*# SIDE EFFECTS: May evaluate REG_IERROR, REG_SERROR, and REG_VERROR. -*# -*# DESCRIPTION : Write val parameter to field field in write only register -*# reg of interface i and in the shadow register. If the -*# shadow register isn't initiated REG_SERROR is evaluated, -*# and if the val parameter is out of range REG_VERROR is -*# evaluated, and if the interface number is out of range -*# REG_IERROR is evaluated. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Reg and field name parameters now -*# have "_" appended. -*#**********************************************************************/ - -#define REG_ISET_WO(i, reg_, field_, val) ( \ - *REG_SADDR_I(i, reg_) = ( \ - REG_ICHECK_INIT(i, reg_) \ - (REG_SVAL_I(i, reg_) & REG_IMASK(reg_, field_)) | \ - (reg_##_##field_##_##field_##_VAL(reg_, field_, val) << \ - reg_##_##field_##_BITNR) \ - ), \ - reg_##_WRITE(REG_ADDR_I(i, reg_), *REG_SADDR_I(i, reg_)) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET_VAL_WO -*# -*# PARAMETERS : reg_ : Name of a register, with "_" appended. -*# field_: Name of a field, with "_" appended. -*# val : Integer value to write to symbolic field. -*# -*# RETURNS : Integer value written to complete register. -*# -*# SIDE EFFECTS: May evaluate REG_SERROR and REG_VERROR. -*# -*# DESCRIPTION : Write val parameter to field field in write only register -*# reg and in the shadow register. If the shadow register -*# isn't initiated REG_SERROR is evaluated, and if the -*# val parameter is out of range REG_VERROR is evaluated. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Reg and field name parameters now -*# have "_" appended. -*#**********************************************************************/ - -#define REG_SET_VAL_WO(reg_, field_, val) ( \ - *reg_##_SADDR = ( \ - REG_CHECK_INIT(reg_) \ - (REG_SVAL(reg_) & REG_IMASK(reg_, field_)) | \ - (REG_VAL_VAL(reg_, field_, val) << reg_##_##field_##_BITNR) \ - ), \ - reg_##_WRITE(reg_##_ADDR, *reg_##_SADDR) \ -) - -/*#********************************************************************** -*# Can't write to a read only register, i.e. NO REG_SET_RO, REG_ISET_RO, -*# and REG_SET_VAL_RO macros. -*#**********************************************************************/ - - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET_RW -*# -*# PARAMETERS : reg_ : Name of a register, with "_" appended. -*# field_: Name of a field, with "_" appended. -*# val : Value to write to field. -*# -*# RETURNS : Integer value written to complete register. -*# -*# SIDE EFFECTS: May evaluate REG_VERROR. -*# -*# DESCRIPTION : Write val parameter to field field in read write register -*# reg. If the val parameter is out of range REG_VERROR is -*# evaluated. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Reg and field name parameters now -*# have "_" appended. -*#**********************************************************************/ - -#define REG_SET_RW(reg_, field_, val) ( \ - reg_##_WRITE(reg_##_ADDR, ( \ - (reg_##_READ(reg_##_ADDR) & REG_IMASK(reg_, field_)) | \ - (reg_##_##field_##_##field_##_VAL(reg_, field_, val) << \ - reg_##_##field_##_BITNR) ) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_ISET_RW -*# -*# PARAMETERS : i : Interface number. -*# reg_ : Name of a register, with "_" appended. -*# field_: Name of a field, with "_" appended. -*# val : Value to write to field. -*# -*# RETURNS : Integer value written to complete register. -*# -*# SIDE EFFECTS: May evaluate REG_VERROR and REG_IERROR. -*# -*# DESCRIPTION : Write val parameter to field field in read write register -*# reg of interface i. If the val parameter is out of range -*# REG_VERROR is evaluated, and if the interface number is -*# out of range REG_IERROR is evaluated. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Reg and field name parameters now -*# have "_" appended. -*#**********************************************************************/ - -#define REG_ISET_RW(i, reg_, field_, val) ( \ - reg_##_WRITE(REG_ADDR_I(i, reg_), ( \ - (reg_##_READ(REG_ADDR_I(i, reg_)) & REG_IMASK(reg_, field_))\ - | (reg_##_##field_##_##field_##_VAL(reg_, field_, val) << \ - reg_##_##field_##_BITNR) ) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_SET_VAL_RW -*# -*# PARAMETERS : reg_ : Name of a register, with "_" appended. -*# field_: Name of a field, with "_" appended. -*# val : Integer value to write to symbolic field. -*# -*# RETURNS : Integer value written to complete register. -*# -*# SIDE EFFECTS: May evaluate REG_VERROR. -*# -*# DESCRIPTION : Write val parameter to field field in read write register -*# reg. If the val parameter is out of range REG_VERROR is -*# evaluated. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Reg and field name parameters now -*# have "_" appended. -*#**********************************************************************/ - -#define REG_SET_VAL_RW(reg_, field_, val) ( \ - reg_##_WRITE(reg_##_ADDR, ( \ - (reg_##_READ(reg_##_ADDR) & REG_IMASK(reg_, field_)) | \ - (REG_VAL_VAL(reg_, field_, val) << reg_##_##field_##_BITNR) ) \ - ) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_EQL_WO -*# -*# PARAMETERS : reg_ : Name of a register, with "_" appended. -*# field_: Name of a field, with "_" appended. -*# val : Value to compare with field. -*# -*# RETURNS : TRUE, FALSE -*# -*# SIDE EFFECTS: May evaluate REG_SERROR and REG_VERROR. -*# -*# DESCRIPTION : Compare val parameter with field field in write only -*# register reg. If the val parameter is out of range -*# REG_VERROR is evaluated, and if the shadow register -*# isn't initiated REG_SERROR is evaluated. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Reg and field name parameters now -*# have "_" appended. -*#**********************************************************************/ - -#define REG_EQL_WO(reg_, field_, val) ( \ - REG_CHECK_INIT(reg_) \ - ( (REG_SVAL(reg_) & reg_##_##field_##_##field_##_MASK) >> \ - reg_##_##field_##_BITNR \ - ) == reg_##_##field_##_##field_##_VAL(reg_, field_, val) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_EQL_RO, REG_EQL_RW -*# -*# PARAMETERS : reg_ : Name of a register, with "_" appended. -*# field_: Name of a field, with "_" appended. -*# val : Value to compare with field. -*# -*# RETURNS : TRUE, FALSE -*# -*# SIDE EFFECTS: May evaluate REG_VERROR. -*# -*# DESCRIPTION : Compare val parameter with field field in read only -*# or read write register reg. If the val parameter is -*# out of range REG_VERROR is evaluated. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Reg and field name parameters now -*# have "_" appended. -*#**********************************************************************/ - -#define REG_EQL_RO(reg_, field_, val) ( \ - ( (reg_##_READ(reg_##_ADDR) & reg_##_##field_##_##field_##_MASK) >> \ - reg_##_##field_##_BITNR \ - ) == reg_##_##field_##_##field_##_VAL(reg_, field_, val) \ -) - -#define REG_EQL_RW REG_EQL_RO - -/*#********************************************************************** -*# -*# MACRO NAME : REG_IEQL_WO -*# -*# PARAMETERS : i : Interface number. -*# reg_ : Name of a register, with "_" appended. -*# field_: Name of a field, with "_" appended. -*# val : Value to compare with field. -*# -*# RETURNS : TRUE, FALSE -*# -*# SIDE EFFECTS: May evaluate REG_VERROR, REG_IERROR, and REG_SERROR. -*# -*# DESCRIPTION : Compare val parameter with field field in write only -*# register reg of interface i. If the val parameter is -*# out of range REG_VERROR is evaluated, and if the -*# interface number is out of range REG_IERROR is evaluated, -*# and if the shadow register isn't initiated REG_SERROR -*# is evaluated. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Reg and field name parameters now -*# have "_" appended. -*#**********************************************************************/ - -#define REG_IEQL_WO(i, reg_, field_, val) ( \ - REG_ICHECK_INIT(i, reg_) \ - ( (REG_SVAL_I(i, reg_) & reg_##_##field_##_##field_##_MASK) >> \ - reg_##_##field_##_BITNR \ - ) == reg_##_##field_##_##field_##_VAL(reg_, field_, val) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_IEQL_RO, REG_IEQL_RW -*# -*# PARAMETERS : i : Interface number. -*# reg_ : Name of a register. -*# field_: Name of a field. -*# val : Value to compare with field. -*# -*# RETURNS : TRUE, FALSE -*# -*# SIDE EFFECTS: May evaluate REG_VERROR and REG_IERROR. -*# -*# DESCRIPTION : Compare val parameter with field field in read only -*# or read write register reg of interface i. If the val -*# parameter is out of range REG_VERROR is evaluated, and -*# if the interface number is out of range REG_IERROR is -*# evaluated. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Reg and field name parameters now -*# have "_" appended. -*#**********************************************************************/ - -#define REG_IEQL_RO(i, reg_, field_, val) ( \ - ( (reg_##_READ(REG_ADDR_I(i, reg_)) & \ - reg_##_##field_##_##field_##_MASK) >> reg_##_##field_##_BITNR \ - ) == reg_##_##field_##_##field_##_VAL(reg_, field_, val) \ -) - -#define REG_IEQL_RW REG_IEQL_RO - -/*#********************************************************************** -*# -*# MACRO NAME : REG_RD_WO -*# -*# PARAMETERS : reg_ : Name of a register, with "_" appended. -*# -*# RETURNS : Contents of register reg. -*# -*# SIDE EFFECTS: May evaluate REG_SERROR. -*# -*# DESCRIPTION : Read contents of write only register reg, i.e. read -*# the shadow register. If the shadow register isn't -*# initiated REG_SERROR is evaluated. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Reg parameter now has "_" appended. -*#**********************************************************************/ - -#define REG_RD_WO(reg_) ( \ - REG_CHECK_INIT(reg_) \ - REG_SVAL(reg_) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_RD_RO, REG_RD_RW -*# -*# PARAMETERS : reg_ : Name of a register, with "_" appended. -*# -*# RETURNS : Contents of register reg. -*# -*# SIDE EFFECTS: none -*# -*# DESCRIPTION : Read contents of read only or read write register reg. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Reg parameter now has "_" appended. -*#**********************************************************************/ - -#define REG_RD_RO(reg_) ( \ - reg_##_READ(reg_##_ADDR) \ -) - -#define REG_RD_RW REG_RD_RO - -/*#********************************************************************** -*# -*# MACRO NAME : REG_IRD_WO -*# -*# PARAMETERS : i : Interface number. -*# reg_ : Name of a register, with "_" appended. -*# -*# RETURNS : Contents of register reg. -*# -*# SIDE EFFECTS: May evaluate REG_SERROR and REG_IERROR. -*# -*# DESCRIPTION : Read contents of write only register reg, i.e. read -*# the shadow register of interface i. If the shadow register -*# isn't initiated REG_SERROR is evaluated, and if the -*# interface number is out of range REG_IERROR is evaluated. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Reg parameter now has "_" appended. -*#**********************************************************************/ - -#define REG_IRD_WO(i, reg_) ( \ - REG_ICHECK_INIT(i, reg_) \ - REG_SVAL_I(i, reg_) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_IRD_RO, REG_IRD_RW -*# -*# PARAMETERS : i : Interface number. -*# reg_ : Name of a register. -*# -*# RETURNS : Contents of register reg. -*# -*# SIDE EFFECTS: none -*# -*# DESCRIPTION : Read contents of read only or read write register reg -*# of interface i. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Reg parameter now has "_" appended. -*#**********************************************************************/ - -#define REG_IRD_RO(i, reg_) ( \ - reg_##_READ(REG_ADDR_I(i, reg_)) \ -) - -#define REG_IRD_RW REG_IRD_RO - -/*#********************************************************************** -*# -*# MACRO NAME : REG_WR_WO -*# -*# PARAMETERS : reg_ : Name of a register, with "_" appended. -*# var : Variable (or value) to write to reg. -*# -*# RETURNS : integer value written to register reg. -*# -*# SIDE EFFECTS: May evaluate REG_SERROR. -*# -*# DESCRIPTION : Write value of var parameter to register reg and to -*# the shadow register. If the shadow register -*# isn't initiated REG_SERROR is evaluated. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Reg parameter now has "_" appended. -*#**********************************************************************/ - -#define REG_WR_WO(reg_, var) ( \ - *reg_##_SADDR = ( \ - REG_CHECK_INIT(reg_) \ - (reg_##_TYPE var) \ - ), \ - reg_##_WRITE(reg_##_ADDR, *reg_##_SADDR) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_WR_RW -*# -*# PARAMETERS : reg_ : Name of a register, with "_" appended. -*# var : Variable (or value) to write to reg. -*# -*# RETURNS : integer value written to register reg. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of var parameter to register reg. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Reg parameter now has "_" appended. -*#**********************************************************************/ - -#define REG_WR_RW(reg_, var) ( \ - reg_##_WRITE(reg_##_ADDR, (reg_##_TYPE (var))) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_IWR_WO -*# -*# PARAMETERS : i : Interface number. -*# reg_ : Name of a register, with "_" appended. -*# var : Variable (or value) to write to reg. -*# -*# RETURNS : integer value written to register reg. -*# -*# SIDE EFFECTS: May evaluate REG_SERROR. -*# -*# DESCRIPTION : Write value of var parameter to register reg and to -*# the shadow register of interface i. If the shadow -*# register isn't initiated REG_SERROR is evaluated. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Reg parameter now has "_" appended. -*#**********************************************************************/ - -#define REG_IWR_WO(i, reg_, var) ( \ - *REG_SADDR_I(i, reg_) = ( \ - REG_ICHECK_INIT(i, reg_) \ - reg_##_TYPE (var) \ - ), \ - reg_##_WRITE(REG_ADDR_I(i, reg_), *REG_SADDR_I(i, reg_)) \ -) - -/*#********************************************************************** -*# -*# MACRO NAME : REG_IWR_RW -*# -*# PARAMETERS : i : Interface number. -*# reg_ : Name of a register. -*# var : Variable (or value) to write to reg. -*# -*# RETURNS : integer value written to register reg. -*# -*# SIDE EFFECTS: None. -*# -*# DESCRIPTION : Write value of var parameter to register reg of -*# interface i. -*# -*#---------------------------------------------------------------------- -*# HISTORY -*# -*# DATE NAME CHANGES -*# ---- ---- ------- -*# Apr 01 1998 Jan Bengtsson Initial version -*# Oct 01 2002 Hans-Peter Nilsson Reg parameter now has "_" appended. -*#**********************************************************************/ - -#define REG_IWR_RW(i, reg_, var) ( \ - reg_##_WRITE(REG_ADDR_I(i, reg_), (reg_##_TYPE (var))) \ -) - -/* - * Can't write to a read only register, i.e. NO REG_WR_RO, REG_IWR_RO - * macros. - */ - -#endif /* __REG_GENERAL_INT_H__ */ - -/* - * R_ALT_SER_BAUDRATE - * - type: WO - * - addr: 0xb000005c - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -#define R_ALT_SER_BAUDRATE__ADDR (REG_TYPECAST_UDWORD 0xb000005c) - -#ifndef REG_NO_SHADOW -#define R_ALT_SER_BAUDRATE__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_ALT_SER_BAUDRATE + 0)) -#define R_ALT_SER_BAUDRATE__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_ALT_SER_BAUDRATE + 0)) -#else /* REG_NO_SHADOW */ -#define R_ALT_SER_BAUDRATE__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_ALT_SER_BAUDRATE__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_ALT_SER_BAUDRATE__STYPECAST REG_STYPECAST_UDWORD -#define R_ALT_SER_BAUDRATE__SVAL REG_SVAL_SHADOW -#define R_ALT_SER_BAUDRATE__SVAL_I REG_SVAL_I_SHADOW -#define R_ALT_SER_BAUDRATE__TYPECAST REG_TYPECAST_UDWORD -#define R_ALT_SER_BAUDRATE__TYPE (REG_UDWORD) -#define R_ALT_SER_BAUDRATE__GET REG_GET_WO -#define R_ALT_SER_BAUDRATE__IGET REG_IGET_WO -#define R_ALT_SER_BAUDRATE__SET REG_SET_WO -#define R_ALT_SER_BAUDRATE__ISET REG_ISET_WO -#define R_ALT_SER_BAUDRATE__SET_VAL REG_SET_VAL_WO -#define R_ALT_SER_BAUDRATE__EQL REG_EQL_WO -#define R_ALT_SER_BAUDRATE__IEQL REG_IEQL_WO -#define R_ALT_SER_BAUDRATE__RD REG_RD_WO -#define R_ALT_SER_BAUDRATE__IRD REG_IRD_WO -#define R_ALT_SER_BAUDRATE__WR REG_WR_WO -#define R_ALT_SER_BAUDRATE__IWR REG_IWR_WO - -#define R_ALT_SER_BAUDRATE__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_ALT_SER_BAUDRATE__ser3_tr__ser3_tr__MASK 0x30000000U -#define R_ALT_SER_BAUDRATE__ser3_rec__ser3_rec__MASK 0x03000000U -#define R_ALT_SER_BAUDRATE__ser2_tr__ser2_tr__MASK 0x00300000U -#define R_ALT_SER_BAUDRATE__ser2_rec__ser2_rec__MASK 0x00030000U -#define R_ALT_SER_BAUDRATE__ser1_tr__ser1_tr__MASK 0x00003000U -#define R_ALT_SER_BAUDRATE__ser1_rec__ser1_rec__MASK 0x00000300U -#define R_ALT_SER_BAUDRATE__ser0_tr__ser0_tr__MASK 0x00000030U -#define R_ALT_SER_BAUDRATE__ser0_rec__ser0_rec__MASK 0x00000003U - -#define R_ALT_SER_BAUDRATE__ser3_tr__MAX 0x3 -#define R_ALT_SER_BAUDRATE__ser3_rec__MAX 0x3 -#define R_ALT_SER_BAUDRATE__ser2_tr__MAX 0x3 -#define R_ALT_SER_BAUDRATE__ser2_rec__MAX 0x3 -#define R_ALT_SER_BAUDRATE__ser1_tr__MAX 0x3 -#define R_ALT_SER_BAUDRATE__ser1_rec__MAX 0x3 -#define R_ALT_SER_BAUDRATE__ser0_tr__MAX 0x3 -#define R_ALT_SER_BAUDRATE__ser0_rec__MAX 0x3 - -#define R_ALT_SER_BAUDRATE__ser3_tr__MIN 0 -#define R_ALT_SER_BAUDRATE__ser3_rec__MIN 0 -#define R_ALT_SER_BAUDRATE__ser2_tr__MIN 0 -#define R_ALT_SER_BAUDRATE__ser2_rec__MIN 0 -#define R_ALT_SER_BAUDRATE__ser1_tr__MIN 0 -#define R_ALT_SER_BAUDRATE__ser1_rec__MIN 0 -#define R_ALT_SER_BAUDRATE__ser0_tr__MIN 0 -#define R_ALT_SER_BAUDRATE__ser0_rec__MIN 0 - -#define R_ALT_SER_BAUDRATE__ser3_tr__BITNR 28 -#define R_ALT_SER_BAUDRATE__ser3_rec__BITNR 24 -#define R_ALT_SER_BAUDRATE__ser2_tr__BITNR 20 -#define R_ALT_SER_BAUDRATE__ser2_rec__BITNR 16 -#define R_ALT_SER_BAUDRATE__ser1_tr__BITNR 12 -#define R_ALT_SER_BAUDRATE__ser1_rec__BITNR 8 -#define R_ALT_SER_BAUDRATE__ser0_tr__BITNR 4 -#define R_ALT_SER_BAUDRATE__ser0_rec__BITNR 0 - -#define R_ALT_SER_BAUDRATE__ser3_tr__ser3_tr__VAL REG_VAL_ENUM -#define R_ALT_SER_BAUDRATE__ser3_rec__ser3_rec__VAL REG_VAL_ENUM -#define R_ALT_SER_BAUDRATE__ser2_tr__ser2_tr__VAL REG_VAL_ENUM -#define R_ALT_SER_BAUDRATE__ser2_rec__ser2_rec__VAL REG_VAL_ENUM -#define R_ALT_SER_BAUDRATE__ser1_tr__ser1_tr__VAL REG_VAL_ENUM -#define R_ALT_SER_BAUDRATE__ser1_rec__ser1_rec__VAL REG_VAL_ENUM -#define R_ALT_SER_BAUDRATE__ser0_tr__ser0_tr__VAL REG_VAL_ENUM -#define R_ALT_SER_BAUDRATE__ser0_rec__ser0_rec__VAL REG_VAL_ENUM - -#define R_ALT_SER_BAUDRATE__ser3_tr__ser3_tr__extern 2 -#define R_ALT_SER_BAUDRATE__ser3_tr__ser3_tr__normal 0 -#define R_ALT_SER_BAUDRATE__ser3_tr__ser3_tr__prescale 1 -#define R_ALT_SER_BAUDRATE__ser3_tr__ser3_tr__timer 3 -#define R_ALT_SER_BAUDRATE__ser3_rec__ser3_rec__extern 2 -#define R_ALT_SER_BAUDRATE__ser3_rec__ser3_rec__normal 0 -#define R_ALT_SER_BAUDRATE__ser3_rec__ser3_rec__prescale 1 -#define R_ALT_SER_BAUDRATE__ser3_rec__ser3_rec__timer 3 -#define R_ALT_SER_BAUDRATE__ser2_tr__ser2_tr__extern 2 -#define R_ALT_SER_BAUDRATE__ser2_tr__ser2_tr__normal 0 -#define R_ALT_SER_BAUDRATE__ser2_tr__ser2_tr__prescale 1 -#define R_ALT_SER_BAUDRATE__ser2_tr__ser2_tr__timer 3 -#define R_ALT_SER_BAUDRATE__ser2_rec__ser2_rec__extern 2 -#define R_ALT_SER_BAUDRATE__ser2_rec__ser2_rec__normal 0 -#define R_ALT_SER_BAUDRATE__ser2_rec__ser2_rec__prescale 1 -#define R_ALT_SER_BAUDRATE__ser2_rec__ser2_rec__timer 3 -#define R_ALT_SER_BAUDRATE__ser1_tr__ser1_tr__extern 2 -#define R_ALT_SER_BAUDRATE__ser1_tr__ser1_tr__normal 0 -#define R_ALT_SER_BAUDRATE__ser1_tr__ser1_tr__prescale 1 -#define R_ALT_SER_BAUDRATE__ser1_tr__ser1_tr__timer 3 -#define R_ALT_SER_BAUDRATE__ser1_rec__ser1_rec__extern 2 -#define R_ALT_SER_BAUDRATE__ser1_rec__ser1_rec__normal 0 -#define R_ALT_SER_BAUDRATE__ser1_rec__ser1_rec__prescale 1 -#define R_ALT_SER_BAUDRATE__ser1_rec__ser1_rec__timer 3 -#define R_ALT_SER_BAUDRATE__ser0_tr__ser0_tr__extern 2 -#define R_ALT_SER_BAUDRATE__ser0_tr__ser0_tr__normal 0 -#define R_ALT_SER_BAUDRATE__ser0_tr__ser0_tr__prescale 1 -#define R_ALT_SER_BAUDRATE__ser0_tr__ser0_tr__timer 3 -#define R_ALT_SER_BAUDRATE__ser0_rec__ser0_rec__extern 2 -#define R_ALT_SER_BAUDRATE__ser0_rec__ser0_rec__normal 0 -#define R_ALT_SER_BAUDRATE__ser0_rec__ser0_rec__prescale 1 -#define R_ALT_SER_BAUDRATE__ser0_rec__ser0_rec__timer 3 - -#endif - -/* - * R_ATA_CONFIG - * - type: WO - * - addr: 0xb0000044 - * - group: ATA interface registers - */ - -#if USE_GROUP__ATA_interface_registers - -#define R_ATA_CONFIG__ADDR (REG_TYPECAST_UDWORD 0xb0000044) - -#ifndef REG_NO_SHADOW -#define R_ATA_CONFIG__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_ATA_CONFIG + 0)) -#define R_ATA_CONFIG__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_ATA_CONFIG + 0)) -#else /* REG_NO_SHADOW */ -#define R_ATA_CONFIG__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_ATA_CONFIG__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_ATA_CONFIG__STYPECAST REG_STYPECAST_UDWORD -#define R_ATA_CONFIG__SVAL REG_SVAL_SHADOW -#define R_ATA_CONFIG__SVAL_I REG_SVAL_I_SHADOW -#define R_ATA_CONFIG__TYPECAST REG_TYPECAST_UDWORD -#define R_ATA_CONFIG__TYPE (REG_UDWORD) -#define R_ATA_CONFIG__GET REG_GET_WO -#define R_ATA_CONFIG__IGET REG_IGET_WO -#define R_ATA_CONFIG__SET REG_SET_WO -#define R_ATA_CONFIG__ISET REG_ISET_WO -#define R_ATA_CONFIG__SET_VAL REG_SET_VAL_WO -#define R_ATA_CONFIG__EQL REG_EQL_WO -#define R_ATA_CONFIG__IEQL REG_IEQL_WO -#define R_ATA_CONFIG__RD REG_RD_WO -#define R_ATA_CONFIG__IRD REG_IRD_WO -#define R_ATA_CONFIG__WR REG_WR_WO -#define R_ATA_CONFIG__IWR REG_IWR_WO - -#define R_ATA_CONFIG__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_ATA_CONFIG__enable__enable__MASK 0x02000000U -#define R_ATA_CONFIG__dma_strobe__dma_strobe__MASK 0x01f00000U -#define R_ATA_CONFIG__dma_hold__dma_hold__MASK 0x000f8000U -#define R_ATA_CONFIG__pio_setup__pio_setup__MASK 0x00007c00U -#define R_ATA_CONFIG__pio_strobe__pio_strobe__MASK 0x000003e0U -#define R_ATA_CONFIG__pio_hold__pio_hold__MASK 0x0000001fU - -#define R_ATA_CONFIG__enable__MAX 0x1 -#define R_ATA_CONFIG__dma_strobe__MAX 31 -#define R_ATA_CONFIG__dma_hold__MAX 31 -#define R_ATA_CONFIG__pio_setup__MAX 31 -#define R_ATA_CONFIG__pio_strobe__MAX 31 -#define R_ATA_CONFIG__pio_hold__MAX 31 - -#define R_ATA_CONFIG__enable__MIN 0 -#define R_ATA_CONFIG__dma_strobe__MIN 0 -#define R_ATA_CONFIG__dma_hold__MIN 0 -#define R_ATA_CONFIG__pio_setup__MIN 0 -#define R_ATA_CONFIG__pio_strobe__MIN 0 -#define R_ATA_CONFIG__pio_hold__MIN 0 - -#define R_ATA_CONFIG__enable__BITNR 25 -#define R_ATA_CONFIG__dma_strobe__BITNR 20 -#define R_ATA_CONFIG__dma_hold__BITNR 15 -#define R_ATA_CONFIG__pio_setup__BITNR 10 -#define R_ATA_CONFIG__pio_strobe__BITNR 5 -#define R_ATA_CONFIG__pio_hold__BITNR 0 - -#define R_ATA_CONFIG__enable__enable__VAL REG_VAL_ENUM -#define R_ATA_CONFIG__dma_strobe__dma_strobe__VAL REG_VAL_VAL -#define R_ATA_CONFIG__dma_hold__dma_hold__VAL REG_VAL_VAL -#define R_ATA_CONFIG__pio_setup__pio_setup__VAL REG_VAL_VAL -#define R_ATA_CONFIG__pio_strobe__pio_strobe__VAL REG_VAL_VAL -#define R_ATA_CONFIG__pio_hold__pio_hold__VAL REG_VAL_VAL - -#define R_ATA_CONFIG__enable__enable__off 0 -#define R_ATA_CONFIG__enable__enable__on 1 - -#endif - -/* - * R_ATA_CTRL_DATA - * - type: WO - * - addr: 0xb0000040 - * - group: ATA interface registers - */ - -#if USE_GROUP__ATA_interface_registers - -#define R_ATA_CTRL_DATA__ADDR (REG_TYPECAST_UDWORD 0xb0000040) - -#ifndef REG_NO_SHADOW -#define R_ATA_CTRL_DATA__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_ATA_CTRL_DATA + 0)) -#define R_ATA_CTRL_DATA__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_ATA_CTRL_DATA + 0)) -#else /* REG_NO_SHADOW */ -#define R_ATA_CTRL_DATA__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_ATA_CTRL_DATA__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_ATA_CTRL_DATA__STYPECAST REG_STYPECAST_UDWORD -#define R_ATA_CTRL_DATA__SVAL REG_SVAL_SHADOW -#define R_ATA_CTRL_DATA__SVAL_I REG_SVAL_I_SHADOW -#define R_ATA_CTRL_DATA__TYPECAST REG_TYPECAST_UDWORD -#define R_ATA_CTRL_DATA__TYPE (REG_UDWORD) -#define R_ATA_CTRL_DATA__GET REG_GET_WO -#define R_ATA_CTRL_DATA__IGET REG_IGET_WO -#define R_ATA_CTRL_DATA__SET REG_SET_WO -#define R_ATA_CTRL_DATA__ISET REG_ISET_WO -#define R_ATA_CTRL_DATA__SET_VAL REG_SET_VAL_WO -#define R_ATA_CTRL_DATA__EQL REG_EQL_WO -#define R_ATA_CTRL_DATA__IEQL REG_IEQL_WO -#define R_ATA_CTRL_DATA__RD REG_RD_WO -#define R_ATA_CTRL_DATA__IRD REG_IRD_WO -#define R_ATA_CTRL_DATA__WR REG_WR_WO -#define R_ATA_CTRL_DATA__IWR REG_IWR_WO - -#define R_ATA_CTRL_DATA__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_ATA_CTRL_DATA__sel__sel__MASK 0xc0000000U -#define R_ATA_CTRL_DATA__cs1__cs1__MASK 0x20000000U -#define R_ATA_CTRL_DATA__cs0__cs0__MASK 0x10000000U -#define R_ATA_CTRL_DATA__addr__addr__MASK 0x0e000000U -#define R_ATA_CTRL_DATA__rw__rw__MASK 0x01000000U -#define R_ATA_CTRL_DATA__src_dst__src_dst__MASK 0x00800000U -#define R_ATA_CTRL_DATA__handsh__handsh__MASK 0x00400000U -#define R_ATA_CTRL_DATA__multi__multi__MASK 0x00200000U -#define R_ATA_CTRL_DATA__dma_size__dma_size__MASK 0x00100000U -#define R_ATA_CTRL_DATA__data__data__MASK 0x0000ffffU - -#define R_ATA_CTRL_DATA__sel__MAX 3 -#define R_ATA_CTRL_DATA__cs1__MAX 0x1 -#define R_ATA_CTRL_DATA__cs0__MAX 0x1 -#define R_ATA_CTRL_DATA__addr__MAX 7 -#define R_ATA_CTRL_DATA__rw__MAX 0x1 -#define R_ATA_CTRL_DATA__src_dst__MAX 0x1 -#define R_ATA_CTRL_DATA__handsh__MAX 0x1 -#define R_ATA_CTRL_DATA__multi__MAX 0x1 -#define R_ATA_CTRL_DATA__dma_size__MAX 0x1 -#define R_ATA_CTRL_DATA__data__MAX 0xffff - -#define R_ATA_CTRL_DATA__sel__MIN 0 -#define R_ATA_CTRL_DATA__cs1__MIN 0 -#define R_ATA_CTRL_DATA__cs0__MIN 0 -#define R_ATA_CTRL_DATA__addr__MIN 0 -#define R_ATA_CTRL_DATA__rw__MIN 0 -#define R_ATA_CTRL_DATA__src_dst__MIN 0 -#define R_ATA_CTRL_DATA__handsh__MIN 0 -#define R_ATA_CTRL_DATA__multi__MIN 0 -#define R_ATA_CTRL_DATA__dma_size__MIN 0 -#define R_ATA_CTRL_DATA__data__MIN 0 - -#define R_ATA_CTRL_DATA__sel__BITNR 30 -#define R_ATA_CTRL_DATA__cs1__BITNR 29 -#define R_ATA_CTRL_DATA__cs0__BITNR 28 -#define R_ATA_CTRL_DATA__addr__BITNR 25 -#define R_ATA_CTRL_DATA__rw__BITNR 24 -#define R_ATA_CTRL_DATA__src_dst__BITNR 23 -#define R_ATA_CTRL_DATA__handsh__BITNR 22 -#define R_ATA_CTRL_DATA__multi__BITNR 21 -#define R_ATA_CTRL_DATA__dma_size__BITNR 20 -#define R_ATA_CTRL_DATA__data__BITNR 0 - -#define R_ATA_CTRL_DATA__sel__sel__VAL REG_VAL_VAL -#define R_ATA_CTRL_DATA__cs1__cs1__VAL REG_VAL_ENUM -#define R_ATA_CTRL_DATA__cs0__cs0__VAL REG_VAL_ENUM -#define R_ATA_CTRL_DATA__addr__addr__VAL REG_VAL_VAL -#define R_ATA_CTRL_DATA__rw__rw__VAL REG_VAL_ENUM -#define R_ATA_CTRL_DATA__src_dst__src_dst__VAL REG_VAL_ENUM -#define R_ATA_CTRL_DATA__handsh__handsh__VAL REG_VAL_ENUM -#define R_ATA_CTRL_DATA__multi__multi__VAL REG_VAL_ENUM -#define R_ATA_CTRL_DATA__dma_size__dma_size__VAL REG_VAL_ENUM -#define R_ATA_CTRL_DATA__data__data__VAL REG_VAL_VAL - -#define R_ATA_CTRL_DATA__cs1__cs1__active 1 -#define R_ATA_CTRL_DATA__cs1__cs1__inactive 0 -#define R_ATA_CTRL_DATA__cs0__cs0__active 1 -#define R_ATA_CTRL_DATA__cs0__cs0__inactive 0 -#define R_ATA_CTRL_DATA__rw__rw__read 1 -#define R_ATA_CTRL_DATA__rw__rw__write 0 -#define R_ATA_CTRL_DATA__src_dst__src_dst__dma 1 -#define R_ATA_CTRL_DATA__src_dst__src_dst__register 0 -#define R_ATA_CTRL_DATA__handsh__handsh__dma 1 -#define R_ATA_CTRL_DATA__handsh__handsh__pio 0 -#define R_ATA_CTRL_DATA__multi__multi__off 0 -#define R_ATA_CTRL_DATA__multi__multi__on 1 -#define R_ATA_CTRL_DATA__dma_size__dma_size__byte 1 -#define R_ATA_CTRL_DATA__dma_size__dma_size__word 0 - -#endif - -/* - * R_ATA_STATUS_DATA - * - type: RO - * - addr: 0xb0000040 - * - group: ATA interface registers - */ - -#if USE_GROUP__ATA_interface_registers - -#define R_ATA_STATUS_DATA__ADDR (REG_TYPECAST_UDWORD 0xb0000040) -#define R_ATA_STATUS_DATA__SVAL REG_SVAL_SHADOW -#define R_ATA_STATUS_DATA__SVAL_I REG_SVAL_I_SHADOW -#define R_ATA_STATUS_DATA__TYPECAST REG_TYPECAST_UDWORD -#define R_ATA_STATUS_DATA__TYPE (REG_UDWORD) -#define R_ATA_STATUS_DATA__GET REG_GET_RO -#define R_ATA_STATUS_DATA__IGET REG_IGET_RO -#define R_ATA_STATUS_DATA__SET REG_SET_RO -#define R_ATA_STATUS_DATA__ISET REG_ISET_RO -#define R_ATA_STATUS_DATA__SET_VAL REG_SET_VAL_RO -#define R_ATA_STATUS_DATA__EQL REG_EQL_RO -#define R_ATA_STATUS_DATA__IEQL REG_IEQL_RO -#define R_ATA_STATUS_DATA__RD REG_RD_RO -#define R_ATA_STATUS_DATA__IRD REG_IRD_RO -#define R_ATA_STATUS_DATA__WR REG_WR_RO -#define R_ATA_STATUS_DATA__IWR REG_IWR_RO - -#define R_ATA_STATUS_DATA__READ(addr) \ - (*(addr)) - -#define R_ATA_STATUS_DATA__busy__busy__MASK 0x00040000U -#define R_ATA_STATUS_DATA__tr_rdy__tr_rdy__MASK 0x00020000U -#define R_ATA_STATUS_DATA__dav__dav__MASK 0x00010000U -#define R_ATA_STATUS_DATA__data__data__MASK 0x0000ffffU - -#define R_ATA_STATUS_DATA__busy__MAX 0x1 -#define R_ATA_STATUS_DATA__tr_rdy__MAX 0x1 -#define R_ATA_STATUS_DATA__dav__MAX 0x1 -#define R_ATA_STATUS_DATA__data__MAX 0xffff - -#define R_ATA_STATUS_DATA__busy__MIN 0 -#define R_ATA_STATUS_DATA__tr_rdy__MIN 0 -#define R_ATA_STATUS_DATA__dav__MIN 0 -#define R_ATA_STATUS_DATA__data__MIN 0 - -#define R_ATA_STATUS_DATA__busy__BITNR 18 -#define R_ATA_STATUS_DATA__tr_rdy__BITNR 17 -#define R_ATA_STATUS_DATA__dav__BITNR 16 -#define R_ATA_STATUS_DATA__data__BITNR 0 - -#define R_ATA_STATUS_DATA__busy__busy__VAL REG_VAL_ENUM -#define R_ATA_STATUS_DATA__tr_rdy__tr_rdy__VAL REG_VAL_ENUM -#define R_ATA_STATUS_DATA__dav__dav__VAL REG_VAL_ENUM -#define R_ATA_STATUS_DATA__data__data__VAL REG_VAL_VAL - -#define R_ATA_STATUS_DATA__busy__busy__no 0 -#define R_ATA_STATUS_DATA__busy__busy__yes 1 -#define R_ATA_STATUS_DATA__tr_rdy__tr_rdy__busy 0 -#define R_ATA_STATUS_DATA__tr_rdy__tr_rdy__ready 1 -#define R_ATA_STATUS_DATA__dav__dav__data 1 -#define R_ATA_STATUS_DATA__dav__dav__nodata 0 - -#endif - -/* - * R_ATA_TRANSFER_CNT - * - type: RW - * - addr: 0xb0000048 - * - group: ATA interface registers - */ - -#if USE_GROUP__ATA_interface_registers - -#define R_ATA_TRANSFER_CNT__ADDR (REG_TYPECAST_UDWORD 0xb0000048) -#define R_ATA_TRANSFER_CNT__SVAL REG_SVAL_SHADOW -#define R_ATA_TRANSFER_CNT__SVAL_I REG_SVAL_I_SHADOW -#define R_ATA_TRANSFER_CNT__TYPECAST REG_TYPECAST_UDWORD -#define R_ATA_TRANSFER_CNT__TYPE (REG_UDWORD) -#define R_ATA_TRANSFER_CNT__GET REG_GET_RW -#define R_ATA_TRANSFER_CNT__IGET REG_IGET_RW -#define R_ATA_TRANSFER_CNT__SET REG_SET_RW -#define R_ATA_TRANSFER_CNT__ISET REG_ISET_RW -#define R_ATA_TRANSFER_CNT__SET_VAL REG_SET_VAL_RW -#define R_ATA_TRANSFER_CNT__EQL REG_EQL_RW -#define R_ATA_TRANSFER_CNT__IEQL REG_IEQL_RW -#define R_ATA_TRANSFER_CNT__RD REG_RD_RW -#define R_ATA_TRANSFER_CNT__IRD REG_IRD_RW -#define R_ATA_TRANSFER_CNT__WR REG_WR_RW -#define R_ATA_TRANSFER_CNT__IWR REG_IWR_RW - -#define R_ATA_TRANSFER_CNT__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_ATA_TRANSFER_CNT__READ(addr) \ - (*(addr)) - -#define R_ATA_TRANSFER_CNT__count__count__MASK 0x0001ffffU - -#define R_ATA_TRANSFER_CNT__count__MAX 0x1ffff - -#define R_ATA_TRANSFER_CNT__count__MIN 0 - -#define R_ATA_TRANSFER_CNT__count__BITNR 0 - -#define R_ATA_TRANSFER_CNT__count__count__VAL REG_VAL_VAL - - -#endif - -/* - * R_BUS_CONFIG - * - type: WO - * - addr: 0xb0000004 - * - group: Bus interface configuration registers - */ - -#if USE_GROUP__Bus_interface_configuration_registers - -#define R_BUS_CONFIG__ADDR (REG_TYPECAST_UDWORD 0xb0000004) - -#ifndef REG_NO_SHADOW -#define R_BUS_CONFIG__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_BUS_CONFIG + 0)) -#define R_BUS_CONFIG__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_BUS_CONFIG + 0)) -#else /* REG_NO_SHADOW */ -#define R_BUS_CONFIG__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_BUS_CONFIG__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_BUS_CONFIG__STYPECAST REG_STYPECAST_UDWORD -#define R_BUS_CONFIG__SVAL REG_SVAL_SHADOW -#define R_BUS_CONFIG__SVAL_I REG_SVAL_I_SHADOW -#define R_BUS_CONFIG__TYPECAST REG_TYPECAST_UDWORD -#define R_BUS_CONFIG__TYPE (REG_UDWORD) -#define R_BUS_CONFIG__GET REG_GET_WO -#define R_BUS_CONFIG__IGET REG_IGET_WO -#define R_BUS_CONFIG__SET REG_SET_WO -#define R_BUS_CONFIG__ISET REG_ISET_WO -#define R_BUS_CONFIG__SET_VAL REG_SET_VAL_WO -#define R_BUS_CONFIG__EQL REG_EQL_WO -#define R_BUS_CONFIG__IEQL REG_IEQL_WO -#define R_BUS_CONFIG__RD REG_RD_WO -#define R_BUS_CONFIG__IRD REG_IRD_WO -#define R_BUS_CONFIG__WR REG_WR_WO -#define R_BUS_CONFIG__IWR REG_IWR_WO - -#define R_BUS_CONFIG__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_BUS_CONFIG__sram_type__sram_type__MASK 0x00000200U -#define R_BUS_CONFIG__dma_burst__dma_burst__MASK 0x00000100U -#define R_BUS_CONFIG__pcs4_7_wr__pcs4_7_wr__MASK 0x00000080U -#define R_BUS_CONFIG__pcs0_3_wr__pcs0_3_wr__MASK 0x00000040U -#define R_BUS_CONFIG__sram_wr__sram_wr__MASK 0x00000020U -#define R_BUS_CONFIG__flash_wr__flash_wr__MASK 0x00000010U -#define R_BUS_CONFIG__pcs4_7_bw__pcs4_7_bw__MASK 0x00000008U -#define R_BUS_CONFIG__pcs0_3_bw__pcs0_3_bw__MASK 0x00000004U -#define R_BUS_CONFIG__sram_bw__sram_bw__MASK 0x00000002U -#define R_BUS_CONFIG__flash_bw__flash_bw__MASK 0x00000001U - -#define R_BUS_CONFIG__sram_type__MAX 0x1 -#define R_BUS_CONFIG__dma_burst__MAX 0x1 -#define R_BUS_CONFIG__pcs4_7_wr__MAX 0x1 -#define R_BUS_CONFIG__pcs0_3_wr__MAX 0x1 -#define R_BUS_CONFIG__sram_wr__MAX 0x1 -#define R_BUS_CONFIG__flash_wr__MAX 0x1 -#define R_BUS_CONFIG__pcs4_7_bw__MAX 0x1 -#define R_BUS_CONFIG__pcs0_3_bw__MAX 0x1 -#define R_BUS_CONFIG__sram_bw__MAX 0x1 -#define R_BUS_CONFIG__flash_bw__MAX 0x1 - -#define R_BUS_CONFIG__sram_type__MIN 0 -#define R_BUS_CONFIG__dma_burst__MIN 0 -#define R_BUS_CONFIG__pcs4_7_wr__MIN 0 -#define R_BUS_CONFIG__pcs0_3_wr__MIN 0 -#define R_BUS_CONFIG__sram_wr__MIN 0 -#define R_BUS_CONFIG__flash_wr__MIN 0 -#define R_BUS_CONFIG__pcs4_7_bw__MIN 0 -#define R_BUS_CONFIG__pcs0_3_bw__MIN 0 -#define R_BUS_CONFIG__sram_bw__MIN 0 -#define R_BUS_CONFIG__flash_bw__MIN 0 - -#define R_BUS_CONFIG__sram_type__BITNR 9 -#define R_BUS_CONFIG__dma_burst__BITNR 8 -#define R_BUS_CONFIG__pcs4_7_wr__BITNR 7 -#define R_BUS_CONFIG__pcs0_3_wr__BITNR 6 -#define R_BUS_CONFIG__sram_wr__BITNR 5 -#define R_BUS_CONFIG__flash_wr__BITNR 4 -#define R_BUS_CONFIG__pcs4_7_bw__BITNR 3 -#define R_BUS_CONFIG__pcs0_3_bw__BITNR 2 -#define R_BUS_CONFIG__sram_bw__BITNR 1 -#define R_BUS_CONFIG__flash_bw__BITNR 0 - -#define R_BUS_CONFIG__sram_type__sram_type__VAL REG_VAL_ENUM -#define R_BUS_CONFIG__dma_burst__dma_burst__VAL REG_VAL_ENUM -#define R_BUS_CONFIG__pcs4_7_wr__pcs4_7_wr__VAL REG_VAL_ENUM -#define R_BUS_CONFIG__pcs0_3_wr__pcs0_3_wr__VAL REG_VAL_ENUM -#define R_BUS_CONFIG__sram_wr__sram_wr__VAL REG_VAL_ENUM -#define R_BUS_CONFIG__flash_wr__flash_wr__VAL REG_VAL_ENUM -#define R_BUS_CONFIG__pcs4_7_bw__pcs4_7_bw__VAL REG_VAL_ENUM -#define R_BUS_CONFIG__pcs0_3_bw__pcs0_3_bw__VAL REG_VAL_ENUM -#define R_BUS_CONFIG__sram_bw__sram_bw__VAL REG_VAL_ENUM -#define R_BUS_CONFIG__flash_bw__flash_bw__VAL REG_VAL_ENUM - -#define R_BUS_CONFIG__sram_type__sram_type__bwe 0 -#define R_BUS_CONFIG__sram_type__sram_type__cwe 1 -#define R_BUS_CONFIG__dma_burst__dma_burst__burst16 1 -#define R_BUS_CONFIG__dma_burst__dma_burst__burst32 0 -#define R_BUS_CONFIG__pcs4_7_wr__pcs4_7_wr__ext 1 -#define R_BUS_CONFIG__pcs4_7_wr__pcs4_7_wr__norm 0 -#define R_BUS_CONFIG__pcs0_3_wr__pcs0_3_wr__ext 1 -#define R_BUS_CONFIG__pcs0_3_wr__pcs0_3_wr__norm 0 -#define R_BUS_CONFIG__sram_wr__sram_wr__ext 1 -#define R_BUS_CONFIG__sram_wr__sram_wr__norm 0 -#define R_BUS_CONFIG__flash_wr__flash_wr__ext 1 -#define R_BUS_CONFIG__flash_wr__flash_wr__norm 0 -#define R_BUS_CONFIG__pcs4_7_bw__pcs4_7_bw__bw16 0 -#define R_BUS_CONFIG__pcs4_7_bw__pcs4_7_bw__bw32 1 -#define R_BUS_CONFIG__pcs0_3_bw__pcs0_3_bw__bw16 0 -#define R_BUS_CONFIG__pcs0_3_bw__pcs0_3_bw__bw32 1 -#define R_BUS_CONFIG__sram_bw__sram_bw__bw16 0 -#define R_BUS_CONFIG__sram_bw__sram_bw__bw32 1 -#define R_BUS_CONFIG__flash_bw__flash_bw__bw16 0 -#define R_BUS_CONFIG__flash_bw__flash_bw__bw32 1 - -#endif - -/* - * R_BUS_STATUS - * - type: RO - * - addr: 0xb0000004 - * - group: Bus interface configuration registers - */ - -#if USE_GROUP__Bus_interface_configuration_registers - -#define R_BUS_STATUS__ADDR (REG_TYPECAST_UDWORD 0xb0000004) -#define R_BUS_STATUS__SVAL REG_SVAL_SHADOW -#define R_BUS_STATUS__SVAL_I REG_SVAL_I_SHADOW -#define R_BUS_STATUS__TYPECAST REG_TYPECAST_UDWORD -#define R_BUS_STATUS__TYPE (REG_UDWORD) -#define R_BUS_STATUS__GET REG_GET_RO -#define R_BUS_STATUS__IGET REG_IGET_RO -#define R_BUS_STATUS__SET REG_SET_RO -#define R_BUS_STATUS__ISET REG_ISET_RO -#define R_BUS_STATUS__SET_VAL REG_SET_VAL_RO -#define R_BUS_STATUS__EQL REG_EQL_RO -#define R_BUS_STATUS__IEQL REG_IEQL_RO -#define R_BUS_STATUS__RD REG_RD_RO -#define R_BUS_STATUS__IRD REG_IRD_RO -#define R_BUS_STATUS__WR REG_WR_RO -#define R_BUS_STATUS__IWR REG_IWR_RO - -#define R_BUS_STATUS__READ(addr) \ - (*(addr)) - -#define R_BUS_STATUS__pll_lock_tm__pll_lock_tm__MASK 0x00000020U -#define R_BUS_STATUS__both_faults__both_faults__MASK 0x00000010U -#define R_BUS_STATUS__bsen___bsen___MASK 0x00000008U -#define R_BUS_STATUS__boot__boot__MASK 0x00000006U -#define R_BUS_STATUS__flashw__flashw__MASK 0x00000001U - -#define R_BUS_STATUS__pll_lock_tm__MAX 0x1 -#define R_BUS_STATUS__both_faults__MAX 0x1 -#define R_BUS_STATUS__bsen___MAX 0x1 -#define R_BUS_STATUS__boot__MAX 0x3 -#define R_BUS_STATUS__flashw__MAX 0x1 - -#define R_BUS_STATUS__pll_lock_tm__MIN 0 -#define R_BUS_STATUS__both_faults__MIN 0 -#define R_BUS_STATUS__bsen___MIN 0 -#define R_BUS_STATUS__boot__MIN 0 -#define R_BUS_STATUS__flashw__MIN 0 - -#define R_BUS_STATUS__pll_lock_tm__BITNR 5 -#define R_BUS_STATUS__both_faults__BITNR 4 -#define R_BUS_STATUS__bsen___BITNR 3 -#define R_BUS_STATUS__boot__BITNR 1 -#define R_BUS_STATUS__flashw__BITNR 0 - -#define R_BUS_STATUS__pll_lock_tm__pll_lock_tm__VAL REG_VAL_ENUM -#define R_BUS_STATUS__both_faults__both_faults__VAL REG_VAL_ENUM -#define R_BUS_STATUS__bsen___bsen___VAL REG_VAL_ENUM -#define R_BUS_STATUS__boot__boot__VAL REG_VAL_ENUM -#define R_BUS_STATUS__flashw__flashw__VAL REG_VAL_ENUM - -#define R_BUS_STATUS__pll_lock_tm__pll_lock_tm__counting 1 -#define R_BUS_STATUS__pll_lock_tm__pll_lock_tm__expired 0 -#define R_BUS_STATUS__both_faults__both_faults__no 0 -#define R_BUS_STATUS__both_faults__both_faults__yes 1 -#define R_BUS_STATUS__bsen___bsen___disable 1 -#define R_BUS_STATUS__bsen___bsen___enable 0 -#define R_BUS_STATUS__boot__boot__network 2 -#define R_BUS_STATUS__boot__boot__parallel 3 -#define R_BUS_STATUS__boot__boot__serial 1 -#define R_BUS_STATUS__boot__boot__uncached 0 -#define R_BUS_STATUS__flashw__flashw__bw16 0 -#define R_BUS_STATUS__flashw__flashw__bw32 1 - -#endif - -/* - * R_CLOCK_PRESCALE - * - type: WO - * - addr: 0xb00000f0 - * - group: Timer registers - */ - -#if USE_GROUP__Timer_registers - -#define R_CLOCK_PRESCALE__ADDR (REG_TYPECAST_UDWORD 0xb00000f0) - -#ifndef REG_NO_SHADOW -#define R_CLOCK_PRESCALE__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_CLOCK_PRESCALE + 0)) -#define R_CLOCK_PRESCALE__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_CLOCK_PRESCALE + 0)) -#else /* REG_NO_SHADOW */ -#define R_CLOCK_PRESCALE__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_CLOCK_PRESCALE__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_CLOCK_PRESCALE__STYPECAST REG_STYPECAST_UDWORD -#define R_CLOCK_PRESCALE__SVAL REG_SVAL_SHADOW -#define R_CLOCK_PRESCALE__SVAL_I REG_SVAL_I_SHADOW -#define R_CLOCK_PRESCALE__TYPECAST REG_TYPECAST_UDWORD -#define R_CLOCK_PRESCALE__TYPE (REG_UDWORD) -#define R_CLOCK_PRESCALE__GET REG_GET_WO -#define R_CLOCK_PRESCALE__IGET REG_IGET_WO -#define R_CLOCK_PRESCALE__SET REG_SET_WO -#define R_CLOCK_PRESCALE__ISET REG_ISET_WO -#define R_CLOCK_PRESCALE__SET_VAL REG_SET_VAL_WO -#define R_CLOCK_PRESCALE__EQL REG_EQL_WO -#define R_CLOCK_PRESCALE__IEQL REG_IEQL_WO -#define R_CLOCK_PRESCALE__RD REG_RD_WO -#define R_CLOCK_PRESCALE__IRD REG_IRD_WO -#define R_CLOCK_PRESCALE__WR REG_WR_WO -#define R_CLOCK_PRESCALE__IWR REG_IWR_WO - -#define R_CLOCK_PRESCALE__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_CLOCK_PRESCALE__ser_presc__ser_presc__MASK 0xffff0000U -#define R_CLOCK_PRESCALE__tim_presc__tim_presc__MASK 0x0000ffffU - -#define R_CLOCK_PRESCALE__ser_presc__MAX 0xffff -#define R_CLOCK_PRESCALE__tim_presc__MAX 0xffff - -#define R_CLOCK_PRESCALE__ser_presc__MIN 0 -#define R_CLOCK_PRESCALE__tim_presc__MIN 0 - -#define R_CLOCK_PRESCALE__ser_presc__BITNR 16 -#define R_CLOCK_PRESCALE__tim_presc__BITNR 0 - -#define R_CLOCK_PRESCALE__ser_presc__ser_presc__VAL REG_VAL_VAL -#define R_CLOCK_PRESCALE__tim_presc__tim_presc__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH0_BUF - * - type: RW - * - addr: 0xb0000108 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH0_BUF__ADDR (REG_TYPECAST_UDWORD 0xb0000108) -#define R_DMA_CH0_BUF__SVAL REG_SVAL_SHADOW -#define R_DMA_CH0_BUF__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH0_BUF__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH0_BUF__TYPE (REG_UDWORD) -#define R_DMA_CH0_BUF__GET REG_GET_RW -#define R_DMA_CH0_BUF__IGET REG_IGET_RW -#define R_DMA_CH0_BUF__SET REG_SET_RW -#define R_DMA_CH0_BUF__ISET REG_ISET_RW -#define R_DMA_CH0_BUF__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH0_BUF__EQL REG_EQL_RW -#define R_DMA_CH0_BUF__IEQL REG_IEQL_RW -#define R_DMA_CH0_BUF__RD REG_RD_RW -#define R_DMA_CH0_BUF__IRD REG_IRD_RW -#define R_DMA_CH0_BUF__WR REG_WR_RW -#define R_DMA_CH0_BUF__IWR REG_IWR_RW - -#define R_DMA_CH0_BUF__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH0_BUF__READ(addr) \ - (*(addr)) - -/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */ -#define R_DMA_CH0_BUF__FIRST 0 -#define R_DMA_CH0_BUF__LAST 9 -#define R_DMA_CH0_BUF__OFFSET 16 -/* end */ - -#define R_DMA_CH0_BUF__buf__buf__MASK 0xffffffffU - -#define R_DMA_CH0_BUF__buf__MAX 0xffffffff - -#define R_DMA_CH0_BUF__buf__MIN 0 - -#define R_DMA_CH0_BUF__buf__BITNR 0 - -#define R_DMA_CH0_BUF__buf__buf__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH0_CLR_INTR - * - type: WO - * - addr: 0xb00001d1 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH0_CLR_INTR__ADDR (REG_TYPECAST_BYTE 0xb00001d1) - -#ifndef REG_NO_SHADOW -#define R_DMA_CH0_CLR_INTR__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_DMA_CH0_CLR_INTR + 0)) -#define R_DMA_CH0_CLR_INTR__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_DMA_CH0_CLR_INTR + 0)) -#else /* REG_NO_SHADOW */ -#define R_DMA_CH0_CLR_INTR__SADDR (REG_STYPECAST_BYTE (®_shadow__hwregs)) -#define R_DMA_CH0_CLR_INTR__IADDR (REG_STYPECAST_BYTE (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_DMA_CH0_CLR_INTR__STYPECAST REG_STYPECAST_BYTE -#define R_DMA_CH0_CLR_INTR__SVAL REG_SVAL_ZERO -#define R_DMA_CH0_CLR_INTR__SVAL_I REG_SVAL_I_ZERO -#define R_DMA_CH0_CLR_INTR__TYPECAST REG_TYPECAST_BYTE -#define R_DMA_CH0_CLR_INTR__TYPE (REG_BYTE) -#define R_DMA_CH0_CLR_INTR__GET REG_GET_WO -#define R_DMA_CH0_CLR_INTR__IGET REG_IGET_WO -#define R_DMA_CH0_CLR_INTR__SET REG_SET_WO -#define R_DMA_CH0_CLR_INTR__ISET REG_ISET_WO -#define R_DMA_CH0_CLR_INTR__SET_VAL REG_SET_VAL_WO -#define R_DMA_CH0_CLR_INTR__EQL REG_EQL_WO -#define R_DMA_CH0_CLR_INTR__IEQL REG_IEQL_WO -#define R_DMA_CH0_CLR_INTR__RD REG_RD_WO -#define R_DMA_CH0_CLR_INTR__IRD REG_IRD_WO -#define R_DMA_CH0_CLR_INTR__WR REG_WR_WO -#define R_DMA_CH0_CLR_INTR__IWR REG_IWR_WO - -#define R_DMA_CH0_CLR_INTR__WRITE(addr,value) \ - (*(addr) = (value)) - -/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */ -#define R_DMA_CH0_CLR_INTR__FIRST 0 -#define R_DMA_CH0_CLR_INTR__IOFFSET 0 -#define R_DMA_CH0_CLR_INTR__LAST 9 -#define R_DMA_CH0_CLR_INTR__OFFSET 4 -#define R_DMA_CH0_CLR_INTR__SOFFSET 0 -/* end */ - -#define R_DMA_CH0_CLR_INTR__clr_eop__clr_eop__MASK 0x00000002U -#define R_DMA_CH0_CLR_INTR__clr_descr__clr_descr__MASK 0x00000001U - -#define R_DMA_CH0_CLR_INTR__clr_eop__MAX 0x1 -#define R_DMA_CH0_CLR_INTR__clr_descr__MAX 0x1 - -#define R_DMA_CH0_CLR_INTR__clr_eop__MIN 0 -#define R_DMA_CH0_CLR_INTR__clr_descr__MIN 0 - -#define R_DMA_CH0_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH0_CLR_INTR__clr_descr__BITNR 0 - -#define R_DMA_CH0_CLR_INTR__clr_eop__clr_eop__VAL REG_VAL_ENUM -#define R_DMA_CH0_CLR_INTR__clr_descr__clr_descr__VAL REG_VAL_ENUM - -#define R_DMA_CH0_CLR_INTR__clr_eop__clr_eop__do 1 -#define R_DMA_CH0_CLR_INTR__clr_eop__clr_eop__dont 0 -#define R_DMA_CH0_CLR_INTR__clr_descr__clr_descr__do 1 -#define R_DMA_CH0_CLR_INTR__clr_descr__clr_descr__dont 0 - -#endif - -/* - * R_DMA_CH0_CMD - * - type: RW - * - addr: 0xb00001d0 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH0_CMD__ADDR (REG_TYPECAST_BYTE 0xb00001d0) -#define R_DMA_CH0_CMD__SVAL REG_SVAL_SHADOW -#define R_DMA_CH0_CMD__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH0_CMD__TYPECAST REG_TYPECAST_BYTE -#define R_DMA_CH0_CMD__TYPE (REG_BYTE) -#define R_DMA_CH0_CMD__GET REG_GET_RW -#define R_DMA_CH0_CMD__IGET REG_IGET_RW -#define R_DMA_CH0_CMD__SET REG_SET_RW -#define R_DMA_CH0_CMD__ISET REG_ISET_RW -#define R_DMA_CH0_CMD__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH0_CMD__EQL REG_EQL_RW -#define R_DMA_CH0_CMD__IEQL REG_IEQL_RW -#define R_DMA_CH0_CMD__RD REG_RD_RW -#define R_DMA_CH0_CMD__IRD REG_IRD_RW -#define R_DMA_CH0_CMD__WR REG_WR_RW -#define R_DMA_CH0_CMD__IWR REG_IWR_RW - -#define R_DMA_CH0_CMD__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH0_CMD__READ(addr) \ - (*(addr)) - -/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */ -#define R_DMA_CH0_CMD__FIRST 0 -#define R_DMA_CH0_CMD__LAST 9 -#define R_DMA_CH0_CMD__OFFSET 4 -/* end */ - -#define R_DMA_CH0_CMD__cmd__cmd__MASK 0x00000007U - -#define R_DMA_CH0_CMD__cmd__MAX 0x7 - -#define R_DMA_CH0_CMD__cmd__MIN 0 - -#define R_DMA_CH0_CMD__cmd__BITNR 0 - -#define R_DMA_CH0_CMD__cmd__cmd__VAL REG_VAL_ENUM - -#define R_DMA_CH0_CMD__cmd__cmd__continue 3 -#define R_DMA_CH0_CMD__cmd__cmd__hold 0 -#define R_DMA_CH0_CMD__cmd__cmd__reset 4 -#define R_DMA_CH0_CMD__cmd__cmd__restart 3 -#define R_DMA_CH0_CMD__cmd__cmd__start 1 - -#endif - -/* - * R_DMA_CH0_DESCR - * - type: RW - * - addr: 0xb000010c - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH0_DESCR__ADDR (REG_TYPECAST_UDWORD 0xb000010c) -#define R_DMA_CH0_DESCR__SVAL REG_SVAL_SHADOW -#define R_DMA_CH0_DESCR__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH0_DESCR__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH0_DESCR__TYPE (REG_UDWORD) -#define R_DMA_CH0_DESCR__GET REG_GET_RW -#define R_DMA_CH0_DESCR__IGET REG_IGET_RW -#define R_DMA_CH0_DESCR__SET REG_SET_RW -#define R_DMA_CH0_DESCR__ISET REG_ISET_RW -#define R_DMA_CH0_DESCR__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH0_DESCR__EQL REG_EQL_RW -#define R_DMA_CH0_DESCR__IEQL REG_IEQL_RW -#define R_DMA_CH0_DESCR__RD REG_RD_RW -#define R_DMA_CH0_DESCR__IRD REG_IRD_RW -#define R_DMA_CH0_DESCR__WR REG_WR_RW -#define R_DMA_CH0_DESCR__IWR REG_IWR_RW - -#define R_DMA_CH0_DESCR__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH0_DESCR__READ(addr) \ - (*(addr)) - -/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */ -#define R_DMA_CH0_DESCR__FIRST 0 -#define R_DMA_CH0_DESCR__LAST 9 -#define R_DMA_CH0_DESCR__OFFSET 16 -/* end */ - -#define R_DMA_CH0_DESCR__descr__descr__MASK 0xffffffffU - -#define R_DMA_CH0_DESCR__descr__MAX 0xffffffff - -#define R_DMA_CH0_DESCR__descr__MIN 0 - -#define R_DMA_CH0_DESCR__descr__BITNR 0 - -#define R_DMA_CH0_DESCR__descr__descr__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH0_FIRST - * - type: RW - * - addr: 0xb00001a0 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH0_FIRST__ADDR (REG_TYPECAST_UDWORD 0xb00001a0) -#define R_DMA_CH0_FIRST__SVAL REG_SVAL_SHADOW -#define R_DMA_CH0_FIRST__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH0_FIRST__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH0_FIRST__TYPE (REG_UDWORD) -#define R_DMA_CH0_FIRST__GET REG_GET_RW -#define R_DMA_CH0_FIRST__IGET REG_IGET_RW -#define R_DMA_CH0_FIRST__SET REG_SET_RW -#define R_DMA_CH0_FIRST__ISET REG_ISET_RW -#define R_DMA_CH0_FIRST__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH0_FIRST__EQL REG_EQL_RW -#define R_DMA_CH0_FIRST__IEQL REG_IEQL_RW -#define R_DMA_CH0_FIRST__RD REG_RD_RW -#define R_DMA_CH0_FIRST__IRD REG_IRD_RW -#define R_DMA_CH0_FIRST__WR REG_WR_RW -#define R_DMA_CH0_FIRST__IWR REG_IWR_RW - -#define R_DMA_CH0_FIRST__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH0_FIRST__READ(addr) \ - (*(addr)) - -/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */ -#define R_DMA_CH0_FIRST__FIRST 0 -#define R_DMA_CH0_FIRST__LAST 9 -#define R_DMA_CH0_FIRST__OFFSET 4 -/* end */ - -#define R_DMA_CH0_FIRST__first__first__MASK 0xffffffffU - -#define R_DMA_CH0_FIRST__first__MAX 0xffffffff - -#define R_DMA_CH0_FIRST__first__MIN 0 - -#define R_DMA_CH0_FIRST__first__BITNR 0 - -#define R_DMA_CH0_FIRST__first__first__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH0_HWSW - * - type: RW - * - addr: 0xb0000100 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH0_HWSW__ADDR (REG_TYPECAST_UDWORD 0xb0000100) -#define R_DMA_CH0_HWSW__SVAL REG_SVAL_SHADOW -#define R_DMA_CH0_HWSW__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH0_HWSW__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH0_HWSW__TYPE (REG_UDWORD) -#define R_DMA_CH0_HWSW__GET REG_GET_RW -#define R_DMA_CH0_HWSW__IGET REG_IGET_RW -#define R_DMA_CH0_HWSW__SET REG_SET_RW -#define R_DMA_CH0_HWSW__ISET REG_ISET_RW -#define R_DMA_CH0_HWSW__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH0_HWSW__EQL REG_EQL_RW -#define R_DMA_CH0_HWSW__IEQL REG_IEQL_RW -#define R_DMA_CH0_HWSW__RD REG_RD_RW -#define R_DMA_CH0_HWSW__IRD REG_IRD_RW -#define R_DMA_CH0_HWSW__WR REG_WR_RW -#define R_DMA_CH0_HWSW__IWR REG_IWR_RW - -#define R_DMA_CH0_HWSW__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH0_HWSW__READ(addr) \ - (*(addr)) - -/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */ -#define R_DMA_CH0_HWSW__FIRST 0 -#define R_DMA_CH0_HWSW__LAST 9 -#define R_DMA_CH0_HWSW__OFFSET 16 -/* end */ - -#define R_DMA_CH0_HWSW__hw__hw__MASK 0xffff0000U -#define R_DMA_CH0_HWSW__sw__sw__MASK 0x0000ffffU - -#define R_DMA_CH0_HWSW__hw__MAX 0xffff -#define R_DMA_CH0_HWSW__sw__MAX 0xffff - -#define R_DMA_CH0_HWSW__hw__MIN 0 -#define R_DMA_CH0_HWSW__sw__MIN 0 - -#define R_DMA_CH0_HWSW__hw__BITNR 16 -#define R_DMA_CH0_HWSW__sw__BITNR 0 - -#define R_DMA_CH0_HWSW__hw__hw__VAL REG_VAL_VAL -#define R_DMA_CH0_HWSW__sw__sw__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH0_NEXT - * - type: RW - * - addr: 0xb0000104 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH0_NEXT__ADDR (REG_TYPECAST_UDWORD 0xb0000104) -#define R_DMA_CH0_NEXT__SVAL REG_SVAL_SHADOW -#define R_DMA_CH0_NEXT__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH0_NEXT__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH0_NEXT__TYPE (REG_UDWORD) -#define R_DMA_CH0_NEXT__GET REG_GET_RW -#define R_DMA_CH0_NEXT__IGET REG_IGET_RW -#define R_DMA_CH0_NEXT__SET REG_SET_RW -#define R_DMA_CH0_NEXT__ISET REG_ISET_RW -#define R_DMA_CH0_NEXT__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH0_NEXT__EQL REG_EQL_RW -#define R_DMA_CH0_NEXT__IEQL REG_IEQL_RW -#define R_DMA_CH0_NEXT__RD REG_RD_RW -#define R_DMA_CH0_NEXT__IRD REG_IRD_RW -#define R_DMA_CH0_NEXT__WR REG_WR_RW -#define R_DMA_CH0_NEXT__IWR REG_IWR_RW - -#define R_DMA_CH0_NEXT__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH0_NEXT__READ(addr) \ - (*(addr)) - -/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */ -#define R_DMA_CH0_NEXT__FIRST 0 -#define R_DMA_CH0_NEXT__LAST 9 -#define R_DMA_CH0_NEXT__OFFSET 16 -/* end */ - -#define R_DMA_CH0_NEXT__next__next__MASK 0xffffffffU - -#define R_DMA_CH0_NEXT__next__MAX 0xffffffff - -#define R_DMA_CH0_NEXT__next__MIN 0 - -#define R_DMA_CH0_NEXT__next__BITNR 0 - -#define R_DMA_CH0_NEXT__next__next__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH0_STATUS - * - type: RO - * - addr: 0xb00001d2 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH0_STATUS__ADDR (REG_TYPECAST_BYTE 0xb00001d2) -#define R_DMA_CH0_STATUS__SVAL REG_SVAL_SHADOW -#define R_DMA_CH0_STATUS__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH0_STATUS__TYPECAST REG_TYPECAST_BYTE -#define R_DMA_CH0_STATUS__TYPE (REG_BYTE) -#define R_DMA_CH0_STATUS__GET REG_GET_RO -#define R_DMA_CH0_STATUS__IGET REG_IGET_RO -#define R_DMA_CH0_STATUS__SET REG_SET_RO -#define R_DMA_CH0_STATUS__ISET REG_ISET_RO -#define R_DMA_CH0_STATUS__SET_VAL REG_SET_VAL_RO -#define R_DMA_CH0_STATUS__EQL REG_EQL_RO -#define R_DMA_CH0_STATUS__IEQL REG_IEQL_RO -#define R_DMA_CH0_STATUS__RD REG_RD_RO -#define R_DMA_CH0_STATUS__IRD REG_IRD_RO -#define R_DMA_CH0_STATUS__WR REG_WR_RO -#define R_DMA_CH0_STATUS__IWR REG_IWR_RO - -#define R_DMA_CH0_STATUS__READ(addr) \ - (*(addr)) - -/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */ -#define R_DMA_CH0_STATUS__FIRST 0 -#define R_DMA_CH0_STATUS__LAST 9 -#define R_DMA_CH0_STATUS__OFFSET 4 -/* end */ - -#define R_DMA_CH0_STATUS__avail__avail__MASK 0x0000007fU - -#define R_DMA_CH0_STATUS__avail__MAX 0x7f - -#define R_DMA_CH0_STATUS__avail__MIN 0 - -#define R_DMA_CH0_STATUS__avail__BITNR 0 - -#define R_DMA_CH0_STATUS__avail__avail__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH1_BUF - * - type: RW - * - addr: 0xb0000118 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH1_BUF__ADDR (REG_TYPECAST_UDWORD 0xb0000118) -#define R_DMA_CH1_BUF__SVAL REG_SVAL_SHADOW -#define R_DMA_CH1_BUF__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH1_BUF__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH1_BUF__TYPE (REG_UDWORD) -#define R_DMA_CH1_BUF__GET REG_GET_RW -#define R_DMA_CH1_BUF__IGET REG_IGET_RW -#define R_DMA_CH1_BUF__SET REG_SET_RW -#define R_DMA_CH1_BUF__ISET REG_ISET_RW -#define R_DMA_CH1_BUF__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH1_BUF__EQL REG_EQL_RW -#define R_DMA_CH1_BUF__IEQL REG_IEQL_RW -#define R_DMA_CH1_BUF__RD REG_RD_RW -#define R_DMA_CH1_BUF__IRD REG_IRD_RW -#define R_DMA_CH1_BUF__WR REG_WR_RW -#define R_DMA_CH1_BUF__IWR REG_IWR_RW - -#define R_DMA_CH1_BUF__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH1_BUF__READ(addr) \ - (*(addr)) - -#define R_DMA_CH1_BUF__buf__buf__MASK 0xffffffffU - -#define R_DMA_CH1_BUF__buf__MAX 0xffffffff - -#define R_DMA_CH1_BUF__buf__MIN 0 - -#define R_DMA_CH1_BUF__buf__BITNR 0 - -#define R_DMA_CH1_BUF__buf__buf__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH1_CLR_INTR - * - type: WO - * - addr: 0xb00001d5 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH1_CLR_INTR__ADDR (REG_TYPECAST_BYTE 0xb00001d5) - -#ifndef REG_NO_SHADOW -#define R_DMA_CH1_CLR_INTR__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_DMA_CH1_CLR_INTR + 0)) -#define R_DMA_CH1_CLR_INTR__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_DMA_CH1_CLR_INTR + 0)) -#else /* REG_NO_SHADOW */ -#define R_DMA_CH1_CLR_INTR__SADDR (REG_STYPECAST_BYTE (®_shadow__hwregs)) -#define R_DMA_CH1_CLR_INTR__IADDR (REG_STYPECAST_BYTE (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_DMA_CH1_CLR_INTR__STYPECAST REG_STYPECAST_BYTE -#define R_DMA_CH1_CLR_INTR__SVAL REG_SVAL_ZERO -#define R_DMA_CH1_CLR_INTR__SVAL_I REG_SVAL_I_ZERO -#define R_DMA_CH1_CLR_INTR__TYPECAST REG_TYPECAST_BYTE -#define R_DMA_CH1_CLR_INTR__TYPE (REG_BYTE) -#define R_DMA_CH1_CLR_INTR__GET REG_GET_WO -#define R_DMA_CH1_CLR_INTR__IGET REG_IGET_WO -#define R_DMA_CH1_CLR_INTR__SET REG_SET_WO -#define R_DMA_CH1_CLR_INTR__ISET REG_ISET_WO -#define R_DMA_CH1_CLR_INTR__SET_VAL REG_SET_VAL_WO -#define R_DMA_CH1_CLR_INTR__EQL REG_EQL_WO -#define R_DMA_CH1_CLR_INTR__IEQL REG_IEQL_WO -#define R_DMA_CH1_CLR_INTR__RD REG_RD_WO -#define R_DMA_CH1_CLR_INTR__IRD REG_IRD_WO -#define R_DMA_CH1_CLR_INTR__WR REG_WR_WO -#define R_DMA_CH1_CLR_INTR__IWR REG_IWR_WO - -#define R_DMA_CH1_CLR_INTR__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_DMA_CH1_CLR_INTR__clr_eop__clr_eop__MASK 0x00000002U -#define R_DMA_CH1_CLR_INTR__clr_descr__clr_descr__MASK 0x00000001U - -#define R_DMA_CH1_CLR_INTR__clr_eop__MAX 0x1 -#define R_DMA_CH1_CLR_INTR__clr_descr__MAX 0x1 - -#define R_DMA_CH1_CLR_INTR__clr_eop__MIN 0 -#define R_DMA_CH1_CLR_INTR__clr_descr__MIN 0 - -#define R_DMA_CH1_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH1_CLR_INTR__clr_descr__BITNR 0 - -#define R_DMA_CH1_CLR_INTR__clr_eop__clr_eop__VAL REG_VAL_ENUM -#define R_DMA_CH1_CLR_INTR__clr_descr__clr_descr__VAL REG_VAL_ENUM - -#define R_DMA_CH1_CLR_INTR__clr_eop__clr_eop__do 1 -#define R_DMA_CH1_CLR_INTR__clr_eop__clr_eop__dont 0 -#define R_DMA_CH1_CLR_INTR__clr_descr__clr_descr__do 1 -#define R_DMA_CH1_CLR_INTR__clr_descr__clr_descr__dont 0 - -#endif - -/* - * R_DMA_CH1_CMD - * - type: RW - * - addr: 0xb00001d4 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH1_CMD__ADDR (REG_TYPECAST_BYTE 0xb00001d4) -#define R_DMA_CH1_CMD__SVAL REG_SVAL_SHADOW -#define R_DMA_CH1_CMD__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH1_CMD__TYPECAST REG_TYPECAST_BYTE -#define R_DMA_CH1_CMD__TYPE (REG_BYTE) -#define R_DMA_CH1_CMD__GET REG_GET_RW -#define R_DMA_CH1_CMD__IGET REG_IGET_RW -#define R_DMA_CH1_CMD__SET REG_SET_RW -#define R_DMA_CH1_CMD__ISET REG_ISET_RW -#define R_DMA_CH1_CMD__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH1_CMD__EQL REG_EQL_RW -#define R_DMA_CH1_CMD__IEQL REG_IEQL_RW -#define R_DMA_CH1_CMD__RD REG_RD_RW -#define R_DMA_CH1_CMD__IRD REG_IRD_RW -#define R_DMA_CH1_CMD__WR REG_WR_RW -#define R_DMA_CH1_CMD__IWR REG_IWR_RW - -#define R_DMA_CH1_CMD__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH1_CMD__READ(addr) \ - (*(addr)) - -#define R_DMA_CH1_CMD__cmd__cmd__MASK 0x00000007U - -#define R_DMA_CH1_CMD__cmd__MAX 0x7 - -#define R_DMA_CH1_CMD__cmd__MIN 0 - -#define R_DMA_CH1_CMD__cmd__BITNR 0 - -#define R_DMA_CH1_CMD__cmd__cmd__VAL REG_VAL_ENUM - -#define R_DMA_CH1_CMD__cmd__cmd__continue 3 -#define R_DMA_CH1_CMD__cmd__cmd__hold 0 -#define R_DMA_CH1_CMD__cmd__cmd__reset 4 -#define R_DMA_CH1_CMD__cmd__cmd__restart 3 -#define R_DMA_CH1_CMD__cmd__cmd__start 1 - -#endif - -/* - * R_DMA_CH1_DESCR - * - type: RW - * - addr: 0xb000011c - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH1_DESCR__ADDR (REG_TYPECAST_UDWORD 0xb000011c) -#define R_DMA_CH1_DESCR__SVAL REG_SVAL_SHADOW -#define R_DMA_CH1_DESCR__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH1_DESCR__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH1_DESCR__TYPE (REG_UDWORD) -#define R_DMA_CH1_DESCR__GET REG_GET_RW -#define R_DMA_CH1_DESCR__IGET REG_IGET_RW -#define R_DMA_CH1_DESCR__SET REG_SET_RW -#define R_DMA_CH1_DESCR__ISET REG_ISET_RW -#define R_DMA_CH1_DESCR__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH1_DESCR__EQL REG_EQL_RW -#define R_DMA_CH1_DESCR__IEQL REG_IEQL_RW -#define R_DMA_CH1_DESCR__RD REG_RD_RW -#define R_DMA_CH1_DESCR__IRD REG_IRD_RW -#define R_DMA_CH1_DESCR__WR REG_WR_RW -#define R_DMA_CH1_DESCR__IWR REG_IWR_RW - -#define R_DMA_CH1_DESCR__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH1_DESCR__READ(addr) \ - (*(addr)) - -#define R_DMA_CH1_DESCR__descr__descr__MASK 0xffffffffU - -#define R_DMA_CH1_DESCR__descr__MAX 0xffffffff - -#define R_DMA_CH1_DESCR__descr__MIN 0 - -#define R_DMA_CH1_DESCR__descr__BITNR 0 - -#define R_DMA_CH1_DESCR__descr__descr__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH1_FIRST - * - type: RW - * - addr: 0xb00001a4 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH1_FIRST__ADDR (REG_TYPECAST_UDWORD 0xb00001a4) -#define R_DMA_CH1_FIRST__SVAL REG_SVAL_SHADOW -#define R_DMA_CH1_FIRST__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH1_FIRST__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH1_FIRST__TYPE (REG_UDWORD) -#define R_DMA_CH1_FIRST__GET REG_GET_RW -#define R_DMA_CH1_FIRST__IGET REG_IGET_RW -#define R_DMA_CH1_FIRST__SET REG_SET_RW -#define R_DMA_CH1_FIRST__ISET REG_ISET_RW -#define R_DMA_CH1_FIRST__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH1_FIRST__EQL REG_EQL_RW -#define R_DMA_CH1_FIRST__IEQL REG_IEQL_RW -#define R_DMA_CH1_FIRST__RD REG_RD_RW -#define R_DMA_CH1_FIRST__IRD REG_IRD_RW -#define R_DMA_CH1_FIRST__WR REG_WR_RW -#define R_DMA_CH1_FIRST__IWR REG_IWR_RW - -#define R_DMA_CH1_FIRST__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH1_FIRST__READ(addr) \ - (*(addr)) - -#define R_DMA_CH1_FIRST__first__first__MASK 0xffffffffU - -#define R_DMA_CH1_FIRST__first__MAX 0xffffffff - -#define R_DMA_CH1_FIRST__first__MIN 0 - -#define R_DMA_CH1_FIRST__first__BITNR 0 - -#define R_DMA_CH1_FIRST__first__first__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH1_HWSW - * - type: RW - * - addr: 0xb0000110 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH1_HWSW__ADDR (REG_TYPECAST_UDWORD 0xb0000110) -#define R_DMA_CH1_HWSW__SVAL REG_SVAL_SHADOW -#define R_DMA_CH1_HWSW__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH1_HWSW__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH1_HWSW__TYPE (REG_UDWORD) -#define R_DMA_CH1_HWSW__GET REG_GET_RW -#define R_DMA_CH1_HWSW__IGET REG_IGET_RW -#define R_DMA_CH1_HWSW__SET REG_SET_RW -#define R_DMA_CH1_HWSW__ISET REG_ISET_RW -#define R_DMA_CH1_HWSW__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH1_HWSW__EQL REG_EQL_RW -#define R_DMA_CH1_HWSW__IEQL REG_IEQL_RW -#define R_DMA_CH1_HWSW__RD REG_RD_RW -#define R_DMA_CH1_HWSW__IRD REG_IRD_RW -#define R_DMA_CH1_HWSW__WR REG_WR_RW -#define R_DMA_CH1_HWSW__IWR REG_IWR_RW - -#define R_DMA_CH1_HWSW__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH1_HWSW__READ(addr) \ - (*(addr)) - -#define R_DMA_CH1_HWSW__hw__hw__MASK 0xffff0000U -#define R_DMA_CH1_HWSW__sw__sw__MASK 0x0000ffffU - -#define R_DMA_CH1_HWSW__hw__MAX 0xffff -#define R_DMA_CH1_HWSW__sw__MAX 0xffff - -#define R_DMA_CH1_HWSW__hw__MIN 0 -#define R_DMA_CH1_HWSW__sw__MIN 0 - -#define R_DMA_CH1_HWSW__hw__BITNR 16 -#define R_DMA_CH1_HWSW__sw__BITNR 0 - -#define R_DMA_CH1_HWSW__hw__hw__VAL REG_VAL_VAL -#define R_DMA_CH1_HWSW__sw__sw__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH1_NEXT - * - type: RW - * - addr: 0xb0000114 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH1_NEXT__ADDR (REG_TYPECAST_UDWORD 0xb0000114) -#define R_DMA_CH1_NEXT__SVAL REG_SVAL_SHADOW -#define R_DMA_CH1_NEXT__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH1_NEXT__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH1_NEXT__TYPE (REG_UDWORD) -#define R_DMA_CH1_NEXT__GET REG_GET_RW -#define R_DMA_CH1_NEXT__IGET REG_IGET_RW -#define R_DMA_CH1_NEXT__SET REG_SET_RW -#define R_DMA_CH1_NEXT__ISET REG_ISET_RW -#define R_DMA_CH1_NEXT__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH1_NEXT__EQL REG_EQL_RW -#define R_DMA_CH1_NEXT__IEQL REG_IEQL_RW -#define R_DMA_CH1_NEXT__RD REG_RD_RW -#define R_DMA_CH1_NEXT__IRD REG_IRD_RW -#define R_DMA_CH1_NEXT__WR REG_WR_RW -#define R_DMA_CH1_NEXT__IWR REG_IWR_RW - -#define R_DMA_CH1_NEXT__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH1_NEXT__READ(addr) \ - (*(addr)) - -#define R_DMA_CH1_NEXT__next__next__MASK 0xffffffffU - -#define R_DMA_CH1_NEXT__next__MAX 0xffffffff - -#define R_DMA_CH1_NEXT__next__MIN 0 - -#define R_DMA_CH1_NEXT__next__BITNR 0 - -#define R_DMA_CH1_NEXT__next__next__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH1_STATUS - * - type: RO - * - addr: 0xb00001d6 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH1_STATUS__ADDR (REG_TYPECAST_BYTE 0xb00001d6) -#define R_DMA_CH1_STATUS__SVAL REG_SVAL_SHADOW -#define R_DMA_CH1_STATUS__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH1_STATUS__TYPECAST REG_TYPECAST_BYTE -#define R_DMA_CH1_STATUS__TYPE (REG_BYTE) -#define R_DMA_CH1_STATUS__GET REG_GET_RO -#define R_DMA_CH1_STATUS__IGET REG_IGET_RO -#define R_DMA_CH1_STATUS__SET REG_SET_RO -#define R_DMA_CH1_STATUS__ISET REG_ISET_RO -#define R_DMA_CH1_STATUS__SET_VAL REG_SET_VAL_RO -#define R_DMA_CH1_STATUS__EQL REG_EQL_RO -#define R_DMA_CH1_STATUS__IEQL REG_IEQL_RO -#define R_DMA_CH1_STATUS__RD REG_RD_RO -#define R_DMA_CH1_STATUS__IRD REG_IRD_RO -#define R_DMA_CH1_STATUS__WR REG_WR_RO -#define R_DMA_CH1_STATUS__IWR REG_IWR_RO - -#define R_DMA_CH1_STATUS__READ(addr) \ - (*(addr)) - -#define R_DMA_CH1_STATUS__avail__avail__MASK 0x0000007fU - -#define R_DMA_CH1_STATUS__avail__MAX 0x7f - -#define R_DMA_CH1_STATUS__avail__MIN 0 - -#define R_DMA_CH1_STATUS__avail__BITNR 0 - -#define R_DMA_CH1_STATUS__avail__avail__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH2_BUF - * - type: RW - * - addr: 0xb0000128 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH2_BUF__ADDR (REG_TYPECAST_UDWORD 0xb0000128) -#define R_DMA_CH2_BUF__SVAL REG_SVAL_SHADOW -#define R_DMA_CH2_BUF__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH2_BUF__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH2_BUF__TYPE (REG_UDWORD) -#define R_DMA_CH2_BUF__GET REG_GET_RW -#define R_DMA_CH2_BUF__IGET REG_IGET_RW -#define R_DMA_CH2_BUF__SET REG_SET_RW -#define R_DMA_CH2_BUF__ISET REG_ISET_RW -#define R_DMA_CH2_BUF__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH2_BUF__EQL REG_EQL_RW -#define R_DMA_CH2_BUF__IEQL REG_IEQL_RW -#define R_DMA_CH2_BUF__RD REG_RD_RW -#define R_DMA_CH2_BUF__IRD REG_IRD_RW -#define R_DMA_CH2_BUF__WR REG_WR_RW -#define R_DMA_CH2_BUF__IWR REG_IWR_RW - -#define R_DMA_CH2_BUF__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH2_BUF__READ(addr) \ - (*(addr)) - -#define R_DMA_CH2_BUF__buf__buf__MASK 0xffffffffU - -#define R_DMA_CH2_BUF__buf__MAX 0xffffffff - -#define R_DMA_CH2_BUF__buf__MIN 0 - -#define R_DMA_CH2_BUF__buf__BITNR 0 - -#define R_DMA_CH2_BUF__buf__buf__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH2_CLR_INTR - * - type: WO - * - addr: 0xb00001d9 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH2_CLR_INTR__ADDR (REG_TYPECAST_BYTE 0xb00001d9) - -#ifndef REG_NO_SHADOW -#define R_DMA_CH2_CLR_INTR__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_DMA_CH2_CLR_INTR + 0)) -#define R_DMA_CH2_CLR_INTR__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_DMA_CH2_CLR_INTR + 0)) -#else /* REG_NO_SHADOW */ -#define R_DMA_CH2_CLR_INTR__SADDR (REG_STYPECAST_BYTE (®_shadow__hwregs)) -#define R_DMA_CH2_CLR_INTR__IADDR (REG_STYPECAST_BYTE (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_DMA_CH2_CLR_INTR__STYPECAST REG_STYPECAST_BYTE -#define R_DMA_CH2_CLR_INTR__SVAL REG_SVAL_ZERO -#define R_DMA_CH2_CLR_INTR__SVAL_I REG_SVAL_I_ZERO -#define R_DMA_CH2_CLR_INTR__TYPECAST REG_TYPECAST_BYTE -#define R_DMA_CH2_CLR_INTR__TYPE (REG_BYTE) -#define R_DMA_CH2_CLR_INTR__GET REG_GET_WO -#define R_DMA_CH2_CLR_INTR__IGET REG_IGET_WO -#define R_DMA_CH2_CLR_INTR__SET REG_SET_WO -#define R_DMA_CH2_CLR_INTR__ISET REG_ISET_WO -#define R_DMA_CH2_CLR_INTR__SET_VAL REG_SET_VAL_WO -#define R_DMA_CH2_CLR_INTR__EQL REG_EQL_WO -#define R_DMA_CH2_CLR_INTR__IEQL REG_IEQL_WO -#define R_DMA_CH2_CLR_INTR__RD REG_RD_WO -#define R_DMA_CH2_CLR_INTR__IRD REG_IRD_WO -#define R_DMA_CH2_CLR_INTR__WR REG_WR_WO -#define R_DMA_CH2_CLR_INTR__IWR REG_IWR_WO - -#define R_DMA_CH2_CLR_INTR__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_DMA_CH2_CLR_INTR__clr_eop__clr_eop__MASK 0x00000002U -#define R_DMA_CH2_CLR_INTR__clr_descr__clr_descr__MASK 0x00000001U - -#define R_DMA_CH2_CLR_INTR__clr_eop__MAX 0x1 -#define R_DMA_CH2_CLR_INTR__clr_descr__MAX 0x1 - -#define R_DMA_CH2_CLR_INTR__clr_eop__MIN 0 -#define R_DMA_CH2_CLR_INTR__clr_descr__MIN 0 - -#define R_DMA_CH2_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH2_CLR_INTR__clr_descr__BITNR 0 - -#define R_DMA_CH2_CLR_INTR__clr_eop__clr_eop__VAL REG_VAL_ENUM -#define R_DMA_CH2_CLR_INTR__clr_descr__clr_descr__VAL REG_VAL_ENUM - -#define R_DMA_CH2_CLR_INTR__clr_eop__clr_eop__do 1 -#define R_DMA_CH2_CLR_INTR__clr_eop__clr_eop__dont 0 -#define R_DMA_CH2_CLR_INTR__clr_descr__clr_descr__do 1 -#define R_DMA_CH2_CLR_INTR__clr_descr__clr_descr__dont 0 - -#endif - -/* - * R_DMA_CH2_CMD - * - type: RW - * - addr: 0xb00001d8 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH2_CMD__ADDR (REG_TYPECAST_BYTE 0xb00001d8) -#define R_DMA_CH2_CMD__SVAL REG_SVAL_SHADOW -#define R_DMA_CH2_CMD__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH2_CMD__TYPECAST REG_TYPECAST_BYTE -#define R_DMA_CH2_CMD__TYPE (REG_BYTE) -#define R_DMA_CH2_CMD__GET REG_GET_RW -#define R_DMA_CH2_CMD__IGET REG_IGET_RW -#define R_DMA_CH2_CMD__SET REG_SET_RW -#define R_DMA_CH2_CMD__ISET REG_ISET_RW -#define R_DMA_CH2_CMD__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH2_CMD__EQL REG_EQL_RW -#define R_DMA_CH2_CMD__IEQL REG_IEQL_RW -#define R_DMA_CH2_CMD__RD REG_RD_RW -#define R_DMA_CH2_CMD__IRD REG_IRD_RW -#define R_DMA_CH2_CMD__WR REG_WR_RW -#define R_DMA_CH2_CMD__IWR REG_IWR_RW - -#define R_DMA_CH2_CMD__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH2_CMD__READ(addr) \ - (*(addr)) - -#define R_DMA_CH2_CMD__cmd__cmd__MASK 0x00000007U - -#define R_DMA_CH2_CMD__cmd__MAX 0x7 - -#define R_DMA_CH2_CMD__cmd__MIN 0 - -#define R_DMA_CH2_CMD__cmd__BITNR 0 - -#define R_DMA_CH2_CMD__cmd__cmd__VAL REG_VAL_ENUM - -#define R_DMA_CH2_CMD__cmd__cmd__continue 3 -#define R_DMA_CH2_CMD__cmd__cmd__hold 0 -#define R_DMA_CH2_CMD__cmd__cmd__reset 4 -#define R_DMA_CH2_CMD__cmd__cmd__restart 3 -#define R_DMA_CH2_CMD__cmd__cmd__start 1 - -#endif - -/* - * R_DMA_CH2_DESCR - * - type: RW - * - addr: 0xb000012c - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH2_DESCR__ADDR (REG_TYPECAST_UDWORD 0xb000012c) -#define R_DMA_CH2_DESCR__SVAL REG_SVAL_SHADOW -#define R_DMA_CH2_DESCR__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH2_DESCR__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH2_DESCR__TYPE (REG_UDWORD) -#define R_DMA_CH2_DESCR__GET REG_GET_RW -#define R_DMA_CH2_DESCR__IGET REG_IGET_RW -#define R_DMA_CH2_DESCR__SET REG_SET_RW -#define R_DMA_CH2_DESCR__ISET REG_ISET_RW -#define R_DMA_CH2_DESCR__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH2_DESCR__EQL REG_EQL_RW -#define R_DMA_CH2_DESCR__IEQL REG_IEQL_RW -#define R_DMA_CH2_DESCR__RD REG_RD_RW -#define R_DMA_CH2_DESCR__IRD REG_IRD_RW -#define R_DMA_CH2_DESCR__WR REG_WR_RW -#define R_DMA_CH2_DESCR__IWR REG_IWR_RW - -#define R_DMA_CH2_DESCR__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH2_DESCR__READ(addr) \ - (*(addr)) - -#define R_DMA_CH2_DESCR__descr__descr__MASK 0xffffffffU - -#define R_DMA_CH2_DESCR__descr__MAX 0xffffffff - -#define R_DMA_CH2_DESCR__descr__MIN 0 - -#define R_DMA_CH2_DESCR__descr__BITNR 0 - -#define R_DMA_CH2_DESCR__descr__descr__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH2_FIRST - * - type: RW - * - addr: 0xb00001a8 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH2_FIRST__ADDR (REG_TYPECAST_UDWORD 0xb00001a8) -#define R_DMA_CH2_FIRST__SVAL REG_SVAL_SHADOW -#define R_DMA_CH2_FIRST__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH2_FIRST__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH2_FIRST__TYPE (REG_UDWORD) -#define R_DMA_CH2_FIRST__GET REG_GET_RW -#define R_DMA_CH2_FIRST__IGET REG_IGET_RW -#define R_DMA_CH2_FIRST__SET REG_SET_RW -#define R_DMA_CH2_FIRST__ISET REG_ISET_RW -#define R_DMA_CH2_FIRST__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH2_FIRST__EQL REG_EQL_RW -#define R_DMA_CH2_FIRST__IEQL REG_IEQL_RW -#define R_DMA_CH2_FIRST__RD REG_RD_RW -#define R_DMA_CH2_FIRST__IRD REG_IRD_RW -#define R_DMA_CH2_FIRST__WR REG_WR_RW -#define R_DMA_CH2_FIRST__IWR REG_IWR_RW - -#define R_DMA_CH2_FIRST__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH2_FIRST__READ(addr) \ - (*(addr)) - -#define R_DMA_CH2_FIRST__first__first__MASK 0xffffffffU - -#define R_DMA_CH2_FIRST__first__MAX 0xffffffff - -#define R_DMA_CH2_FIRST__first__MIN 0 - -#define R_DMA_CH2_FIRST__first__BITNR 0 - -#define R_DMA_CH2_FIRST__first__first__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH2_HWSW - * - type: RW - * - addr: 0xb0000120 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH2_HWSW__ADDR (REG_TYPECAST_UDWORD 0xb0000120) -#define R_DMA_CH2_HWSW__SVAL REG_SVAL_SHADOW -#define R_DMA_CH2_HWSW__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH2_HWSW__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH2_HWSW__TYPE (REG_UDWORD) -#define R_DMA_CH2_HWSW__GET REG_GET_RW -#define R_DMA_CH2_HWSW__IGET REG_IGET_RW -#define R_DMA_CH2_HWSW__SET REG_SET_RW -#define R_DMA_CH2_HWSW__ISET REG_ISET_RW -#define R_DMA_CH2_HWSW__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH2_HWSW__EQL REG_EQL_RW -#define R_DMA_CH2_HWSW__IEQL REG_IEQL_RW -#define R_DMA_CH2_HWSW__RD REG_RD_RW -#define R_DMA_CH2_HWSW__IRD REG_IRD_RW -#define R_DMA_CH2_HWSW__WR REG_WR_RW -#define R_DMA_CH2_HWSW__IWR REG_IWR_RW - -#define R_DMA_CH2_HWSW__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH2_HWSW__READ(addr) \ - (*(addr)) - -#define R_DMA_CH2_HWSW__hw__hw__MASK 0xffff0000U -#define R_DMA_CH2_HWSW__sw__sw__MASK 0x0000ffffU - -#define R_DMA_CH2_HWSW__hw__MAX 0xffff -#define R_DMA_CH2_HWSW__sw__MAX 0xffff - -#define R_DMA_CH2_HWSW__hw__MIN 0 -#define R_DMA_CH2_HWSW__sw__MIN 0 - -#define R_DMA_CH2_HWSW__hw__BITNR 16 -#define R_DMA_CH2_HWSW__sw__BITNR 0 - -#define R_DMA_CH2_HWSW__hw__hw__VAL REG_VAL_VAL -#define R_DMA_CH2_HWSW__sw__sw__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH2_NEXT - * - type: RW - * - addr: 0xb0000124 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH2_NEXT__ADDR (REG_TYPECAST_UDWORD 0xb0000124) -#define R_DMA_CH2_NEXT__SVAL REG_SVAL_SHADOW -#define R_DMA_CH2_NEXT__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH2_NEXT__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH2_NEXT__TYPE (REG_UDWORD) -#define R_DMA_CH2_NEXT__GET REG_GET_RW -#define R_DMA_CH2_NEXT__IGET REG_IGET_RW -#define R_DMA_CH2_NEXT__SET REG_SET_RW -#define R_DMA_CH2_NEXT__ISET REG_ISET_RW -#define R_DMA_CH2_NEXT__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH2_NEXT__EQL REG_EQL_RW -#define R_DMA_CH2_NEXT__IEQL REG_IEQL_RW -#define R_DMA_CH2_NEXT__RD REG_RD_RW -#define R_DMA_CH2_NEXT__IRD REG_IRD_RW -#define R_DMA_CH2_NEXT__WR REG_WR_RW -#define R_DMA_CH2_NEXT__IWR REG_IWR_RW - -#define R_DMA_CH2_NEXT__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH2_NEXT__READ(addr) \ - (*(addr)) - -#define R_DMA_CH2_NEXT__next__next__MASK 0xffffffffU - -#define R_DMA_CH2_NEXT__next__MAX 0xffffffff - -#define R_DMA_CH2_NEXT__next__MIN 0 - -#define R_DMA_CH2_NEXT__next__BITNR 0 - -#define R_DMA_CH2_NEXT__next__next__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH2_STATUS - * - type: RO - * - addr: 0xb00001da - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH2_STATUS__ADDR (REG_TYPECAST_BYTE 0xb00001da) -#define R_DMA_CH2_STATUS__SVAL REG_SVAL_SHADOW -#define R_DMA_CH2_STATUS__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH2_STATUS__TYPECAST REG_TYPECAST_BYTE -#define R_DMA_CH2_STATUS__TYPE (REG_BYTE) -#define R_DMA_CH2_STATUS__GET REG_GET_RO -#define R_DMA_CH2_STATUS__IGET REG_IGET_RO -#define R_DMA_CH2_STATUS__SET REG_SET_RO -#define R_DMA_CH2_STATUS__ISET REG_ISET_RO -#define R_DMA_CH2_STATUS__SET_VAL REG_SET_VAL_RO -#define R_DMA_CH2_STATUS__EQL REG_EQL_RO -#define R_DMA_CH2_STATUS__IEQL REG_IEQL_RO -#define R_DMA_CH2_STATUS__RD REG_RD_RO -#define R_DMA_CH2_STATUS__IRD REG_IRD_RO -#define R_DMA_CH2_STATUS__WR REG_WR_RO -#define R_DMA_CH2_STATUS__IWR REG_IWR_RO - -#define R_DMA_CH2_STATUS__READ(addr) \ - (*(addr)) - -#define R_DMA_CH2_STATUS__avail__avail__MASK 0x0000007fU - -#define R_DMA_CH2_STATUS__avail__MAX 0x7f - -#define R_DMA_CH2_STATUS__avail__MIN 0 - -#define R_DMA_CH2_STATUS__avail__BITNR 0 - -#define R_DMA_CH2_STATUS__avail__avail__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH3_BUF - * - type: RW - * - addr: 0xb0000138 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH3_BUF__ADDR (REG_TYPECAST_UDWORD 0xb0000138) -#define R_DMA_CH3_BUF__SVAL REG_SVAL_SHADOW -#define R_DMA_CH3_BUF__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH3_BUF__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH3_BUF__TYPE (REG_UDWORD) -#define R_DMA_CH3_BUF__GET REG_GET_RW -#define R_DMA_CH3_BUF__IGET REG_IGET_RW -#define R_DMA_CH3_BUF__SET REG_SET_RW -#define R_DMA_CH3_BUF__ISET REG_ISET_RW -#define R_DMA_CH3_BUF__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH3_BUF__EQL REG_EQL_RW -#define R_DMA_CH3_BUF__IEQL REG_IEQL_RW -#define R_DMA_CH3_BUF__RD REG_RD_RW -#define R_DMA_CH3_BUF__IRD REG_IRD_RW -#define R_DMA_CH3_BUF__WR REG_WR_RW -#define R_DMA_CH3_BUF__IWR REG_IWR_RW - -#define R_DMA_CH3_BUF__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH3_BUF__READ(addr) \ - (*(addr)) - -#define R_DMA_CH3_BUF__buf__buf__MASK 0xffffffffU - -#define R_DMA_CH3_BUF__buf__MAX 0xffffffff - -#define R_DMA_CH3_BUF__buf__MIN 0 - -#define R_DMA_CH3_BUF__buf__BITNR 0 - -#define R_DMA_CH3_BUF__buf__buf__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH3_CLR_INTR - * - type: WO - * - addr: 0xb00001dd - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH3_CLR_INTR__ADDR (REG_TYPECAST_BYTE 0xb00001dd) - -#ifndef REG_NO_SHADOW -#define R_DMA_CH3_CLR_INTR__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_DMA_CH3_CLR_INTR + 0)) -#define R_DMA_CH3_CLR_INTR__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_DMA_CH3_CLR_INTR + 0)) -#else /* REG_NO_SHADOW */ -#define R_DMA_CH3_CLR_INTR__SADDR (REG_STYPECAST_BYTE (®_shadow__hwregs)) -#define R_DMA_CH3_CLR_INTR__IADDR (REG_STYPECAST_BYTE (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_DMA_CH3_CLR_INTR__STYPECAST REG_STYPECAST_BYTE -#define R_DMA_CH3_CLR_INTR__SVAL REG_SVAL_ZERO -#define R_DMA_CH3_CLR_INTR__SVAL_I REG_SVAL_I_ZERO -#define R_DMA_CH3_CLR_INTR__TYPECAST REG_TYPECAST_BYTE -#define R_DMA_CH3_CLR_INTR__TYPE (REG_BYTE) -#define R_DMA_CH3_CLR_INTR__GET REG_GET_WO -#define R_DMA_CH3_CLR_INTR__IGET REG_IGET_WO -#define R_DMA_CH3_CLR_INTR__SET REG_SET_WO -#define R_DMA_CH3_CLR_INTR__ISET REG_ISET_WO -#define R_DMA_CH3_CLR_INTR__SET_VAL REG_SET_VAL_WO -#define R_DMA_CH3_CLR_INTR__EQL REG_EQL_WO -#define R_DMA_CH3_CLR_INTR__IEQL REG_IEQL_WO -#define R_DMA_CH3_CLR_INTR__RD REG_RD_WO -#define R_DMA_CH3_CLR_INTR__IRD REG_IRD_WO -#define R_DMA_CH3_CLR_INTR__WR REG_WR_WO -#define R_DMA_CH3_CLR_INTR__IWR REG_IWR_WO - -#define R_DMA_CH3_CLR_INTR__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_DMA_CH3_CLR_INTR__clr_eop__clr_eop__MASK 0x00000002U -#define R_DMA_CH3_CLR_INTR__clr_descr__clr_descr__MASK 0x00000001U - -#define R_DMA_CH3_CLR_INTR__clr_eop__MAX 0x1 -#define R_DMA_CH3_CLR_INTR__clr_descr__MAX 0x1 - -#define R_DMA_CH3_CLR_INTR__clr_eop__MIN 0 -#define R_DMA_CH3_CLR_INTR__clr_descr__MIN 0 - -#define R_DMA_CH3_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH3_CLR_INTR__clr_descr__BITNR 0 - -#define R_DMA_CH3_CLR_INTR__clr_eop__clr_eop__VAL REG_VAL_ENUM -#define R_DMA_CH3_CLR_INTR__clr_descr__clr_descr__VAL REG_VAL_ENUM - -#define R_DMA_CH3_CLR_INTR__clr_eop__clr_eop__do 1 -#define R_DMA_CH3_CLR_INTR__clr_eop__clr_eop__dont 0 -#define R_DMA_CH3_CLR_INTR__clr_descr__clr_descr__do 1 -#define R_DMA_CH3_CLR_INTR__clr_descr__clr_descr__dont 0 - -#endif - -/* - * R_DMA_CH3_CMD - * - type: RW - * - addr: 0xb00001dc - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH3_CMD__ADDR (REG_TYPECAST_BYTE 0xb00001dc) -#define R_DMA_CH3_CMD__SVAL REG_SVAL_SHADOW -#define R_DMA_CH3_CMD__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH3_CMD__TYPECAST REG_TYPECAST_BYTE -#define R_DMA_CH3_CMD__TYPE (REG_BYTE) -#define R_DMA_CH3_CMD__GET REG_GET_RW -#define R_DMA_CH3_CMD__IGET REG_IGET_RW -#define R_DMA_CH3_CMD__SET REG_SET_RW -#define R_DMA_CH3_CMD__ISET REG_ISET_RW -#define R_DMA_CH3_CMD__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH3_CMD__EQL REG_EQL_RW -#define R_DMA_CH3_CMD__IEQL REG_IEQL_RW -#define R_DMA_CH3_CMD__RD REG_RD_RW -#define R_DMA_CH3_CMD__IRD REG_IRD_RW -#define R_DMA_CH3_CMD__WR REG_WR_RW -#define R_DMA_CH3_CMD__IWR REG_IWR_RW - -#define R_DMA_CH3_CMD__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH3_CMD__READ(addr) \ - (*(addr)) - -#define R_DMA_CH3_CMD__cmd__cmd__MASK 0x00000007U - -#define R_DMA_CH3_CMD__cmd__MAX 0x7 - -#define R_DMA_CH3_CMD__cmd__MIN 0 - -#define R_DMA_CH3_CMD__cmd__BITNR 0 - -#define R_DMA_CH3_CMD__cmd__cmd__VAL REG_VAL_ENUM - -#define R_DMA_CH3_CMD__cmd__cmd__continue 3 -#define R_DMA_CH3_CMD__cmd__cmd__hold 0 -#define R_DMA_CH3_CMD__cmd__cmd__reset 4 -#define R_DMA_CH3_CMD__cmd__cmd__restart 3 -#define R_DMA_CH3_CMD__cmd__cmd__start 1 - -#endif - -/* - * R_DMA_CH3_DESCR - * - type: RW - * - addr: 0xb000013c - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH3_DESCR__ADDR (REG_TYPECAST_UDWORD 0xb000013c) -#define R_DMA_CH3_DESCR__SVAL REG_SVAL_SHADOW -#define R_DMA_CH3_DESCR__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH3_DESCR__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH3_DESCR__TYPE (REG_UDWORD) -#define R_DMA_CH3_DESCR__GET REG_GET_RW -#define R_DMA_CH3_DESCR__IGET REG_IGET_RW -#define R_DMA_CH3_DESCR__SET REG_SET_RW -#define R_DMA_CH3_DESCR__ISET REG_ISET_RW -#define R_DMA_CH3_DESCR__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH3_DESCR__EQL REG_EQL_RW -#define R_DMA_CH3_DESCR__IEQL REG_IEQL_RW -#define R_DMA_CH3_DESCR__RD REG_RD_RW -#define R_DMA_CH3_DESCR__IRD REG_IRD_RW -#define R_DMA_CH3_DESCR__WR REG_WR_RW -#define R_DMA_CH3_DESCR__IWR REG_IWR_RW - -#define R_DMA_CH3_DESCR__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH3_DESCR__READ(addr) \ - (*(addr)) - -#define R_DMA_CH3_DESCR__descr__descr__MASK 0xffffffffU - -#define R_DMA_CH3_DESCR__descr__MAX 0xffffffff - -#define R_DMA_CH3_DESCR__descr__MIN 0 - -#define R_DMA_CH3_DESCR__descr__BITNR 0 - -#define R_DMA_CH3_DESCR__descr__descr__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH3_FIRST - * - type: RW - * - addr: 0xb00001ac - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH3_FIRST__ADDR (REG_TYPECAST_UDWORD 0xb00001ac) -#define R_DMA_CH3_FIRST__SVAL REG_SVAL_SHADOW -#define R_DMA_CH3_FIRST__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH3_FIRST__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH3_FIRST__TYPE (REG_UDWORD) -#define R_DMA_CH3_FIRST__GET REG_GET_RW -#define R_DMA_CH3_FIRST__IGET REG_IGET_RW -#define R_DMA_CH3_FIRST__SET REG_SET_RW -#define R_DMA_CH3_FIRST__ISET REG_ISET_RW -#define R_DMA_CH3_FIRST__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH3_FIRST__EQL REG_EQL_RW -#define R_DMA_CH3_FIRST__IEQL REG_IEQL_RW -#define R_DMA_CH3_FIRST__RD REG_RD_RW -#define R_DMA_CH3_FIRST__IRD REG_IRD_RW -#define R_DMA_CH3_FIRST__WR REG_WR_RW -#define R_DMA_CH3_FIRST__IWR REG_IWR_RW - -#define R_DMA_CH3_FIRST__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH3_FIRST__READ(addr) \ - (*(addr)) - -#define R_DMA_CH3_FIRST__first__first__MASK 0xffffffffU - -#define R_DMA_CH3_FIRST__first__MAX 0xffffffff - -#define R_DMA_CH3_FIRST__first__MIN 0 - -#define R_DMA_CH3_FIRST__first__BITNR 0 - -#define R_DMA_CH3_FIRST__first__first__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH3_HWSW - * - type: RW - * - addr: 0xb0000130 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH3_HWSW__ADDR (REG_TYPECAST_UDWORD 0xb0000130) -#define R_DMA_CH3_HWSW__SVAL REG_SVAL_SHADOW -#define R_DMA_CH3_HWSW__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH3_HWSW__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH3_HWSW__TYPE (REG_UDWORD) -#define R_DMA_CH3_HWSW__GET REG_GET_RW -#define R_DMA_CH3_HWSW__IGET REG_IGET_RW -#define R_DMA_CH3_HWSW__SET REG_SET_RW -#define R_DMA_CH3_HWSW__ISET REG_ISET_RW -#define R_DMA_CH3_HWSW__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH3_HWSW__EQL REG_EQL_RW -#define R_DMA_CH3_HWSW__IEQL REG_IEQL_RW -#define R_DMA_CH3_HWSW__RD REG_RD_RW -#define R_DMA_CH3_HWSW__IRD REG_IRD_RW -#define R_DMA_CH3_HWSW__WR REG_WR_RW -#define R_DMA_CH3_HWSW__IWR REG_IWR_RW - -#define R_DMA_CH3_HWSW__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH3_HWSW__READ(addr) \ - (*(addr)) - -#define R_DMA_CH3_HWSW__hw__hw__MASK 0xffff0000U -#define R_DMA_CH3_HWSW__sw__sw__MASK 0x0000ffffU - -#define R_DMA_CH3_HWSW__hw__MAX 0xffff -#define R_DMA_CH3_HWSW__sw__MAX 0xffff - -#define R_DMA_CH3_HWSW__hw__MIN 0 -#define R_DMA_CH3_HWSW__sw__MIN 0 - -#define R_DMA_CH3_HWSW__hw__BITNR 16 -#define R_DMA_CH3_HWSW__sw__BITNR 0 - -#define R_DMA_CH3_HWSW__hw__hw__VAL REG_VAL_VAL -#define R_DMA_CH3_HWSW__sw__sw__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH3_NEXT - * - type: RW - * - addr: 0xb0000134 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH3_NEXT__ADDR (REG_TYPECAST_UDWORD 0xb0000134) -#define R_DMA_CH3_NEXT__SVAL REG_SVAL_SHADOW -#define R_DMA_CH3_NEXT__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH3_NEXT__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH3_NEXT__TYPE (REG_UDWORD) -#define R_DMA_CH3_NEXT__GET REG_GET_RW -#define R_DMA_CH3_NEXT__IGET REG_IGET_RW -#define R_DMA_CH3_NEXT__SET REG_SET_RW -#define R_DMA_CH3_NEXT__ISET REG_ISET_RW -#define R_DMA_CH3_NEXT__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH3_NEXT__EQL REG_EQL_RW -#define R_DMA_CH3_NEXT__IEQL REG_IEQL_RW -#define R_DMA_CH3_NEXT__RD REG_RD_RW -#define R_DMA_CH3_NEXT__IRD REG_IRD_RW -#define R_DMA_CH3_NEXT__WR REG_WR_RW -#define R_DMA_CH3_NEXT__IWR REG_IWR_RW - -#define R_DMA_CH3_NEXT__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH3_NEXT__READ(addr) \ - (*(addr)) - -#define R_DMA_CH3_NEXT__next__next__MASK 0xffffffffU - -#define R_DMA_CH3_NEXT__next__MAX 0xffffffff - -#define R_DMA_CH3_NEXT__next__MIN 0 - -#define R_DMA_CH3_NEXT__next__BITNR 0 - -#define R_DMA_CH3_NEXT__next__next__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH3_STATUS - * - type: RO - * - addr: 0xb00001de - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH3_STATUS__ADDR (REG_TYPECAST_BYTE 0xb00001de) -#define R_DMA_CH3_STATUS__SVAL REG_SVAL_SHADOW -#define R_DMA_CH3_STATUS__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH3_STATUS__TYPECAST REG_TYPECAST_BYTE -#define R_DMA_CH3_STATUS__TYPE (REG_BYTE) -#define R_DMA_CH3_STATUS__GET REG_GET_RO -#define R_DMA_CH3_STATUS__IGET REG_IGET_RO -#define R_DMA_CH3_STATUS__SET REG_SET_RO -#define R_DMA_CH3_STATUS__ISET REG_ISET_RO -#define R_DMA_CH3_STATUS__SET_VAL REG_SET_VAL_RO -#define R_DMA_CH3_STATUS__EQL REG_EQL_RO -#define R_DMA_CH3_STATUS__IEQL REG_IEQL_RO -#define R_DMA_CH3_STATUS__RD REG_RD_RO -#define R_DMA_CH3_STATUS__IRD REG_IRD_RO -#define R_DMA_CH3_STATUS__WR REG_WR_RO -#define R_DMA_CH3_STATUS__IWR REG_IWR_RO - -#define R_DMA_CH3_STATUS__READ(addr) \ - (*(addr)) - -#define R_DMA_CH3_STATUS__avail__avail__MASK 0x0000007fU - -#define R_DMA_CH3_STATUS__avail__MAX 0x7f - -#define R_DMA_CH3_STATUS__avail__MIN 0 - -#define R_DMA_CH3_STATUS__avail__BITNR 0 - -#define R_DMA_CH3_STATUS__avail__avail__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH4_BUF - * - type: RW - * - addr: 0xb0000148 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH4_BUF__ADDR (REG_TYPECAST_UDWORD 0xb0000148) -#define R_DMA_CH4_BUF__SVAL REG_SVAL_SHADOW -#define R_DMA_CH4_BUF__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH4_BUF__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH4_BUF__TYPE (REG_UDWORD) -#define R_DMA_CH4_BUF__GET REG_GET_RW -#define R_DMA_CH4_BUF__IGET REG_IGET_RW -#define R_DMA_CH4_BUF__SET REG_SET_RW -#define R_DMA_CH4_BUF__ISET REG_ISET_RW -#define R_DMA_CH4_BUF__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH4_BUF__EQL REG_EQL_RW -#define R_DMA_CH4_BUF__IEQL REG_IEQL_RW -#define R_DMA_CH4_BUF__RD REG_RD_RW -#define R_DMA_CH4_BUF__IRD REG_IRD_RW -#define R_DMA_CH4_BUF__WR REG_WR_RW -#define R_DMA_CH4_BUF__IWR REG_IWR_RW - -#define R_DMA_CH4_BUF__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH4_BUF__READ(addr) \ - (*(addr)) - -#define R_DMA_CH4_BUF__buf__buf__MASK 0xffffffffU - -#define R_DMA_CH4_BUF__buf__MAX 0xffffffff - -#define R_DMA_CH4_BUF__buf__MIN 0 - -#define R_DMA_CH4_BUF__buf__BITNR 0 - -#define R_DMA_CH4_BUF__buf__buf__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH4_CLR_INTR - * - type: WO - * - addr: 0xb00001e1 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH4_CLR_INTR__ADDR (REG_TYPECAST_BYTE 0xb00001e1) - -#ifndef REG_NO_SHADOW -#define R_DMA_CH4_CLR_INTR__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_DMA_CH4_CLR_INTR + 0)) -#define R_DMA_CH4_CLR_INTR__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_DMA_CH4_CLR_INTR + 0)) -#else /* REG_NO_SHADOW */ -#define R_DMA_CH4_CLR_INTR__SADDR (REG_STYPECAST_BYTE (®_shadow__hwregs)) -#define R_DMA_CH4_CLR_INTR__IADDR (REG_STYPECAST_BYTE (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_DMA_CH4_CLR_INTR__STYPECAST REG_STYPECAST_BYTE -#define R_DMA_CH4_CLR_INTR__SVAL REG_SVAL_ZERO -#define R_DMA_CH4_CLR_INTR__SVAL_I REG_SVAL_I_ZERO -#define R_DMA_CH4_CLR_INTR__TYPECAST REG_TYPECAST_BYTE -#define R_DMA_CH4_CLR_INTR__TYPE (REG_BYTE) -#define R_DMA_CH4_CLR_INTR__GET REG_GET_WO -#define R_DMA_CH4_CLR_INTR__IGET REG_IGET_WO -#define R_DMA_CH4_CLR_INTR__SET REG_SET_WO -#define R_DMA_CH4_CLR_INTR__ISET REG_ISET_WO -#define R_DMA_CH4_CLR_INTR__SET_VAL REG_SET_VAL_WO -#define R_DMA_CH4_CLR_INTR__EQL REG_EQL_WO -#define R_DMA_CH4_CLR_INTR__IEQL REG_IEQL_WO -#define R_DMA_CH4_CLR_INTR__RD REG_RD_WO -#define R_DMA_CH4_CLR_INTR__IRD REG_IRD_WO -#define R_DMA_CH4_CLR_INTR__WR REG_WR_WO -#define R_DMA_CH4_CLR_INTR__IWR REG_IWR_WO - -#define R_DMA_CH4_CLR_INTR__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_DMA_CH4_CLR_INTR__clr_eop__clr_eop__MASK 0x00000002U -#define R_DMA_CH4_CLR_INTR__clr_descr__clr_descr__MASK 0x00000001U - -#define R_DMA_CH4_CLR_INTR__clr_eop__MAX 0x1 -#define R_DMA_CH4_CLR_INTR__clr_descr__MAX 0x1 - -#define R_DMA_CH4_CLR_INTR__clr_eop__MIN 0 -#define R_DMA_CH4_CLR_INTR__clr_descr__MIN 0 - -#define R_DMA_CH4_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH4_CLR_INTR__clr_descr__BITNR 0 - -#define R_DMA_CH4_CLR_INTR__clr_eop__clr_eop__VAL REG_VAL_ENUM -#define R_DMA_CH4_CLR_INTR__clr_descr__clr_descr__VAL REG_VAL_ENUM - -#define R_DMA_CH4_CLR_INTR__clr_eop__clr_eop__do 1 -#define R_DMA_CH4_CLR_INTR__clr_eop__clr_eop__dont 0 -#define R_DMA_CH4_CLR_INTR__clr_descr__clr_descr__do 1 -#define R_DMA_CH4_CLR_INTR__clr_descr__clr_descr__dont 0 - -#endif - -/* - * R_DMA_CH4_CMD - * - type: RW - * - addr: 0xb00001e0 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH4_CMD__ADDR (REG_TYPECAST_BYTE 0xb00001e0) -#define R_DMA_CH4_CMD__SVAL REG_SVAL_SHADOW -#define R_DMA_CH4_CMD__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH4_CMD__TYPECAST REG_TYPECAST_BYTE -#define R_DMA_CH4_CMD__TYPE (REG_BYTE) -#define R_DMA_CH4_CMD__GET REG_GET_RW -#define R_DMA_CH4_CMD__IGET REG_IGET_RW -#define R_DMA_CH4_CMD__SET REG_SET_RW -#define R_DMA_CH4_CMD__ISET REG_ISET_RW -#define R_DMA_CH4_CMD__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH4_CMD__EQL REG_EQL_RW -#define R_DMA_CH4_CMD__IEQL REG_IEQL_RW -#define R_DMA_CH4_CMD__RD REG_RD_RW -#define R_DMA_CH4_CMD__IRD REG_IRD_RW -#define R_DMA_CH4_CMD__WR REG_WR_RW -#define R_DMA_CH4_CMD__IWR REG_IWR_RW - -#define R_DMA_CH4_CMD__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH4_CMD__READ(addr) \ - (*(addr)) - -#define R_DMA_CH4_CMD__cmd__cmd__MASK 0x00000007U - -#define R_DMA_CH4_CMD__cmd__MAX 0x7 - -#define R_DMA_CH4_CMD__cmd__MIN 0 - -#define R_DMA_CH4_CMD__cmd__BITNR 0 - -#define R_DMA_CH4_CMD__cmd__cmd__VAL REG_VAL_ENUM - -#define R_DMA_CH4_CMD__cmd__cmd__continue 3 -#define R_DMA_CH4_CMD__cmd__cmd__hold 0 -#define R_DMA_CH4_CMD__cmd__cmd__reset 4 -#define R_DMA_CH4_CMD__cmd__cmd__restart 3 -#define R_DMA_CH4_CMD__cmd__cmd__start 1 - -#endif - -/* - * R_DMA_CH4_DESCR - * - type: RW - * - addr: 0xb000014c - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH4_DESCR__ADDR (REG_TYPECAST_UDWORD 0xb000014c) -#define R_DMA_CH4_DESCR__SVAL REG_SVAL_SHADOW -#define R_DMA_CH4_DESCR__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH4_DESCR__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH4_DESCR__TYPE (REG_UDWORD) -#define R_DMA_CH4_DESCR__GET REG_GET_RW -#define R_DMA_CH4_DESCR__IGET REG_IGET_RW -#define R_DMA_CH4_DESCR__SET REG_SET_RW -#define R_DMA_CH4_DESCR__ISET REG_ISET_RW -#define R_DMA_CH4_DESCR__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH4_DESCR__EQL REG_EQL_RW -#define R_DMA_CH4_DESCR__IEQL REG_IEQL_RW -#define R_DMA_CH4_DESCR__RD REG_RD_RW -#define R_DMA_CH4_DESCR__IRD REG_IRD_RW -#define R_DMA_CH4_DESCR__WR REG_WR_RW -#define R_DMA_CH4_DESCR__IWR REG_IWR_RW - -#define R_DMA_CH4_DESCR__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH4_DESCR__READ(addr) \ - (*(addr)) - -#define R_DMA_CH4_DESCR__descr__descr__MASK 0xffffffffU - -#define R_DMA_CH4_DESCR__descr__MAX 0xffffffff - -#define R_DMA_CH4_DESCR__descr__MIN 0 - -#define R_DMA_CH4_DESCR__descr__BITNR 0 - -#define R_DMA_CH4_DESCR__descr__descr__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH4_FIRST - * - type: RW - * - addr: 0xb00001b0 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH4_FIRST__ADDR (REG_TYPECAST_UDWORD 0xb00001b0) -#define R_DMA_CH4_FIRST__SVAL REG_SVAL_SHADOW -#define R_DMA_CH4_FIRST__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH4_FIRST__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH4_FIRST__TYPE (REG_UDWORD) -#define R_DMA_CH4_FIRST__GET REG_GET_RW -#define R_DMA_CH4_FIRST__IGET REG_IGET_RW -#define R_DMA_CH4_FIRST__SET REG_SET_RW -#define R_DMA_CH4_FIRST__ISET REG_ISET_RW -#define R_DMA_CH4_FIRST__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH4_FIRST__EQL REG_EQL_RW -#define R_DMA_CH4_FIRST__IEQL REG_IEQL_RW -#define R_DMA_CH4_FIRST__RD REG_RD_RW -#define R_DMA_CH4_FIRST__IRD REG_IRD_RW -#define R_DMA_CH4_FIRST__WR REG_WR_RW -#define R_DMA_CH4_FIRST__IWR REG_IWR_RW - -#define R_DMA_CH4_FIRST__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH4_FIRST__READ(addr) \ - (*(addr)) - -#define R_DMA_CH4_FIRST__first__first__MASK 0xffffffffU - -#define R_DMA_CH4_FIRST__first__MAX 0xffffffff - -#define R_DMA_CH4_FIRST__first__MIN 0 - -#define R_DMA_CH4_FIRST__first__BITNR 0 - -#define R_DMA_CH4_FIRST__first__first__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH4_HWSW - * - type: RW - * - addr: 0xb0000140 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH4_HWSW__ADDR (REG_TYPECAST_UDWORD 0xb0000140) -#define R_DMA_CH4_HWSW__SVAL REG_SVAL_SHADOW -#define R_DMA_CH4_HWSW__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH4_HWSW__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH4_HWSW__TYPE (REG_UDWORD) -#define R_DMA_CH4_HWSW__GET REG_GET_RW -#define R_DMA_CH4_HWSW__IGET REG_IGET_RW -#define R_DMA_CH4_HWSW__SET REG_SET_RW -#define R_DMA_CH4_HWSW__ISET REG_ISET_RW -#define R_DMA_CH4_HWSW__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH4_HWSW__EQL REG_EQL_RW -#define R_DMA_CH4_HWSW__IEQL REG_IEQL_RW -#define R_DMA_CH4_HWSW__RD REG_RD_RW -#define R_DMA_CH4_HWSW__IRD REG_IRD_RW -#define R_DMA_CH4_HWSW__WR REG_WR_RW -#define R_DMA_CH4_HWSW__IWR REG_IWR_RW - -#define R_DMA_CH4_HWSW__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH4_HWSW__READ(addr) \ - (*(addr)) - -#define R_DMA_CH4_HWSW__hw__hw__MASK 0xffff0000U -#define R_DMA_CH4_HWSW__sw__sw__MASK 0x0000ffffU - -#define R_DMA_CH4_HWSW__hw__MAX 0xffff -#define R_DMA_CH4_HWSW__sw__MAX 0xffff - -#define R_DMA_CH4_HWSW__hw__MIN 0 -#define R_DMA_CH4_HWSW__sw__MIN 0 - -#define R_DMA_CH4_HWSW__hw__BITNR 16 -#define R_DMA_CH4_HWSW__sw__BITNR 0 - -#define R_DMA_CH4_HWSW__hw__hw__VAL REG_VAL_VAL -#define R_DMA_CH4_HWSW__sw__sw__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH4_NEXT - * - type: RW - * - addr: 0xb0000144 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH4_NEXT__ADDR (REG_TYPECAST_UDWORD 0xb0000144) -#define R_DMA_CH4_NEXT__SVAL REG_SVAL_SHADOW -#define R_DMA_CH4_NEXT__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH4_NEXT__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH4_NEXT__TYPE (REG_UDWORD) -#define R_DMA_CH4_NEXT__GET REG_GET_RW -#define R_DMA_CH4_NEXT__IGET REG_IGET_RW -#define R_DMA_CH4_NEXT__SET REG_SET_RW -#define R_DMA_CH4_NEXT__ISET REG_ISET_RW -#define R_DMA_CH4_NEXT__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH4_NEXT__EQL REG_EQL_RW -#define R_DMA_CH4_NEXT__IEQL REG_IEQL_RW -#define R_DMA_CH4_NEXT__RD REG_RD_RW -#define R_DMA_CH4_NEXT__IRD REG_IRD_RW -#define R_DMA_CH4_NEXT__WR REG_WR_RW -#define R_DMA_CH4_NEXT__IWR REG_IWR_RW - -#define R_DMA_CH4_NEXT__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH4_NEXT__READ(addr) \ - (*(addr)) - -#define R_DMA_CH4_NEXT__next__next__MASK 0xffffffffU - -#define R_DMA_CH4_NEXT__next__MAX 0xffffffff - -#define R_DMA_CH4_NEXT__next__MIN 0 - -#define R_DMA_CH4_NEXT__next__BITNR 0 - -#define R_DMA_CH4_NEXT__next__next__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH4_STATUS - * - type: RO - * - addr: 0xb00001e2 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH4_STATUS__ADDR (REG_TYPECAST_BYTE 0xb00001e2) -#define R_DMA_CH4_STATUS__SVAL REG_SVAL_SHADOW -#define R_DMA_CH4_STATUS__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH4_STATUS__TYPECAST REG_TYPECAST_BYTE -#define R_DMA_CH4_STATUS__TYPE (REG_BYTE) -#define R_DMA_CH4_STATUS__GET REG_GET_RO -#define R_DMA_CH4_STATUS__IGET REG_IGET_RO -#define R_DMA_CH4_STATUS__SET REG_SET_RO -#define R_DMA_CH4_STATUS__ISET REG_ISET_RO -#define R_DMA_CH4_STATUS__SET_VAL REG_SET_VAL_RO -#define R_DMA_CH4_STATUS__EQL REG_EQL_RO -#define R_DMA_CH4_STATUS__IEQL REG_IEQL_RO -#define R_DMA_CH4_STATUS__RD REG_RD_RO -#define R_DMA_CH4_STATUS__IRD REG_IRD_RO -#define R_DMA_CH4_STATUS__WR REG_WR_RO -#define R_DMA_CH4_STATUS__IWR REG_IWR_RO - -#define R_DMA_CH4_STATUS__READ(addr) \ - (*(addr)) - -#define R_DMA_CH4_STATUS__avail__avail__MASK 0x0000007fU - -#define R_DMA_CH4_STATUS__avail__MAX 0x7f - -#define R_DMA_CH4_STATUS__avail__MIN 0 - -#define R_DMA_CH4_STATUS__avail__BITNR 0 - -#define R_DMA_CH4_STATUS__avail__avail__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH5_BUF - * - type: RW - * - addr: 0xb0000158 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH5_BUF__ADDR (REG_TYPECAST_UDWORD 0xb0000158) -#define R_DMA_CH5_BUF__SVAL REG_SVAL_SHADOW -#define R_DMA_CH5_BUF__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH5_BUF__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH5_BUF__TYPE (REG_UDWORD) -#define R_DMA_CH5_BUF__GET REG_GET_RW -#define R_DMA_CH5_BUF__IGET REG_IGET_RW -#define R_DMA_CH5_BUF__SET REG_SET_RW -#define R_DMA_CH5_BUF__ISET REG_ISET_RW -#define R_DMA_CH5_BUF__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH5_BUF__EQL REG_EQL_RW -#define R_DMA_CH5_BUF__IEQL REG_IEQL_RW -#define R_DMA_CH5_BUF__RD REG_RD_RW -#define R_DMA_CH5_BUF__IRD REG_IRD_RW -#define R_DMA_CH5_BUF__WR REG_WR_RW -#define R_DMA_CH5_BUF__IWR REG_IWR_RW - -#define R_DMA_CH5_BUF__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH5_BUF__READ(addr) \ - (*(addr)) - -#define R_DMA_CH5_BUF__buf__buf__MASK 0xffffffffU - -#define R_DMA_CH5_BUF__buf__MAX 0xffffffff - -#define R_DMA_CH5_BUF__buf__MIN 0 - -#define R_DMA_CH5_BUF__buf__BITNR 0 - -#define R_DMA_CH5_BUF__buf__buf__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH5_CLR_INTR - * - type: WO - * - addr: 0xb00001e5 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH5_CLR_INTR__ADDR (REG_TYPECAST_BYTE 0xb00001e5) - -#ifndef REG_NO_SHADOW -#define R_DMA_CH5_CLR_INTR__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_DMA_CH5_CLR_INTR + 0)) -#define R_DMA_CH5_CLR_INTR__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_DMA_CH5_CLR_INTR + 0)) -#else /* REG_NO_SHADOW */ -#define R_DMA_CH5_CLR_INTR__SADDR (REG_STYPECAST_BYTE (®_shadow__hwregs)) -#define R_DMA_CH5_CLR_INTR__IADDR (REG_STYPECAST_BYTE (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_DMA_CH5_CLR_INTR__STYPECAST REG_STYPECAST_BYTE -#define R_DMA_CH5_CLR_INTR__SVAL REG_SVAL_ZERO -#define R_DMA_CH5_CLR_INTR__SVAL_I REG_SVAL_I_ZERO -#define R_DMA_CH5_CLR_INTR__TYPECAST REG_TYPECAST_BYTE -#define R_DMA_CH5_CLR_INTR__TYPE (REG_BYTE) -#define R_DMA_CH5_CLR_INTR__GET REG_GET_WO -#define R_DMA_CH5_CLR_INTR__IGET REG_IGET_WO -#define R_DMA_CH5_CLR_INTR__SET REG_SET_WO -#define R_DMA_CH5_CLR_INTR__ISET REG_ISET_WO -#define R_DMA_CH5_CLR_INTR__SET_VAL REG_SET_VAL_WO -#define R_DMA_CH5_CLR_INTR__EQL REG_EQL_WO -#define R_DMA_CH5_CLR_INTR__IEQL REG_IEQL_WO -#define R_DMA_CH5_CLR_INTR__RD REG_RD_WO -#define R_DMA_CH5_CLR_INTR__IRD REG_IRD_WO -#define R_DMA_CH5_CLR_INTR__WR REG_WR_WO -#define R_DMA_CH5_CLR_INTR__IWR REG_IWR_WO - -#define R_DMA_CH5_CLR_INTR__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_DMA_CH5_CLR_INTR__clr_eop__clr_eop__MASK 0x00000002U -#define R_DMA_CH5_CLR_INTR__clr_descr__clr_descr__MASK 0x00000001U - -#define R_DMA_CH5_CLR_INTR__clr_eop__MAX 0x1 -#define R_DMA_CH5_CLR_INTR__clr_descr__MAX 0x1 - -#define R_DMA_CH5_CLR_INTR__clr_eop__MIN 0 -#define R_DMA_CH5_CLR_INTR__clr_descr__MIN 0 - -#define R_DMA_CH5_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH5_CLR_INTR__clr_descr__BITNR 0 - -#define R_DMA_CH5_CLR_INTR__clr_eop__clr_eop__VAL REG_VAL_ENUM -#define R_DMA_CH5_CLR_INTR__clr_descr__clr_descr__VAL REG_VAL_ENUM - -#define R_DMA_CH5_CLR_INTR__clr_eop__clr_eop__do 1 -#define R_DMA_CH5_CLR_INTR__clr_eop__clr_eop__dont 0 -#define R_DMA_CH5_CLR_INTR__clr_descr__clr_descr__do 1 -#define R_DMA_CH5_CLR_INTR__clr_descr__clr_descr__dont 0 - -#endif - -/* - * R_DMA_CH5_CMD - * - type: RW - * - addr: 0xb00001e4 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH5_CMD__ADDR (REG_TYPECAST_BYTE 0xb00001e4) -#define R_DMA_CH5_CMD__SVAL REG_SVAL_SHADOW -#define R_DMA_CH5_CMD__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH5_CMD__TYPECAST REG_TYPECAST_BYTE -#define R_DMA_CH5_CMD__TYPE (REG_BYTE) -#define R_DMA_CH5_CMD__GET REG_GET_RW -#define R_DMA_CH5_CMD__IGET REG_IGET_RW -#define R_DMA_CH5_CMD__SET REG_SET_RW -#define R_DMA_CH5_CMD__ISET REG_ISET_RW -#define R_DMA_CH5_CMD__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH5_CMD__EQL REG_EQL_RW -#define R_DMA_CH5_CMD__IEQL REG_IEQL_RW -#define R_DMA_CH5_CMD__RD REG_RD_RW -#define R_DMA_CH5_CMD__IRD REG_IRD_RW -#define R_DMA_CH5_CMD__WR REG_WR_RW -#define R_DMA_CH5_CMD__IWR REG_IWR_RW - -#define R_DMA_CH5_CMD__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH5_CMD__READ(addr) \ - (*(addr)) - -#define R_DMA_CH5_CMD__cmd__cmd__MASK 0x00000007U - -#define R_DMA_CH5_CMD__cmd__MAX 0x7 - -#define R_DMA_CH5_CMD__cmd__MIN 0 - -#define R_DMA_CH5_CMD__cmd__BITNR 0 - -#define R_DMA_CH5_CMD__cmd__cmd__VAL REG_VAL_ENUM - -#define R_DMA_CH5_CMD__cmd__cmd__continue 3 -#define R_DMA_CH5_CMD__cmd__cmd__hold 0 -#define R_DMA_CH5_CMD__cmd__cmd__reset 4 -#define R_DMA_CH5_CMD__cmd__cmd__restart 3 -#define R_DMA_CH5_CMD__cmd__cmd__start 1 - -#endif - -/* - * R_DMA_CH5_DESCR - * - type: RW - * - addr: 0xb000015c - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH5_DESCR__ADDR (REG_TYPECAST_UDWORD 0xb000015c) -#define R_DMA_CH5_DESCR__SVAL REG_SVAL_SHADOW -#define R_DMA_CH5_DESCR__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH5_DESCR__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH5_DESCR__TYPE (REG_UDWORD) -#define R_DMA_CH5_DESCR__GET REG_GET_RW -#define R_DMA_CH5_DESCR__IGET REG_IGET_RW -#define R_DMA_CH5_DESCR__SET REG_SET_RW -#define R_DMA_CH5_DESCR__ISET REG_ISET_RW -#define R_DMA_CH5_DESCR__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH5_DESCR__EQL REG_EQL_RW -#define R_DMA_CH5_DESCR__IEQL REG_IEQL_RW -#define R_DMA_CH5_DESCR__RD REG_RD_RW -#define R_DMA_CH5_DESCR__IRD REG_IRD_RW -#define R_DMA_CH5_DESCR__WR REG_WR_RW -#define R_DMA_CH5_DESCR__IWR REG_IWR_RW - -#define R_DMA_CH5_DESCR__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH5_DESCR__READ(addr) \ - (*(addr)) - -#define R_DMA_CH5_DESCR__descr__descr__MASK 0xffffffffU - -#define R_DMA_CH5_DESCR__descr__MAX 0xffffffff - -#define R_DMA_CH5_DESCR__descr__MIN 0 - -#define R_DMA_CH5_DESCR__descr__BITNR 0 - -#define R_DMA_CH5_DESCR__descr__descr__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH5_FIRST - * - type: RW - * - addr: 0xb00001b4 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH5_FIRST__ADDR (REG_TYPECAST_UDWORD 0xb00001b4) -#define R_DMA_CH5_FIRST__SVAL REG_SVAL_SHADOW -#define R_DMA_CH5_FIRST__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH5_FIRST__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH5_FIRST__TYPE (REG_UDWORD) -#define R_DMA_CH5_FIRST__GET REG_GET_RW -#define R_DMA_CH5_FIRST__IGET REG_IGET_RW -#define R_DMA_CH5_FIRST__SET REG_SET_RW -#define R_DMA_CH5_FIRST__ISET REG_ISET_RW -#define R_DMA_CH5_FIRST__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH5_FIRST__EQL REG_EQL_RW -#define R_DMA_CH5_FIRST__IEQL REG_IEQL_RW -#define R_DMA_CH5_FIRST__RD REG_RD_RW -#define R_DMA_CH5_FIRST__IRD REG_IRD_RW -#define R_DMA_CH5_FIRST__WR REG_WR_RW -#define R_DMA_CH5_FIRST__IWR REG_IWR_RW - -#define R_DMA_CH5_FIRST__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH5_FIRST__READ(addr) \ - (*(addr)) - -#define R_DMA_CH5_FIRST__first__first__MASK 0xffffffffU - -#define R_DMA_CH5_FIRST__first__MAX 0xffffffff - -#define R_DMA_CH5_FIRST__first__MIN 0 - -#define R_DMA_CH5_FIRST__first__BITNR 0 - -#define R_DMA_CH5_FIRST__first__first__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH5_HWSW - * - type: RW - * - addr: 0xb0000150 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH5_HWSW__ADDR (REG_TYPECAST_UDWORD 0xb0000150) -#define R_DMA_CH5_HWSW__SVAL REG_SVAL_SHADOW -#define R_DMA_CH5_HWSW__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH5_HWSW__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH5_HWSW__TYPE (REG_UDWORD) -#define R_DMA_CH5_HWSW__GET REG_GET_RW -#define R_DMA_CH5_HWSW__IGET REG_IGET_RW -#define R_DMA_CH5_HWSW__SET REG_SET_RW -#define R_DMA_CH5_HWSW__ISET REG_ISET_RW -#define R_DMA_CH5_HWSW__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH5_HWSW__EQL REG_EQL_RW -#define R_DMA_CH5_HWSW__IEQL REG_IEQL_RW -#define R_DMA_CH5_HWSW__RD REG_RD_RW -#define R_DMA_CH5_HWSW__IRD REG_IRD_RW -#define R_DMA_CH5_HWSW__WR REG_WR_RW -#define R_DMA_CH5_HWSW__IWR REG_IWR_RW - -#define R_DMA_CH5_HWSW__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH5_HWSW__READ(addr) \ - (*(addr)) - -#define R_DMA_CH5_HWSW__hw__hw__MASK 0xffff0000U -#define R_DMA_CH5_HWSW__sw__sw__MASK 0x0000ffffU - -#define R_DMA_CH5_HWSW__hw__MAX 0xffff -#define R_DMA_CH5_HWSW__sw__MAX 0xffff - -#define R_DMA_CH5_HWSW__hw__MIN 0 -#define R_DMA_CH5_HWSW__sw__MIN 0 - -#define R_DMA_CH5_HWSW__hw__BITNR 16 -#define R_DMA_CH5_HWSW__sw__BITNR 0 - -#define R_DMA_CH5_HWSW__hw__hw__VAL REG_VAL_VAL -#define R_DMA_CH5_HWSW__sw__sw__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH5_NEXT - * - type: RW - * - addr: 0xb0000154 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH5_NEXT__ADDR (REG_TYPECAST_UDWORD 0xb0000154) -#define R_DMA_CH5_NEXT__SVAL REG_SVAL_SHADOW -#define R_DMA_CH5_NEXT__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH5_NEXT__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH5_NEXT__TYPE (REG_UDWORD) -#define R_DMA_CH5_NEXT__GET REG_GET_RW -#define R_DMA_CH5_NEXT__IGET REG_IGET_RW -#define R_DMA_CH5_NEXT__SET REG_SET_RW -#define R_DMA_CH5_NEXT__ISET REG_ISET_RW -#define R_DMA_CH5_NEXT__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH5_NEXT__EQL REG_EQL_RW -#define R_DMA_CH5_NEXT__IEQL REG_IEQL_RW -#define R_DMA_CH5_NEXT__RD REG_RD_RW -#define R_DMA_CH5_NEXT__IRD REG_IRD_RW -#define R_DMA_CH5_NEXT__WR REG_WR_RW -#define R_DMA_CH5_NEXT__IWR REG_IWR_RW - -#define R_DMA_CH5_NEXT__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH5_NEXT__READ(addr) \ - (*(addr)) - -#define R_DMA_CH5_NEXT__next__next__MASK 0xffffffffU - -#define R_DMA_CH5_NEXT__next__MAX 0xffffffff - -#define R_DMA_CH5_NEXT__next__MIN 0 - -#define R_DMA_CH5_NEXT__next__BITNR 0 - -#define R_DMA_CH5_NEXT__next__next__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH5_STATUS - * - type: RO - * - addr: 0xb00001e6 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH5_STATUS__ADDR (REG_TYPECAST_BYTE 0xb00001e6) -#define R_DMA_CH5_STATUS__SVAL REG_SVAL_SHADOW -#define R_DMA_CH5_STATUS__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH5_STATUS__TYPECAST REG_TYPECAST_BYTE -#define R_DMA_CH5_STATUS__TYPE (REG_BYTE) -#define R_DMA_CH5_STATUS__GET REG_GET_RO -#define R_DMA_CH5_STATUS__IGET REG_IGET_RO -#define R_DMA_CH5_STATUS__SET REG_SET_RO -#define R_DMA_CH5_STATUS__ISET REG_ISET_RO -#define R_DMA_CH5_STATUS__SET_VAL REG_SET_VAL_RO -#define R_DMA_CH5_STATUS__EQL REG_EQL_RO -#define R_DMA_CH5_STATUS__IEQL REG_IEQL_RO -#define R_DMA_CH5_STATUS__RD REG_RD_RO -#define R_DMA_CH5_STATUS__IRD REG_IRD_RO -#define R_DMA_CH5_STATUS__WR REG_WR_RO -#define R_DMA_CH5_STATUS__IWR REG_IWR_RO - -#define R_DMA_CH5_STATUS__READ(addr) \ - (*(addr)) - -#define R_DMA_CH5_STATUS__avail__avail__MASK 0x0000007fU - -#define R_DMA_CH5_STATUS__avail__MAX 0x7f - -#define R_DMA_CH5_STATUS__avail__MIN 0 - -#define R_DMA_CH5_STATUS__avail__BITNR 0 - -#define R_DMA_CH5_STATUS__avail__avail__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH6_BUF - * - type: RW - * - addr: 0xb0000168 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH6_BUF__ADDR (REG_TYPECAST_UDWORD 0xb0000168) -#define R_DMA_CH6_BUF__SVAL REG_SVAL_SHADOW -#define R_DMA_CH6_BUF__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH6_BUF__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH6_BUF__TYPE (REG_UDWORD) -#define R_DMA_CH6_BUF__GET REG_GET_RW -#define R_DMA_CH6_BUF__IGET REG_IGET_RW -#define R_DMA_CH6_BUF__SET REG_SET_RW -#define R_DMA_CH6_BUF__ISET REG_ISET_RW -#define R_DMA_CH6_BUF__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH6_BUF__EQL REG_EQL_RW -#define R_DMA_CH6_BUF__IEQL REG_IEQL_RW -#define R_DMA_CH6_BUF__RD REG_RD_RW -#define R_DMA_CH6_BUF__IRD REG_IRD_RW -#define R_DMA_CH6_BUF__WR REG_WR_RW -#define R_DMA_CH6_BUF__IWR REG_IWR_RW - -#define R_DMA_CH6_BUF__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH6_BUF__READ(addr) \ - (*(addr)) - -#define R_DMA_CH6_BUF__buf__buf__MASK 0xffffffffU - -#define R_DMA_CH6_BUF__buf__MAX 0xffffffff - -#define R_DMA_CH6_BUF__buf__MIN 0 - -#define R_DMA_CH6_BUF__buf__BITNR 0 - -#define R_DMA_CH6_BUF__buf__buf__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH6_CLR_INTR - * - type: WO - * - addr: 0xb00001e9 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH6_CLR_INTR__ADDR (REG_TYPECAST_BYTE 0xb00001e9) - -#ifndef REG_NO_SHADOW -#define R_DMA_CH6_CLR_INTR__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_DMA_CH6_CLR_INTR + 0)) -#define R_DMA_CH6_CLR_INTR__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_DMA_CH6_CLR_INTR + 0)) -#else /* REG_NO_SHADOW */ -#define R_DMA_CH6_CLR_INTR__SADDR (REG_STYPECAST_BYTE (®_shadow__hwregs)) -#define R_DMA_CH6_CLR_INTR__IADDR (REG_STYPECAST_BYTE (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_DMA_CH6_CLR_INTR__STYPECAST REG_STYPECAST_BYTE -#define R_DMA_CH6_CLR_INTR__SVAL REG_SVAL_ZERO -#define R_DMA_CH6_CLR_INTR__SVAL_I REG_SVAL_I_ZERO -#define R_DMA_CH6_CLR_INTR__TYPECAST REG_TYPECAST_BYTE -#define R_DMA_CH6_CLR_INTR__TYPE (REG_BYTE) -#define R_DMA_CH6_CLR_INTR__GET REG_GET_WO -#define R_DMA_CH6_CLR_INTR__IGET REG_IGET_WO -#define R_DMA_CH6_CLR_INTR__SET REG_SET_WO -#define R_DMA_CH6_CLR_INTR__ISET REG_ISET_WO -#define R_DMA_CH6_CLR_INTR__SET_VAL REG_SET_VAL_WO -#define R_DMA_CH6_CLR_INTR__EQL REG_EQL_WO -#define R_DMA_CH6_CLR_INTR__IEQL REG_IEQL_WO -#define R_DMA_CH6_CLR_INTR__RD REG_RD_WO -#define R_DMA_CH6_CLR_INTR__IRD REG_IRD_WO -#define R_DMA_CH6_CLR_INTR__WR REG_WR_WO -#define R_DMA_CH6_CLR_INTR__IWR REG_IWR_WO - -#define R_DMA_CH6_CLR_INTR__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_DMA_CH6_CLR_INTR__clr_eop__clr_eop__MASK 0x00000002U -#define R_DMA_CH6_CLR_INTR__clr_descr__clr_descr__MASK 0x00000001U - -#define R_DMA_CH6_CLR_INTR__clr_eop__MAX 0x1 -#define R_DMA_CH6_CLR_INTR__clr_descr__MAX 0x1 - -#define R_DMA_CH6_CLR_INTR__clr_eop__MIN 0 -#define R_DMA_CH6_CLR_INTR__clr_descr__MIN 0 - -#define R_DMA_CH6_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH6_CLR_INTR__clr_descr__BITNR 0 - -#define R_DMA_CH6_CLR_INTR__clr_eop__clr_eop__VAL REG_VAL_ENUM -#define R_DMA_CH6_CLR_INTR__clr_descr__clr_descr__VAL REG_VAL_ENUM - -#define R_DMA_CH6_CLR_INTR__clr_eop__clr_eop__do 1 -#define R_DMA_CH6_CLR_INTR__clr_eop__clr_eop__dont 0 -#define R_DMA_CH6_CLR_INTR__clr_descr__clr_descr__do 1 -#define R_DMA_CH6_CLR_INTR__clr_descr__clr_descr__dont 0 - -#endif - -/* - * R_DMA_CH6_CMD - * - type: RW - * - addr: 0xb00001e8 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH6_CMD__ADDR (REG_TYPECAST_BYTE 0xb00001e8) -#define R_DMA_CH6_CMD__SVAL REG_SVAL_SHADOW -#define R_DMA_CH6_CMD__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH6_CMD__TYPECAST REG_TYPECAST_BYTE -#define R_DMA_CH6_CMD__TYPE (REG_BYTE) -#define R_DMA_CH6_CMD__GET REG_GET_RW -#define R_DMA_CH6_CMD__IGET REG_IGET_RW -#define R_DMA_CH6_CMD__SET REG_SET_RW -#define R_DMA_CH6_CMD__ISET REG_ISET_RW -#define R_DMA_CH6_CMD__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH6_CMD__EQL REG_EQL_RW -#define R_DMA_CH6_CMD__IEQL REG_IEQL_RW -#define R_DMA_CH6_CMD__RD REG_RD_RW -#define R_DMA_CH6_CMD__IRD REG_IRD_RW -#define R_DMA_CH6_CMD__WR REG_WR_RW -#define R_DMA_CH6_CMD__IWR REG_IWR_RW - -#define R_DMA_CH6_CMD__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH6_CMD__READ(addr) \ - (*(addr)) - -#define R_DMA_CH6_CMD__cmd__cmd__MASK 0x00000007U - -#define R_DMA_CH6_CMD__cmd__MAX 0x7 - -#define R_DMA_CH6_CMD__cmd__MIN 0 - -#define R_DMA_CH6_CMD__cmd__BITNR 0 - -#define R_DMA_CH6_CMD__cmd__cmd__VAL REG_VAL_ENUM - -#define R_DMA_CH6_CMD__cmd__cmd__continue 3 -#define R_DMA_CH6_CMD__cmd__cmd__hold 0 -#define R_DMA_CH6_CMD__cmd__cmd__reset 4 -#define R_DMA_CH6_CMD__cmd__cmd__restart 3 -#define R_DMA_CH6_CMD__cmd__cmd__start 1 - -#endif - -/* - * R_DMA_CH6_DESCR - * - type: RW - * - addr: 0xb000016c - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH6_DESCR__ADDR (REG_TYPECAST_UDWORD 0xb000016c) -#define R_DMA_CH6_DESCR__SVAL REG_SVAL_SHADOW -#define R_DMA_CH6_DESCR__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH6_DESCR__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH6_DESCR__TYPE (REG_UDWORD) -#define R_DMA_CH6_DESCR__GET REG_GET_RW -#define R_DMA_CH6_DESCR__IGET REG_IGET_RW -#define R_DMA_CH6_DESCR__SET REG_SET_RW -#define R_DMA_CH6_DESCR__ISET REG_ISET_RW -#define R_DMA_CH6_DESCR__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH6_DESCR__EQL REG_EQL_RW -#define R_DMA_CH6_DESCR__IEQL REG_IEQL_RW -#define R_DMA_CH6_DESCR__RD REG_RD_RW -#define R_DMA_CH6_DESCR__IRD REG_IRD_RW -#define R_DMA_CH6_DESCR__WR REG_WR_RW -#define R_DMA_CH6_DESCR__IWR REG_IWR_RW - -#define R_DMA_CH6_DESCR__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH6_DESCR__READ(addr) \ - (*(addr)) - -#define R_DMA_CH6_DESCR__descr__descr__MASK 0xffffffffU - -#define R_DMA_CH6_DESCR__descr__MAX 0xffffffff - -#define R_DMA_CH6_DESCR__descr__MIN 0 - -#define R_DMA_CH6_DESCR__descr__BITNR 0 - -#define R_DMA_CH6_DESCR__descr__descr__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH6_FIRST - * - type: RW - * - addr: 0xb00001b8 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH6_FIRST__ADDR (REG_TYPECAST_UDWORD 0xb00001b8) -#define R_DMA_CH6_FIRST__SVAL REG_SVAL_SHADOW -#define R_DMA_CH6_FIRST__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH6_FIRST__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH6_FIRST__TYPE (REG_UDWORD) -#define R_DMA_CH6_FIRST__GET REG_GET_RW -#define R_DMA_CH6_FIRST__IGET REG_IGET_RW -#define R_DMA_CH6_FIRST__SET REG_SET_RW -#define R_DMA_CH6_FIRST__ISET REG_ISET_RW -#define R_DMA_CH6_FIRST__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH6_FIRST__EQL REG_EQL_RW -#define R_DMA_CH6_FIRST__IEQL REG_IEQL_RW -#define R_DMA_CH6_FIRST__RD REG_RD_RW -#define R_DMA_CH6_FIRST__IRD REG_IRD_RW -#define R_DMA_CH6_FIRST__WR REG_WR_RW -#define R_DMA_CH6_FIRST__IWR REG_IWR_RW - -#define R_DMA_CH6_FIRST__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH6_FIRST__READ(addr) \ - (*(addr)) - -#define R_DMA_CH6_FIRST__first__first__MASK 0xffffffffU - -#define R_DMA_CH6_FIRST__first__MAX 0xffffffff - -#define R_DMA_CH6_FIRST__first__MIN 0 - -#define R_DMA_CH6_FIRST__first__BITNR 0 - -#define R_DMA_CH6_FIRST__first__first__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH6_HWSW - * - type: RW - * - addr: 0xb0000160 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH6_HWSW__ADDR (REG_TYPECAST_UDWORD 0xb0000160) -#define R_DMA_CH6_HWSW__SVAL REG_SVAL_SHADOW -#define R_DMA_CH6_HWSW__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH6_HWSW__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH6_HWSW__TYPE (REG_UDWORD) -#define R_DMA_CH6_HWSW__GET REG_GET_RW -#define R_DMA_CH6_HWSW__IGET REG_IGET_RW -#define R_DMA_CH6_HWSW__SET REG_SET_RW -#define R_DMA_CH6_HWSW__ISET REG_ISET_RW -#define R_DMA_CH6_HWSW__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH6_HWSW__EQL REG_EQL_RW -#define R_DMA_CH6_HWSW__IEQL REG_IEQL_RW -#define R_DMA_CH6_HWSW__RD REG_RD_RW -#define R_DMA_CH6_HWSW__IRD REG_IRD_RW -#define R_DMA_CH6_HWSW__WR REG_WR_RW -#define R_DMA_CH6_HWSW__IWR REG_IWR_RW - -#define R_DMA_CH6_HWSW__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH6_HWSW__READ(addr) \ - (*(addr)) - -#define R_DMA_CH6_HWSW__hw__hw__MASK 0xffff0000U -#define R_DMA_CH6_HWSW__sw__sw__MASK 0x0000ffffU - -#define R_DMA_CH6_HWSW__hw__MAX 0xffff -#define R_DMA_CH6_HWSW__sw__MAX 0xffff - -#define R_DMA_CH6_HWSW__hw__MIN 0 -#define R_DMA_CH6_HWSW__sw__MIN 0 - -#define R_DMA_CH6_HWSW__hw__BITNR 16 -#define R_DMA_CH6_HWSW__sw__BITNR 0 - -#define R_DMA_CH6_HWSW__hw__hw__VAL REG_VAL_VAL -#define R_DMA_CH6_HWSW__sw__sw__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH6_NEXT - * - type: RW - * - addr: 0xb0000164 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH6_NEXT__ADDR (REG_TYPECAST_UDWORD 0xb0000164) -#define R_DMA_CH6_NEXT__SVAL REG_SVAL_SHADOW -#define R_DMA_CH6_NEXT__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH6_NEXT__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH6_NEXT__TYPE (REG_UDWORD) -#define R_DMA_CH6_NEXT__GET REG_GET_RW -#define R_DMA_CH6_NEXT__IGET REG_IGET_RW -#define R_DMA_CH6_NEXT__SET REG_SET_RW -#define R_DMA_CH6_NEXT__ISET REG_ISET_RW -#define R_DMA_CH6_NEXT__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH6_NEXT__EQL REG_EQL_RW -#define R_DMA_CH6_NEXT__IEQL REG_IEQL_RW -#define R_DMA_CH6_NEXT__RD REG_RD_RW -#define R_DMA_CH6_NEXT__IRD REG_IRD_RW -#define R_DMA_CH6_NEXT__WR REG_WR_RW -#define R_DMA_CH6_NEXT__IWR REG_IWR_RW - -#define R_DMA_CH6_NEXT__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH6_NEXT__READ(addr) \ - (*(addr)) - -#define R_DMA_CH6_NEXT__next__next__MASK 0xffffffffU - -#define R_DMA_CH6_NEXT__next__MAX 0xffffffff - -#define R_DMA_CH6_NEXT__next__MIN 0 - -#define R_DMA_CH6_NEXT__next__BITNR 0 - -#define R_DMA_CH6_NEXT__next__next__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH6_STATUS - * - type: RO - * - addr: 0xb00001ea - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH6_STATUS__ADDR (REG_TYPECAST_BYTE 0xb00001ea) -#define R_DMA_CH6_STATUS__SVAL REG_SVAL_SHADOW -#define R_DMA_CH6_STATUS__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH6_STATUS__TYPECAST REG_TYPECAST_BYTE -#define R_DMA_CH6_STATUS__TYPE (REG_BYTE) -#define R_DMA_CH6_STATUS__GET REG_GET_RO -#define R_DMA_CH6_STATUS__IGET REG_IGET_RO -#define R_DMA_CH6_STATUS__SET REG_SET_RO -#define R_DMA_CH6_STATUS__ISET REG_ISET_RO -#define R_DMA_CH6_STATUS__SET_VAL REG_SET_VAL_RO -#define R_DMA_CH6_STATUS__EQL REG_EQL_RO -#define R_DMA_CH6_STATUS__IEQL REG_IEQL_RO -#define R_DMA_CH6_STATUS__RD REG_RD_RO -#define R_DMA_CH6_STATUS__IRD REG_IRD_RO -#define R_DMA_CH6_STATUS__WR REG_WR_RO -#define R_DMA_CH6_STATUS__IWR REG_IWR_RO - -#define R_DMA_CH6_STATUS__READ(addr) \ - (*(addr)) - -#define R_DMA_CH6_STATUS__avail__avail__MASK 0x0000007fU - -#define R_DMA_CH6_STATUS__avail__MAX 0x7f - -#define R_DMA_CH6_STATUS__avail__MIN 0 - -#define R_DMA_CH6_STATUS__avail__BITNR 0 - -#define R_DMA_CH6_STATUS__avail__avail__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH7_BUF - * - type: RW - * - addr: 0xb0000178 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH7_BUF__ADDR (REG_TYPECAST_UDWORD 0xb0000178) -#define R_DMA_CH7_BUF__SVAL REG_SVAL_SHADOW -#define R_DMA_CH7_BUF__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH7_BUF__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH7_BUF__TYPE (REG_UDWORD) -#define R_DMA_CH7_BUF__GET REG_GET_RW -#define R_DMA_CH7_BUF__IGET REG_IGET_RW -#define R_DMA_CH7_BUF__SET REG_SET_RW -#define R_DMA_CH7_BUF__ISET REG_ISET_RW -#define R_DMA_CH7_BUF__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH7_BUF__EQL REG_EQL_RW -#define R_DMA_CH7_BUF__IEQL REG_IEQL_RW -#define R_DMA_CH7_BUF__RD REG_RD_RW -#define R_DMA_CH7_BUF__IRD REG_IRD_RW -#define R_DMA_CH7_BUF__WR REG_WR_RW -#define R_DMA_CH7_BUF__IWR REG_IWR_RW - -#define R_DMA_CH7_BUF__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH7_BUF__READ(addr) \ - (*(addr)) - -#define R_DMA_CH7_BUF__buf__buf__MASK 0xffffffffU - -#define R_DMA_CH7_BUF__buf__MAX 0xffffffff - -#define R_DMA_CH7_BUF__buf__MIN 0 - -#define R_DMA_CH7_BUF__buf__BITNR 0 - -#define R_DMA_CH7_BUF__buf__buf__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH7_CLR_INTR - * - type: WO - * - addr: 0xb00001ed - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH7_CLR_INTR__ADDR (REG_TYPECAST_BYTE 0xb00001ed) - -#ifndef REG_NO_SHADOW -#define R_DMA_CH7_CLR_INTR__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_DMA_CH7_CLR_INTR + 0)) -#define R_DMA_CH7_CLR_INTR__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_DMA_CH7_CLR_INTR + 0)) -#else /* REG_NO_SHADOW */ -#define R_DMA_CH7_CLR_INTR__SADDR (REG_STYPECAST_BYTE (®_shadow__hwregs)) -#define R_DMA_CH7_CLR_INTR__IADDR (REG_STYPECAST_BYTE (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_DMA_CH7_CLR_INTR__STYPECAST REG_STYPECAST_BYTE -#define R_DMA_CH7_CLR_INTR__SVAL REG_SVAL_ZERO -#define R_DMA_CH7_CLR_INTR__SVAL_I REG_SVAL_I_ZERO -#define R_DMA_CH7_CLR_INTR__TYPECAST REG_TYPECAST_BYTE -#define R_DMA_CH7_CLR_INTR__TYPE (REG_BYTE) -#define R_DMA_CH7_CLR_INTR__GET REG_GET_WO -#define R_DMA_CH7_CLR_INTR__IGET REG_IGET_WO -#define R_DMA_CH7_CLR_INTR__SET REG_SET_WO -#define R_DMA_CH7_CLR_INTR__ISET REG_ISET_WO -#define R_DMA_CH7_CLR_INTR__SET_VAL REG_SET_VAL_WO -#define R_DMA_CH7_CLR_INTR__EQL REG_EQL_WO -#define R_DMA_CH7_CLR_INTR__IEQL REG_IEQL_WO -#define R_DMA_CH7_CLR_INTR__RD REG_RD_WO -#define R_DMA_CH7_CLR_INTR__IRD REG_IRD_WO -#define R_DMA_CH7_CLR_INTR__WR REG_WR_WO -#define R_DMA_CH7_CLR_INTR__IWR REG_IWR_WO - -#define R_DMA_CH7_CLR_INTR__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_DMA_CH7_CLR_INTR__clr_eop__clr_eop__MASK 0x00000002U -#define R_DMA_CH7_CLR_INTR__clr_descr__clr_descr__MASK 0x00000001U - -#define R_DMA_CH7_CLR_INTR__clr_eop__MAX 0x1 -#define R_DMA_CH7_CLR_INTR__clr_descr__MAX 0x1 - -#define R_DMA_CH7_CLR_INTR__clr_eop__MIN 0 -#define R_DMA_CH7_CLR_INTR__clr_descr__MIN 0 - -#define R_DMA_CH7_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH7_CLR_INTR__clr_descr__BITNR 0 - -#define R_DMA_CH7_CLR_INTR__clr_eop__clr_eop__VAL REG_VAL_ENUM -#define R_DMA_CH7_CLR_INTR__clr_descr__clr_descr__VAL REG_VAL_ENUM - -#define R_DMA_CH7_CLR_INTR__clr_eop__clr_eop__do 1 -#define R_DMA_CH7_CLR_INTR__clr_eop__clr_eop__dont 0 -#define R_DMA_CH7_CLR_INTR__clr_descr__clr_descr__do 1 -#define R_DMA_CH7_CLR_INTR__clr_descr__clr_descr__dont 0 - -#endif - -/* - * R_DMA_CH7_CMD - * - type: RW - * - addr: 0xb00001ec - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH7_CMD__ADDR (REG_TYPECAST_BYTE 0xb00001ec) -#define R_DMA_CH7_CMD__SVAL REG_SVAL_SHADOW -#define R_DMA_CH7_CMD__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH7_CMD__TYPECAST REG_TYPECAST_BYTE -#define R_DMA_CH7_CMD__TYPE (REG_BYTE) -#define R_DMA_CH7_CMD__GET REG_GET_RW -#define R_DMA_CH7_CMD__IGET REG_IGET_RW -#define R_DMA_CH7_CMD__SET REG_SET_RW -#define R_DMA_CH7_CMD__ISET REG_ISET_RW -#define R_DMA_CH7_CMD__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH7_CMD__EQL REG_EQL_RW -#define R_DMA_CH7_CMD__IEQL REG_IEQL_RW -#define R_DMA_CH7_CMD__RD REG_RD_RW -#define R_DMA_CH7_CMD__IRD REG_IRD_RW -#define R_DMA_CH7_CMD__WR REG_WR_RW -#define R_DMA_CH7_CMD__IWR REG_IWR_RW - -#define R_DMA_CH7_CMD__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH7_CMD__READ(addr) \ - (*(addr)) - -#define R_DMA_CH7_CMD__cmd__cmd__MASK 0x00000007U - -#define R_DMA_CH7_CMD__cmd__MAX 0x7 - -#define R_DMA_CH7_CMD__cmd__MIN 0 - -#define R_DMA_CH7_CMD__cmd__BITNR 0 - -#define R_DMA_CH7_CMD__cmd__cmd__VAL REG_VAL_ENUM - -#define R_DMA_CH7_CMD__cmd__cmd__continue 3 -#define R_DMA_CH7_CMD__cmd__cmd__hold 0 -#define R_DMA_CH7_CMD__cmd__cmd__reset 4 -#define R_DMA_CH7_CMD__cmd__cmd__restart 3 -#define R_DMA_CH7_CMD__cmd__cmd__start 1 - -#endif - -/* - * R_DMA_CH7_DESCR - * - type: RW - * - addr: 0xb000017c - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH7_DESCR__ADDR (REG_TYPECAST_UDWORD 0xb000017c) -#define R_DMA_CH7_DESCR__SVAL REG_SVAL_SHADOW -#define R_DMA_CH7_DESCR__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH7_DESCR__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH7_DESCR__TYPE (REG_UDWORD) -#define R_DMA_CH7_DESCR__GET REG_GET_RW -#define R_DMA_CH7_DESCR__IGET REG_IGET_RW -#define R_DMA_CH7_DESCR__SET REG_SET_RW -#define R_DMA_CH7_DESCR__ISET REG_ISET_RW -#define R_DMA_CH7_DESCR__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH7_DESCR__EQL REG_EQL_RW -#define R_DMA_CH7_DESCR__IEQL REG_IEQL_RW -#define R_DMA_CH7_DESCR__RD REG_RD_RW -#define R_DMA_CH7_DESCR__IRD REG_IRD_RW -#define R_DMA_CH7_DESCR__WR REG_WR_RW -#define R_DMA_CH7_DESCR__IWR REG_IWR_RW - -#define R_DMA_CH7_DESCR__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH7_DESCR__READ(addr) \ - (*(addr)) - -#define R_DMA_CH7_DESCR__descr__descr__MASK 0xffffffffU - -#define R_DMA_CH7_DESCR__descr__MAX 0xffffffff - -#define R_DMA_CH7_DESCR__descr__MIN 0 - -#define R_DMA_CH7_DESCR__descr__BITNR 0 - -#define R_DMA_CH7_DESCR__descr__descr__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH7_FIRST - * - type: RW - * - addr: 0xb00001bc - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH7_FIRST__ADDR (REG_TYPECAST_UDWORD 0xb00001bc) -#define R_DMA_CH7_FIRST__SVAL REG_SVAL_SHADOW -#define R_DMA_CH7_FIRST__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH7_FIRST__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH7_FIRST__TYPE (REG_UDWORD) -#define R_DMA_CH7_FIRST__GET REG_GET_RW -#define R_DMA_CH7_FIRST__IGET REG_IGET_RW -#define R_DMA_CH7_FIRST__SET REG_SET_RW -#define R_DMA_CH7_FIRST__ISET REG_ISET_RW -#define R_DMA_CH7_FIRST__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH7_FIRST__EQL REG_EQL_RW -#define R_DMA_CH7_FIRST__IEQL REG_IEQL_RW -#define R_DMA_CH7_FIRST__RD REG_RD_RW -#define R_DMA_CH7_FIRST__IRD REG_IRD_RW -#define R_DMA_CH7_FIRST__WR REG_WR_RW -#define R_DMA_CH7_FIRST__IWR REG_IWR_RW - -#define R_DMA_CH7_FIRST__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH7_FIRST__READ(addr) \ - (*(addr)) - -#define R_DMA_CH7_FIRST__first__first__MASK 0xffffffffU - -#define R_DMA_CH7_FIRST__first__MAX 0xffffffff - -#define R_DMA_CH7_FIRST__first__MIN 0 - -#define R_DMA_CH7_FIRST__first__BITNR 0 - -#define R_DMA_CH7_FIRST__first__first__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH7_HWSW - * - type: RW - * - addr: 0xb0000170 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH7_HWSW__ADDR (REG_TYPECAST_UDWORD 0xb0000170) -#define R_DMA_CH7_HWSW__SVAL REG_SVAL_SHADOW -#define R_DMA_CH7_HWSW__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH7_HWSW__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH7_HWSW__TYPE (REG_UDWORD) -#define R_DMA_CH7_HWSW__GET REG_GET_RW -#define R_DMA_CH7_HWSW__IGET REG_IGET_RW -#define R_DMA_CH7_HWSW__SET REG_SET_RW -#define R_DMA_CH7_HWSW__ISET REG_ISET_RW -#define R_DMA_CH7_HWSW__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH7_HWSW__EQL REG_EQL_RW -#define R_DMA_CH7_HWSW__IEQL REG_IEQL_RW -#define R_DMA_CH7_HWSW__RD REG_RD_RW -#define R_DMA_CH7_HWSW__IRD REG_IRD_RW -#define R_DMA_CH7_HWSW__WR REG_WR_RW -#define R_DMA_CH7_HWSW__IWR REG_IWR_RW - -#define R_DMA_CH7_HWSW__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH7_HWSW__READ(addr) \ - (*(addr)) - -#define R_DMA_CH7_HWSW__hw__hw__MASK 0xffff0000U -#define R_DMA_CH7_HWSW__sw__sw__MASK 0x0000ffffU - -#define R_DMA_CH7_HWSW__hw__MAX 0xffff -#define R_DMA_CH7_HWSW__sw__MAX 0xffff - -#define R_DMA_CH7_HWSW__hw__MIN 0 -#define R_DMA_CH7_HWSW__sw__MIN 0 - -#define R_DMA_CH7_HWSW__hw__BITNR 16 -#define R_DMA_CH7_HWSW__sw__BITNR 0 - -#define R_DMA_CH7_HWSW__hw__hw__VAL REG_VAL_VAL -#define R_DMA_CH7_HWSW__sw__sw__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH7_NEXT - * - type: RW - * - addr: 0xb0000174 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH7_NEXT__ADDR (REG_TYPECAST_UDWORD 0xb0000174) -#define R_DMA_CH7_NEXT__SVAL REG_SVAL_SHADOW -#define R_DMA_CH7_NEXT__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH7_NEXT__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH7_NEXT__TYPE (REG_UDWORD) -#define R_DMA_CH7_NEXT__GET REG_GET_RW -#define R_DMA_CH7_NEXT__IGET REG_IGET_RW -#define R_DMA_CH7_NEXT__SET REG_SET_RW -#define R_DMA_CH7_NEXT__ISET REG_ISET_RW -#define R_DMA_CH7_NEXT__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH7_NEXT__EQL REG_EQL_RW -#define R_DMA_CH7_NEXT__IEQL REG_IEQL_RW -#define R_DMA_CH7_NEXT__RD REG_RD_RW -#define R_DMA_CH7_NEXT__IRD REG_IRD_RW -#define R_DMA_CH7_NEXT__WR REG_WR_RW -#define R_DMA_CH7_NEXT__IWR REG_IWR_RW - -#define R_DMA_CH7_NEXT__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH7_NEXT__READ(addr) \ - (*(addr)) - -#define R_DMA_CH7_NEXT__next__next__MASK 0xffffffffU - -#define R_DMA_CH7_NEXT__next__MAX 0xffffffff - -#define R_DMA_CH7_NEXT__next__MIN 0 - -#define R_DMA_CH7_NEXT__next__BITNR 0 - -#define R_DMA_CH7_NEXT__next__next__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH7_STATUS - * - type: RO - * - addr: 0xb00001ee - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH7_STATUS__ADDR (REG_TYPECAST_BYTE 0xb00001ee) -#define R_DMA_CH7_STATUS__SVAL REG_SVAL_SHADOW -#define R_DMA_CH7_STATUS__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH7_STATUS__TYPECAST REG_TYPECAST_BYTE -#define R_DMA_CH7_STATUS__TYPE (REG_BYTE) -#define R_DMA_CH7_STATUS__GET REG_GET_RO -#define R_DMA_CH7_STATUS__IGET REG_IGET_RO -#define R_DMA_CH7_STATUS__SET REG_SET_RO -#define R_DMA_CH7_STATUS__ISET REG_ISET_RO -#define R_DMA_CH7_STATUS__SET_VAL REG_SET_VAL_RO -#define R_DMA_CH7_STATUS__EQL REG_EQL_RO -#define R_DMA_CH7_STATUS__IEQL REG_IEQL_RO -#define R_DMA_CH7_STATUS__RD REG_RD_RO -#define R_DMA_CH7_STATUS__IRD REG_IRD_RO -#define R_DMA_CH7_STATUS__WR REG_WR_RO -#define R_DMA_CH7_STATUS__IWR REG_IWR_RO - -#define R_DMA_CH7_STATUS__READ(addr) \ - (*(addr)) - -#define R_DMA_CH7_STATUS__avail__avail__MASK 0x0000007fU - -#define R_DMA_CH7_STATUS__avail__MAX 0x7f - -#define R_DMA_CH7_STATUS__avail__MIN 0 - -#define R_DMA_CH7_STATUS__avail__BITNR 0 - -#define R_DMA_CH7_STATUS__avail__avail__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH8_BUF - * - type: RW - * - addr: 0xb0000188 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH8_BUF__ADDR (REG_TYPECAST_UDWORD 0xb0000188) -#define R_DMA_CH8_BUF__SVAL REG_SVAL_SHADOW -#define R_DMA_CH8_BUF__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH8_BUF__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH8_BUF__TYPE (REG_UDWORD) -#define R_DMA_CH8_BUF__GET REG_GET_RW -#define R_DMA_CH8_BUF__IGET REG_IGET_RW -#define R_DMA_CH8_BUF__SET REG_SET_RW -#define R_DMA_CH8_BUF__ISET REG_ISET_RW -#define R_DMA_CH8_BUF__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH8_BUF__EQL REG_EQL_RW -#define R_DMA_CH8_BUF__IEQL REG_IEQL_RW -#define R_DMA_CH8_BUF__RD REG_RD_RW -#define R_DMA_CH8_BUF__IRD REG_IRD_RW -#define R_DMA_CH8_BUF__WR REG_WR_RW -#define R_DMA_CH8_BUF__IWR REG_IWR_RW - -#define R_DMA_CH8_BUF__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH8_BUF__READ(addr) \ - (*(addr)) - -#define R_DMA_CH8_BUF__buf__buf__MASK 0xffffffffU - -#define R_DMA_CH8_BUF__buf__MAX 0xffffffff - -#define R_DMA_CH8_BUF__buf__MIN 0 - -#define R_DMA_CH8_BUF__buf__BITNR 0 - -#define R_DMA_CH8_BUF__buf__buf__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH8_CLR_INTR - * - type: WO - * - addr: 0xb00001f1 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH8_CLR_INTR__ADDR (REG_TYPECAST_BYTE 0xb00001f1) - -#ifndef REG_NO_SHADOW -#define R_DMA_CH8_CLR_INTR__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_DMA_CH8_CLR_INTR + 0)) -#define R_DMA_CH8_CLR_INTR__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_DMA_CH8_CLR_INTR + 0)) -#else /* REG_NO_SHADOW */ -#define R_DMA_CH8_CLR_INTR__SADDR (REG_STYPECAST_BYTE (®_shadow__hwregs)) -#define R_DMA_CH8_CLR_INTR__IADDR (REG_STYPECAST_BYTE (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_DMA_CH8_CLR_INTR__STYPECAST REG_STYPECAST_BYTE -#define R_DMA_CH8_CLR_INTR__SVAL REG_SVAL_ZERO -#define R_DMA_CH8_CLR_INTR__SVAL_I REG_SVAL_I_ZERO -#define R_DMA_CH8_CLR_INTR__TYPECAST REG_TYPECAST_BYTE -#define R_DMA_CH8_CLR_INTR__TYPE (REG_BYTE) -#define R_DMA_CH8_CLR_INTR__GET REG_GET_WO -#define R_DMA_CH8_CLR_INTR__IGET REG_IGET_WO -#define R_DMA_CH8_CLR_INTR__SET REG_SET_WO -#define R_DMA_CH8_CLR_INTR__ISET REG_ISET_WO -#define R_DMA_CH8_CLR_INTR__SET_VAL REG_SET_VAL_WO -#define R_DMA_CH8_CLR_INTR__EQL REG_EQL_WO -#define R_DMA_CH8_CLR_INTR__IEQL REG_IEQL_WO -#define R_DMA_CH8_CLR_INTR__RD REG_RD_WO -#define R_DMA_CH8_CLR_INTR__IRD REG_IRD_WO -#define R_DMA_CH8_CLR_INTR__WR REG_WR_WO -#define R_DMA_CH8_CLR_INTR__IWR REG_IWR_WO - -#define R_DMA_CH8_CLR_INTR__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_DMA_CH8_CLR_INTR__clr_eop__clr_eop__MASK 0x00000002U -#define R_DMA_CH8_CLR_INTR__clr_descr__clr_descr__MASK 0x00000001U - -#define R_DMA_CH8_CLR_INTR__clr_eop__MAX 0x1 -#define R_DMA_CH8_CLR_INTR__clr_descr__MAX 0x1 - -#define R_DMA_CH8_CLR_INTR__clr_eop__MIN 0 -#define R_DMA_CH8_CLR_INTR__clr_descr__MIN 0 - -#define R_DMA_CH8_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH8_CLR_INTR__clr_descr__BITNR 0 - -#define R_DMA_CH8_CLR_INTR__clr_eop__clr_eop__VAL REG_VAL_ENUM -#define R_DMA_CH8_CLR_INTR__clr_descr__clr_descr__VAL REG_VAL_ENUM - -#define R_DMA_CH8_CLR_INTR__clr_eop__clr_eop__do 1 -#define R_DMA_CH8_CLR_INTR__clr_eop__clr_eop__dont 0 -#define R_DMA_CH8_CLR_INTR__clr_descr__clr_descr__do 1 -#define R_DMA_CH8_CLR_INTR__clr_descr__clr_descr__dont 0 - -#endif - -/* - * R_DMA_CH8_CMD - * - type: RW - * - addr: 0xb00001f0 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH8_CMD__ADDR (REG_TYPECAST_BYTE 0xb00001f0) -#define R_DMA_CH8_CMD__SVAL REG_SVAL_SHADOW -#define R_DMA_CH8_CMD__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH8_CMD__TYPECAST REG_TYPECAST_BYTE -#define R_DMA_CH8_CMD__TYPE (REG_BYTE) -#define R_DMA_CH8_CMD__GET REG_GET_RW -#define R_DMA_CH8_CMD__IGET REG_IGET_RW -#define R_DMA_CH8_CMD__SET REG_SET_RW -#define R_DMA_CH8_CMD__ISET REG_ISET_RW -#define R_DMA_CH8_CMD__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH8_CMD__EQL REG_EQL_RW -#define R_DMA_CH8_CMD__IEQL REG_IEQL_RW -#define R_DMA_CH8_CMD__RD REG_RD_RW -#define R_DMA_CH8_CMD__IRD REG_IRD_RW -#define R_DMA_CH8_CMD__WR REG_WR_RW -#define R_DMA_CH8_CMD__IWR REG_IWR_RW - -#define R_DMA_CH8_CMD__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH8_CMD__READ(addr) \ - (*(addr)) - -#define R_DMA_CH8_CMD__cmd__cmd__MASK 0x00000007U - -#define R_DMA_CH8_CMD__cmd__MAX 0x7 - -#define R_DMA_CH8_CMD__cmd__MIN 0 - -#define R_DMA_CH8_CMD__cmd__BITNR 0 - -#define R_DMA_CH8_CMD__cmd__cmd__VAL REG_VAL_ENUM - -#define R_DMA_CH8_CMD__cmd__cmd__continue 3 -#define R_DMA_CH8_CMD__cmd__cmd__hold 0 -#define R_DMA_CH8_CMD__cmd__cmd__reset 4 -#define R_DMA_CH8_CMD__cmd__cmd__restart 3 -#define R_DMA_CH8_CMD__cmd__cmd__start 1 - -#endif - -/* - * R_DMA_CH8_DESCR - * - type: RW - * - addr: 0xb000018c - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH8_DESCR__ADDR (REG_TYPECAST_UDWORD 0xb000018c) -#define R_DMA_CH8_DESCR__SVAL REG_SVAL_SHADOW -#define R_DMA_CH8_DESCR__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH8_DESCR__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH8_DESCR__TYPE (REG_UDWORD) -#define R_DMA_CH8_DESCR__GET REG_GET_RW -#define R_DMA_CH8_DESCR__IGET REG_IGET_RW -#define R_DMA_CH8_DESCR__SET REG_SET_RW -#define R_DMA_CH8_DESCR__ISET REG_ISET_RW -#define R_DMA_CH8_DESCR__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH8_DESCR__EQL REG_EQL_RW -#define R_DMA_CH8_DESCR__IEQL REG_IEQL_RW -#define R_DMA_CH8_DESCR__RD REG_RD_RW -#define R_DMA_CH8_DESCR__IRD REG_IRD_RW -#define R_DMA_CH8_DESCR__WR REG_WR_RW -#define R_DMA_CH8_DESCR__IWR REG_IWR_RW - -#define R_DMA_CH8_DESCR__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH8_DESCR__READ(addr) \ - (*(addr)) - -#define R_DMA_CH8_DESCR__descr__descr__MASK 0xffffffffU - -#define R_DMA_CH8_DESCR__descr__MAX 0xffffffff - -#define R_DMA_CH8_DESCR__descr__MIN 0 - -#define R_DMA_CH8_DESCR__descr__BITNR 0 - -#define R_DMA_CH8_DESCR__descr__descr__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH8_FIRST - * - type: RW - * - addr: 0xb00001c0 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH8_FIRST__ADDR (REG_TYPECAST_UDWORD 0xb00001c0) -#define R_DMA_CH8_FIRST__SVAL REG_SVAL_SHADOW -#define R_DMA_CH8_FIRST__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH8_FIRST__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH8_FIRST__TYPE (REG_UDWORD) -#define R_DMA_CH8_FIRST__GET REG_GET_RW -#define R_DMA_CH8_FIRST__IGET REG_IGET_RW -#define R_DMA_CH8_FIRST__SET REG_SET_RW -#define R_DMA_CH8_FIRST__ISET REG_ISET_RW -#define R_DMA_CH8_FIRST__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH8_FIRST__EQL REG_EQL_RW -#define R_DMA_CH8_FIRST__IEQL REG_IEQL_RW -#define R_DMA_CH8_FIRST__RD REG_RD_RW -#define R_DMA_CH8_FIRST__IRD REG_IRD_RW -#define R_DMA_CH8_FIRST__WR REG_WR_RW -#define R_DMA_CH8_FIRST__IWR REG_IWR_RW - -#define R_DMA_CH8_FIRST__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH8_FIRST__READ(addr) \ - (*(addr)) - -#define R_DMA_CH8_FIRST__first__first__MASK 0xffffffffU - -#define R_DMA_CH8_FIRST__first__MAX 0xffffffff - -#define R_DMA_CH8_FIRST__first__MIN 0 - -#define R_DMA_CH8_FIRST__first__BITNR 0 - -#define R_DMA_CH8_FIRST__first__first__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH8_HWSW - * - type: RW - * - addr: 0xb0000180 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH8_HWSW__ADDR (REG_TYPECAST_UDWORD 0xb0000180) -#define R_DMA_CH8_HWSW__SVAL REG_SVAL_SHADOW -#define R_DMA_CH8_HWSW__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH8_HWSW__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH8_HWSW__TYPE (REG_UDWORD) -#define R_DMA_CH8_HWSW__GET REG_GET_RW -#define R_DMA_CH8_HWSW__IGET REG_IGET_RW -#define R_DMA_CH8_HWSW__SET REG_SET_RW -#define R_DMA_CH8_HWSW__ISET REG_ISET_RW -#define R_DMA_CH8_HWSW__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH8_HWSW__EQL REG_EQL_RW -#define R_DMA_CH8_HWSW__IEQL REG_IEQL_RW -#define R_DMA_CH8_HWSW__RD REG_RD_RW -#define R_DMA_CH8_HWSW__IRD REG_IRD_RW -#define R_DMA_CH8_HWSW__WR REG_WR_RW -#define R_DMA_CH8_HWSW__IWR REG_IWR_RW - -#define R_DMA_CH8_HWSW__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH8_HWSW__READ(addr) \ - (*(addr)) - -#define R_DMA_CH8_HWSW__hw__hw__MASK 0xffff0000U -#define R_DMA_CH8_HWSW__sw__sw__MASK 0x0000ffffU - -#define R_DMA_CH8_HWSW__hw__MAX 0xffff -#define R_DMA_CH8_HWSW__sw__MAX 0xffff - -#define R_DMA_CH8_HWSW__hw__MIN 0 -#define R_DMA_CH8_HWSW__sw__MIN 0 - -#define R_DMA_CH8_HWSW__hw__BITNR 16 -#define R_DMA_CH8_HWSW__sw__BITNR 0 - -#define R_DMA_CH8_HWSW__hw__hw__VAL REG_VAL_VAL -#define R_DMA_CH8_HWSW__sw__sw__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH8_NEP - * - type: RW - * - addr: 0xb00001c0 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH8_NEP__ADDR (REG_TYPECAST_UDWORD 0xb00001c0) -#define R_DMA_CH8_NEP__SVAL REG_SVAL_SHADOW -#define R_DMA_CH8_NEP__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH8_NEP__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH8_NEP__TYPE (REG_UDWORD) -#define R_DMA_CH8_NEP__GET REG_GET_RW -#define R_DMA_CH8_NEP__IGET REG_IGET_RW -#define R_DMA_CH8_NEP__SET REG_SET_RW -#define R_DMA_CH8_NEP__ISET REG_ISET_RW -#define R_DMA_CH8_NEP__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH8_NEP__EQL REG_EQL_RW -#define R_DMA_CH8_NEP__IEQL REG_IEQL_RW -#define R_DMA_CH8_NEP__RD REG_RD_RW -#define R_DMA_CH8_NEP__IRD REG_IRD_RW -#define R_DMA_CH8_NEP__WR REG_WR_RW -#define R_DMA_CH8_NEP__IWR REG_IWR_RW - -#define R_DMA_CH8_NEP__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH8_NEP__READ(addr) \ - (*(addr)) - -#define R_DMA_CH8_NEP__nep__nep__MASK 0xffffffffU - -#define R_DMA_CH8_NEP__nep__MAX 0xffffffff - -#define R_DMA_CH8_NEP__nep__MIN 0 - -#define R_DMA_CH8_NEP__nep__BITNR 0 - -#define R_DMA_CH8_NEP__nep__nep__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH8_NEXT - * - type: RW - * - addr: 0xb0000184 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH8_NEXT__ADDR (REG_TYPECAST_UDWORD 0xb0000184) -#define R_DMA_CH8_NEXT__SVAL REG_SVAL_SHADOW -#define R_DMA_CH8_NEXT__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH8_NEXT__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH8_NEXT__TYPE (REG_UDWORD) -#define R_DMA_CH8_NEXT__GET REG_GET_RW -#define R_DMA_CH8_NEXT__IGET REG_IGET_RW -#define R_DMA_CH8_NEXT__SET REG_SET_RW -#define R_DMA_CH8_NEXT__ISET REG_ISET_RW -#define R_DMA_CH8_NEXT__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH8_NEXT__EQL REG_EQL_RW -#define R_DMA_CH8_NEXT__IEQL REG_IEQL_RW -#define R_DMA_CH8_NEXT__RD REG_RD_RW -#define R_DMA_CH8_NEXT__IRD REG_IRD_RW -#define R_DMA_CH8_NEXT__WR REG_WR_RW -#define R_DMA_CH8_NEXT__IWR REG_IWR_RW - -#define R_DMA_CH8_NEXT__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH8_NEXT__READ(addr) \ - (*(addr)) - -#define R_DMA_CH8_NEXT__next__next__MASK 0xffffffffU - -#define R_DMA_CH8_NEXT__next__MAX 0xffffffff - -#define R_DMA_CH8_NEXT__next__MIN 0 - -#define R_DMA_CH8_NEXT__next__BITNR 0 - -#define R_DMA_CH8_NEXT__next__next__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH8_STATUS - * - type: RO - * - addr: 0xb00001f2 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH8_STATUS__ADDR (REG_TYPECAST_BYTE 0xb00001f2) -#define R_DMA_CH8_STATUS__SVAL REG_SVAL_SHADOW -#define R_DMA_CH8_STATUS__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH8_STATUS__TYPECAST REG_TYPECAST_BYTE -#define R_DMA_CH8_STATUS__TYPE (REG_BYTE) -#define R_DMA_CH8_STATUS__GET REG_GET_RO -#define R_DMA_CH8_STATUS__IGET REG_IGET_RO -#define R_DMA_CH8_STATUS__SET REG_SET_RO -#define R_DMA_CH8_STATUS__ISET REG_ISET_RO -#define R_DMA_CH8_STATUS__SET_VAL REG_SET_VAL_RO -#define R_DMA_CH8_STATUS__EQL REG_EQL_RO -#define R_DMA_CH8_STATUS__IEQL REG_IEQL_RO -#define R_DMA_CH8_STATUS__RD REG_RD_RO -#define R_DMA_CH8_STATUS__IRD REG_IRD_RO -#define R_DMA_CH8_STATUS__WR REG_WR_RO -#define R_DMA_CH8_STATUS__IWR REG_IWR_RO - -#define R_DMA_CH8_STATUS__READ(addr) \ - (*(addr)) - -#define R_DMA_CH8_STATUS__avail__avail__MASK 0x0000007fU - -#define R_DMA_CH8_STATUS__avail__MAX 0x7f - -#define R_DMA_CH8_STATUS__avail__MIN 0 - -#define R_DMA_CH8_STATUS__avail__BITNR 0 - -#define R_DMA_CH8_STATUS__avail__avail__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH8_SUB - * - type: RW - * - addr: 0xb000018c - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH8_SUB__ADDR (REG_TYPECAST_UDWORD 0xb000018c) -#define R_DMA_CH8_SUB__SVAL REG_SVAL_SHADOW -#define R_DMA_CH8_SUB__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH8_SUB__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH8_SUB__TYPE (REG_UDWORD) -#define R_DMA_CH8_SUB__GET REG_GET_RW -#define R_DMA_CH8_SUB__IGET REG_IGET_RW -#define R_DMA_CH8_SUB__SET REG_SET_RW -#define R_DMA_CH8_SUB__ISET REG_ISET_RW -#define R_DMA_CH8_SUB__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH8_SUB__EQL REG_EQL_RW -#define R_DMA_CH8_SUB__IEQL REG_IEQL_RW -#define R_DMA_CH8_SUB__RD REG_RD_RW -#define R_DMA_CH8_SUB__IRD REG_IRD_RW -#define R_DMA_CH8_SUB__WR REG_WR_RW -#define R_DMA_CH8_SUB__IWR REG_IWR_RW - -#define R_DMA_CH8_SUB__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH8_SUB__READ(addr) \ - (*(addr)) - -#define R_DMA_CH8_SUB__sub__sub__MASK 0xffffffffU - -#define R_DMA_CH8_SUB__sub__MAX 0xffffffff - -#define R_DMA_CH8_SUB__sub__MIN 0 - -#define R_DMA_CH8_SUB__sub__BITNR 0 - -#define R_DMA_CH8_SUB__sub__sub__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH8_SUB0_CLR_INTR - * - type: WO - * - addr: 0xb00001e3 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH8_SUB0_CLR_INTR__ADDR (REG_TYPECAST_BYTE 0xb00001e3) - -#ifndef REG_NO_SHADOW -#define R_DMA_CH8_SUB0_CLR_INTR__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_DMA_CH8_SUB0_CLR_INTR + 0)) -#define R_DMA_CH8_SUB0_CLR_INTR__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_DMA_CH8_SUB0_CLR_INTR + 0)) -#else /* REG_NO_SHADOW */ -#define R_DMA_CH8_SUB0_CLR_INTR__SADDR (REG_STYPECAST_BYTE (®_shadow__hwregs)) -#define R_DMA_CH8_SUB0_CLR_INTR__IADDR (REG_STYPECAST_BYTE (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_DMA_CH8_SUB0_CLR_INTR__STYPECAST REG_STYPECAST_BYTE -#define R_DMA_CH8_SUB0_CLR_INTR__SVAL REG_SVAL_ZERO -#define R_DMA_CH8_SUB0_CLR_INTR__SVAL_I REG_SVAL_I_ZERO -#define R_DMA_CH8_SUB0_CLR_INTR__TYPECAST REG_TYPECAST_BYTE -#define R_DMA_CH8_SUB0_CLR_INTR__TYPE (REG_BYTE) -#define R_DMA_CH8_SUB0_CLR_INTR__GET REG_GET_WO -#define R_DMA_CH8_SUB0_CLR_INTR__IGET REG_IGET_WO -#define R_DMA_CH8_SUB0_CLR_INTR__SET REG_SET_WO -#define R_DMA_CH8_SUB0_CLR_INTR__ISET REG_ISET_WO -#define R_DMA_CH8_SUB0_CLR_INTR__SET_VAL REG_SET_VAL_WO -#define R_DMA_CH8_SUB0_CLR_INTR__EQL REG_EQL_WO -#define R_DMA_CH8_SUB0_CLR_INTR__IEQL REG_IEQL_WO -#define R_DMA_CH8_SUB0_CLR_INTR__RD REG_RD_WO -#define R_DMA_CH8_SUB0_CLR_INTR__IRD REG_IRD_WO -#define R_DMA_CH8_SUB0_CLR_INTR__WR REG_WR_WO -#define R_DMA_CH8_SUB0_CLR_INTR__IWR REG_IWR_WO - -#define R_DMA_CH8_SUB0_CLR_INTR__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__clr_descr__MASK 0x00000001U - -#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__MAX 0x1 - -#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__MIN 0 - -#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__BITNR 0 - -#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__clr_descr__VAL REG_VAL_ENUM - -#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__clr_descr__do 1 -#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__clr_descr__dont 0 - -#endif - -/* - * R_DMA_CH8_SUB0_CMD - * - type: RW - * - addr: 0xb00001d3 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH8_SUB0_CMD__ADDR (REG_TYPECAST_BYTE 0xb00001d3) -#define R_DMA_CH8_SUB0_CMD__SVAL REG_SVAL_SHADOW -#define R_DMA_CH8_SUB0_CMD__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH8_SUB0_CMD__TYPECAST REG_TYPECAST_BYTE -#define R_DMA_CH8_SUB0_CMD__TYPE (REG_BYTE) -#define R_DMA_CH8_SUB0_CMD__GET REG_GET_RW -#define R_DMA_CH8_SUB0_CMD__IGET REG_IGET_RW -#define R_DMA_CH8_SUB0_CMD__SET REG_SET_RW -#define R_DMA_CH8_SUB0_CMD__ISET REG_ISET_RW -#define R_DMA_CH8_SUB0_CMD__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH8_SUB0_CMD__EQL REG_EQL_RW -#define R_DMA_CH8_SUB0_CMD__IEQL REG_IEQL_RW -#define R_DMA_CH8_SUB0_CMD__RD REG_RD_RW -#define R_DMA_CH8_SUB0_CMD__IRD REG_IRD_RW -#define R_DMA_CH8_SUB0_CMD__WR REG_WR_RW -#define R_DMA_CH8_SUB0_CMD__IWR REG_IWR_RW - -#define R_DMA_CH8_SUB0_CMD__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH8_SUB0_CMD__READ(addr) \ - (*(addr)) - -#define R_DMA_CH8_SUB0_CMD__cmd__cmd__MASK 0x00000001U - -#define R_DMA_CH8_SUB0_CMD__cmd__MAX 0x1 - -#define R_DMA_CH8_SUB0_CMD__cmd__MIN 0 - -#define R_DMA_CH8_SUB0_CMD__cmd__BITNR 0 - -#define R_DMA_CH8_SUB0_CMD__cmd__cmd__VAL REG_VAL_ENUM - -#define R_DMA_CH8_SUB0_CMD__cmd__cmd__start 1 -#define R_DMA_CH8_SUB0_CMD__cmd__cmd__stop 0 - -#endif - -/* - * R_DMA_CH8_SUB0_EP - * - type: RW - * - addr: 0xb00001c8 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH8_SUB0_EP__ADDR (REG_TYPECAST_UDWORD 0xb00001c8) -#define R_DMA_CH8_SUB0_EP__SVAL REG_SVAL_SHADOW -#define R_DMA_CH8_SUB0_EP__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH8_SUB0_EP__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH8_SUB0_EP__TYPE (REG_UDWORD) -#define R_DMA_CH8_SUB0_EP__GET REG_GET_RW -#define R_DMA_CH8_SUB0_EP__IGET REG_IGET_RW -#define R_DMA_CH8_SUB0_EP__SET REG_SET_RW -#define R_DMA_CH8_SUB0_EP__ISET REG_ISET_RW -#define R_DMA_CH8_SUB0_EP__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH8_SUB0_EP__EQL REG_EQL_RW -#define R_DMA_CH8_SUB0_EP__IEQL REG_IEQL_RW -#define R_DMA_CH8_SUB0_EP__RD REG_RD_RW -#define R_DMA_CH8_SUB0_EP__IRD REG_IRD_RW -#define R_DMA_CH8_SUB0_EP__WR REG_WR_RW -#define R_DMA_CH8_SUB0_EP__IWR REG_IWR_RW - -#define R_DMA_CH8_SUB0_EP__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH8_SUB0_EP__READ(addr) \ - (*(addr)) - -#define R_DMA_CH8_SUB0_EP__ep__ep__MASK 0xffffffffU - -#define R_DMA_CH8_SUB0_EP__ep__MAX 0xffffffff - -#define R_DMA_CH8_SUB0_EP__ep__MIN 0 - -#define R_DMA_CH8_SUB0_EP__ep__BITNR 0 - -#define R_DMA_CH8_SUB0_EP__ep__ep__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH8_SUB1_CLR_INTR - * - type: WO - * - addr: 0xb00001e7 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH8_SUB1_CLR_INTR__ADDR (REG_TYPECAST_BYTE 0xb00001e7) - -#ifndef REG_NO_SHADOW -#define R_DMA_CH8_SUB1_CLR_INTR__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_DMA_CH8_SUB1_CLR_INTR + 0)) -#define R_DMA_CH8_SUB1_CLR_INTR__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_DMA_CH8_SUB1_CLR_INTR + 0)) -#else /* REG_NO_SHADOW */ -#define R_DMA_CH8_SUB1_CLR_INTR__SADDR (REG_STYPECAST_BYTE (®_shadow__hwregs)) -#define R_DMA_CH8_SUB1_CLR_INTR__IADDR (REG_STYPECAST_BYTE (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_DMA_CH8_SUB1_CLR_INTR__STYPECAST REG_STYPECAST_BYTE -#define R_DMA_CH8_SUB1_CLR_INTR__SVAL REG_SVAL_ZERO -#define R_DMA_CH8_SUB1_CLR_INTR__SVAL_I REG_SVAL_I_ZERO -#define R_DMA_CH8_SUB1_CLR_INTR__TYPECAST REG_TYPECAST_BYTE -#define R_DMA_CH8_SUB1_CLR_INTR__TYPE (REG_BYTE) -#define R_DMA_CH8_SUB1_CLR_INTR__GET REG_GET_WO -#define R_DMA_CH8_SUB1_CLR_INTR__IGET REG_IGET_WO -#define R_DMA_CH8_SUB1_CLR_INTR__SET REG_SET_WO -#define R_DMA_CH8_SUB1_CLR_INTR__ISET REG_ISET_WO -#define R_DMA_CH8_SUB1_CLR_INTR__SET_VAL REG_SET_VAL_WO -#define R_DMA_CH8_SUB1_CLR_INTR__EQL REG_EQL_WO -#define R_DMA_CH8_SUB1_CLR_INTR__IEQL REG_IEQL_WO -#define R_DMA_CH8_SUB1_CLR_INTR__RD REG_RD_WO -#define R_DMA_CH8_SUB1_CLR_INTR__IRD REG_IRD_WO -#define R_DMA_CH8_SUB1_CLR_INTR__WR REG_WR_WO -#define R_DMA_CH8_SUB1_CLR_INTR__IWR REG_IWR_WO - -#define R_DMA_CH8_SUB1_CLR_INTR__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__clr_descr__MASK 0x00000001U - -#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__MAX 0x1 - -#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__MIN 0 - -#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__BITNR 0 - -#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__clr_descr__VAL REG_VAL_ENUM - -#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__clr_descr__do 1 -#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__clr_descr__dont 0 - -#endif - -/* - * R_DMA_CH8_SUB1_CMD - * - type: RW - * - addr: 0xb00001d7 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH8_SUB1_CMD__ADDR (REG_TYPECAST_BYTE 0xb00001d7) -#define R_DMA_CH8_SUB1_CMD__SVAL REG_SVAL_SHADOW -#define R_DMA_CH8_SUB1_CMD__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH8_SUB1_CMD__TYPECAST REG_TYPECAST_BYTE -#define R_DMA_CH8_SUB1_CMD__TYPE (REG_BYTE) -#define R_DMA_CH8_SUB1_CMD__GET REG_GET_RW -#define R_DMA_CH8_SUB1_CMD__IGET REG_IGET_RW -#define R_DMA_CH8_SUB1_CMD__SET REG_SET_RW -#define R_DMA_CH8_SUB1_CMD__ISET REG_ISET_RW -#define R_DMA_CH8_SUB1_CMD__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH8_SUB1_CMD__EQL REG_EQL_RW -#define R_DMA_CH8_SUB1_CMD__IEQL REG_IEQL_RW -#define R_DMA_CH8_SUB1_CMD__RD REG_RD_RW -#define R_DMA_CH8_SUB1_CMD__IRD REG_IRD_RW -#define R_DMA_CH8_SUB1_CMD__WR REG_WR_RW -#define R_DMA_CH8_SUB1_CMD__IWR REG_IWR_RW - -#define R_DMA_CH8_SUB1_CMD__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH8_SUB1_CMD__READ(addr) \ - (*(addr)) - -#define R_DMA_CH8_SUB1_CMD__cmd__cmd__MASK 0x00000001U - -#define R_DMA_CH8_SUB1_CMD__cmd__MAX 0x1 - -#define R_DMA_CH8_SUB1_CMD__cmd__MIN 0 - -#define R_DMA_CH8_SUB1_CMD__cmd__BITNR 0 - -#define R_DMA_CH8_SUB1_CMD__cmd__cmd__VAL REG_VAL_ENUM - -#define R_DMA_CH8_SUB1_CMD__cmd__cmd__start 1 -#define R_DMA_CH8_SUB1_CMD__cmd__cmd__stop 0 - -#endif - -/* - * R_DMA_CH8_SUB1_EP - * - type: RW - * - addr: 0xb00001cc - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH8_SUB1_EP__ADDR (REG_TYPECAST_UDWORD 0xb00001cc) -#define R_DMA_CH8_SUB1_EP__SVAL REG_SVAL_SHADOW -#define R_DMA_CH8_SUB1_EP__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH8_SUB1_EP__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH8_SUB1_EP__TYPE (REG_UDWORD) -#define R_DMA_CH8_SUB1_EP__GET REG_GET_RW -#define R_DMA_CH8_SUB1_EP__IGET REG_IGET_RW -#define R_DMA_CH8_SUB1_EP__SET REG_SET_RW -#define R_DMA_CH8_SUB1_EP__ISET REG_ISET_RW -#define R_DMA_CH8_SUB1_EP__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH8_SUB1_EP__EQL REG_EQL_RW -#define R_DMA_CH8_SUB1_EP__IEQL REG_IEQL_RW -#define R_DMA_CH8_SUB1_EP__RD REG_RD_RW -#define R_DMA_CH8_SUB1_EP__IRD REG_IRD_RW -#define R_DMA_CH8_SUB1_EP__WR REG_WR_RW -#define R_DMA_CH8_SUB1_EP__IWR REG_IWR_RW - -#define R_DMA_CH8_SUB1_EP__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH8_SUB1_EP__READ(addr) \ - (*(addr)) - -#define R_DMA_CH8_SUB1_EP__ep__ep__MASK 0xffffffffU - -#define R_DMA_CH8_SUB1_EP__ep__MAX 0xffffffff - -#define R_DMA_CH8_SUB1_EP__ep__MIN 0 - -#define R_DMA_CH8_SUB1_EP__ep__BITNR 0 - -#define R_DMA_CH8_SUB1_EP__ep__ep__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH8_SUB2_CLR_INTR - * - type: WO - * - addr: 0xb00001eb - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH8_SUB2_CLR_INTR__ADDR (REG_TYPECAST_BYTE 0xb00001eb) - -#ifndef REG_NO_SHADOW -#define R_DMA_CH8_SUB2_CLR_INTR__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_DMA_CH8_SUB2_CLR_INTR + 0)) -#define R_DMA_CH8_SUB2_CLR_INTR__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_DMA_CH8_SUB2_CLR_INTR + 0)) -#else /* REG_NO_SHADOW */ -#define R_DMA_CH8_SUB2_CLR_INTR__SADDR (REG_STYPECAST_BYTE (®_shadow__hwregs)) -#define R_DMA_CH8_SUB2_CLR_INTR__IADDR (REG_STYPECAST_BYTE (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_DMA_CH8_SUB2_CLR_INTR__STYPECAST REG_STYPECAST_BYTE -#define R_DMA_CH8_SUB2_CLR_INTR__SVAL REG_SVAL_ZERO -#define R_DMA_CH8_SUB2_CLR_INTR__SVAL_I REG_SVAL_I_ZERO -#define R_DMA_CH8_SUB2_CLR_INTR__TYPECAST REG_TYPECAST_BYTE -#define R_DMA_CH8_SUB2_CLR_INTR__TYPE (REG_BYTE) -#define R_DMA_CH8_SUB2_CLR_INTR__GET REG_GET_WO -#define R_DMA_CH8_SUB2_CLR_INTR__IGET REG_IGET_WO -#define R_DMA_CH8_SUB2_CLR_INTR__SET REG_SET_WO -#define R_DMA_CH8_SUB2_CLR_INTR__ISET REG_ISET_WO -#define R_DMA_CH8_SUB2_CLR_INTR__SET_VAL REG_SET_VAL_WO -#define R_DMA_CH8_SUB2_CLR_INTR__EQL REG_EQL_WO -#define R_DMA_CH8_SUB2_CLR_INTR__IEQL REG_IEQL_WO -#define R_DMA_CH8_SUB2_CLR_INTR__RD REG_RD_WO -#define R_DMA_CH8_SUB2_CLR_INTR__IRD REG_IRD_WO -#define R_DMA_CH8_SUB2_CLR_INTR__WR REG_WR_WO -#define R_DMA_CH8_SUB2_CLR_INTR__IWR REG_IWR_WO - -#define R_DMA_CH8_SUB2_CLR_INTR__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__clr_descr__MASK 0x00000001U - -#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__MAX 0x1 - -#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__MIN 0 - -#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__BITNR 0 - -#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__clr_descr__VAL REG_VAL_ENUM - -#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__clr_descr__do 1 -#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__clr_descr__dont 0 - -#endif - -/* - * R_DMA_CH8_SUB2_CMD - * - type: RW - * - addr: 0xb00001db - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH8_SUB2_CMD__ADDR (REG_TYPECAST_BYTE 0xb00001db) -#define R_DMA_CH8_SUB2_CMD__SVAL REG_SVAL_SHADOW -#define R_DMA_CH8_SUB2_CMD__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH8_SUB2_CMD__TYPECAST REG_TYPECAST_BYTE -#define R_DMA_CH8_SUB2_CMD__TYPE (REG_BYTE) -#define R_DMA_CH8_SUB2_CMD__GET REG_GET_RW -#define R_DMA_CH8_SUB2_CMD__IGET REG_IGET_RW -#define R_DMA_CH8_SUB2_CMD__SET REG_SET_RW -#define R_DMA_CH8_SUB2_CMD__ISET REG_ISET_RW -#define R_DMA_CH8_SUB2_CMD__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH8_SUB2_CMD__EQL REG_EQL_RW -#define R_DMA_CH8_SUB2_CMD__IEQL REG_IEQL_RW -#define R_DMA_CH8_SUB2_CMD__RD REG_RD_RW -#define R_DMA_CH8_SUB2_CMD__IRD REG_IRD_RW -#define R_DMA_CH8_SUB2_CMD__WR REG_WR_RW -#define R_DMA_CH8_SUB2_CMD__IWR REG_IWR_RW - -#define R_DMA_CH8_SUB2_CMD__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH8_SUB2_CMD__READ(addr) \ - (*(addr)) - -#define R_DMA_CH8_SUB2_CMD__cmd__cmd__MASK 0x00000001U - -#define R_DMA_CH8_SUB2_CMD__cmd__MAX 0x1 - -#define R_DMA_CH8_SUB2_CMD__cmd__MIN 0 - -#define R_DMA_CH8_SUB2_CMD__cmd__BITNR 0 - -#define R_DMA_CH8_SUB2_CMD__cmd__cmd__VAL REG_VAL_ENUM - -#define R_DMA_CH8_SUB2_CMD__cmd__cmd__start 1 -#define R_DMA_CH8_SUB2_CMD__cmd__cmd__stop 0 - -#endif - -/* - * R_DMA_CH8_SUB2_EP - * - type: RW - * - addr: 0xb00001f8 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH8_SUB2_EP__ADDR (REG_TYPECAST_UDWORD 0xb00001f8) -#define R_DMA_CH8_SUB2_EP__SVAL REG_SVAL_SHADOW -#define R_DMA_CH8_SUB2_EP__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH8_SUB2_EP__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH8_SUB2_EP__TYPE (REG_UDWORD) -#define R_DMA_CH8_SUB2_EP__GET REG_GET_RW -#define R_DMA_CH8_SUB2_EP__IGET REG_IGET_RW -#define R_DMA_CH8_SUB2_EP__SET REG_SET_RW -#define R_DMA_CH8_SUB2_EP__ISET REG_ISET_RW -#define R_DMA_CH8_SUB2_EP__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH8_SUB2_EP__EQL REG_EQL_RW -#define R_DMA_CH8_SUB2_EP__IEQL REG_IEQL_RW -#define R_DMA_CH8_SUB2_EP__RD REG_RD_RW -#define R_DMA_CH8_SUB2_EP__IRD REG_IRD_RW -#define R_DMA_CH8_SUB2_EP__WR REG_WR_RW -#define R_DMA_CH8_SUB2_EP__IWR REG_IWR_RW - -#define R_DMA_CH8_SUB2_EP__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH8_SUB2_EP__READ(addr) \ - (*(addr)) - -#define R_DMA_CH8_SUB2_EP__ep__ep__MASK 0xffffffffU - -#define R_DMA_CH8_SUB2_EP__ep__MAX 0xffffffff - -#define R_DMA_CH8_SUB2_EP__ep__MIN 0 - -#define R_DMA_CH8_SUB2_EP__ep__BITNR 0 - -#define R_DMA_CH8_SUB2_EP__ep__ep__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH8_SUB3_CLR_INTR - * - type: WO - * - addr: 0xb00001ef - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH8_SUB3_CLR_INTR__ADDR (REG_TYPECAST_BYTE 0xb00001ef) - -#ifndef REG_NO_SHADOW -#define R_DMA_CH8_SUB3_CLR_INTR__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_DMA_CH8_SUB3_CLR_INTR + 0)) -#define R_DMA_CH8_SUB3_CLR_INTR__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_DMA_CH8_SUB3_CLR_INTR + 0)) -#else /* REG_NO_SHADOW */ -#define R_DMA_CH8_SUB3_CLR_INTR__SADDR (REG_STYPECAST_BYTE (®_shadow__hwregs)) -#define R_DMA_CH8_SUB3_CLR_INTR__IADDR (REG_STYPECAST_BYTE (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_DMA_CH8_SUB3_CLR_INTR__STYPECAST REG_STYPECAST_BYTE -#define R_DMA_CH8_SUB3_CLR_INTR__SVAL REG_SVAL_ZERO -#define R_DMA_CH8_SUB3_CLR_INTR__SVAL_I REG_SVAL_I_ZERO -#define R_DMA_CH8_SUB3_CLR_INTR__TYPECAST REG_TYPECAST_BYTE -#define R_DMA_CH8_SUB3_CLR_INTR__TYPE (REG_BYTE) -#define R_DMA_CH8_SUB3_CLR_INTR__GET REG_GET_WO -#define R_DMA_CH8_SUB3_CLR_INTR__IGET REG_IGET_WO -#define R_DMA_CH8_SUB3_CLR_INTR__SET REG_SET_WO -#define R_DMA_CH8_SUB3_CLR_INTR__ISET REG_ISET_WO -#define R_DMA_CH8_SUB3_CLR_INTR__SET_VAL REG_SET_VAL_WO -#define R_DMA_CH8_SUB3_CLR_INTR__EQL REG_EQL_WO -#define R_DMA_CH8_SUB3_CLR_INTR__IEQL REG_IEQL_WO -#define R_DMA_CH8_SUB3_CLR_INTR__RD REG_RD_WO -#define R_DMA_CH8_SUB3_CLR_INTR__IRD REG_IRD_WO -#define R_DMA_CH8_SUB3_CLR_INTR__WR REG_WR_WO -#define R_DMA_CH8_SUB3_CLR_INTR__IWR REG_IWR_WO - -#define R_DMA_CH8_SUB3_CLR_INTR__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__clr_descr__MASK 0x00000001U - -#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__MAX 0x1 - -#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__MIN 0 - -#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__BITNR 0 - -#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__clr_descr__VAL REG_VAL_ENUM - -#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__clr_descr__do 1 -#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__clr_descr__dont 0 - -#endif - -/* - * R_DMA_CH8_SUB3_CMD - * - type: RW - * - addr: 0xb00001df - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH8_SUB3_CMD__ADDR (REG_TYPECAST_BYTE 0xb00001df) -#define R_DMA_CH8_SUB3_CMD__SVAL REG_SVAL_SHADOW -#define R_DMA_CH8_SUB3_CMD__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH8_SUB3_CMD__TYPECAST REG_TYPECAST_BYTE -#define R_DMA_CH8_SUB3_CMD__TYPE (REG_BYTE) -#define R_DMA_CH8_SUB3_CMD__GET REG_GET_RW -#define R_DMA_CH8_SUB3_CMD__IGET REG_IGET_RW -#define R_DMA_CH8_SUB3_CMD__SET REG_SET_RW -#define R_DMA_CH8_SUB3_CMD__ISET REG_ISET_RW -#define R_DMA_CH8_SUB3_CMD__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH8_SUB3_CMD__EQL REG_EQL_RW -#define R_DMA_CH8_SUB3_CMD__IEQL REG_IEQL_RW -#define R_DMA_CH8_SUB3_CMD__RD REG_RD_RW -#define R_DMA_CH8_SUB3_CMD__IRD REG_IRD_RW -#define R_DMA_CH8_SUB3_CMD__WR REG_WR_RW -#define R_DMA_CH8_SUB3_CMD__IWR REG_IWR_RW - -#define R_DMA_CH8_SUB3_CMD__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH8_SUB3_CMD__READ(addr) \ - (*(addr)) - -#define R_DMA_CH8_SUB3_CMD__cmd__cmd__MASK 0x00000001U - -#define R_DMA_CH8_SUB3_CMD__cmd__MAX 0x1 - -#define R_DMA_CH8_SUB3_CMD__cmd__MIN 0 - -#define R_DMA_CH8_SUB3_CMD__cmd__BITNR 0 - -#define R_DMA_CH8_SUB3_CMD__cmd__cmd__VAL REG_VAL_ENUM - -#define R_DMA_CH8_SUB3_CMD__cmd__cmd__start 1 -#define R_DMA_CH8_SUB3_CMD__cmd__cmd__stop 0 - -#endif - -/* - * R_DMA_CH8_SUB3_EP - * - type: RW - * - addr: 0xb00001fc - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH8_SUB3_EP__ADDR (REG_TYPECAST_UDWORD 0xb00001fc) -#define R_DMA_CH8_SUB3_EP__SVAL REG_SVAL_SHADOW -#define R_DMA_CH8_SUB3_EP__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH8_SUB3_EP__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH8_SUB3_EP__TYPE (REG_UDWORD) -#define R_DMA_CH8_SUB3_EP__GET REG_GET_RW -#define R_DMA_CH8_SUB3_EP__IGET REG_IGET_RW -#define R_DMA_CH8_SUB3_EP__SET REG_SET_RW -#define R_DMA_CH8_SUB3_EP__ISET REG_ISET_RW -#define R_DMA_CH8_SUB3_EP__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH8_SUB3_EP__EQL REG_EQL_RW -#define R_DMA_CH8_SUB3_EP__IEQL REG_IEQL_RW -#define R_DMA_CH8_SUB3_EP__RD REG_RD_RW -#define R_DMA_CH8_SUB3_EP__IRD REG_IRD_RW -#define R_DMA_CH8_SUB3_EP__WR REG_WR_RW -#define R_DMA_CH8_SUB3_EP__IWR REG_IWR_RW - -#define R_DMA_CH8_SUB3_EP__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH8_SUB3_EP__READ(addr) \ - (*(addr)) - -#define R_DMA_CH8_SUB3_EP__ep__ep__MASK 0xffffffffU - -#define R_DMA_CH8_SUB3_EP__ep__MAX 0xffffffff - -#define R_DMA_CH8_SUB3_EP__ep__MIN 0 - -#define R_DMA_CH8_SUB3_EP__ep__BITNR 0 - -#define R_DMA_CH8_SUB3_EP__ep__ep__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH9_BUF - * - type: RW - * - addr: 0xb0000198 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH9_BUF__ADDR (REG_TYPECAST_UDWORD 0xb0000198) -#define R_DMA_CH9_BUF__SVAL REG_SVAL_SHADOW -#define R_DMA_CH9_BUF__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH9_BUF__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH9_BUF__TYPE (REG_UDWORD) -#define R_DMA_CH9_BUF__GET REG_GET_RW -#define R_DMA_CH9_BUF__IGET REG_IGET_RW -#define R_DMA_CH9_BUF__SET REG_SET_RW -#define R_DMA_CH9_BUF__ISET REG_ISET_RW -#define R_DMA_CH9_BUF__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH9_BUF__EQL REG_EQL_RW -#define R_DMA_CH9_BUF__IEQL REG_IEQL_RW -#define R_DMA_CH9_BUF__RD REG_RD_RW -#define R_DMA_CH9_BUF__IRD REG_IRD_RW -#define R_DMA_CH9_BUF__WR REG_WR_RW -#define R_DMA_CH9_BUF__IWR REG_IWR_RW - -#define R_DMA_CH9_BUF__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH9_BUF__READ(addr) \ - (*(addr)) - -#define R_DMA_CH9_BUF__buf__buf__MASK 0xffffffffU - -#define R_DMA_CH9_BUF__buf__MAX 0xffffffff - -#define R_DMA_CH9_BUF__buf__MIN 0 - -#define R_DMA_CH9_BUF__buf__BITNR 0 - -#define R_DMA_CH9_BUF__buf__buf__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH9_CLR_INTR - * - type: WO - * - addr: 0xb00001f5 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH9_CLR_INTR__ADDR (REG_TYPECAST_BYTE 0xb00001f5) - -#ifndef REG_NO_SHADOW -#define R_DMA_CH9_CLR_INTR__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_DMA_CH9_CLR_INTR + 0)) -#define R_DMA_CH9_CLR_INTR__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_DMA_CH9_CLR_INTR + 0)) -#else /* REG_NO_SHADOW */ -#define R_DMA_CH9_CLR_INTR__SADDR (REG_STYPECAST_BYTE (®_shadow__hwregs)) -#define R_DMA_CH9_CLR_INTR__IADDR (REG_STYPECAST_BYTE (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_DMA_CH9_CLR_INTR__STYPECAST REG_STYPECAST_BYTE -#define R_DMA_CH9_CLR_INTR__SVAL REG_SVAL_ZERO -#define R_DMA_CH9_CLR_INTR__SVAL_I REG_SVAL_I_ZERO -#define R_DMA_CH9_CLR_INTR__TYPECAST REG_TYPECAST_BYTE -#define R_DMA_CH9_CLR_INTR__TYPE (REG_BYTE) -#define R_DMA_CH9_CLR_INTR__GET REG_GET_WO -#define R_DMA_CH9_CLR_INTR__IGET REG_IGET_WO -#define R_DMA_CH9_CLR_INTR__SET REG_SET_WO -#define R_DMA_CH9_CLR_INTR__ISET REG_ISET_WO -#define R_DMA_CH9_CLR_INTR__SET_VAL REG_SET_VAL_WO -#define R_DMA_CH9_CLR_INTR__EQL REG_EQL_WO -#define R_DMA_CH9_CLR_INTR__IEQL REG_IEQL_WO -#define R_DMA_CH9_CLR_INTR__RD REG_RD_WO -#define R_DMA_CH9_CLR_INTR__IRD REG_IRD_WO -#define R_DMA_CH9_CLR_INTR__WR REG_WR_WO -#define R_DMA_CH9_CLR_INTR__IWR REG_IWR_WO - -#define R_DMA_CH9_CLR_INTR__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_DMA_CH9_CLR_INTR__clr_eop__clr_eop__MASK 0x00000002U -#define R_DMA_CH9_CLR_INTR__clr_descr__clr_descr__MASK 0x00000001U - -#define R_DMA_CH9_CLR_INTR__clr_eop__MAX 0x1 -#define R_DMA_CH9_CLR_INTR__clr_descr__MAX 0x1 - -#define R_DMA_CH9_CLR_INTR__clr_eop__MIN 0 -#define R_DMA_CH9_CLR_INTR__clr_descr__MIN 0 - -#define R_DMA_CH9_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH9_CLR_INTR__clr_descr__BITNR 0 - -#define R_DMA_CH9_CLR_INTR__clr_eop__clr_eop__VAL REG_VAL_ENUM -#define R_DMA_CH9_CLR_INTR__clr_descr__clr_descr__VAL REG_VAL_ENUM - -#define R_DMA_CH9_CLR_INTR__clr_eop__clr_eop__do 1 -#define R_DMA_CH9_CLR_INTR__clr_eop__clr_eop__dont 0 -#define R_DMA_CH9_CLR_INTR__clr_descr__clr_descr__do 1 -#define R_DMA_CH9_CLR_INTR__clr_descr__clr_descr__dont 0 - -#endif - -/* - * R_DMA_CH9_CMD - * - type: RW - * - addr: 0xb00001f4 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH9_CMD__ADDR (REG_TYPECAST_BYTE 0xb00001f4) -#define R_DMA_CH9_CMD__SVAL REG_SVAL_SHADOW -#define R_DMA_CH9_CMD__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH9_CMD__TYPECAST REG_TYPECAST_BYTE -#define R_DMA_CH9_CMD__TYPE (REG_BYTE) -#define R_DMA_CH9_CMD__GET REG_GET_RW -#define R_DMA_CH9_CMD__IGET REG_IGET_RW -#define R_DMA_CH9_CMD__SET REG_SET_RW -#define R_DMA_CH9_CMD__ISET REG_ISET_RW -#define R_DMA_CH9_CMD__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH9_CMD__EQL REG_EQL_RW -#define R_DMA_CH9_CMD__IEQL REG_IEQL_RW -#define R_DMA_CH9_CMD__RD REG_RD_RW -#define R_DMA_CH9_CMD__IRD REG_IRD_RW -#define R_DMA_CH9_CMD__WR REG_WR_RW -#define R_DMA_CH9_CMD__IWR REG_IWR_RW - -#define R_DMA_CH9_CMD__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH9_CMD__READ(addr) \ - (*(addr)) - -#define R_DMA_CH9_CMD__cmd__cmd__MASK 0x00000007U - -#define R_DMA_CH9_CMD__cmd__MAX 0x7 - -#define R_DMA_CH9_CMD__cmd__MIN 0 - -#define R_DMA_CH9_CMD__cmd__BITNR 0 - -#define R_DMA_CH9_CMD__cmd__cmd__VAL REG_VAL_ENUM - -#define R_DMA_CH9_CMD__cmd__cmd__continue 3 -#define R_DMA_CH9_CMD__cmd__cmd__hold 0 -#define R_DMA_CH9_CMD__cmd__cmd__reset 4 -#define R_DMA_CH9_CMD__cmd__cmd__restart 3 -#define R_DMA_CH9_CMD__cmd__cmd__start 1 - -#endif - -/* - * R_DMA_CH9_DESCR - * - type: RW - * - addr: 0xb000019c - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH9_DESCR__ADDR (REG_TYPECAST_UDWORD 0xb000019c) -#define R_DMA_CH9_DESCR__SVAL REG_SVAL_SHADOW -#define R_DMA_CH9_DESCR__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH9_DESCR__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH9_DESCR__TYPE (REG_UDWORD) -#define R_DMA_CH9_DESCR__GET REG_GET_RW -#define R_DMA_CH9_DESCR__IGET REG_IGET_RW -#define R_DMA_CH9_DESCR__SET REG_SET_RW -#define R_DMA_CH9_DESCR__ISET REG_ISET_RW -#define R_DMA_CH9_DESCR__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH9_DESCR__EQL REG_EQL_RW -#define R_DMA_CH9_DESCR__IEQL REG_IEQL_RW -#define R_DMA_CH9_DESCR__RD REG_RD_RW -#define R_DMA_CH9_DESCR__IRD REG_IRD_RW -#define R_DMA_CH9_DESCR__WR REG_WR_RW -#define R_DMA_CH9_DESCR__IWR REG_IWR_RW - -#define R_DMA_CH9_DESCR__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH9_DESCR__READ(addr) \ - (*(addr)) - -#define R_DMA_CH9_DESCR__descr__descr__MASK 0xffffffffU - -#define R_DMA_CH9_DESCR__descr__MAX 0xffffffff - -#define R_DMA_CH9_DESCR__descr__MIN 0 - -#define R_DMA_CH9_DESCR__descr__BITNR 0 - -#define R_DMA_CH9_DESCR__descr__descr__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH9_FIRST - * - type: RW - * - addr: 0xb00001c4 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH9_FIRST__ADDR (REG_TYPECAST_UDWORD 0xb00001c4) -#define R_DMA_CH9_FIRST__SVAL REG_SVAL_SHADOW -#define R_DMA_CH9_FIRST__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH9_FIRST__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH9_FIRST__TYPE (REG_UDWORD) -#define R_DMA_CH9_FIRST__GET REG_GET_RW -#define R_DMA_CH9_FIRST__IGET REG_IGET_RW -#define R_DMA_CH9_FIRST__SET REG_SET_RW -#define R_DMA_CH9_FIRST__ISET REG_ISET_RW -#define R_DMA_CH9_FIRST__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH9_FIRST__EQL REG_EQL_RW -#define R_DMA_CH9_FIRST__IEQL REG_IEQL_RW -#define R_DMA_CH9_FIRST__RD REG_RD_RW -#define R_DMA_CH9_FIRST__IRD REG_IRD_RW -#define R_DMA_CH9_FIRST__WR REG_WR_RW -#define R_DMA_CH9_FIRST__IWR REG_IWR_RW - -#define R_DMA_CH9_FIRST__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH9_FIRST__READ(addr) \ - (*(addr)) - -#define R_DMA_CH9_FIRST__first__first__MASK 0xffffffffU - -#define R_DMA_CH9_FIRST__first__MAX 0xffffffff - -#define R_DMA_CH9_FIRST__first__MIN 0 - -#define R_DMA_CH9_FIRST__first__BITNR 0 - -#define R_DMA_CH9_FIRST__first__first__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH9_HWSW - * - type: RW - * - addr: 0xb0000190 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH9_HWSW__ADDR (REG_TYPECAST_UDWORD 0xb0000190) -#define R_DMA_CH9_HWSW__SVAL REG_SVAL_SHADOW -#define R_DMA_CH9_HWSW__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH9_HWSW__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH9_HWSW__TYPE (REG_UDWORD) -#define R_DMA_CH9_HWSW__GET REG_GET_RW -#define R_DMA_CH9_HWSW__IGET REG_IGET_RW -#define R_DMA_CH9_HWSW__SET REG_SET_RW -#define R_DMA_CH9_HWSW__ISET REG_ISET_RW -#define R_DMA_CH9_HWSW__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH9_HWSW__EQL REG_EQL_RW -#define R_DMA_CH9_HWSW__IEQL REG_IEQL_RW -#define R_DMA_CH9_HWSW__RD REG_RD_RW -#define R_DMA_CH9_HWSW__IRD REG_IRD_RW -#define R_DMA_CH9_HWSW__WR REG_WR_RW -#define R_DMA_CH9_HWSW__IWR REG_IWR_RW - -#define R_DMA_CH9_HWSW__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH9_HWSW__READ(addr) \ - (*(addr)) - -#define R_DMA_CH9_HWSW__hw__hw__MASK 0xffff0000U -#define R_DMA_CH9_HWSW__sw__sw__MASK 0x0000ffffU - -#define R_DMA_CH9_HWSW__hw__MAX 0xffff -#define R_DMA_CH9_HWSW__sw__MAX 0xffff - -#define R_DMA_CH9_HWSW__hw__MIN 0 -#define R_DMA_CH9_HWSW__sw__MIN 0 - -#define R_DMA_CH9_HWSW__hw__BITNR 16 -#define R_DMA_CH9_HWSW__sw__BITNR 0 - -#define R_DMA_CH9_HWSW__hw__hw__VAL REG_VAL_VAL -#define R_DMA_CH9_HWSW__sw__sw__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH9_NEXT - * - type: RW - * - addr: 0xb0000194 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH9_NEXT__ADDR (REG_TYPECAST_UDWORD 0xb0000194) -#define R_DMA_CH9_NEXT__SVAL REG_SVAL_SHADOW -#define R_DMA_CH9_NEXT__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH9_NEXT__TYPECAST REG_TYPECAST_UDWORD -#define R_DMA_CH9_NEXT__TYPE (REG_UDWORD) -#define R_DMA_CH9_NEXT__GET REG_GET_RW -#define R_DMA_CH9_NEXT__IGET REG_IGET_RW -#define R_DMA_CH9_NEXT__SET REG_SET_RW -#define R_DMA_CH9_NEXT__ISET REG_ISET_RW -#define R_DMA_CH9_NEXT__SET_VAL REG_SET_VAL_RW -#define R_DMA_CH9_NEXT__EQL REG_EQL_RW -#define R_DMA_CH9_NEXT__IEQL REG_IEQL_RW -#define R_DMA_CH9_NEXT__RD REG_RD_RW -#define R_DMA_CH9_NEXT__IRD REG_IRD_RW -#define R_DMA_CH9_NEXT__WR REG_WR_RW -#define R_DMA_CH9_NEXT__IWR REG_IWR_RW - -#define R_DMA_CH9_NEXT__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_DMA_CH9_NEXT__READ(addr) \ - (*(addr)) - -#define R_DMA_CH9_NEXT__next__next__MASK 0xffffffffU - -#define R_DMA_CH9_NEXT__next__MAX 0xffffffff - -#define R_DMA_CH9_NEXT__next__MIN 0 - -#define R_DMA_CH9_NEXT__next__BITNR 0 - -#define R_DMA_CH9_NEXT__next__next__VAL REG_VAL_VAL - - -#endif - -/* - * R_DMA_CH9_STATUS - * - type: RO - * - addr: 0xb00001f6 - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_DMA_CH9_STATUS__ADDR (REG_TYPECAST_BYTE 0xb00001f6) -#define R_DMA_CH9_STATUS__SVAL REG_SVAL_SHADOW -#define R_DMA_CH9_STATUS__SVAL_I REG_SVAL_I_SHADOW -#define R_DMA_CH9_STATUS__TYPECAST REG_TYPECAST_BYTE -#define R_DMA_CH9_STATUS__TYPE (REG_BYTE) -#define R_DMA_CH9_STATUS__GET REG_GET_RO -#define R_DMA_CH9_STATUS__IGET REG_IGET_RO -#define R_DMA_CH9_STATUS__SET REG_SET_RO -#define R_DMA_CH9_STATUS__ISET REG_ISET_RO -#define R_DMA_CH9_STATUS__SET_VAL REG_SET_VAL_RO -#define R_DMA_CH9_STATUS__EQL REG_EQL_RO -#define R_DMA_CH9_STATUS__IEQL REG_IEQL_RO -#define R_DMA_CH9_STATUS__RD REG_RD_RO -#define R_DMA_CH9_STATUS__IRD REG_IRD_RO -#define R_DMA_CH9_STATUS__WR REG_WR_RO -#define R_DMA_CH9_STATUS__IWR REG_IWR_RO - -#define R_DMA_CH9_STATUS__READ(addr) \ - (*(addr)) - -#define R_DMA_CH9_STATUS__avail__avail__MASK 0x0000007fU - -#define R_DMA_CH9_STATUS__avail__MAX 0x7f - -#define R_DMA_CH9_STATUS__avail__MIN 0 - -#define R_DMA_CH9_STATUS__avail__BITNR 0 - -#define R_DMA_CH9_STATUS__avail__avail__VAL REG_VAL_VAL - - -#endif - -/* - * R_DRAM_CONFIG - * - type: WO - * - addr: 0xb000000c - * - group: Bus interface configuration registers - */ - -#if USE_GROUP__Bus_interface_configuration_registers - -#define R_DRAM_CONFIG__ADDR (REG_TYPECAST_UDWORD 0xb000000c) - -#ifndef REG_NO_SHADOW -#define R_DRAM_CONFIG__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_DRAM_CONFIG + 0)) -#define R_DRAM_CONFIG__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_DRAM_CONFIG + 0)) -#else /* REG_NO_SHADOW */ -#define R_DRAM_CONFIG__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_DRAM_CONFIG__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_DRAM_CONFIG__STYPECAST REG_STYPECAST_UDWORD -#define R_DRAM_CONFIG__SVAL REG_SVAL_SHADOW -#define R_DRAM_CONFIG__SVAL_I REG_SVAL_I_SHADOW -#define R_DRAM_CONFIG__TYPECAST REG_TYPECAST_UDWORD -#define R_DRAM_CONFIG__TYPE (REG_UDWORD) -#define R_DRAM_CONFIG__GET REG_GET_WO -#define R_DRAM_CONFIG__IGET REG_IGET_WO -#define R_DRAM_CONFIG__SET REG_SET_WO -#define R_DRAM_CONFIG__ISET REG_ISET_WO -#define R_DRAM_CONFIG__SET_VAL REG_SET_VAL_WO -#define R_DRAM_CONFIG__EQL REG_EQL_WO -#define R_DRAM_CONFIG__IEQL REG_IEQL_WO -#define R_DRAM_CONFIG__RD REG_RD_WO -#define R_DRAM_CONFIG__IRD REG_IRD_WO -#define R_DRAM_CONFIG__WR REG_WR_WO -#define R_DRAM_CONFIG__IWR REG_IWR_WO - -#define R_DRAM_CONFIG__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_DRAM_CONFIG__wmm1__wmm1__MASK 0x80000000U -#define R_DRAM_CONFIG__wmm0__wmm0__MASK 0x40000000U -#define R_DRAM_CONFIG__sh1__sh1__MASK 0x38000000U -#define R_DRAM_CONFIG__sh0__sh0__MASK 0x07000000U -#define R_DRAM_CONFIG__w__w__MASK 0x00800000U -#define R_DRAM_CONFIG__c__c__MASK 0x00400000U -#define R_DRAM_CONFIG__e__e__MASK 0x00200000U -#define R_DRAM_CONFIG__group_sel__group_sel__MASK 0x001f0000U -#define R_DRAM_CONFIG__ca1__ca1__MASK 0x0000e000U -#define R_DRAM_CONFIG__bank23sel__bank23sel__MASK 0x00001f00U -#define R_DRAM_CONFIG__ca0__ca0__MASK 0x000000e0U -#define R_DRAM_CONFIG__bank01sel__bank01sel__MASK 0x0000001fU - -#define R_DRAM_CONFIG__wmm1__MAX 0x1 -#define R_DRAM_CONFIG__wmm0__MAX 0x1 -#define R_DRAM_CONFIG__sh1__MAX 7 -#define R_DRAM_CONFIG__sh0__MAX 7 -#define R_DRAM_CONFIG__w__MAX 0x1 -#define R_DRAM_CONFIG__c__MAX 0x1 -#define R_DRAM_CONFIG__e__MAX 0x1 -#define R_DRAM_CONFIG__group_sel__MAX 0x1f -#define R_DRAM_CONFIG__ca1__MAX 7 -#define R_DRAM_CONFIG__bank23sel__MAX 0x1f -#define R_DRAM_CONFIG__ca0__MAX 7 -#define R_DRAM_CONFIG__bank01sel__MAX 0x1f - -#define R_DRAM_CONFIG__wmm1__MIN 0 -#define R_DRAM_CONFIG__wmm0__MIN 0 -#define R_DRAM_CONFIG__sh1__MIN 0 -#define R_DRAM_CONFIG__sh0__MIN 0 -#define R_DRAM_CONFIG__w__MIN 0 -#define R_DRAM_CONFIG__c__MIN 0 -#define R_DRAM_CONFIG__e__MIN 0 -#define R_DRAM_CONFIG__group_sel__MIN 0 -#define R_DRAM_CONFIG__ca1__MIN 0 -#define R_DRAM_CONFIG__bank23sel__MIN 0 -#define R_DRAM_CONFIG__ca0__MIN 0 -#define R_DRAM_CONFIG__bank01sel__MIN 0 - -#define R_DRAM_CONFIG__wmm1__BITNR 31 -#define R_DRAM_CONFIG__wmm0__BITNR 30 -#define R_DRAM_CONFIG__sh1__BITNR 27 -#define R_DRAM_CONFIG__sh0__BITNR 24 -#define R_DRAM_CONFIG__w__BITNR 23 -#define R_DRAM_CONFIG__c__BITNR 22 -#define R_DRAM_CONFIG__e__BITNR 21 -#define R_DRAM_CONFIG__group_sel__BITNR 16 -#define R_DRAM_CONFIG__ca1__BITNR 13 -#define R_DRAM_CONFIG__bank23sel__BITNR 8 -#define R_DRAM_CONFIG__ca0__BITNR 5 -#define R_DRAM_CONFIG__bank01sel__BITNR 0 - -#define R_DRAM_CONFIG__wmm1__wmm1__VAL REG_VAL_ENUM -#define R_DRAM_CONFIG__wmm0__wmm0__VAL REG_VAL_ENUM -#define R_DRAM_CONFIG__sh1__sh1__VAL REG_VAL_VAL -#define R_DRAM_CONFIG__sh0__sh0__VAL REG_VAL_VAL -#define R_DRAM_CONFIG__w__w__VAL REG_VAL_ENUM -#define R_DRAM_CONFIG__c__c__VAL REG_VAL_ENUM -#define R_DRAM_CONFIG__e__e__VAL REG_VAL_ENUM -#define R_DRAM_CONFIG__group_sel__group_sel__VAL REG_VAL_ENUM -#define R_DRAM_CONFIG__ca1__ca1__VAL REG_VAL_VAL -#define R_DRAM_CONFIG__bank23sel__bank23sel__VAL REG_VAL_ENUM -#define R_DRAM_CONFIG__ca0__ca0__VAL REG_VAL_VAL -#define R_DRAM_CONFIG__bank01sel__bank01sel__VAL REG_VAL_ENUM - -#define R_DRAM_CONFIG__wmm1__wmm1__norm 0 -#define R_DRAM_CONFIG__wmm1__wmm1__wmm 1 -#define R_DRAM_CONFIG__wmm0__wmm0__norm 0 -#define R_DRAM_CONFIG__wmm0__wmm0__wmm 1 -#define R_DRAM_CONFIG__w__w__bw16 0 -#define R_DRAM_CONFIG__w__w__bw32 1 -#define R_DRAM_CONFIG__c__c__bank 1 -#define R_DRAM_CONFIG__c__c__byte 0 -#define R_DRAM_CONFIG__e__e__edo 1 -#define R_DRAM_CONFIG__e__e__fast 0 -#define R_DRAM_CONFIG__group_sel__group_sel__bit10 10 -#define R_DRAM_CONFIG__group_sel__group_sel__bit11 11 -#define R_DRAM_CONFIG__group_sel__group_sel__bit12 12 -#define R_DRAM_CONFIG__group_sel__group_sel__bit13 13 -#define R_DRAM_CONFIG__group_sel__group_sel__bit14 14 -#define R_DRAM_CONFIG__group_sel__group_sel__bit15 15 -#define R_DRAM_CONFIG__group_sel__group_sel__bit16 16 -#define R_DRAM_CONFIG__group_sel__group_sel__bit17 17 -#define R_DRAM_CONFIG__group_sel__group_sel__bit18 18 -#define R_DRAM_CONFIG__group_sel__group_sel__bit19 19 -#define R_DRAM_CONFIG__group_sel__group_sel__bit20 20 -#define R_DRAM_CONFIG__group_sel__group_sel__bit21 21 -#define R_DRAM_CONFIG__group_sel__group_sel__bit22 22 -#define R_DRAM_CONFIG__group_sel__group_sel__bit23 23 -#define R_DRAM_CONFIG__group_sel__group_sel__bit24 24 -#define R_DRAM_CONFIG__group_sel__group_sel__bit25 25 -#define R_DRAM_CONFIG__group_sel__group_sel__bit26 26 -#define R_DRAM_CONFIG__group_sel__group_sel__bit27 27 -#define R_DRAM_CONFIG__group_sel__group_sel__bit28 28 -#define R_DRAM_CONFIG__group_sel__group_sel__bit29 29 -#define R_DRAM_CONFIG__group_sel__group_sel__bit9 9 -#define R_DRAM_CONFIG__group_sel__group_sel__grp0 0 -#define R_DRAM_CONFIG__group_sel__group_sel__grp1 1 -#define R_DRAM_CONFIG__bank23sel__bank23sel__bank0 0 -#define R_DRAM_CONFIG__bank23sel__bank23sel__bank1 1 -#define R_DRAM_CONFIG__bank23sel__bank23sel__bit10 10 -#define R_DRAM_CONFIG__bank23sel__bank23sel__bit11 11 -#define R_DRAM_CONFIG__bank23sel__bank23sel__bit12 12 -#define R_DRAM_CONFIG__bank23sel__bank23sel__bit13 13 -#define R_DRAM_CONFIG__bank23sel__bank23sel__bit14 14 -#define R_DRAM_CONFIG__bank23sel__bank23sel__bit15 15 -#define R_DRAM_CONFIG__bank23sel__bank23sel__bit16 16 -#define R_DRAM_CONFIG__bank23sel__bank23sel__bit17 17 -#define R_DRAM_CONFIG__bank23sel__bank23sel__bit18 18 -#define R_DRAM_CONFIG__bank23sel__bank23sel__bit19 19 -#define R_DRAM_CONFIG__bank23sel__bank23sel__bit20 20 -#define R_DRAM_CONFIG__bank23sel__bank23sel__bit21 21 -#define R_DRAM_CONFIG__bank23sel__bank23sel__bit22 22 -#define R_DRAM_CONFIG__bank23sel__bank23sel__bit23 23 -#define R_DRAM_CONFIG__bank23sel__bank23sel__bit24 24 -#define R_DRAM_CONFIG__bank23sel__bank23sel__bit25 25 -#define R_DRAM_CONFIG__bank23sel__bank23sel__bit26 26 -#define R_DRAM_CONFIG__bank23sel__bank23sel__bit27 27 -#define R_DRAM_CONFIG__bank23sel__bank23sel__bit28 28 -#define R_DRAM_CONFIG__bank23sel__bank23sel__bit29 29 -#define R_DRAM_CONFIG__bank23sel__bank23sel__bit9 9 -#define R_DRAM_CONFIG__bank01sel__bank01sel__bank0 0 -#define R_DRAM_CONFIG__bank01sel__bank01sel__bank1 1 -#define R_DRAM_CONFIG__bank01sel__bank01sel__bit10 10 -#define R_DRAM_CONFIG__bank01sel__bank01sel__bit11 11 -#define R_DRAM_CONFIG__bank01sel__bank01sel__bit12 12 -#define R_DRAM_CONFIG__bank01sel__bank01sel__bit13 13 -#define R_DRAM_CONFIG__bank01sel__bank01sel__bit14 14 -#define R_DRAM_CONFIG__bank01sel__bank01sel__bit15 15 -#define R_DRAM_CONFIG__bank01sel__bank01sel__bit16 16 -#define R_DRAM_CONFIG__bank01sel__bank01sel__bit17 17 -#define R_DRAM_CONFIG__bank01sel__bank01sel__bit18 18 -#define R_DRAM_CONFIG__bank01sel__bank01sel__bit19 19 -#define R_DRAM_CONFIG__bank01sel__bank01sel__bit20 20 -#define R_DRAM_CONFIG__bank01sel__bank01sel__bit21 21 -#define R_DRAM_CONFIG__bank01sel__bank01sel__bit22 22 -#define R_DRAM_CONFIG__bank01sel__bank01sel__bit23 23 -#define R_DRAM_CONFIG__bank01sel__bank01sel__bit24 24 -#define R_DRAM_CONFIG__bank01sel__bank01sel__bit25 25 -#define R_DRAM_CONFIG__bank01sel__bank01sel__bit26 26 -#define R_DRAM_CONFIG__bank01sel__bank01sel__bit27 27 -#define R_DRAM_CONFIG__bank01sel__bank01sel__bit28 28 -#define R_DRAM_CONFIG__bank01sel__bank01sel__bit29 29 -#define R_DRAM_CONFIG__bank01sel__bank01sel__bit9 9 - -#endif - -/* - * R_DRAM_TIMING - * - type: WO - * - addr: 0xb0000008 - * - group: Bus interface configuration registers - */ - -#if USE_GROUP__Bus_interface_configuration_registers - -#define R_DRAM_TIMING__ADDR (REG_TYPECAST_UDWORD 0xb0000008) - -#ifndef REG_NO_SHADOW -#define R_DRAM_TIMING__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_DRAM_TIMING + 0)) -#define R_DRAM_TIMING__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_DRAM_TIMING + 0)) -#else /* REG_NO_SHADOW */ -#define R_DRAM_TIMING__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_DRAM_TIMING__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_DRAM_TIMING__STYPECAST REG_STYPECAST_UDWORD -#define R_DRAM_TIMING__SVAL REG_SVAL_SHADOW -#define R_DRAM_TIMING__SVAL_I REG_SVAL_I_SHADOW -#define R_DRAM_TIMING__TYPECAST REG_TYPECAST_UDWORD -#define R_DRAM_TIMING__TYPE (REG_UDWORD) -#define R_DRAM_TIMING__GET REG_GET_WO -#define R_DRAM_TIMING__IGET REG_IGET_WO -#define R_DRAM_TIMING__SET REG_SET_WO -#define R_DRAM_TIMING__ISET REG_ISET_WO -#define R_DRAM_TIMING__SET_VAL REG_SET_VAL_WO -#define R_DRAM_TIMING__EQL REG_EQL_WO -#define R_DRAM_TIMING__IEQL REG_IEQL_WO -#define R_DRAM_TIMING__RD REG_RD_WO -#define R_DRAM_TIMING__IRD REG_IRD_WO -#define R_DRAM_TIMING__WR REG_WR_WO -#define R_DRAM_TIMING__IWR REG_IWR_WO - -#define R_DRAM_TIMING__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_DRAM_TIMING__sdram__sdram__MASK 0x80000000U -#define R_DRAM_TIMING__ref__ref__MASK 0x0000c000U -#define R_DRAM_TIMING__rp__rp__MASK 0x00003000U -#define R_DRAM_TIMING__rs__rs__MASK 0x00000c00U -#define R_DRAM_TIMING__rh__rh__MASK 0x00000300U -#define R_DRAM_TIMING__w__w__MASK 0x00000080U -#define R_DRAM_TIMING__c__c__MASK 0x00000040U -#define R_DRAM_TIMING__cz__cz__MASK 0x00000030U -#define R_DRAM_TIMING__cp__cp__MASK 0x0000000cU -#define R_DRAM_TIMING__cw__cw__MASK 0x00000003U - -#define R_DRAM_TIMING__sdram__MAX 0x1 -#define R_DRAM_TIMING__ref__MAX 0x3 -#define R_DRAM_TIMING__rp__MAX 3 -#define R_DRAM_TIMING__rs__MAX 3 -#define R_DRAM_TIMING__rh__MAX 3 -#define R_DRAM_TIMING__w__MAX 0x1 -#define R_DRAM_TIMING__c__MAX 0x1 -#define R_DRAM_TIMING__cz__MAX 3 -#define R_DRAM_TIMING__cp__MAX 3 -#define R_DRAM_TIMING__cw__MAX 3 - -#define R_DRAM_TIMING__sdram__MIN 0 -#define R_DRAM_TIMING__ref__MIN 0 -#define R_DRAM_TIMING__rp__MIN 0 -#define R_DRAM_TIMING__rs__MIN 0 -#define R_DRAM_TIMING__rh__MIN 0 -#define R_DRAM_TIMING__w__MIN 0 -#define R_DRAM_TIMING__c__MIN 0 -#define R_DRAM_TIMING__cz__MIN 0 -#define R_DRAM_TIMING__cp__MIN 0 -#define R_DRAM_TIMING__cw__MIN 0 - -#define R_DRAM_TIMING__sdram__BITNR 31 -#define R_DRAM_TIMING__ref__BITNR 14 -#define R_DRAM_TIMING__rp__BITNR 12 -#define R_DRAM_TIMING__rs__BITNR 10 -#define R_DRAM_TIMING__rh__BITNR 8 -#define R_DRAM_TIMING__w__BITNR 7 -#define R_DRAM_TIMING__c__BITNR 6 -#define R_DRAM_TIMING__cz__BITNR 4 -#define R_DRAM_TIMING__cp__BITNR 2 -#define R_DRAM_TIMING__cw__BITNR 0 - -#define R_DRAM_TIMING__sdram__sdram__VAL REG_VAL_ENUM -#define R_DRAM_TIMING__ref__ref__VAL REG_VAL_ENUM -#define R_DRAM_TIMING__rp__rp__VAL REG_VAL_VAL -#define R_DRAM_TIMING__rs__rs__VAL REG_VAL_VAL -#define R_DRAM_TIMING__rh__rh__VAL REG_VAL_VAL -#define R_DRAM_TIMING__w__w__VAL REG_VAL_ENUM -#define R_DRAM_TIMING__c__c__VAL REG_VAL_ENUM -#define R_DRAM_TIMING__cz__cz__VAL REG_VAL_VAL -#define R_DRAM_TIMING__cp__cp__VAL REG_VAL_VAL -#define R_DRAM_TIMING__cw__cw__VAL REG_VAL_VAL - -#define R_DRAM_TIMING__sdram__sdram__disable 0 -#define R_DRAM_TIMING__sdram__sdram__enable 1 -#define R_DRAM_TIMING__ref__ref__disable 3 -#define R_DRAM_TIMING__ref__ref__e13us 1 -#define R_DRAM_TIMING__ref__ref__e52us 0 -#define R_DRAM_TIMING__ref__ref__e8700ns 2 -#define R_DRAM_TIMING__w__w__ext 1 -#define R_DRAM_TIMING__w__w__norm 0 -#define R_DRAM_TIMING__c__c__ext 1 -#define R_DRAM_TIMING__c__c__norm 0 - -#endif - -/* - * R_EXT_DMA_0_ADDR - * - type: WO - * - addr: 0xb0000014 - * - group: External DMA registers - */ - -#if USE_GROUP__External_DMA_registers - -#define R_EXT_DMA_0_ADDR__ADDR (REG_TYPECAST_UDWORD 0xb0000014) - -#ifndef REG_NO_SHADOW -#define R_EXT_DMA_0_ADDR__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_EXT_DMA_0_ADDR + 0)) -#define R_EXT_DMA_0_ADDR__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_EXT_DMA_0_ADDR + 0)) -#else /* REG_NO_SHADOW */ -#define R_EXT_DMA_0_ADDR__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_EXT_DMA_0_ADDR__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_EXT_DMA_0_ADDR__STYPECAST REG_STYPECAST_UDWORD -#define R_EXT_DMA_0_ADDR__SVAL REG_SVAL_SHADOW -#define R_EXT_DMA_0_ADDR__SVAL_I REG_SVAL_I_SHADOW -#define R_EXT_DMA_0_ADDR__TYPECAST REG_TYPECAST_UDWORD -#define R_EXT_DMA_0_ADDR__TYPE (REG_UDWORD) -#define R_EXT_DMA_0_ADDR__GET REG_GET_WO -#define R_EXT_DMA_0_ADDR__IGET REG_IGET_WO -#define R_EXT_DMA_0_ADDR__SET REG_SET_WO -#define R_EXT_DMA_0_ADDR__ISET REG_ISET_WO -#define R_EXT_DMA_0_ADDR__SET_VAL REG_SET_VAL_WO -#define R_EXT_DMA_0_ADDR__EQL REG_EQL_WO -#define R_EXT_DMA_0_ADDR__IEQL REG_IEQL_WO -#define R_EXT_DMA_0_ADDR__RD REG_RD_WO -#define R_EXT_DMA_0_ADDR__IRD REG_IRD_WO -#define R_EXT_DMA_0_ADDR__WR REG_WR_WO -#define R_EXT_DMA_0_ADDR__IWR REG_IWR_WO - -#define R_EXT_DMA_0_ADDR__WRITE(addr,value) \ - (*(addr) = (value)) - -/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */ -#define R_EXT_DMA_0_ADDR__FIRST 0 -#define R_EXT_DMA_0_ADDR__IOFFSET 8 -#define R_EXT_DMA_0_ADDR__LAST 1 -#define R_EXT_DMA_0_ADDR__OFFSET 8 -#define R_EXT_DMA_0_ADDR__SOFFSET 8 -/* end */ - -#define R_EXT_DMA_0_ADDR__ext0_addr__ext0_addr__MASK 0x3ffffffcU - -#define R_EXT_DMA_0_ADDR__ext0_addr__MAX 0xfffffff - -#define R_EXT_DMA_0_ADDR__ext0_addr__MIN 0 - -#define R_EXT_DMA_0_ADDR__ext0_addr__BITNR 2 - -#define R_EXT_DMA_0_ADDR__ext0_addr__ext0_addr__VAL REG_VAL_VAL - - -#endif - -/* - * R_EXT_DMA_0_CMD - * - type: WO - * - addr: 0xb0000010 - * - group: External DMA registers - */ - -#if USE_GROUP__External_DMA_registers - -#define R_EXT_DMA_0_CMD__ADDR (REG_TYPECAST_UDWORD 0xb0000010) - -#ifndef REG_NO_SHADOW -#define R_EXT_DMA_0_CMD__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_EXT_DMA_0_CMD + 0)) -#define R_EXT_DMA_0_CMD__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_EXT_DMA_0_CMD + 0)) -#else /* REG_NO_SHADOW */ -#define R_EXT_DMA_0_CMD__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_EXT_DMA_0_CMD__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_EXT_DMA_0_CMD__STYPECAST REG_STYPECAST_UDWORD -#define R_EXT_DMA_0_CMD__SVAL REG_SVAL_SHADOW -#define R_EXT_DMA_0_CMD__SVAL_I REG_SVAL_I_SHADOW -#define R_EXT_DMA_0_CMD__TYPECAST REG_TYPECAST_UDWORD -#define R_EXT_DMA_0_CMD__TYPE (REG_UDWORD) -#define R_EXT_DMA_0_CMD__GET REG_GET_WO -#define R_EXT_DMA_0_CMD__IGET REG_IGET_WO -#define R_EXT_DMA_0_CMD__SET REG_SET_WO -#define R_EXT_DMA_0_CMD__ISET REG_ISET_WO -#define R_EXT_DMA_0_CMD__SET_VAL REG_SET_VAL_WO -#define R_EXT_DMA_0_CMD__EQL REG_EQL_WO -#define R_EXT_DMA_0_CMD__IEQL REG_IEQL_WO -#define R_EXT_DMA_0_CMD__RD REG_RD_WO -#define R_EXT_DMA_0_CMD__IRD REG_IRD_WO -#define R_EXT_DMA_0_CMD__WR REG_WR_WO -#define R_EXT_DMA_0_CMD__IWR REG_IWR_WO - -#define R_EXT_DMA_0_CMD__WRITE(addr,value) \ - (*(addr) = (value)) - -/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */ -#define R_EXT_DMA_0_CMD__FIRST 0 -#define R_EXT_DMA_0_CMD__IOFFSET 8 -#define R_EXT_DMA_0_CMD__LAST 1 -#define R_EXT_DMA_0_CMD__OFFSET 8 -#define R_EXT_DMA_0_CMD__SOFFSET 8 -/* end */ - -#define R_EXT_DMA_0_CMD__cnt__cnt__MASK 0x00800000U -#define R_EXT_DMA_0_CMD__rqpol__rqpol__MASK 0x00400000U -#define R_EXT_DMA_0_CMD__apol__apol__MASK 0x00200000U -#define R_EXT_DMA_0_CMD__rq_ack__rq_ack__MASK 0x00100000U -#define R_EXT_DMA_0_CMD__wid__wid__MASK 0x000c0000U -#define R_EXT_DMA_0_CMD__dir__dir__MASK 0x00020000U -#define R_EXT_DMA_0_CMD__run__run__MASK 0x00010000U -#define R_EXT_DMA_0_CMD__trf_count__trf_count__MASK 0x0000ffffU - -#define R_EXT_DMA_0_CMD__cnt__MAX 0x1 -#define R_EXT_DMA_0_CMD__rqpol__MAX 0x1 -#define R_EXT_DMA_0_CMD__apol__MAX 0x1 -#define R_EXT_DMA_0_CMD__rq_ack__MAX 0x1 -#define R_EXT_DMA_0_CMD__wid__MAX 0x3 -#define R_EXT_DMA_0_CMD__dir__MAX 0x1 -#define R_EXT_DMA_0_CMD__run__MAX 0x1 -#define R_EXT_DMA_0_CMD__trf_count__MAX 0xffff - -#define R_EXT_DMA_0_CMD__cnt__MIN 0 -#define R_EXT_DMA_0_CMD__rqpol__MIN 0 -#define R_EXT_DMA_0_CMD__apol__MIN 0 -#define R_EXT_DMA_0_CMD__rq_ack__MIN 0 -#define R_EXT_DMA_0_CMD__wid__MIN 0 -#define R_EXT_DMA_0_CMD__dir__MIN 0 -#define R_EXT_DMA_0_CMD__run__MIN 0 -#define R_EXT_DMA_0_CMD__trf_count__MIN 0 - -#define R_EXT_DMA_0_CMD__cnt__BITNR 23 -#define R_EXT_DMA_0_CMD__rqpol__BITNR 22 -#define R_EXT_DMA_0_CMD__apol__BITNR 21 -#define R_EXT_DMA_0_CMD__rq_ack__BITNR 20 -#define R_EXT_DMA_0_CMD__wid__BITNR 18 -#define R_EXT_DMA_0_CMD__dir__BITNR 17 -#define R_EXT_DMA_0_CMD__run__BITNR 16 -#define R_EXT_DMA_0_CMD__trf_count__BITNR 0 - -#define R_EXT_DMA_0_CMD__cnt__cnt__VAL REG_VAL_ENUM -#define R_EXT_DMA_0_CMD__rqpol__rqpol__VAL REG_VAL_ENUM -#define R_EXT_DMA_0_CMD__apol__apol__VAL REG_VAL_ENUM -#define R_EXT_DMA_0_CMD__rq_ack__rq_ack__VAL REG_VAL_ENUM -#define R_EXT_DMA_0_CMD__wid__wid__VAL REG_VAL_ENUM -#define R_EXT_DMA_0_CMD__dir__dir__VAL REG_VAL_ENUM -#define R_EXT_DMA_0_CMD__run__run__VAL REG_VAL_ENUM -#define R_EXT_DMA_0_CMD__trf_count__trf_count__VAL REG_VAL_VAL - -#define R_EXT_DMA_0_CMD__cnt__cnt__disable 0 -#define R_EXT_DMA_0_CMD__cnt__cnt__enable 1 -#define R_EXT_DMA_0_CMD__rqpol__rqpol__ahigh 0 -#define R_EXT_DMA_0_CMD__rqpol__rqpol__alow 1 -#define R_EXT_DMA_0_CMD__apol__apol__ahigh 0 -#define R_EXT_DMA_0_CMD__apol__apol__alow 1 -#define R_EXT_DMA_0_CMD__rq_ack__rq_ack__burst 0 -#define R_EXT_DMA_0_CMD__rq_ack__rq_ack__handsh 1 -#define R_EXT_DMA_0_CMD__wid__wid__byte 0 -#define R_EXT_DMA_0_CMD__wid__wid__dword 2 -#define R_EXT_DMA_0_CMD__wid__wid__word 1 -#define R_EXT_DMA_0_CMD__dir__dir__input 0 -#define R_EXT_DMA_0_CMD__dir__dir__output 1 -#define R_EXT_DMA_0_CMD__run__run__start 1 -#define R_EXT_DMA_0_CMD__run__run__stop 0 - -#endif - -/* - * R_EXT_DMA_0_STAT - * - type: RO - * - addr: 0xb0000010 - * - group: External DMA registers - */ - -#if USE_GROUP__External_DMA_registers - -#define R_EXT_DMA_0_STAT__ADDR (REG_TYPECAST_UDWORD 0xb0000010) -#define R_EXT_DMA_0_STAT__SVAL REG_SVAL_SHADOW -#define R_EXT_DMA_0_STAT__SVAL_I REG_SVAL_I_SHADOW -#define R_EXT_DMA_0_STAT__TYPECAST REG_TYPECAST_UDWORD -#define R_EXT_DMA_0_STAT__TYPE (REG_UDWORD) -#define R_EXT_DMA_0_STAT__GET REG_GET_RO -#define R_EXT_DMA_0_STAT__IGET REG_IGET_RO -#define R_EXT_DMA_0_STAT__SET REG_SET_RO -#define R_EXT_DMA_0_STAT__ISET REG_ISET_RO -#define R_EXT_DMA_0_STAT__SET_VAL REG_SET_VAL_RO -#define R_EXT_DMA_0_STAT__EQL REG_EQL_RO -#define R_EXT_DMA_0_STAT__IEQL REG_IEQL_RO -#define R_EXT_DMA_0_STAT__RD REG_RD_RO -#define R_EXT_DMA_0_STAT__IRD REG_IRD_RO -#define R_EXT_DMA_0_STAT__WR REG_WR_RO -#define R_EXT_DMA_0_STAT__IWR REG_IWR_RO - -#define R_EXT_DMA_0_STAT__READ(addr) \ - (*(addr)) - -/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */ -#define R_EXT_DMA_0_STAT__FIRST 0 -#define R_EXT_DMA_0_STAT__LAST 1 -#define R_EXT_DMA_0_STAT__OFFSET 8 -/* end */ - -#define R_EXT_DMA_0_STAT__run__run__MASK 0x00010000U -#define R_EXT_DMA_0_STAT__trf_count__trf_count__MASK 0x0000ffffU - -#define R_EXT_DMA_0_STAT__run__MAX 0x1 -#define R_EXT_DMA_0_STAT__trf_count__MAX 0xffff - -#define R_EXT_DMA_0_STAT__run__MIN 0 -#define R_EXT_DMA_0_STAT__trf_count__MIN 0 - -#define R_EXT_DMA_0_STAT__run__BITNR 16 -#define R_EXT_DMA_0_STAT__trf_count__BITNR 0 - -#define R_EXT_DMA_0_STAT__run__run__VAL REG_VAL_ENUM -#define R_EXT_DMA_0_STAT__trf_count__trf_count__VAL REG_VAL_VAL - -#define R_EXT_DMA_0_STAT__run__run__start 1 -#define R_EXT_DMA_0_STAT__run__run__stop 0 - -#endif - -/* - * R_EXT_DMA_1_ADDR - * - type: WO - * - addr: 0xb000001c - * - group: External DMA registers - */ - -#if USE_GROUP__External_DMA_registers - -#define R_EXT_DMA_1_ADDR__ADDR (REG_TYPECAST_UDWORD 0xb000001c) - -#ifndef REG_NO_SHADOW -#define R_EXT_DMA_1_ADDR__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_EXT_DMA_1_ADDR + 0)) -#define R_EXT_DMA_1_ADDR__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_EXT_DMA_1_ADDR + 0)) -#else /* REG_NO_SHADOW */ -#define R_EXT_DMA_1_ADDR__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_EXT_DMA_1_ADDR__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_EXT_DMA_1_ADDR__STYPECAST REG_STYPECAST_UDWORD -#define R_EXT_DMA_1_ADDR__SVAL REG_SVAL_SHADOW -#define R_EXT_DMA_1_ADDR__SVAL_I REG_SVAL_I_SHADOW -#define R_EXT_DMA_1_ADDR__TYPECAST REG_TYPECAST_UDWORD -#define R_EXT_DMA_1_ADDR__TYPE (REG_UDWORD) -#define R_EXT_DMA_1_ADDR__GET REG_GET_WO -#define R_EXT_DMA_1_ADDR__IGET REG_IGET_WO -#define R_EXT_DMA_1_ADDR__SET REG_SET_WO -#define R_EXT_DMA_1_ADDR__ISET REG_ISET_WO -#define R_EXT_DMA_1_ADDR__SET_VAL REG_SET_VAL_WO -#define R_EXT_DMA_1_ADDR__EQL REG_EQL_WO -#define R_EXT_DMA_1_ADDR__IEQL REG_IEQL_WO -#define R_EXT_DMA_1_ADDR__RD REG_RD_WO -#define R_EXT_DMA_1_ADDR__IRD REG_IRD_WO -#define R_EXT_DMA_1_ADDR__WR REG_WR_WO -#define R_EXT_DMA_1_ADDR__IWR REG_IWR_WO - -#define R_EXT_DMA_1_ADDR__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_EXT_DMA_1_ADDR__ext0_addr__ext0_addr__MASK 0x3ffffffcU - -#define R_EXT_DMA_1_ADDR__ext0_addr__MAX 0xfffffff - -#define R_EXT_DMA_1_ADDR__ext0_addr__MIN 0 - -#define R_EXT_DMA_1_ADDR__ext0_addr__BITNR 2 - -#define R_EXT_DMA_1_ADDR__ext0_addr__ext0_addr__VAL REG_VAL_VAL - - -#endif - -/* - * R_EXT_DMA_1_CMD - * - type: WO - * - addr: 0xb0000018 - * - group: External DMA registers - */ - -#if USE_GROUP__External_DMA_registers - -#define R_EXT_DMA_1_CMD__ADDR (REG_TYPECAST_UDWORD 0xb0000018) - -#ifndef REG_NO_SHADOW -#define R_EXT_DMA_1_CMD__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_EXT_DMA_1_CMD + 0)) -#define R_EXT_DMA_1_CMD__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_EXT_DMA_1_CMD + 0)) -#else /* REG_NO_SHADOW */ -#define R_EXT_DMA_1_CMD__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_EXT_DMA_1_CMD__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_EXT_DMA_1_CMD__STYPECAST REG_STYPECAST_UDWORD -#define R_EXT_DMA_1_CMD__SVAL REG_SVAL_SHADOW -#define R_EXT_DMA_1_CMD__SVAL_I REG_SVAL_I_SHADOW -#define R_EXT_DMA_1_CMD__TYPECAST REG_TYPECAST_UDWORD -#define R_EXT_DMA_1_CMD__TYPE (REG_UDWORD) -#define R_EXT_DMA_1_CMD__GET REG_GET_WO -#define R_EXT_DMA_1_CMD__IGET REG_IGET_WO -#define R_EXT_DMA_1_CMD__SET REG_SET_WO -#define R_EXT_DMA_1_CMD__ISET REG_ISET_WO -#define R_EXT_DMA_1_CMD__SET_VAL REG_SET_VAL_WO -#define R_EXT_DMA_1_CMD__EQL REG_EQL_WO -#define R_EXT_DMA_1_CMD__IEQL REG_IEQL_WO -#define R_EXT_DMA_1_CMD__RD REG_RD_WO -#define R_EXT_DMA_1_CMD__IRD REG_IRD_WO -#define R_EXT_DMA_1_CMD__WR REG_WR_WO -#define R_EXT_DMA_1_CMD__IWR REG_IWR_WO - -#define R_EXT_DMA_1_CMD__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_EXT_DMA_1_CMD__cnt__cnt__MASK 0x00800000U -#define R_EXT_DMA_1_CMD__rqpol__rqpol__MASK 0x00400000U -#define R_EXT_DMA_1_CMD__apol__apol__MASK 0x00200000U -#define R_EXT_DMA_1_CMD__rq_ack__rq_ack__MASK 0x00100000U -#define R_EXT_DMA_1_CMD__wid__wid__MASK 0x000c0000U -#define R_EXT_DMA_1_CMD__dir__dir__MASK 0x00020000U -#define R_EXT_DMA_1_CMD__run__run__MASK 0x00010000U -#define R_EXT_DMA_1_CMD__trf_count__trf_count__MASK 0x0000ffffU - -#define R_EXT_DMA_1_CMD__cnt__MAX 0x1 -#define R_EXT_DMA_1_CMD__rqpol__MAX 0x1 -#define R_EXT_DMA_1_CMD__apol__MAX 0x1 -#define R_EXT_DMA_1_CMD__rq_ack__MAX 0x1 -#define R_EXT_DMA_1_CMD__wid__MAX 0x3 -#define R_EXT_DMA_1_CMD__dir__MAX 0x1 -#define R_EXT_DMA_1_CMD__run__MAX 0x1 -#define R_EXT_DMA_1_CMD__trf_count__MAX 0xffff - -#define R_EXT_DMA_1_CMD__cnt__MIN 0 -#define R_EXT_DMA_1_CMD__rqpol__MIN 0 -#define R_EXT_DMA_1_CMD__apol__MIN 0 -#define R_EXT_DMA_1_CMD__rq_ack__MIN 0 -#define R_EXT_DMA_1_CMD__wid__MIN 0 -#define R_EXT_DMA_1_CMD__dir__MIN 0 -#define R_EXT_DMA_1_CMD__run__MIN 0 -#define R_EXT_DMA_1_CMD__trf_count__MIN 0 - -#define R_EXT_DMA_1_CMD__cnt__BITNR 23 -#define R_EXT_DMA_1_CMD__rqpol__BITNR 22 -#define R_EXT_DMA_1_CMD__apol__BITNR 21 -#define R_EXT_DMA_1_CMD__rq_ack__BITNR 20 -#define R_EXT_DMA_1_CMD__wid__BITNR 18 -#define R_EXT_DMA_1_CMD__dir__BITNR 17 -#define R_EXT_DMA_1_CMD__run__BITNR 16 -#define R_EXT_DMA_1_CMD__trf_count__BITNR 0 - -#define R_EXT_DMA_1_CMD__cnt__cnt__VAL REG_VAL_ENUM -#define R_EXT_DMA_1_CMD__rqpol__rqpol__VAL REG_VAL_ENUM -#define R_EXT_DMA_1_CMD__apol__apol__VAL REG_VAL_ENUM -#define R_EXT_DMA_1_CMD__rq_ack__rq_ack__VAL REG_VAL_ENUM -#define R_EXT_DMA_1_CMD__wid__wid__VAL REG_VAL_ENUM -#define R_EXT_DMA_1_CMD__dir__dir__VAL REG_VAL_ENUM -#define R_EXT_DMA_1_CMD__run__run__VAL REG_VAL_ENUM -#define R_EXT_DMA_1_CMD__trf_count__trf_count__VAL REG_VAL_VAL - -#define R_EXT_DMA_1_CMD__cnt__cnt__disable 0 -#define R_EXT_DMA_1_CMD__cnt__cnt__enable 1 -#define R_EXT_DMA_1_CMD__rqpol__rqpol__ahigh 0 -#define R_EXT_DMA_1_CMD__rqpol__rqpol__alow 1 -#define R_EXT_DMA_1_CMD__apol__apol__ahigh 0 -#define R_EXT_DMA_1_CMD__apol__apol__alow 1 -#define R_EXT_DMA_1_CMD__rq_ack__rq_ack__burst 0 -#define R_EXT_DMA_1_CMD__rq_ack__rq_ack__handsh 1 -#define R_EXT_DMA_1_CMD__wid__wid__byte 0 -#define R_EXT_DMA_1_CMD__wid__wid__dword 2 -#define R_EXT_DMA_1_CMD__wid__wid__word 1 -#define R_EXT_DMA_1_CMD__dir__dir__input 0 -#define R_EXT_DMA_1_CMD__dir__dir__output 1 -#define R_EXT_DMA_1_CMD__run__run__start 1 -#define R_EXT_DMA_1_CMD__run__run__stop 0 - -#endif - -/* - * R_EXT_DMA_1_STAT - * - type: RO - * - addr: 0xb0000018 - * - group: External DMA registers - */ - -#if USE_GROUP__External_DMA_registers - -#define R_EXT_DMA_1_STAT__ADDR (REG_TYPECAST_UDWORD 0xb0000018) -#define R_EXT_DMA_1_STAT__SVAL REG_SVAL_SHADOW -#define R_EXT_DMA_1_STAT__SVAL_I REG_SVAL_I_SHADOW -#define R_EXT_DMA_1_STAT__TYPECAST REG_TYPECAST_UDWORD -#define R_EXT_DMA_1_STAT__TYPE (REG_UDWORD) -#define R_EXT_DMA_1_STAT__GET REG_GET_RO -#define R_EXT_DMA_1_STAT__IGET REG_IGET_RO -#define R_EXT_DMA_1_STAT__SET REG_SET_RO -#define R_EXT_DMA_1_STAT__ISET REG_ISET_RO -#define R_EXT_DMA_1_STAT__SET_VAL REG_SET_VAL_RO -#define R_EXT_DMA_1_STAT__EQL REG_EQL_RO -#define R_EXT_DMA_1_STAT__IEQL REG_IEQL_RO -#define R_EXT_DMA_1_STAT__RD REG_RD_RO -#define R_EXT_DMA_1_STAT__IRD REG_IRD_RO -#define R_EXT_DMA_1_STAT__WR REG_WR_RO -#define R_EXT_DMA_1_STAT__IWR REG_IWR_RO - -#define R_EXT_DMA_1_STAT__READ(addr) \ - (*(addr)) - -#define R_EXT_DMA_1_STAT__run__run__MASK 0x00010000U -#define R_EXT_DMA_1_STAT__trf_count__trf_count__MASK 0x0000ffffU - -#define R_EXT_DMA_1_STAT__run__MAX 0x1 -#define R_EXT_DMA_1_STAT__trf_count__MAX 0xffff - -#define R_EXT_DMA_1_STAT__run__MIN 0 -#define R_EXT_DMA_1_STAT__trf_count__MIN 0 - -#define R_EXT_DMA_1_STAT__run__BITNR 16 -#define R_EXT_DMA_1_STAT__trf_count__BITNR 0 - -#define R_EXT_DMA_1_STAT__run__run__VAL REG_VAL_ENUM -#define R_EXT_DMA_1_STAT__trf_count__trf_count__VAL REG_VAL_VAL - -#define R_EXT_DMA_1_STAT__run__run__start 1 -#define R_EXT_DMA_1_STAT__run__run__stop 0 - -#endif - -/* - * R_GEN_CONFIG - * - type: WO - * - addr: 0xb000002c - * - group: General config registers - */ - -#if USE_GROUP__General_config_registers - -#define R_GEN_CONFIG__ADDR (REG_TYPECAST_UDWORD 0xb000002c) - -#ifndef REG_NO_SHADOW -#define R_GEN_CONFIG__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_GEN_CONFIG + 0)) -#define R_GEN_CONFIG__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_GEN_CONFIG + 0)) -#else /* REG_NO_SHADOW */ -#define R_GEN_CONFIG__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_GEN_CONFIG__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_GEN_CONFIG__STYPECAST REG_STYPECAST_UDWORD -#define R_GEN_CONFIG__SVAL REG_SVAL_SHADOW -#define R_GEN_CONFIG__SVAL_I REG_SVAL_I_SHADOW -#define R_GEN_CONFIG__TYPECAST REG_TYPECAST_UDWORD -#define R_GEN_CONFIG__TYPE (REG_UDWORD) -#define R_GEN_CONFIG__GET REG_GET_WO -#define R_GEN_CONFIG__IGET REG_IGET_WO -#define R_GEN_CONFIG__SET REG_SET_WO -#define R_GEN_CONFIG__ISET REG_ISET_WO -#define R_GEN_CONFIG__SET_VAL REG_SET_VAL_WO -#define R_GEN_CONFIG__EQL REG_EQL_WO -#define R_GEN_CONFIG__IEQL REG_IEQL_WO -#define R_GEN_CONFIG__RD REG_RD_WO -#define R_GEN_CONFIG__IRD REG_IRD_WO -#define R_GEN_CONFIG__WR REG_WR_WO -#define R_GEN_CONFIG__IWR REG_IWR_WO - -#define R_GEN_CONFIG__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_GEN_CONFIG__par_w__par_w__MASK 0x80000000U -#define R_GEN_CONFIG__usb2__usb2__MASK 0x40000000U -#define R_GEN_CONFIG__usb1__usb1__MASK 0x20000000U -#define R_GEN_CONFIG__g24dir__g24dir__MASK 0x08000000U -#define R_GEN_CONFIG__g16_23dir__g16_23dir__MASK 0x04000000U -#define R_GEN_CONFIG__g16_20dir__g16_20dir__MASK 0x04000000U -#define R_GEN_CONFIG__g16_23dir__g16_20dir__MASK 0x04000000U -#define R_GEN_CONFIG__g8_15dir__g8_15dir__MASK 0x02000000U -#define R_GEN_CONFIG__g0dir__g0dir__MASK 0x01000000U -#define R_GEN_CONFIG__dma9__dma9__MASK 0x00800000U -#define R_GEN_CONFIG__dma8__dma8__MASK 0x00400000U -#define R_GEN_CONFIG__dma7__dma7__MASK 0x00300000U -#define R_GEN_CONFIG__dma6__dma6__MASK 0x000c0000U -#define R_GEN_CONFIG__dma5__dma5__MASK 0x00030000U -#define R_GEN_CONFIG__dma4__dma4__MASK 0x0000c000U -#define R_GEN_CONFIG__dma3__dma3__MASK 0x00003000U -#define R_GEN_CONFIG__dma2__dma2__MASK 0x00000c00U -#define R_GEN_CONFIG__mio_w__mio_w__MASK 0x00000200U -#define R_GEN_CONFIG__ser3__ser3__MASK 0x00000100U -#define R_GEN_CONFIG__par1__par1__MASK 0x00000080U -#define R_GEN_CONFIG__scsi0w__scsi0w__MASK 0x00000040U -#define R_GEN_CONFIG__scsi1__scsi1__MASK 0x00000020U -#define R_GEN_CONFIG__mio__mio__MASK 0x00000010U -#define R_GEN_CONFIG__ser2__ser2__MASK 0x00000008U -#define R_GEN_CONFIG__par0__par0__MASK 0x00000004U -#define R_GEN_CONFIG__ata__ata__MASK 0x00000002U -#define R_GEN_CONFIG__scsi0__scsi0__MASK 0x00000001U - -#define R_GEN_CONFIG__par_w__MAX 0x1 -#define R_GEN_CONFIG__usb2__MAX 0x1 -#define R_GEN_CONFIG__usb1__MAX 0x1 -#define R_GEN_CONFIG__g24dir__MAX 0x1 -#define R_GEN_CONFIG__g16_23dir__MAX 0x1 -#define R_GEN_CONFIG__g16_20dir__MAX 0x1 -#define R_GEN_CONFIG__g8_15dir__MAX 0x1 -#define R_GEN_CONFIG__g0dir__MAX 0x1 -#define R_GEN_CONFIG__dma9__MAX 0x1 -#define R_GEN_CONFIG__dma8__MAX 0x1 -#define R_GEN_CONFIG__dma7__MAX 0x3 -#define R_GEN_CONFIG__dma6__MAX 0x3 -#define R_GEN_CONFIG__dma5__MAX 0x3 -#define R_GEN_CONFIG__dma4__MAX 0x3 -#define R_GEN_CONFIG__dma3__MAX 0x3 -#define R_GEN_CONFIG__dma2__MAX 0x3 -#define R_GEN_CONFIG__mio_w__MAX 0x1 -#define R_GEN_CONFIG__ser3__MAX 0x1 -#define R_GEN_CONFIG__par1__MAX 0x1 -#define R_GEN_CONFIG__scsi0w__MAX 0x1 -#define R_GEN_CONFIG__scsi1__MAX 0x1 -#define R_GEN_CONFIG__mio__MAX 0x1 -#define R_GEN_CONFIG__ser2__MAX 0x1 -#define R_GEN_CONFIG__par0__MAX 0x1 -#define R_GEN_CONFIG__ata__MAX 0x1 -#define R_GEN_CONFIG__scsi0__MAX 0x1 - -#define R_GEN_CONFIG__par_w__MIN 0 -#define R_GEN_CONFIG__usb2__MIN 0 -#define R_GEN_CONFIG__usb1__MIN 0 -#define R_GEN_CONFIG__g24dir__MIN 0 -#define R_GEN_CONFIG__g16_23dir__MIN 0 -#define R_GEN_CONFIG__g16_20dir__MIN 0 -#define R_GEN_CONFIG__g8_15dir__MIN 0 -#define R_GEN_CONFIG__g0dir__MIN 0 -#define R_GEN_CONFIG__dma9__MIN 0 -#define R_GEN_CONFIG__dma8__MIN 0 -#define R_GEN_CONFIG__dma7__MIN 0 -#define R_GEN_CONFIG__dma6__MIN 0 -#define R_GEN_CONFIG__dma5__MIN 0 -#define R_GEN_CONFIG__dma4__MIN 0 -#define R_GEN_CONFIG__dma3__MIN 0 -#define R_GEN_CONFIG__dma2__MIN 0 -#define R_GEN_CONFIG__mio_w__MIN 0 -#define R_GEN_CONFIG__ser3__MIN 0 -#define R_GEN_CONFIG__par1__MIN 0 -#define R_GEN_CONFIG__scsi0w__MIN 0 -#define R_GEN_CONFIG__scsi1__MIN 0 -#define R_GEN_CONFIG__mio__MIN 0 -#define R_GEN_CONFIG__ser2__MIN 0 -#define R_GEN_CONFIG__par0__MIN 0 -#define R_GEN_CONFIG__ata__MIN 0 -#define R_GEN_CONFIG__scsi0__MIN 0 - -#define R_GEN_CONFIG__par_w__BITNR 31 -#define R_GEN_CONFIG__usb2__BITNR 30 -#define R_GEN_CONFIG__usb1__BITNR 29 -#define R_GEN_CONFIG__g24dir__BITNR 27 -#define R_GEN_CONFIG__g16_23dir__BITNR 26 -#define R_GEN_CONFIG__g16_20dir__BITNR 26 -#define R_GEN_CONFIG__g8_15dir__BITNR 25 -#define R_GEN_CONFIG__g0dir__BITNR 24 -#define R_GEN_CONFIG__dma9__BITNR 23 -#define R_GEN_CONFIG__dma8__BITNR 22 -#define R_GEN_CONFIG__dma7__BITNR 20 -#define R_GEN_CONFIG__dma6__BITNR 18 -#define R_GEN_CONFIG__dma5__BITNR 16 -#define R_GEN_CONFIG__dma4__BITNR 14 -#define R_GEN_CONFIG__dma3__BITNR 12 -#define R_GEN_CONFIG__dma2__BITNR 10 -#define R_GEN_CONFIG__mio_w__BITNR 9 -#define R_GEN_CONFIG__ser3__BITNR 8 -#define R_GEN_CONFIG__par1__BITNR 7 -#define R_GEN_CONFIG__scsi0w__BITNR 6 -#define R_GEN_CONFIG__scsi1__BITNR 5 -#define R_GEN_CONFIG__mio__BITNR 4 -#define R_GEN_CONFIG__ser2__BITNR 3 -#define R_GEN_CONFIG__par0__BITNR 2 -#define R_GEN_CONFIG__ata__BITNR 1 -#define R_GEN_CONFIG__scsi0__BITNR 0 - -#define R_GEN_CONFIG__par_w__par_w__VAL REG_VAL_ENUM -#define R_GEN_CONFIG__usb2__usb2__VAL REG_VAL_ENUM -#define R_GEN_CONFIG__usb1__usb1__VAL REG_VAL_ENUM -#define R_GEN_CONFIG__g24dir__g24dir__VAL REG_VAL_ENUM -#define R_GEN_CONFIG__g16_23dir__g16_23dir__VAL REG_VAL_ENUM -#define R_GEN_CONFIG__g16_20dir__g16_20dir__VAL REG_VAL_ENUM -#define R_GEN_CONFIG__g16_23dir__g16_20dir__VAL REG_VAL_ENUM -#define R_GEN_CONFIG__g8_15dir__g8_15dir__VAL REG_VAL_ENUM -#define R_GEN_CONFIG__g0dir__g0dir__VAL REG_VAL_ENUM -#define R_GEN_CONFIG__dma9__dma9__VAL REG_VAL_ENUM -#define R_GEN_CONFIG__dma8__dma8__VAL REG_VAL_ENUM -#define R_GEN_CONFIG__dma7__dma7__VAL REG_VAL_ENUM -#define R_GEN_CONFIG__dma6__dma6__VAL REG_VAL_ENUM -#define R_GEN_CONFIG__dma5__dma5__VAL REG_VAL_ENUM -#define R_GEN_CONFIG__dma4__dma4__VAL REG_VAL_ENUM -#define R_GEN_CONFIG__dma3__dma3__VAL REG_VAL_ENUM -#define R_GEN_CONFIG__dma2__dma2__VAL REG_VAL_ENUM -#define R_GEN_CONFIG__mio_w__mio_w__VAL REG_VAL_ENUM -#define R_GEN_CONFIG__ser3__ser3__VAL REG_VAL_ENUM -#define R_GEN_CONFIG__par1__par1__VAL REG_VAL_ENUM -#define R_GEN_CONFIG__scsi0w__scsi0w__VAL REG_VAL_ENUM -#define R_GEN_CONFIG__scsi1__scsi1__VAL REG_VAL_ENUM -#define R_GEN_CONFIG__mio__mio__VAL REG_VAL_ENUM -#define R_GEN_CONFIG__ser2__ser2__VAL REG_VAL_ENUM -#define R_GEN_CONFIG__par0__par0__VAL REG_VAL_ENUM -#define R_GEN_CONFIG__ata__ata__VAL REG_VAL_ENUM -#define R_GEN_CONFIG__scsi0__scsi0__VAL REG_VAL_ENUM - -#define R_GEN_CONFIG__par_w__par_w__disable 0 -#define R_GEN_CONFIG__par_w__par_w__select 1 -#define R_GEN_CONFIG__usb2__usb2__disable 0 -#define R_GEN_CONFIG__usb2__usb2__select 1 -#define R_GEN_CONFIG__usb1__usb1__disable 0 -#define R_GEN_CONFIG__usb1__usb1__select 1 -#define R_GEN_CONFIG__g24dir__g24dir__in 0 -#define R_GEN_CONFIG__g24dir__g24dir__out 1 -#define R_GEN_CONFIG__g16_23dir__g16_23dir__in 0 -#define R_GEN_CONFIG__g16_23dir__g16_23dir__out 1 -#define R_GEN_CONFIG__g16_20dir__g16_20dir__in 0 -#define R_GEN_CONFIG__g16_20dir__g16_20dir__out 1 -#define R_GEN_CONFIG__g8_15dir__g8_15dir__in 0 -#define R_GEN_CONFIG__g8_15dir__g8_15dir__out 1 -#define R_GEN_CONFIG__g0dir__g0dir__in 0 -#define R_GEN_CONFIG__g0dir__g0dir__out 1 -#define R_GEN_CONFIG__dma9__dma9__serial1 1 -#define R_GEN_CONFIG__dma9__dma9__usb 0 -#define R_GEN_CONFIG__dma8__dma8__serial1 1 -#define R_GEN_CONFIG__dma8__dma8__usb 0 -#define R_GEN_CONFIG__dma7__dma7__extdma1 2 -#define R_GEN_CONFIG__dma7__dma7__intdma6 3 -#define R_GEN_CONFIG__dma7__dma7__serial0 1 -#define R_GEN_CONFIG__dma7__dma7__unused 0 -#define R_GEN_CONFIG__dma6__dma6__extdma1 2 -#define R_GEN_CONFIG__dma6__dma6__intdma7 3 -#define R_GEN_CONFIG__dma6__dma6__serial0 1 -#define R_GEN_CONFIG__dma6__dma6__unused 0 -#define R_GEN_CONFIG__dma5__dma5__extdma0 3 -#define R_GEN_CONFIG__dma5__dma5__par1 0 -#define R_GEN_CONFIG__dma5__dma5__scsi1 1 -#define R_GEN_CONFIG__dma5__dma5__serial3 2 -#define R_GEN_CONFIG__dma4__dma4__extdma0 3 -#define R_GEN_CONFIG__dma4__dma4__par1 0 -#define R_GEN_CONFIG__dma4__dma4__scsi1 1 -#define R_GEN_CONFIG__dma4__dma4__serial3 2 -#define R_GEN_CONFIG__dma3__dma3__ata 3 -#define R_GEN_CONFIG__dma3__dma3__par0 0 -#define R_GEN_CONFIG__dma3__dma3__scsi0 1 -#define R_GEN_CONFIG__dma3__dma3__serial2 2 -#define R_GEN_CONFIG__dma2__dma2__ata 3 -#define R_GEN_CONFIG__dma2__dma2__par0 0 -#define R_GEN_CONFIG__dma2__dma2__scsi0 1 -#define R_GEN_CONFIG__dma2__dma2__serial2 2 -#define R_GEN_CONFIG__mio_w__mio_w__disable 0 -#define R_GEN_CONFIG__mio_w__mio_w__select 1 -#define R_GEN_CONFIG__ser3__ser3__disable 0 -#define R_GEN_CONFIG__ser3__ser3__select 1 -#define R_GEN_CONFIG__par1__par1__disable 0 -#define R_GEN_CONFIG__par1__par1__select 1 -#define R_GEN_CONFIG__scsi0w__scsi0w__disable 0 -#define R_GEN_CONFIG__scsi0w__scsi0w__select 1 -#define R_GEN_CONFIG__scsi1__scsi1__disable 0 -#define R_GEN_CONFIG__scsi1__scsi1__select 1 -#define R_GEN_CONFIG__mio__mio__disable 0 -#define R_GEN_CONFIG__mio__mio__select 1 -#define R_GEN_CONFIG__ser2__ser2__disable 0 -#define R_GEN_CONFIG__ser2__ser2__select 1 -#define R_GEN_CONFIG__par0__par0__disable 0 -#define R_GEN_CONFIG__par0__par0__select 1 -#define R_GEN_CONFIG__ata__ata__disable 0 -#define R_GEN_CONFIG__ata__ata__select 1 -#define R_GEN_CONFIG__scsi0__scsi0__disable 0 -#define R_GEN_CONFIG__scsi0__scsi0__select 1 - -#endif - -/* - * R_GEN_CONFIG_II - * - type: WO - * - addr: 0xb0000034 - * - group: General config registers - */ - -#if USE_GROUP__General_config_registers - -#define R_GEN_CONFIG_II__ADDR (REG_TYPECAST_UDWORD 0xb0000034) - -#ifndef REG_NO_SHADOW -#define R_GEN_CONFIG_II__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_GEN_CONFIG_II + 0)) -#define R_GEN_CONFIG_II__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_GEN_CONFIG_II + 0)) -#else /* REG_NO_SHADOW */ -#define R_GEN_CONFIG_II__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_GEN_CONFIG_II__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_GEN_CONFIG_II__STYPECAST REG_STYPECAST_UDWORD -#define R_GEN_CONFIG_II__SVAL REG_SVAL_SHADOW -#define R_GEN_CONFIG_II__SVAL_I REG_SVAL_I_SHADOW -#define R_GEN_CONFIG_II__TYPECAST REG_TYPECAST_UDWORD -#define R_GEN_CONFIG_II__TYPE (REG_UDWORD) -#define R_GEN_CONFIG_II__GET REG_GET_WO -#define R_GEN_CONFIG_II__IGET REG_IGET_WO -#define R_GEN_CONFIG_II__SET REG_SET_WO -#define R_GEN_CONFIG_II__ISET REG_ISET_WO -#define R_GEN_CONFIG_II__SET_VAL REG_SET_VAL_WO -#define R_GEN_CONFIG_II__EQL REG_EQL_WO -#define R_GEN_CONFIG_II__IEQL REG_IEQL_WO -#define R_GEN_CONFIG_II__RD REG_RD_WO -#define R_GEN_CONFIG_II__IRD REG_IRD_WO -#define R_GEN_CONFIG_II__WR REG_WR_WO -#define R_GEN_CONFIG_II__IWR REG_IWR_WO - -#define R_GEN_CONFIG_II__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_GEN_CONFIG_II__sermode3__sermode3__MASK 0x00000040U -#define R_GEN_CONFIG_II__sermode1__sermode1__MASK 0x00000010U -#define R_GEN_CONFIG_II__ext_clk__ext_clk__MASK 0x00000004U -#define R_GEN_CONFIG_II__ser3__ser3__MASK 0x00000002U -#define R_GEN_CONFIG_II__ser2__ser2__MASK 0x00000001U - -#define R_GEN_CONFIG_II__sermode3__MAX 0x1 -#define R_GEN_CONFIG_II__sermode1__MAX 0x1 -#define R_GEN_CONFIG_II__ext_clk__MAX 0x1 -#define R_GEN_CONFIG_II__ser3__MAX 0x1 -#define R_GEN_CONFIG_II__ser2__MAX 0x1 - -#define R_GEN_CONFIG_II__sermode3__MIN 0 -#define R_GEN_CONFIG_II__sermode1__MIN 0 -#define R_GEN_CONFIG_II__ext_clk__MIN 0 -#define R_GEN_CONFIG_II__ser3__MIN 0 -#define R_GEN_CONFIG_II__ser2__MIN 0 - -#define R_GEN_CONFIG_II__sermode3__BITNR 6 -#define R_GEN_CONFIG_II__sermode1__BITNR 4 -#define R_GEN_CONFIG_II__ext_clk__BITNR 2 -#define R_GEN_CONFIG_II__ser3__BITNR 1 -#define R_GEN_CONFIG_II__ser2__BITNR 0 - -#define R_GEN_CONFIG_II__sermode3__sermode3__VAL REG_VAL_ENUM -#define R_GEN_CONFIG_II__sermode1__sermode1__VAL REG_VAL_ENUM -#define R_GEN_CONFIG_II__ext_clk__ext_clk__VAL REG_VAL_ENUM -#define R_GEN_CONFIG_II__ser3__ser3__VAL REG_VAL_ENUM -#define R_GEN_CONFIG_II__ser2__ser2__VAL REG_VAL_ENUM - -#define R_GEN_CONFIG_II__sermode3__sermode3__async 0 -#define R_GEN_CONFIG_II__sermode3__sermode3__sync 1 -#define R_GEN_CONFIG_II__sermode1__sermode1__async 0 -#define R_GEN_CONFIG_II__sermode1__sermode1__sync 1 -#define R_GEN_CONFIG_II__ext_clk__ext_clk__disable 0 -#define R_GEN_CONFIG_II__ext_clk__ext_clk__select 1 -#define R_GEN_CONFIG_II__ser3__ser3__disable 0 -#define R_GEN_CONFIG_II__ser3__ser3__select 1 -#define R_GEN_CONFIG_II__ser2__ser2__disable 0 -#define R_GEN_CONFIG_II__ser2__ser2__select 1 - -#endif - -/* - * R_IRQ_MASK0_CLR - * - type: WO - * - addr: 0xb00000c0 - * - group: Interrupt mask and status registers - */ - -#if USE_GROUP__Interrupt_mask_and_status_registers - -#define R_IRQ_MASK0_CLR__ADDR (REG_TYPECAST_UDWORD 0xb00000c0) - -#ifndef REG_NO_SHADOW -#define R_IRQ_MASK0_CLR__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_IRQ_MASK0_CLR + 0)) -#define R_IRQ_MASK0_CLR__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_IRQ_MASK0_CLR + 0)) -#else /* REG_NO_SHADOW */ -#define R_IRQ_MASK0_CLR__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_IRQ_MASK0_CLR__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_IRQ_MASK0_CLR__STYPECAST REG_STYPECAST_UDWORD -#define R_IRQ_MASK0_CLR__SVAL REG_SVAL_ZERO -#define R_IRQ_MASK0_CLR__SVAL_I REG_SVAL_I_ZERO -#define R_IRQ_MASK0_CLR__TYPECAST REG_TYPECAST_UDWORD -#define R_IRQ_MASK0_CLR__TYPE (REG_UDWORD) -#define R_IRQ_MASK0_CLR__GET REG_GET_WO -#define R_IRQ_MASK0_CLR__IGET REG_IGET_WO -#define R_IRQ_MASK0_CLR__SET REG_SET_WO -#define R_IRQ_MASK0_CLR__ISET REG_ISET_WO -#define R_IRQ_MASK0_CLR__SET_VAL REG_SET_VAL_WO -#define R_IRQ_MASK0_CLR__EQL REG_EQL_WO -#define R_IRQ_MASK0_CLR__IEQL REG_IEQL_WO -#define R_IRQ_MASK0_CLR__RD REG_RD_WO -#define R_IRQ_MASK0_CLR__IRD REG_IRD_WO -#define R_IRQ_MASK0_CLR__WR REG_WR_WO -#define R_IRQ_MASK0_CLR__IWR REG_IWR_WO - -#define R_IRQ_MASK0_CLR__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_IRQ_MASK0_CLR__nmi_pin__nmi_pin__MASK 0x80000000U -#define R_IRQ_MASK0_CLR__watchdog_nmi__watchdog_nmi__MASK 0x40000000U -#define R_IRQ_MASK0_CLR__sqe_test_error__sqe_test_error__MASK 0x20000000U -#define R_IRQ_MASK0_CLR__carrier_loss__carrier_loss__MASK 0x10000000U -#define R_IRQ_MASK0_CLR__deferred__deferred__MASK 0x08000000U -#define R_IRQ_MASK0_CLR__late_col__late_col__MASK 0x04000000U -#define R_IRQ_MASK0_CLR__multiple_col__multiple_col__MASK 0x02000000U -#define R_IRQ_MASK0_CLR__single_col__single_col__MASK 0x01000000U -#define R_IRQ_MASK0_CLR__congestion__congestion__MASK 0x00800000U -#define R_IRQ_MASK0_CLR__oversize__oversize__MASK 0x00400000U -#define R_IRQ_MASK0_CLR__alignment_error__alignment_error__MASK 0x00200000U -#define R_IRQ_MASK0_CLR__crc_error__crc_error__MASK 0x00100000U -#define R_IRQ_MASK0_CLR__overrun__overrun__MASK 0x00080000U -#define R_IRQ_MASK0_CLR__underrun__underrun__MASK 0x00040000U -#define R_IRQ_MASK0_CLR__excessive_col__excessive_col__MASK 0x00020000U -#define R_IRQ_MASK0_CLR__mdio__mdio__MASK 0x00010000U -#define R_IRQ_MASK0_CLR__ata_drq3__ata_drq3__MASK 0x00008000U -#define R_IRQ_MASK0_CLR__ata_drq2__ata_drq2__MASK 0x00004000U -#define R_IRQ_MASK0_CLR__ata_drq1__ata_drq1__MASK 0x00002000U -#define R_IRQ_MASK0_CLR__ata_drq0__ata_drq0__MASK 0x00001000U -#define R_IRQ_MASK0_CLR__par0_ecp_cmd__par0_ecp_cmd__MASK 0x00000800U -#define R_IRQ_MASK0_CLR__ata_irq3__ata_irq3__MASK 0x00000800U -#define R_IRQ_MASK0_CLR__par0_ecp_cmd__ata_irq3__MASK 0x00000800U -#define R_IRQ_MASK0_CLR__par0_peri__par0_peri__MASK 0x00000400U -#define R_IRQ_MASK0_CLR__ata_irq2__ata_irq2__MASK 0x00000400U -#define R_IRQ_MASK0_CLR__par0_peri__ata_irq2__MASK 0x00000400U -#define R_IRQ_MASK0_CLR__par0_data__par0_data__MASK 0x00000200U -#define R_IRQ_MASK0_CLR__ata_irq1__ata_irq1__MASK 0x00000200U -#define R_IRQ_MASK0_CLR__par0_data__ata_irq1__MASK 0x00000200U -#define R_IRQ_MASK0_CLR__par0_ready__par0_ready__MASK 0x00000100U -#define R_IRQ_MASK0_CLR__ata_irq0__ata_irq0__MASK 0x00000100U -#define R_IRQ_MASK0_CLR__par0_ready__ata_irq0__MASK 0x00000100U -#define R_IRQ_MASK0_CLR__mio__mio__MASK 0x00000100U -#define R_IRQ_MASK0_CLR__par0_ready__mio__MASK 0x00000100U -#define R_IRQ_MASK0_CLR__scsi0__scsi0__MASK 0x00000100U -#define R_IRQ_MASK0_CLR__par0_ready__scsi0__MASK 0x00000100U -#define R_IRQ_MASK0_CLR__ata_dmaend__ata_dmaend__MASK 0x00000080U -#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__irq_ext_vector_nr__MASK 0x00000020U -#define R_IRQ_MASK0_CLR__irq_int_vector_nr__irq_int_vector_nr__MASK 0x00000010U -#define R_IRQ_MASK0_CLR__ext_dma1__ext_dma1__MASK 0x00000008U -#define R_IRQ_MASK0_CLR__ext_dma0__ext_dma0__MASK 0x00000004U -#define R_IRQ_MASK0_CLR__timer1__timer1__MASK 0x00000002U -#define R_IRQ_MASK0_CLR__timer0__timer0__MASK 0x00000001U - -#define R_IRQ_MASK0_CLR__nmi_pin__MAX 0x1 -#define R_IRQ_MASK0_CLR__watchdog_nmi__MAX 0x1 -#define R_IRQ_MASK0_CLR__sqe_test_error__MAX 0x1 -#define R_IRQ_MASK0_CLR__carrier_loss__MAX 0x1 -#define R_IRQ_MASK0_CLR__deferred__MAX 0x1 -#define R_IRQ_MASK0_CLR__late_col__MAX 0x1 -#define R_IRQ_MASK0_CLR__multiple_col__MAX 0x1 -#define R_IRQ_MASK0_CLR__single_col__MAX 0x1 -#define R_IRQ_MASK0_CLR__congestion__MAX 0x1 -#define R_IRQ_MASK0_CLR__oversize__MAX 0x1 -#define R_IRQ_MASK0_CLR__alignment_error__MAX 0x1 -#define R_IRQ_MASK0_CLR__crc_error__MAX 0x1 -#define R_IRQ_MASK0_CLR__overrun__MAX 0x1 -#define R_IRQ_MASK0_CLR__underrun__MAX 0x1 -#define R_IRQ_MASK0_CLR__excessive_col__MAX 0x1 -#define R_IRQ_MASK0_CLR__mdio__MAX 0x1 -#define R_IRQ_MASK0_CLR__ata_drq3__MAX 0x1 -#define R_IRQ_MASK0_CLR__ata_drq2__MAX 0x1 -#define R_IRQ_MASK0_CLR__ata_drq1__MAX 0x1 -#define R_IRQ_MASK0_CLR__ata_drq0__MAX 0x1 -#define R_IRQ_MASK0_CLR__par0_ecp_cmd__MAX 0x1 -#define R_IRQ_MASK0_CLR__ata_irq3__MAX 0x1 -#define R_IRQ_MASK0_CLR__par0_peri__MAX 0x1 -#define R_IRQ_MASK0_CLR__ata_irq2__MAX 0x1 -#define R_IRQ_MASK0_CLR__par0_data__MAX 0x1 -#define R_IRQ_MASK0_CLR__ata_irq1__MAX 0x1 -#define R_IRQ_MASK0_CLR__par0_ready__MAX 0x1 -#define R_IRQ_MASK0_CLR__ata_irq0__MAX 0x1 -#define R_IRQ_MASK0_CLR__mio__MAX 0x1 -#define R_IRQ_MASK0_CLR__scsi0__MAX 0x1 -#define R_IRQ_MASK0_CLR__ata_dmaend__MAX 0x1 -#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__MAX 0x1 -#define R_IRQ_MASK0_CLR__irq_int_vector_nr__MAX 0x1 -#define R_IRQ_MASK0_CLR__ext_dma1__MAX 0x1 -#define R_IRQ_MASK0_CLR__ext_dma0__MAX 0x1 -#define R_IRQ_MASK0_CLR__timer1__MAX 0x1 -#define R_IRQ_MASK0_CLR__timer0__MAX 0x1 - -#define R_IRQ_MASK0_CLR__nmi_pin__MIN 0 -#define R_IRQ_MASK0_CLR__watchdog_nmi__MIN 0 -#define R_IRQ_MASK0_CLR__sqe_test_error__MIN 0 -#define R_IRQ_MASK0_CLR__carrier_loss__MIN 0 -#define R_IRQ_MASK0_CLR__deferred__MIN 0 -#define R_IRQ_MASK0_CLR__late_col__MIN 0 -#define R_IRQ_MASK0_CLR__multiple_col__MIN 0 -#define R_IRQ_MASK0_CLR__single_col__MIN 0 -#define R_IRQ_MASK0_CLR__congestion__MIN 0 -#define R_IRQ_MASK0_CLR__oversize__MIN 0 -#define R_IRQ_MASK0_CLR__alignment_error__MIN 0 -#define R_IRQ_MASK0_CLR__crc_error__MIN 0 -#define R_IRQ_MASK0_CLR__overrun__MIN 0 -#define R_IRQ_MASK0_CLR__underrun__MIN 0 -#define R_IRQ_MASK0_CLR__excessive_col__MIN 0 -#define R_IRQ_MASK0_CLR__mdio__MIN 0 -#define R_IRQ_MASK0_CLR__ata_drq3__MIN 0 -#define R_IRQ_MASK0_CLR__ata_drq2__MIN 0 -#define R_IRQ_MASK0_CLR__ata_drq1__MIN 0 -#define R_IRQ_MASK0_CLR__ata_drq0__MIN 0 -#define R_IRQ_MASK0_CLR__par0_ecp_cmd__MIN 0 -#define R_IRQ_MASK0_CLR__ata_irq3__MIN 0 -#define R_IRQ_MASK0_CLR__par0_peri__MIN 0 -#define R_IRQ_MASK0_CLR__ata_irq2__MIN 0 -#define R_IRQ_MASK0_CLR__par0_data__MIN 0 -#define R_IRQ_MASK0_CLR__ata_irq1__MIN 0 -#define R_IRQ_MASK0_CLR__par0_ready__MIN 0 -#define R_IRQ_MASK0_CLR__ata_irq0__MIN 0 -#define R_IRQ_MASK0_CLR__mio__MIN 0 -#define R_IRQ_MASK0_CLR__scsi0__MIN 0 -#define R_IRQ_MASK0_CLR__ata_dmaend__MIN 0 -#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__MIN 0 -#define R_IRQ_MASK0_CLR__irq_int_vector_nr__MIN 0 -#define R_IRQ_MASK0_CLR__ext_dma1__MIN 0 -#define R_IRQ_MASK0_CLR__ext_dma0__MIN 0 -#define R_IRQ_MASK0_CLR__timer1__MIN 0 -#define R_IRQ_MASK0_CLR__timer0__MIN 0 - -#define R_IRQ_MASK0_CLR__nmi_pin__BITNR 31 -#define R_IRQ_MASK0_CLR__watchdog_nmi__BITNR 30 -#define R_IRQ_MASK0_CLR__sqe_test_error__BITNR 29 -#define R_IRQ_MASK0_CLR__carrier_loss__BITNR 28 -#define R_IRQ_MASK0_CLR__deferred__BITNR 27 -#define R_IRQ_MASK0_CLR__late_col__BITNR 26 -#define R_IRQ_MASK0_CLR__multiple_col__BITNR 25 -#define R_IRQ_MASK0_CLR__single_col__BITNR 24 -#define R_IRQ_MASK0_CLR__congestion__BITNR 23 -#define R_IRQ_MASK0_CLR__oversize__BITNR 22 -#define R_IRQ_MASK0_CLR__alignment_error__BITNR 21 -#define R_IRQ_MASK0_CLR__crc_error__BITNR 20 -#define R_IRQ_MASK0_CLR__overrun__BITNR 19 -#define R_IRQ_MASK0_CLR__underrun__BITNR 18 -#define R_IRQ_MASK0_CLR__excessive_col__BITNR 17 -#define R_IRQ_MASK0_CLR__mdio__BITNR 16 -#define R_IRQ_MASK0_CLR__ata_drq3__BITNR 15 -#define R_IRQ_MASK0_CLR__ata_drq2__BITNR 14 -#define R_IRQ_MASK0_CLR__ata_drq1__BITNR 13 -#define R_IRQ_MASK0_CLR__ata_drq0__BITNR 12 -#define R_IRQ_MASK0_CLR__par0_ecp_cmd__BITNR 11 -#define R_IRQ_MASK0_CLR__ata_irq3__BITNR 11 -#define R_IRQ_MASK0_CLR__par0_peri__BITNR 10 -#define R_IRQ_MASK0_CLR__ata_irq2__BITNR 10 -#define R_IRQ_MASK0_CLR__par0_data__BITNR 9 -#define R_IRQ_MASK0_CLR__ata_irq1__BITNR 9 -#define R_IRQ_MASK0_CLR__par0_ready__BITNR 8 -#define R_IRQ_MASK0_CLR__ata_irq0__BITNR 8 -#define R_IRQ_MASK0_CLR__mio__BITNR 8 -#define R_IRQ_MASK0_CLR__scsi0__BITNR 8 -#define R_IRQ_MASK0_CLR__ata_dmaend__BITNR 7 -#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__BITNR 5 -#define R_IRQ_MASK0_CLR__irq_int_vector_nr__BITNR 4 -#define R_IRQ_MASK0_CLR__ext_dma1__BITNR 3 -#define R_IRQ_MASK0_CLR__ext_dma0__BITNR 2 -#define R_IRQ_MASK0_CLR__timer1__BITNR 1 -#define R_IRQ_MASK0_CLR__timer0__BITNR 0 - -#define R_IRQ_MASK0_CLR__nmi_pin__nmi_pin__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_CLR__watchdog_nmi__watchdog_nmi__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_CLR__sqe_test_error__sqe_test_error__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_CLR__carrier_loss__carrier_loss__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_CLR__deferred__deferred__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_CLR__late_col__late_col__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_CLR__multiple_col__multiple_col__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_CLR__single_col__single_col__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_CLR__congestion__congestion__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_CLR__oversize__oversize__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_CLR__alignment_error__alignment_error__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_CLR__crc_error__crc_error__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_CLR__overrun__overrun__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_CLR__underrun__underrun__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_CLR__excessive_col__excessive_col__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_CLR__mdio__mdio__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_CLR__ata_drq3__ata_drq3__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_CLR__ata_drq2__ata_drq2__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_CLR__ata_drq1__ata_drq1__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_CLR__ata_drq0__ata_drq0__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_CLR__par0_ecp_cmd__par0_ecp_cmd__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_CLR__ata_irq3__ata_irq3__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_CLR__par0_ecp_cmd__ata_irq3__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_CLR__par0_peri__par0_peri__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_CLR__ata_irq2__ata_irq2__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_CLR__par0_peri__ata_irq2__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_CLR__par0_data__par0_data__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_CLR__ata_irq1__ata_irq1__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_CLR__par0_data__ata_irq1__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_CLR__par0_ready__par0_ready__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_CLR__ata_irq0__ata_irq0__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_CLR__par0_ready__ata_irq0__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_CLR__mio__mio__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_CLR__par0_ready__mio__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_CLR__scsi0__scsi0__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_CLR__par0_ready__scsi0__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_CLR__ata_dmaend__ata_dmaend__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__irq_ext_vector_nr__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_CLR__irq_int_vector_nr__irq_int_vector_nr__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_CLR__ext_dma1__ext_dma1__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_CLR__ext_dma0__ext_dma0__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_CLR__timer1__timer1__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_CLR__timer0__timer0__VAL REG_VAL_ENUM - -#define R_IRQ_MASK0_CLR__nmi_pin__nmi_pin__clr 1 -#define R_IRQ_MASK0_CLR__nmi_pin__nmi_pin__nop 0 -#define R_IRQ_MASK0_CLR__watchdog_nmi__watchdog_nmi__clr 1 -#define R_IRQ_MASK0_CLR__watchdog_nmi__watchdog_nmi__nop 0 -#define R_IRQ_MASK0_CLR__sqe_test_error__sqe_test_error__clr 1 -#define R_IRQ_MASK0_CLR__sqe_test_error__sqe_test_error__nop 0 -#define R_IRQ_MASK0_CLR__carrier_loss__carrier_loss__clr 1 -#define R_IRQ_MASK0_CLR__carrier_loss__carrier_loss__nop 0 -#define R_IRQ_MASK0_CLR__deferred__deferred__clr 1 -#define R_IRQ_MASK0_CLR__deferred__deferred__nop 0 -#define R_IRQ_MASK0_CLR__late_col__late_col__clr 1 -#define R_IRQ_MASK0_CLR__late_col__late_col__nop 0 -#define R_IRQ_MASK0_CLR__multiple_col__multiple_col__clr 1 -#define R_IRQ_MASK0_CLR__multiple_col__multiple_col__nop 0 -#define R_IRQ_MASK0_CLR__single_col__single_col__clr 1 -#define R_IRQ_MASK0_CLR__single_col__single_col__nop 0 -#define R_IRQ_MASK0_CLR__congestion__congestion__clr 1 -#define R_IRQ_MASK0_CLR__congestion__congestion__nop 0 -#define R_IRQ_MASK0_CLR__oversize__oversize__clr 1 -#define R_IRQ_MASK0_CLR__oversize__oversize__nop 0 -#define R_IRQ_MASK0_CLR__alignment_error__alignment_error__clr 1 -#define R_IRQ_MASK0_CLR__alignment_error__alignment_error__nop 0 -#define R_IRQ_MASK0_CLR__crc_error__crc_error__clr 1 -#define R_IRQ_MASK0_CLR__crc_error__crc_error__nop 0 -#define R_IRQ_MASK0_CLR__overrun__overrun__clr 1 -#define R_IRQ_MASK0_CLR__overrun__overrun__nop 0 -#define R_IRQ_MASK0_CLR__underrun__underrun__clr 1 -#define R_IRQ_MASK0_CLR__underrun__underrun__nop 0 -#define R_IRQ_MASK0_CLR__excessive_col__excessive_col__clr 1 -#define R_IRQ_MASK0_CLR__excessive_col__excessive_col__nop 0 -#define R_IRQ_MASK0_CLR__mdio__mdio__clr 1 -#define R_IRQ_MASK0_CLR__mdio__mdio__nop 0 -#define R_IRQ_MASK0_CLR__ata_drq3__ata_drq3__clr 1 -#define R_IRQ_MASK0_CLR__ata_drq3__ata_drq3__nop 0 -#define R_IRQ_MASK0_CLR__ata_drq2__ata_drq2__clr 1 -#define R_IRQ_MASK0_CLR__ata_drq2__ata_drq2__nop 0 -#define R_IRQ_MASK0_CLR__ata_drq1__ata_drq1__clr 1 -#define R_IRQ_MASK0_CLR__ata_drq1__ata_drq1__nop 0 -#define R_IRQ_MASK0_CLR__ata_drq0__ata_drq0__clr 1 -#define R_IRQ_MASK0_CLR__ata_drq0__ata_drq0__nop 0 -#define R_IRQ_MASK0_CLR__par0_ecp_cmd__par0_ecp_cmd__clr 1 -#define R_IRQ_MASK0_CLR__par0_ecp_cmd__par0_ecp_cmd__nop 0 -#define R_IRQ_MASK0_CLR__ata_irq3__ata_irq3__clr 1 -#define R_IRQ_MASK0_CLR__ata_irq3__ata_irq3__nop 0 -#define R_IRQ_MASK0_CLR__par0_peri__par0_peri__clr 1 -#define R_IRQ_MASK0_CLR__par0_peri__par0_peri__nop 0 -#define R_IRQ_MASK0_CLR__ata_irq2__ata_irq2__clr 1 -#define R_IRQ_MASK0_CLR__ata_irq2__ata_irq2__nop 0 -#define R_IRQ_MASK0_CLR__par0_data__par0_data__clr 1 -#define R_IRQ_MASK0_CLR__par0_data__par0_data__nop 0 -#define R_IRQ_MASK0_CLR__ata_irq1__ata_irq1__clr 1 -#define R_IRQ_MASK0_CLR__ata_irq1__ata_irq1__nop 0 -#define R_IRQ_MASK0_CLR__par0_ready__par0_ready__clr 1 -#define R_IRQ_MASK0_CLR__par0_ready__par0_ready__nop 0 -#define R_IRQ_MASK0_CLR__ata_irq0__ata_irq0__clr 1 -#define R_IRQ_MASK0_CLR__ata_irq0__ata_irq0__nop 0 -#define R_IRQ_MASK0_CLR__mio__mio__clr 1 -#define R_IRQ_MASK0_CLR__mio__mio__nop 0 -#define R_IRQ_MASK0_CLR__scsi0__scsi0__clr 1 -#define R_IRQ_MASK0_CLR__scsi0__scsi0__nop 0 -#define R_IRQ_MASK0_CLR__ata_dmaend__ata_dmaend__clr 1 -#define R_IRQ_MASK0_CLR__ata_dmaend__ata_dmaend__nop 0 -#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__irq_ext_vector_nr__clr 1 -#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__irq_ext_vector_nr__nop 0 -#define R_IRQ_MASK0_CLR__irq_int_vector_nr__irq_int_vector_nr__clr 1 -#define R_IRQ_MASK0_CLR__irq_int_vector_nr__irq_int_vector_nr__nop 0 -#define R_IRQ_MASK0_CLR__ext_dma1__ext_dma1__clr 1 -#define R_IRQ_MASK0_CLR__ext_dma1__ext_dma1__nop 0 -#define R_IRQ_MASK0_CLR__ext_dma0__ext_dma0__clr 1 -#define R_IRQ_MASK0_CLR__ext_dma0__ext_dma0__nop 0 -#define R_IRQ_MASK0_CLR__timer1__timer1__clr 1 -#define R_IRQ_MASK0_CLR__timer1__timer1__nop 0 -#define R_IRQ_MASK0_CLR__timer0__timer0__clr 1 -#define R_IRQ_MASK0_CLR__timer0__timer0__nop 0 - -#endif - -/* - * R_IRQ_MASK0_RD - * - type: RO - * - addr: 0xb00000c0 - * - group: Interrupt mask and status registers - */ - -#if USE_GROUP__Interrupt_mask_and_status_registers - -#define R_IRQ_MASK0_RD__ADDR (REG_TYPECAST_UDWORD 0xb00000c0) -#define R_IRQ_MASK0_RD__SVAL REG_SVAL_SHADOW -#define R_IRQ_MASK0_RD__SVAL_I REG_SVAL_I_SHADOW -#define R_IRQ_MASK0_RD__TYPECAST REG_TYPECAST_UDWORD -#define R_IRQ_MASK0_RD__TYPE (REG_UDWORD) -#define R_IRQ_MASK0_RD__GET REG_GET_RO -#define R_IRQ_MASK0_RD__IGET REG_IGET_RO -#define R_IRQ_MASK0_RD__SET REG_SET_RO -#define R_IRQ_MASK0_RD__ISET REG_ISET_RO -#define R_IRQ_MASK0_RD__SET_VAL REG_SET_VAL_RO -#define R_IRQ_MASK0_RD__EQL REG_EQL_RO -#define R_IRQ_MASK0_RD__IEQL REG_IEQL_RO -#define R_IRQ_MASK0_RD__RD REG_RD_RO -#define R_IRQ_MASK0_RD__IRD REG_IRD_RO -#define R_IRQ_MASK0_RD__WR REG_WR_RO -#define R_IRQ_MASK0_RD__IWR REG_IWR_RO - -#define R_IRQ_MASK0_RD__READ(addr) \ - (*(addr)) - -#define R_IRQ_MASK0_RD__nmi_pin__nmi_pin__MASK 0x80000000U -#define R_IRQ_MASK0_RD__watchdog_nmi__watchdog_nmi__MASK 0x40000000U -#define R_IRQ_MASK0_RD__sqe_test_error__sqe_test_error__MASK 0x20000000U -#define R_IRQ_MASK0_RD__carrier_loss__carrier_loss__MASK 0x10000000U -#define R_IRQ_MASK0_RD__deferred__deferred__MASK 0x08000000U -#define R_IRQ_MASK0_RD__late_col__late_col__MASK 0x04000000U -#define R_IRQ_MASK0_RD__multiple_col__multiple_col__MASK 0x02000000U -#define R_IRQ_MASK0_RD__single_col__single_col__MASK 0x01000000U -#define R_IRQ_MASK0_RD__congestion__congestion__MASK 0x00800000U -#define R_IRQ_MASK0_RD__oversize__oversize__MASK 0x00400000U -#define R_IRQ_MASK0_RD__alignment_error__alignment_error__MASK 0x00200000U -#define R_IRQ_MASK0_RD__crc_error__crc_error__MASK 0x00100000U -#define R_IRQ_MASK0_RD__overrun__overrun__MASK 0x00080000U -#define R_IRQ_MASK0_RD__underrun__underrun__MASK 0x00040000U -#define R_IRQ_MASK0_RD__excessive_col__excessive_col__MASK 0x00020000U -#define R_IRQ_MASK0_RD__mdio__mdio__MASK 0x00010000U -#define R_IRQ_MASK0_RD__ata_drq3__ata_drq3__MASK 0x00008000U -#define R_IRQ_MASK0_RD__ata_drq2__ata_drq2__MASK 0x00004000U -#define R_IRQ_MASK0_RD__ata_drq1__ata_drq1__MASK 0x00002000U -#define R_IRQ_MASK0_RD__ata_drq0__ata_drq0__MASK 0x00001000U -#define R_IRQ_MASK0_RD__par0_ecp_cmd__par0_ecp_cmd__MASK 0x00000800U -#define R_IRQ_MASK0_RD__ata_irq3__ata_irq3__MASK 0x00000800U -#define R_IRQ_MASK0_RD__par0_ecp_cmd__ata_irq3__MASK 0x00000800U -#define R_IRQ_MASK0_RD__par0_peri__par0_peri__MASK 0x00000400U -#define R_IRQ_MASK0_RD__ata_irq2__ata_irq2__MASK 0x00000400U -#define R_IRQ_MASK0_RD__par0_peri__ata_irq2__MASK 0x00000400U -#define R_IRQ_MASK0_RD__par0_data__par0_data__MASK 0x00000200U -#define R_IRQ_MASK0_RD__ata_irq1__ata_irq1__MASK 0x00000200U -#define R_IRQ_MASK0_RD__par0_data__ata_irq1__MASK 0x00000200U -#define R_IRQ_MASK0_RD__par0_ready__par0_ready__MASK 0x00000100U -#define R_IRQ_MASK0_RD__ata_irq0__ata_irq0__MASK 0x00000100U -#define R_IRQ_MASK0_RD__par0_ready__ata_irq0__MASK 0x00000100U -#define R_IRQ_MASK0_RD__mio__mio__MASK 0x00000100U -#define R_IRQ_MASK0_RD__par0_ready__mio__MASK 0x00000100U -#define R_IRQ_MASK0_RD__scsi0__scsi0__MASK 0x00000100U -#define R_IRQ_MASK0_RD__par0_ready__scsi0__MASK 0x00000100U -#define R_IRQ_MASK0_RD__ata_dmaend__ata_dmaend__MASK 0x00000080U -#define R_IRQ_MASK0_RD__irq_ext_vector_nr__irq_ext_vector_nr__MASK 0x00000020U -#define R_IRQ_MASK0_RD__irq_int_vector_nr__irq_int_vector_nr__MASK 0x00000010U -#define R_IRQ_MASK0_RD__ext_dma1__ext_dma1__MASK 0x00000008U -#define R_IRQ_MASK0_RD__ext_dma0__ext_dma0__MASK 0x00000004U -#define R_IRQ_MASK0_RD__timer1__timer1__MASK 0x00000002U -#define R_IRQ_MASK0_RD__timer0__timer0__MASK 0x00000001U - -#define R_IRQ_MASK0_RD__nmi_pin__MAX 0x1 -#define R_IRQ_MASK0_RD__watchdog_nmi__MAX 0x1 -#define R_IRQ_MASK0_RD__sqe_test_error__MAX 0x1 -#define R_IRQ_MASK0_RD__carrier_loss__MAX 0x1 -#define R_IRQ_MASK0_RD__deferred__MAX 0x1 -#define R_IRQ_MASK0_RD__late_col__MAX 0x1 -#define R_IRQ_MASK0_RD__multiple_col__MAX 0x1 -#define R_IRQ_MASK0_RD__single_col__MAX 0x1 -#define R_IRQ_MASK0_RD__congestion__MAX 0x1 -#define R_IRQ_MASK0_RD__oversize__MAX 0x1 -#define R_IRQ_MASK0_RD__alignment_error__MAX 0x1 -#define R_IRQ_MASK0_RD__crc_error__MAX 0x1 -#define R_IRQ_MASK0_RD__overrun__MAX 0x1 -#define R_IRQ_MASK0_RD__underrun__MAX 0x1 -#define R_IRQ_MASK0_RD__excessive_col__MAX 0x1 -#define R_IRQ_MASK0_RD__mdio__MAX 0x1 -#define R_IRQ_MASK0_RD__ata_drq3__MAX 0x1 -#define R_IRQ_MASK0_RD__ata_drq2__MAX 0x1 -#define R_IRQ_MASK0_RD__ata_drq1__MAX 0x1 -#define R_IRQ_MASK0_RD__ata_drq0__MAX 0x1 -#define R_IRQ_MASK0_RD__par0_ecp_cmd__MAX 0x1 -#define R_IRQ_MASK0_RD__ata_irq3__MAX 0x1 -#define R_IRQ_MASK0_RD__par0_peri__MAX 0x1 -#define R_IRQ_MASK0_RD__ata_irq2__MAX 0x1 -#define R_IRQ_MASK0_RD__par0_data__MAX 0x1 -#define R_IRQ_MASK0_RD__ata_irq1__MAX 0x1 -#define R_IRQ_MASK0_RD__par0_ready__MAX 0x1 -#define R_IRQ_MASK0_RD__ata_irq0__MAX 0x1 -#define R_IRQ_MASK0_RD__mio__MAX 0x1 -#define R_IRQ_MASK0_RD__scsi0__MAX 0x1 -#define R_IRQ_MASK0_RD__ata_dmaend__MAX 0x1 -#define R_IRQ_MASK0_RD__irq_ext_vector_nr__MAX 0x1 -#define R_IRQ_MASK0_RD__irq_int_vector_nr__MAX 0x1 -#define R_IRQ_MASK0_RD__ext_dma1__MAX 0x1 -#define R_IRQ_MASK0_RD__ext_dma0__MAX 0x1 -#define R_IRQ_MASK0_RD__timer1__MAX 0x1 -#define R_IRQ_MASK0_RD__timer0__MAX 0x1 - -#define R_IRQ_MASK0_RD__nmi_pin__MIN 0 -#define R_IRQ_MASK0_RD__watchdog_nmi__MIN 0 -#define R_IRQ_MASK0_RD__sqe_test_error__MIN 0 -#define R_IRQ_MASK0_RD__carrier_loss__MIN 0 -#define R_IRQ_MASK0_RD__deferred__MIN 0 -#define R_IRQ_MASK0_RD__late_col__MIN 0 -#define R_IRQ_MASK0_RD__multiple_col__MIN 0 -#define R_IRQ_MASK0_RD__single_col__MIN 0 -#define R_IRQ_MASK0_RD__congestion__MIN 0 -#define R_IRQ_MASK0_RD__oversize__MIN 0 -#define R_IRQ_MASK0_RD__alignment_error__MIN 0 -#define R_IRQ_MASK0_RD__crc_error__MIN 0 -#define R_IRQ_MASK0_RD__overrun__MIN 0 -#define R_IRQ_MASK0_RD__underrun__MIN 0 -#define R_IRQ_MASK0_RD__excessive_col__MIN 0 -#define R_IRQ_MASK0_RD__mdio__MIN 0 -#define R_IRQ_MASK0_RD__ata_drq3__MIN 0 -#define R_IRQ_MASK0_RD__ata_drq2__MIN 0 -#define R_IRQ_MASK0_RD__ata_drq1__MIN 0 -#define R_IRQ_MASK0_RD__ata_drq0__MIN 0 -#define R_IRQ_MASK0_RD__par0_ecp_cmd__MIN 0 -#define R_IRQ_MASK0_RD__ata_irq3__MIN 0 -#define R_IRQ_MASK0_RD__par0_peri__MIN 0 -#define R_IRQ_MASK0_RD__ata_irq2__MIN 0 -#define R_IRQ_MASK0_RD__par0_data__MIN 0 -#define R_IRQ_MASK0_RD__ata_irq1__MIN 0 -#define R_IRQ_MASK0_RD__par0_ready__MIN 0 -#define R_IRQ_MASK0_RD__ata_irq0__MIN 0 -#define R_IRQ_MASK0_RD__mio__MIN 0 -#define R_IRQ_MASK0_RD__scsi0__MIN 0 -#define R_IRQ_MASK0_RD__ata_dmaend__MIN 0 -#define R_IRQ_MASK0_RD__irq_ext_vector_nr__MIN 0 -#define R_IRQ_MASK0_RD__irq_int_vector_nr__MIN 0 -#define R_IRQ_MASK0_RD__ext_dma1__MIN 0 -#define R_IRQ_MASK0_RD__ext_dma0__MIN 0 -#define R_IRQ_MASK0_RD__timer1__MIN 0 -#define R_IRQ_MASK0_RD__timer0__MIN 0 - -#define R_IRQ_MASK0_RD__nmi_pin__BITNR 31 -#define R_IRQ_MASK0_RD__watchdog_nmi__BITNR 30 -#define R_IRQ_MASK0_RD__sqe_test_error__BITNR 29 -#define R_IRQ_MASK0_RD__carrier_loss__BITNR 28 -#define R_IRQ_MASK0_RD__deferred__BITNR 27 -#define R_IRQ_MASK0_RD__late_col__BITNR 26 -#define R_IRQ_MASK0_RD__multiple_col__BITNR 25 -#define R_IRQ_MASK0_RD__single_col__BITNR 24 -#define R_IRQ_MASK0_RD__congestion__BITNR 23 -#define R_IRQ_MASK0_RD__oversize__BITNR 22 -#define R_IRQ_MASK0_RD__alignment_error__BITNR 21 -#define R_IRQ_MASK0_RD__crc_error__BITNR 20 -#define R_IRQ_MASK0_RD__overrun__BITNR 19 -#define R_IRQ_MASK0_RD__underrun__BITNR 18 -#define R_IRQ_MASK0_RD__excessive_col__BITNR 17 -#define R_IRQ_MASK0_RD__mdio__BITNR 16 -#define R_IRQ_MASK0_RD__ata_drq3__BITNR 15 -#define R_IRQ_MASK0_RD__ata_drq2__BITNR 14 -#define R_IRQ_MASK0_RD__ata_drq1__BITNR 13 -#define R_IRQ_MASK0_RD__ata_drq0__BITNR 12 -#define R_IRQ_MASK0_RD__par0_ecp_cmd__BITNR 11 -#define R_IRQ_MASK0_RD__ata_irq3__BITNR 11 -#define R_IRQ_MASK0_RD__par0_peri__BITNR 10 -#define R_IRQ_MASK0_RD__ata_irq2__BITNR 10 -#define R_IRQ_MASK0_RD__par0_data__BITNR 9 -#define R_IRQ_MASK0_RD__ata_irq1__BITNR 9 -#define R_IRQ_MASK0_RD__par0_ready__BITNR 8 -#define R_IRQ_MASK0_RD__ata_irq0__BITNR 8 -#define R_IRQ_MASK0_RD__mio__BITNR 8 -#define R_IRQ_MASK0_RD__scsi0__BITNR 8 -#define R_IRQ_MASK0_RD__ata_dmaend__BITNR 7 -#define R_IRQ_MASK0_RD__irq_ext_vector_nr__BITNR 5 -#define R_IRQ_MASK0_RD__irq_int_vector_nr__BITNR 4 -#define R_IRQ_MASK0_RD__ext_dma1__BITNR 3 -#define R_IRQ_MASK0_RD__ext_dma0__BITNR 2 -#define R_IRQ_MASK0_RD__timer1__BITNR 1 -#define R_IRQ_MASK0_RD__timer0__BITNR 0 - -#define R_IRQ_MASK0_RD__nmi_pin__nmi_pin__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_RD__watchdog_nmi__watchdog_nmi__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_RD__sqe_test_error__sqe_test_error__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_RD__carrier_loss__carrier_loss__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_RD__deferred__deferred__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_RD__late_col__late_col__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_RD__multiple_col__multiple_col__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_RD__single_col__single_col__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_RD__congestion__congestion__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_RD__oversize__oversize__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_RD__alignment_error__alignment_error__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_RD__crc_error__crc_error__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_RD__overrun__overrun__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_RD__underrun__underrun__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_RD__excessive_col__excessive_col__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_RD__mdio__mdio__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_RD__ata_drq3__ata_drq3__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_RD__ata_drq2__ata_drq2__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_RD__ata_drq1__ata_drq1__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_RD__ata_drq0__ata_drq0__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_RD__par0_ecp_cmd__par0_ecp_cmd__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_RD__ata_irq3__ata_irq3__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_RD__par0_ecp_cmd__ata_irq3__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_RD__par0_peri__par0_peri__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_RD__ata_irq2__ata_irq2__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_RD__par0_peri__ata_irq2__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_RD__par0_data__par0_data__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_RD__ata_irq1__ata_irq1__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_RD__par0_data__ata_irq1__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_RD__par0_ready__par0_ready__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_RD__ata_irq0__ata_irq0__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_RD__par0_ready__ata_irq0__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_RD__mio__mio__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_RD__par0_ready__mio__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_RD__scsi0__scsi0__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_RD__par0_ready__scsi0__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_RD__ata_dmaend__ata_dmaend__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_RD__irq_ext_vector_nr__irq_ext_vector_nr__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_RD__irq_int_vector_nr__irq_int_vector_nr__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_RD__ext_dma1__ext_dma1__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_RD__ext_dma0__ext_dma0__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_RD__timer1__timer1__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_RD__timer0__timer0__VAL REG_VAL_ENUM - -#define R_IRQ_MASK0_RD__nmi_pin__nmi_pin__active 1 -#define R_IRQ_MASK0_RD__nmi_pin__nmi_pin__inactive 0 -#define R_IRQ_MASK0_RD__watchdog_nmi__watchdog_nmi__active 1 -#define R_IRQ_MASK0_RD__watchdog_nmi__watchdog_nmi__inactive 0 -#define R_IRQ_MASK0_RD__sqe_test_error__sqe_test_error__active 1 -#define R_IRQ_MASK0_RD__sqe_test_error__sqe_test_error__inactive 0 -#define R_IRQ_MASK0_RD__carrier_loss__carrier_loss__active 1 -#define R_IRQ_MASK0_RD__carrier_loss__carrier_loss__inactive 0 -#define R_IRQ_MASK0_RD__deferred__deferred__active 1 -#define R_IRQ_MASK0_RD__deferred__deferred__inactive 0 -#define R_IRQ_MASK0_RD__late_col__late_col__active 1 -#define R_IRQ_MASK0_RD__late_col__late_col__inactive 0 -#define R_IRQ_MASK0_RD__multiple_col__multiple_col__active 1 -#define R_IRQ_MASK0_RD__multiple_col__multiple_col__inactive 0 -#define R_IRQ_MASK0_RD__single_col__single_col__active 1 -#define R_IRQ_MASK0_RD__single_col__single_col__inactive 0 -#define R_IRQ_MASK0_RD__congestion__congestion__active 1 -#define R_IRQ_MASK0_RD__congestion__congestion__inactive 0 -#define R_IRQ_MASK0_RD__oversize__oversize__active 1 -#define R_IRQ_MASK0_RD__oversize__oversize__inactive 0 -#define R_IRQ_MASK0_RD__alignment_error__alignment_error__active 1 -#define R_IRQ_MASK0_RD__alignment_error__alignment_error__inactive 0 -#define R_IRQ_MASK0_RD__crc_error__crc_error__active 1 -#define R_IRQ_MASK0_RD__crc_error__crc_error__inactive 0 -#define R_IRQ_MASK0_RD__overrun__overrun__active 1 -#define R_IRQ_MASK0_RD__overrun__overrun__inactive 0 -#define R_IRQ_MASK0_RD__underrun__underrun__active 1 -#define R_IRQ_MASK0_RD__underrun__underrun__inactive 0 -#define R_IRQ_MASK0_RD__excessive_col__excessive_col__active 1 -#define R_IRQ_MASK0_RD__excessive_col__excessive_col__inactive 0 -#define R_IRQ_MASK0_RD__mdio__mdio__active 1 -#define R_IRQ_MASK0_RD__mdio__mdio__inactive 0 -#define R_IRQ_MASK0_RD__ata_drq3__ata_drq3__active 1 -#define R_IRQ_MASK0_RD__ata_drq3__ata_drq3__inactive 0 -#define R_IRQ_MASK0_RD__ata_drq2__ata_drq2__active 1 -#define R_IRQ_MASK0_RD__ata_drq2__ata_drq2__inactive 0 -#define R_IRQ_MASK0_RD__ata_drq1__ata_drq1__active 1 -#define R_IRQ_MASK0_RD__ata_drq1__ata_drq1__inactive 0 -#define R_IRQ_MASK0_RD__ata_drq0__ata_drq0__active 1 -#define R_IRQ_MASK0_RD__ata_drq0__ata_drq0__inactive 0 -#define R_IRQ_MASK0_RD__par0_ecp_cmd__par0_ecp_cmd__active 1 -#define R_IRQ_MASK0_RD__par0_ecp_cmd__par0_ecp_cmd__inactive 0 -#define R_IRQ_MASK0_RD__ata_irq3__ata_irq3__active 1 -#define R_IRQ_MASK0_RD__ata_irq3__ata_irq3__inactive 0 -#define R_IRQ_MASK0_RD__par0_peri__par0_peri__active 1 -#define R_IRQ_MASK0_RD__par0_peri__par0_peri__inactive 0 -#define R_IRQ_MASK0_RD__ata_irq2__ata_irq2__active 1 -#define R_IRQ_MASK0_RD__ata_irq2__ata_irq2__inactive 0 -#define R_IRQ_MASK0_RD__par0_data__par0_data__active 1 -#define R_IRQ_MASK0_RD__par0_data__par0_data__inactive 0 -#define R_IRQ_MASK0_RD__ata_irq1__ata_irq1__active 1 -#define R_IRQ_MASK0_RD__ata_irq1__ata_irq1__inactive 0 -#define R_IRQ_MASK0_RD__par0_ready__par0_ready__active 1 -#define R_IRQ_MASK0_RD__par0_ready__par0_ready__inactive 0 -#define R_IRQ_MASK0_RD__ata_irq0__ata_irq0__active 1 -#define R_IRQ_MASK0_RD__ata_irq0__ata_irq0__inactive 0 -#define R_IRQ_MASK0_RD__mio__mio__active 1 -#define R_IRQ_MASK0_RD__mio__mio__inactive 0 -#define R_IRQ_MASK0_RD__scsi0__scsi0__active 1 -#define R_IRQ_MASK0_RD__scsi0__scsi0__inactive 0 -#define R_IRQ_MASK0_RD__ata_dmaend__ata_dmaend__active 1 -#define R_IRQ_MASK0_RD__ata_dmaend__ata_dmaend__inactive 0 -#define R_IRQ_MASK0_RD__irq_ext_vector_nr__irq_ext_vector_nr__active 1 -#define R_IRQ_MASK0_RD__irq_ext_vector_nr__irq_ext_vector_nr__inactive 0 -#define R_IRQ_MASK0_RD__irq_int_vector_nr__irq_int_vector_nr__active 1 -#define R_IRQ_MASK0_RD__irq_int_vector_nr__irq_int_vector_nr__inactive 0 -#define R_IRQ_MASK0_RD__ext_dma1__ext_dma1__active 1 -#define R_IRQ_MASK0_RD__ext_dma1__ext_dma1__inactive 0 -#define R_IRQ_MASK0_RD__ext_dma0__ext_dma0__active 1 -#define R_IRQ_MASK0_RD__ext_dma0__ext_dma0__inactive 0 -#define R_IRQ_MASK0_RD__timer1__timer1__active 1 -#define R_IRQ_MASK0_RD__timer1__timer1__inactive 0 -#define R_IRQ_MASK0_RD__timer0__timer0__active 1 -#define R_IRQ_MASK0_RD__timer0__timer0__inactive 0 - -#endif - -/* - * R_IRQ_MASK0_SET - * - type: WO - * - addr: 0xb00000c4 - * - group: Interrupt mask and status registers - */ - -#if USE_GROUP__Interrupt_mask_and_status_registers - -#define R_IRQ_MASK0_SET__ADDR (REG_TYPECAST_UDWORD 0xb00000c4) - -#ifndef REG_NO_SHADOW -#define R_IRQ_MASK0_SET__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_IRQ_MASK0_SET + 0)) -#define R_IRQ_MASK0_SET__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_IRQ_MASK0_SET + 0)) -#else /* REG_NO_SHADOW */ -#define R_IRQ_MASK0_SET__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_IRQ_MASK0_SET__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_IRQ_MASK0_SET__STYPECAST REG_STYPECAST_UDWORD -#define R_IRQ_MASK0_SET__SVAL REG_SVAL_ZERO -#define R_IRQ_MASK0_SET__SVAL_I REG_SVAL_I_ZERO -#define R_IRQ_MASK0_SET__TYPECAST REG_TYPECAST_UDWORD -#define R_IRQ_MASK0_SET__TYPE (REG_UDWORD) -#define R_IRQ_MASK0_SET__GET REG_GET_WO -#define R_IRQ_MASK0_SET__IGET REG_IGET_WO -#define R_IRQ_MASK0_SET__SET REG_SET_WO -#define R_IRQ_MASK0_SET__ISET REG_ISET_WO -#define R_IRQ_MASK0_SET__SET_VAL REG_SET_VAL_WO -#define R_IRQ_MASK0_SET__EQL REG_EQL_WO -#define R_IRQ_MASK0_SET__IEQL REG_IEQL_WO -#define R_IRQ_MASK0_SET__RD REG_RD_WO -#define R_IRQ_MASK0_SET__IRD REG_IRD_WO -#define R_IRQ_MASK0_SET__WR REG_WR_WO -#define R_IRQ_MASK0_SET__IWR REG_IWR_WO - -#define R_IRQ_MASK0_SET__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_IRQ_MASK0_SET__nmi_pin__nmi_pin__MASK 0x80000000U -#define R_IRQ_MASK0_SET__watchdog_nmi__watchdog_nmi__MASK 0x40000000U -#define R_IRQ_MASK0_SET__sqe_test_error__sqe_test_error__MASK 0x20000000U -#define R_IRQ_MASK0_SET__carrier_loss__carrier_loss__MASK 0x10000000U -#define R_IRQ_MASK0_SET__deferred__deferred__MASK 0x08000000U -#define R_IRQ_MASK0_SET__late_col__late_col__MASK 0x04000000U -#define R_IRQ_MASK0_SET__multiple_col__multiple_col__MASK 0x02000000U -#define R_IRQ_MASK0_SET__single_col__single_col__MASK 0x01000000U -#define R_IRQ_MASK0_SET__congestion__congestion__MASK 0x00800000U -#define R_IRQ_MASK0_SET__oversize__oversize__MASK 0x00400000U -#define R_IRQ_MASK0_SET__alignment_error__alignment_error__MASK 0x00200000U -#define R_IRQ_MASK0_SET__crc_error__crc_error__MASK 0x00100000U -#define R_IRQ_MASK0_SET__overrun__overrun__MASK 0x00080000U -#define R_IRQ_MASK0_SET__underrun__underrun__MASK 0x00040000U -#define R_IRQ_MASK0_SET__excessive_col__excessive_col__MASK 0x00020000U -#define R_IRQ_MASK0_SET__mdio__mdio__MASK 0x00010000U -#define R_IRQ_MASK0_SET__ata_drq3__ata_drq3__MASK 0x00008000U -#define R_IRQ_MASK0_SET__ata_drq2__ata_drq2__MASK 0x00004000U -#define R_IRQ_MASK0_SET__ata_drq1__ata_drq1__MASK 0x00002000U -#define R_IRQ_MASK0_SET__ata_drq0__ata_drq0__MASK 0x00001000U -#define R_IRQ_MASK0_SET__par0_ecp_cmd__par0_ecp_cmd__MASK 0x00000800U -#define R_IRQ_MASK0_SET__ata_irq3__ata_irq3__MASK 0x00000800U -#define R_IRQ_MASK0_SET__par0_ecp_cmd__ata_irq3__MASK 0x00000800U -#define R_IRQ_MASK0_SET__par0_peri__par0_peri__MASK 0x00000400U -#define R_IRQ_MASK0_SET__ata_irq2__ata_irq2__MASK 0x00000400U -#define R_IRQ_MASK0_SET__par0_peri__ata_irq2__MASK 0x00000400U -#define R_IRQ_MASK0_SET__par0_data__par0_data__MASK 0x00000200U -#define R_IRQ_MASK0_SET__ata_irq1__ata_irq1__MASK 0x00000200U -#define R_IRQ_MASK0_SET__par0_data__ata_irq1__MASK 0x00000200U -#define R_IRQ_MASK0_SET__par0_ready__par0_ready__MASK 0x00000100U -#define R_IRQ_MASK0_SET__ata_irq0__ata_irq0__MASK 0x00000100U -#define R_IRQ_MASK0_SET__par0_ready__ata_irq0__MASK 0x00000100U -#define R_IRQ_MASK0_SET__mio__mio__MASK 0x00000100U -#define R_IRQ_MASK0_SET__par0_ready__mio__MASK 0x00000100U -#define R_IRQ_MASK0_SET__scsi0__scsi0__MASK 0x00000100U -#define R_IRQ_MASK0_SET__par0_ready__scsi0__MASK 0x00000100U -#define R_IRQ_MASK0_SET__ata_dmaend__ata_dmaend__MASK 0x00000080U -#define R_IRQ_MASK0_SET__irq_ext_vector_nr__irq_ext_vector_nr__MASK 0x00000020U -#define R_IRQ_MASK0_SET__irq_int_vector_nr__irq_int_vector_nr__MASK 0x00000010U -#define R_IRQ_MASK0_SET__ext_dma1__ext_dma1__MASK 0x00000008U -#define R_IRQ_MASK0_SET__ext_dma0__ext_dma0__MASK 0x00000004U -#define R_IRQ_MASK0_SET__timer1__timer1__MASK 0x00000002U -#define R_IRQ_MASK0_SET__timer0__timer0__MASK 0x00000001U - -#define R_IRQ_MASK0_SET__nmi_pin__MAX 0x1 -#define R_IRQ_MASK0_SET__watchdog_nmi__MAX 0x1 -#define R_IRQ_MASK0_SET__sqe_test_error__MAX 0x1 -#define R_IRQ_MASK0_SET__carrier_loss__MAX 0x1 -#define R_IRQ_MASK0_SET__deferred__MAX 0x1 -#define R_IRQ_MASK0_SET__late_col__MAX 0x1 -#define R_IRQ_MASK0_SET__multiple_col__MAX 0x1 -#define R_IRQ_MASK0_SET__single_col__MAX 0x1 -#define R_IRQ_MASK0_SET__congestion__MAX 0x1 -#define R_IRQ_MASK0_SET__oversize__MAX 0x1 -#define R_IRQ_MASK0_SET__alignment_error__MAX 0x1 -#define R_IRQ_MASK0_SET__crc_error__MAX 0x1 -#define R_IRQ_MASK0_SET__overrun__MAX 0x1 -#define R_IRQ_MASK0_SET__underrun__MAX 0x1 -#define R_IRQ_MASK0_SET__excessive_col__MAX 0x1 -#define R_IRQ_MASK0_SET__mdio__MAX 0x1 -#define R_IRQ_MASK0_SET__ata_drq3__MAX 0x1 -#define R_IRQ_MASK0_SET__ata_drq2__MAX 0x1 -#define R_IRQ_MASK0_SET__ata_drq1__MAX 0x1 -#define R_IRQ_MASK0_SET__ata_drq0__MAX 0x1 -#define R_IRQ_MASK0_SET__par0_ecp_cmd__MAX 0x1 -#define R_IRQ_MASK0_SET__ata_irq3__MAX 0x1 -#define R_IRQ_MASK0_SET__par0_peri__MAX 0x1 -#define R_IRQ_MASK0_SET__ata_irq2__MAX 0x1 -#define R_IRQ_MASK0_SET__par0_data__MAX 0x1 -#define R_IRQ_MASK0_SET__ata_irq1__MAX 0x1 -#define R_IRQ_MASK0_SET__par0_ready__MAX 0x1 -#define R_IRQ_MASK0_SET__ata_irq0__MAX 0x1 -#define R_IRQ_MASK0_SET__mio__MAX 0x1 -#define R_IRQ_MASK0_SET__scsi0__MAX 0x1 -#define R_IRQ_MASK0_SET__ata_dmaend__MAX 0x1 -#define R_IRQ_MASK0_SET__irq_ext_vector_nr__MAX 0x1 -#define R_IRQ_MASK0_SET__irq_int_vector_nr__MAX 0x1 -#define R_IRQ_MASK0_SET__ext_dma1__MAX 0x1 -#define R_IRQ_MASK0_SET__ext_dma0__MAX 0x1 -#define R_IRQ_MASK0_SET__timer1__MAX 0x1 -#define R_IRQ_MASK0_SET__timer0__MAX 0x1 - -#define R_IRQ_MASK0_SET__nmi_pin__MIN 0 -#define R_IRQ_MASK0_SET__watchdog_nmi__MIN 0 -#define R_IRQ_MASK0_SET__sqe_test_error__MIN 0 -#define R_IRQ_MASK0_SET__carrier_loss__MIN 0 -#define R_IRQ_MASK0_SET__deferred__MIN 0 -#define R_IRQ_MASK0_SET__late_col__MIN 0 -#define R_IRQ_MASK0_SET__multiple_col__MIN 0 -#define R_IRQ_MASK0_SET__single_col__MIN 0 -#define R_IRQ_MASK0_SET__congestion__MIN 0 -#define R_IRQ_MASK0_SET__oversize__MIN 0 -#define R_IRQ_MASK0_SET__alignment_error__MIN 0 -#define R_IRQ_MASK0_SET__crc_error__MIN 0 -#define R_IRQ_MASK0_SET__overrun__MIN 0 -#define R_IRQ_MASK0_SET__underrun__MIN 0 -#define R_IRQ_MASK0_SET__excessive_col__MIN 0 -#define R_IRQ_MASK0_SET__mdio__MIN 0 -#define R_IRQ_MASK0_SET__ata_drq3__MIN 0 -#define R_IRQ_MASK0_SET__ata_drq2__MIN 0 -#define R_IRQ_MASK0_SET__ata_drq1__MIN 0 -#define R_IRQ_MASK0_SET__ata_drq0__MIN 0 -#define R_IRQ_MASK0_SET__par0_ecp_cmd__MIN 0 -#define R_IRQ_MASK0_SET__ata_irq3__MIN 0 -#define R_IRQ_MASK0_SET__par0_peri__MIN 0 -#define R_IRQ_MASK0_SET__ata_irq2__MIN 0 -#define R_IRQ_MASK0_SET__par0_data__MIN 0 -#define R_IRQ_MASK0_SET__ata_irq1__MIN 0 -#define R_IRQ_MASK0_SET__par0_ready__MIN 0 -#define R_IRQ_MASK0_SET__ata_irq0__MIN 0 -#define R_IRQ_MASK0_SET__mio__MIN 0 -#define R_IRQ_MASK0_SET__scsi0__MIN 0 -#define R_IRQ_MASK0_SET__ata_dmaend__MIN 0 -#define R_IRQ_MASK0_SET__irq_ext_vector_nr__MIN 0 -#define R_IRQ_MASK0_SET__irq_int_vector_nr__MIN 0 -#define R_IRQ_MASK0_SET__ext_dma1__MIN 0 -#define R_IRQ_MASK0_SET__ext_dma0__MIN 0 -#define R_IRQ_MASK0_SET__timer1__MIN 0 -#define R_IRQ_MASK0_SET__timer0__MIN 0 - -#define R_IRQ_MASK0_SET__nmi_pin__BITNR 31 -#define R_IRQ_MASK0_SET__watchdog_nmi__BITNR 30 -#define R_IRQ_MASK0_SET__sqe_test_error__BITNR 29 -#define R_IRQ_MASK0_SET__carrier_loss__BITNR 28 -#define R_IRQ_MASK0_SET__deferred__BITNR 27 -#define R_IRQ_MASK0_SET__late_col__BITNR 26 -#define R_IRQ_MASK0_SET__multiple_col__BITNR 25 -#define R_IRQ_MASK0_SET__single_col__BITNR 24 -#define R_IRQ_MASK0_SET__congestion__BITNR 23 -#define R_IRQ_MASK0_SET__oversize__BITNR 22 -#define R_IRQ_MASK0_SET__alignment_error__BITNR 21 -#define R_IRQ_MASK0_SET__crc_error__BITNR 20 -#define R_IRQ_MASK0_SET__overrun__BITNR 19 -#define R_IRQ_MASK0_SET__underrun__BITNR 18 -#define R_IRQ_MASK0_SET__excessive_col__BITNR 17 -#define R_IRQ_MASK0_SET__mdio__BITNR 16 -#define R_IRQ_MASK0_SET__ata_drq3__BITNR 15 -#define R_IRQ_MASK0_SET__ata_drq2__BITNR 14 -#define R_IRQ_MASK0_SET__ata_drq1__BITNR 13 -#define R_IRQ_MASK0_SET__ata_drq0__BITNR 12 -#define R_IRQ_MASK0_SET__par0_ecp_cmd__BITNR 11 -#define R_IRQ_MASK0_SET__ata_irq3__BITNR 11 -#define R_IRQ_MASK0_SET__par0_peri__BITNR 10 -#define R_IRQ_MASK0_SET__ata_irq2__BITNR 10 -#define R_IRQ_MASK0_SET__par0_data__BITNR 9 -#define R_IRQ_MASK0_SET__ata_irq1__BITNR 9 -#define R_IRQ_MASK0_SET__par0_ready__BITNR 8 -#define R_IRQ_MASK0_SET__ata_irq0__BITNR 8 -#define R_IRQ_MASK0_SET__mio__BITNR 8 -#define R_IRQ_MASK0_SET__scsi0__BITNR 8 -#define R_IRQ_MASK0_SET__ata_dmaend__BITNR 7 -#define R_IRQ_MASK0_SET__irq_ext_vector_nr__BITNR 5 -#define R_IRQ_MASK0_SET__irq_int_vector_nr__BITNR 4 -#define R_IRQ_MASK0_SET__ext_dma1__BITNR 3 -#define R_IRQ_MASK0_SET__ext_dma0__BITNR 2 -#define R_IRQ_MASK0_SET__timer1__BITNR 1 -#define R_IRQ_MASK0_SET__timer0__BITNR 0 - -#define R_IRQ_MASK0_SET__nmi_pin__nmi_pin__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_SET__watchdog_nmi__watchdog_nmi__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_SET__sqe_test_error__sqe_test_error__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_SET__carrier_loss__carrier_loss__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_SET__deferred__deferred__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_SET__late_col__late_col__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_SET__multiple_col__multiple_col__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_SET__single_col__single_col__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_SET__congestion__congestion__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_SET__oversize__oversize__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_SET__alignment_error__alignment_error__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_SET__crc_error__crc_error__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_SET__overrun__overrun__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_SET__underrun__underrun__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_SET__excessive_col__excessive_col__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_SET__mdio__mdio__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_SET__ata_drq3__ata_drq3__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_SET__ata_drq2__ata_drq2__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_SET__ata_drq1__ata_drq1__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_SET__ata_drq0__ata_drq0__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_SET__par0_ecp_cmd__par0_ecp_cmd__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_SET__ata_irq3__ata_irq3__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_SET__par0_ecp_cmd__ata_irq3__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_SET__par0_peri__par0_peri__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_SET__ata_irq2__ata_irq2__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_SET__par0_peri__ata_irq2__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_SET__par0_data__par0_data__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_SET__ata_irq1__ata_irq1__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_SET__par0_data__ata_irq1__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_SET__par0_ready__par0_ready__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_SET__ata_irq0__ata_irq0__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_SET__par0_ready__ata_irq0__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_SET__mio__mio__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_SET__par0_ready__mio__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_SET__scsi0__scsi0__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_SET__par0_ready__scsi0__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_SET__ata_dmaend__ata_dmaend__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_SET__irq_ext_vector_nr__irq_ext_vector_nr__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_SET__irq_int_vector_nr__irq_int_vector_nr__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_SET__ext_dma1__ext_dma1__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_SET__ext_dma0__ext_dma0__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_SET__timer1__timer1__VAL REG_VAL_ENUM -#define R_IRQ_MASK0_SET__timer0__timer0__VAL REG_VAL_ENUM - -#define R_IRQ_MASK0_SET__nmi_pin__nmi_pin__nop 0 -#define R_IRQ_MASK0_SET__nmi_pin__nmi_pin__set 1 -#define R_IRQ_MASK0_SET__watchdog_nmi__watchdog_nmi__nop 0 -#define R_IRQ_MASK0_SET__watchdog_nmi__watchdog_nmi__set 1 -#define R_IRQ_MASK0_SET__sqe_test_error__sqe_test_error__nop 0 -#define R_IRQ_MASK0_SET__sqe_test_error__sqe_test_error__set 1 -#define R_IRQ_MASK0_SET__carrier_loss__carrier_loss__nop 0 -#define R_IRQ_MASK0_SET__carrier_loss__carrier_loss__set 1 -#define R_IRQ_MASK0_SET__deferred__deferred__nop 0 -#define R_IRQ_MASK0_SET__deferred__deferred__set 1 -#define R_IRQ_MASK0_SET__late_col__late_col__nop 0 -#define R_IRQ_MASK0_SET__late_col__late_col__set 1 -#define R_IRQ_MASK0_SET__multiple_col__multiple_col__nop 0 -#define R_IRQ_MASK0_SET__multiple_col__multiple_col__set 1 -#define R_IRQ_MASK0_SET__single_col__single_col__nop 0 -#define R_IRQ_MASK0_SET__single_col__single_col__set 1 -#define R_IRQ_MASK0_SET__congestion__congestion__nop 0 -#define R_IRQ_MASK0_SET__congestion__congestion__set 1 -#define R_IRQ_MASK0_SET__oversize__oversize__nop 0 -#define R_IRQ_MASK0_SET__oversize__oversize__set 1 -#define R_IRQ_MASK0_SET__alignment_error__alignment_error__nop 0 -#define R_IRQ_MASK0_SET__alignment_error__alignment_error__set 1 -#define R_IRQ_MASK0_SET__crc_error__crc_error__nop 0 -#define R_IRQ_MASK0_SET__crc_error__crc_error__set 1 -#define R_IRQ_MASK0_SET__overrun__overrun__nop 0 -#define R_IRQ_MASK0_SET__overrun__overrun__set 1 -#define R_IRQ_MASK0_SET__underrun__underrun__nop 0 -#define R_IRQ_MASK0_SET__underrun__underrun__set 1 -#define R_IRQ_MASK0_SET__excessive_col__excessive_col__nop 0 -#define R_IRQ_MASK0_SET__excessive_col__excessive_col__set 1 -#define R_IRQ_MASK0_SET__mdio__mdio__nop 0 -#define R_IRQ_MASK0_SET__mdio__mdio__set 1 -#define R_IRQ_MASK0_SET__ata_drq3__ata_drq3__nop 0 -#define R_IRQ_MASK0_SET__ata_drq3__ata_drq3__set 1 -#define R_IRQ_MASK0_SET__ata_drq2__ata_drq2__nop 0 -#define R_IRQ_MASK0_SET__ata_drq2__ata_drq2__set 1 -#define R_IRQ_MASK0_SET__ata_drq1__ata_drq1__nop 0 -#define R_IRQ_MASK0_SET__ata_drq1__ata_drq1__set 1 -#define R_IRQ_MASK0_SET__ata_drq0__ata_drq0__nop 0 -#define R_IRQ_MASK0_SET__ata_drq0__ata_drq0__set 1 -#define R_IRQ_MASK0_SET__par0_ecp_cmd__par0_ecp_cmd__nop 0 -#define R_IRQ_MASK0_SET__par0_ecp_cmd__par0_ecp_cmd__set 1 -#define R_IRQ_MASK0_SET__ata_irq3__ata_irq3__nop 0 -#define R_IRQ_MASK0_SET__ata_irq3__ata_irq3__set 1 -#define R_IRQ_MASK0_SET__par0_peri__par0_peri__nop 0 -#define R_IRQ_MASK0_SET__par0_peri__par0_peri__set 1 -#define R_IRQ_MASK0_SET__ata_irq2__ata_irq2__nop 0 -#define R_IRQ_MASK0_SET__ata_irq2__ata_irq2__set 1 -#define R_IRQ_MASK0_SET__par0_data__par0_data__nop 0 -#define R_IRQ_MASK0_SET__par0_data__par0_data__set 1 -#define R_IRQ_MASK0_SET__ata_irq1__ata_irq1__nop 0 -#define R_IRQ_MASK0_SET__ata_irq1__ata_irq1__set 1 -#define R_IRQ_MASK0_SET__par0_ready__par0_ready__nop 0 -#define R_IRQ_MASK0_SET__par0_ready__par0_ready__set 1 -#define R_IRQ_MASK0_SET__ata_irq0__ata_irq0__nop 0 -#define R_IRQ_MASK0_SET__ata_irq0__ata_irq0__set 1 -#define R_IRQ_MASK0_SET__mio__mio__nop 0 -#define R_IRQ_MASK0_SET__mio__mio__set 1 -#define R_IRQ_MASK0_SET__scsi0__scsi0__nop 0 -#define R_IRQ_MASK0_SET__scsi0__scsi0__set 1 -#define R_IRQ_MASK0_SET__ata_dmaend__ata_dmaend__nop 0 -#define R_IRQ_MASK0_SET__ata_dmaend__ata_dmaend__set 1 -#define R_IRQ_MASK0_SET__irq_ext_vector_nr__irq_ext_vector_nr__nop 0 -#define R_IRQ_MASK0_SET__irq_ext_vector_nr__irq_ext_vector_nr__set 1 -#define R_IRQ_MASK0_SET__irq_int_vector_nr__irq_int_vector_nr__nop 0 -#define R_IRQ_MASK0_SET__irq_int_vector_nr__irq_int_vector_nr__set 1 -#define R_IRQ_MASK0_SET__ext_dma1__ext_dma1__nop 0 -#define R_IRQ_MASK0_SET__ext_dma1__ext_dma1__set 1 -#define R_IRQ_MASK0_SET__ext_dma0__ext_dma0__nop 0 -#define R_IRQ_MASK0_SET__ext_dma0__ext_dma0__set 1 -#define R_IRQ_MASK0_SET__timer1__timer1__nop 0 -#define R_IRQ_MASK0_SET__timer1__timer1__set 1 -#define R_IRQ_MASK0_SET__timer0__timer0__nop 0 -#define R_IRQ_MASK0_SET__timer0__timer0__set 1 - -#endif - -/* - * R_IRQ_MASK1_CLR - * - type: WO - * - addr: 0xb00000c8 - * - group: Interrupt mask and status registers - */ - -#if USE_GROUP__Interrupt_mask_and_status_registers - -#define R_IRQ_MASK1_CLR__ADDR (REG_TYPECAST_UDWORD 0xb00000c8) - -#ifndef REG_NO_SHADOW -#define R_IRQ_MASK1_CLR__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_IRQ_MASK1_CLR + 0)) -#define R_IRQ_MASK1_CLR__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_IRQ_MASK1_CLR + 0)) -#else /* REG_NO_SHADOW */ -#define R_IRQ_MASK1_CLR__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_IRQ_MASK1_CLR__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_IRQ_MASK1_CLR__STYPECAST REG_STYPECAST_UDWORD -#define R_IRQ_MASK1_CLR__SVAL REG_SVAL_ZERO -#define R_IRQ_MASK1_CLR__SVAL_I REG_SVAL_I_ZERO -#define R_IRQ_MASK1_CLR__TYPECAST REG_TYPECAST_UDWORD -#define R_IRQ_MASK1_CLR__TYPE (REG_UDWORD) -#define R_IRQ_MASK1_CLR__GET REG_GET_WO -#define R_IRQ_MASK1_CLR__IGET REG_IGET_WO -#define R_IRQ_MASK1_CLR__SET REG_SET_WO -#define R_IRQ_MASK1_CLR__ISET REG_ISET_WO -#define R_IRQ_MASK1_CLR__SET_VAL REG_SET_VAL_WO -#define R_IRQ_MASK1_CLR__EQL REG_EQL_WO -#define R_IRQ_MASK1_CLR__IEQL REG_IEQL_WO -#define R_IRQ_MASK1_CLR__RD REG_RD_WO -#define R_IRQ_MASK1_CLR__IRD REG_IRD_WO -#define R_IRQ_MASK1_CLR__WR REG_WR_WO -#define R_IRQ_MASK1_CLR__IWR REG_IWR_WO - -#define R_IRQ_MASK1_CLR__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_IRQ_MASK1_CLR__sw_int7__sw_int7__MASK 0x80000000U -#define R_IRQ_MASK1_CLR__sw_int6__sw_int6__MASK 0x40000000U -#define R_IRQ_MASK1_CLR__sw_int5__sw_int5__MASK 0x20000000U -#define R_IRQ_MASK1_CLR__sw_int4__sw_int4__MASK 0x10000000U -#define R_IRQ_MASK1_CLR__sw_int3__sw_int3__MASK 0x08000000U -#define R_IRQ_MASK1_CLR__sw_int2__sw_int2__MASK 0x04000000U -#define R_IRQ_MASK1_CLR__sw_int1__sw_int1__MASK 0x02000000U -#define R_IRQ_MASK1_CLR__sw_int0__sw_int0__MASK 0x01000000U -#define R_IRQ_MASK1_CLR__par1_ecp_cmd__par1_ecp_cmd__MASK 0x00080000U -#define R_IRQ_MASK1_CLR__par1_peri__par1_peri__MASK 0x00040000U -#define R_IRQ_MASK1_CLR__par1_data__par1_data__MASK 0x00020000U -#define R_IRQ_MASK1_CLR__par1_ready__par1_ready__MASK 0x00010000U -#define R_IRQ_MASK1_CLR__scsi1__scsi1__MASK 0x00010000U -#define R_IRQ_MASK1_CLR__par1_ready__scsi1__MASK 0x00010000U -#define R_IRQ_MASK1_CLR__ser3_ready__ser3_ready__MASK 0x00008000U -#define R_IRQ_MASK1_CLR__ser3_data__ser3_data__MASK 0x00004000U -#define R_IRQ_MASK1_CLR__ser2_ready__ser2_ready__MASK 0x00002000U -#define R_IRQ_MASK1_CLR__ser2_data__ser2_data__MASK 0x00001000U -#define R_IRQ_MASK1_CLR__ser1_ready__ser1_ready__MASK 0x00000800U -#define R_IRQ_MASK1_CLR__ser1_data__ser1_data__MASK 0x00000400U -#define R_IRQ_MASK1_CLR__ser0_ready__ser0_ready__MASK 0x00000200U -#define R_IRQ_MASK1_CLR__ser0_data__ser0_data__MASK 0x00000100U -#define R_IRQ_MASK1_CLR__pa7__pa7__MASK 0x00000080U -#define R_IRQ_MASK1_CLR__pa6__pa6__MASK 0x00000040U -#define R_IRQ_MASK1_CLR__pa5__pa5__MASK 0x00000020U -#define R_IRQ_MASK1_CLR__pa4__pa4__MASK 0x00000010U -#define R_IRQ_MASK1_CLR__pa3__pa3__MASK 0x00000008U -#define R_IRQ_MASK1_CLR__pa2__pa2__MASK 0x00000004U -#define R_IRQ_MASK1_CLR__pa1__pa1__MASK 0x00000002U -#define R_IRQ_MASK1_CLR__pa0__pa0__MASK 0x00000001U - -#define R_IRQ_MASK1_CLR__sw_int7__MAX 0x1 -#define R_IRQ_MASK1_CLR__sw_int6__MAX 0x1 -#define R_IRQ_MASK1_CLR__sw_int5__MAX 0x1 -#define R_IRQ_MASK1_CLR__sw_int4__MAX 0x1 -#define R_IRQ_MASK1_CLR__sw_int3__MAX 0x1 -#define R_IRQ_MASK1_CLR__sw_int2__MAX 0x1 -#define R_IRQ_MASK1_CLR__sw_int1__MAX 0x1 -#define R_IRQ_MASK1_CLR__sw_int0__MAX 0x1 -#define R_IRQ_MASK1_CLR__par1_ecp_cmd__MAX 0x1 -#define R_IRQ_MASK1_CLR__par1_peri__MAX 0x1 -#define R_IRQ_MASK1_CLR__par1_data__MAX 0x1 -#define R_IRQ_MASK1_CLR__par1_ready__MAX 0x1 -#define R_IRQ_MASK1_CLR__scsi1__MAX 0x1 -#define R_IRQ_MASK1_CLR__ser3_ready__MAX 0x1 -#define R_IRQ_MASK1_CLR__ser3_data__MAX 0x1 -#define R_IRQ_MASK1_CLR__ser2_ready__MAX 0x1 -#define R_IRQ_MASK1_CLR__ser2_data__MAX 0x1 -#define R_IRQ_MASK1_CLR__ser1_ready__MAX 0x1 -#define R_IRQ_MASK1_CLR__ser1_data__MAX 0x1 -#define R_IRQ_MASK1_CLR__ser0_ready__MAX 0x1 -#define R_IRQ_MASK1_CLR__ser0_data__MAX 0x1 -#define R_IRQ_MASK1_CLR__pa7__MAX 0x1 -#define R_IRQ_MASK1_CLR__pa6__MAX 0x1 -#define R_IRQ_MASK1_CLR__pa5__MAX 0x1 -#define R_IRQ_MASK1_CLR__pa4__MAX 0x1 -#define R_IRQ_MASK1_CLR__pa3__MAX 0x1 -#define R_IRQ_MASK1_CLR__pa2__MAX 0x1 -#define R_IRQ_MASK1_CLR__pa1__MAX 0x1 -#define R_IRQ_MASK1_CLR__pa0__MAX 0x1 - -#define R_IRQ_MASK1_CLR__sw_int7__MIN 0 -#define R_IRQ_MASK1_CLR__sw_int6__MIN 0 -#define R_IRQ_MASK1_CLR__sw_int5__MIN 0 -#define R_IRQ_MASK1_CLR__sw_int4__MIN 0 -#define R_IRQ_MASK1_CLR__sw_int3__MIN 0 -#define R_IRQ_MASK1_CLR__sw_int2__MIN 0 -#define R_IRQ_MASK1_CLR__sw_int1__MIN 0 -#define R_IRQ_MASK1_CLR__sw_int0__MIN 0 -#define R_IRQ_MASK1_CLR__par1_ecp_cmd__MIN 0 -#define R_IRQ_MASK1_CLR__par1_peri__MIN 0 -#define R_IRQ_MASK1_CLR__par1_data__MIN 0 -#define R_IRQ_MASK1_CLR__par1_ready__MIN 0 -#define R_IRQ_MASK1_CLR__scsi1__MIN 0 -#define R_IRQ_MASK1_CLR__ser3_ready__MIN 0 -#define R_IRQ_MASK1_CLR__ser3_data__MIN 0 -#define R_IRQ_MASK1_CLR__ser2_ready__MIN 0 -#define R_IRQ_MASK1_CLR__ser2_data__MIN 0 -#define R_IRQ_MASK1_CLR__ser1_ready__MIN 0 -#define R_IRQ_MASK1_CLR__ser1_data__MIN 0 -#define R_IRQ_MASK1_CLR__ser0_ready__MIN 0 -#define R_IRQ_MASK1_CLR__ser0_data__MIN 0 -#define R_IRQ_MASK1_CLR__pa7__MIN 0 -#define R_IRQ_MASK1_CLR__pa6__MIN 0 -#define R_IRQ_MASK1_CLR__pa5__MIN 0 -#define R_IRQ_MASK1_CLR__pa4__MIN 0 -#define R_IRQ_MASK1_CLR__pa3__MIN 0 -#define R_IRQ_MASK1_CLR__pa2__MIN 0 -#define R_IRQ_MASK1_CLR__pa1__MIN 0 -#define R_IRQ_MASK1_CLR__pa0__MIN 0 - -#define R_IRQ_MASK1_CLR__sw_int7__BITNR 31 -#define R_IRQ_MASK1_CLR__sw_int6__BITNR 30 -#define R_IRQ_MASK1_CLR__sw_int5__BITNR 29 -#define R_IRQ_MASK1_CLR__sw_int4__BITNR 28 -#define R_IRQ_MASK1_CLR__sw_int3__BITNR 27 -#define R_IRQ_MASK1_CLR__sw_int2__BITNR 26 -#define R_IRQ_MASK1_CLR__sw_int1__BITNR 25 -#define R_IRQ_MASK1_CLR__sw_int0__BITNR 24 -#define R_IRQ_MASK1_CLR__par1_ecp_cmd__BITNR 19 -#define R_IRQ_MASK1_CLR__par1_peri__BITNR 18 -#define R_IRQ_MASK1_CLR__par1_data__BITNR 17 -#define R_IRQ_MASK1_CLR__par1_ready__BITNR 16 -#define R_IRQ_MASK1_CLR__scsi1__BITNR 16 -#define R_IRQ_MASK1_CLR__ser3_ready__BITNR 15 -#define R_IRQ_MASK1_CLR__ser3_data__BITNR 14 -#define R_IRQ_MASK1_CLR__ser2_ready__BITNR 13 -#define R_IRQ_MASK1_CLR__ser2_data__BITNR 12 -#define R_IRQ_MASK1_CLR__ser1_ready__BITNR 11 -#define R_IRQ_MASK1_CLR__ser1_data__BITNR 10 -#define R_IRQ_MASK1_CLR__ser0_ready__BITNR 9 -#define R_IRQ_MASK1_CLR__ser0_data__BITNR 8 -#define R_IRQ_MASK1_CLR__pa7__BITNR 7 -#define R_IRQ_MASK1_CLR__pa6__BITNR 6 -#define R_IRQ_MASK1_CLR__pa5__BITNR 5 -#define R_IRQ_MASK1_CLR__pa4__BITNR 4 -#define R_IRQ_MASK1_CLR__pa3__BITNR 3 -#define R_IRQ_MASK1_CLR__pa2__BITNR 2 -#define R_IRQ_MASK1_CLR__pa1__BITNR 1 -#define R_IRQ_MASK1_CLR__pa0__BITNR 0 - -#define R_IRQ_MASK1_CLR__sw_int7__sw_int7__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_CLR__sw_int6__sw_int6__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_CLR__sw_int5__sw_int5__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_CLR__sw_int4__sw_int4__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_CLR__sw_int3__sw_int3__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_CLR__sw_int2__sw_int2__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_CLR__sw_int1__sw_int1__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_CLR__sw_int0__sw_int0__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_CLR__par1_ecp_cmd__par1_ecp_cmd__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_CLR__par1_peri__par1_peri__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_CLR__par1_data__par1_data__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_CLR__par1_ready__par1_ready__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_CLR__scsi1__scsi1__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_CLR__par1_ready__scsi1__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_CLR__ser3_ready__ser3_ready__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_CLR__ser3_data__ser3_data__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_CLR__ser2_ready__ser2_ready__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_CLR__ser2_data__ser2_data__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_CLR__ser1_ready__ser1_ready__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_CLR__ser1_data__ser1_data__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_CLR__ser0_ready__ser0_ready__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_CLR__ser0_data__ser0_data__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_CLR__pa7__pa7__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_CLR__pa6__pa6__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_CLR__pa5__pa5__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_CLR__pa4__pa4__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_CLR__pa3__pa3__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_CLR__pa2__pa2__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_CLR__pa1__pa1__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_CLR__pa0__pa0__VAL REG_VAL_ENUM - -#define R_IRQ_MASK1_CLR__sw_int7__sw_int7__clr 1 -#define R_IRQ_MASK1_CLR__sw_int7__sw_int7__nop 0 -#define R_IRQ_MASK1_CLR__sw_int6__sw_int6__clr 1 -#define R_IRQ_MASK1_CLR__sw_int6__sw_int6__nop 0 -#define R_IRQ_MASK1_CLR__sw_int5__sw_int5__clr 1 -#define R_IRQ_MASK1_CLR__sw_int5__sw_int5__nop 0 -#define R_IRQ_MASK1_CLR__sw_int4__sw_int4__clr 1 -#define R_IRQ_MASK1_CLR__sw_int4__sw_int4__nop 0 -#define R_IRQ_MASK1_CLR__sw_int3__sw_int3__clr 1 -#define R_IRQ_MASK1_CLR__sw_int3__sw_int3__nop 0 -#define R_IRQ_MASK1_CLR__sw_int2__sw_int2__clr 1 -#define R_IRQ_MASK1_CLR__sw_int2__sw_int2__nop 0 -#define R_IRQ_MASK1_CLR__sw_int1__sw_int1__clr 1 -#define R_IRQ_MASK1_CLR__sw_int1__sw_int1__nop 0 -#define R_IRQ_MASK1_CLR__sw_int0__sw_int0__clr 1 -#define R_IRQ_MASK1_CLR__sw_int0__sw_int0__nop 0 -#define R_IRQ_MASK1_CLR__par1_ecp_cmd__par1_ecp_cmd__clr 1 -#define R_IRQ_MASK1_CLR__par1_ecp_cmd__par1_ecp_cmd__nop 0 -#define R_IRQ_MASK1_CLR__par1_peri__par1_peri__clr 1 -#define R_IRQ_MASK1_CLR__par1_peri__par1_peri__nop 0 -#define R_IRQ_MASK1_CLR__par1_data__par1_data__clr 1 -#define R_IRQ_MASK1_CLR__par1_data__par1_data__nop 0 -#define R_IRQ_MASK1_CLR__par1_ready__par1_ready__clr 1 -#define R_IRQ_MASK1_CLR__par1_ready__par1_ready__nop 0 -#define R_IRQ_MASK1_CLR__scsi1__scsi1__clr 1 -#define R_IRQ_MASK1_CLR__scsi1__scsi1__nop 0 -#define R_IRQ_MASK1_CLR__ser3_ready__ser3_ready__clr 1 -#define R_IRQ_MASK1_CLR__ser3_ready__ser3_ready__nop 0 -#define R_IRQ_MASK1_CLR__ser3_data__ser3_data__clr 1 -#define R_IRQ_MASK1_CLR__ser3_data__ser3_data__nop 0 -#define R_IRQ_MASK1_CLR__ser2_ready__ser2_ready__clr 1 -#define R_IRQ_MASK1_CLR__ser2_ready__ser2_ready__nop 0 -#define R_IRQ_MASK1_CLR__ser2_data__ser2_data__clr 1 -#define R_IRQ_MASK1_CLR__ser2_data__ser2_data__nop 0 -#define R_IRQ_MASK1_CLR__ser1_ready__ser1_ready__clr 1 -#define R_IRQ_MASK1_CLR__ser1_ready__ser1_ready__nop 0 -#define R_IRQ_MASK1_CLR__ser1_data__ser1_data__clr 1 -#define R_IRQ_MASK1_CLR__ser1_data__ser1_data__nop 0 -#define R_IRQ_MASK1_CLR__ser0_ready__ser0_ready__clr 1 -#define R_IRQ_MASK1_CLR__ser0_ready__ser0_ready__nop 0 -#define R_IRQ_MASK1_CLR__ser0_data__ser0_data__clr 1 -#define R_IRQ_MASK1_CLR__ser0_data__ser0_data__nop 0 -#define R_IRQ_MASK1_CLR__pa7__pa7__clr 1 -#define R_IRQ_MASK1_CLR__pa7__pa7__nop 0 -#define R_IRQ_MASK1_CLR__pa6__pa6__clr 1 -#define R_IRQ_MASK1_CLR__pa6__pa6__nop 0 -#define R_IRQ_MASK1_CLR__pa5__pa5__clr 1 -#define R_IRQ_MASK1_CLR__pa5__pa5__nop 0 -#define R_IRQ_MASK1_CLR__pa4__pa4__clr 1 -#define R_IRQ_MASK1_CLR__pa4__pa4__nop 0 -#define R_IRQ_MASK1_CLR__pa3__pa3__clr 1 -#define R_IRQ_MASK1_CLR__pa3__pa3__nop 0 -#define R_IRQ_MASK1_CLR__pa2__pa2__clr 1 -#define R_IRQ_MASK1_CLR__pa2__pa2__nop 0 -#define R_IRQ_MASK1_CLR__pa1__pa1__clr 1 -#define R_IRQ_MASK1_CLR__pa1__pa1__nop 0 -#define R_IRQ_MASK1_CLR__pa0__pa0__clr 1 -#define R_IRQ_MASK1_CLR__pa0__pa0__nop 0 - -#endif - -/* - * R_IRQ_MASK1_RD - * - type: RO - * - addr: 0xb00000c8 - * - group: Interrupt mask and status registers - */ - -#if USE_GROUP__Interrupt_mask_and_status_registers - -#define R_IRQ_MASK1_RD__ADDR (REG_TYPECAST_UDWORD 0xb00000c8) -#define R_IRQ_MASK1_RD__SVAL REG_SVAL_SHADOW -#define R_IRQ_MASK1_RD__SVAL_I REG_SVAL_I_SHADOW -#define R_IRQ_MASK1_RD__TYPECAST REG_TYPECAST_UDWORD -#define R_IRQ_MASK1_RD__TYPE (REG_UDWORD) -#define R_IRQ_MASK1_RD__GET REG_GET_RO -#define R_IRQ_MASK1_RD__IGET REG_IGET_RO -#define R_IRQ_MASK1_RD__SET REG_SET_RO -#define R_IRQ_MASK1_RD__ISET REG_ISET_RO -#define R_IRQ_MASK1_RD__SET_VAL REG_SET_VAL_RO -#define R_IRQ_MASK1_RD__EQL REG_EQL_RO -#define R_IRQ_MASK1_RD__IEQL REG_IEQL_RO -#define R_IRQ_MASK1_RD__RD REG_RD_RO -#define R_IRQ_MASK1_RD__IRD REG_IRD_RO -#define R_IRQ_MASK1_RD__WR REG_WR_RO -#define R_IRQ_MASK1_RD__IWR REG_IWR_RO - -#define R_IRQ_MASK1_RD__READ(addr) \ - (*(addr)) - -#define R_IRQ_MASK1_RD__sw_int7__sw_int7__MASK 0x80000000U -#define R_IRQ_MASK1_RD__sw_int6__sw_int6__MASK 0x40000000U -#define R_IRQ_MASK1_RD__sw_int5__sw_int5__MASK 0x20000000U -#define R_IRQ_MASK1_RD__sw_int4__sw_int4__MASK 0x10000000U -#define R_IRQ_MASK1_RD__sw_int3__sw_int3__MASK 0x08000000U -#define R_IRQ_MASK1_RD__sw_int2__sw_int2__MASK 0x04000000U -#define R_IRQ_MASK1_RD__sw_int1__sw_int1__MASK 0x02000000U -#define R_IRQ_MASK1_RD__sw_int0__sw_int0__MASK 0x01000000U -#define R_IRQ_MASK1_RD__par1_ecp_cmd__par1_ecp_cmd__MASK 0x00080000U -#define R_IRQ_MASK1_RD__par1_peri__par1_peri__MASK 0x00040000U -#define R_IRQ_MASK1_RD__par1_data__par1_data__MASK 0x00020000U -#define R_IRQ_MASK1_RD__par1_ready__par1_ready__MASK 0x00010000U -#define R_IRQ_MASK1_RD__scsi1__scsi1__MASK 0x00010000U -#define R_IRQ_MASK1_RD__par1_ready__scsi1__MASK 0x00010000U -#define R_IRQ_MASK1_RD__ser3_ready__ser3_ready__MASK 0x00008000U -#define R_IRQ_MASK1_RD__ser3_data__ser3_data__MASK 0x00004000U -#define R_IRQ_MASK1_RD__ser2_ready__ser2_ready__MASK 0x00002000U -#define R_IRQ_MASK1_RD__ser2_data__ser2_data__MASK 0x00001000U -#define R_IRQ_MASK1_RD__ser1_ready__ser1_ready__MASK 0x00000800U -#define R_IRQ_MASK1_RD__ser1_data__ser1_data__MASK 0x00000400U -#define R_IRQ_MASK1_RD__ser0_ready__ser0_ready__MASK 0x00000200U -#define R_IRQ_MASK1_RD__ser0_data__ser0_data__MASK 0x00000100U -#define R_IRQ_MASK1_RD__pa7__pa7__MASK 0x00000080U -#define R_IRQ_MASK1_RD__pa6__pa6__MASK 0x00000040U -#define R_IRQ_MASK1_RD__pa5__pa5__MASK 0x00000020U -#define R_IRQ_MASK1_RD__pa4__pa4__MASK 0x00000010U -#define R_IRQ_MASK1_RD__pa3__pa3__MASK 0x00000008U -#define R_IRQ_MASK1_RD__pa2__pa2__MASK 0x00000004U -#define R_IRQ_MASK1_RD__pa1__pa1__MASK 0x00000002U -#define R_IRQ_MASK1_RD__pa0__pa0__MASK 0x00000001U - -#define R_IRQ_MASK1_RD__sw_int7__MAX 0x1 -#define R_IRQ_MASK1_RD__sw_int6__MAX 0x1 -#define R_IRQ_MASK1_RD__sw_int5__MAX 0x1 -#define R_IRQ_MASK1_RD__sw_int4__MAX 0x1 -#define R_IRQ_MASK1_RD__sw_int3__MAX 0x1 -#define R_IRQ_MASK1_RD__sw_int2__MAX 0x1 -#define R_IRQ_MASK1_RD__sw_int1__MAX 0x1 -#define R_IRQ_MASK1_RD__sw_int0__MAX 0x1 -#define R_IRQ_MASK1_RD__par1_ecp_cmd__MAX 0x1 -#define R_IRQ_MASK1_RD__par1_peri__MAX 0x1 -#define R_IRQ_MASK1_RD__par1_data__MAX 0x1 -#define R_IRQ_MASK1_RD__par1_ready__MAX 0x1 -#define R_IRQ_MASK1_RD__scsi1__MAX 0x1 -#define R_IRQ_MASK1_RD__ser3_ready__MAX 0x1 -#define R_IRQ_MASK1_RD__ser3_data__MAX 0x1 -#define R_IRQ_MASK1_RD__ser2_ready__MAX 0x1 -#define R_IRQ_MASK1_RD__ser2_data__MAX 0x1 -#define R_IRQ_MASK1_RD__ser1_ready__MAX 0x1 -#define R_IRQ_MASK1_RD__ser1_data__MAX 0x1 -#define R_IRQ_MASK1_RD__ser0_ready__MAX 0x1 -#define R_IRQ_MASK1_RD__ser0_data__MAX 0x1 -#define R_IRQ_MASK1_RD__pa7__MAX 0x1 -#define R_IRQ_MASK1_RD__pa6__MAX 0x1 -#define R_IRQ_MASK1_RD__pa5__MAX 0x1 -#define R_IRQ_MASK1_RD__pa4__MAX 0x1 -#define R_IRQ_MASK1_RD__pa3__MAX 0x1 -#define R_IRQ_MASK1_RD__pa2__MAX 0x1 -#define R_IRQ_MASK1_RD__pa1__MAX 0x1 -#define R_IRQ_MASK1_RD__pa0__MAX 0x1 - -#define R_IRQ_MASK1_RD__sw_int7__MIN 0 -#define R_IRQ_MASK1_RD__sw_int6__MIN 0 -#define R_IRQ_MASK1_RD__sw_int5__MIN 0 -#define R_IRQ_MASK1_RD__sw_int4__MIN 0 -#define R_IRQ_MASK1_RD__sw_int3__MIN 0 -#define R_IRQ_MASK1_RD__sw_int2__MIN 0 -#define R_IRQ_MASK1_RD__sw_int1__MIN 0 -#define R_IRQ_MASK1_RD__sw_int0__MIN 0 -#define R_IRQ_MASK1_RD__par1_ecp_cmd__MIN 0 -#define R_IRQ_MASK1_RD__par1_peri__MIN 0 -#define R_IRQ_MASK1_RD__par1_data__MIN 0 -#define R_IRQ_MASK1_RD__par1_ready__MIN 0 -#define R_IRQ_MASK1_RD__scsi1__MIN 0 -#define R_IRQ_MASK1_RD__ser3_ready__MIN 0 -#define R_IRQ_MASK1_RD__ser3_data__MIN 0 -#define R_IRQ_MASK1_RD__ser2_ready__MIN 0 -#define R_IRQ_MASK1_RD__ser2_data__MIN 0 -#define R_IRQ_MASK1_RD__ser1_ready__MIN 0 -#define R_IRQ_MASK1_RD__ser1_data__MIN 0 -#define R_IRQ_MASK1_RD__ser0_ready__MIN 0 -#define R_IRQ_MASK1_RD__ser0_data__MIN 0 -#define R_IRQ_MASK1_RD__pa7__MIN 0 -#define R_IRQ_MASK1_RD__pa6__MIN 0 -#define R_IRQ_MASK1_RD__pa5__MIN 0 -#define R_IRQ_MASK1_RD__pa4__MIN 0 -#define R_IRQ_MASK1_RD__pa3__MIN 0 -#define R_IRQ_MASK1_RD__pa2__MIN 0 -#define R_IRQ_MASK1_RD__pa1__MIN 0 -#define R_IRQ_MASK1_RD__pa0__MIN 0 - -#define R_IRQ_MASK1_RD__sw_int7__BITNR 31 -#define R_IRQ_MASK1_RD__sw_int6__BITNR 30 -#define R_IRQ_MASK1_RD__sw_int5__BITNR 29 -#define R_IRQ_MASK1_RD__sw_int4__BITNR 28 -#define R_IRQ_MASK1_RD__sw_int3__BITNR 27 -#define R_IRQ_MASK1_RD__sw_int2__BITNR 26 -#define R_IRQ_MASK1_RD__sw_int1__BITNR 25 -#define R_IRQ_MASK1_RD__sw_int0__BITNR 24 -#define R_IRQ_MASK1_RD__par1_ecp_cmd__BITNR 19 -#define R_IRQ_MASK1_RD__par1_peri__BITNR 18 -#define R_IRQ_MASK1_RD__par1_data__BITNR 17 -#define R_IRQ_MASK1_RD__par1_ready__BITNR 16 -#define R_IRQ_MASK1_RD__scsi1__BITNR 16 -#define R_IRQ_MASK1_RD__ser3_ready__BITNR 15 -#define R_IRQ_MASK1_RD__ser3_data__BITNR 14 -#define R_IRQ_MASK1_RD__ser2_ready__BITNR 13 -#define R_IRQ_MASK1_RD__ser2_data__BITNR 12 -#define R_IRQ_MASK1_RD__ser1_ready__BITNR 11 -#define R_IRQ_MASK1_RD__ser1_data__BITNR 10 -#define R_IRQ_MASK1_RD__ser0_ready__BITNR 9 -#define R_IRQ_MASK1_RD__ser0_data__BITNR 8 -#define R_IRQ_MASK1_RD__pa7__BITNR 7 -#define R_IRQ_MASK1_RD__pa6__BITNR 6 -#define R_IRQ_MASK1_RD__pa5__BITNR 5 -#define R_IRQ_MASK1_RD__pa4__BITNR 4 -#define R_IRQ_MASK1_RD__pa3__BITNR 3 -#define R_IRQ_MASK1_RD__pa2__BITNR 2 -#define R_IRQ_MASK1_RD__pa1__BITNR 1 -#define R_IRQ_MASK1_RD__pa0__BITNR 0 - -#define R_IRQ_MASK1_RD__sw_int7__sw_int7__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_RD__sw_int6__sw_int6__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_RD__sw_int5__sw_int5__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_RD__sw_int4__sw_int4__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_RD__sw_int3__sw_int3__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_RD__sw_int2__sw_int2__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_RD__sw_int1__sw_int1__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_RD__sw_int0__sw_int0__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_RD__par1_ecp_cmd__par1_ecp_cmd__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_RD__par1_peri__par1_peri__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_RD__par1_data__par1_data__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_RD__par1_ready__par1_ready__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_RD__scsi1__scsi1__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_RD__par1_ready__scsi1__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_RD__ser3_ready__ser3_ready__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_RD__ser3_data__ser3_data__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_RD__ser2_ready__ser2_ready__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_RD__ser2_data__ser2_data__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_RD__ser1_ready__ser1_ready__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_RD__ser1_data__ser1_data__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_RD__ser0_ready__ser0_ready__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_RD__ser0_data__ser0_data__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_RD__pa7__pa7__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_RD__pa6__pa6__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_RD__pa5__pa5__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_RD__pa4__pa4__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_RD__pa3__pa3__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_RD__pa2__pa2__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_RD__pa1__pa1__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_RD__pa0__pa0__VAL REG_VAL_ENUM - -#define R_IRQ_MASK1_RD__sw_int7__sw_int7__active 1 -#define R_IRQ_MASK1_RD__sw_int7__sw_int7__inactive 0 -#define R_IRQ_MASK1_RD__sw_int6__sw_int6__active 1 -#define R_IRQ_MASK1_RD__sw_int6__sw_int6__inactive 0 -#define R_IRQ_MASK1_RD__sw_int5__sw_int5__active 1 -#define R_IRQ_MASK1_RD__sw_int5__sw_int5__inactive 0 -#define R_IRQ_MASK1_RD__sw_int4__sw_int4__active 1 -#define R_IRQ_MASK1_RD__sw_int4__sw_int4__inactive 0 -#define R_IRQ_MASK1_RD__sw_int3__sw_int3__active 1 -#define R_IRQ_MASK1_RD__sw_int3__sw_int3__inactive 0 -#define R_IRQ_MASK1_RD__sw_int2__sw_int2__active 1 -#define R_IRQ_MASK1_RD__sw_int2__sw_int2__inactive 0 -#define R_IRQ_MASK1_RD__sw_int1__sw_int1__active 1 -#define R_IRQ_MASK1_RD__sw_int1__sw_int1__inactive 0 -#define R_IRQ_MASK1_RD__sw_int0__sw_int0__active 1 -#define R_IRQ_MASK1_RD__sw_int0__sw_int0__inactive 0 -#define R_IRQ_MASK1_RD__par1_ecp_cmd__par1_ecp_cmd__active 1 -#define R_IRQ_MASK1_RD__par1_ecp_cmd__par1_ecp_cmd__inactive 0 -#define R_IRQ_MASK1_RD__par1_peri__par1_peri__active 1 -#define R_IRQ_MASK1_RD__par1_peri__par1_peri__inactive 0 -#define R_IRQ_MASK1_RD__par1_data__par1_data__active 1 -#define R_IRQ_MASK1_RD__par1_data__par1_data__inactive 0 -#define R_IRQ_MASK1_RD__par1_ready__par1_ready__active 1 -#define R_IRQ_MASK1_RD__par1_ready__par1_ready__inactive 0 -#define R_IRQ_MASK1_RD__scsi1__scsi1__active 1 -#define R_IRQ_MASK1_RD__scsi1__scsi1__inactive 0 -#define R_IRQ_MASK1_RD__ser3_ready__ser3_ready__active 1 -#define R_IRQ_MASK1_RD__ser3_ready__ser3_ready__inactive 0 -#define R_IRQ_MASK1_RD__ser3_data__ser3_data__active 1 -#define R_IRQ_MASK1_RD__ser3_data__ser3_data__inactive 0 -#define R_IRQ_MASK1_RD__ser2_ready__ser2_ready__active 1 -#define R_IRQ_MASK1_RD__ser2_ready__ser2_ready__inactive 0 -#define R_IRQ_MASK1_RD__ser2_data__ser2_data__active 1 -#define R_IRQ_MASK1_RD__ser2_data__ser2_data__inactive 0 -#define R_IRQ_MASK1_RD__ser1_ready__ser1_ready__active 1 -#define R_IRQ_MASK1_RD__ser1_ready__ser1_ready__inactive 0 -#define R_IRQ_MASK1_RD__ser1_data__ser1_data__active 1 -#define R_IRQ_MASK1_RD__ser1_data__ser1_data__inactive 0 -#define R_IRQ_MASK1_RD__ser0_ready__ser0_ready__active 1 -#define R_IRQ_MASK1_RD__ser0_ready__ser0_ready__inactive 0 -#define R_IRQ_MASK1_RD__ser0_data__ser0_data__active 1 -#define R_IRQ_MASK1_RD__ser0_data__ser0_data__inactive 0 -#define R_IRQ_MASK1_RD__pa7__pa7__active 1 -#define R_IRQ_MASK1_RD__pa7__pa7__inactive 0 -#define R_IRQ_MASK1_RD__pa6__pa6__active 1 -#define R_IRQ_MASK1_RD__pa6__pa6__inactive 0 -#define R_IRQ_MASK1_RD__pa5__pa5__active 1 -#define R_IRQ_MASK1_RD__pa5__pa5__inactive 0 -#define R_IRQ_MASK1_RD__pa4__pa4__active 1 -#define R_IRQ_MASK1_RD__pa4__pa4__inactive 0 -#define R_IRQ_MASK1_RD__pa3__pa3__active 1 -#define R_IRQ_MASK1_RD__pa3__pa3__inactive 0 -#define R_IRQ_MASK1_RD__pa2__pa2__active 1 -#define R_IRQ_MASK1_RD__pa2__pa2__inactive 0 -#define R_IRQ_MASK1_RD__pa1__pa1__active 1 -#define R_IRQ_MASK1_RD__pa1__pa1__inactive 0 -#define R_IRQ_MASK1_RD__pa0__pa0__active 1 -#define R_IRQ_MASK1_RD__pa0__pa0__inactive 0 - -#endif - -/* - * R_IRQ_MASK1_SET - * - type: WO - * - addr: 0xb00000cc - * - group: Interrupt mask and status registers - */ - -#if USE_GROUP__Interrupt_mask_and_status_registers - -#define R_IRQ_MASK1_SET__ADDR (REG_TYPECAST_UDWORD 0xb00000cc) - -#ifndef REG_NO_SHADOW -#define R_IRQ_MASK1_SET__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_IRQ_MASK1_SET + 0)) -#define R_IRQ_MASK1_SET__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_IRQ_MASK1_SET + 0)) -#else /* REG_NO_SHADOW */ -#define R_IRQ_MASK1_SET__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_IRQ_MASK1_SET__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_IRQ_MASK1_SET__STYPECAST REG_STYPECAST_UDWORD -#define R_IRQ_MASK1_SET__SVAL REG_SVAL_ZERO -#define R_IRQ_MASK1_SET__SVAL_I REG_SVAL_I_ZERO -#define R_IRQ_MASK1_SET__TYPECAST REG_TYPECAST_UDWORD -#define R_IRQ_MASK1_SET__TYPE (REG_UDWORD) -#define R_IRQ_MASK1_SET__GET REG_GET_WO -#define R_IRQ_MASK1_SET__IGET REG_IGET_WO -#define R_IRQ_MASK1_SET__SET REG_SET_WO -#define R_IRQ_MASK1_SET__ISET REG_ISET_WO -#define R_IRQ_MASK1_SET__SET_VAL REG_SET_VAL_WO -#define R_IRQ_MASK1_SET__EQL REG_EQL_WO -#define R_IRQ_MASK1_SET__IEQL REG_IEQL_WO -#define R_IRQ_MASK1_SET__RD REG_RD_WO -#define R_IRQ_MASK1_SET__IRD REG_IRD_WO -#define R_IRQ_MASK1_SET__WR REG_WR_WO -#define R_IRQ_MASK1_SET__IWR REG_IWR_WO - -#define R_IRQ_MASK1_SET__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_IRQ_MASK1_SET__sw_int7__sw_int7__MASK 0x80000000U -#define R_IRQ_MASK1_SET__sw_int6__sw_int6__MASK 0x40000000U -#define R_IRQ_MASK1_SET__sw_int5__sw_int5__MASK 0x20000000U -#define R_IRQ_MASK1_SET__sw_int4__sw_int4__MASK 0x10000000U -#define R_IRQ_MASK1_SET__sw_int3__sw_int3__MASK 0x08000000U -#define R_IRQ_MASK1_SET__sw_int2__sw_int2__MASK 0x04000000U -#define R_IRQ_MASK1_SET__sw_int1__sw_int1__MASK 0x02000000U -#define R_IRQ_MASK1_SET__sw_int0__sw_int0__MASK 0x01000000U -#define R_IRQ_MASK1_SET__par1_ecp_cmd__par1_ecp_cmd__MASK 0x00080000U -#define R_IRQ_MASK1_SET__par1_peri__par1_peri__MASK 0x00040000U -#define R_IRQ_MASK1_SET__par1_data__par1_data__MASK 0x00020000U -#define R_IRQ_MASK1_SET__par1_ready__par1_ready__MASK 0x00010000U -#define R_IRQ_MASK1_SET__scsi1__scsi1__MASK 0x00010000U -#define R_IRQ_MASK1_SET__par1_ready__scsi1__MASK 0x00010000U -#define R_IRQ_MASK1_SET__ser3_ready__ser3_ready__MASK 0x00008000U -#define R_IRQ_MASK1_SET__ser3_data__ser3_data__MASK 0x00004000U -#define R_IRQ_MASK1_SET__ser2_ready__ser2_ready__MASK 0x00002000U -#define R_IRQ_MASK1_SET__ser2_data__ser2_data__MASK 0x00001000U -#define R_IRQ_MASK1_SET__ser1_ready__ser1_ready__MASK 0x00000800U -#define R_IRQ_MASK1_SET__ser1_data__ser1_data__MASK 0x00000400U -#define R_IRQ_MASK1_SET__ser0_ready__ser0_ready__MASK 0x00000200U -#define R_IRQ_MASK1_SET__ser0_data__ser0_data__MASK 0x00000100U -#define R_IRQ_MASK1_SET__pa7__pa7__MASK 0x00000080U -#define R_IRQ_MASK1_SET__pa6__pa6__MASK 0x00000040U -#define R_IRQ_MASK1_SET__pa5__pa5__MASK 0x00000020U -#define R_IRQ_MASK1_SET__pa4__pa4__MASK 0x00000010U -#define R_IRQ_MASK1_SET__pa3__pa3__MASK 0x00000008U -#define R_IRQ_MASK1_SET__pa2__pa2__MASK 0x00000004U -#define R_IRQ_MASK1_SET__pa1__pa1__MASK 0x00000002U -#define R_IRQ_MASK1_SET__pa0__pa0__MASK 0x00000001U - -#define R_IRQ_MASK1_SET__sw_int7__MAX 0x1 -#define R_IRQ_MASK1_SET__sw_int6__MAX 0x1 -#define R_IRQ_MASK1_SET__sw_int5__MAX 0x1 -#define R_IRQ_MASK1_SET__sw_int4__MAX 0x1 -#define R_IRQ_MASK1_SET__sw_int3__MAX 0x1 -#define R_IRQ_MASK1_SET__sw_int2__MAX 0x1 -#define R_IRQ_MASK1_SET__sw_int1__MAX 0x1 -#define R_IRQ_MASK1_SET__sw_int0__MAX 0x1 -#define R_IRQ_MASK1_SET__par1_ecp_cmd__MAX 0x1 -#define R_IRQ_MASK1_SET__par1_peri__MAX 0x1 -#define R_IRQ_MASK1_SET__par1_data__MAX 0x1 -#define R_IRQ_MASK1_SET__par1_ready__MAX 0x1 -#define R_IRQ_MASK1_SET__scsi1__MAX 0x1 -#define R_IRQ_MASK1_SET__ser3_ready__MAX 0x1 -#define R_IRQ_MASK1_SET__ser3_data__MAX 0x1 -#define R_IRQ_MASK1_SET__ser2_ready__MAX 0x1 -#define R_IRQ_MASK1_SET__ser2_data__MAX 0x1 -#define R_IRQ_MASK1_SET__ser1_ready__MAX 0x1 -#define R_IRQ_MASK1_SET__ser1_data__MAX 0x1 -#define R_IRQ_MASK1_SET__ser0_ready__MAX 0x1 -#define R_IRQ_MASK1_SET__ser0_data__MAX 0x1 -#define R_IRQ_MASK1_SET__pa7__MAX 0x1 -#define R_IRQ_MASK1_SET__pa6__MAX 0x1 -#define R_IRQ_MASK1_SET__pa5__MAX 0x1 -#define R_IRQ_MASK1_SET__pa4__MAX 0x1 -#define R_IRQ_MASK1_SET__pa3__MAX 0x1 -#define R_IRQ_MASK1_SET__pa2__MAX 0x1 -#define R_IRQ_MASK1_SET__pa1__MAX 0x1 -#define R_IRQ_MASK1_SET__pa0__MAX 0x1 - -#define R_IRQ_MASK1_SET__sw_int7__MIN 0 -#define R_IRQ_MASK1_SET__sw_int6__MIN 0 -#define R_IRQ_MASK1_SET__sw_int5__MIN 0 -#define R_IRQ_MASK1_SET__sw_int4__MIN 0 -#define R_IRQ_MASK1_SET__sw_int3__MIN 0 -#define R_IRQ_MASK1_SET__sw_int2__MIN 0 -#define R_IRQ_MASK1_SET__sw_int1__MIN 0 -#define R_IRQ_MASK1_SET__sw_int0__MIN 0 -#define R_IRQ_MASK1_SET__par1_ecp_cmd__MIN 0 -#define R_IRQ_MASK1_SET__par1_peri__MIN 0 -#define R_IRQ_MASK1_SET__par1_data__MIN 0 -#define R_IRQ_MASK1_SET__par1_ready__MIN 0 -#define R_IRQ_MASK1_SET__scsi1__MIN 0 -#define R_IRQ_MASK1_SET__ser3_ready__MIN 0 -#define R_IRQ_MASK1_SET__ser3_data__MIN 0 -#define R_IRQ_MASK1_SET__ser2_ready__MIN 0 -#define R_IRQ_MASK1_SET__ser2_data__MIN 0 -#define R_IRQ_MASK1_SET__ser1_ready__MIN 0 -#define R_IRQ_MASK1_SET__ser1_data__MIN 0 -#define R_IRQ_MASK1_SET__ser0_ready__MIN 0 -#define R_IRQ_MASK1_SET__ser0_data__MIN 0 -#define R_IRQ_MASK1_SET__pa7__MIN 0 -#define R_IRQ_MASK1_SET__pa6__MIN 0 -#define R_IRQ_MASK1_SET__pa5__MIN 0 -#define R_IRQ_MASK1_SET__pa4__MIN 0 -#define R_IRQ_MASK1_SET__pa3__MIN 0 -#define R_IRQ_MASK1_SET__pa2__MIN 0 -#define R_IRQ_MASK1_SET__pa1__MIN 0 -#define R_IRQ_MASK1_SET__pa0__MIN 0 - -#define R_IRQ_MASK1_SET__sw_int7__BITNR 31 -#define R_IRQ_MASK1_SET__sw_int6__BITNR 30 -#define R_IRQ_MASK1_SET__sw_int5__BITNR 29 -#define R_IRQ_MASK1_SET__sw_int4__BITNR 28 -#define R_IRQ_MASK1_SET__sw_int3__BITNR 27 -#define R_IRQ_MASK1_SET__sw_int2__BITNR 26 -#define R_IRQ_MASK1_SET__sw_int1__BITNR 25 -#define R_IRQ_MASK1_SET__sw_int0__BITNR 24 -#define R_IRQ_MASK1_SET__par1_ecp_cmd__BITNR 19 -#define R_IRQ_MASK1_SET__par1_peri__BITNR 18 -#define R_IRQ_MASK1_SET__par1_data__BITNR 17 -#define R_IRQ_MASK1_SET__par1_ready__BITNR 16 -#define R_IRQ_MASK1_SET__scsi1__BITNR 16 -#define R_IRQ_MASK1_SET__ser3_ready__BITNR 15 -#define R_IRQ_MASK1_SET__ser3_data__BITNR 14 -#define R_IRQ_MASK1_SET__ser2_ready__BITNR 13 -#define R_IRQ_MASK1_SET__ser2_data__BITNR 12 -#define R_IRQ_MASK1_SET__ser1_ready__BITNR 11 -#define R_IRQ_MASK1_SET__ser1_data__BITNR 10 -#define R_IRQ_MASK1_SET__ser0_ready__BITNR 9 -#define R_IRQ_MASK1_SET__ser0_data__BITNR 8 -#define R_IRQ_MASK1_SET__pa7__BITNR 7 -#define R_IRQ_MASK1_SET__pa6__BITNR 6 -#define R_IRQ_MASK1_SET__pa5__BITNR 5 -#define R_IRQ_MASK1_SET__pa4__BITNR 4 -#define R_IRQ_MASK1_SET__pa3__BITNR 3 -#define R_IRQ_MASK1_SET__pa2__BITNR 2 -#define R_IRQ_MASK1_SET__pa1__BITNR 1 -#define R_IRQ_MASK1_SET__pa0__BITNR 0 - -#define R_IRQ_MASK1_SET__sw_int7__sw_int7__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_SET__sw_int6__sw_int6__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_SET__sw_int5__sw_int5__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_SET__sw_int4__sw_int4__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_SET__sw_int3__sw_int3__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_SET__sw_int2__sw_int2__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_SET__sw_int1__sw_int1__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_SET__sw_int0__sw_int0__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_SET__par1_ecp_cmd__par1_ecp_cmd__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_SET__par1_peri__par1_peri__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_SET__par1_data__par1_data__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_SET__par1_ready__par1_ready__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_SET__scsi1__scsi1__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_SET__par1_ready__scsi1__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_SET__ser3_ready__ser3_ready__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_SET__ser3_data__ser3_data__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_SET__ser2_ready__ser2_ready__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_SET__ser2_data__ser2_data__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_SET__ser1_ready__ser1_ready__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_SET__ser1_data__ser1_data__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_SET__ser0_ready__ser0_ready__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_SET__ser0_data__ser0_data__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_SET__pa7__pa7__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_SET__pa6__pa6__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_SET__pa5__pa5__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_SET__pa4__pa4__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_SET__pa3__pa3__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_SET__pa2__pa2__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_SET__pa1__pa1__VAL REG_VAL_ENUM -#define R_IRQ_MASK1_SET__pa0__pa0__VAL REG_VAL_ENUM - -#define R_IRQ_MASK1_SET__sw_int7__sw_int7__nop 0 -#define R_IRQ_MASK1_SET__sw_int7__sw_int7__set 1 -#define R_IRQ_MASK1_SET__sw_int6__sw_int6__nop 0 -#define R_IRQ_MASK1_SET__sw_int6__sw_int6__set 1 -#define R_IRQ_MASK1_SET__sw_int5__sw_int5__nop 0 -#define R_IRQ_MASK1_SET__sw_int5__sw_int5__set 1 -#define R_IRQ_MASK1_SET__sw_int4__sw_int4__nop 0 -#define R_IRQ_MASK1_SET__sw_int4__sw_int4__set 1 -#define R_IRQ_MASK1_SET__sw_int3__sw_int3__nop 0 -#define R_IRQ_MASK1_SET__sw_int3__sw_int3__set 1 -#define R_IRQ_MASK1_SET__sw_int2__sw_int2__nop 0 -#define R_IRQ_MASK1_SET__sw_int2__sw_int2__set 1 -#define R_IRQ_MASK1_SET__sw_int1__sw_int1__nop 0 -#define R_IRQ_MASK1_SET__sw_int1__sw_int1__set 1 -#define R_IRQ_MASK1_SET__sw_int0__sw_int0__nop 0 -#define R_IRQ_MASK1_SET__sw_int0__sw_int0__set 1 -#define R_IRQ_MASK1_SET__par1_ecp_cmd__par1_ecp_cmd__nop 0 -#define R_IRQ_MASK1_SET__par1_ecp_cmd__par1_ecp_cmd__set 1 -#define R_IRQ_MASK1_SET__par1_peri__par1_peri__nop 0 -#define R_IRQ_MASK1_SET__par1_peri__par1_peri__set 1 -#define R_IRQ_MASK1_SET__par1_data__par1_data__nop 0 -#define R_IRQ_MASK1_SET__par1_data__par1_data__set 1 -#define R_IRQ_MASK1_SET__par1_ready__par1_ready__nop 0 -#define R_IRQ_MASK1_SET__par1_ready__par1_ready__set 1 -#define R_IRQ_MASK1_SET__scsi1__scsi1__nop 0 -#define R_IRQ_MASK1_SET__scsi1__scsi1__set 1 -#define R_IRQ_MASK1_SET__ser3_ready__ser3_ready__nop 0 -#define R_IRQ_MASK1_SET__ser3_ready__ser3_ready__set 1 -#define R_IRQ_MASK1_SET__ser3_data__ser3_data__nop 0 -#define R_IRQ_MASK1_SET__ser3_data__ser3_data__set 1 -#define R_IRQ_MASK1_SET__ser2_ready__ser2_ready__nop 0 -#define R_IRQ_MASK1_SET__ser2_ready__ser2_ready__set 1 -#define R_IRQ_MASK1_SET__ser2_data__ser2_data__nop 0 -#define R_IRQ_MASK1_SET__ser2_data__ser2_data__set 1 -#define R_IRQ_MASK1_SET__ser1_ready__ser1_ready__nop 0 -#define R_IRQ_MASK1_SET__ser1_ready__ser1_ready__set 1 -#define R_IRQ_MASK1_SET__ser1_data__ser1_data__nop 0 -#define R_IRQ_MASK1_SET__ser1_data__ser1_data__set 1 -#define R_IRQ_MASK1_SET__ser0_ready__ser0_ready__nop 0 -#define R_IRQ_MASK1_SET__ser0_ready__ser0_ready__set 1 -#define R_IRQ_MASK1_SET__ser0_data__ser0_data__nop 0 -#define R_IRQ_MASK1_SET__ser0_data__ser0_data__set 1 -#define R_IRQ_MASK1_SET__pa7__pa7__nop 0 -#define R_IRQ_MASK1_SET__pa7__pa7__set 1 -#define R_IRQ_MASK1_SET__pa6__pa6__nop 0 -#define R_IRQ_MASK1_SET__pa6__pa6__set 1 -#define R_IRQ_MASK1_SET__pa5__pa5__nop 0 -#define R_IRQ_MASK1_SET__pa5__pa5__set 1 -#define R_IRQ_MASK1_SET__pa4__pa4__nop 0 -#define R_IRQ_MASK1_SET__pa4__pa4__set 1 -#define R_IRQ_MASK1_SET__pa3__pa3__nop 0 -#define R_IRQ_MASK1_SET__pa3__pa3__set 1 -#define R_IRQ_MASK1_SET__pa2__pa2__nop 0 -#define R_IRQ_MASK1_SET__pa2__pa2__set 1 -#define R_IRQ_MASK1_SET__pa1__pa1__nop 0 -#define R_IRQ_MASK1_SET__pa1__pa1__set 1 -#define R_IRQ_MASK1_SET__pa0__pa0__nop 0 -#define R_IRQ_MASK1_SET__pa0__pa0__set 1 - -#endif - -/* - * R_IRQ_MASK2_CLR - * - type: WO - * - addr: 0xb00000d0 - * - group: Interrupt mask and status registers - */ - -#if USE_GROUP__Interrupt_mask_and_status_registers - -#define R_IRQ_MASK2_CLR__ADDR (REG_TYPECAST_UDWORD 0xb00000d0) - -#ifndef REG_NO_SHADOW -#define R_IRQ_MASK2_CLR__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_IRQ_MASK2_CLR + 0)) -#define R_IRQ_MASK2_CLR__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_IRQ_MASK2_CLR + 0)) -#else /* REG_NO_SHADOW */ -#define R_IRQ_MASK2_CLR__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_IRQ_MASK2_CLR__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_IRQ_MASK2_CLR__STYPECAST REG_STYPECAST_UDWORD -#define R_IRQ_MASK2_CLR__SVAL REG_SVAL_ZERO -#define R_IRQ_MASK2_CLR__SVAL_I REG_SVAL_I_ZERO -#define R_IRQ_MASK2_CLR__TYPECAST REG_TYPECAST_UDWORD -#define R_IRQ_MASK2_CLR__TYPE (REG_UDWORD) -#define R_IRQ_MASK2_CLR__GET REG_GET_WO -#define R_IRQ_MASK2_CLR__IGET REG_IGET_WO -#define R_IRQ_MASK2_CLR__SET REG_SET_WO -#define R_IRQ_MASK2_CLR__ISET REG_ISET_WO -#define R_IRQ_MASK2_CLR__SET_VAL REG_SET_VAL_WO -#define R_IRQ_MASK2_CLR__EQL REG_EQL_WO -#define R_IRQ_MASK2_CLR__IEQL REG_IEQL_WO -#define R_IRQ_MASK2_CLR__RD REG_RD_WO -#define R_IRQ_MASK2_CLR__IRD REG_IRD_WO -#define R_IRQ_MASK2_CLR__WR REG_WR_WO -#define R_IRQ_MASK2_CLR__IWR REG_IWR_WO - -#define R_IRQ_MASK2_CLR__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_IRQ_MASK2_CLR__dma8_sub3_descr__dma8_sub3_descr__MASK 0x00800000U -#define R_IRQ_MASK2_CLR__dma8_sub2_descr__dma8_sub2_descr__MASK 0x00400000U -#define R_IRQ_MASK2_CLR__dma8_sub1_descr__dma8_sub1_descr__MASK 0x00200000U -#define R_IRQ_MASK2_CLR__dma8_sub0_descr__dma8_sub0_descr__MASK 0x00100000U -#define R_IRQ_MASK2_CLR__dma9_eop__dma9_eop__MASK 0x00080000U -#define R_IRQ_MASK2_CLR__dma9_descr__dma9_descr__MASK 0x00040000U -#define R_IRQ_MASK2_CLR__dma8_eop__dma8_eop__MASK 0x00020000U -#define R_IRQ_MASK2_CLR__dma8_descr__dma8_descr__MASK 0x00010000U -#define R_IRQ_MASK2_CLR__dma7_eop__dma7_eop__MASK 0x00008000U -#define R_IRQ_MASK2_CLR__dma7_descr__dma7_descr__MASK 0x00004000U -#define R_IRQ_MASK2_CLR__dma6_eop__dma6_eop__MASK 0x00002000U -#define R_IRQ_MASK2_CLR__dma6_descr__dma6_descr__MASK 0x00001000U -#define R_IRQ_MASK2_CLR__dma5_eop__dma5_eop__MASK 0x00000800U -#define R_IRQ_MASK2_CLR__dma5_descr__dma5_descr__MASK 0x00000400U -#define R_IRQ_MASK2_CLR__dma4_eop__dma4_eop__MASK 0x00000200U -#define R_IRQ_MASK2_CLR__dma4_descr__dma4_descr__MASK 0x00000100U -#define R_IRQ_MASK2_CLR__dma3_eop__dma3_eop__MASK 0x00000080U -#define R_IRQ_MASK2_CLR__dma3_descr__dma3_descr__MASK 0x00000040U -#define R_IRQ_MASK2_CLR__dma2_eop__dma2_eop__MASK 0x00000020U -#define R_IRQ_MASK2_CLR__dma2_descr__dma2_descr__MASK 0x00000010U -#define R_IRQ_MASK2_CLR__dma1_eop__dma1_eop__MASK 0x00000008U -#define R_IRQ_MASK2_CLR__dma1_descr__dma1_descr__MASK 0x00000004U -#define R_IRQ_MASK2_CLR__dma0_eop__dma0_eop__MASK 0x00000002U -#define R_IRQ_MASK2_CLR__dma0_descr__dma0_descr__MASK 0x00000001U - -#define R_IRQ_MASK2_CLR__dma8_sub3_descr__MAX 0x1 -#define R_IRQ_MASK2_CLR__dma8_sub2_descr__MAX 0x1 -#define R_IRQ_MASK2_CLR__dma8_sub1_descr__MAX 0x1 -#define R_IRQ_MASK2_CLR__dma8_sub0_descr__MAX 0x1 -#define R_IRQ_MASK2_CLR__dma9_eop__MAX 0x1 -#define R_IRQ_MASK2_CLR__dma9_descr__MAX 0x1 -#define R_IRQ_MASK2_CLR__dma8_eop__MAX 0x1 -#define R_IRQ_MASK2_CLR__dma8_descr__MAX 0x1 -#define R_IRQ_MASK2_CLR__dma7_eop__MAX 0x1 -#define R_IRQ_MASK2_CLR__dma7_descr__MAX 0x1 -#define R_IRQ_MASK2_CLR__dma6_eop__MAX 0x1 -#define R_IRQ_MASK2_CLR__dma6_descr__MAX 0x1 -#define R_IRQ_MASK2_CLR__dma5_eop__MAX 0x1 -#define R_IRQ_MASK2_CLR__dma5_descr__MAX 0x1 -#define R_IRQ_MASK2_CLR__dma4_eop__MAX 0x1 -#define R_IRQ_MASK2_CLR__dma4_descr__MAX 0x1 -#define R_IRQ_MASK2_CLR__dma3_eop__MAX 0x1 -#define R_IRQ_MASK2_CLR__dma3_descr__MAX 0x1 -#define R_IRQ_MASK2_CLR__dma2_eop__MAX 0x1 -#define R_IRQ_MASK2_CLR__dma2_descr__MAX 0x1 -#define R_IRQ_MASK2_CLR__dma1_eop__MAX 0x1 -#define R_IRQ_MASK2_CLR__dma1_descr__MAX 0x1 -#define R_IRQ_MASK2_CLR__dma0_eop__MAX 0x1 -#define R_IRQ_MASK2_CLR__dma0_descr__MAX 0x1 - -#define R_IRQ_MASK2_CLR__dma8_sub3_descr__MIN 0 -#define R_IRQ_MASK2_CLR__dma8_sub2_descr__MIN 0 -#define R_IRQ_MASK2_CLR__dma8_sub1_descr__MIN 0 -#define R_IRQ_MASK2_CLR__dma8_sub0_descr__MIN 0 -#define R_IRQ_MASK2_CLR__dma9_eop__MIN 0 -#define R_IRQ_MASK2_CLR__dma9_descr__MIN 0 -#define R_IRQ_MASK2_CLR__dma8_eop__MIN 0 -#define R_IRQ_MASK2_CLR__dma8_descr__MIN 0 -#define R_IRQ_MASK2_CLR__dma7_eop__MIN 0 -#define R_IRQ_MASK2_CLR__dma7_descr__MIN 0 -#define R_IRQ_MASK2_CLR__dma6_eop__MIN 0 -#define R_IRQ_MASK2_CLR__dma6_descr__MIN 0 -#define R_IRQ_MASK2_CLR__dma5_eop__MIN 0 -#define R_IRQ_MASK2_CLR__dma5_descr__MIN 0 -#define R_IRQ_MASK2_CLR__dma4_eop__MIN 0 -#define R_IRQ_MASK2_CLR__dma4_descr__MIN 0 -#define R_IRQ_MASK2_CLR__dma3_eop__MIN 0 -#define R_IRQ_MASK2_CLR__dma3_descr__MIN 0 -#define R_IRQ_MASK2_CLR__dma2_eop__MIN 0 -#define R_IRQ_MASK2_CLR__dma2_descr__MIN 0 -#define R_IRQ_MASK2_CLR__dma1_eop__MIN 0 -#define R_IRQ_MASK2_CLR__dma1_descr__MIN 0 -#define R_IRQ_MASK2_CLR__dma0_eop__MIN 0 -#define R_IRQ_MASK2_CLR__dma0_descr__MIN 0 - -#define R_IRQ_MASK2_CLR__dma8_sub3_descr__BITNR 23 -#define R_IRQ_MASK2_CLR__dma8_sub2_descr__BITNR 22 -#define R_IRQ_MASK2_CLR__dma8_sub1_descr__BITNR 21 -#define R_IRQ_MASK2_CLR__dma8_sub0_descr__BITNR 20 -#define R_IRQ_MASK2_CLR__dma9_eop__BITNR 19 -#define R_IRQ_MASK2_CLR__dma9_descr__BITNR 18 -#define R_IRQ_MASK2_CLR__dma8_eop__BITNR 17 -#define R_IRQ_MASK2_CLR__dma8_descr__BITNR 16 -#define R_IRQ_MASK2_CLR__dma7_eop__BITNR 15 -#define R_IRQ_MASK2_CLR__dma7_descr__BITNR 14 -#define R_IRQ_MASK2_CLR__dma6_eop__BITNR 13 -#define R_IRQ_MASK2_CLR__dma6_descr__BITNR 12 -#define R_IRQ_MASK2_CLR__dma5_eop__BITNR 11 -#define R_IRQ_MASK2_CLR__dma5_descr__BITNR 10 -#define R_IRQ_MASK2_CLR__dma4_eop__BITNR 9 -#define R_IRQ_MASK2_CLR__dma4_descr__BITNR 8 -#define R_IRQ_MASK2_CLR__dma3_eop__BITNR 7 -#define R_IRQ_MASK2_CLR__dma3_descr__BITNR 6 -#define R_IRQ_MASK2_CLR__dma2_eop__BITNR 5 -#define R_IRQ_MASK2_CLR__dma2_descr__BITNR 4 -#define R_IRQ_MASK2_CLR__dma1_eop__BITNR 3 -#define R_IRQ_MASK2_CLR__dma1_descr__BITNR 2 -#define R_IRQ_MASK2_CLR__dma0_eop__BITNR 1 -#define R_IRQ_MASK2_CLR__dma0_descr__BITNR 0 - -#define R_IRQ_MASK2_CLR__dma8_sub3_descr__dma8_sub3_descr__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_CLR__dma8_sub2_descr__dma8_sub2_descr__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_CLR__dma8_sub1_descr__dma8_sub1_descr__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_CLR__dma8_sub0_descr__dma8_sub0_descr__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_CLR__dma9_eop__dma9_eop__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_CLR__dma9_descr__dma9_descr__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_CLR__dma8_eop__dma8_eop__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_CLR__dma8_descr__dma8_descr__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_CLR__dma7_eop__dma7_eop__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_CLR__dma7_descr__dma7_descr__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_CLR__dma6_eop__dma6_eop__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_CLR__dma6_descr__dma6_descr__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_CLR__dma5_eop__dma5_eop__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_CLR__dma5_descr__dma5_descr__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_CLR__dma4_eop__dma4_eop__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_CLR__dma4_descr__dma4_descr__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_CLR__dma3_eop__dma3_eop__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_CLR__dma3_descr__dma3_descr__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_CLR__dma2_eop__dma2_eop__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_CLR__dma2_descr__dma2_descr__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_CLR__dma1_eop__dma1_eop__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_CLR__dma1_descr__dma1_descr__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_CLR__dma0_eop__dma0_eop__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_CLR__dma0_descr__dma0_descr__VAL REG_VAL_ENUM - -#define R_IRQ_MASK2_CLR__dma8_sub3_descr__dma8_sub3_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma8_sub3_descr__dma8_sub3_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma8_sub2_descr__dma8_sub2_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma8_sub2_descr__dma8_sub2_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma8_sub1_descr__dma8_sub1_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma8_sub1_descr__dma8_sub1_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma8_sub0_descr__dma8_sub0_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma8_sub0_descr__dma8_sub0_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma9_eop__dma9_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma9_eop__dma9_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma9_descr__dma9_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma9_descr__dma9_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma8_eop__dma8_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma8_eop__dma8_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma8_descr__dma8_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma8_descr__dma8_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma7_eop__dma7_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma7_eop__dma7_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma7_descr__dma7_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma7_descr__dma7_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma6_eop__dma6_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma6_eop__dma6_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma6_descr__dma6_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma6_descr__dma6_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma5_eop__dma5_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma5_eop__dma5_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma5_descr__dma5_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma5_descr__dma5_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma4_eop__dma4_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma4_eop__dma4_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma4_descr__dma4_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma4_descr__dma4_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma3_eop__dma3_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma3_eop__dma3_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma3_descr__dma3_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma3_descr__dma3_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma2_eop__dma2_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma2_eop__dma2_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma2_descr__dma2_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma2_descr__dma2_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma1_eop__dma1_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma1_eop__dma1_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma1_descr__dma1_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma1_descr__dma1_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma0_eop__dma0_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma0_eop__dma0_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma0_descr__dma0_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma0_descr__dma0_descr__nop 0 - -#endif - -/* - * R_IRQ_MASK2_RD - * - type: RO - * - addr: 0xb00000d0 - * - group: Interrupt mask and status registers - */ - -#if USE_GROUP__Interrupt_mask_and_status_registers - -#define R_IRQ_MASK2_RD__ADDR (REG_TYPECAST_UDWORD 0xb00000d0) -#define R_IRQ_MASK2_RD__SVAL REG_SVAL_SHADOW -#define R_IRQ_MASK2_RD__SVAL_I REG_SVAL_I_SHADOW -#define R_IRQ_MASK2_RD__TYPECAST REG_TYPECAST_UDWORD -#define R_IRQ_MASK2_RD__TYPE (REG_UDWORD) -#define R_IRQ_MASK2_RD__GET REG_GET_RO -#define R_IRQ_MASK2_RD__IGET REG_IGET_RO -#define R_IRQ_MASK2_RD__SET REG_SET_RO -#define R_IRQ_MASK2_RD__ISET REG_ISET_RO -#define R_IRQ_MASK2_RD__SET_VAL REG_SET_VAL_RO -#define R_IRQ_MASK2_RD__EQL REG_EQL_RO -#define R_IRQ_MASK2_RD__IEQL REG_IEQL_RO -#define R_IRQ_MASK2_RD__RD REG_RD_RO -#define R_IRQ_MASK2_RD__IRD REG_IRD_RO -#define R_IRQ_MASK2_RD__WR REG_WR_RO -#define R_IRQ_MASK2_RD__IWR REG_IWR_RO - -#define R_IRQ_MASK2_RD__READ(addr) \ - (*(addr)) - -#define R_IRQ_MASK2_RD__dma8_sub3_descr__dma8_sub3_descr__MASK 0x00800000U -#define R_IRQ_MASK2_RD__dma8_sub2_descr__dma8_sub2_descr__MASK 0x00400000U -#define R_IRQ_MASK2_RD__dma8_sub1_descr__dma8_sub1_descr__MASK 0x00200000U -#define R_IRQ_MASK2_RD__dma8_sub0_descr__dma8_sub0_descr__MASK 0x00100000U -#define R_IRQ_MASK2_RD__dma9_eop__dma9_eop__MASK 0x00080000U -#define R_IRQ_MASK2_RD__dma9_descr__dma9_descr__MASK 0x00040000U -#define R_IRQ_MASK2_RD__dma8_eop__dma8_eop__MASK 0x00020000U -#define R_IRQ_MASK2_RD__dma8_descr__dma8_descr__MASK 0x00010000U -#define R_IRQ_MASK2_RD__dma7_eop__dma7_eop__MASK 0x00008000U -#define R_IRQ_MASK2_RD__dma7_descr__dma7_descr__MASK 0x00004000U -#define R_IRQ_MASK2_RD__dma6_eop__dma6_eop__MASK 0x00002000U -#define R_IRQ_MASK2_RD__dma6_descr__dma6_descr__MASK 0x00001000U -#define R_IRQ_MASK2_RD__dma5_eop__dma5_eop__MASK 0x00000800U -#define R_IRQ_MASK2_RD__dma5_descr__dma5_descr__MASK 0x00000400U -#define R_IRQ_MASK2_RD__dma4_eop__dma4_eop__MASK 0x00000200U -#define R_IRQ_MASK2_RD__dma4_descr__dma4_descr__MASK 0x00000100U -#define R_IRQ_MASK2_RD__dma3_eop__dma3_eop__MASK 0x00000080U -#define R_IRQ_MASK2_RD__dma3_descr__dma3_descr__MASK 0x00000040U -#define R_IRQ_MASK2_RD__dma2_eop__dma2_eop__MASK 0x00000020U -#define R_IRQ_MASK2_RD__dma2_descr__dma2_descr__MASK 0x00000010U -#define R_IRQ_MASK2_RD__dma1_eop__dma1_eop__MASK 0x00000008U -#define R_IRQ_MASK2_RD__dma1_descr__dma1_descr__MASK 0x00000004U -#define R_IRQ_MASK2_RD__dma0_eop__dma0_eop__MASK 0x00000002U -#define R_IRQ_MASK2_RD__dma0_descr__dma0_descr__MASK 0x00000001U - -#define R_IRQ_MASK2_RD__dma8_sub3_descr__MAX 0x1 -#define R_IRQ_MASK2_RD__dma8_sub2_descr__MAX 0x1 -#define R_IRQ_MASK2_RD__dma8_sub1_descr__MAX 0x1 -#define R_IRQ_MASK2_RD__dma8_sub0_descr__MAX 0x1 -#define R_IRQ_MASK2_RD__dma9_eop__MAX 0x1 -#define R_IRQ_MASK2_RD__dma9_descr__MAX 0x1 -#define R_IRQ_MASK2_RD__dma8_eop__MAX 0x1 -#define R_IRQ_MASK2_RD__dma8_descr__MAX 0x1 -#define R_IRQ_MASK2_RD__dma7_eop__MAX 0x1 -#define R_IRQ_MASK2_RD__dma7_descr__MAX 0x1 -#define R_IRQ_MASK2_RD__dma6_eop__MAX 0x1 -#define R_IRQ_MASK2_RD__dma6_descr__MAX 0x1 -#define R_IRQ_MASK2_RD__dma5_eop__MAX 0x1 -#define R_IRQ_MASK2_RD__dma5_descr__MAX 0x1 -#define R_IRQ_MASK2_RD__dma4_eop__MAX 0x1 -#define R_IRQ_MASK2_RD__dma4_descr__MAX 0x1 -#define R_IRQ_MASK2_RD__dma3_eop__MAX 0x1 -#define R_IRQ_MASK2_RD__dma3_descr__MAX 0x1 -#define R_IRQ_MASK2_RD__dma2_eop__MAX 0x1 -#define R_IRQ_MASK2_RD__dma2_descr__MAX 0x1 -#define R_IRQ_MASK2_RD__dma1_eop__MAX 0x1 -#define R_IRQ_MASK2_RD__dma1_descr__MAX 0x1 -#define R_IRQ_MASK2_RD__dma0_eop__MAX 0x1 -#define R_IRQ_MASK2_RD__dma0_descr__MAX 0x1 - -#define R_IRQ_MASK2_RD__dma8_sub3_descr__MIN 0 -#define R_IRQ_MASK2_RD__dma8_sub2_descr__MIN 0 -#define R_IRQ_MASK2_RD__dma8_sub1_descr__MIN 0 -#define R_IRQ_MASK2_RD__dma8_sub0_descr__MIN 0 -#define R_IRQ_MASK2_RD__dma9_eop__MIN 0 -#define R_IRQ_MASK2_RD__dma9_descr__MIN 0 -#define R_IRQ_MASK2_RD__dma8_eop__MIN 0 -#define R_IRQ_MASK2_RD__dma8_descr__MIN 0 -#define R_IRQ_MASK2_RD__dma7_eop__MIN 0 -#define R_IRQ_MASK2_RD__dma7_descr__MIN 0 -#define R_IRQ_MASK2_RD__dma6_eop__MIN 0 -#define R_IRQ_MASK2_RD__dma6_descr__MIN 0 -#define R_IRQ_MASK2_RD__dma5_eop__MIN 0 -#define R_IRQ_MASK2_RD__dma5_descr__MIN 0 -#define R_IRQ_MASK2_RD__dma4_eop__MIN 0 -#define R_IRQ_MASK2_RD__dma4_descr__MIN 0 -#define R_IRQ_MASK2_RD__dma3_eop__MIN 0 -#define R_IRQ_MASK2_RD__dma3_descr__MIN 0 -#define R_IRQ_MASK2_RD__dma2_eop__MIN 0 -#define R_IRQ_MASK2_RD__dma2_descr__MIN 0 -#define R_IRQ_MASK2_RD__dma1_eop__MIN 0 -#define R_IRQ_MASK2_RD__dma1_descr__MIN 0 -#define R_IRQ_MASK2_RD__dma0_eop__MIN 0 -#define R_IRQ_MASK2_RD__dma0_descr__MIN 0 - -#define R_IRQ_MASK2_RD__dma8_sub3_descr__BITNR 23 -#define R_IRQ_MASK2_RD__dma8_sub2_descr__BITNR 22 -#define R_IRQ_MASK2_RD__dma8_sub1_descr__BITNR 21 -#define R_IRQ_MASK2_RD__dma8_sub0_descr__BITNR 20 -#define R_IRQ_MASK2_RD__dma9_eop__BITNR 19 -#define R_IRQ_MASK2_RD__dma9_descr__BITNR 18 -#define R_IRQ_MASK2_RD__dma8_eop__BITNR 17 -#define R_IRQ_MASK2_RD__dma8_descr__BITNR 16 -#define R_IRQ_MASK2_RD__dma7_eop__BITNR 15 -#define R_IRQ_MASK2_RD__dma7_descr__BITNR 14 -#define R_IRQ_MASK2_RD__dma6_eop__BITNR 13 -#define R_IRQ_MASK2_RD__dma6_descr__BITNR 12 -#define R_IRQ_MASK2_RD__dma5_eop__BITNR 11 -#define R_IRQ_MASK2_RD__dma5_descr__BITNR 10 -#define R_IRQ_MASK2_RD__dma4_eop__BITNR 9 -#define R_IRQ_MASK2_RD__dma4_descr__BITNR 8 -#define R_IRQ_MASK2_RD__dma3_eop__BITNR 7 -#define R_IRQ_MASK2_RD__dma3_descr__BITNR 6 -#define R_IRQ_MASK2_RD__dma2_eop__BITNR 5 -#define R_IRQ_MASK2_RD__dma2_descr__BITNR 4 -#define R_IRQ_MASK2_RD__dma1_eop__BITNR 3 -#define R_IRQ_MASK2_RD__dma1_descr__BITNR 2 -#define R_IRQ_MASK2_RD__dma0_eop__BITNR 1 -#define R_IRQ_MASK2_RD__dma0_descr__BITNR 0 - -#define R_IRQ_MASK2_RD__dma8_sub3_descr__dma8_sub3_descr__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_RD__dma8_sub2_descr__dma8_sub2_descr__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_RD__dma8_sub1_descr__dma8_sub1_descr__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_RD__dma8_sub0_descr__dma8_sub0_descr__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_RD__dma9_eop__dma9_eop__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_RD__dma9_descr__dma9_descr__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_RD__dma8_eop__dma8_eop__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_RD__dma8_descr__dma8_descr__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_RD__dma7_eop__dma7_eop__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_RD__dma7_descr__dma7_descr__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_RD__dma6_eop__dma6_eop__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_RD__dma6_descr__dma6_descr__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_RD__dma5_eop__dma5_eop__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_RD__dma5_descr__dma5_descr__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_RD__dma4_eop__dma4_eop__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_RD__dma4_descr__dma4_descr__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_RD__dma3_eop__dma3_eop__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_RD__dma3_descr__dma3_descr__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_RD__dma2_eop__dma2_eop__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_RD__dma2_descr__dma2_descr__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_RD__dma1_eop__dma1_eop__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_RD__dma1_descr__dma1_descr__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_RD__dma0_eop__dma0_eop__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_RD__dma0_descr__dma0_descr__VAL REG_VAL_ENUM - -#define R_IRQ_MASK2_RD__dma8_sub3_descr__dma8_sub3_descr__active 1 -#define R_IRQ_MASK2_RD__dma8_sub3_descr__dma8_sub3_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma8_sub2_descr__dma8_sub2_descr__active 1 -#define R_IRQ_MASK2_RD__dma8_sub2_descr__dma8_sub2_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma8_sub1_descr__dma8_sub1_descr__active 1 -#define R_IRQ_MASK2_RD__dma8_sub1_descr__dma8_sub1_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma8_sub0_descr__dma8_sub0_descr__active 1 -#define R_IRQ_MASK2_RD__dma8_sub0_descr__dma8_sub0_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma9_eop__dma9_eop__active 1 -#define R_IRQ_MASK2_RD__dma9_eop__dma9_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma9_descr__dma9_descr__active 1 -#define R_IRQ_MASK2_RD__dma9_descr__dma9_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma8_eop__dma8_eop__active 1 -#define R_IRQ_MASK2_RD__dma8_eop__dma8_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma8_descr__dma8_descr__active 1 -#define R_IRQ_MASK2_RD__dma8_descr__dma8_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma7_eop__dma7_eop__active 1 -#define R_IRQ_MASK2_RD__dma7_eop__dma7_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma7_descr__dma7_descr__active 1 -#define R_IRQ_MASK2_RD__dma7_descr__dma7_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma6_eop__dma6_eop__active 1 -#define R_IRQ_MASK2_RD__dma6_eop__dma6_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma6_descr__dma6_descr__active 1 -#define R_IRQ_MASK2_RD__dma6_descr__dma6_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma5_eop__dma5_eop__active 1 -#define R_IRQ_MASK2_RD__dma5_eop__dma5_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma5_descr__dma5_descr__active 1 -#define R_IRQ_MASK2_RD__dma5_descr__dma5_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma4_eop__dma4_eop__active 1 -#define R_IRQ_MASK2_RD__dma4_eop__dma4_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma4_descr__dma4_descr__active 1 -#define R_IRQ_MASK2_RD__dma4_descr__dma4_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma3_eop__dma3_eop__active 1 -#define R_IRQ_MASK2_RD__dma3_eop__dma3_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma3_descr__dma3_descr__active 1 -#define R_IRQ_MASK2_RD__dma3_descr__dma3_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma2_eop__dma2_eop__active 1 -#define R_IRQ_MASK2_RD__dma2_eop__dma2_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma2_descr__dma2_descr__active 1 -#define R_IRQ_MASK2_RD__dma2_descr__dma2_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma1_eop__dma1_eop__active 1 -#define R_IRQ_MASK2_RD__dma1_eop__dma1_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma1_descr__dma1_descr__active 1 -#define R_IRQ_MASK2_RD__dma1_descr__dma1_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma0_eop__dma0_eop__active 1 -#define R_IRQ_MASK2_RD__dma0_eop__dma0_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma0_descr__dma0_descr__active 1 -#define R_IRQ_MASK2_RD__dma0_descr__dma0_descr__inactive 0 - -#endif - -/* - * R_IRQ_MASK2_SET - * - type: WO - * - addr: 0xb00000d4 - * - group: Interrupt mask and status registers - */ - -#if USE_GROUP__Interrupt_mask_and_status_registers - -#define R_IRQ_MASK2_SET__ADDR (REG_TYPECAST_UDWORD 0xb00000d4) - -#ifndef REG_NO_SHADOW -#define R_IRQ_MASK2_SET__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_IRQ_MASK2_SET + 0)) -#define R_IRQ_MASK2_SET__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_IRQ_MASK2_SET + 0)) -#else /* REG_NO_SHADOW */ -#define R_IRQ_MASK2_SET__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_IRQ_MASK2_SET__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_IRQ_MASK2_SET__STYPECAST REG_STYPECAST_UDWORD -#define R_IRQ_MASK2_SET__SVAL REG_SVAL_ZERO -#define R_IRQ_MASK2_SET__SVAL_I REG_SVAL_I_ZERO -#define R_IRQ_MASK2_SET__TYPECAST REG_TYPECAST_UDWORD -#define R_IRQ_MASK2_SET__TYPE (REG_UDWORD) -#define R_IRQ_MASK2_SET__GET REG_GET_WO -#define R_IRQ_MASK2_SET__IGET REG_IGET_WO -#define R_IRQ_MASK2_SET__SET REG_SET_WO -#define R_IRQ_MASK2_SET__ISET REG_ISET_WO -#define R_IRQ_MASK2_SET__SET_VAL REG_SET_VAL_WO -#define R_IRQ_MASK2_SET__EQL REG_EQL_WO -#define R_IRQ_MASK2_SET__IEQL REG_IEQL_WO -#define R_IRQ_MASK2_SET__RD REG_RD_WO -#define R_IRQ_MASK2_SET__IRD REG_IRD_WO -#define R_IRQ_MASK2_SET__WR REG_WR_WO -#define R_IRQ_MASK2_SET__IWR REG_IWR_WO - -#define R_IRQ_MASK2_SET__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_IRQ_MASK2_SET__dma8_sub3_descr__dma8_sub3_descr__MASK 0x00800000U -#define R_IRQ_MASK2_SET__dma8_sub2_descr__dma8_sub2_descr__MASK 0x00400000U -#define R_IRQ_MASK2_SET__dma8_sub1_descr__dma8_sub1_descr__MASK 0x00200000U -#define R_IRQ_MASK2_SET__dma8_sub0_descr__dma8_sub0_descr__MASK 0x00100000U -#define R_IRQ_MASK2_SET__dma9_eop__dma9_eop__MASK 0x00080000U -#define R_IRQ_MASK2_SET__dma9_descr__dma9_descr__MASK 0x00040000U -#define R_IRQ_MASK2_SET__dma8_eop__dma8_eop__MASK 0x00020000U -#define R_IRQ_MASK2_SET__dma8_descr__dma8_descr__MASK 0x00010000U -#define R_IRQ_MASK2_SET__dma7_eop__dma7_eop__MASK 0x00008000U -#define R_IRQ_MASK2_SET__dma7_descr__dma7_descr__MASK 0x00004000U -#define R_IRQ_MASK2_SET__dma6_eop__dma6_eop__MASK 0x00002000U -#define R_IRQ_MASK2_SET__dma6_descr__dma6_descr__MASK 0x00001000U -#define R_IRQ_MASK2_SET__dma5_eop__dma5_eop__MASK 0x00000800U -#define R_IRQ_MASK2_SET__dma5_descr__dma5_descr__MASK 0x00000400U -#define R_IRQ_MASK2_SET__dma4_eop__dma4_eop__MASK 0x00000200U -#define R_IRQ_MASK2_SET__dma4_descr__dma4_descr__MASK 0x00000100U -#define R_IRQ_MASK2_SET__dma3_eop__dma3_eop__MASK 0x00000080U -#define R_IRQ_MASK2_SET__dma3_descr__dma3_descr__MASK 0x00000040U -#define R_IRQ_MASK2_SET__dma2_eop__dma2_eop__MASK 0x00000020U -#define R_IRQ_MASK2_SET__dma2_descr__dma2_descr__MASK 0x00000010U -#define R_IRQ_MASK2_SET__dma1_eop__dma1_eop__MASK 0x00000008U -#define R_IRQ_MASK2_SET__dma1_descr__dma1_descr__MASK 0x00000004U -#define R_IRQ_MASK2_SET__dma0_eop__dma0_eop__MASK 0x00000002U -#define R_IRQ_MASK2_SET__dma0_descr__dma0_descr__MASK 0x00000001U - -#define R_IRQ_MASK2_SET__dma8_sub3_descr__MAX 0x1 -#define R_IRQ_MASK2_SET__dma8_sub2_descr__MAX 0x1 -#define R_IRQ_MASK2_SET__dma8_sub1_descr__MAX 0x1 -#define R_IRQ_MASK2_SET__dma8_sub0_descr__MAX 0x1 -#define R_IRQ_MASK2_SET__dma9_eop__MAX 0x1 -#define R_IRQ_MASK2_SET__dma9_descr__MAX 0x1 -#define R_IRQ_MASK2_SET__dma8_eop__MAX 0x1 -#define R_IRQ_MASK2_SET__dma8_descr__MAX 0x1 -#define R_IRQ_MASK2_SET__dma7_eop__MAX 0x1 -#define R_IRQ_MASK2_SET__dma7_descr__MAX 0x1 -#define R_IRQ_MASK2_SET__dma6_eop__MAX 0x1 -#define R_IRQ_MASK2_SET__dma6_descr__MAX 0x1 -#define R_IRQ_MASK2_SET__dma5_eop__MAX 0x1 -#define R_IRQ_MASK2_SET__dma5_descr__MAX 0x1 -#define R_IRQ_MASK2_SET__dma4_eop__MAX 0x1 -#define R_IRQ_MASK2_SET__dma4_descr__MAX 0x1 -#define R_IRQ_MASK2_SET__dma3_eop__MAX 0x1 -#define R_IRQ_MASK2_SET__dma3_descr__MAX 0x1 -#define R_IRQ_MASK2_SET__dma2_eop__MAX 0x1 -#define R_IRQ_MASK2_SET__dma2_descr__MAX 0x1 -#define R_IRQ_MASK2_SET__dma1_eop__MAX 0x1 -#define R_IRQ_MASK2_SET__dma1_descr__MAX 0x1 -#define R_IRQ_MASK2_SET__dma0_eop__MAX 0x1 -#define R_IRQ_MASK2_SET__dma0_descr__MAX 0x1 - -#define R_IRQ_MASK2_SET__dma8_sub3_descr__MIN 0 -#define R_IRQ_MASK2_SET__dma8_sub2_descr__MIN 0 -#define R_IRQ_MASK2_SET__dma8_sub1_descr__MIN 0 -#define R_IRQ_MASK2_SET__dma8_sub0_descr__MIN 0 -#define R_IRQ_MASK2_SET__dma9_eop__MIN 0 -#define R_IRQ_MASK2_SET__dma9_descr__MIN 0 -#define R_IRQ_MASK2_SET__dma8_eop__MIN 0 -#define R_IRQ_MASK2_SET__dma8_descr__MIN 0 -#define R_IRQ_MASK2_SET__dma7_eop__MIN 0 -#define R_IRQ_MASK2_SET__dma7_descr__MIN 0 -#define R_IRQ_MASK2_SET__dma6_eop__MIN 0 -#define R_IRQ_MASK2_SET__dma6_descr__MIN 0 -#define R_IRQ_MASK2_SET__dma5_eop__MIN 0 -#define R_IRQ_MASK2_SET__dma5_descr__MIN 0 -#define R_IRQ_MASK2_SET__dma4_eop__MIN 0 -#define R_IRQ_MASK2_SET__dma4_descr__MIN 0 -#define R_IRQ_MASK2_SET__dma3_eop__MIN 0 -#define R_IRQ_MASK2_SET__dma3_descr__MIN 0 -#define R_IRQ_MASK2_SET__dma2_eop__MIN 0 -#define R_IRQ_MASK2_SET__dma2_descr__MIN 0 -#define R_IRQ_MASK2_SET__dma1_eop__MIN 0 -#define R_IRQ_MASK2_SET__dma1_descr__MIN 0 -#define R_IRQ_MASK2_SET__dma0_eop__MIN 0 -#define R_IRQ_MASK2_SET__dma0_descr__MIN 0 - -#define R_IRQ_MASK2_SET__dma8_sub3_descr__BITNR 23 -#define R_IRQ_MASK2_SET__dma8_sub2_descr__BITNR 22 -#define R_IRQ_MASK2_SET__dma8_sub1_descr__BITNR 21 -#define R_IRQ_MASK2_SET__dma8_sub0_descr__BITNR 20 -#define R_IRQ_MASK2_SET__dma9_eop__BITNR 19 -#define R_IRQ_MASK2_SET__dma9_descr__BITNR 18 -#define R_IRQ_MASK2_SET__dma8_eop__BITNR 17 -#define R_IRQ_MASK2_SET__dma8_descr__BITNR 16 -#define R_IRQ_MASK2_SET__dma7_eop__BITNR 15 -#define R_IRQ_MASK2_SET__dma7_descr__BITNR 14 -#define R_IRQ_MASK2_SET__dma6_eop__BITNR 13 -#define R_IRQ_MASK2_SET__dma6_descr__BITNR 12 -#define R_IRQ_MASK2_SET__dma5_eop__BITNR 11 -#define R_IRQ_MASK2_SET__dma5_descr__BITNR 10 -#define R_IRQ_MASK2_SET__dma4_eop__BITNR 9 -#define R_IRQ_MASK2_SET__dma4_descr__BITNR 8 -#define R_IRQ_MASK2_SET__dma3_eop__BITNR 7 -#define R_IRQ_MASK2_SET__dma3_descr__BITNR 6 -#define R_IRQ_MASK2_SET__dma2_eop__BITNR 5 -#define R_IRQ_MASK2_SET__dma2_descr__BITNR 4 -#define R_IRQ_MASK2_SET__dma1_eop__BITNR 3 -#define R_IRQ_MASK2_SET__dma1_descr__BITNR 2 -#define R_IRQ_MASK2_SET__dma0_eop__BITNR 1 -#define R_IRQ_MASK2_SET__dma0_descr__BITNR 0 - -#define R_IRQ_MASK2_SET__dma8_sub3_descr__dma8_sub3_descr__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_SET__dma8_sub2_descr__dma8_sub2_descr__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_SET__dma8_sub1_descr__dma8_sub1_descr__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_SET__dma8_sub0_descr__dma8_sub0_descr__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_SET__dma9_eop__dma9_eop__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_SET__dma9_descr__dma9_descr__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_SET__dma8_eop__dma8_eop__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_SET__dma8_descr__dma8_descr__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_SET__dma7_eop__dma7_eop__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_SET__dma7_descr__dma7_descr__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_SET__dma6_eop__dma6_eop__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_SET__dma6_descr__dma6_descr__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_SET__dma5_eop__dma5_eop__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_SET__dma5_descr__dma5_descr__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_SET__dma4_eop__dma4_eop__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_SET__dma4_descr__dma4_descr__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_SET__dma3_eop__dma3_eop__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_SET__dma3_descr__dma3_descr__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_SET__dma2_eop__dma2_eop__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_SET__dma2_descr__dma2_descr__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_SET__dma1_eop__dma1_eop__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_SET__dma1_descr__dma1_descr__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_SET__dma0_eop__dma0_eop__VAL REG_VAL_ENUM -#define R_IRQ_MASK2_SET__dma0_descr__dma0_descr__VAL REG_VAL_ENUM - -#define R_IRQ_MASK2_SET__dma8_sub3_descr__dma8_sub3_descr__nop 0 -#define R_IRQ_MASK2_SET__dma8_sub3_descr__dma8_sub3_descr__set 1 -#define R_IRQ_MASK2_SET__dma8_sub2_descr__dma8_sub2_descr__nop 0 -#define R_IRQ_MASK2_SET__dma8_sub2_descr__dma8_sub2_descr__set 1 -#define R_IRQ_MASK2_SET__dma8_sub1_descr__dma8_sub1_descr__nop 0 -#define R_IRQ_MASK2_SET__dma8_sub1_descr__dma8_sub1_descr__set 1 -#define R_IRQ_MASK2_SET__dma8_sub0_descr__dma8_sub0_descr__nop 0 -#define R_IRQ_MASK2_SET__dma8_sub0_descr__dma8_sub0_descr__set 1 -#define R_IRQ_MASK2_SET__dma9_eop__dma9_eop__nop 0 -#define R_IRQ_MASK2_SET__dma9_eop__dma9_eop__set 1 -#define R_IRQ_MASK2_SET__dma9_descr__dma9_descr__nop 0 -#define R_IRQ_MASK2_SET__dma9_descr__dma9_descr__set 1 -#define R_IRQ_MASK2_SET__dma8_eop__dma8_eop__nop 0 -#define R_IRQ_MASK2_SET__dma8_eop__dma8_eop__set 1 -#define R_IRQ_MASK2_SET__dma8_descr__dma8_descr__nop 0 -#define R_IRQ_MASK2_SET__dma8_descr__dma8_descr__set 1 -#define R_IRQ_MASK2_SET__dma7_eop__dma7_eop__nop 0 -#define R_IRQ_MASK2_SET__dma7_eop__dma7_eop__set 1 -#define R_IRQ_MASK2_SET__dma7_descr__dma7_descr__nop 0 -#define R_IRQ_MASK2_SET__dma7_descr__dma7_descr__set 1 -#define R_IRQ_MASK2_SET__dma6_eop__dma6_eop__nop 0 -#define R_IRQ_MASK2_SET__dma6_eop__dma6_eop__set 1 -#define R_IRQ_MASK2_SET__dma6_descr__dma6_descr__nop 0 -#define R_IRQ_MASK2_SET__dma6_descr__dma6_descr__set 1 -#define R_IRQ_MASK2_SET__dma5_eop__dma5_eop__nop 0 -#define R_IRQ_MASK2_SET__dma5_eop__dma5_eop__set 1 -#define R_IRQ_MASK2_SET__dma5_descr__dma5_descr__nop 0 -#define R_IRQ_MASK2_SET__dma5_descr__dma5_descr__set 1 -#define R_IRQ_MASK2_SET__dma4_eop__dma4_eop__nop 0 -#define R_IRQ_MASK2_SET__dma4_eop__dma4_eop__set 1 -#define R_IRQ_MASK2_SET__dma4_descr__dma4_descr__nop 0 -#define R_IRQ_MASK2_SET__dma4_descr__dma4_descr__set 1 -#define R_IRQ_MASK2_SET__dma3_eop__dma3_eop__nop 0 -#define R_IRQ_MASK2_SET__dma3_eop__dma3_eop__set 1 -#define R_IRQ_MASK2_SET__dma3_descr__dma3_descr__nop 0 -#define R_IRQ_MASK2_SET__dma3_descr__dma3_descr__set 1 -#define R_IRQ_MASK2_SET__dma2_eop__dma2_eop__nop 0 -#define R_IRQ_MASK2_SET__dma2_eop__dma2_eop__set 1 -#define R_IRQ_MASK2_SET__dma2_descr__dma2_descr__nop 0 -#define R_IRQ_MASK2_SET__dma2_descr__dma2_descr__set 1 -#define R_IRQ_MASK2_SET__dma1_eop__dma1_eop__nop 0 -#define R_IRQ_MASK2_SET__dma1_eop__dma1_eop__set 1 -#define R_IRQ_MASK2_SET__dma1_descr__dma1_descr__nop 0 -#define R_IRQ_MASK2_SET__dma1_descr__dma1_descr__set 1 -#define R_IRQ_MASK2_SET__dma0_eop__dma0_eop__nop 0 -#define R_IRQ_MASK2_SET__dma0_eop__dma0_eop__set 1 -#define R_IRQ_MASK2_SET__dma0_descr__dma0_descr__nop 0 -#define R_IRQ_MASK2_SET__dma0_descr__dma0_descr__set 1 - -#endif - -/* - * R_IRQ_READ0 - * - type: RO - * - addr: 0xb00000c4 - * - group: Interrupt mask and status registers - */ - -#if USE_GROUP__Interrupt_mask_and_status_registers - -#define R_IRQ_READ0__ADDR (REG_TYPECAST_UDWORD 0xb00000c4) -#define R_IRQ_READ0__SVAL REG_SVAL_SHADOW -#define R_IRQ_READ0__SVAL_I REG_SVAL_I_SHADOW -#define R_IRQ_READ0__TYPECAST REG_TYPECAST_UDWORD -#define R_IRQ_READ0__TYPE (REG_UDWORD) -#define R_IRQ_READ0__GET REG_GET_RO -#define R_IRQ_READ0__IGET REG_IGET_RO -#define R_IRQ_READ0__SET REG_SET_RO -#define R_IRQ_READ0__ISET REG_ISET_RO -#define R_IRQ_READ0__SET_VAL REG_SET_VAL_RO -#define R_IRQ_READ0__EQL REG_EQL_RO -#define R_IRQ_READ0__IEQL REG_IEQL_RO -#define R_IRQ_READ0__RD REG_RD_RO -#define R_IRQ_READ0__IRD REG_IRD_RO -#define R_IRQ_READ0__WR REG_WR_RO -#define R_IRQ_READ0__IWR REG_IWR_RO - -#define R_IRQ_READ0__READ(addr) \ - (*(addr)) - -#define R_IRQ_READ0__nmi_pin__nmi_pin__MASK 0x80000000U -#define R_IRQ_READ0__watchdog_nmi__watchdog_nmi__MASK 0x40000000U -#define R_IRQ_READ0__sqe_test_error__sqe_test_error__MASK 0x20000000U -#define R_IRQ_READ0__carrier_loss__carrier_loss__MASK 0x10000000U -#define R_IRQ_READ0__deferred__deferred__MASK 0x08000000U -#define R_IRQ_READ0__late_col__late_col__MASK 0x04000000U -#define R_IRQ_READ0__multiple_col__multiple_col__MASK 0x02000000U -#define R_IRQ_READ0__single_col__single_col__MASK 0x01000000U -#define R_IRQ_READ0__congestion__congestion__MASK 0x00800000U -#define R_IRQ_READ0__oversize__oversize__MASK 0x00400000U -#define R_IRQ_READ0__alignment_error__alignment_error__MASK 0x00200000U -#define R_IRQ_READ0__crc_error__crc_error__MASK 0x00100000U -#define R_IRQ_READ0__overrun__overrun__MASK 0x00080000U -#define R_IRQ_READ0__underrun__underrun__MASK 0x00040000U -#define R_IRQ_READ0__excessive_col__excessive_col__MASK 0x00020000U -#define R_IRQ_READ0__mdio__mdio__MASK 0x00010000U -#define R_IRQ_READ0__ata_drq3__ata_drq3__MASK 0x00008000U -#define R_IRQ_READ0__ata_drq2__ata_drq2__MASK 0x00004000U -#define R_IRQ_READ0__ata_drq1__ata_drq1__MASK 0x00002000U -#define R_IRQ_READ0__ata_drq0__ata_drq0__MASK 0x00001000U -#define R_IRQ_READ0__par0_ecp_cmd__par0_ecp_cmd__MASK 0x00000800U -#define R_IRQ_READ0__ata_irq3__ata_irq3__MASK 0x00000800U -#define R_IRQ_READ0__par0_ecp_cmd__ata_irq3__MASK 0x00000800U -#define R_IRQ_READ0__par0_peri__par0_peri__MASK 0x00000400U -#define R_IRQ_READ0__ata_irq2__ata_irq2__MASK 0x00000400U -#define R_IRQ_READ0__par0_peri__ata_irq2__MASK 0x00000400U -#define R_IRQ_READ0__par0_data__par0_data__MASK 0x00000200U -#define R_IRQ_READ0__ata_irq1__ata_irq1__MASK 0x00000200U -#define R_IRQ_READ0__par0_data__ata_irq1__MASK 0x00000200U -#define R_IRQ_READ0__par0_ready__par0_ready__MASK 0x00000100U -#define R_IRQ_READ0__ata_irq0__ata_irq0__MASK 0x00000100U -#define R_IRQ_READ0__par0_ready__ata_irq0__MASK 0x00000100U -#define R_IRQ_READ0__mio__mio__MASK 0x00000100U -#define R_IRQ_READ0__par0_ready__mio__MASK 0x00000100U -#define R_IRQ_READ0__scsi0__scsi0__MASK 0x00000100U -#define R_IRQ_READ0__par0_ready__scsi0__MASK 0x00000100U -#define R_IRQ_READ0__ata_dmaend__ata_dmaend__MASK 0x00000080U -#define R_IRQ_READ0__irq_ext_vector_nr__irq_ext_vector_nr__MASK 0x00000020U -#define R_IRQ_READ0__irq_int_vector_nr__irq_int_vector_nr__MASK 0x00000010U -#define R_IRQ_READ0__ext_dma1__ext_dma1__MASK 0x00000008U -#define R_IRQ_READ0__ext_dma0__ext_dma0__MASK 0x00000004U -#define R_IRQ_READ0__timer1__timer1__MASK 0x00000002U -#define R_IRQ_READ0__timer0__timer0__MASK 0x00000001U - -#define R_IRQ_READ0__nmi_pin__MAX 0x1 -#define R_IRQ_READ0__watchdog_nmi__MAX 0x1 -#define R_IRQ_READ0__sqe_test_error__MAX 0x1 -#define R_IRQ_READ0__carrier_loss__MAX 0x1 -#define R_IRQ_READ0__deferred__MAX 0x1 -#define R_IRQ_READ0__late_col__MAX 0x1 -#define R_IRQ_READ0__multiple_col__MAX 0x1 -#define R_IRQ_READ0__single_col__MAX 0x1 -#define R_IRQ_READ0__congestion__MAX 0x1 -#define R_IRQ_READ0__oversize__MAX 0x1 -#define R_IRQ_READ0__alignment_error__MAX 0x1 -#define R_IRQ_READ0__crc_error__MAX 0x1 -#define R_IRQ_READ0__overrun__MAX 0x1 -#define R_IRQ_READ0__underrun__MAX 0x1 -#define R_IRQ_READ0__excessive_col__MAX 0x1 -#define R_IRQ_READ0__mdio__MAX 0x1 -#define R_IRQ_READ0__ata_drq3__MAX 0x1 -#define R_IRQ_READ0__ata_drq2__MAX 0x1 -#define R_IRQ_READ0__ata_drq1__MAX 0x1 -#define R_IRQ_READ0__ata_drq0__MAX 0x1 -#define R_IRQ_READ0__par0_ecp_cmd__MAX 0x1 -#define R_IRQ_READ0__ata_irq3__MAX 0x1 -#define R_IRQ_READ0__par0_peri__MAX 0x1 -#define R_IRQ_READ0__ata_irq2__MAX 0x1 -#define R_IRQ_READ0__par0_data__MAX 0x1 -#define R_IRQ_READ0__ata_irq1__MAX 0x1 -#define R_IRQ_READ0__par0_ready__MAX 0x1 -#define R_IRQ_READ0__ata_irq0__MAX 0x1 -#define R_IRQ_READ0__mio__MAX 0x1 -#define R_IRQ_READ0__scsi0__MAX 0x1 -#define R_IRQ_READ0__ata_dmaend__MAX 0x1 -#define R_IRQ_READ0__irq_ext_vector_nr__MAX 0x1 -#define R_IRQ_READ0__irq_int_vector_nr__MAX 0x1 -#define R_IRQ_READ0__ext_dma1__MAX 0x1 -#define R_IRQ_READ0__ext_dma0__MAX 0x1 -#define R_IRQ_READ0__timer1__MAX 0x1 -#define R_IRQ_READ0__timer0__MAX 0x1 - -#define R_IRQ_READ0__nmi_pin__MIN 0 -#define R_IRQ_READ0__watchdog_nmi__MIN 0 -#define R_IRQ_READ0__sqe_test_error__MIN 0 -#define R_IRQ_READ0__carrier_loss__MIN 0 -#define R_IRQ_READ0__deferred__MIN 0 -#define R_IRQ_READ0__late_col__MIN 0 -#define R_IRQ_READ0__multiple_col__MIN 0 -#define R_IRQ_READ0__single_col__MIN 0 -#define R_IRQ_READ0__congestion__MIN 0 -#define R_IRQ_READ0__oversize__MIN 0 -#define R_IRQ_READ0__alignment_error__MIN 0 -#define R_IRQ_READ0__crc_error__MIN 0 -#define R_IRQ_READ0__overrun__MIN 0 -#define R_IRQ_READ0__underrun__MIN 0 -#define R_IRQ_READ0__excessive_col__MIN 0 -#define R_IRQ_READ0__mdio__MIN 0 -#define R_IRQ_READ0__ata_drq3__MIN 0 -#define R_IRQ_READ0__ata_drq2__MIN 0 -#define R_IRQ_READ0__ata_drq1__MIN 0 -#define R_IRQ_READ0__ata_drq0__MIN 0 -#define R_IRQ_READ0__par0_ecp_cmd__MIN 0 -#define R_IRQ_READ0__ata_irq3__MIN 0 -#define R_IRQ_READ0__par0_peri__MIN 0 -#define R_IRQ_READ0__ata_irq2__MIN 0 -#define R_IRQ_READ0__par0_data__MIN 0 -#define R_IRQ_READ0__ata_irq1__MIN 0 -#define R_IRQ_READ0__par0_ready__MIN 0 -#define R_IRQ_READ0__ata_irq0__MIN 0 -#define R_IRQ_READ0__mio__MIN 0 -#define R_IRQ_READ0__scsi0__MIN 0 -#define R_IRQ_READ0__ata_dmaend__MIN 0 -#define R_IRQ_READ0__irq_ext_vector_nr__MIN 0 -#define R_IRQ_READ0__irq_int_vector_nr__MIN 0 -#define R_IRQ_READ0__ext_dma1__MIN 0 -#define R_IRQ_READ0__ext_dma0__MIN 0 -#define R_IRQ_READ0__timer1__MIN 0 -#define R_IRQ_READ0__timer0__MIN 0 - -#define R_IRQ_READ0__nmi_pin__BITNR 31 -#define R_IRQ_READ0__watchdog_nmi__BITNR 30 -#define R_IRQ_READ0__sqe_test_error__BITNR 29 -#define R_IRQ_READ0__carrier_loss__BITNR 28 -#define R_IRQ_READ0__deferred__BITNR 27 -#define R_IRQ_READ0__late_col__BITNR 26 -#define R_IRQ_READ0__multiple_col__BITNR 25 -#define R_IRQ_READ0__single_col__BITNR 24 -#define R_IRQ_READ0__congestion__BITNR 23 -#define R_IRQ_READ0__oversize__BITNR 22 -#define R_IRQ_READ0__alignment_error__BITNR 21 -#define R_IRQ_READ0__crc_error__BITNR 20 -#define R_IRQ_READ0__overrun__BITNR 19 -#define R_IRQ_READ0__underrun__BITNR 18 -#define R_IRQ_READ0__excessive_col__BITNR 17 -#define R_IRQ_READ0__mdio__BITNR 16 -#define R_IRQ_READ0__ata_drq3__BITNR 15 -#define R_IRQ_READ0__ata_drq2__BITNR 14 -#define R_IRQ_READ0__ata_drq1__BITNR 13 -#define R_IRQ_READ0__ata_drq0__BITNR 12 -#define R_IRQ_READ0__par0_ecp_cmd__BITNR 11 -#define R_IRQ_READ0__ata_irq3__BITNR 11 -#define R_IRQ_READ0__par0_peri__BITNR 10 -#define R_IRQ_READ0__ata_irq2__BITNR 10 -#define R_IRQ_READ0__par0_data__BITNR 9 -#define R_IRQ_READ0__ata_irq1__BITNR 9 -#define R_IRQ_READ0__par0_ready__BITNR 8 -#define R_IRQ_READ0__ata_irq0__BITNR 8 -#define R_IRQ_READ0__mio__BITNR 8 -#define R_IRQ_READ0__scsi0__BITNR 8 -#define R_IRQ_READ0__ata_dmaend__BITNR 7 -#define R_IRQ_READ0__irq_ext_vector_nr__BITNR 5 -#define R_IRQ_READ0__irq_int_vector_nr__BITNR 4 -#define R_IRQ_READ0__ext_dma1__BITNR 3 -#define R_IRQ_READ0__ext_dma0__BITNR 2 -#define R_IRQ_READ0__timer1__BITNR 1 -#define R_IRQ_READ0__timer0__BITNR 0 - -#define R_IRQ_READ0__nmi_pin__nmi_pin__VAL REG_VAL_ENUM -#define R_IRQ_READ0__watchdog_nmi__watchdog_nmi__VAL REG_VAL_ENUM -#define R_IRQ_READ0__sqe_test_error__sqe_test_error__VAL REG_VAL_ENUM -#define R_IRQ_READ0__carrier_loss__carrier_loss__VAL REG_VAL_ENUM -#define R_IRQ_READ0__deferred__deferred__VAL REG_VAL_ENUM -#define R_IRQ_READ0__late_col__late_col__VAL REG_VAL_ENUM -#define R_IRQ_READ0__multiple_col__multiple_col__VAL REG_VAL_ENUM -#define R_IRQ_READ0__single_col__single_col__VAL REG_VAL_ENUM -#define R_IRQ_READ0__congestion__congestion__VAL REG_VAL_ENUM -#define R_IRQ_READ0__oversize__oversize__VAL REG_VAL_ENUM -#define R_IRQ_READ0__alignment_error__alignment_error__VAL REG_VAL_ENUM -#define R_IRQ_READ0__crc_error__crc_error__VAL REG_VAL_ENUM -#define R_IRQ_READ0__overrun__overrun__VAL REG_VAL_ENUM -#define R_IRQ_READ0__underrun__underrun__VAL REG_VAL_ENUM -#define R_IRQ_READ0__excessive_col__excessive_col__VAL REG_VAL_ENUM -#define R_IRQ_READ0__mdio__mdio__VAL REG_VAL_ENUM -#define R_IRQ_READ0__ata_drq3__ata_drq3__VAL REG_VAL_ENUM -#define R_IRQ_READ0__ata_drq2__ata_drq2__VAL REG_VAL_ENUM -#define R_IRQ_READ0__ata_drq1__ata_drq1__VAL REG_VAL_ENUM -#define R_IRQ_READ0__ata_drq0__ata_drq0__VAL REG_VAL_ENUM -#define R_IRQ_READ0__par0_ecp_cmd__par0_ecp_cmd__VAL REG_VAL_ENUM -#define R_IRQ_READ0__ata_irq3__ata_irq3__VAL REG_VAL_ENUM -#define R_IRQ_READ0__par0_ecp_cmd__ata_irq3__VAL REG_VAL_ENUM -#define R_IRQ_READ0__par0_peri__par0_peri__VAL REG_VAL_ENUM -#define R_IRQ_READ0__ata_irq2__ata_irq2__VAL REG_VAL_ENUM -#define R_IRQ_READ0__par0_peri__ata_irq2__VAL REG_VAL_ENUM -#define R_IRQ_READ0__par0_data__par0_data__VAL REG_VAL_ENUM -#define R_IRQ_READ0__ata_irq1__ata_irq1__VAL REG_VAL_ENUM -#define R_IRQ_READ0__par0_data__ata_irq1__VAL REG_VAL_ENUM -#define R_IRQ_READ0__par0_ready__par0_ready__VAL REG_VAL_ENUM -#define R_IRQ_READ0__ata_irq0__ata_irq0__VAL REG_VAL_ENUM -#define R_IRQ_READ0__par0_ready__ata_irq0__VAL REG_VAL_ENUM -#define R_IRQ_READ0__mio__mio__VAL REG_VAL_ENUM -#define R_IRQ_READ0__par0_ready__mio__VAL REG_VAL_ENUM -#define R_IRQ_READ0__scsi0__scsi0__VAL REG_VAL_ENUM -#define R_IRQ_READ0__par0_ready__scsi0__VAL REG_VAL_ENUM -#define R_IRQ_READ0__ata_dmaend__ata_dmaend__VAL REG_VAL_ENUM -#define R_IRQ_READ0__irq_ext_vector_nr__irq_ext_vector_nr__VAL REG_VAL_ENUM -#define R_IRQ_READ0__irq_int_vector_nr__irq_int_vector_nr__VAL REG_VAL_ENUM -#define R_IRQ_READ0__ext_dma1__ext_dma1__VAL REG_VAL_ENUM -#define R_IRQ_READ0__ext_dma0__ext_dma0__VAL REG_VAL_ENUM -#define R_IRQ_READ0__timer1__timer1__VAL REG_VAL_ENUM -#define R_IRQ_READ0__timer0__timer0__VAL REG_VAL_ENUM - -#define R_IRQ_READ0__nmi_pin__nmi_pin__active 1 -#define R_IRQ_READ0__nmi_pin__nmi_pin__inactive 0 -#define R_IRQ_READ0__watchdog_nmi__watchdog_nmi__active 1 -#define R_IRQ_READ0__watchdog_nmi__watchdog_nmi__inactive 0 -#define R_IRQ_READ0__sqe_test_error__sqe_test_error__active 1 -#define R_IRQ_READ0__sqe_test_error__sqe_test_error__inactive 0 -#define R_IRQ_READ0__carrier_loss__carrier_loss__active 1 -#define R_IRQ_READ0__carrier_loss__carrier_loss__inactive 0 -#define R_IRQ_READ0__deferred__deferred__active 1 -#define R_IRQ_READ0__deferred__deferred__inactive 0 -#define R_IRQ_READ0__late_col__late_col__active 1 -#define R_IRQ_READ0__late_col__late_col__inactive 0 -#define R_IRQ_READ0__multiple_col__multiple_col__active 1 -#define R_IRQ_READ0__multiple_col__multiple_col__inactive 0 -#define R_IRQ_READ0__single_col__single_col__active 1 -#define R_IRQ_READ0__single_col__single_col__inactive 0 -#define R_IRQ_READ0__congestion__congestion__active 1 -#define R_IRQ_READ0__congestion__congestion__inactive 0 -#define R_IRQ_READ0__oversize__oversize__active 1 -#define R_IRQ_READ0__oversize__oversize__inactive 0 -#define R_IRQ_READ0__alignment_error__alignment_error__active 1 -#define R_IRQ_READ0__alignment_error__alignment_error__inactive 0 -#define R_IRQ_READ0__crc_error__crc_error__active 1 -#define R_IRQ_READ0__crc_error__crc_error__inactive 0 -#define R_IRQ_READ0__overrun__overrun__active 1 -#define R_IRQ_READ0__overrun__overrun__inactive 0 -#define R_IRQ_READ0__underrun__underrun__active 1 -#define R_IRQ_READ0__underrun__underrun__inactive 0 -#define R_IRQ_READ0__excessive_col__excessive_col__active 1 -#define R_IRQ_READ0__excessive_col__excessive_col__inactive 0 -#define R_IRQ_READ0__mdio__mdio__active 1 -#define R_IRQ_READ0__mdio__mdio__inactive 0 -#define R_IRQ_READ0__ata_drq3__ata_drq3__active 1 -#define R_IRQ_READ0__ata_drq3__ata_drq3__inactive 0 -#define R_IRQ_READ0__ata_drq2__ata_drq2__active 1 -#define R_IRQ_READ0__ata_drq2__ata_drq2__inactive 0 -#define R_IRQ_READ0__ata_drq1__ata_drq1__active 1 -#define R_IRQ_READ0__ata_drq1__ata_drq1__inactive 0 -#define R_IRQ_READ0__ata_drq0__ata_drq0__active 1 -#define R_IRQ_READ0__ata_drq0__ata_drq0__inactive 0 -#define R_IRQ_READ0__par0_ecp_cmd__par0_ecp_cmd__active 1 -#define R_IRQ_READ0__par0_ecp_cmd__par0_ecp_cmd__inactive 0 -#define R_IRQ_READ0__ata_irq3__ata_irq3__active 1 -#define R_IRQ_READ0__ata_irq3__ata_irq3__inactive 0 -#define R_IRQ_READ0__par0_peri__par0_peri__active 1 -#define R_IRQ_READ0__par0_peri__par0_peri__inactive 0 -#define R_IRQ_READ0__ata_irq2__ata_irq2__active 1 -#define R_IRQ_READ0__ata_irq2__ata_irq2__inactive 0 -#define R_IRQ_READ0__par0_data__par0_data__active 1 -#define R_IRQ_READ0__par0_data__par0_data__inactive 0 -#define R_IRQ_READ0__ata_irq1__ata_irq1__active 1 -#define R_IRQ_READ0__ata_irq1__ata_irq1__inactive 0 -#define R_IRQ_READ0__par0_ready__par0_ready__active 1 -#define R_IRQ_READ0__par0_ready__par0_ready__inactive 0 -#define R_IRQ_READ0__ata_irq0__ata_irq0__active 1 -#define R_IRQ_READ0__ata_irq0__ata_irq0__inactive 0 -#define R_IRQ_READ0__mio__mio__active 1 -#define R_IRQ_READ0__mio__mio__inactive 0 -#define R_IRQ_READ0__scsi0__scsi0__active 1 -#define R_IRQ_READ0__scsi0__scsi0__inactive 0 -#define R_IRQ_READ0__ata_dmaend__ata_dmaend__active 1 -#define R_IRQ_READ0__ata_dmaend__ata_dmaend__inactive 0 -#define R_IRQ_READ0__irq_ext_vector_nr__irq_ext_vector_nr__active 1 -#define R_IRQ_READ0__irq_ext_vector_nr__irq_ext_vector_nr__inactive 0 -#define R_IRQ_READ0__irq_int_vector_nr__irq_int_vector_nr__active 1 -#define R_IRQ_READ0__irq_int_vector_nr__irq_int_vector_nr__inactive 0 -#define R_IRQ_READ0__ext_dma1__ext_dma1__active 1 -#define R_IRQ_READ0__ext_dma1__ext_dma1__inactive 0 -#define R_IRQ_READ0__ext_dma0__ext_dma0__active 1 -#define R_IRQ_READ0__ext_dma0__ext_dma0__inactive 0 -#define R_IRQ_READ0__timer1__timer1__active 1 -#define R_IRQ_READ0__timer1__timer1__inactive 0 -#define R_IRQ_READ0__timer0__timer0__active 1 -#define R_IRQ_READ0__timer0__timer0__inactive 0 - -#endif - -/* - * R_IRQ_READ1 - * - type: RO - * - addr: 0xb00000cc - * - group: Interrupt mask and status registers - */ - -#if USE_GROUP__Interrupt_mask_and_status_registers - -#define R_IRQ_READ1__ADDR (REG_TYPECAST_UDWORD 0xb00000cc) -#define R_IRQ_READ1__SVAL REG_SVAL_SHADOW -#define R_IRQ_READ1__SVAL_I REG_SVAL_I_SHADOW -#define R_IRQ_READ1__TYPECAST REG_TYPECAST_UDWORD -#define R_IRQ_READ1__TYPE (REG_UDWORD) -#define R_IRQ_READ1__GET REG_GET_RO -#define R_IRQ_READ1__IGET REG_IGET_RO -#define R_IRQ_READ1__SET REG_SET_RO -#define R_IRQ_READ1__ISET REG_ISET_RO -#define R_IRQ_READ1__SET_VAL REG_SET_VAL_RO -#define R_IRQ_READ1__EQL REG_EQL_RO -#define R_IRQ_READ1__IEQL REG_IEQL_RO -#define R_IRQ_READ1__RD REG_RD_RO -#define R_IRQ_READ1__IRD REG_IRD_RO -#define R_IRQ_READ1__WR REG_WR_RO -#define R_IRQ_READ1__IWR REG_IWR_RO - -#define R_IRQ_READ1__READ(addr) \ - (*(addr)) - -#define R_IRQ_READ1__sw_int7__sw_int7__MASK 0x80000000U -#define R_IRQ_READ1__sw_int6__sw_int6__MASK 0x40000000U -#define R_IRQ_READ1__sw_int5__sw_int5__MASK 0x20000000U -#define R_IRQ_READ1__sw_int4__sw_int4__MASK 0x10000000U -#define R_IRQ_READ1__sw_int3__sw_int3__MASK 0x08000000U -#define R_IRQ_READ1__sw_int2__sw_int2__MASK 0x04000000U -#define R_IRQ_READ1__sw_int1__sw_int1__MASK 0x02000000U -#define R_IRQ_READ1__sw_int0__sw_int0__MASK 0x01000000U -#define R_IRQ_READ1__par1_ecp_cmd__par1_ecp_cmd__MASK 0x00080000U -#define R_IRQ_READ1__par1_peri__par1_peri__MASK 0x00040000U -#define R_IRQ_READ1__par1_data__par1_data__MASK 0x00020000U -#define R_IRQ_READ1__par1_ready__par1_ready__MASK 0x00010000U -#define R_IRQ_READ1__scsi1__scsi1__MASK 0x00010000U -#define R_IRQ_READ1__par1_ready__scsi1__MASK 0x00010000U -#define R_IRQ_READ1__ser3_ready__ser3_ready__MASK 0x00008000U -#define R_IRQ_READ1__ser3_data__ser3_data__MASK 0x00004000U -#define R_IRQ_READ1__ser2_ready__ser2_ready__MASK 0x00002000U -#define R_IRQ_READ1__ser2_data__ser2_data__MASK 0x00001000U -#define R_IRQ_READ1__ser1_ready__ser1_ready__MASK 0x00000800U -#define R_IRQ_READ1__ser1_data__ser1_data__MASK 0x00000400U -#define R_IRQ_READ1__ser0_ready__ser0_ready__MASK 0x00000200U -#define R_IRQ_READ1__ser0_data__ser0_data__MASK 0x00000100U -#define R_IRQ_READ1__pa7__pa7__MASK 0x00000080U -#define R_IRQ_READ1__pa6__pa6__MASK 0x00000040U -#define R_IRQ_READ1__pa5__pa5__MASK 0x00000020U -#define R_IRQ_READ1__pa4__pa4__MASK 0x00000010U -#define R_IRQ_READ1__pa3__pa3__MASK 0x00000008U -#define R_IRQ_READ1__pa2__pa2__MASK 0x00000004U -#define R_IRQ_READ1__pa1__pa1__MASK 0x00000002U -#define R_IRQ_READ1__pa0__pa0__MASK 0x00000001U - -#define R_IRQ_READ1__sw_int7__MAX 0x1 -#define R_IRQ_READ1__sw_int6__MAX 0x1 -#define R_IRQ_READ1__sw_int5__MAX 0x1 -#define R_IRQ_READ1__sw_int4__MAX 0x1 -#define R_IRQ_READ1__sw_int3__MAX 0x1 -#define R_IRQ_READ1__sw_int2__MAX 0x1 -#define R_IRQ_READ1__sw_int1__MAX 0x1 -#define R_IRQ_READ1__sw_int0__MAX 0x1 -#define R_IRQ_READ1__par1_ecp_cmd__MAX 0x1 -#define R_IRQ_READ1__par1_peri__MAX 0x1 -#define R_IRQ_READ1__par1_data__MAX 0x1 -#define R_IRQ_READ1__par1_ready__MAX 0x1 -#define R_IRQ_READ1__scsi1__MAX 0x1 -#define R_IRQ_READ1__ser3_ready__MAX 0x1 -#define R_IRQ_READ1__ser3_data__MAX 0x1 -#define R_IRQ_READ1__ser2_ready__MAX 0x1 -#define R_IRQ_READ1__ser2_data__MAX 0x1 -#define R_IRQ_READ1__ser1_ready__MAX 0x1 -#define R_IRQ_READ1__ser1_data__MAX 0x1 -#define R_IRQ_READ1__ser0_ready__MAX 0x1 -#define R_IRQ_READ1__ser0_data__MAX 0x1 -#define R_IRQ_READ1__pa7__MAX 0x1 -#define R_IRQ_READ1__pa6__MAX 0x1 -#define R_IRQ_READ1__pa5__MAX 0x1 -#define R_IRQ_READ1__pa4__MAX 0x1 -#define R_IRQ_READ1__pa3__MAX 0x1 -#define R_IRQ_READ1__pa2__MAX 0x1 -#define R_IRQ_READ1__pa1__MAX 0x1 -#define R_IRQ_READ1__pa0__MAX 0x1 - -#define R_IRQ_READ1__sw_int7__MIN 0 -#define R_IRQ_READ1__sw_int6__MIN 0 -#define R_IRQ_READ1__sw_int5__MIN 0 -#define R_IRQ_READ1__sw_int4__MIN 0 -#define R_IRQ_READ1__sw_int3__MIN 0 -#define R_IRQ_READ1__sw_int2__MIN 0 -#define R_IRQ_READ1__sw_int1__MIN 0 -#define R_IRQ_READ1__sw_int0__MIN 0 -#define R_IRQ_READ1__par1_ecp_cmd__MIN 0 -#define R_IRQ_READ1__par1_peri__MIN 0 -#define R_IRQ_READ1__par1_data__MIN 0 -#define R_IRQ_READ1__par1_ready__MIN 0 -#define R_IRQ_READ1__scsi1__MIN 0 -#define R_IRQ_READ1__ser3_ready__MIN 0 -#define R_IRQ_READ1__ser3_data__MIN 0 -#define R_IRQ_READ1__ser2_ready__MIN 0 -#define R_IRQ_READ1__ser2_data__MIN 0 -#define R_IRQ_READ1__ser1_ready__MIN 0 -#define R_IRQ_READ1__ser1_data__MIN 0 -#define R_IRQ_READ1__ser0_ready__MIN 0 -#define R_IRQ_READ1__ser0_data__MIN 0 -#define R_IRQ_READ1__pa7__MIN 0 -#define R_IRQ_READ1__pa6__MIN 0 -#define R_IRQ_READ1__pa5__MIN 0 -#define R_IRQ_READ1__pa4__MIN 0 -#define R_IRQ_READ1__pa3__MIN 0 -#define R_IRQ_READ1__pa2__MIN 0 -#define R_IRQ_READ1__pa1__MIN 0 -#define R_IRQ_READ1__pa0__MIN 0 - -#define R_IRQ_READ1__sw_int7__BITNR 31 -#define R_IRQ_READ1__sw_int6__BITNR 30 -#define R_IRQ_READ1__sw_int5__BITNR 29 -#define R_IRQ_READ1__sw_int4__BITNR 28 -#define R_IRQ_READ1__sw_int3__BITNR 27 -#define R_IRQ_READ1__sw_int2__BITNR 26 -#define R_IRQ_READ1__sw_int1__BITNR 25 -#define R_IRQ_READ1__sw_int0__BITNR 24 -#define R_IRQ_READ1__par1_ecp_cmd__BITNR 19 -#define R_IRQ_READ1__par1_peri__BITNR 18 -#define R_IRQ_READ1__par1_data__BITNR 17 -#define R_IRQ_READ1__par1_ready__BITNR 16 -#define R_IRQ_READ1__scsi1__BITNR 16 -#define R_IRQ_READ1__ser3_ready__BITNR 15 -#define R_IRQ_READ1__ser3_data__BITNR 14 -#define R_IRQ_READ1__ser2_ready__BITNR 13 -#define R_IRQ_READ1__ser2_data__BITNR 12 -#define R_IRQ_READ1__ser1_ready__BITNR 11 -#define R_IRQ_READ1__ser1_data__BITNR 10 -#define R_IRQ_READ1__ser0_ready__BITNR 9 -#define R_IRQ_READ1__ser0_data__BITNR 8 -#define R_IRQ_READ1__pa7__BITNR 7 -#define R_IRQ_READ1__pa6__BITNR 6 -#define R_IRQ_READ1__pa5__BITNR 5 -#define R_IRQ_READ1__pa4__BITNR 4 -#define R_IRQ_READ1__pa3__BITNR 3 -#define R_IRQ_READ1__pa2__BITNR 2 -#define R_IRQ_READ1__pa1__BITNR 1 -#define R_IRQ_READ1__pa0__BITNR 0 - -#define R_IRQ_READ1__sw_int7__sw_int7__VAL REG_VAL_ENUM -#define R_IRQ_READ1__sw_int6__sw_int6__VAL REG_VAL_ENUM -#define R_IRQ_READ1__sw_int5__sw_int5__VAL REG_VAL_ENUM -#define R_IRQ_READ1__sw_int4__sw_int4__VAL REG_VAL_ENUM -#define R_IRQ_READ1__sw_int3__sw_int3__VAL REG_VAL_ENUM -#define R_IRQ_READ1__sw_int2__sw_int2__VAL REG_VAL_ENUM -#define R_IRQ_READ1__sw_int1__sw_int1__VAL REG_VAL_ENUM -#define R_IRQ_READ1__sw_int0__sw_int0__VAL REG_VAL_ENUM -#define R_IRQ_READ1__par1_ecp_cmd__par1_ecp_cmd__VAL REG_VAL_ENUM -#define R_IRQ_READ1__par1_peri__par1_peri__VAL REG_VAL_ENUM -#define R_IRQ_READ1__par1_data__par1_data__VAL REG_VAL_ENUM -#define R_IRQ_READ1__par1_ready__par1_ready__VAL REG_VAL_ENUM -#define R_IRQ_READ1__scsi1__scsi1__VAL REG_VAL_ENUM -#define R_IRQ_READ1__par1_ready__scsi1__VAL REG_VAL_ENUM -#define R_IRQ_READ1__ser3_ready__ser3_ready__VAL REG_VAL_ENUM -#define R_IRQ_READ1__ser3_data__ser3_data__VAL REG_VAL_ENUM -#define R_IRQ_READ1__ser2_ready__ser2_ready__VAL REG_VAL_ENUM -#define R_IRQ_READ1__ser2_data__ser2_data__VAL REG_VAL_ENUM -#define R_IRQ_READ1__ser1_ready__ser1_ready__VAL REG_VAL_ENUM -#define R_IRQ_READ1__ser1_data__ser1_data__VAL REG_VAL_ENUM -#define R_IRQ_READ1__ser0_ready__ser0_ready__VAL REG_VAL_ENUM -#define R_IRQ_READ1__ser0_data__ser0_data__VAL REG_VAL_ENUM -#define R_IRQ_READ1__pa7__pa7__VAL REG_VAL_ENUM -#define R_IRQ_READ1__pa6__pa6__VAL REG_VAL_ENUM -#define R_IRQ_READ1__pa5__pa5__VAL REG_VAL_ENUM -#define R_IRQ_READ1__pa4__pa4__VAL REG_VAL_ENUM -#define R_IRQ_READ1__pa3__pa3__VAL REG_VAL_ENUM -#define R_IRQ_READ1__pa2__pa2__VAL REG_VAL_ENUM -#define R_IRQ_READ1__pa1__pa1__VAL REG_VAL_ENUM -#define R_IRQ_READ1__pa0__pa0__VAL REG_VAL_ENUM - -#define R_IRQ_READ1__sw_int7__sw_int7__active 1 -#define R_IRQ_READ1__sw_int7__sw_int7__inactive 0 -#define R_IRQ_READ1__sw_int6__sw_int6__active 1 -#define R_IRQ_READ1__sw_int6__sw_int6__inactive 0 -#define R_IRQ_READ1__sw_int5__sw_int5__active 1 -#define R_IRQ_READ1__sw_int5__sw_int5__inactive 0 -#define R_IRQ_READ1__sw_int4__sw_int4__active 1 -#define R_IRQ_READ1__sw_int4__sw_int4__inactive 0 -#define R_IRQ_READ1__sw_int3__sw_int3__active 1 -#define R_IRQ_READ1__sw_int3__sw_int3__inactive 0 -#define R_IRQ_READ1__sw_int2__sw_int2__active 1 -#define R_IRQ_READ1__sw_int2__sw_int2__inactive 0 -#define R_IRQ_READ1__sw_int1__sw_int1__active 1 -#define R_IRQ_READ1__sw_int1__sw_int1__inactive 0 -#define R_IRQ_READ1__sw_int0__sw_int0__active 1 -#define R_IRQ_READ1__sw_int0__sw_int0__inactive 0 -#define R_IRQ_READ1__par1_ecp_cmd__par1_ecp_cmd__active 1 -#define R_IRQ_READ1__par1_ecp_cmd__par1_ecp_cmd__inactive 0 -#define R_IRQ_READ1__par1_peri__par1_peri__active 1 -#define R_IRQ_READ1__par1_peri__par1_peri__inactive 0 -#define R_IRQ_READ1__par1_data__par1_data__active 1 -#define R_IRQ_READ1__par1_data__par1_data__inactive 0 -#define R_IRQ_READ1__par1_ready__par1_ready__active 1 -#define R_IRQ_READ1__par1_ready__par1_ready__inactive 0 -#define R_IRQ_READ1__scsi1__scsi1__active 1 -#define R_IRQ_READ1__scsi1__scsi1__inactive 0 -#define R_IRQ_READ1__ser3_ready__ser3_ready__active 1 -#define R_IRQ_READ1__ser3_ready__ser3_ready__inactive 0 -#define R_IRQ_READ1__ser3_data__ser3_data__active 1 -#define R_IRQ_READ1__ser3_data__ser3_data__inactive 0 -#define R_IRQ_READ1__ser2_ready__ser2_ready__active 1 -#define R_IRQ_READ1__ser2_ready__ser2_ready__inactive 0 -#define R_IRQ_READ1__ser2_data__ser2_data__active 1 -#define R_IRQ_READ1__ser2_data__ser2_data__inactive 0 -#define R_IRQ_READ1__ser1_ready__ser1_ready__active 1 -#define R_IRQ_READ1__ser1_ready__ser1_ready__inactive 0 -#define R_IRQ_READ1__ser1_data__ser1_data__active 1 -#define R_IRQ_READ1__ser1_data__ser1_data__inactive 0 -#define R_IRQ_READ1__ser0_ready__ser0_ready__active 1 -#define R_IRQ_READ1__ser0_ready__ser0_ready__inactive 0 -#define R_IRQ_READ1__ser0_data__ser0_data__active 1 -#define R_IRQ_READ1__ser0_data__ser0_data__inactive 0 -#define R_IRQ_READ1__pa7__pa7__active 1 -#define R_IRQ_READ1__pa7__pa7__inactive 0 -#define R_IRQ_READ1__pa6__pa6__active 1 -#define R_IRQ_READ1__pa6__pa6__inactive 0 -#define R_IRQ_READ1__pa5__pa5__active 1 -#define R_IRQ_READ1__pa5__pa5__inactive 0 -#define R_IRQ_READ1__pa4__pa4__active 1 -#define R_IRQ_READ1__pa4__pa4__inactive 0 -#define R_IRQ_READ1__pa3__pa3__active 1 -#define R_IRQ_READ1__pa3__pa3__inactive 0 -#define R_IRQ_READ1__pa2__pa2__active 1 -#define R_IRQ_READ1__pa2__pa2__inactive 0 -#define R_IRQ_READ1__pa1__pa1__active 1 -#define R_IRQ_READ1__pa1__pa1__inactive 0 -#define R_IRQ_READ1__pa0__pa0__active 1 -#define R_IRQ_READ1__pa0__pa0__inactive 0 - -#endif - -/* - * R_IRQ_READ2 - * - type: RO - * - addr: 0xb00000d4 - * - group: Interrupt mask and status registers - */ - -#if USE_GROUP__Interrupt_mask_and_status_registers - -#define R_IRQ_READ2__ADDR (REG_TYPECAST_UDWORD 0xb00000d4) -#define R_IRQ_READ2__SVAL REG_SVAL_SHADOW -#define R_IRQ_READ2__SVAL_I REG_SVAL_I_SHADOW -#define R_IRQ_READ2__TYPECAST REG_TYPECAST_UDWORD -#define R_IRQ_READ2__TYPE (REG_UDWORD) -#define R_IRQ_READ2__GET REG_GET_RO -#define R_IRQ_READ2__IGET REG_IGET_RO -#define R_IRQ_READ2__SET REG_SET_RO -#define R_IRQ_READ2__ISET REG_ISET_RO -#define R_IRQ_READ2__SET_VAL REG_SET_VAL_RO -#define R_IRQ_READ2__EQL REG_EQL_RO -#define R_IRQ_READ2__IEQL REG_IEQL_RO -#define R_IRQ_READ2__RD REG_RD_RO -#define R_IRQ_READ2__IRD REG_IRD_RO -#define R_IRQ_READ2__WR REG_WR_RO -#define R_IRQ_READ2__IWR REG_IWR_RO - -#define R_IRQ_READ2__READ(addr) \ - (*(addr)) - -#define R_IRQ_READ2__dma8_sub3_descr__dma8_sub3_descr__MASK 0x00800000U -#define R_IRQ_READ2__dma8_sub2_descr__dma8_sub2_descr__MASK 0x00400000U -#define R_IRQ_READ2__dma8_sub1_descr__dma8_sub1_descr__MASK 0x00200000U -#define R_IRQ_READ2__dma8_sub0_descr__dma8_sub0_descr__MASK 0x00100000U -#define R_IRQ_READ2__dma9_eop__dma9_eop__MASK 0x00080000U -#define R_IRQ_READ2__dma9_descr__dma9_descr__MASK 0x00040000U -#define R_IRQ_READ2__dma8_eop__dma8_eop__MASK 0x00020000U -#define R_IRQ_READ2__dma8_descr__dma8_descr__MASK 0x00010000U -#define R_IRQ_READ2__dma7_eop__dma7_eop__MASK 0x00008000U -#define R_IRQ_READ2__dma7_descr__dma7_descr__MASK 0x00004000U -#define R_IRQ_READ2__dma6_eop__dma6_eop__MASK 0x00002000U -#define R_IRQ_READ2__dma6_descr__dma6_descr__MASK 0x00001000U -#define R_IRQ_READ2__dma5_eop__dma5_eop__MASK 0x00000800U -#define R_IRQ_READ2__dma5_descr__dma5_descr__MASK 0x00000400U -#define R_IRQ_READ2__dma4_eop__dma4_eop__MASK 0x00000200U -#define R_IRQ_READ2__dma4_descr__dma4_descr__MASK 0x00000100U -#define R_IRQ_READ2__dma3_eop__dma3_eop__MASK 0x00000080U -#define R_IRQ_READ2__dma3_descr__dma3_descr__MASK 0x00000040U -#define R_IRQ_READ2__dma2_eop__dma2_eop__MASK 0x00000020U -#define R_IRQ_READ2__dma2_descr__dma2_descr__MASK 0x00000010U -#define R_IRQ_READ2__dma1_eop__dma1_eop__MASK 0x00000008U -#define R_IRQ_READ2__dma1_descr__dma1_descr__MASK 0x00000004U -#define R_IRQ_READ2__dma0_eop__dma0_eop__MASK 0x00000002U -#define R_IRQ_READ2__dma0_descr__dma0_descr__MASK 0x00000001U - -#define R_IRQ_READ2__dma8_sub3_descr__MAX 0x1 -#define R_IRQ_READ2__dma8_sub2_descr__MAX 0x1 -#define R_IRQ_READ2__dma8_sub1_descr__MAX 0x1 -#define R_IRQ_READ2__dma8_sub0_descr__MAX 0x1 -#define R_IRQ_READ2__dma9_eop__MAX 0x1 -#define R_IRQ_READ2__dma9_descr__MAX 0x1 -#define R_IRQ_READ2__dma8_eop__MAX 0x1 -#define R_IRQ_READ2__dma8_descr__MAX 0x1 -#define R_IRQ_READ2__dma7_eop__MAX 0x1 -#define R_IRQ_READ2__dma7_descr__MAX 0x1 -#define R_IRQ_READ2__dma6_eop__MAX 0x1 -#define R_IRQ_READ2__dma6_descr__MAX 0x1 -#define R_IRQ_READ2__dma5_eop__MAX 0x1 -#define R_IRQ_READ2__dma5_descr__MAX 0x1 -#define R_IRQ_READ2__dma4_eop__MAX 0x1 -#define R_IRQ_READ2__dma4_descr__MAX 0x1 -#define R_IRQ_READ2__dma3_eop__MAX 0x1 -#define R_IRQ_READ2__dma3_descr__MAX 0x1 -#define R_IRQ_READ2__dma2_eop__MAX 0x1 -#define R_IRQ_READ2__dma2_descr__MAX 0x1 -#define R_IRQ_READ2__dma1_eop__MAX 0x1 -#define R_IRQ_READ2__dma1_descr__MAX 0x1 -#define R_IRQ_READ2__dma0_eop__MAX 0x1 -#define R_IRQ_READ2__dma0_descr__MAX 0x1 - -#define R_IRQ_READ2__dma8_sub3_descr__MIN 0 -#define R_IRQ_READ2__dma8_sub2_descr__MIN 0 -#define R_IRQ_READ2__dma8_sub1_descr__MIN 0 -#define R_IRQ_READ2__dma8_sub0_descr__MIN 0 -#define R_IRQ_READ2__dma9_eop__MIN 0 -#define R_IRQ_READ2__dma9_descr__MIN 0 -#define R_IRQ_READ2__dma8_eop__MIN 0 -#define R_IRQ_READ2__dma8_descr__MIN 0 -#define R_IRQ_READ2__dma7_eop__MIN 0 -#define R_IRQ_READ2__dma7_descr__MIN 0 -#define R_IRQ_READ2__dma6_eop__MIN 0 -#define R_IRQ_READ2__dma6_descr__MIN 0 -#define R_IRQ_READ2__dma5_eop__MIN 0 -#define R_IRQ_READ2__dma5_descr__MIN 0 -#define R_IRQ_READ2__dma4_eop__MIN 0 -#define R_IRQ_READ2__dma4_descr__MIN 0 -#define R_IRQ_READ2__dma3_eop__MIN 0 -#define R_IRQ_READ2__dma3_descr__MIN 0 -#define R_IRQ_READ2__dma2_eop__MIN 0 -#define R_IRQ_READ2__dma2_descr__MIN 0 -#define R_IRQ_READ2__dma1_eop__MIN 0 -#define R_IRQ_READ2__dma1_descr__MIN 0 -#define R_IRQ_READ2__dma0_eop__MIN 0 -#define R_IRQ_READ2__dma0_descr__MIN 0 - -#define R_IRQ_READ2__dma8_sub3_descr__BITNR 23 -#define R_IRQ_READ2__dma8_sub2_descr__BITNR 22 -#define R_IRQ_READ2__dma8_sub1_descr__BITNR 21 -#define R_IRQ_READ2__dma8_sub0_descr__BITNR 20 -#define R_IRQ_READ2__dma9_eop__BITNR 19 -#define R_IRQ_READ2__dma9_descr__BITNR 18 -#define R_IRQ_READ2__dma8_eop__BITNR 17 -#define R_IRQ_READ2__dma8_descr__BITNR 16 -#define R_IRQ_READ2__dma7_eop__BITNR 15 -#define R_IRQ_READ2__dma7_descr__BITNR 14 -#define R_IRQ_READ2__dma6_eop__BITNR 13 -#define R_IRQ_READ2__dma6_descr__BITNR 12 -#define R_IRQ_READ2__dma5_eop__BITNR 11 -#define R_IRQ_READ2__dma5_descr__BITNR 10 -#define R_IRQ_READ2__dma4_eop__BITNR 9 -#define R_IRQ_READ2__dma4_descr__BITNR 8 -#define R_IRQ_READ2__dma3_eop__BITNR 7 -#define R_IRQ_READ2__dma3_descr__BITNR 6 -#define R_IRQ_READ2__dma2_eop__BITNR 5 -#define R_IRQ_READ2__dma2_descr__BITNR 4 -#define R_IRQ_READ2__dma1_eop__BITNR 3 -#define R_IRQ_READ2__dma1_descr__BITNR 2 -#define R_IRQ_READ2__dma0_eop__BITNR 1 -#define R_IRQ_READ2__dma0_descr__BITNR 0 - -#define R_IRQ_READ2__dma8_sub3_descr__dma8_sub3_descr__VAL REG_VAL_ENUM -#define R_IRQ_READ2__dma8_sub2_descr__dma8_sub2_descr__VAL REG_VAL_ENUM -#define R_IRQ_READ2__dma8_sub1_descr__dma8_sub1_descr__VAL REG_VAL_ENUM -#define R_IRQ_READ2__dma8_sub0_descr__dma8_sub0_descr__VAL REG_VAL_ENUM -#define R_IRQ_READ2__dma9_eop__dma9_eop__VAL REG_VAL_ENUM -#define R_IRQ_READ2__dma9_descr__dma9_descr__VAL REG_VAL_ENUM -#define R_IRQ_READ2__dma8_eop__dma8_eop__VAL REG_VAL_ENUM -#define R_IRQ_READ2__dma8_descr__dma8_descr__VAL REG_VAL_ENUM -#define R_IRQ_READ2__dma7_eop__dma7_eop__VAL REG_VAL_ENUM -#define R_IRQ_READ2__dma7_descr__dma7_descr__VAL REG_VAL_ENUM -#define R_IRQ_READ2__dma6_eop__dma6_eop__VAL REG_VAL_ENUM -#define R_IRQ_READ2__dma6_descr__dma6_descr__VAL REG_VAL_ENUM -#define R_IRQ_READ2__dma5_eop__dma5_eop__VAL REG_VAL_ENUM -#define R_IRQ_READ2__dma5_descr__dma5_descr__VAL REG_VAL_ENUM -#define R_IRQ_READ2__dma4_eop__dma4_eop__VAL REG_VAL_ENUM -#define R_IRQ_READ2__dma4_descr__dma4_descr__VAL REG_VAL_ENUM -#define R_IRQ_READ2__dma3_eop__dma3_eop__VAL REG_VAL_ENUM -#define R_IRQ_READ2__dma3_descr__dma3_descr__VAL REG_VAL_ENUM -#define R_IRQ_READ2__dma2_eop__dma2_eop__VAL REG_VAL_ENUM -#define R_IRQ_READ2__dma2_descr__dma2_descr__VAL REG_VAL_ENUM -#define R_IRQ_READ2__dma1_eop__dma1_eop__VAL REG_VAL_ENUM -#define R_IRQ_READ2__dma1_descr__dma1_descr__VAL REG_VAL_ENUM -#define R_IRQ_READ2__dma0_eop__dma0_eop__VAL REG_VAL_ENUM -#define R_IRQ_READ2__dma0_descr__dma0_descr__VAL REG_VAL_ENUM - -#define R_IRQ_READ2__dma8_sub3_descr__dma8_sub3_descr__active 1 -#define R_IRQ_READ2__dma8_sub3_descr__dma8_sub3_descr__inactive 0 -#define R_IRQ_READ2__dma8_sub2_descr__dma8_sub2_descr__active 1 -#define R_IRQ_READ2__dma8_sub2_descr__dma8_sub2_descr__inactive 0 -#define R_IRQ_READ2__dma8_sub1_descr__dma8_sub1_descr__active 1 -#define R_IRQ_READ2__dma8_sub1_descr__dma8_sub1_descr__inactive 0 -#define R_IRQ_READ2__dma8_sub0_descr__dma8_sub0_descr__active 1 -#define R_IRQ_READ2__dma8_sub0_descr__dma8_sub0_descr__inactive 0 -#define R_IRQ_READ2__dma9_eop__dma9_eop__active 1 -#define R_IRQ_READ2__dma9_eop__dma9_eop__inactive 0 -#define R_IRQ_READ2__dma9_descr__dma9_descr__active 1 -#define R_IRQ_READ2__dma9_descr__dma9_descr__inactive 0 -#define R_IRQ_READ2__dma8_eop__dma8_eop__active 1 -#define R_IRQ_READ2__dma8_eop__dma8_eop__inactive 0 -#define R_IRQ_READ2__dma8_descr__dma8_descr__active 1 -#define R_IRQ_READ2__dma8_descr__dma8_descr__inactive 0 -#define R_IRQ_READ2__dma7_eop__dma7_eop__active 1 -#define R_IRQ_READ2__dma7_eop__dma7_eop__inactive 0 -#define R_IRQ_READ2__dma7_descr__dma7_descr__active 1 -#define R_IRQ_READ2__dma7_descr__dma7_descr__inactive 0 -#define R_IRQ_READ2__dma6_eop__dma6_eop__active 1 -#define R_IRQ_READ2__dma6_eop__dma6_eop__inactive 0 -#define R_IRQ_READ2__dma6_descr__dma6_descr__active 1 -#define R_IRQ_READ2__dma6_descr__dma6_descr__inactive 0 -#define R_IRQ_READ2__dma5_eop__dma5_eop__active 1 -#define R_IRQ_READ2__dma5_eop__dma5_eop__inactive 0 -#define R_IRQ_READ2__dma5_descr__dma5_descr__active 1 -#define R_IRQ_READ2__dma5_descr__dma5_descr__inactive 0 -#define R_IRQ_READ2__dma4_eop__dma4_eop__active 1 -#define R_IRQ_READ2__dma4_eop__dma4_eop__inactive 0 -#define R_IRQ_READ2__dma4_descr__dma4_descr__active 1 -#define R_IRQ_READ2__dma4_descr__dma4_descr__inactive 0 -#define R_IRQ_READ2__dma3_eop__dma3_eop__active 1 -#define R_IRQ_READ2__dma3_eop__dma3_eop__inactive 0 -#define R_IRQ_READ2__dma3_descr__dma3_descr__active 1 -#define R_IRQ_READ2__dma3_descr__dma3_descr__inactive 0 -#define R_IRQ_READ2__dma2_eop__dma2_eop__active 1 -#define R_IRQ_READ2__dma2_eop__dma2_eop__inactive 0 -#define R_IRQ_READ2__dma2_descr__dma2_descr__active 1 -#define R_IRQ_READ2__dma2_descr__dma2_descr__inactive 0 -#define R_IRQ_READ2__dma1_eop__dma1_eop__active 1 -#define R_IRQ_READ2__dma1_eop__dma1_eop__inactive 0 -#define R_IRQ_READ2__dma1_descr__dma1_descr__active 1 -#define R_IRQ_READ2__dma1_descr__dma1_descr__inactive 0 -#define R_IRQ_READ2__dma0_eop__dma0_eop__active 1 -#define R_IRQ_READ2__dma0_eop__dma0_eop__inactive 0 -#define R_IRQ_READ2__dma0_descr__dma0_descr__active 1 -#define R_IRQ_READ2__dma0_descr__dma0_descr__inactive 0 - -#endif - -/* - * R_MMU_CAUSE - * - type: RO - * - addr: 0xb0000250 - * - group: MMU registers - */ - -#if USE_GROUP__MMU_registers - -#define R_MMU_CAUSE__ADDR (REG_TYPECAST_UDWORD 0xb0000250) -#define R_MMU_CAUSE__SVAL REG_SVAL_SHADOW -#define R_MMU_CAUSE__SVAL_I REG_SVAL_I_SHADOW -#define R_MMU_CAUSE__TYPECAST REG_TYPECAST_UDWORD -#define R_MMU_CAUSE__TYPE (REG_UDWORD) -#define R_MMU_CAUSE__GET REG_GET_RO -#define R_MMU_CAUSE__IGET REG_IGET_RO -#define R_MMU_CAUSE__SET REG_SET_RO -#define R_MMU_CAUSE__ISET REG_ISET_RO -#define R_MMU_CAUSE__SET_VAL REG_SET_VAL_RO -#define R_MMU_CAUSE__EQL REG_EQL_RO -#define R_MMU_CAUSE__IEQL REG_IEQL_RO -#define R_MMU_CAUSE__RD REG_RD_RO -#define R_MMU_CAUSE__IRD REG_IRD_RO -#define R_MMU_CAUSE__WR REG_WR_RO -#define R_MMU_CAUSE__IWR REG_IWR_RO - -#define R_MMU_CAUSE__READ(addr) \ - (*(addr)) - -#define R_MMU_CAUSE__vpn__vpn__MASK 0xffffe000U -#define R_MMU_CAUSE__miss_excp__miss_excp__MASK 0x00001000U -#define R_MMU_CAUSE__inv_excp__inv_excp__MASK 0x00000800U -#define R_MMU_CAUSE__acc_excp__acc_excp__MASK 0x00000400U -#define R_MMU_CAUSE__we_excp__we_excp__MASK 0x00000200U -#define R_MMU_CAUSE__wr_rd__wr_rd__MASK 0x00000100U -#define R_MMU_CAUSE__page_id__page_id__MASK 0x0000003fU - -#define R_MMU_CAUSE__vpn__MAX 0x7ffff -#define R_MMU_CAUSE__miss_excp__MAX 0x1 -#define R_MMU_CAUSE__inv_excp__MAX 0x1 -#define R_MMU_CAUSE__acc_excp__MAX 0x1 -#define R_MMU_CAUSE__we_excp__MAX 0x1 -#define R_MMU_CAUSE__wr_rd__MAX 0x1 -#define R_MMU_CAUSE__page_id__MAX 63 - -#define R_MMU_CAUSE__vpn__MIN 0 -#define R_MMU_CAUSE__miss_excp__MIN 0 -#define R_MMU_CAUSE__inv_excp__MIN 0 -#define R_MMU_CAUSE__acc_excp__MIN 0 -#define R_MMU_CAUSE__we_excp__MIN 0 -#define R_MMU_CAUSE__wr_rd__MIN 0 -#define R_MMU_CAUSE__page_id__MIN 0 - -#define R_MMU_CAUSE__vpn__BITNR 13 -#define R_MMU_CAUSE__miss_excp__BITNR 12 -#define R_MMU_CAUSE__inv_excp__BITNR 11 -#define R_MMU_CAUSE__acc_excp__BITNR 10 -#define R_MMU_CAUSE__we_excp__BITNR 9 -#define R_MMU_CAUSE__wr_rd__BITNR 8 -#define R_MMU_CAUSE__page_id__BITNR 0 - -#define R_MMU_CAUSE__vpn__vpn__VAL REG_VAL_VAL -#define R_MMU_CAUSE__miss_excp__miss_excp__VAL REG_VAL_ENUM -#define R_MMU_CAUSE__inv_excp__inv_excp__VAL REG_VAL_ENUM -#define R_MMU_CAUSE__acc_excp__acc_excp__VAL REG_VAL_ENUM -#define R_MMU_CAUSE__we_excp__we_excp__VAL REG_VAL_ENUM -#define R_MMU_CAUSE__wr_rd__wr_rd__VAL REG_VAL_ENUM -#define R_MMU_CAUSE__page_id__page_id__VAL REG_VAL_VAL - -#define R_MMU_CAUSE__miss_excp__miss_excp__no 0 -#define R_MMU_CAUSE__miss_excp__miss_excp__yes 1 -#define R_MMU_CAUSE__inv_excp__inv_excp__no 0 -#define R_MMU_CAUSE__inv_excp__inv_excp__yes 1 -#define R_MMU_CAUSE__acc_excp__acc_excp__no 0 -#define R_MMU_CAUSE__acc_excp__acc_excp__yes 1 -#define R_MMU_CAUSE__we_excp__we_excp__no 0 -#define R_MMU_CAUSE__we_excp__we_excp__yes 1 -#define R_MMU_CAUSE__wr_rd__wr_rd__read 0 -#define R_MMU_CAUSE__wr_rd__wr_rd__write 1 - -#endif - -/* - * R_MMU_CONFIG - * - type: WO - * - addr: 0xb0000240 - * - group: MMU registers - */ - -#if USE_GROUP__MMU_registers - -#define R_MMU_CONFIG__ADDR (REG_TYPECAST_UDWORD 0xb0000240) - -#ifndef REG_NO_SHADOW -#define R_MMU_CONFIG__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_MMU_CONFIG + 2)) -#define R_MMU_CONFIG__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_MMU_CONFIG + 2)) -#else /* REG_NO_SHADOW */ -#define R_MMU_CONFIG__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_MMU_CONFIG__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_MMU_CONFIG__STYPECAST REG_STYPECAST_UDWORD -#define R_MMU_CONFIG__SVAL REG_SVAL_SHADOW -#define R_MMU_CONFIG__SVAL_I REG_SVAL_I_SHADOW -#define R_MMU_CONFIG__TYPECAST REG_TYPECAST_UDWORD -#define R_MMU_CONFIG__TYPE (REG_UDWORD) -#define R_MMU_CONFIG__GET REG_GET_WO -#define R_MMU_CONFIG__IGET REG_IGET_WO -#define R_MMU_CONFIG__SET REG_SET_WO -#define R_MMU_CONFIG__ISET REG_ISET_WO -#define R_MMU_CONFIG__SET_VAL REG_SET_VAL_WO -#define R_MMU_CONFIG__EQL REG_EQL_WO -#define R_MMU_CONFIG__IEQL REG_IEQL_WO -#define R_MMU_CONFIG__RD REG_RD_WO -#define R_MMU_CONFIG__IRD REG_IRD_WO -#define R_MMU_CONFIG__WR REG_WR_WO -#define R_MMU_CONFIG__IWR REG_IWR_WO - -#define R_MMU_CONFIG__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_MMU_CONFIG__mmu_enable__mmu_enable__MASK 0x80000000U -#define R_MMU_CONFIG__inv_excp__inv_excp__MASK 0x00040000U -#define R_MMU_CONFIG__acc_excp__acc_excp__MASK 0x00020000U -#define R_MMU_CONFIG__we_excp__we_excp__MASK 0x00010000U -#define R_MMU_CONFIG__seg_f__seg_f__MASK 0x00008000U -#define R_MMU_CONFIG__seg_e__seg_e__MASK 0x00004000U -#define R_MMU_CONFIG__seg_d__seg_d__MASK 0x00002000U -#define R_MMU_CONFIG__seg_c__seg_c__MASK 0x00001000U -#define R_MMU_CONFIG__seg_b__seg_b__MASK 0x00000800U -#define R_MMU_CONFIG__seg_a__seg_a__MASK 0x00000400U -#define R_MMU_CONFIG__seg_9__seg_9__MASK 0x00000200U -#define R_MMU_CONFIG__seg_8__seg_8__MASK 0x00000100U -#define R_MMU_CONFIG__seg_7__seg_7__MASK 0x00000080U -#define R_MMU_CONFIG__seg_6__seg_6__MASK 0x00000040U -#define R_MMU_CONFIG__seg_5__seg_5__MASK 0x00000020U -#define R_MMU_CONFIG__seg_4__seg_4__MASK 0x00000010U -#define R_MMU_CONFIG__seg_3__seg_3__MASK 0x00000008U -#define R_MMU_CONFIG__seg_2__seg_2__MASK 0x00000004U -#define R_MMU_CONFIG__seg_1__seg_1__MASK 0x00000002U -#define R_MMU_CONFIG__seg_0__seg_0__MASK 0x00000001U - -#define R_MMU_CONFIG__mmu_enable__MAX 0x1 -#define R_MMU_CONFIG__inv_excp__MAX 0x1 -#define R_MMU_CONFIG__acc_excp__MAX 0x1 -#define R_MMU_CONFIG__we_excp__MAX 0x1 -#define R_MMU_CONFIG__seg_f__MAX 0x1 -#define R_MMU_CONFIG__seg_e__MAX 0x1 -#define R_MMU_CONFIG__seg_d__MAX 0x1 -#define R_MMU_CONFIG__seg_c__MAX 0x1 -#define R_MMU_CONFIG__seg_b__MAX 0x1 -#define R_MMU_CONFIG__seg_a__MAX 0x1 -#define R_MMU_CONFIG__seg_9__MAX 0x1 -#define R_MMU_CONFIG__seg_8__MAX 0x1 -#define R_MMU_CONFIG__seg_7__MAX 0x1 -#define R_MMU_CONFIG__seg_6__MAX 0x1 -#define R_MMU_CONFIG__seg_5__MAX 0x1 -#define R_MMU_CONFIG__seg_4__MAX 0x1 -#define R_MMU_CONFIG__seg_3__MAX 0x1 -#define R_MMU_CONFIG__seg_2__MAX 0x1 -#define R_MMU_CONFIG__seg_1__MAX 0x1 -#define R_MMU_CONFIG__seg_0__MAX 0x1 - -#define R_MMU_CONFIG__mmu_enable__MIN 0 -#define R_MMU_CONFIG__inv_excp__MIN 0 -#define R_MMU_CONFIG__acc_excp__MIN 0 -#define R_MMU_CONFIG__we_excp__MIN 0 -#define R_MMU_CONFIG__seg_f__MIN 0 -#define R_MMU_CONFIG__seg_e__MIN 0 -#define R_MMU_CONFIG__seg_d__MIN 0 -#define R_MMU_CONFIG__seg_c__MIN 0 -#define R_MMU_CONFIG__seg_b__MIN 0 -#define R_MMU_CONFIG__seg_a__MIN 0 -#define R_MMU_CONFIG__seg_9__MIN 0 -#define R_MMU_CONFIG__seg_8__MIN 0 -#define R_MMU_CONFIG__seg_7__MIN 0 -#define R_MMU_CONFIG__seg_6__MIN 0 -#define R_MMU_CONFIG__seg_5__MIN 0 -#define R_MMU_CONFIG__seg_4__MIN 0 -#define R_MMU_CONFIG__seg_3__MIN 0 -#define R_MMU_CONFIG__seg_2__MIN 0 -#define R_MMU_CONFIG__seg_1__MIN 0 -#define R_MMU_CONFIG__seg_0__MIN 0 - -#define R_MMU_CONFIG__mmu_enable__BITNR 31 -#define R_MMU_CONFIG__inv_excp__BITNR 18 -#define R_MMU_CONFIG__acc_excp__BITNR 17 -#define R_MMU_CONFIG__we_excp__BITNR 16 -#define R_MMU_CONFIG__seg_f__BITNR 15 -#define R_MMU_CONFIG__seg_e__BITNR 14 -#define R_MMU_CONFIG__seg_d__BITNR 13 -#define R_MMU_CONFIG__seg_c__BITNR 12 -#define R_MMU_CONFIG__seg_b__BITNR 11 -#define R_MMU_CONFIG__seg_a__BITNR 10 -#define R_MMU_CONFIG__seg_9__BITNR 9 -#define R_MMU_CONFIG__seg_8__BITNR 8 -#define R_MMU_CONFIG__seg_7__BITNR 7 -#define R_MMU_CONFIG__seg_6__BITNR 6 -#define R_MMU_CONFIG__seg_5__BITNR 5 -#define R_MMU_CONFIG__seg_4__BITNR 4 -#define R_MMU_CONFIG__seg_3__BITNR 3 -#define R_MMU_CONFIG__seg_2__BITNR 2 -#define R_MMU_CONFIG__seg_1__BITNR 1 -#define R_MMU_CONFIG__seg_0__BITNR 0 - -#define R_MMU_CONFIG__mmu_enable__mmu_enable__VAL REG_VAL_ENUM -#define R_MMU_CONFIG__inv_excp__inv_excp__VAL REG_VAL_ENUM -#define R_MMU_CONFIG__acc_excp__acc_excp__VAL REG_VAL_ENUM -#define R_MMU_CONFIG__we_excp__we_excp__VAL REG_VAL_ENUM -#define R_MMU_CONFIG__seg_f__seg_f__VAL REG_VAL_ENUM -#define R_MMU_CONFIG__seg_e__seg_e__VAL REG_VAL_ENUM -#define R_MMU_CONFIG__seg_d__seg_d__VAL REG_VAL_ENUM -#define R_MMU_CONFIG__seg_c__seg_c__VAL REG_VAL_ENUM -#define R_MMU_CONFIG__seg_b__seg_b__VAL REG_VAL_ENUM -#define R_MMU_CONFIG__seg_a__seg_a__VAL REG_VAL_ENUM -#define R_MMU_CONFIG__seg_9__seg_9__VAL REG_VAL_ENUM -#define R_MMU_CONFIG__seg_8__seg_8__VAL REG_VAL_ENUM -#define R_MMU_CONFIG__seg_7__seg_7__VAL REG_VAL_ENUM -#define R_MMU_CONFIG__seg_6__seg_6__VAL REG_VAL_ENUM -#define R_MMU_CONFIG__seg_5__seg_5__VAL REG_VAL_ENUM -#define R_MMU_CONFIG__seg_4__seg_4__VAL REG_VAL_ENUM -#define R_MMU_CONFIG__seg_3__seg_3__VAL REG_VAL_ENUM -#define R_MMU_CONFIG__seg_2__seg_2__VAL REG_VAL_ENUM -#define R_MMU_CONFIG__seg_1__seg_1__VAL REG_VAL_ENUM -#define R_MMU_CONFIG__seg_0__seg_0__VAL REG_VAL_ENUM - -#define R_MMU_CONFIG__mmu_enable__mmu_enable__disable 0 -#define R_MMU_CONFIG__mmu_enable__mmu_enable__enable 1 -#define R_MMU_CONFIG__inv_excp__inv_excp__disable 0 -#define R_MMU_CONFIG__inv_excp__inv_excp__enable 1 -#define R_MMU_CONFIG__acc_excp__acc_excp__disable 0 -#define R_MMU_CONFIG__acc_excp__acc_excp__enable 1 -#define R_MMU_CONFIG__we_excp__we_excp__disable 0 -#define R_MMU_CONFIG__we_excp__we_excp__enable 1 -#define R_MMU_CONFIG__seg_f__seg_f__page 0 -#define R_MMU_CONFIG__seg_f__seg_f__seg 1 -#define R_MMU_CONFIG__seg_e__seg_e__page 0 -#define R_MMU_CONFIG__seg_e__seg_e__seg 1 -#define R_MMU_CONFIG__seg_d__seg_d__page 0 -#define R_MMU_CONFIG__seg_d__seg_d__seg 1 -#define R_MMU_CONFIG__seg_c__seg_c__page 0 -#define R_MMU_CONFIG__seg_c__seg_c__seg 1 -#define R_MMU_CONFIG__seg_b__seg_b__page 0 -#define R_MMU_CONFIG__seg_b__seg_b__seg 1 -#define R_MMU_CONFIG__seg_a__seg_a__page 0 -#define R_MMU_CONFIG__seg_a__seg_a__seg 1 -#define R_MMU_CONFIG__seg_9__seg_9__page 0 -#define R_MMU_CONFIG__seg_9__seg_9__seg 1 -#define R_MMU_CONFIG__seg_8__seg_8__page 0 -#define R_MMU_CONFIG__seg_8__seg_8__seg 1 -#define R_MMU_CONFIG__seg_7__seg_7__page 0 -#define R_MMU_CONFIG__seg_7__seg_7__seg 1 -#define R_MMU_CONFIG__seg_6__seg_6__page 0 -#define R_MMU_CONFIG__seg_6__seg_6__seg 1 -#define R_MMU_CONFIG__seg_5__seg_5__page 0 -#define R_MMU_CONFIG__seg_5__seg_5__seg 1 -#define R_MMU_CONFIG__seg_4__seg_4__page 0 -#define R_MMU_CONFIG__seg_4__seg_4__seg 1 -#define R_MMU_CONFIG__seg_3__seg_3__page 0 -#define R_MMU_CONFIG__seg_3__seg_3__seg 1 -#define R_MMU_CONFIG__seg_2__seg_2__page 0 -#define R_MMU_CONFIG__seg_2__seg_2__seg 1 -#define R_MMU_CONFIG__seg_1__seg_1__page 0 -#define R_MMU_CONFIG__seg_1__seg_1__seg 1 -#define R_MMU_CONFIG__seg_0__seg_0__page 0 -#define R_MMU_CONFIG__seg_0__seg_0__seg 1 - -#endif - -/* - * R_MMU_CONTEXT - * - type: RW - * - addr: 0xb000024c - * - group: MMU registers - */ - -#if USE_GROUP__MMU_registers - -#define R_MMU_CONTEXT__ADDR (REG_TYPECAST_BYTE 0xb000024c) -#define R_MMU_CONTEXT__SVAL REG_SVAL_SHADOW -#define R_MMU_CONTEXT__SVAL_I REG_SVAL_I_SHADOW -#define R_MMU_CONTEXT__TYPECAST REG_TYPECAST_BYTE -#define R_MMU_CONTEXT__TYPE (REG_BYTE) -#define R_MMU_CONTEXT__GET REG_GET_RW -#define R_MMU_CONTEXT__IGET REG_IGET_RW -#define R_MMU_CONTEXT__SET REG_SET_RW -#define R_MMU_CONTEXT__ISET REG_ISET_RW -#define R_MMU_CONTEXT__SET_VAL REG_SET_VAL_RW -#define R_MMU_CONTEXT__EQL REG_EQL_RW -#define R_MMU_CONTEXT__IEQL REG_IEQL_RW -#define R_MMU_CONTEXT__RD REG_RD_RW -#define R_MMU_CONTEXT__IRD REG_IRD_RW -#define R_MMU_CONTEXT__WR REG_WR_RW -#define R_MMU_CONTEXT__IWR REG_IWR_RW - -#define R_MMU_CONTEXT__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_MMU_CONTEXT__READ(addr) \ - (*(addr)) - -#define R_MMU_CONTEXT__page_id__page_id__MASK 0x0000003fU - -#define R_MMU_CONTEXT__page_id__MAX 63 - -#define R_MMU_CONTEXT__page_id__MIN 0 - -#define R_MMU_CONTEXT__page_id__BITNR 0 - -#define R_MMU_CONTEXT__page_id__page_id__VAL REG_VAL_VAL - - -#endif - -/* - * R_MMU_CTRL - * - type: WO - * - addr: 0xb0000242 - * - group: MMU registers - */ - -#if USE_GROUP__MMU_registers - -#define R_MMU_CTRL__ADDR (REG_TYPECAST_BYTE 0xb0000242) - -#ifndef REG_NO_SHADOW -#define R_MMU_CTRL__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_MMU_CONFIG + 0)) -#define R_MMU_CTRL__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_MMU_CONFIG + 0)) -#else /* REG_NO_SHADOW */ -#define R_MMU_CTRL__SADDR (REG_STYPECAST_BYTE (®_shadow__hwregs)) -#define R_MMU_CTRL__IADDR (REG_STYPECAST_BYTE (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_MMU_CTRL__STYPECAST REG_STYPECAST_BYTE -#define R_MMU_CTRL__SVAL REG_SVAL_SHADOW -#define R_MMU_CTRL__SVAL_I REG_SVAL_I_SHADOW -#define R_MMU_CTRL__TYPECAST REG_TYPECAST_BYTE -#define R_MMU_CTRL__TYPE (REG_BYTE) -#define R_MMU_CTRL__GET REG_GET_WO -#define R_MMU_CTRL__IGET REG_IGET_WO -#define R_MMU_CTRL__SET REG_SET_WO -#define R_MMU_CTRL__ISET REG_ISET_WO -#define R_MMU_CTRL__SET_VAL REG_SET_VAL_WO -#define R_MMU_CTRL__EQL REG_EQL_WO -#define R_MMU_CTRL__IEQL REG_IEQL_WO -#define R_MMU_CTRL__RD REG_RD_WO -#define R_MMU_CTRL__IRD REG_IRD_WO -#define R_MMU_CTRL__WR REG_WR_WO -#define R_MMU_CTRL__IWR REG_IWR_WO - -#define R_MMU_CTRL__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_MMU_CTRL__inv_excp__inv_excp__MASK 0x00000004U -#define R_MMU_CTRL__acc_excp__acc_excp__MASK 0x00000002U -#define R_MMU_CTRL__we_excp__we_excp__MASK 0x00000001U - -#define R_MMU_CTRL__inv_excp__MAX 0x1 -#define R_MMU_CTRL__acc_excp__MAX 0x1 -#define R_MMU_CTRL__we_excp__MAX 0x1 - -#define R_MMU_CTRL__inv_excp__MIN 0 -#define R_MMU_CTRL__acc_excp__MIN 0 -#define R_MMU_CTRL__we_excp__MIN 0 - -#define R_MMU_CTRL__inv_excp__BITNR 2 -#define R_MMU_CTRL__acc_excp__BITNR 1 -#define R_MMU_CTRL__we_excp__BITNR 0 - -#define R_MMU_CTRL__inv_excp__inv_excp__VAL REG_VAL_ENUM -#define R_MMU_CTRL__acc_excp__acc_excp__VAL REG_VAL_ENUM -#define R_MMU_CTRL__we_excp__we_excp__VAL REG_VAL_ENUM - -#define R_MMU_CTRL__inv_excp__inv_excp__disable 0 -#define R_MMU_CTRL__inv_excp__inv_excp__enable 1 -#define R_MMU_CTRL__acc_excp__acc_excp__disable 0 -#define R_MMU_CTRL__acc_excp__acc_excp__enable 1 -#define R_MMU_CTRL__we_excp__we_excp__disable 0 -#define R_MMU_CTRL__we_excp__we_excp__enable 1 - -#endif - -/* - * R_MMU_ENABLE - * - type: WO - * - addr: 0xb0000243 - * - group: MMU registers - */ - -#if USE_GROUP__MMU_registers - -#define R_MMU_ENABLE__ADDR (REG_TYPECAST_BYTE 0xb0000243) - -#ifndef REG_NO_SHADOW -#define R_MMU_ENABLE__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_MMU_CONFIG + 1)) -#define R_MMU_ENABLE__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_MMU_CONFIG + 1)) -#else /* REG_NO_SHADOW */ -#define R_MMU_ENABLE__SADDR (REG_STYPECAST_BYTE (®_shadow__hwregs)) -#define R_MMU_ENABLE__IADDR (REG_STYPECAST_BYTE (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_MMU_ENABLE__STYPECAST REG_STYPECAST_BYTE -#define R_MMU_ENABLE__SVAL REG_SVAL_SHADOW -#define R_MMU_ENABLE__SVAL_I REG_SVAL_I_SHADOW -#define R_MMU_ENABLE__TYPECAST REG_TYPECAST_BYTE -#define R_MMU_ENABLE__TYPE (REG_BYTE) -#define R_MMU_ENABLE__GET REG_GET_WO -#define R_MMU_ENABLE__IGET REG_IGET_WO -#define R_MMU_ENABLE__SET REG_SET_WO -#define R_MMU_ENABLE__ISET REG_ISET_WO -#define R_MMU_ENABLE__SET_VAL REG_SET_VAL_WO -#define R_MMU_ENABLE__EQL REG_EQL_WO -#define R_MMU_ENABLE__IEQL REG_IEQL_WO -#define R_MMU_ENABLE__RD REG_RD_WO -#define R_MMU_ENABLE__IRD REG_IRD_WO -#define R_MMU_ENABLE__WR REG_WR_WO -#define R_MMU_ENABLE__IWR REG_IWR_WO - -#define R_MMU_ENABLE__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_MMU_ENABLE__mmu_enable__mmu_enable__MASK 0x00000080U - -#define R_MMU_ENABLE__mmu_enable__MAX 0x1 - -#define R_MMU_ENABLE__mmu_enable__MIN 0 - -#define R_MMU_ENABLE__mmu_enable__BITNR 7 - -#define R_MMU_ENABLE__mmu_enable__mmu_enable__VAL REG_VAL_ENUM - -#define R_MMU_ENABLE__mmu_enable__mmu_enable__disable 0 -#define R_MMU_ENABLE__mmu_enable__mmu_enable__enable 1 - -#endif - -/* - * R_MMU_KBASE_HI - * - type: WO - * - addr: 0xb0000248 - * - group: MMU registers - */ - -#if USE_GROUP__MMU_registers - -#define R_MMU_KBASE_HI__ADDR (REG_TYPECAST_UDWORD 0xb0000248) - -#ifndef REG_NO_SHADOW -#define R_MMU_KBASE_HI__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_MMU_KBASE_HI + 2)) -#define R_MMU_KBASE_HI__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_MMU_KBASE_HI + 2)) -#else /* REG_NO_SHADOW */ -#define R_MMU_KBASE_HI__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_MMU_KBASE_HI__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_MMU_KBASE_HI__STYPECAST REG_STYPECAST_UDWORD -#define R_MMU_KBASE_HI__SVAL REG_SVAL_SHADOW -#define R_MMU_KBASE_HI__SVAL_I REG_SVAL_I_SHADOW -#define R_MMU_KBASE_HI__TYPECAST REG_TYPECAST_UDWORD -#define R_MMU_KBASE_HI__TYPE (REG_UDWORD) -#define R_MMU_KBASE_HI__GET REG_GET_WO -#define R_MMU_KBASE_HI__IGET REG_IGET_WO -#define R_MMU_KBASE_HI__SET REG_SET_WO -#define R_MMU_KBASE_HI__ISET REG_ISET_WO -#define R_MMU_KBASE_HI__SET_VAL REG_SET_VAL_WO -#define R_MMU_KBASE_HI__EQL REG_EQL_WO -#define R_MMU_KBASE_HI__IEQL REG_IEQL_WO -#define R_MMU_KBASE_HI__RD REG_RD_WO -#define R_MMU_KBASE_HI__IRD REG_IRD_WO -#define R_MMU_KBASE_HI__WR REG_WR_WO -#define R_MMU_KBASE_HI__IWR REG_IWR_WO - -#define R_MMU_KBASE_HI__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_MMU_KBASE_HI__base_f__base_f__MASK 0xf0000000U -#define R_MMU_KBASE_HI__base_e__base_e__MASK 0x0f000000U -#define R_MMU_KBASE_HI__base_d__base_d__MASK 0x00f00000U -#define R_MMU_KBASE_HI__base_c__base_c__MASK 0x000f0000U -#define R_MMU_KBASE_HI__base_b__base_b__MASK 0x0000f000U -#define R_MMU_KBASE_HI__base_a__base_a__MASK 0x00000f00U -#define R_MMU_KBASE_HI__base_9__base_9__MASK 0x000000f0U -#define R_MMU_KBASE_HI__base_8__base_8__MASK 0x0000000fU - -#define R_MMU_KBASE_HI__base_f__MAX 15 -#define R_MMU_KBASE_HI__base_e__MAX 15 -#define R_MMU_KBASE_HI__base_d__MAX 15 -#define R_MMU_KBASE_HI__base_c__MAX 15 -#define R_MMU_KBASE_HI__base_b__MAX 15 -#define R_MMU_KBASE_HI__base_a__MAX 15 -#define R_MMU_KBASE_HI__base_9__MAX 15 -#define R_MMU_KBASE_HI__base_8__MAX 15 - -#define R_MMU_KBASE_HI__base_f__MIN 0 -#define R_MMU_KBASE_HI__base_e__MIN 0 -#define R_MMU_KBASE_HI__base_d__MIN 0 -#define R_MMU_KBASE_HI__base_c__MIN 0 -#define R_MMU_KBASE_HI__base_b__MIN 0 -#define R_MMU_KBASE_HI__base_a__MIN 0 -#define R_MMU_KBASE_HI__base_9__MIN 0 -#define R_MMU_KBASE_HI__base_8__MIN 0 - -#define R_MMU_KBASE_HI__base_f__BITNR 28 -#define R_MMU_KBASE_HI__base_e__BITNR 24 -#define R_MMU_KBASE_HI__base_d__BITNR 20 -#define R_MMU_KBASE_HI__base_c__BITNR 16 -#define R_MMU_KBASE_HI__base_b__BITNR 12 -#define R_MMU_KBASE_HI__base_a__BITNR 8 -#define R_MMU_KBASE_HI__base_9__BITNR 4 -#define R_MMU_KBASE_HI__base_8__BITNR 0 - -#define R_MMU_KBASE_HI__base_f__base_f__VAL REG_VAL_VAL -#define R_MMU_KBASE_HI__base_e__base_e__VAL REG_VAL_VAL -#define R_MMU_KBASE_HI__base_d__base_d__VAL REG_VAL_VAL -#define R_MMU_KBASE_HI__base_c__base_c__VAL REG_VAL_VAL -#define R_MMU_KBASE_HI__base_b__base_b__VAL REG_VAL_VAL -#define R_MMU_KBASE_HI__base_a__base_a__VAL REG_VAL_VAL -#define R_MMU_KBASE_HI__base_9__base_9__VAL REG_VAL_VAL -#define R_MMU_KBASE_HI__base_8__base_8__VAL REG_VAL_VAL - - -#endif - -/* - * R_MMU_KBASE_LO - * - type: WO - * - addr: 0xb0000244 - * - group: MMU registers - */ - -#if USE_GROUP__MMU_registers - -#define R_MMU_KBASE_LO__ADDR (REG_TYPECAST_UDWORD 0xb0000244) - -#ifndef REG_NO_SHADOW -#define R_MMU_KBASE_LO__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_MMU_KBASE_LO + 2)) -#define R_MMU_KBASE_LO__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_MMU_KBASE_LO + 2)) -#else /* REG_NO_SHADOW */ -#define R_MMU_KBASE_LO__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_MMU_KBASE_LO__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_MMU_KBASE_LO__STYPECAST REG_STYPECAST_UDWORD -#define R_MMU_KBASE_LO__SVAL REG_SVAL_SHADOW -#define R_MMU_KBASE_LO__SVAL_I REG_SVAL_I_SHADOW -#define R_MMU_KBASE_LO__TYPECAST REG_TYPECAST_UDWORD -#define R_MMU_KBASE_LO__TYPE (REG_UDWORD) -#define R_MMU_KBASE_LO__GET REG_GET_WO -#define R_MMU_KBASE_LO__IGET REG_IGET_WO -#define R_MMU_KBASE_LO__SET REG_SET_WO -#define R_MMU_KBASE_LO__ISET REG_ISET_WO -#define R_MMU_KBASE_LO__SET_VAL REG_SET_VAL_WO -#define R_MMU_KBASE_LO__EQL REG_EQL_WO -#define R_MMU_KBASE_LO__IEQL REG_IEQL_WO -#define R_MMU_KBASE_LO__RD REG_RD_WO -#define R_MMU_KBASE_LO__IRD REG_IRD_WO -#define R_MMU_KBASE_LO__WR REG_WR_WO -#define R_MMU_KBASE_LO__IWR REG_IWR_WO - -#define R_MMU_KBASE_LO__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_MMU_KBASE_LO__base_7__base_7__MASK 0xf0000000U -#define R_MMU_KBASE_LO__base_6__base_6__MASK 0x0f000000U -#define R_MMU_KBASE_LO__base_5__base_5__MASK 0x00f00000U -#define R_MMU_KBASE_LO__base_4__base_4__MASK 0x000f0000U -#define R_MMU_KBASE_LO__base_3__base_3__MASK 0x0000f000U -#define R_MMU_KBASE_LO__base_2__base_2__MASK 0x00000f00U -#define R_MMU_KBASE_LO__base_1__base_1__MASK 0x000000f0U -#define R_MMU_KBASE_LO__base_0__base_0__MASK 0x0000000fU - -#define R_MMU_KBASE_LO__base_7__MAX 15 -#define R_MMU_KBASE_LO__base_6__MAX 15 -#define R_MMU_KBASE_LO__base_5__MAX 15 -#define R_MMU_KBASE_LO__base_4__MAX 15 -#define R_MMU_KBASE_LO__base_3__MAX 15 -#define R_MMU_KBASE_LO__base_2__MAX 15 -#define R_MMU_KBASE_LO__base_1__MAX 15 -#define R_MMU_KBASE_LO__base_0__MAX 15 - -#define R_MMU_KBASE_LO__base_7__MIN 0 -#define R_MMU_KBASE_LO__base_6__MIN 0 -#define R_MMU_KBASE_LO__base_5__MIN 0 -#define R_MMU_KBASE_LO__base_4__MIN 0 -#define R_MMU_KBASE_LO__base_3__MIN 0 -#define R_MMU_KBASE_LO__base_2__MIN 0 -#define R_MMU_KBASE_LO__base_1__MIN 0 -#define R_MMU_KBASE_LO__base_0__MIN 0 - -#define R_MMU_KBASE_LO__base_7__BITNR 28 -#define R_MMU_KBASE_LO__base_6__BITNR 24 -#define R_MMU_KBASE_LO__base_5__BITNR 20 -#define R_MMU_KBASE_LO__base_4__BITNR 16 -#define R_MMU_KBASE_LO__base_3__BITNR 12 -#define R_MMU_KBASE_LO__base_2__BITNR 8 -#define R_MMU_KBASE_LO__base_1__BITNR 4 -#define R_MMU_KBASE_LO__base_0__BITNR 0 - -#define R_MMU_KBASE_LO__base_7__base_7__VAL REG_VAL_VAL -#define R_MMU_KBASE_LO__base_6__base_6__VAL REG_VAL_VAL -#define R_MMU_KBASE_LO__base_5__base_5__VAL REG_VAL_VAL -#define R_MMU_KBASE_LO__base_4__base_4__VAL REG_VAL_VAL -#define R_MMU_KBASE_LO__base_3__base_3__VAL REG_VAL_VAL -#define R_MMU_KBASE_LO__base_2__base_2__VAL REG_VAL_VAL -#define R_MMU_KBASE_LO__base_1__base_1__VAL REG_VAL_VAL -#define R_MMU_KBASE_LO__base_0__base_0__VAL REG_VAL_VAL - - -#endif - -/* - * R_MMU_KSEG - * - type: WO - * - addr: 0xb0000240 - * - group: MMU registers - */ - -#if USE_GROUP__MMU_registers - -#define R_MMU_KSEG__ADDR (REG_TYPECAST_UWORD 0xb0000240) - -#ifndef REG_NO_SHADOW -#define R_MMU_KSEG__SADDR (REG_STYPECAST_UWORD (reg_shadow__hwregs.R_MMU_CONFIG + 2)) -#define R_MMU_KSEG__IADDR (REG_STYPECAST_UWORD (reg_initiated__hwregs.R_MMU_CONFIG + 2)) -#else /* REG_NO_SHADOW */ -#define R_MMU_KSEG__SADDR (REG_STYPECAST_UWORD (®_shadow__hwregs)) -#define R_MMU_KSEG__IADDR (REG_STYPECAST_UWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_MMU_KSEG__STYPECAST REG_STYPECAST_UWORD -#define R_MMU_KSEG__SVAL REG_SVAL_SHADOW -#define R_MMU_KSEG__SVAL_I REG_SVAL_I_SHADOW -#define R_MMU_KSEG__TYPECAST REG_TYPECAST_UWORD -#define R_MMU_KSEG__TYPE (REG_UWORD) -#define R_MMU_KSEG__GET REG_GET_WO -#define R_MMU_KSEG__IGET REG_IGET_WO -#define R_MMU_KSEG__SET REG_SET_WO -#define R_MMU_KSEG__ISET REG_ISET_WO -#define R_MMU_KSEG__SET_VAL REG_SET_VAL_WO -#define R_MMU_KSEG__EQL REG_EQL_WO -#define R_MMU_KSEG__IEQL REG_IEQL_WO -#define R_MMU_KSEG__RD REG_RD_WO -#define R_MMU_KSEG__IRD REG_IRD_WO -#define R_MMU_KSEG__WR REG_WR_WO -#define R_MMU_KSEG__IWR REG_IWR_WO - -#define R_MMU_KSEG__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_MMU_KSEG__seg_f__seg_f__MASK 0x00008000U -#define R_MMU_KSEG__seg_e__seg_e__MASK 0x00004000U -#define R_MMU_KSEG__seg_d__seg_d__MASK 0x00002000U -#define R_MMU_KSEG__seg_c__seg_c__MASK 0x00001000U -#define R_MMU_KSEG__seg_b__seg_b__MASK 0x00000800U -#define R_MMU_KSEG__seg_a__seg_a__MASK 0x00000400U -#define R_MMU_KSEG__seg_9__seg_9__MASK 0x00000200U -#define R_MMU_KSEG__seg_8__seg_8__MASK 0x00000100U -#define R_MMU_KSEG__seg_7__seg_7__MASK 0x00000080U -#define R_MMU_KSEG__seg_6__seg_6__MASK 0x00000040U -#define R_MMU_KSEG__seg_5__seg_5__MASK 0x00000020U -#define R_MMU_KSEG__seg_4__seg_4__MASK 0x00000010U -#define R_MMU_KSEG__seg_3__seg_3__MASK 0x00000008U -#define R_MMU_KSEG__seg_2__seg_2__MASK 0x00000004U -#define R_MMU_KSEG__seg_1__seg_1__MASK 0x00000002U -#define R_MMU_KSEG__seg_0__seg_0__MASK 0x00000001U - -#define R_MMU_KSEG__seg_f__MAX 0x1 -#define R_MMU_KSEG__seg_e__MAX 0x1 -#define R_MMU_KSEG__seg_d__MAX 0x1 -#define R_MMU_KSEG__seg_c__MAX 0x1 -#define R_MMU_KSEG__seg_b__MAX 0x1 -#define R_MMU_KSEG__seg_a__MAX 0x1 -#define R_MMU_KSEG__seg_9__MAX 0x1 -#define R_MMU_KSEG__seg_8__MAX 0x1 -#define R_MMU_KSEG__seg_7__MAX 0x1 -#define R_MMU_KSEG__seg_6__MAX 0x1 -#define R_MMU_KSEG__seg_5__MAX 0x1 -#define R_MMU_KSEG__seg_4__MAX 0x1 -#define R_MMU_KSEG__seg_3__MAX 0x1 -#define R_MMU_KSEG__seg_2__MAX 0x1 -#define R_MMU_KSEG__seg_1__MAX 0x1 -#define R_MMU_KSEG__seg_0__MAX 0x1 - -#define R_MMU_KSEG__seg_f__MIN 0 -#define R_MMU_KSEG__seg_e__MIN 0 -#define R_MMU_KSEG__seg_d__MIN 0 -#define R_MMU_KSEG__seg_c__MIN 0 -#define R_MMU_KSEG__seg_b__MIN 0 -#define R_MMU_KSEG__seg_a__MIN 0 -#define R_MMU_KSEG__seg_9__MIN 0 -#define R_MMU_KSEG__seg_8__MIN 0 -#define R_MMU_KSEG__seg_7__MIN 0 -#define R_MMU_KSEG__seg_6__MIN 0 -#define R_MMU_KSEG__seg_5__MIN 0 -#define R_MMU_KSEG__seg_4__MIN 0 -#define R_MMU_KSEG__seg_3__MIN 0 -#define R_MMU_KSEG__seg_2__MIN 0 -#define R_MMU_KSEG__seg_1__MIN 0 -#define R_MMU_KSEG__seg_0__MIN 0 - -#define R_MMU_KSEG__seg_f__BITNR 15 -#define R_MMU_KSEG__seg_e__BITNR 14 -#define R_MMU_KSEG__seg_d__BITNR 13 -#define R_MMU_KSEG__seg_c__BITNR 12 -#define R_MMU_KSEG__seg_b__BITNR 11 -#define R_MMU_KSEG__seg_a__BITNR 10 -#define R_MMU_KSEG__seg_9__BITNR 9 -#define R_MMU_KSEG__seg_8__BITNR 8 -#define R_MMU_KSEG__seg_7__BITNR 7 -#define R_MMU_KSEG__seg_6__BITNR 6 -#define R_MMU_KSEG__seg_5__BITNR 5 -#define R_MMU_KSEG__seg_4__BITNR 4 -#define R_MMU_KSEG__seg_3__BITNR 3 -#define R_MMU_KSEG__seg_2__BITNR 2 -#define R_MMU_KSEG__seg_1__BITNR 1 -#define R_MMU_KSEG__seg_0__BITNR 0 - -#define R_MMU_KSEG__seg_f__seg_f__VAL REG_VAL_ENUM -#define R_MMU_KSEG__seg_e__seg_e__VAL REG_VAL_ENUM -#define R_MMU_KSEG__seg_d__seg_d__VAL REG_VAL_ENUM -#define R_MMU_KSEG__seg_c__seg_c__VAL REG_VAL_ENUM -#define R_MMU_KSEG__seg_b__seg_b__VAL REG_VAL_ENUM -#define R_MMU_KSEG__seg_a__seg_a__VAL REG_VAL_ENUM -#define R_MMU_KSEG__seg_9__seg_9__VAL REG_VAL_ENUM -#define R_MMU_KSEG__seg_8__seg_8__VAL REG_VAL_ENUM -#define R_MMU_KSEG__seg_7__seg_7__VAL REG_VAL_ENUM -#define R_MMU_KSEG__seg_6__seg_6__VAL REG_VAL_ENUM -#define R_MMU_KSEG__seg_5__seg_5__VAL REG_VAL_ENUM -#define R_MMU_KSEG__seg_4__seg_4__VAL REG_VAL_ENUM -#define R_MMU_KSEG__seg_3__seg_3__VAL REG_VAL_ENUM -#define R_MMU_KSEG__seg_2__seg_2__VAL REG_VAL_ENUM -#define R_MMU_KSEG__seg_1__seg_1__VAL REG_VAL_ENUM -#define R_MMU_KSEG__seg_0__seg_0__VAL REG_VAL_ENUM - -#define R_MMU_KSEG__seg_f__seg_f__page 0 -#define R_MMU_KSEG__seg_f__seg_f__seg 1 -#define R_MMU_KSEG__seg_e__seg_e__page 0 -#define R_MMU_KSEG__seg_e__seg_e__seg 1 -#define R_MMU_KSEG__seg_d__seg_d__page 0 -#define R_MMU_KSEG__seg_d__seg_d__seg 1 -#define R_MMU_KSEG__seg_c__seg_c__page 0 -#define R_MMU_KSEG__seg_c__seg_c__seg 1 -#define R_MMU_KSEG__seg_b__seg_b__page 0 -#define R_MMU_KSEG__seg_b__seg_b__seg 1 -#define R_MMU_KSEG__seg_a__seg_a__page 0 -#define R_MMU_KSEG__seg_a__seg_a__seg 1 -#define R_MMU_KSEG__seg_9__seg_9__page 0 -#define R_MMU_KSEG__seg_9__seg_9__seg 1 -#define R_MMU_KSEG__seg_8__seg_8__page 0 -#define R_MMU_KSEG__seg_8__seg_8__seg 1 -#define R_MMU_KSEG__seg_7__seg_7__page 0 -#define R_MMU_KSEG__seg_7__seg_7__seg 1 -#define R_MMU_KSEG__seg_6__seg_6__page 0 -#define R_MMU_KSEG__seg_6__seg_6__seg 1 -#define R_MMU_KSEG__seg_5__seg_5__page 0 -#define R_MMU_KSEG__seg_5__seg_5__seg 1 -#define R_MMU_KSEG__seg_4__seg_4__page 0 -#define R_MMU_KSEG__seg_4__seg_4__seg 1 -#define R_MMU_KSEG__seg_3__seg_3__page 0 -#define R_MMU_KSEG__seg_3__seg_3__seg 1 -#define R_MMU_KSEG__seg_2__seg_2__page 0 -#define R_MMU_KSEG__seg_2__seg_2__seg 1 -#define R_MMU_KSEG__seg_1__seg_1__page 0 -#define R_MMU_KSEG__seg_1__seg_1__seg 1 -#define R_MMU_KSEG__seg_0__seg_0__page 0 -#define R_MMU_KSEG__seg_0__seg_0__seg 1 - -#endif - -/* - * R_NETWORK_GA_0 - * - type: WO - * - addr: 0xb000008c - * - group: Network interface registers - */ - -#if USE_GROUP__Network_interface_registers - -#define R_NETWORK_GA_0__ADDR (REG_TYPECAST_UDWORD 0xb000008c) - -#ifndef REG_NO_SHADOW -#define R_NETWORK_GA_0__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_NETWORK_GA_0 + 0)) -#define R_NETWORK_GA_0__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_NETWORK_GA_0 + 0)) -#else /* REG_NO_SHADOW */ -#define R_NETWORK_GA_0__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_NETWORK_GA_0__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_NETWORK_GA_0__STYPECAST REG_STYPECAST_UDWORD -#define R_NETWORK_GA_0__SVAL REG_SVAL_SHADOW -#define R_NETWORK_GA_0__SVAL_I REG_SVAL_I_SHADOW -#define R_NETWORK_GA_0__TYPECAST REG_TYPECAST_UDWORD -#define R_NETWORK_GA_0__TYPE (REG_UDWORD) -#define R_NETWORK_GA_0__GET REG_GET_WO -#define R_NETWORK_GA_0__IGET REG_IGET_WO -#define R_NETWORK_GA_0__SET REG_SET_WO -#define R_NETWORK_GA_0__ISET REG_ISET_WO -#define R_NETWORK_GA_0__SET_VAL REG_SET_VAL_WO -#define R_NETWORK_GA_0__EQL REG_EQL_WO -#define R_NETWORK_GA_0__IEQL REG_IEQL_WO -#define R_NETWORK_GA_0__RD REG_RD_WO -#define R_NETWORK_GA_0__IRD REG_IRD_WO -#define R_NETWORK_GA_0__WR REG_WR_WO -#define R_NETWORK_GA_0__IWR REG_IWR_WO - -#define R_NETWORK_GA_0__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_NETWORK_GA_0__ga_low__ga_low__MASK 0xffffffffU - -#define R_NETWORK_GA_0__ga_low__MAX 0xffffffff - -#define R_NETWORK_GA_0__ga_low__MIN 0 - -#define R_NETWORK_GA_0__ga_low__BITNR 0 - -#define R_NETWORK_GA_0__ga_low__ga_low__VAL REG_VAL_VAL - - -#endif - -/* - * R_NETWORK_GA_1 - * - type: WO - * - addr: 0xb0000090 - * - group: Network interface registers - */ - -#if USE_GROUP__Network_interface_registers - -#define R_NETWORK_GA_1__ADDR (REG_TYPECAST_UDWORD 0xb0000090) - -#ifndef REG_NO_SHADOW -#define R_NETWORK_GA_1__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_NETWORK_GA_1 + 0)) -#define R_NETWORK_GA_1__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_NETWORK_GA_1 + 0)) -#else /* REG_NO_SHADOW */ -#define R_NETWORK_GA_1__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_NETWORK_GA_1__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_NETWORK_GA_1__STYPECAST REG_STYPECAST_UDWORD -#define R_NETWORK_GA_1__SVAL REG_SVAL_SHADOW -#define R_NETWORK_GA_1__SVAL_I REG_SVAL_I_SHADOW -#define R_NETWORK_GA_1__TYPECAST REG_TYPECAST_UDWORD -#define R_NETWORK_GA_1__TYPE (REG_UDWORD) -#define R_NETWORK_GA_1__GET REG_GET_WO -#define R_NETWORK_GA_1__IGET REG_IGET_WO -#define R_NETWORK_GA_1__SET REG_SET_WO -#define R_NETWORK_GA_1__ISET REG_ISET_WO -#define R_NETWORK_GA_1__SET_VAL REG_SET_VAL_WO -#define R_NETWORK_GA_1__EQL REG_EQL_WO -#define R_NETWORK_GA_1__IEQL REG_IEQL_WO -#define R_NETWORK_GA_1__RD REG_RD_WO -#define R_NETWORK_GA_1__IRD REG_IRD_WO -#define R_NETWORK_GA_1__WR REG_WR_WO -#define R_NETWORK_GA_1__IWR REG_IWR_WO - -#define R_NETWORK_GA_1__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_NETWORK_GA_1__ga_high__ga_high__MASK 0xffffffffU - -#define R_NETWORK_GA_1__ga_high__MAX 0xffffffff - -#define R_NETWORK_GA_1__ga_high__MIN 0 - -#define R_NETWORK_GA_1__ga_high__BITNR 0 - -#define R_NETWORK_GA_1__ga_high__ga_high__VAL REG_VAL_VAL - - -#endif - -/* - * R_NETWORK_GEN_CONFIG - * - type: WO - * - addr: 0xb0000098 - * - group: Network interface registers - */ - -#if USE_GROUP__Network_interface_registers - -#define R_NETWORK_GEN_CONFIG__ADDR (REG_TYPECAST_UDWORD 0xb0000098) - -#ifndef REG_NO_SHADOW -#define R_NETWORK_GEN_CONFIG__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_NETWORK_GEN_CONFIG + 0)) -#define R_NETWORK_GEN_CONFIG__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_NETWORK_GEN_CONFIG + 0)) -#else /* REG_NO_SHADOW */ -#define R_NETWORK_GEN_CONFIG__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_NETWORK_GEN_CONFIG__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_NETWORK_GEN_CONFIG__STYPECAST REG_STYPECAST_UDWORD -#define R_NETWORK_GEN_CONFIG__SVAL REG_SVAL_SHADOW -#define R_NETWORK_GEN_CONFIG__SVAL_I REG_SVAL_I_SHADOW -#define R_NETWORK_GEN_CONFIG__TYPECAST REG_TYPECAST_UDWORD -#define R_NETWORK_GEN_CONFIG__TYPE (REG_UDWORD) -#define R_NETWORK_GEN_CONFIG__GET REG_GET_WO -#define R_NETWORK_GEN_CONFIG__IGET REG_IGET_WO -#define R_NETWORK_GEN_CONFIG__SET REG_SET_WO -#define R_NETWORK_GEN_CONFIG__ISET REG_ISET_WO -#define R_NETWORK_GEN_CONFIG__SET_VAL REG_SET_VAL_WO -#define R_NETWORK_GEN_CONFIG__EQL REG_EQL_WO -#define R_NETWORK_GEN_CONFIG__IEQL REG_IEQL_WO -#define R_NETWORK_GEN_CONFIG__RD REG_RD_WO -#define R_NETWORK_GEN_CONFIG__IRD REG_IRD_WO -#define R_NETWORK_GEN_CONFIG__WR REG_WR_WO -#define R_NETWORK_GEN_CONFIG__IWR REG_IWR_WO - -#define R_NETWORK_GEN_CONFIG__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_NETWORK_GEN_CONFIG__loopback__loopback__MASK 0x00000020U -#define R_NETWORK_GEN_CONFIG__frame__frame__MASK 0x00000010U -#define R_NETWORK_GEN_CONFIG__vg__vg__MASK 0x00000008U -#define R_NETWORK_GEN_CONFIG__phy__phy__MASK 0x00000006U -#define R_NETWORK_GEN_CONFIG__enable__enable__MASK 0x00000001U - -#define R_NETWORK_GEN_CONFIG__loopback__MAX 0x1 -#define R_NETWORK_GEN_CONFIG__frame__MAX 0x1 -#define R_NETWORK_GEN_CONFIG__vg__MAX 0x1 -#define R_NETWORK_GEN_CONFIG__phy__MAX 0x3 -#define R_NETWORK_GEN_CONFIG__enable__MAX 0x1 - -#define R_NETWORK_GEN_CONFIG__loopback__MIN 0 -#define R_NETWORK_GEN_CONFIG__frame__MIN 0 -#define R_NETWORK_GEN_CONFIG__vg__MIN 0 -#define R_NETWORK_GEN_CONFIG__phy__MIN 0 -#define R_NETWORK_GEN_CONFIG__enable__MIN 0 - -#define R_NETWORK_GEN_CONFIG__loopback__BITNR 5 -#define R_NETWORK_GEN_CONFIG__frame__BITNR 4 -#define R_NETWORK_GEN_CONFIG__vg__BITNR 3 -#define R_NETWORK_GEN_CONFIG__phy__BITNR 1 -#define R_NETWORK_GEN_CONFIG__enable__BITNR 0 - -#define R_NETWORK_GEN_CONFIG__loopback__loopback__VAL REG_VAL_ENUM -#define R_NETWORK_GEN_CONFIG__frame__frame__VAL REG_VAL_ENUM -#define R_NETWORK_GEN_CONFIG__vg__vg__VAL REG_VAL_ENUM -#define R_NETWORK_GEN_CONFIG__phy__phy__VAL REG_VAL_ENUM -#define R_NETWORK_GEN_CONFIG__enable__enable__VAL REG_VAL_ENUM - -#define R_NETWORK_GEN_CONFIG__loopback__loopback__off 0 -#define R_NETWORK_GEN_CONFIG__loopback__loopback__on 1 -#define R_NETWORK_GEN_CONFIG__frame__frame__ether 0 -#define R_NETWORK_GEN_CONFIG__frame__frame__tokenr 1 -#define R_NETWORK_GEN_CONFIG__vg__vg__off 0 -#define R_NETWORK_GEN_CONFIG__vg__vg__on 1 -#define R_NETWORK_GEN_CONFIG__phy__phy__mii_clk 1 -#define R_NETWORK_GEN_CONFIG__phy__phy__mii_err 2 -#define R_NETWORK_GEN_CONFIG__phy__phy__mii_req 3 -#define R_NETWORK_GEN_CONFIG__phy__phy__sni 0 -#define R_NETWORK_GEN_CONFIG__enable__enable__off 0 -#define R_NETWORK_GEN_CONFIG__enable__enable__on 1 - -#endif - -/* - * R_NETWORK_MGM_CTRL - * - type: WO - * - addr: 0xb00000a0 - * - group: Network interface registers - */ - -#if USE_GROUP__Network_interface_registers - -#define R_NETWORK_MGM_CTRL__ADDR (REG_TYPECAST_UDWORD 0xb00000a0) - -#ifndef REG_NO_SHADOW -#define R_NETWORK_MGM_CTRL__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_NETWORK_MGM_CTRL + 0)) -#define R_NETWORK_MGM_CTRL__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_NETWORK_MGM_CTRL + 0)) -#else /* REG_NO_SHADOW */ -#define R_NETWORK_MGM_CTRL__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_NETWORK_MGM_CTRL__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_NETWORK_MGM_CTRL__STYPECAST REG_STYPECAST_UDWORD -#define R_NETWORK_MGM_CTRL__SVAL REG_SVAL_SHADOW -#define R_NETWORK_MGM_CTRL__SVAL_I REG_SVAL_I_SHADOW -#define R_NETWORK_MGM_CTRL__TYPECAST REG_TYPECAST_UDWORD -#define R_NETWORK_MGM_CTRL__TYPE (REG_UDWORD) -#define R_NETWORK_MGM_CTRL__GET REG_GET_WO -#define R_NETWORK_MGM_CTRL__IGET REG_IGET_WO -#define R_NETWORK_MGM_CTRL__SET REG_SET_WO -#define R_NETWORK_MGM_CTRL__ISET REG_ISET_WO -#define R_NETWORK_MGM_CTRL__SET_VAL REG_SET_VAL_WO -#define R_NETWORK_MGM_CTRL__EQL REG_EQL_WO -#define R_NETWORK_MGM_CTRL__IEQL REG_IEQL_WO -#define R_NETWORK_MGM_CTRL__RD REG_RD_WO -#define R_NETWORK_MGM_CTRL__IRD REG_IRD_WO -#define R_NETWORK_MGM_CTRL__WR REG_WR_WO -#define R_NETWORK_MGM_CTRL__IWR REG_IWR_WO - -#define R_NETWORK_MGM_CTRL__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_NETWORK_MGM_CTRL__txd_pins__txd_pins__MASK 0x000000f0U -#define R_NETWORK_MGM_CTRL__txer_pin__txer_pin__MASK 0x00000008U -#define R_NETWORK_MGM_CTRL__mdck__mdck__MASK 0x00000004U -#define R_NETWORK_MGM_CTRL__mdoe__mdoe__MASK 0x00000002U -#define R_NETWORK_MGM_CTRL__mdio__mdio__MASK 0x00000001U - -#define R_NETWORK_MGM_CTRL__txd_pins__MAX 0xf -#define R_NETWORK_MGM_CTRL__txer_pin__MAX 0x1 -#define R_NETWORK_MGM_CTRL__mdck__MAX 0x1 -#define R_NETWORK_MGM_CTRL__mdoe__MAX 0x1 -#define R_NETWORK_MGM_CTRL__mdio__MAX 0x1 - -#define R_NETWORK_MGM_CTRL__txd_pins__MIN 0 -#define R_NETWORK_MGM_CTRL__txer_pin__MIN 0 -#define R_NETWORK_MGM_CTRL__mdck__MIN 0 -#define R_NETWORK_MGM_CTRL__mdoe__MIN 0 -#define R_NETWORK_MGM_CTRL__mdio__MIN 0 - -#define R_NETWORK_MGM_CTRL__txd_pins__BITNR 4 -#define R_NETWORK_MGM_CTRL__txer_pin__BITNR 3 -#define R_NETWORK_MGM_CTRL__mdck__BITNR 2 -#define R_NETWORK_MGM_CTRL__mdoe__BITNR 1 -#define R_NETWORK_MGM_CTRL__mdio__BITNR 0 - -#define R_NETWORK_MGM_CTRL__txd_pins__txd_pins__VAL REG_VAL_VAL -#define R_NETWORK_MGM_CTRL__txer_pin__txer_pin__VAL REG_VAL_VAL -#define R_NETWORK_MGM_CTRL__mdck__mdck__VAL REG_VAL_VAL -#define R_NETWORK_MGM_CTRL__mdoe__mdoe__VAL REG_VAL_ENUM -#define R_NETWORK_MGM_CTRL__mdio__mdio__VAL REG_VAL_VAL - -#define R_NETWORK_MGM_CTRL__mdoe__mdoe__disable 0 -#define R_NETWORK_MGM_CTRL__mdoe__mdoe__enable 1 - -#endif - -/* - * R_NETWORK_REC_CONFIG - * - type: WO - * - addr: 0xb0000094 - * - group: Network interface registers - */ - -#if USE_GROUP__Network_interface_registers - -#define R_NETWORK_REC_CONFIG__ADDR (REG_TYPECAST_UDWORD 0xb0000094) - -#ifndef REG_NO_SHADOW -#define R_NETWORK_REC_CONFIG__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_NETWORK_REC_CONFIG + 0)) -#define R_NETWORK_REC_CONFIG__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_NETWORK_REC_CONFIG + 0)) -#else /* REG_NO_SHADOW */ -#define R_NETWORK_REC_CONFIG__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_NETWORK_REC_CONFIG__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_NETWORK_REC_CONFIG__STYPECAST REG_STYPECAST_UDWORD -#define R_NETWORK_REC_CONFIG__SVAL REG_SVAL_SHADOW -#define R_NETWORK_REC_CONFIG__SVAL_I REG_SVAL_I_SHADOW -#define R_NETWORK_REC_CONFIG__TYPECAST REG_TYPECAST_UDWORD -#define R_NETWORK_REC_CONFIG__TYPE (REG_UDWORD) -#define R_NETWORK_REC_CONFIG__GET REG_GET_WO -#define R_NETWORK_REC_CONFIG__IGET REG_IGET_WO -#define R_NETWORK_REC_CONFIG__SET REG_SET_WO -#define R_NETWORK_REC_CONFIG__ISET REG_ISET_WO -#define R_NETWORK_REC_CONFIG__SET_VAL REG_SET_VAL_WO -#define R_NETWORK_REC_CONFIG__EQL REG_EQL_WO -#define R_NETWORK_REC_CONFIG__IEQL REG_IEQL_WO -#define R_NETWORK_REC_CONFIG__RD REG_RD_WO -#define R_NETWORK_REC_CONFIG__IRD REG_IRD_WO -#define R_NETWORK_REC_CONFIG__WR REG_WR_WO -#define R_NETWORK_REC_CONFIG__IWR REG_IWR_WO - -#define R_NETWORK_REC_CONFIG__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_NETWORK_REC_CONFIG__max_size__max_size__MASK 0x00000400U -#define R_NETWORK_REC_CONFIG__duplex__duplex__MASK 0x00000200U -#define R_NETWORK_REC_CONFIG__bad_crc__bad_crc__MASK 0x00000100U -#define R_NETWORK_REC_CONFIG__oversize__oversize__MASK 0x00000080U -#define R_NETWORK_REC_CONFIG__undersize__undersize__MASK 0x00000040U -#define R_NETWORK_REC_CONFIG__all_roots__all_roots__MASK 0x00000020U -#define R_NETWORK_REC_CONFIG__tr_broadcast__tr_broadcast__MASK 0x00000010U -#define R_NETWORK_REC_CONFIG__broadcast__broadcast__MASK 0x00000008U -#define R_NETWORK_REC_CONFIG__individual__individual__MASK 0x00000004U -#define R_NETWORK_REC_CONFIG__ma1__ma1__MASK 0x00000002U -#define R_NETWORK_REC_CONFIG__ma0__ma0__MASK 0x00000001U - -#define R_NETWORK_REC_CONFIG__max_size__MAX 0x1 -#define R_NETWORK_REC_CONFIG__duplex__MAX 0x1 -#define R_NETWORK_REC_CONFIG__bad_crc__MAX 0x1 -#define R_NETWORK_REC_CONFIG__oversize__MAX 0x1 -#define R_NETWORK_REC_CONFIG__undersize__MAX 0x1 -#define R_NETWORK_REC_CONFIG__all_roots__MAX 0x1 -#define R_NETWORK_REC_CONFIG__tr_broadcast__MAX 0x1 -#define R_NETWORK_REC_CONFIG__broadcast__MAX 0x1 -#define R_NETWORK_REC_CONFIG__individual__MAX 0x1 -#define R_NETWORK_REC_CONFIG__ma1__MAX 0x1 -#define R_NETWORK_REC_CONFIG__ma0__MAX 0x1 - -#define R_NETWORK_REC_CONFIG__max_size__MIN 0 -#define R_NETWORK_REC_CONFIG__duplex__MIN 0 -#define R_NETWORK_REC_CONFIG__bad_crc__MIN 0 -#define R_NETWORK_REC_CONFIG__oversize__MIN 0 -#define R_NETWORK_REC_CONFIG__undersize__MIN 0 -#define R_NETWORK_REC_CONFIG__all_roots__MIN 0 -#define R_NETWORK_REC_CONFIG__tr_broadcast__MIN 0 -#define R_NETWORK_REC_CONFIG__broadcast__MIN 0 -#define R_NETWORK_REC_CONFIG__individual__MIN 0 -#define R_NETWORK_REC_CONFIG__ma1__MIN 0 -#define R_NETWORK_REC_CONFIG__ma0__MIN 0 - -#define R_NETWORK_REC_CONFIG__max_size__BITNR 10 -#define R_NETWORK_REC_CONFIG__duplex__BITNR 9 -#define R_NETWORK_REC_CONFIG__bad_crc__BITNR 8 -#define R_NETWORK_REC_CONFIG__oversize__BITNR 7 -#define R_NETWORK_REC_CONFIG__undersize__BITNR 6 -#define R_NETWORK_REC_CONFIG__all_roots__BITNR 5 -#define R_NETWORK_REC_CONFIG__tr_broadcast__BITNR 4 -#define R_NETWORK_REC_CONFIG__broadcast__BITNR 3 -#define R_NETWORK_REC_CONFIG__individual__BITNR 2 -#define R_NETWORK_REC_CONFIG__ma1__BITNR 1 -#define R_NETWORK_REC_CONFIG__ma0__BITNR 0 - -#define R_NETWORK_REC_CONFIG__max_size__max_size__VAL REG_VAL_ENUM -#define R_NETWORK_REC_CONFIG__duplex__duplex__VAL REG_VAL_ENUM -#define R_NETWORK_REC_CONFIG__bad_crc__bad_crc__VAL REG_VAL_ENUM -#define R_NETWORK_REC_CONFIG__oversize__oversize__VAL REG_VAL_ENUM -#define R_NETWORK_REC_CONFIG__undersize__undersize__VAL REG_VAL_ENUM -#define R_NETWORK_REC_CONFIG__all_roots__all_roots__VAL REG_VAL_ENUM -#define R_NETWORK_REC_CONFIG__tr_broadcast__tr_broadcast__VAL REG_VAL_ENUM -#define R_NETWORK_REC_CONFIG__broadcast__broadcast__VAL REG_VAL_ENUM -#define R_NETWORK_REC_CONFIG__individual__individual__VAL REG_VAL_ENUM -#define R_NETWORK_REC_CONFIG__ma1__ma1__VAL REG_VAL_ENUM -#define R_NETWORK_REC_CONFIG__ma0__ma0__VAL REG_VAL_ENUM - -#define R_NETWORK_REC_CONFIG__max_size__max_size__size1518 0 -#define R_NETWORK_REC_CONFIG__max_size__max_size__size1522 1 -#define R_NETWORK_REC_CONFIG__duplex__duplex__full 1 -#define R_NETWORK_REC_CONFIG__duplex__duplex__half 0 -#define R_NETWORK_REC_CONFIG__bad_crc__bad_crc__discard 0 -#define R_NETWORK_REC_CONFIG__bad_crc__bad_crc__receive 1 -#define R_NETWORK_REC_CONFIG__oversize__oversize__discard 0 -#define R_NETWORK_REC_CONFIG__oversize__oversize__receive 1 -#define R_NETWORK_REC_CONFIG__undersize__undersize__discard 0 -#define R_NETWORK_REC_CONFIG__undersize__undersize__receive 1 -#define R_NETWORK_REC_CONFIG__all_roots__all_roots__discard 0 -#define R_NETWORK_REC_CONFIG__all_roots__all_roots__receive 1 -#define R_NETWORK_REC_CONFIG__tr_broadcast__tr_broadcast__discard 0 -#define R_NETWORK_REC_CONFIG__tr_broadcast__tr_broadcast__receive 1 -#define R_NETWORK_REC_CONFIG__broadcast__broadcast__discard 0 -#define R_NETWORK_REC_CONFIG__broadcast__broadcast__receive 1 -#define R_NETWORK_REC_CONFIG__individual__individual__discard 0 -#define R_NETWORK_REC_CONFIG__individual__individual__receive 1 -#define R_NETWORK_REC_CONFIG__ma1__ma1__disable 0 -#define R_NETWORK_REC_CONFIG__ma1__ma1__enable 1 -#define R_NETWORK_REC_CONFIG__ma0__ma0__disable 0 -#define R_NETWORK_REC_CONFIG__ma0__ma0__enable 1 - -#endif - -/* - * R_NETWORK_SA_0 - * - type: WO - * - addr: 0xb0000080 - * - group: Network interface registers - */ - -#if USE_GROUP__Network_interface_registers - -#define R_NETWORK_SA_0__ADDR (REG_TYPECAST_UDWORD 0xb0000080) - -#ifndef REG_NO_SHADOW -#define R_NETWORK_SA_0__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_NETWORK_SA_0 + 0)) -#define R_NETWORK_SA_0__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_NETWORK_SA_0 + 0)) -#else /* REG_NO_SHADOW */ -#define R_NETWORK_SA_0__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_NETWORK_SA_0__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_NETWORK_SA_0__STYPECAST REG_STYPECAST_UDWORD -#define R_NETWORK_SA_0__SVAL REG_SVAL_SHADOW -#define R_NETWORK_SA_0__SVAL_I REG_SVAL_I_SHADOW -#define R_NETWORK_SA_0__TYPECAST REG_TYPECAST_UDWORD -#define R_NETWORK_SA_0__TYPE (REG_UDWORD) -#define R_NETWORK_SA_0__GET REG_GET_WO -#define R_NETWORK_SA_0__IGET REG_IGET_WO -#define R_NETWORK_SA_0__SET REG_SET_WO -#define R_NETWORK_SA_0__ISET REG_ISET_WO -#define R_NETWORK_SA_0__SET_VAL REG_SET_VAL_WO -#define R_NETWORK_SA_0__EQL REG_EQL_WO -#define R_NETWORK_SA_0__IEQL REG_IEQL_WO -#define R_NETWORK_SA_0__RD REG_RD_WO -#define R_NETWORK_SA_0__IRD REG_IRD_WO -#define R_NETWORK_SA_0__WR REG_WR_WO -#define R_NETWORK_SA_0__IWR REG_IWR_WO - -#define R_NETWORK_SA_0__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_NETWORK_SA_0__ma0_low__ma0_low__MASK 0xffffffffU - -#define R_NETWORK_SA_0__ma0_low__MAX 0xffffffff - -#define R_NETWORK_SA_0__ma0_low__MIN 0 - -#define R_NETWORK_SA_0__ma0_low__BITNR 0 - -#define R_NETWORK_SA_0__ma0_low__ma0_low__VAL REG_VAL_VAL - - -#endif - -/* - * R_NETWORK_SA_1 - * - type: WO - * - addr: 0xb0000084 - * - group: Network interface registers - */ - -#if USE_GROUP__Network_interface_registers - -#define R_NETWORK_SA_1__ADDR (REG_TYPECAST_UDWORD 0xb0000084) - -#ifndef REG_NO_SHADOW -#define R_NETWORK_SA_1__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_NETWORK_SA_1 + 0)) -#define R_NETWORK_SA_1__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_NETWORK_SA_1 + 0)) -#else /* REG_NO_SHADOW */ -#define R_NETWORK_SA_1__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_NETWORK_SA_1__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_NETWORK_SA_1__STYPECAST REG_STYPECAST_UDWORD -#define R_NETWORK_SA_1__SVAL REG_SVAL_SHADOW -#define R_NETWORK_SA_1__SVAL_I REG_SVAL_I_SHADOW -#define R_NETWORK_SA_1__TYPECAST REG_TYPECAST_UDWORD -#define R_NETWORK_SA_1__TYPE (REG_UDWORD) -#define R_NETWORK_SA_1__GET REG_GET_WO -#define R_NETWORK_SA_1__IGET REG_IGET_WO -#define R_NETWORK_SA_1__SET REG_SET_WO -#define R_NETWORK_SA_1__ISET REG_ISET_WO -#define R_NETWORK_SA_1__SET_VAL REG_SET_VAL_WO -#define R_NETWORK_SA_1__EQL REG_EQL_WO -#define R_NETWORK_SA_1__IEQL REG_IEQL_WO -#define R_NETWORK_SA_1__RD REG_RD_WO -#define R_NETWORK_SA_1__IRD REG_IRD_WO -#define R_NETWORK_SA_1__WR REG_WR_WO -#define R_NETWORK_SA_1__IWR REG_IWR_WO - -#define R_NETWORK_SA_1__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_NETWORK_SA_1__ma1_low__ma1_low__MASK 0xffff0000U -#define R_NETWORK_SA_1__ma0_high__ma0_high__MASK 0x0000ffffU - -#define R_NETWORK_SA_1__ma1_low__MAX 0xffff -#define R_NETWORK_SA_1__ma0_high__MAX 0xffff - -#define R_NETWORK_SA_1__ma1_low__MIN 0 -#define R_NETWORK_SA_1__ma0_high__MIN 0 - -#define R_NETWORK_SA_1__ma1_low__BITNR 16 -#define R_NETWORK_SA_1__ma0_high__BITNR 0 - -#define R_NETWORK_SA_1__ma1_low__ma1_low__VAL REG_VAL_VAL -#define R_NETWORK_SA_1__ma0_high__ma0_high__VAL REG_VAL_VAL - - -#endif - -/* - * R_NETWORK_SA_2 - * - type: WO - * - addr: 0xb0000088 - * - group: Network interface registers - */ - -#if USE_GROUP__Network_interface_registers - -#define R_NETWORK_SA_2__ADDR (REG_TYPECAST_UDWORD 0xb0000088) - -#ifndef REG_NO_SHADOW -#define R_NETWORK_SA_2__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_NETWORK_SA_2 + 0)) -#define R_NETWORK_SA_2__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_NETWORK_SA_2 + 0)) -#else /* REG_NO_SHADOW */ -#define R_NETWORK_SA_2__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_NETWORK_SA_2__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_NETWORK_SA_2__STYPECAST REG_STYPECAST_UDWORD -#define R_NETWORK_SA_2__SVAL REG_SVAL_SHADOW -#define R_NETWORK_SA_2__SVAL_I REG_SVAL_I_SHADOW -#define R_NETWORK_SA_2__TYPECAST REG_TYPECAST_UDWORD -#define R_NETWORK_SA_2__TYPE (REG_UDWORD) -#define R_NETWORK_SA_2__GET REG_GET_WO -#define R_NETWORK_SA_2__IGET REG_IGET_WO -#define R_NETWORK_SA_2__SET REG_SET_WO -#define R_NETWORK_SA_2__ISET REG_ISET_WO -#define R_NETWORK_SA_2__SET_VAL REG_SET_VAL_WO -#define R_NETWORK_SA_2__EQL REG_EQL_WO -#define R_NETWORK_SA_2__IEQL REG_IEQL_WO -#define R_NETWORK_SA_2__RD REG_RD_WO -#define R_NETWORK_SA_2__IRD REG_IRD_WO -#define R_NETWORK_SA_2__WR REG_WR_WO -#define R_NETWORK_SA_2__IWR REG_IWR_WO - -#define R_NETWORK_SA_2__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_NETWORK_SA_2__ma1_high__ma1_high__MASK 0xffffffffU - -#define R_NETWORK_SA_2__ma1_high__MAX 0xffffffff - -#define R_NETWORK_SA_2__ma1_high__MIN 0 - -#define R_NETWORK_SA_2__ma1_high__BITNR 0 - -#define R_NETWORK_SA_2__ma1_high__ma1_high__VAL REG_VAL_VAL - - -#endif - -/* - * R_NETWORK_STAT - * - type: RO - * - addr: 0xb00000a0 - * - group: Network interface registers - */ - -#if USE_GROUP__Network_interface_registers - -#define R_NETWORK_STAT__ADDR (REG_TYPECAST_UDWORD 0xb00000a0) -#define R_NETWORK_STAT__SVAL REG_SVAL_SHADOW -#define R_NETWORK_STAT__SVAL_I REG_SVAL_I_SHADOW -#define R_NETWORK_STAT__TYPECAST REG_TYPECAST_UDWORD -#define R_NETWORK_STAT__TYPE (REG_UDWORD) -#define R_NETWORK_STAT__GET REG_GET_RO -#define R_NETWORK_STAT__IGET REG_IGET_RO -#define R_NETWORK_STAT__SET REG_SET_RO -#define R_NETWORK_STAT__ISET REG_ISET_RO -#define R_NETWORK_STAT__SET_VAL REG_SET_VAL_RO -#define R_NETWORK_STAT__EQL REG_EQL_RO -#define R_NETWORK_STAT__IEQL REG_IEQL_RO -#define R_NETWORK_STAT__RD REG_RD_RO -#define R_NETWORK_STAT__IRD REG_IRD_RO -#define R_NETWORK_STAT__WR REG_WR_RO -#define R_NETWORK_STAT__IWR REG_IWR_RO - -#define R_NETWORK_STAT__READ(addr) \ - (*(addr)) - -#define R_NETWORK_STAT__rxd_pins__rxd_pins__MASK 0x000000f0U -#define R_NETWORK_STAT__rxer__rxer__MASK 0x00000008U -#define R_NETWORK_STAT__underrun__underrun__MASK 0x00000004U -#define R_NETWORK_STAT__exc_col__exc_col__MASK 0x00000002U -#define R_NETWORK_STAT__mdio__mdio__MASK 0x00000001U - -#define R_NETWORK_STAT__rxd_pins__MAX 0xf -#define R_NETWORK_STAT__rxer__MAX 0x1 -#define R_NETWORK_STAT__underrun__MAX 0x1 -#define R_NETWORK_STAT__exc_col__MAX 0x1 -#define R_NETWORK_STAT__mdio__MAX 0x1 - -#define R_NETWORK_STAT__rxd_pins__MIN 0 -#define R_NETWORK_STAT__rxer__MIN 0 -#define R_NETWORK_STAT__underrun__MIN 0 -#define R_NETWORK_STAT__exc_col__MIN 0 -#define R_NETWORK_STAT__mdio__MIN 0 - -#define R_NETWORK_STAT__rxd_pins__BITNR 4 -#define R_NETWORK_STAT__rxer__BITNR 3 -#define R_NETWORK_STAT__underrun__BITNR 2 -#define R_NETWORK_STAT__exc_col__BITNR 1 -#define R_NETWORK_STAT__mdio__BITNR 0 - -#define R_NETWORK_STAT__rxd_pins__rxd_pins__VAL REG_VAL_VAL -#define R_NETWORK_STAT__rxer__rxer__VAL REG_VAL_VAL -#define R_NETWORK_STAT__underrun__underrun__VAL REG_VAL_ENUM -#define R_NETWORK_STAT__exc_col__exc_col__VAL REG_VAL_ENUM -#define R_NETWORK_STAT__mdio__mdio__VAL REG_VAL_VAL - -#define R_NETWORK_STAT__underrun__underrun__no 0 -#define R_NETWORK_STAT__underrun__underrun__yes 1 -#define R_NETWORK_STAT__exc_col__exc_col__no 0 -#define R_NETWORK_STAT__exc_col__exc_col__yes 1 - -#endif - -/* - * R_NETWORK_TR_CTRL - * - type: WO - * - addr: 0xb000009c - * - group: Network interface registers - */ - -#if USE_GROUP__Network_interface_registers - -#define R_NETWORK_TR_CTRL__ADDR (REG_TYPECAST_UDWORD 0xb000009c) - -#ifndef REG_NO_SHADOW -#define R_NETWORK_TR_CTRL__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_NETWORK_TR_CTRL + 0)) -#define R_NETWORK_TR_CTRL__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_NETWORK_TR_CTRL + 0)) -#else /* REG_NO_SHADOW */ -#define R_NETWORK_TR_CTRL__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_NETWORK_TR_CTRL__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_NETWORK_TR_CTRL__STYPECAST REG_STYPECAST_UDWORD -#define R_NETWORK_TR_CTRL__SVAL REG_SVAL_SHADOW -#define R_NETWORK_TR_CTRL__SVAL_I REG_SVAL_I_SHADOW -#define R_NETWORK_TR_CTRL__TYPECAST REG_TYPECAST_UDWORD -#define R_NETWORK_TR_CTRL__TYPE (REG_UDWORD) -#define R_NETWORK_TR_CTRL__GET REG_GET_WO -#define R_NETWORK_TR_CTRL__IGET REG_IGET_WO -#define R_NETWORK_TR_CTRL__SET REG_SET_WO -#define R_NETWORK_TR_CTRL__ISET REG_ISET_WO -#define R_NETWORK_TR_CTRL__SET_VAL REG_SET_VAL_WO -#define R_NETWORK_TR_CTRL__EQL REG_EQL_WO -#define R_NETWORK_TR_CTRL__IEQL REG_IEQL_WO -#define R_NETWORK_TR_CTRL__RD REG_RD_WO -#define R_NETWORK_TR_CTRL__IRD REG_IRD_WO -#define R_NETWORK_TR_CTRL__WR REG_WR_WO -#define R_NETWORK_TR_CTRL__IWR REG_IWR_WO - -#define R_NETWORK_TR_CTRL__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_NETWORK_TR_CTRL__clr_error__clr_error__MASK 0x00000100U -#define R_NETWORK_TR_CTRL__delay__delay__MASK 0x00000020U -#define R_NETWORK_TR_CTRL__cancel__cancel__MASK 0x00000010U -#define R_NETWORK_TR_CTRL__cd__cd__MASK 0x00000008U -#define R_NETWORK_TR_CTRL__retry__retry__MASK 0x00000004U -#define R_NETWORK_TR_CTRL__pad__pad__MASK 0x00000002U -#define R_NETWORK_TR_CTRL__crc__crc__MASK 0x00000001U - -#define R_NETWORK_TR_CTRL__clr_error__MAX 0x1 -#define R_NETWORK_TR_CTRL__delay__MAX 0x1 -#define R_NETWORK_TR_CTRL__cancel__MAX 0x1 -#define R_NETWORK_TR_CTRL__cd__MAX 0x1 -#define R_NETWORK_TR_CTRL__retry__MAX 0x1 -#define R_NETWORK_TR_CTRL__pad__MAX 0x1 -#define R_NETWORK_TR_CTRL__crc__MAX 0x1 - -#define R_NETWORK_TR_CTRL__clr_error__MIN 0 -#define R_NETWORK_TR_CTRL__delay__MIN 0 -#define R_NETWORK_TR_CTRL__cancel__MIN 0 -#define R_NETWORK_TR_CTRL__cd__MIN 0 -#define R_NETWORK_TR_CTRL__retry__MIN 0 -#define R_NETWORK_TR_CTRL__pad__MIN 0 -#define R_NETWORK_TR_CTRL__crc__MIN 0 - -#define R_NETWORK_TR_CTRL__clr_error__BITNR 8 -#define R_NETWORK_TR_CTRL__delay__BITNR 5 -#define R_NETWORK_TR_CTRL__cancel__BITNR 4 -#define R_NETWORK_TR_CTRL__cd__BITNR 3 -#define R_NETWORK_TR_CTRL__retry__BITNR 2 -#define R_NETWORK_TR_CTRL__pad__BITNR 1 -#define R_NETWORK_TR_CTRL__crc__BITNR 0 - -#define R_NETWORK_TR_CTRL__clr_error__clr_error__VAL REG_VAL_ENUM -#define R_NETWORK_TR_CTRL__delay__delay__VAL REG_VAL_ENUM -#define R_NETWORK_TR_CTRL__cancel__cancel__VAL REG_VAL_ENUM -#define R_NETWORK_TR_CTRL__cd__cd__VAL REG_VAL_ENUM -#define R_NETWORK_TR_CTRL__retry__retry__VAL REG_VAL_ENUM -#define R_NETWORK_TR_CTRL__pad__pad__VAL REG_VAL_ENUM -#define R_NETWORK_TR_CTRL__crc__crc__VAL REG_VAL_ENUM - -#define R_NETWORK_TR_CTRL__clr_error__clr_error__clr 1 -#define R_NETWORK_TR_CTRL__clr_error__clr_error__nop 0 -#define R_NETWORK_TR_CTRL__delay__delay__d2us 1 -#define R_NETWORK_TR_CTRL__delay__delay__none 0 -#define R_NETWORK_TR_CTRL__cancel__cancel__do 1 -#define R_NETWORK_TR_CTRL__cancel__cancel__dont 0 -#define R_NETWORK_TR_CTRL__cd__cd__ack_col 0 -#define R_NETWORK_TR_CTRL__cd__cd__ack_crs 1 -#define R_NETWORK_TR_CTRL__cd__cd__disable 1 -#define R_NETWORK_TR_CTRL__cd__cd__enable 0 -#define R_NETWORK_TR_CTRL__retry__retry__disable 1 -#define R_NETWORK_TR_CTRL__retry__retry__enable 0 -#define R_NETWORK_TR_CTRL__pad__pad__disable 0 -#define R_NETWORK_TR_CTRL__pad__pad__enable 1 -#define R_NETWORK_TR_CTRL__crc__crc__disable 1 -#define R_NETWORK_TR_CTRL__crc__crc__enable 0 - -#endif - -/* - * R_PAR0_CONFIG - * - type: WO - * - addr: 0xb0000044 - * - group: Parallel printer port registers - */ - -#if USE_GROUP__Parallel_printer_port_registers - -#define R_PAR0_CONFIG__ADDR (REG_TYPECAST_UDWORD 0xb0000044) - -#ifndef REG_NO_SHADOW -#define R_PAR0_CONFIG__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_ATA_CONFIG + 0)) -#define R_PAR0_CONFIG__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_ATA_CONFIG + 0)) -#else /* REG_NO_SHADOW */ -#define R_PAR0_CONFIG__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_PAR0_CONFIG__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_PAR0_CONFIG__STYPECAST REG_STYPECAST_UDWORD -#define R_PAR0_CONFIG__SVAL REG_SVAL_SHADOW -#define R_PAR0_CONFIG__SVAL_I REG_SVAL_I_SHADOW -#define R_PAR0_CONFIG__TYPECAST REG_TYPECAST_UDWORD -#define R_PAR0_CONFIG__TYPE (REG_UDWORD) -#define R_PAR0_CONFIG__GET REG_GET_WO -#define R_PAR0_CONFIG__IGET REG_IGET_WO -#define R_PAR0_CONFIG__SET REG_SET_WO -#define R_PAR0_CONFIG__ISET REG_ISET_WO -#define R_PAR0_CONFIG__SET_VAL REG_SET_VAL_WO -#define R_PAR0_CONFIG__EQL REG_EQL_WO -#define R_PAR0_CONFIG__IEQL REG_IEQL_WO -#define R_PAR0_CONFIG__RD REG_RD_WO -#define R_PAR0_CONFIG__IRD REG_IRD_WO -#define R_PAR0_CONFIG__WR REG_WR_WO -#define R_PAR0_CONFIG__IWR REG_IWR_WO - -#define R_PAR0_CONFIG__WRITE(addr,value) \ - (*(addr) = (value)) - -/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */ -#define R_PAR0_CONFIG__FIRST 0 -#define R_PAR0_CONFIG__IOFFSET 12 -#define R_PAR0_CONFIG__LAST 1 -#define R_PAR0_CONFIG__OFFSET 16 -#define R_PAR0_CONFIG__SOFFSET 12 -/* end */ - -#define R_PAR0_CONFIG__ioe__ioe__MASK 0x02000000U -#define R_PAR0_CONFIG__iseli__iseli__MASK 0x01000000U -#define R_PAR0_CONFIG__iautofd__iautofd__MASK 0x00800000U -#define R_PAR0_CONFIG__istrb__istrb__MASK 0x00400000U -#define R_PAR0_CONFIG__iinit__iinit__MASK 0x00200000U -#define R_PAR0_CONFIG__iperr__iperr__MASK 0x00100000U -#define R_PAR0_CONFIG__iack__iack__MASK 0x00080000U -#define R_PAR0_CONFIG__ibusy__ibusy__MASK 0x00040000U -#define R_PAR0_CONFIG__ifault__ifault__MASK 0x00020000U -#define R_PAR0_CONFIG__isel__isel__MASK 0x00010000U -#define R_PAR0_CONFIG__ext_mode__ext_mode__MASK 0x00000800U -#define R_PAR0_CONFIG__wide__wide__MASK 0x00000400U -#define R_PAR0_CONFIG__dma__dma__MASK 0x00000200U -#define R_PAR0_CONFIG__rle_in__rle_in__MASK 0x00000100U -#define R_PAR0_CONFIG__rle_out__rle_out__MASK 0x00000080U -#define R_PAR0_CONFIG__enable__enable__MASK 0x00000040U -#define R_PAR0_CONFIG__force__force__MASK 0x00000020U -#define R_PAR0_CONFIG__ign_ack__ign_ack__MASK 0x00000010U -#define R_PAR0_CONFIG__oe_ack__oe_ack__MASK 0x00000008U -#define R_PAR0_CONFIG__epp_addr_data__epp_addr_data__MASK 0x00000008U -#define R_PAR0_CONFIG__oe_ack__epp_addr_data__MASK 0x00000008U -#define R_PAR0_CONFIG__mode__mode__MASK 0x00000007U - -#define R_PAR0_CONFIG__ioe__MAX 0x1 -#define R_PAR0_CONFIG__iseli__MAX 0x1 -#define R_PAR0_CONFIG__iautofd__MAX 0x1 -#define R_PAR0_CONFIG__istrb__MAX 0x1 -#define R_PAR0_CONFIG__iinit__MAX 0x1 -#define R_PAR0_CONFIG__iperr__MAX 0x1 -#define R_PAR0_CONFIG__iack__MAX 0x1 -#define R_PAR0_CONFIG__ibusy__MAX 0x1 -#define R_PAR0_CONFIG__ifault__MAX 0x1 -#define R_PAR0_CONFIG__isel__MAX 0x1 -#define R_PAR0_CONFIG__ext_mode__MAX 0x1 -#define R_PAR0_CONFIG__wide__MAX 0x1 -#define R_PAR0_CONFIG__dma__MAX 0x1 -#define R_PAR0_CONFIG__rle_in__MAX 0x1 -#define R_PAR0_CONFIG__rle_out__MAX 0x1 -#define R_PAR0_CONFIG__enable__MAX 0x1 -#define R_PAR0_CONFIG__force__MAX 0x1 -#define R_PAR0_CONFIG__ign_ack__MAX 0x1 -#define R_PAR0_CONFIG__oe_ack__MAX 0x1 -#define R_PAR0_CONFIG__epp_addr_data__MAX 0x1 -#define R_PAR0_CONFIG__mode__MAX 0x7 - -#define R_PAR0_CONFIG__ioe__MIN 0 -#define R_PAR0_CONFIG__iseli__MIN 0 -#define R_PAR0_CONFIG__iautofd__MIN 0 -#define R_PAR0_CONFIG__istrb__MIN 0 -#define R_PAR0_CONFIG__iinit__MIN 0 -#define R_PAR0_CONFIG__iperr__MIN 0 -#define R_PAR0_CONFIG__iack__MIN 0 -#define R_PAR0_CONFIG__ibusy__MIN 0 -#define R_PAR0_CONFIG__ifault__MIN 0 -#define R_PAR0_CONFIG__isel__MIN 0 -#define R_PAR0_CONFIG__ext_mode__MIN 0 -#define R_PAR0_CONFIG__wide__MIN 0 -#define R_PAR0_CONFIG__dma__MIN 0 -#define R_PAR0_CONFIG__rle_in__MIN 0 -#define R_PAR0_CONFIG__rle_out__MIN 0 -#define R_PAR0_CONFIG__enable__MIN 0 -#define R_PAR0_CONFIG__force__MIN 0 -#define R_PAR0_CONFIG__ign_ack__MIN 0 -#define R_PAR0_CONFIG__oe_ack__MIN 0 -#define R_PAR0_CONFIG__epp_addr_data__MIN 0 -#define R_PAR0_CONFIG__mode__MIN 0 - -#define R_PAR0_CONFIG__ioe__BITNR 25 -#define R_PAR0_CONFIG__iseli__BITNR 24 -#define R_PAR0_CONFIG__iautofd__BITNR 23 -#define R_PAR0_CONFIG__istrb__BITNR 22 -#define R_PAR0_CONFIG__iinit__BITNR 21 -#define R_PAR0_CONFIG__iperr__BITNR 20 -#define R_PAR0_CONFIG__iack__BITNR 19 -#define R_PAR0_CONFIG__ibusy__BITNR 18 -#define R_PAR0_CONFIG__ifault__BITNR 17 -#define R_PAR0_CONFIG__isel__BITNR 16 -#define R_PAR0_CONFIG__ext_mode__BITNR 11 -#define R_PAR0_CONFIG__wide__BITNR 10 -#define R_PAR0_CONFIG__dma__BITNR 9 -#define R_PAR0_CONFIG__rle_in__BITNR 8 -#define R_PAR0_CONFIG__rle_out__BITNR 7 -#define R_PAR0_CONFIG__enable__BITNR 6 -#define R_PAR0_CONFIG__force__BITNR 5 -#define R_PAR0_CONFIG__ign_ack__BITNR 4 -#define R_PAR0_CONFIG__oe_ack__BITNR 3 -#define R_PAR0_CONFIG__epp_addr_data__BITNR 3 -#define R_PAR0_CONFIG__mode__BITNR 0 - -#define R_PAR0_CONFIG__ioe__ioe__VAL REG_VAL_ENUM -#define R_PAR0_CONFIG__iseli__iseli__VAL REG_VAL_ENUM -#define R_PAR0_CONFIG__iautofd__iautofd__VAL REG_VAL_ENUM -#define R_PAR0_CONFIG__istrb__istrb__VAL REG_VAL_ENUM -#define R_PAR0_CONFIG__iinit__iinit__VAL REG_VAL_ENUM -#define R_PAR0_CONFIG__iperr__iperr__VAL REG_VAL_ENUM -#define R_PAR0_CONFIG__iack__iack__VAL REG_VAL_ENUM -#define R_PAR0_CONFIG__ibusy__ibusy__VAL REG_VAL_ENUM -#define R_PAR0_CONFIG__ifault__ifault__VAL REG_VAL_ENUM -#define R_PAR0_CONFIG__isel__isel__VAL REG_VAL_ENUM -#define R_PAR0_CONFIG__ext_mode__ext_mode__VAL REG_VAL_ENUM -#define R_PAR0_CONFIG__wide__wide__VAL REG_VAL_ENUM -#define R_PAR0_CONFIG__dma__dma__VAL REG_VAL_ENUM -#define R_PAR0_CONFIG__rle_in__rle_in__VAL REG_VAL_ENUM -#define R_PAR0_CONFIG__rle_out__rle_out__VAL REG_VAL_ENUM -#define R_PAR0_CONFIG__enable__enable__VAL REG_VAL_ENUM -#define R_PAR0_CONFIG__force__force__VAL REG_VAL_ENUM -#define R_PAR0_CONFIG__ign_ack__ign_ack__VAL REG_VAL_ENUM -#define R_PAR0_CONFIG__oe_ack__oe_ack__VAL REG_VAL_ENUM -#define R_PAR0_CONFIG__epp_addr_data__epp_addr_data__VAL REG_VAL_ENUM -#define R_PAR0_CONFIG__oe_ack__epp_addr_data__VAL REG_VAL_ENUM -#define R_PAR0_CONFIG__mode__mode__VAL REG_VAL_ENUM - -#define R_PAR0_CONFIG__ioe__ioe__inv 1 -#define R_PAR0_CONFIG__ioe__ioe__noninv 0 -#define R_PAR0_CONFIG__iseli__iseli__inv 1 -#define R_PAR0_CONFIG__iseli__iseli__noninv 0 -#define R_PAR0_CONFIG__iautofd__iautofd__inv 1 -#define R_PAR0_CONFIG__iautofd__iautofd__noninv 0 -#define R_PAR0_CONFIG__istrb__istrb__inv 1 -#define R_PAR0_CONFIG__istrb__istrb__noninv 0 -#define R_PAR0_CONFIG__iinit__iinit__inv 1 -#define R_PAR0_CONFIG__iinit__iinit__noninv 0 -#define R_PAR0_CONFIG__iperr__iperr__inv 1 -#define R_PAR0_CONFIG__iperr__iperr__noninv 0 -#define R_PAR0_CONFIG__iack__iack__inv 1 -#define R_PAR0_CONFIG__iack__iack__noninv 0 -#define R_PAR0_CONFIG__ibusy__ibusy__inv 1 -#define R_PAR0_CONFIG__ibusy__ibusy__noninv 0 -#define R_PAR0_CONFIG__ifault__ifault__inv 1 -#define R_PAR0_CONFIG__ifault__ifault__noninv 0 -#define R_PAR0_CONFIG__isel__isel__inv 1 -#define R_PAR0_CONFIG__isel__isel__noninv 0 -#define R_PAR0_CONFIG__ext_mode__ext_mode__disable 0 -#define R_PAR0_CONFIG__ext_mode__ext_mode__enable 1 -#define R_PAR0_CONFIG__wide__wide__disable 0 -#define R_PAR0_CONFIG__wide__wide__enable 1 -#define R_PAR0_CONFIG__dma__dma__disable 0 -#define R_PAR0_CONFIG__dma__dma__enable 1 -#define R_PAR0_CONFIG__rle_in__rle_in__disable 0 -#define R_PAR0_CONFIG__rle_in__rle_in__enable 1 -#define R_PAR0_CONFIG__rle_out__rle_out__disable 0 -#define R_PAR0_CONFIG__rle_out__rle_out__enable 1 -#define R_PAR0_CONFIG__enable__enable__on 1 -#define R_PAR0_CONFIG__enable__enable__reset 0 -#define R_PAR0_CONFIG__force__force__off 0 -#define R_PAR0_CONFIG__force__force__on 1 -#define R_PAR0_CONFIG__ign_ack__ign_ack__ignore 1 -#define R_PAR0_CONFIG__ign_ack__ign_ack__wait 0 -#define R_PAR0_CONFIG__oe_ack__oe_ack__dont_wait 0 -#define R_PAR0_CONFIG__oe_ack__oe_ack__epp_addr 1 -#define R_PAR0_CONFIG__oe_ack__oe_ack__epp_data 0 -#define R_PAR0_CONFIG__oe_ack__oe_ack__wait_oe 1 -#define R_PAR0_CONFIG__epp_addr_data__epp_addr_data__dont_wait 0 -#define R_PAR0_CONFIG__epp_addr_data__epp_addr_data__epp_addr 1 -#define R_PAR0_CONFIG__epp_addr_data__epp_addr_data__epp_data 0 -#define R_PAR0_CONFIG__epp_addr_data__epp_addr_data__wait_oe 1 -#define R_PAR0_CONFIG__mode__mode__byte 4 -#define R_PAR0_CONFIG__mode__mode__centronics 1 -#define R_PAR0_CONFIG__mode__mode__ecp_fwd 5 -#define R_PAR0_CONFIG__mode__mode__ecp_rev 6 -#define R_PAR0_CONFIG__mode__mode__epp_rd 0 -#define R_PAR0_CONFIG__mode__mode__epp_wr1 5 -#define R_PAR0_CONFIG__mode__mode__epp_wr2 6 -#define R_PAR0_CONFIG__mode__mode__epp_wr3 7 -#define R_PAR0_CONFIG__mode__mode__fastbyte 2 -#define R_PAR0_CONFIG__mode__mode__manual 0 -#define R_PAR0_CONFIG__mode__mode__nibble 3 -#define R_PAR0_CONFIG__mode__mode__off 7 - -#endif - -/* - * R_PAR0_CTRL - * - type: WO - * - addr: 0xb0000042 - * - group: Parallel printer port registers - */ - -#if USE_GROUP__Parallel_printer_port_registers - -#define R_PAR0_CTRL__ADDR (REG_TYPECAST_BYTE 0xb0000042) - -#ifndef REG_NO_SHADOW -#define R_PAR0_CTRL__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_ATA_CTRL_DATA + 2)) -#define R_PAR0_CTRL__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_ATA_CTRL_DATA + 2)) -#else /* REG_NO_SHADOW */ -#define R_PAR0_CTRL__SADDR (REG_STYPECAST_BYTE (®_shadow__hwregs)) -#define R_PAR0_CTRL__IADDR (REG_STYPECAST_BYTE (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_PAR0_CTRL__STYPECAST REG_STYPECAST_BYTE -#define R_PAR0_CTRL__SVAL REG_SVAL_SHADOW -#define R_PAR0_CTRL__SVAL_I REG_SVAL_I_SHADOW -#define R_PAR0_CTRL__TYPECAST REG_TYPECAST_BYTE -#define R_PAR0_CTRL__TYPE (REG_BYTE) -#define R_PAR0_CTRL__GET REG_GET_WO -#define R_PAR0_CTRL__IGET REG_IGET_WO -#define R_PAR0_CTRL__SET REG_SET_WO -#define R_PAR0_CTRL__ISET REG_ISET_WO -#define R_PAR0_CTRL__SET_VAL REG_SET_VAL_WO -#define R_PAR0_CTRL__EQL REG_EQL_WO -#define R_PAR0_CTRL__IEQL REG_IEQL_WO -#define R_PAR0_CTRL__RD REG_RD_WO -#define R_PAR0_CTRL__IRD REG_IRD_WO -#define R_PAR0_CTRL__WR REG_WR_WO -#define R_PAR0_CTRL__IWR REG_IWR_WO - -#define R_PAR0_CTRL__WRITE(addr,value) \ - (*(addr) = (value)) - -/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */ -#define R_PAR0_CTRL__FIRST 0 -#define R_PAR0_CTRL__IOFFSET 12 -#define R_PAR0_CTRL__LAST 1 -#define R_PAR0_CTRL__OFFSET 16 -#define R_PAR0_CTRL__SOFFSET 12 -/* end */ - -#define R_PAR0_CTRL__ctrl__ctrl__MASK 0x0000001fU - -#define R_PAR0_CTRL__ctrl__MAX 31 - -#define R_PAR0_CTRL__ctrl__MIN 0 - -#define R_PAR0_CTRL__ctrl__BITNR 0 - -#define R_PAR0_CTRL__ctrl__ctrl__VAL REG_VAL_VAL - - -#endif - -/* - * R_PAR0_CTRL_DATA - * - type: WO - * - addr: 0xb0000040 - * - group: Parallel printer port registers - */ - -#if USE_GROUP__Parallel_printer_port_registers - -#define R_PAR0_CTRL_DATA__ADDR (REG_TYPECAST_UDWORD 0xb0000040) - -#ifndef REG_NO_SHADOW -#define R_PAR0_CTRL_DATA__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_ATA_CTRL_DATA + 0)) -#define R_PAR0_CTRL_DATA__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_ATA_CTRL_DATA + 0)) -#else /* REG_NO_SHADOW */ -#define R_PAR0_CTRL_DATA__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_PAR0_CTRL_DATA__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_PAR0_CTRL_DATA__STYPECAST REG_STYPECAST_UDWORD -#define R_PAR0_CTRL_DATA__SVAL REG_SVAL_SHADOW -#define R_PAR0_CTRL_DATA__SVAL_I REG_SVAL_I_SHADOW -#define R_PAR0_CTRL_DATA__TYPECAST REG_TYPECAST_UDWORD -#define R_PAR0_CTRL_DATA__TYPE (REG_UDWORD) -#define R_PAR0_CTRL_DATA__GET REG_GET_WO -#define R_PAR0_CTRL_DATA__IGET REG_IGET_WO -#define R_PAR0_CTRL_DATA__SET REG_SET_WO -#define R_PAR0_CTRL_DATA__ISET REG_ISET_WO -#define R_PAR0_CTRL_DATA__SET_VAL REG_SET_VAL_WO -#define R_PAR0_CTRL_DATA__EQL REG_EQL_WO -#define R_PAR0_CTRL_DATA__IEQL REG_IEQL_WO -#define R_PAR0_CTRL_DATA__RD REG_RD_WO -#define R_PAR0_CTRL_DATA__IRD REG_IRD_WO -#define R_PAR0_CTRL_DATA__WR REG_WR_WO -#define R_PAR0_CTRL_DATA__IWR REG_IWR_WO - -#define R_PAR0_CTRL_DATA__WRITE(addr,value) \ - (*(addr) = (value)) - -/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */ -#define R_PAR0_CTRL_DATA__FIRST 0 -#define R_PAR0_CTRL_DATA__IOFFSET 12 -#define R_PAR0_CTRL_DATA__LAST 1 -#define R_PAR0_CTRL_DATA__OFFSET 16 -#define R_PAR0_CTRL_DATA__SOFFSET 12 -/* end */ - -#define R_PAR0_CTRL_DATA__peri_int__peri_int__MASK 0x01000000U -#define R_PAR0_CTRL_DATA__oe__oe__MASK 0x00100000U -#define R_PAR0_CTRL_DATA__seli__seli__MASK 0x00080000U -#define R_PAR0_CTRL_DATA__autofd__autofd__MASK 0x00040000U -#define R_PAR0_CTRL_DATA__strb__strb__MASK 0x00020000U -#define R_PAR0_CTRL_DATA__init__init__MASK 0x00010000U -#define R_PAR0_CTRL_DATA__ecp_cmd__ecp_cmd__MASK 0x00000100U -#define R_PAR0_CTRL_DATA__data__data__MASK 0x000000ffU - -#define R_PAR0_CTRL_DATA__peri_int__MAX 0x1 -#define R_PAR0_CTRL_DATA__oe__MAX 0x1 -#define R_PAR0_CTRL_DATA__seli__MAX 0x1 -#define R_PAR0_CTRL_DATA__autofd__MAX 0x1 -#define R_PAR0_CTRL_DATA__strb__MAX 0x1 -#define R_PAR0_CTRL_DATA__init__MAX 0x1 -#define R_PAR0_CTRL_DATA__ecp_cmd__MAX 0x1 -#define R_PAR0_CTRL_DATA__data__MAX 0xff - -#define R_PAR0_CTRL_DATA__peri_int__MIN 0 -#define R_PAR0_CTRL_DATA__oe__MIN 0 -#define R_PAR0_CTRL_DATA__seli__MIN 0 -#define R_PAR0_CTRL_DATA__autofd__MIN 0 -#define R_PAR0_CTRL_DATA__strb__MIN 0 -#define R_PAR0_CTRL_DATA__init__MIN 0 -#define R_PAR0_CTRL_DATA__ecp_cmd__MIN 0 -#define R_PAR0_CTRL_DATA__data__MIN 0 - -#define R_PAR0_CTRL_DATA__peri_int__BITNR 24 -#define R_PAR0_CTRL_DATA__oe__BITNR 20 -#define R_PAR0_CTRL_DATA__seli__BITNR 19 -#define R_PAR0_CTRL_DATA__autofd__BITNR 18 -#define R_PAR0_CTRL_DATA__strb__BITNR 17 -#define R_PAR0_CTRL_DATA__init__BITNR 16 -#define R_PAR0_CTRL_DATA__ecp_cmd__BITNR 8 -#define R_PAR0_CTRL_DATA__data__BITNR 0 - -#define R_PAR0_CTRL_DATA__peri_int__peri_int__VAL REG_VAL_ENUM -#define R_PAR0_CTRL_DATA__oe__oe__VAL REG_VAL_ENUM -#define R_PAR0_CTRL_DATA__seli__seli__VAL REG_VAL_ENUM -#define R_PAR0_CTRL_DATA__autofd__autofd__VAL REG_VAL_ENUM -#define R_PAR0_CTRL_DATA__strb__strb__VAL REG_VAL_ENUM -#define R_PAR0_CTRL_DATA__init__init__VAL REG_VAL_ENUM -#define R_PAR0_CTRL_DATA__ecp_cmd__ecp_cmd__VAL REG_VAL_ENUM -#define R_PAR0_CTRL_DATA__data__data__VAL REG_VAL_VAL - -#define R_PAR0_CTRL_DATA__peri_int__peri_int__ack 1 -#define R_PAR0_CTRL_DATA__peri_int__peri_int__nop 0 -#define R_PAR0_CTRL_DATA__oe__oe__disable 0 -#define R_PAR0_CTRL_DATA__oe__oe__enable 1 -#define R_PAR0_CTRL_DATA__seli__seli__active 1 -#define R_PAR0_CTRL_DATA__seli__seli__inactive 0 -#define R_PAR0_CTRL_DATA__autofd__autofd__active 1 -#define R_PAR0_CTRL_DATA__autofd__autofd__inactive 0 -#define R_PAR0_CTRL_DATA__strb__strb__active 1 -#define R_PAR0_CTRL_DATA__strb__strb__inactive 0 -#define R_PAR0_CTRL_DATA__init__init__active 1 -#define R_PAR0_CTRL_DATA__init__init__inactive 0 -#define R_PAR0_CTRL_DATA__ecp_cmd__ecp_cmd__command 1 -#define R_PAR0_CTRL_DATA__ecp_cmd__ecp_cmd__data 0 - -#endif - -/* - * R_PAR0_DELAY - * - type: WO - * - addr: 0xb0000048 - * - group: Parallel printer port registers - */ - -#if USE_GROUP__Parallel_printer_port_registers - -#define R_PAR0_DELAY__ADDR (REG_TYPECAST_UDWORD 0xb0000048) - -#ifndef REG_NO_SHADOW -#define R_PAR0_DELAY__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_PAR0_DELAY + 0)) -#define R_PAR0_DELAY__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_PAR0_DELAY + 0)) -#else /* REG_NO_SHADOW */ -#define R_PAR0_DELAY__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_PAR0_DELAY__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_PAR0_DELAY__STYPECAST REG_STYPECAST_UDWORD -#define R_PAR0_DELAY__SVAL REG_SVAL_SHADOW -#define R_PAR0_DELAY__SVAL_I REG_SVAL_I_SHADOW -#define R_PAR0_DELAY__TYPECAST REG_TYPECAST_UDWORD -#define R_PAR0_DELAY__TYPE (REG_UDWORD) -#define R_PAR0_DELAY__GET REG_GET_WO -#define R_PAR0_DELAY__IGET REG_IGET_WO -#define R_PAR0_DELAY__SET REG_SET_WO -#define R_PAR0_DELAY__ISET REG_ISET_WO -#define R_PAR0_DELAY__SET_VAL REG_SET_VAL_WO -#define R_PAR0_DELAY__EQL REG_EQL_WO -#define R_PAR0_DELAY__IEQL REG_IEQL_WO -#define R_PAR0_DELAY__RD REG_RD_WO -#define R_PAR0_DELAY__IRD REG_IRD_WO -#define R_PAR0_DELAY__WR REG_WR_WO -#define R_PAR0_DELAY__IWR REG_IWR_WO - -#define R_PAR0_DELAY__WRITE(addr,value) \ - (*(addr) = (value)) - -/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */ -#define R_PAR0_DELAY__FIRST 0 -#define R_PAR0_DELAY__IOFFSET 12 -#define R_PAR0_DELAY__LAST 1 -#define R_PAR0_DELAY__OFFSET 16 -#define R_PAR0_DELAY__SOFFSET 12 -/* end */ - -#define R_PAR0_DELAY__fine_hold__fine_hold__MASK 0x00e00000U -#define R_PAR0_DELAY__hold__hold__MASK 0x001f0000U -#define R_PAR0_DELAY__fine_strb__fine_strb__MASK 0x0000e000U -#define R_PAR0_DELAY__strobe__strobe__MASK 0x00001f00U -#define R_PAR0_DELAY__fine_setup__fine_setup__MASK 0x000000e0U -#define R_PAR0_DELAY__setup__setup__MASK 0x0000001fU - -#define R_PAR0_DELAY__fine_hold__MAX 0x7 -#define R_PAR0_DELAY__hold__MAX 0x1f -#define R_PAR0_DELAY__fine_strb__MAX 0x7 -#define R_PAR0_DELAY__strobe__MAX 0x1f -#define R_PAR0_DELAY__fine_setup__MAX 0x7 -#define R_PAR0_DELAY__setup__MAX 0x1f - -#define R_PAR0_DELAY__fine_hold__MIN 0 -#define R_PAR0_DELAY__hold__MIN 0 -#define R_PAR0_DELAY__fine_strb__MIN 0 -#define R_PAR0_DELAY__strobe__MIN 0 -#define R_PAR0_DELAY__fine_setup__MIN 0 -#define R_PAR0_DELAY__setup__MIN 0 - -#define R_PAR0_DELAY__fine_hold__BITNR 21 -#define R_PAR0_DELAY__hold__BITNR 16 -#define R_PAR0_DELAY__fine_strb__BITNR 13 -#define R_PAR0_DELAY__strobe__BITNR 8 -#define R_PAR0_DELAY__fine_setup__BITNR 5 -#define R_PAR0_DELAY__setup__BITNR 0 - -#define R_PAR0_DELAY__fine_hold__fine_hold__VAL REG_VAL_VAL -#define R_PAR0_DELAY__hold__hold__VAL REG_VAL_VAL -#define R_PAR0_DELAY__fine_strb__fine_strb__VAL REG_VAL_VAL -#define R_PAR0_DELAY__strobe__strobe__VAL REG_VAL_VAL -#define R_PAR0_DELAY__fine_setup__fine_setup__VAL REG_VAL_VAL -#define R_PAR0_DELAY__setup__setup__VAL REG_VAL_VAL - - -#endif - -/* - * R_PAR0_STATUS - * - type: RO - * - addr: 0xb0000042 - * - group: Parallel printer port registers - */ - -#if USE_GROUP__Parallel_printer_port_registers - -#define R_PAR0_STATUS__ADDR (REG_TYPECAST_UWORD 0xb0000042) -#define R_PAR0_STATUS__SVAL REG_SVAL_SHADOW -#define R_PAR0_STATUS__SVAL_I REG_SVAL_I_SHADOW -#define R_PAR0_STATUS__TYPECAST REG_TYPECAST_UWORD -#define R_PAR0_STATUS__TYPE (REG_UWORD) -#define R_PAR0_STATUS__GET REG_GET_RO -#define R_PAR0_STATUS__IGET REG_IGET_RO -#define R_PAR0_STATUS__SET REG_SET_RO -#define R_PAR0_STATUS__ISET REG_ISET_RO -#define R_PAR0_STATUS__SET_VAL REG_SET_VAL_RO -#define R_PAR0_STATUS__EQL REG_EQL_RO -#define R_PAR0_STATUS__IEQL REG_IEQL_RO -#define R_PAR0_STATUS__RD REG_RD_RO -#define R_PAR0_STATUS__IRD REG_IRD_RO -#define R_PAR0_STATUS__WR REG_WR_RO -#define R_PAR0_STATUS__IWR REG_IWR_RO - -#define R_PAR0_STATUS__READ(addr) \ - (*(addr)) - -#define R_PAR0_STATUS__mode__mode__MASK 0x0000e000U -#define R_PAR0_STATUS__perr__perr__MASK 0x00001000U -#define R_PAR0_STATUS__ack__ack__MASK 0x00000800U -#define R_PAR0_STATUS__busy__busy__MASK 0x00000400U -#define R_PAR0_STATUS__fault__fault__MASK 0x00000200U -#define R_PAR0_STATUS__sel__sel__MASK 0x00000100U -#define R_PAR0_STATUS__ext_mode__ext_mode__MASK 0x00000080U -#define R_PAR0_STATUS__ecp_16__ecp_16__MASK 0x00000040U -#define R_PAR0_STATUS__tr_rdy__tr_rdy__MASK 0x00000002U -#define R_PAR0_STATUS__dav__dav__MASK 0x00000001U - -#define R_PAR0_STATUS__mode__MAX 0x7 -#define R_PAR0_STATUS__perr__MAX 0x1 -#define R_PAR0_STATUS__ack__MAX 0x1 -#define R_PAR0_STATUS__busy__MAX 0x1 -#define R_PAR0_STATUS__fault__MAX 0x1 -#define R_PAR0_STATUS__sel__MAX 0x1 -#define R_PAR0_STATUS__ext_mode__MAX 0x1 -#define R_PAR0_STATUS__ecp_16__MAX 0x1 -#define R_PAR0_STATUS__tr_rdy__MAX 0x1 -#define R_PAR0_STATUS__dav__MAX 0x1 - -#define R_PAR0_STATUS__mode__MIN 0 -#define R_PAR0_STATUS__perr__MIN 0 -#define R_PAR0_STATUS__ack__MIN 0 -#define R_PAR0_STATUS__busy__MIN 0 -#define R_PAR0_STATUS__fault__MIN 0 -#define R_PAR0_STATUS__sel__MIN 0 -#define R_PAR0_STATUS__ext_mode__MIN 0 -#define R_PAR0_STATUS__ecp_16__MIN 0 -#define R_PAR0_STATUS__tr_rdy__MIN 0 -#define R_PAR0_STATUS__dav__MIN 0 - -#define R_PAR0_STATUS__mode__BITNR 13 -#define R_PAR0_STATUS__perr__BITNR 12 -#define R_PAR0_STATUS__ack__BITNR 11 -#define R_PAR0_STATUS__busy__BITNR 10 -#define R_PAR0_STATUS__fault__BITNR 9 -#define R_PAR0_STATUS__sel__BITNR 8 -#define R_PAR0_STATUS__ext_mode__BITNR 7 -#define R_PAR0_STATUS__ecp_16__BITNR 6 -#define R_PAR0_STATUS__tr_rdy__BITNR 1 -#define R_PAR0_STATUS__dav__BITNR 0 - -#define R_PAR0_STATUS__mode__mode__VAL REG_VAL_ENUM -#define R_PAR0_STATUS__perr__perr__VAL REG_VAL_ENUM -#define R_PAR0_STATUS__ack__ack__VAL REG_VAL_ENUM -#define R_PAR0_STATUS__busy__busy__VAL REG_VAL_ENUM -#define R_PAR0_STATUS__fault__fault__VAL REG_VAL_ENUM -#define R_PAR0_STATUS__sel__sel__VAL REG_VAL_ENUM -#define R_PAR0_STATUS__ext_mode__ext_mode__VAL REG_VAL_ENUM -#define R_PAR0_STATUS__ecp_16__ecp_16__VAL REG_VAL_ENUM -#define R_PAR0_STATUS__tr_rdy__tr_rdy__VAL REG_VAL_ENUM -#define R_PAR0_STATUS__dav__dav__VAL REG_VAL_ENUM - -#define R_PAR0_STATUS__mode__mode__byte 4 -#define R_PAR0_STATUS__mode__mode__centronics 1 -#define R_PAR0_STATUS__mode__mode__ecp_fwd 5 -#define R_PAR0_STATUS__mode__mode__ecp_rev 6 -#define R_PAR0_STATUS__mode__mode__epp_rd 0 -#define R_PAR0_STATUS__mode__mode__epp_wr1 5 -#define R_PAR0_STATUS__mode__mode__epp_wr2 6 -#define R_PAR0_STATUS__mode__mode__epp_wr3 7 -#define R_PAR0_STATUS__mode__mode__fastbyte 2 -#define R_PAR0_STATUS__mode__mode__manual 0 -#define R_PAR0_STATUS__mode__mode__nibble 3 -#define R_PAR0_STATUS__mode__mode__off 7 -#define R_PAR0_STATUS__perr__perr__active 1 -#define R_PAR0_STATUS__perr__perr__inactive 0 -#define R_PAR0_STATUS__ack__ack__active 0 -#define R_PAR0_STATUS__ack__ack__inactive 1 -#define R_PAR0_STATUS__busy__busy__active 1 -#define R_PAR0_STATUS__busy__busy__inactive 0 -#define R_PAR0_STATUS__fault__fault__active 0 -#define R_PAR0_STATUS__fault__fault__inactive 1 -#define R_PAR0_STATUS__sel__sel__active 1 -#define R_PAR0_STATUS__sel__sel__inactive 0 -#define R_PAR0_STATUS__ext_mode__ext_mode__disable 0 -#define R_PAR0_STATUS__ext_mode__ext_mode__enable 1 -#define R_PAR0_STATUS__ecp_16__ecp_16__active 1 -#define R_PAR0_STATUS__ecp_16__ecp_16__inactive 0 -#define R_PAR0_STATUS__tr_rdy__tr_rdy__busy 0 -#define R_PAR0_STATUS__tr_rdy__tr_rdy__ready 1 -#define R_PAR0_STATUS__dav__dav__data 1 -#define R_PAR0_STATUS__dav__dav__nodata 0 - -#endif - -/* - * R_PAR0_STATUS_DATA - * - type: RO - * - addr: 0xb0000040 - * - group: Parallel printer port registers - */ - -#if USE_GROUP__Parallel_printer_port_registers - -#define R_PAR0_STATUS_DATA__ADDR (REG_TYPECAST_UDWORD 0xb0000040) -#define R_PAR0_STATUS_DATA__SVAL REG_SVAL_SHADOW -#define R_PAR0_STATUS_DATA__SVAL_I REG_SVAL_I_SHADOW -#define R_PAR0_STATUS_DATA__TYPECAST REG_TYPECAST_UDWORD -#define R_PAR0_STATUS_DATA__TYPE (REG_UDWORD) -#define R_PAR0_STATUS_DATA__GET REG_GET_RO -#define R_PAR0_STATUS_DATA__IGET REG_IGET_RO -#define R_PAR0_STATUS_DATA__SET REG_SET_RO -#define R_PAR0_STATUS_DATA__ISET REG_ISET_RO -#define R_PAR0_STATUS_DATA__SET_VAL REG_SET_VAL_RO -#define R_PAR0_STATUS_DATA__EQL REG_EQL_RO -#define R_PAR0_STATUS_DATA__IEQL REG_IEQL_RO -#define R_PAR0_STATUS_DATA__RD REG_RD_RO -#define R_PAR0_STATUS_DATA__IRD REG_IRD_RO -#define R_PAR0_STATUS_DATA__WR REG_WR_RO -#define R_PAR0_STATUS_DATA__IWR REG_IWR_RO - -#define R_PAR0_STATUS_DATA__READ(addr) \ - (*(addr)) - -/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */ -#define R_PAR0_STATUS_DATA__FIRST 0 -#define R_PAR0_STATUS_DATA__LAST 1 -#define R_PAR0_STATUS_DATA__OFFSET 16 -/* end */ - -#define R_PAR0_STATUS_DATA__mode__mode__MASK 0xe0000000U -#define R_PAR0_STATUS_DATA__perr__perr__MASK 0x10000000U -#define R_PAR0_STATUS_DATA__ack__ack__MASK 0x08000000U -#define R_PAR0_STATUS_DATA__busy__busy__MASK 0x04000000U -#define R_PAR0_STATUS_DATA__fault__fault__MASK 0x02000000U -#define R_PAR0_STATUS_DATA__sel__sel__MASK 0x01000000U -#define R_PAR0_STATUS_DATA__ext_mode__ext_mode__MASK 0x00800000U -#define R_PAR0_STATUS_DATA__ecp_16__ecp_16__MASK 0x00400000U -#define R_PAR0_STATUS_DATA__tr_rdy__tr_rdy__MASK 0x00020000U -#define R_PAR0_STATUS_DATA__dav__dav__MASK 0x00010000U -#define R_PAR0_STATUS_DATA__ecp_cmd__ecp_cmd__MASK 0x00000100U -#define R_PAR0_STATUS_DATA__data__data__MASK 0x000000ffU - -#define R_PAR0_STATUS_DATA__mode__MAX 0x7 -#define R_PAR0_STATUS_DATA__perr__MAX 0x1 -#define R_PAR0_STATUS_DATA__ack__MAX 0x1 -#define R_PAR0_STATUS_DATA__busy__MAX 0x1 -#define R_PAR0_STATUS_DATA__fault__MAX 0x1 -#define R_PAR0_STATUS_DATA__sel__MAX 0x1 -#define R_PAR0_STATUS_DATA__ext_mode__MAX 0x1 -#define R_PAR0_STATUS_DATA__ecp_16__MAX 0x1 -#define R_PAR0_STATUS_DATA__tr_rdy__MAX 0x1 -#define R_PAR0_STATUS_DATA__dav__MAX 0x1 -#define R_PAR0_STATUS_DATA__ecp_cmd__MAX 0x1 -#define R_PAR0_STATUS_DATA__data__MAX 0xff - -#define R_PAR0_STATUS_DATA__mode__MIN 0 -#define R_PAR0_STATUS_DATA__perr__MIN 0 -#define R_PAR0_STATUS_DATA__ack__MIN 0 -#define R_PAR0_STATUS_DATA__busy__MIN 0 -#define R_PAR0_STATUS_DATA__fault__MIN 0 -#define R_PAR0_STATUS_DATA__sel__MIN 0 -#define R_PAR0_STATUS_DATA__ext_mode__MIN 0 -#define R_PAR0_STATUS_DATA__ecp_16__MIN 0 -#define R_PAR0_STATUS_DATA__tr_rdy__MIN 0 -#define R_PAR0_STATUS_DATA__dav__MIN 0 -#define R_PAR0_STATUS_DATA__ecp_cmd__MIN 0 -#define R_PAR0_STATUS_DATA__data__MIN 0 - -#define R_PAR0_STATUS_DATA__mode__BITNR 29 -#define R_PAR0_STATUS_DATA__perr__BITNR 28 -#define R_PAR0_STATUS_DATA__ack__BITNR 27 -#define R_PAR0_STATUS_DATA__busy__BITNR 26 -#define R_PAR0_STATUS_DATA__fault__BITNR 25 -#define R_PAR0_STATUS_DATA__sel__BITNR 24 -#define R_PAR0_STATUS_DATA__ext_mode__BITNR 23 -#define R_PAR0_STATUS_DATA__ecp_16__BITNR 22 -#define R_PAR0_STATUS_DATA__tr_rdy__BITNR 17 -#define R_PAR0_STATUS_DATA__dav__BITNR 16 -#define R_PAR0_STATUS_DATA__ecp_cmd__BITNR 8 -#define R_PAR0_STATUS_DATA__data__BITNR 0 - -#define R_PAR0_STATUS_DATA__mode__mode__VAL REG_VAL_ENUM -#define R_PAR0_STATUS_DATA__perr__perr__VAL REG_VAL_ENUM -#define R_PAR0_STATUS_DATA__ack__ack__VAL REG_VAL_ENUM -#define R_PAR0_STATUS_DATA__busy__busy__VAL REG_VAL_ENUM -#define R_PAR0_STATUS_DATA__fault__fault__VAL REG_VAL_ENUM -#define R_PAR0_STATUS_DATA__sel__sel__VAL REG_VAL_ENUM -#define R_PAR0_STATUS_DATA__ext_mode__ext_mode__VAL REG_VAL_ENUM -#define R_PAR0_STATUS_DATA__ecp_16__ecp_16__VAL REG_VAL_ENUM -#define R_PAR0_STATUS_DATA__tr_rdy__tr_rdy__VAL REG_VAL_ENUM -#define R_PAR0_STATUS_DATA__dav__dav__VAL REG_VAL_ENUM -#define R_PAR0_STATUS_DATA__ecp_cmd__ecp_cmd__VAL REG_VAL_ENUM -#define R_PAR0_STATUS_DATA__data__data__VAL REG_VAL_VAL - -#define R_PAR0_STATUS_DATA__mode__mode__byte 4 -#define R_PAR0_STATUS_DATA__mode__mode__centronics 1 -#define R_PAR0_STATUS_DATA__mode__mode__ecp_fwd 5 -#define R_PAR0_STATUS_DATA__mode__mode__ecp_rev 6 -#define R_PAR0_STATUS_DATA__mode__mode__epp_rd 0 -#define R_PAR0_STATUS_DATA__mode__mode__epp_wr1 5 -#define R_PAR0_STATUS_DATA__mode__mode__epp_wr2 6 -#define R_PAR0_STATUS_DATA__mode__mode__epp_wr3 7 -#define R_PAR0_STATUS_DATA__mode__mode__fastbyte 2 -#define R_PAR0_STATUS_DATA__mode__mode__manual 0 -#define R_PAR0_STATUS_DATA__mode__mode__nibble 3 -#define R_PAR0_STATUS_DATA__mode__mode__off 7 -#define R_PAR0_STATUS_DATA__perr__perr__active 1 -#define R_PAR0_STATUS_DATA__perr__perr__inactive 0 -#define R_PAR0_STATUS_DATA__ack__ack__active 0 -#define R_PAR0_STATUS_DATA__ack__ack__inactive 1 -#define R_PAR0_STATUS_DATA__busy__busy__active 1 -#define R_PAR0_STATUS_DATA__busy__busy__inactive 0 -#define R_PAR0_STATUS_DATA__fault__fault__active 0 -#define R_PAR0_STATUS_DATA__fault__fault__inactive 1 -#define R_PAR0_STATUS_DATA__sel__sel__active 1 -#define R_PAR0_STATUS_DATA__sel__sel__inactive 0 -#define R_PAR0_STATUS_DATA__ext_mode__ext_mode__disable 0 -#define R_PAR0_STATUS_DATA__ext_mode__ext_mode__enable 1 -#define R_PAR0_STATUS_DATA__ecp_16__ecp_16__active 1 -#define R_PAR0_STATUS_DATA__ecp_16__ecp_16__inactive 0 -#define R_PAR0_STATUS_DATA__tr_rdy__tr_rdy__busy 0 -#define R_PAR0_STATUS_DATA__tr_rdy__tr_rdy__ready 1 -#define R_PAR0_STATUS_DATA__dav__dav__data 1 -#define R_PAR0_STATUS_DATA__dav__dav__nodata 0 -#define R_PAR0_STATUS_DATA__ecp_cmd__ecp_cmd__command 1 -#define R_PAR0_STATUS_DATA__ecp_cmd__ecp_cmd__data 0 - -#endif - -/* - * R_PAR1_CONFIG - * - type: WO - * - addr: 0xb0000054 - * - group: Parallel printer port registers - */ - -#if USE_GROUP__Parallel_printer_port_registers - -#define R_PAR1_CONFIG__ADDR (REG_TYPECAST_UDWORD 0xb0000054) - -#ifndef REG_NO_SHADOW -#define R_PAR1_CONFIG__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_PAR1_CONFIG + 0)) -#define R_PAR1_CONFIG__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_PAR1_CONFIG + 0)) -#else /* REG_NO_SHADOW */ -#define R_PAR1_CONFIG__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_PAR1_CONFIG__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_PAR1_CONFIG__STYPECAST REG_STYPECAST_UDWORD -#define R_PAR1_CONFIG__SVAL REG_SVAL_SHADOW -#define R_PAR1_CONFIG__SVAL_I REG_SVAL_I_SHADOW -#define R_PAR1_CONFIG__TYPECAST REG_TYPECAST_UDWORD -#define R_PAR1_CONFIG__TYPE (REG_UDWORD) -#define R_PAR1_CONFIG__GET REG_GET_WO -#define R_PAR1_CONFIG__IGET REG_IGET_WO -#define R_PAR1_CONFIG__SET REG_SET_WO -#define R_PAR1_CONFIG__ISET REG_ISET_WO -#define R_PAR1_CONFIG__SET_VAL REG_SET_VAL_WO -#define R_PAR1_CONFIG__EQL REG_EQL_WO -#define R_PAR1_CONFIG__IEQL REG_IEQL_WO -#define R_PAR1_CONFIG__RD REG_RD_WO -#define R_PAR1_CONFIG__IRD REG_IRD_WO -#define R_PAR1_CONFIG__WR REG_WR_WO -#define R_PAR1_CONFIG__IWR REG_IWR_WO - -#define R_PAR1_CONFIG__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_PAR1_CONFIG__ioe__ioe__MASK 0x02000000U -#define R_PAR1_CONFIG__iseli__iseli__MASK 0x01000000U -#define R_PAR1_CONFIG__iautofd__iautofd__MASK 0x00800000U -#define R_PAR1_CONFIG__istrb__istrb__MASK 0x00400000U -#define R_PAR1_CONFIG__iinit__iinit__MASK 0x00200000U -#define R_PAR1_CONFIG__iperr__iperr__MASK 0x00100000U -#define R_PAR1_CONFIG__iack__iack__MASK 0x00080000U -#define R_PAR1_CONFIG__ibusy__ibusy__MASK 0x00040000U -#define R_PAR1_CONFIG__ifault__ifault__MASK 0x00020000U -#define R_PAR1_CONFIG__isel__isel__MASK 0x00010000U -#define R_PAR1_CONFIG__ext_mode__ext_mode__MASK 0x00000800U -#define R_PAR1_CONFIG__dma__dma__MASK 0x00000200U -#define R_PAR1_CONFIG__rle_in__rle_in__MASK 0x00000100U -#define R_PAR1_CONFIG__rle_out__rle_out__MASK 0x00000080U -#define R_PAR1_CONFIG__enable__enable__MASK 0x00000040U -#define R_PAR1_CONFIG__force__force__MASK 0x00000020U -#define R_PAR1_CONFIG__ign_ack__ign_ack__MASK 0x00000010U -#define R_PAR1_CONFIG__oe_ack__oe_ack__MASK 0x00000008U -#define R_PAR1_CONFIG__epp_addr_data__epp_addr_data__MASK 0x00000008U -#define R_PAR1_CONFIG__oe_ack__epp_addr_data__MASK 0x00000008U -#define R_PAR1_CONFIG__mode__mode__MASK 0x00000007U - -#define R_PAR1_CONFIG__ioe__MAX 0x1 -#define R_PAR1_CONFIG__iseli__MAX 0x1 -#define R_PAR1_CONFIG__iautofd__MAX 0x1 -#define R_PAR1_CONFIG__istrb__MAX 0x1 -#define R_PAR1_CONFIG__iinit__MAX 0x1 -#define R_PAR1_CONFIG__iperr__MAX 0x1 -#define R_PAR1_CONFIG__iack__MAX 0x1 -#define R_PAR1_CONFIG__ibusy__MAX 0x1 -#define R_PAR1_CONFIG__ifault__MAX 0x1 -#define R_PAR1_CONFIG__isel__MAX 0x1 -#define R_PAR1_CONFIG__ext_mode__MAX 0x1 -#define R_PAR1_CONFIG__dma__MAX 0x1 -#define R_PAR1_CONFIG__rle_in__MAX 0x1 -#define R_PAR1_CONFIG__rle_out__MAX 0x1 -#define R_PAR1_CONFIG__enable__MAX 0x1 -#define R_PAR1_CONFIG__force__MAX 0x1 -#define R_PAR1_CONFIG__ign_ack__MAX 0x1 -#define R_PAR1_CONFIG__oe_ack__MAX 0x1 -#define R_PAR1_CONFIG__epp_addr_data__MAX 0x1 -#define R_PAR1_CONFIG__mode__MAX 0x7 - -#define R_PAR1_CONFIG__ioe__MIN 0 -#define R_PAR1_CONFIG__iseli__MIN 0 -#define R_PAR1_CONFIG__iautofd__MIN 0 -#define R_PAR1_CONFIG__istrb__MIN 0 -#define R_PAR1_CONFIG__iinit__MIN 0 -#define R_PAR1_CONFIG__iperr__MIN 0 -#define R_PAR1_CONFIG__iack__MIN 0 -#define R_PAR1_CONFIG__ibusy__MIN 0 -#define R_PAR1_CONFIG__ifault__MIN 0 -#define R_PAR1_CONFIG__isel__MIN 0 -#define R_PAR1_CONFIG__ext_mode__MIN 0 -#define R_PAR1_CONFIG__dma__MIN 0 -#define R_PAR1_CONFIG__rle_in__MIN 0 -#define R_PAR1_CONFIG__rle_out__MIN 0 -#define R_PAR1_CONFIG__enable__MIN 0 -#define R_PAR1_CONFIG__force__MIN 0 -#define R_PAR1_CONFIG__ign_ack__MIN 0 -#define R_PAR1_CONFIG__oe_ack__MIN 0 -#define R_PAR1_CONFIG__epp_addr_data__MIN 0 -#define R_PAR1_CONFIG__mode__MIN 0 - -#define R_PAR1_CONFIG__ioe__BITNR 25 -#define R_PAR1_CONFIG__iseli__BITNR 24 -#define R_PAR1_CONFIG__iautofd__BITNR 23 -#define R_PAR1_CONFIG__istrb__BITNR 22 -#define R_PAR1_CONFIG__iinit__BITNR 21 -#define R_PAR1_CONFIG__iperr__BITNR 20 -#define R_PAR1_CONFIG__iack__BITNR 19 -#define R_PAR1_CONFIG__ibusy__BITNR 18 -#define R_PAR1_CONFIG__ifault__BITNR 17 -#define R_PAR1_CONFIG__isel__BITNR 16 -#define R_PAR1_CONFIG__ext_mode__BITNR 11 -#define R_PAR1_CONFIG__dma__BITNR 9 -#define R_PAR1_CONFIG__rle_in__BITNR 8 -#define R_PAR1_CONFIG__rle_out__BITNR 7 -#define R_PAR1_CONFIG__enable__BITNR 6 -#define R_PAR1_CONFIG__force__BITNR 5 -#define R_PAR1_CONFIG__ign_ack__BITNR 4 -#define R_PAR1_CONFIG__oe_ack__BITNR 3 -#define R_PAR1_CONFIG__epp_addr_data__BITNR 3 -#define R_PAR1_CONFIG__mode__BITNR 0 - -#define R_PAR1_CONFIG__ioe__ioe__VAL REG_VAL_ENUM -#define R_PAR1_CONFIG__iseli__iseli__VAL REG_VAL_ENUM -#define R_PAR1_CONFIG__iautofd__iautofd__VAL REG_VAL_ENUM -#define R_PAR1_CONFIG__istrb__istrb__VAL REG_VAL_ENUM -#define R_PAR1_CONFIG__iinit__iinit__VAL REG_VAL_ENUM -#define R_PAR1_CONFIG__iperr__iperr__VAL REG_VAL_ENUM -#define R_PAR1_CONFIG__iack__iack__VAL REG_VAL_ENUM -#define R_PAR1_CONFIG__ibusy__ibusy__VAL REG_VAL_ENUM -#define R_PAR1_CONFIG__ifault__ifault__VAL REG_VAL_ENUM -#define R_PAR1_CONFIG__isel__isel__VAL REG_VAL_ENUM -#define R_PAR1_CONFIG__ext_mode__ext_mode__VAL REG_VAL_ENUM -#define R_PAR1_CONFIG__dma__dma__VAL REG_VAL_ENUM -#define R_PAR1_CONFIG__rle_in__rle_in__VAL REG_VAL_ENUM -#define R_PAR1_CONFIG__rle_out__rle_out__VAL REG_VAL_ENUM -#define R_PAR1_CONFIG__enable__enable__VAL REG_VAL_ENUM -#define R_PAR1_CONFIG__force__force__VAL REG_VAL_ENUM -#define R_PAR1_CONFIG__ign_ack__ign_ack__VAL REG_VAL_ENUM -#define R_PAR1_CONFIG__oe_ack__oe_ack__VAL REG_VAL_ENUM -#define R_PAR1_CONFIG__epp_addr_data__epp_addr_data__VAL REG_VAL_ENUM -#define R_PAR1_CONFIG__oe_ack__epp_addr_data__VAL REG_VAL_ENUM -#define R_PAR1_CONFIG__mode__mode__VAL REG_VAL_ENUM - -#define R_PAR1_CONFIG__ioe__ioe__inv 1 -#define R_PAR1_CONFIG__ioe__ioe__noninv 0 -#define R_PAR1_CONFIG__iseli__iseli__inv 1 -#define R_PAR1_CONFIG__iseli__iseli__noninv 0 -#define R_PAR1_CONFIG__iautofd__iautofd__inv 1 -#define R_PAR1_CONFIG__iautofd__iautofd__noninv 0 -#define R_PAR1_CONFIG__istrb__istrb__inv 1 -#define R_PAR1_CONFIG__istrb__istrb__noninv 0 -#define R_PAR1_CONFIG__iinit__iinit__inv 1 -#define R_PAR1_CONFIG__iinit__iinit__noninv 0 -#define R_PAR1_CONFIG__iperr__iperr__inv 1 -#define R_PAR1_CONFIG__iperr__iperr__noninv 0 -#define R_PAR1_CONFIG__iack__iack__inv 1 -#define R_PAR1_CONFIG__iack__iack__noninv 0 -#define R_PAR1_CONFIG__ibusy__ibusy__inv 1 -#define R_PAR1_CONFIG__ibusy__ibusy__noninv 0 -#define R_PAR1_CONFIG__ifault__ifault__inv 1 -#define R_PAR1_CONFIG__ifault__ifault__noninv 0 -#define R_PAR1_CONFIG__isel__isel__inv 1 -#define R_PAR1_CONFIG__isel__isel__noninv 0 -#define R_PAR1_CONFIG__ext_mode__ext_mode__disable 0 -#define R_PAR1_CONFIG__ext_mode__ext_mode__enable 1 -#define R_PAR1_CONFIG__dma__dma__disable 0 -#define R_PAR1_CONFIG__dma__dma__enable 1 -#define R_PAR1_CONFIG__rle_in__rle_in__disable 0 -#define R_PAR1_CONFIG__rle_in__rle_in__enable 1 -#define R_PAR1_CONFIG__rle_out__rle_out__disable 0 -#define R_PAR1_CONFIG__rle_out__rle_out__enable 1 -#define R_PAR1_CONFIG__enable__enable__on 1 -#define R_PAR1_CONFIG__enable__enable__reset 0 -#define R_PAR1_CONFIG__force__force__off 0 -#define R_PAR1_CONFIG__force__force__on 1 -#define R_PAR1_CONFIG__ign_ack__ign_ack__ignore 1 -#define R_PAR1_CONFIG__ign_ack__ign_ack__wait 0 -#define R_PAR1_CONFIG__oe_ack__oe_ack__dont_wait 0 -#define R_PAR1_CONFIG__oe_ack__oe_ack__epp_addr 1 -#define R_PAR1_CONFIG__oe_ack__oe_ack__epp_data 0 -#define R_PAR1_CONFIG__oe_ack__oe_ack__wait_oe 1 -#define R_PAR1_CONFIG__epp_addr_data__epp_addr_data__dont_wait 0 -#define R_PAR1_CONFIG__epp_addr_data__epp_addr_data__epp_addr 1 -#define R_PAR1_CONFIG__epp_addr_data__epp_addr_data__epp_data 0 -#define R_PAR1_CONFIG__epp_addr_data__epp_addr_data__wait_oe 1 -#define R_PAR1_CONFIG__mode__mode__byte 4 -#define R_PAR1_CONFIG__mode__mode__centronics 1 -#define R_PAR1_CONFIG__mode__mode__ecp_fwd 5 -#define R_PAR1_CONFIG__mode__mode__ecp_rev 6 -#define R_PAR1_CONFIG__mode__mode__epp_rd 0 -#define R_PAR1_CONFIG__mode__mode__epp_wr1 5 -#define R_PAR1_CONFIG__mode__mode__epp_wr2 6 -#define R_PAR1_CONFIG__mode__mode__epp_wr3 7 -#define R_PAR1_CONFIG__mode__mode__fastbyte 2 -#define R_PAR1_CONFIG__mode__mode__manual 0 -#define R_PAR1_CONFIG__mode__mode__nibble 3 -#define R_PAR1_CONFIG__mode__mode__off 7 - -#endif - -/* - * R_PAR1_CTRL - * - type: WO - * - addr: 0xb0000052 - * - group: Parallel printer port registers - */ - -#if USE_GROUP__Parallel_printer_port_registers - -#define R_PAR1_CTRL__ADDR (REG_TYPECAST_BYTE 0xb0000052) - -#ifndef REG_NO_SHADOW -#define R_PAR1_CTRL__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_PAR1_CTRL_DATA + 2)) -#define R_PAR1_CTRL__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_PAR1_CTRL_DATA + 2)) -#else /* REG_NO_SHADOW */ -#define R_PAR1_CTRL__SADDR (REG_STYPECAST_BYTE (®_shadow__hwregs)) -#define R_PAR1_CTRL__IADDR (REG_STYPECAST_BYTE (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_PAR1_CTRL__STYPECAST REG_STYPECAST_BYTE -#define R_PAR1_CTRL__SVAL REG_SVAL_SHADOW -#define R_PAR1_CTRL__SVAL_I REG_SVAL_I_SHADOW -#define R_PAR1_CTRL__TYPECAST REG_TYPECAST_BYTE -#define R_PAR1_CTRL__TYPE (REG_BYTE) -#define R_PAR1_CTRL__GET REG_GET_WO -#define R_PAR1_CTRL__IGET REG_IGET_WO -#define R_PAR1_CTRL__SET REG_SET_WO -#define R_PAR1_CTRL__ISET REG_ISET_WO -#define R_PAR1_CTRL__SET_VAL REG_SET_VAL_WO -#define R_PAR1_CTRL__EQL REG_EQL_WO -#define R_PAR1_CTRL__IEQL REG_IEQL_WO -#define R_PAR1_CTRL__RD REG_RD_WO -#define R_PAR1_CTRL__IRD REG_IRD_WO -#define R_PAR1_CTRL__WR REG_WR_WO -#define R_PAR1_CTRL__IWR REG_IWR_WO - -#define R_PAR1_CTRL__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_PAR1_CTRL__ctrl__ctrl__MASK 0x0000001fU - -#define R_PAR1_CTRL__ctrl__MAX 31 - -#define R_PAR1_CTRL__ctrl__MIN 0 - -#define R_PAR1_CTRL__ctrl__BITNR 0 - -#define R_PAR1_CTRL__ctrl__ctrl__VAL REG_VAL_VAL - - -#endif - -/* - * R_PAR1_CTRL_DATA - * - type: WO - * - addr: 0xb0000050 - * - group: Parallel printer port registers - */ - -#if USE_GROUP__Parallel_printer_port_registers - -#define R_PAR1_CTRL_DATA__ADDR (REG_TYPECAST_UDWORD 0xb0000050) - -#ifndef REG_NO_SHADOW -#define R_PAR1_CTRL_DATA__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_PAR1_CTRL_DATA + 0)) -#define R_PAR1_CTRL_DATA__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_PAR1_CTRL_DATA + 0)) -#else /* REG_NO_SHADOW */ -#define R_PAR1_CTRL_DATA__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_PAR1_CTRL_DATA__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_PAR1_CTRL_DATA__STYPECAST REG_STYPECAST_UDWORD -#define R_PAR1_CTRL_DATA__SVAL REG_SVAL_SHADOW -#define R_PAR1_CTRL_DATA__SVAL_I REG_SVAL_I_SHADOW -#define R_PAR1_CTRL_DATA__TYPECAST REG_TYPECAST_UDWORD -#define R_PAR1_CTRL_DATA__TYPE (REG_UDWORD) -#define R_PAR1_CTRL_DATA__GET REG_GET_WO -#define R_PAR1_CTRL_DATA__IGET REG_IGET_WO -#define R_PAR1_CTRL_DATA__SET REG_SET_WO -#define R_PAR1_CTRL_DATA__ISET REG_ISET_WO -#define R_PAR1_CTRL_DATA__SET_VAL REG_SET_VAL_WO -#define R_PAR1_CTRL_DATA__EQL REG_EQL_WO -#define R_PAR1_CTRL_DATA__IEQL REG_IEQL_WO -#define R_PAR1_CTRL_DATA__RD REG_RD_WO -#define R_PAR1_CTRL_DATA__IRD REG_IRD_WO -#define R_PAR1_CTRL_DATA__WR REG_WR_WO -#define R_PAR1_CTRL_DATA__IWR REG_IWR_WO - -#define R_PAR1_CTRL_DATA__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_PAR1_CTRL_DATA__peri_int__peri_int__MASK 0x01000000U -#define R_PAR1_CTRL_DATA__oe__oe__MASK 0x00100000U -#define R_PAR1_CTRL_DATA__seli__seli__MASK 0x00080000U -#define R_PAR1_CTRL_DATA__autofd__autofd__MASK 0x00040000U -#define R_PAR1_CTRL_DATA__strb__strb__MASK 0x00020000U -#define R_PAR1_CTRL_DATA__init__init__MASK 0x00010000U -#define R_PAR1_CTRL_DATA__ecp_cmd__ecp_cmd__MASK 0x00000100U -#define R_PAR1_CTRL_DATA__data__data__MASK 0x000000ffU - -#define R_PAR1_CTRL_DATA__peri_int__MAX 0x1 -#define R_PAR1_CTRL_DATA__oe__MAX 0x1 -#define R_PAR1_CTRL_DATA__seli__MAX 0x1 -#define R_PAR1_CTRL_DATA__autofd__MAX 0x1 -#define R_PAR1_CTRL_DATA__strb__MAX 0x1 -#define R_PAR1_CTRL_DATA__init__MAX 0x1 -#define R_PAR1_CTRL_DATA__ecp_cmd__MAX 0x1 -#define R_PAR1_CTRL_DATA__data__MAX 0xff - -#define R_PAR1_CTRL_DATA__peri_int__MIN 0 -#define R_PAR1_CTRL_DATA__oe__MIN 0 -#define R_PAR1_CTRL_DATA__seli__MIN 0 -#define R_PAR1_CTRL_DATA__autofd__MIN 0 -#define R_PAR1_CTRL_DATA__strb__MIN 0 -#define R_PAR1_CTRL_DATA__init__MIN 0 -#define R_PAR1_CTRL_DATA__ecp_cmd__MIN 0 -#define R_PAR1_CTRL_DATA__data__MIN 0 - -#define R_PAR1_CTRL_DATA__peri_int__BITNR 24 -#define R_PAR1_CTRL_DATA__oe__BITNR 20 -#define R_PAR1_CTRL_DATA__seli__BITNR 19 -#define R_PAR1_CTRL_DATA__autofd__BITNR 18 -#define R_PAR1_CTRL_DATA__strb__BITNR 17 -#define R_PAR1_CTRL_DATA__init__BITNR 16 -#define R_PAR1_CTRL_DATA__ecp_cmd__BITNR 8 -#define R_PAR1_CTRL_DATA__data__BITNR 0 - -#define R_PAR1_CTRL_DATA__peri_int__peri_int__VAL REG_VAL_ENUM -#define R_PAR1_CTRL_DATA__oe__oe__VAL REG_VAL_ENUM -#define R_PAR1_CTRL_DATA__seli__seli__VAL REG_VAL_ENUM -#define R_PAR1_CTRL_DATA__autofd__autofd__VAL REG_VAL_ENUM -#define R_PAR1_CTRL_DATA__strb__strb__VAL REG_VAL_ENUM -#define R_PAR1_CTRL_DATA__init__init__VAL REG_VAL_ENUM -#define R_PAR1_CTRL_DATA__ecp_cmd__ecp_cmd__VAL REG_VAL_ENUM -#define R_PAR1_CTRL_DATA__data__data__VAL REG_VAL_VAL - -#define R_PAR1_CTRL_DATA__peri_int__peri_int__ack 1 -#define R_PAR1_CTRL_DATA__peri_int__peri_int__nop 0 -#define R_PAR1_CTRL_DATA__oe__oe__disable 0 -#define R_PAR1_CTRL_DATA__oe__oe__enable 1 -#define R_PAR1_CTRL_DATA__seli__seli__active 1 -#define R_PAR1_CTRL_DATA__seli__seli__inactive 0 -#define R_PAR1_CTRL_DATA__autofd__autofd__active 1 -#define R_PAR1_CTRL_DATA__autofd__autofd__inactive 0 -#define R_PAR1_CTRL_DATA__strb__strb__active 1 -#define R_PAR1_CTRL_DATA__strb__strb__inactive 0 -#define R_PAR1_CTRL_DATA__init__init__active 1 -#define R_PAR1_CTRL_DATA__init__init__inactive 0 -#define R_PAR1_CTRL_DATA__ecp_cmd__ecp_cmd__command 1 -#define R_PAR1_CTRL_DATA__ecp_cmd__ecp_cmd__data 0 - -#endif - -/* - * R_PAR1_DELAY - * - type: WO - * - addr: 0xb0000058 - * - group: Parallel printer port registers - */ - -#if USE_GROUP__Parallel_printer_port_registers - -#define R_PAR1_DELAY__ADDR (REG_TYPECAST_UDWORD 0xb0000058) - -#ifndef REG_NO_SHADOW -#define R_PAR1_DELAY__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_PAR1_DELAY + 0)) -#define R_PAR1_DELAY__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_PAR1_DELAY + 0)) -#else /* REG_NO_SHADOW */ -#define R_PAR1_DELAY__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_PAR1_DELAY__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_PAR1_DELAY__STYPECAST REG_STYPECAST_UDWORD -#define R_PAR1_DELAY__SVAL REG_SVAL_SHADOW -#define R_PAR1_DELAY__SVAL_I REG_SVAL_I_SHADOW -#define R_PAR1_DELAY__TYPECAST REG_TYPECAST_UDWORD -#define R_PAR1_DELAY__TYPE (REG_UDWORD) -#define R_PAR1_DELAY__GET REG_GET_WO -#define R_PAR1_DELAY__IGET REG_IGET_WO -#define R_PAR1_DELAY__SET REG_SET_WO -#define R_PAR1_DELAY__ISET REG_ISET_WO -#define R_PAR1_DELAY__SET_VAL REG_SET_VAL_WO -#define R_PAR1_DELAY__EQL REG_EQL_WO -#define R_PAR1_DELAY__IEQL REG_IEQL_WO -#define R_PAR1_DELAY__RD REG_RD_WO -#define R_PAR1_DELAY__IRD REG_IRD_WO -#define R_PAR1_DELAY__WR REG_WR_WO -#define R_PAR1_DELAY__IWR REG_IWR_WO - -#define R_PAR1_DELAY__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_PAR1_DELAY__fine_hold__fine_hold__MASK 0x00e00000U -#define R_PAR1_DELAY__hold__hold__MASK 0x001f0000U -#define R_PAR1_DELAY__fine_strb__fine_strb__MASK 0x0000e000U -#define R_PAR1_DELAY__strobe__strobe__MASK 0x00001f00U -#define R_PAR1_DELAY__fine_setup__fine_setup__MASK 0x000000e0U -#define R_PAR1_DELAY__setup__setup__MASK 0x0000001fU - -#define R_PAR1_DELAY__fine_hold__MAX 0x7 -#define R_PAR1_DELAY__hold__MAX 0x1f -#define R_PAR1_DELAY__fine_strb__MAX 0x7 -#define R_PAR1_DELAY__strobe__MAX 0x1f -#define R_PAR1_DELAY__fine_setup__MAX 0x7 -#define R_PAR1_DELAY__setup__MAX 0x1f - -#define R_PAR1_DELAY__fine_hold__MIN 0 -#define R_PAR1_DELAY__hold__MIN 0 -#define R_PAR1_DELAY__fine_strb__MIN 0 -#define R_PAR1_DELAY__strobe__MIN 0 -#define R_PAR1_DELAY__fine_setup__MIN 0 -#define R_PAR1_DELAY__setup__MIN 0 - -#define R_PAR1_DELAY__fine_hold__BITNR 21 -#define R_PAR1_DELAY__hold__BITNR 16 -#define R_PAR1_DELAY__fine_strb__BITNR 13 -#define R_PAR1_DELAY__strobe__BITNR 8 -#define R_PAR1_DELAY__fine_setup__BITNR 5 -#define R_PAR1_DELAY__setup__BITNR 0 - -#define R_PAR1_DELAY__fine_hold__fine_hold__VAL REG_VAL_VAL -#define R_PAR1_DELAY__hold__hold__VAL REG_VAL_VAL -#define R_PAR1_DELAY__fine_strb__fine_strb__VAL REG_VAL_VAL -#define R_PAR1_DELAY__strobe__strobe__VAL REG_VAL_VAL -#define R_PAR1_DELAY__fine_setup__fine_setup__VAL REG_VAL_VAL -#define R_PAR1_DELAY__setup__setup__VAL REG_VAL_VAL - - -#endif - -/* - * R_PAR1_STATUS - * - type: RO - * - addr: 0xb0000052 - * - group: Parallel printer port registers - */ - -#if USE_GROUP__Parallel_printer_port_registers - -#define R_PAR1_STATUS__ADDR (REG_TYPECAST_UWORD 0xb0000052) -#define R_PAR1_STATUS__SVAL REG_SVAL_SHADOW -#define R_PAR1_STATUS__SVAL_I REG_SVAL_I_SHADOW -#define R_PAR1_STATUS__TYPECAST REG_TYPECAST_UWORD -#define R_PAR1_STATUS__TYPE (REG_UWORD) -#define R_PAR1_STATUS__GET REG_GET_RO -#define R_PAR1_STATUS__IGET REG_IGET_RO -#define R_PAR1_STATUS__SET REG_SET_RO -#define R_PAR1_STATUS__ISET REG_ISET_RO -#define R_PAR1_STATUS__SET_VAL REG_SET_VAL_RO -#define R_PAR1_STATUS__EQL REG_EQL_RO -#define R_PAR1_STATUS__IEQL REG_IEQL_RO -#define R_PAR1_STATUS__RD REG_RD_RO -#define R_PAR1_STATUS__IRD REG_IRD_RO -#define R_PAR1_STATUS__WR REG_WR_RO -#define R_PAR1_STATUS__IWR REG_IWR_RO - -#define R_PAR1_STATUS__READ(addr) \ - (*(addr)) - -#define R_PAR1_STATUS__mode__mode__MASK 0x0000e000U -#define R_PAR1_STATUS__perr__perr__MASK 0x00001000U -#define R_PAR1_STATUS__ack__ack__MASK 0x00000800U -#define R_PAR1_STATUS__busy__busy__MASK 0x00000400U -#define R_PAR1_STATUS__fault__fault__MASK 0x00000200U -#define R_PAR1_STATUS__sel__sel__MASK 0x00000100U -#define R_PAR1_STATUS__ext_mode__ext_mode__MASK 0x00000080U -#define R_PAR1_STATUS__tr_rdy__tr_rdy__MASK 0x00000002U -#define R_PAR1_STATUS__dav__dav__MASK 0x00000001U - -#define R_PAR1_STATUS__mode__MAX 0x7 -#define R_PAR1_STATUS__perr__MAX 0x1 -#define R_PAR1_STATUS__ack__MAX 0x1 -#define R_PAR1_STATUS__busy__MAX 0x1 -#define R_PAR1_STATUS__fault__MAX 0x1 -#define R_PAR1_STATUS__sel__MAX 0x1 -#define R_PAR1_STATUS__ext_mode__MAX 0x1 -#define R_PAR1_STATUS__tr_rdy__MAX 0x1 -#define R_PAR1_STATUS__dav__MAX 0x1 - -#define R_PAR1_STATUS__mode__MIN 0 -#define R_PAR1_STATUS__perr__MIN 0 -#define R_PAR1_STATUS__ack__MIN 0 -#define R_PAR1_STATUS__busy__MIN 0 -#define R_PAR1_STATUS__fault__MIN 0 -#define R_PAR1_STATUS__sel__MIN 0 -#define R_PAR1_STATUS__ext_mode__MIN 0 -#define R_PAR1_STATUS__tr_rdy__MIN 0 -#define R_PAR1_STATUS__dav__MIN 0 - -#define R_PAR1_STATUS__mode__BITNR 13 -#define R_PAR1_STATUS__perr__BITNR 12 -#define R_PAR1_STATUS__ack__BITNR 11 -#define R_PAR1_STATUS__busy__BITNR 10 -#define R_PAR1_STATUS__fault__BITNR 9 -#define R_PAR1_STATUS__sel__BITNR 8 -#define R_PAR1_STATUS__ext_mode__BITNR 7 -#define R_PAR1_STATUS__tr_rdy__BITNR 1 -#define R_PAR1_STATUS__dav__BITNR 0 - -#define R_PAR1_STATUS__mode__mode__VAL REG_VAL_ENUM -#define R_PAR1_STATUS__perr__perr__VAL REG_VAL_ENUM -#define R_PAR1_STATUS__ack__ack__VAL REG_VAL_ENUM -#define R_PAR1_STATUS__busy__busy__VAL REG_VAL_ENUM -#define R_PAR1_STATUS__fault__fault__VAL REG_VAL_ENUM -#define R_PAR1_STATUS__sel__sel__VAL REG_VAL_ENUM -#define R_PAR1_STATUS__ext_mode__ext_mode__VAL REG_VAL_ENUM -#define R_PAR1_STATUS__tr_rdy__tr_rdy__VAL REG_VAL_ENUM -#define R_PAR1_STATUS__dav__dav__VAL REG_VAL_ENUM - -#define R_PAR1_STATUS__mode__mode__byte 4 -#define R_PAR1_STATUS__mode__mode__centronics 1 -#define R_PAR1_STATUS__mode__mode__ecp_fwd 5 -#define R_PAR1_STATUS__mode__mode__ecp_rev 6 -#define R_PAR1_STATUS__mode__mode__epp_rd 0 -#define R_PAR1_STATUS__mode__mode__epp_wr1 5 -#define R_PAR1_STATUS__mode__mode__epp_wr2 6 -#define R_PAR1_STATUS__mode__mode__epp_wr3 7 -#define R_PAR1_STATUS__mode__mode__fastbyte 2 -#define R_PAR1_STATUS__mode__mode__manual 0 -#define R_PAR1_STATUS__mode__mode__nibble 3 -#define R_PAR1_STATUS__mode__mode__off 7 -#define R_PAR1_STATUS__perr__perr__active 1 -#define R_PAR1_STATUS__perr__perr__inactive 0 -#define R_PAR1_STATUS__ack__ack__active 0 -#define R_PAR1_STATUS__ack__ack__inactive 1 -#define R_PAR1_STATUS__busy__busy__active 1 -#define R_PAR1_STATUS__busy__busy__inactive 0 -#define R_PAR1_STATUS__fault__fault__active 0 -#define R_PAR1_STATUS__fault__fault__inactive 1 -#define R_PAR1_STATUS__sel__sel__active 1 -#define R_PAR1_STATUS__sel__sel__inactive 0 -#define R_PAR1_STATUS__ext_mode__ext_mode__disable 0 -#define R_PAR1_STATUS__ext_mode__ext_mode__enable 1 -#define R_PAR1_STATUS__tr_rdy__tr_rdy__busy 0 -#define R_PAR1_STATUS__tr_rdy__tr_rdy__ready 1 -#define R_PAR1_STATUS__dav__dav__data 1 -#define R_PAR1_STATUS__dav__dav__nodata 0 - -#endif - -/* - * R_PAR1_STATUS_DATA - * - type: RO - * - addr: 0xb0000050 - * - group: Parallel printer port registers - */ - -#if USE_GROUP__Parallel_printer_port_registers - -#define R_PAR1_STATUS_DATA__ADDR (REG_TYPECAST_UDWORD 0xb0000050) -#define R_PAR1_STATUS_DATA__SVAL REG_SVAL_SHADOW -#define R_PAR1_STATUS_DATA__SVAL_I REG_SVAL_I_SHADOW -#define R_PAR1_STATUS_DATA__TYPECAST REG_TYPECAST_UDWORD -#define R_PAR1_STATUS_DATA__TYPE (REG_UDWORD) -#define R_PAR1_STATUS_DATA__GET REG_GET_RO -#define R_PAR1_STATUS_DATA__IGET REG_IGET_RO -#define R_PAR1_STATUS_DATA__SET REG_SET_RO -#define R_PAR1_STATUS_DATA__ISET REG_ISET_RO -#define R_PAR1_STATUS_DATA__SET_VAL REG_SET_VAL_RO -#define R_PAR1_STATUS_DATA__EQL REG_EQL_RO -#define R_PAR1_STATUS_DATA__IEQL REG_IEQL_RO -#define R_PAR1_STATUS_DATA__RD REG_RD_RO -#define R_PAR1_STATUS_DATA__IRD REG_IRD_RO -#define R_PAR1_STATUS_DATA__WR REG_WR_RO -#define R_PAR1_STATUS_DATA__IWR REG_IWR_RO - -#define R_PAR1_STATUS_DATA__READ(addr) \ - (*(addr)) - -#define R_PAR1_STATUS_DATA__mode__mode__MASK 0xe0000000U -#define R_PAR1_STATUS_DATA__perr__perr__MASK 0x10000000U -#define R_PAR1_STATUS_DATA__ack__ack__MASK 0x08000000U -#define R_PAR1_STATUS_DATA__busy__busy__MASK 0x04000000U -#define R_PAR1_STATUS_DATA__fault__fault__MASK 0x02000000U -#define R_PAR1_STATUS_DATA__sel__sel__MASK 0x01000000U -#define R_PAR1_STATUS_DATA__ext_mode__ext_mode__MASK 0x00800000U -#define R_PAR1_STATUS_DATA__tr_rdy__tr_rdy__MASK 0x00020000U -#define R_PAR1_STATUS_DATA__dav__dav__MASK 0x00010000U -#define R_PAR1_STATUS_DATA__ecp_cmd__ecp_cmd__MASK 0x00000100U -#define R_PAR1_STATUS_DATA__data__data__MASK 0x000000ffU - -#define R_PAR1_STATUS_DATA__mode__MAX 0x7 -#define R_PAR1_STATUS_DATA__perr__MAX 0x1 -#define R_PAR1_STATUS_DATA__ack__MAX 0x1 -#define R_PAR1_STATUS_DATA__busy__MAX 0x1 -#define R_PAR1_STATUS_DATA__fault__MAX 0x1 -#define R_PAR1_STATUS_DATA__sel__MAX 0x1 -#define R_PAR1_STATUS_DATA__ext_mode__MAX 0x1 -#define R_PAR1_STATUS_DATA__tr_rdy__MAX 0x1 -#define R_PAR1_STATUS_DATA__dav__MAX 0x1 -#define R_PAR1_STATUS_DATA__ecp_cmd__MAX 0x1 -#define R_PAR1_STATUS_DATA__data__MAX 0xff - -#define R_PAR1_STATUS_DATA__mode__MIN 0 -#define R_PAR1_STATUS_DATA__perr__MIN 0 -#define R_PAR1_STATUS_DATA__ack__MIN 0 -#define R_PAR1_STATUS_DATA__busy__MIN 0 -#define R_PAR1_STATUS_DATA__fault__MIN 0 -#define R_PAR1_STATUS_DATA__sel__MIN 0 -#define R_PAR1_STATUS_DATA__ext_mode__MIN 0 -#define R_PAR1_STATUS_DATA__tr_rdy__MIN 0 -#define R_PAR1_STATUS_DATA__dav__MIN 0 -#define R_PAR1_STATUS_DATA__ecp_cmd__MIN 0 -#define R_PAR1_STATUS_DATA__data__MIN 0 - -#define R_PAR1_STATUS_DATA__mode__BITNR 29 -#define R_PAR1_STATUS_DATA__perr__BITNR 28 -#define R_PAR1_STATUS_DATA__ack__BITNR 27 -#define R_PAR1_STATUS_DATA__busy__BITNR 26 -#define R_PAR1_STATUS_DATA__fault__BITNR 25 -#define R_PAR1_STATUS_DATA__sel__BITNR 24 -#define R_PAR1_STATUS_DATA__ext_mode__BITNR 23 -#define R_PAR1_STATUS_DATA__tr_rdy__BITNR 17 -#define R_PAR1_STATUS_DATA__dav__BITNR 16 -#define R_PAR1_STATUS_DATA__ecp_cmd__BITNR 8 -#define R_PAR1_STATUS_DATA__data__BITNR 0 - -#define R_PAR1_STATUS_DATA__mode__mode__VAL REG_VAL_ENUM -#define R_PAR1_STATUS_DATA__perr__perr__VAL REG_VAL_ENUM -#define R_PAR1_STATUS_DATA__ack__ack__VAL REG_VAL_ENUM -#define R_PAR1_STATUS_DATA__busy__busy__VAL REG_VAL_ENUM -#define R_PAR1_STATUS_DATA__fault__fault__VAL REG_VAL_ENUM -#define R_PAR1_STATUS_DATA__sel__sel__VAL REG_VAL_ENUM -#define R_PAR1_STATUS_DATA__ext_mode__ext_mode__VAL REG_VAL_ENUM -#define R_PAR1_STATUS_DATA__tr_rdy__tr_rdy__VAL REG_VAL_ENUM -#define R_PAR1_STATUS_DATA__dav__dav__VAL REG_VAL_ENUM -#define R_PAR1_STATUS_DATA__ecp_cmd__ecp_cmd__VAL REG_VAL_ENUM -#define R_PAR1_STATUS_DATA__data__data__VAL REG_VAL_VAL - -#define R_PAR1_STATUS_DATA__mode__mode__byte 4 -#define R_PAR1_STATUS_DATA__mode__mode__centronics 1 -#define R_PAR1_STATUS_DATA__mode__mode__ecp_fwd 5 -#define R_PAR1_STATUS_DATA__mode__mode__ecp_rev 6 -#define R_PAR1_STATUS_DATA__mode__mode__epp_rd 0 -#define R_PAR1_STATUS_DATA__mode__mode__epp_wr1 5 -#define R_PAR1_STATUS_DATA__mode__mode__epp_wr2 6 -#define R_PAR1_STATUS_DATA__mode__mode__epp_wr3 7 -#define R_PAR1_STATUS_DATA__mode__mode__fastbyte 2 -#define R_PAR1_STATUS_DATA__mode__mode__manual 0 -#define R_PAR1_STATUS_DATA__mode__mode__nibble 3 -#define R_PAR1_STATUS_DATA__mode__mode__off 7 -#define R_PAR1_STATUS_DATA__perr__perr__active 1 -#define R_PAR1_STATUS_DATA__perr__perr__inactive 0 -#define R_PAR1_STATUS_DATA__ack__ack__active 0 -#define R_PAR1_STATUS_DATA__ack__ack__inactive 1 -#define R_PAR1_STATUS_DATA__busy__busy__active 1 -#define R_PAR1_STATUS_DATA__busy__busy__inactive 0 -#define R_PAR1_STATUS_DATA__fault__fault__active 0 -#define R_PAR1_STATUS_DATA__fault__fault__inactive 1 -#define R_PAR1_STATUS_DATA__sel__sel__active 1 -#define R_PAR1_STATUS_DATA__sel__sel__inactive 0 -#define R_PAR1_STATUS_DATA__ext_mode__ext_mode__disable 0 -#define R_PAR1_STATUS_DATA__ext_mode__ext_mode__enable 1 -#define R_PAR1_STATUS_DATA__tr_rdy__tr_rdy__busy 0 -#define R_PAR1_STATUS_DATA__tr_rdy__tr_rdy__ready 1 -#define R_PAR1_STATUS_DATA__dav__dav__data 1 -#define R_PAR1_STATUS_DATA__dav__dav__nodata 0 -#define R_PAR1_STATUS_DATA__ecp_cmd__ecp_cmd__command 1 -#define R_PAR1_STATUS_DATA__ecp_cmd__ecp_cmd__data 0 - -#endif - -/* - * R_PAR_ECP16_DATA - * - type: RW - * - addr: 0xb0000040 - * - group: Parallel printer port registers - */ - -#if USE_GROUP__Parallel_printer_port_registers - -#define R_PAR_ECP16_DATA__ADDR (REG_TYPECAST_UWORD 0xb0000040) -#define R_PAR_ECP16_DATA__SVAL REG_SVAL_SHADOW -#define R_PAR_ECP16_DATA__SVAL_I REG_SVAL_I_SHADOW -#define R_PAR_ECP16_DATA__TYPECAST REG_TYPECAST_UWORD -#define R_PAR_ECP16_DATA__TYPE (REG_UWORD) -#define R_PAR_ECP16_DATA__GET REG_GET_RW -#define R_PAR_ECP16_DATA__IGET REG_IGET_RW -#define R_PAR_ECP16_DATA__SET REG_SET_RW -#define R_PAR_ECP16_DATA__ISET REG_ISET_RW -#define R_PAR_ECP16_DATA__SET_VAL REG_SET_VAL_RW -#define R_PAR_ECP16_DATA__EQL REG_EQL_RW -#define R_PAR_ECP16_DATA__IEQL REG_IEQL_RW -#define R_PAR_ECP16_DATA__RD REG_RD_RW -#define R_PAR_ECP16_DATA__IRD REG_IRD_RW -#define R_PAR_ECP16_DATA__WR REG_WR_RW -#define R_PAR_ECP16_DATA__IWR REG_IWR_RW - -#define R_PAR_ECP16_DATA__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_PAR_ECP16_DATA__READ(addr) \ - (*(addr)) - -#define R_PAR_ECP16_DATA__data__data__MASK 0x0000ffffU - -#define R_PAR_ECP16_DATA__data__MAX 0xffff - -#define R_PAR_ECP16_DATA__data__MIN 0 - -#define R_PAR_ECP16_DATA__data__BITNR 0 - -#define R_PAR_ECP16_DATA__data__data__VAL REG_VAL_VAL - - -#endif - -/* - * R_PHY_COUNTERS - * - type: RO - * - addr: 0xb00000ac - * - group: Network interface registers - */ - -#if USE_GROUP__Network_interface_registers - -#define R_PHY_COUNTERS__ADDR (REG_TYPECAST_UDWORD 0xb00000ac) -#define R_PHY_COUNTERS__SVAL REG_SVAL_SHADOW -#define R_PHY_COUNTERS__SVAL_I REG_SVAL_I_SHADOW -#define R_PHY_COUNTERS__TYPECAST REG_TYPECAST_UDWORD -#define R_PHY_COUNTERS__TYPE (REG_UDWORD) -#define R_PHY_COUNTERS__GET REG_GET_RO -#define R_PHY_COUNTERS__IGET REG_IGET_RO -#define R_PHY_COUNTERS__SET REG_SET_RO -#define R_PHY_COUNTERS__ISET REG_ISET_RO -#define R_PHY_COUNTERS__SET_VAL REG_SET_VAL_RO -#define R_PHY_COUNTERS__EQL REG_EQL_RO -#define R_PHY_COUNTERS__IEQL REG_IEQL_RO -#define R_PHY_COUNTERS__RD REG_RD_RO -#define R_PHY_COUNTERS__IRD REG_IRD_RO -#define R_PHY_COUNTERS__WR REG_WR_RO -#define R_PHY_COUNTERS__IWR REG_IWR_RO - -#define R_PHY_COUNTERS__READ(addr) \ - (*(addr)) - -#define R_PHY_COUNTERS__sqe_test_error__sqe_test_error__MASK 0x0000ff00U -#define R_PHY_COUNTERS__carrier_loss__carrier_loss__MASK 0x000000ffU - -#define R_PHY_COUNTERS__sqe_test_error__MAX 0xff -#define R_PHY_COUNTERS__carrier_loss__MAX 0xff - -#define R_PHY_COUNTERS__sqe_test_error__MIN 0 -#define R_PHY_COUNTERS__carrier_loss__MIN 0 - -#define R_PHY_COUNTERS__sqe_test_error__BITNR 8 -#define R_PHY_COUNTERS__carrier_loss__BITNR 0 - -#define R_PHY_COUNTERS__sqe_test_error__sqe_test_error__VAL REG_VAL_VAL -#define R_PHY_COUNTERS__carrier_loss__carrier_loss__VAL REG_VAL_VAL - - -#endif - -/* - * R_PORT_G_DATA - * - type: RW - * - addr: 0xb0000028 - * - group: General config registers - */ - -#if USE_GROUP__General_config_registers - -#define R_PORT_G_DATA__ADDR (REG_TYPECAST_UDWORD 0xb0000028) -#define R_PORT_G_DATA__SVAL REG_SVAL_SHADOW -#define R_PORT_G_DATA__SVAL_I REG_SVAL_I_SHADOW -#define R_PORT_G_DATA__TYPECAST REG_TYPECAST_UDWORD -#define R_PORT_G_DATA__TYPE (REG_UDWORD) -#define R_PORT_G_DATA__GET REG_GET_RW -#define R_PORT_G_DATA__IGET REG_IGET_RW -#define R_PORT_G_DATA__SET REG_SET_RW -#define R_PORT_G_DATA__ISET REG_ISET_RW -#define R_PORT_G_DATA__SET_VAL REG_SET_VAL_RW -#define R_PORT_G_DATA__EQL REG_EQL_RW -#define R_PORT_G_DATA__IEQL REG_IEQL_RW -#define R_PORT_G_DATA__RD REG_RD_RW -#define R_PORT_G_DATA__IRD REG_IRD_RW -#define R_PORT_G_DATA__WR REG_WR_RW -#define R_PORT_G_DATA__IWR REG_IWR_RW - -#define R_PORT_G_DATA__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_PORT_G_DATA__READ(addr) \ - (*(addr)) - -#define R_PORT_G_DATA__data__data__MASK 0xffffffffU - -#define R_PORT_G_DATA__data__MAX 0xffffffff - -#define R_PORT_G_DATA__data__MIN 0 - -#define R_PORT_G_DATA__data__BITNR 0 - -#define R_PORT_G_DATA__data__data__VAL REG_VAL_VAL - - -#endif - -/* - * R_PORT_PA_DATA - * - type: WO - * - addr: 0xb0000030 - * - group: General port configuration registers - */ - -#if USE_GROUP__General_port_configuration_registers - -#define R_PORT_PA_DATA__ADDR (REG_TYPECAST_BYTE 0xb0000030) - -#ifndef REG_NO_SHADOW -#define R_PORT_PA_DATA__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_PORT_PA_SET + 0)) -#define R_PORT_PA_DATA__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_PORT_PA_SET + 0)) -#else /* REG_NO_SHADOW */ -#define R_PORT_PA_DATA__SADDR (REG_STYPECAST_BYTE (®_shadow__hwregs)) -#define R_PORT_PA_DATA__IADDR (REG_STYPECAST_BYTE (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_PORT_PA_DATA__STYPECAST REG_STYPECAST_BYTE -#define R_PORT_PA_DATA__SVAL REG_SVAL_SHADOW -#define R_PORT_PA_DATA__SVAL_I REG_SVAL_I_SHADOW -#define R_PORT_PA_DATA__TYPECAST REG_TYPECAST_BYTE -#define R_PORT_PA_DATA__TYPE (REG_BYTE) -#define R_PORT_PA_DATA__GET REG_GET_WO -#define R_PORT_PA_DATA__IGET REG_IGET_WO -#define R_PORT_PA_DATA__SET REG_SET_WO -#define R_PORT_PA_DATA__ISET REG_ISET_WO -#define R_PORT_PA_DATA__SET_VAL REG_SET_VAL_WO -#define R_PORT_PA_DATA__EQL REG_EQL_WO -#define R_PORT_PA_DATA__IEQL REG_IEQL_WO -#define R_PORT_PA_DATA__RD REG_RD_WO -#define R_PORT_PA_DATA__IRD REG_IRD_WO -#define R_PORT_PA_DATA__WR REG_WR_WO -#define R_PORT_PA_DATA__IWR REG_IWR_WO - -#define R_PORT_PA_DATA__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_PORT_PA_DATA__data_out__data_out__MASK 0x000000ffU - -#define R_PORT_PA_DATA__data_out__MAX 255 - -#define R_PORT_PA_DATA__data_out__MIN 0 - -#define R_PORT_PA_DATA__data_out__BITNR 0 - -#define R_PORT_PA_DATA__data_out__data_out__VAL REG_VAL_VAL - - -#endif - -/* - * R_PORT_PA_DIR - * - type: WO - * - addr: 0xb0000031 - * - group: General port configuration registers - */ - -#if USE_GROUP__General_port_configuration_registers - -#define R_PORT_PA_DIR__ADDR (REG_TYPECAST_BYTE 0xb0000031) - -#ifndef REG_NO_SHADOW -#define R_PORT_PA_DIR__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_PORT_PA_SET + 1)) -#define R_PORT_PA_DIR__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_PORT_PA_SET + 1)) -#else /* REG_NO_SHADOW */ -#define R_PORT_PA_DIR__SADDR (REG_STYPECAST_BYTE (®_shadow__hwregs)) -#define R_PORT_PA_DIR__IADDR (REG_STYPECAST_BYTE (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_PORT_PA_DIR__STYPECAST REG_STYPECAST_BYTE -#define R_PORT_PA_DIR__SVAL REG_SVAL_SHADOW -#define R_PORT_PA_DIR__SVAL_I REG_SVAL_I_SHADOW -#define R_PORT_PA_DIR__TYPECAST REG_TYPECAST_BYTE -#define R_PORT_PA_DIR__TYPE (REG_BYTE) -#define R_PORT_PA_DIR__GET REG_GET_WO -#define R_PORT_PA_DIR__IGET REG_IGET_WO -#define R_PORT_PA_DIR__SET REG_SET_WO -#define R_PORT_PA_DIR__ISET REG_ISET_WO -#define R_PORT_PA_DIR__SET_VAL REG_SET_VAL_WO -#define R_PORT_PA_DIR__EQL REG_EQL_WO -#define R_PORT_PA_DIR__IEQL REG_IEQL_WO -#define R_PORT_PA_DIR__RD REG_RD_WO -#define R_PORT_PA_DIR__IRD REG_IRD_WO -#define R_PORT_PA_DIR__WR REG_WR_WO -#define R_PORT_PA_DIR__IWR REG_IWR_WO - -#define R_PORT_PA_DIR__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_PORT_PA_DIR__dir7__dir7__MASK 0x00000080U -#define R_PORT_PA_DIR__dir6__dir6__MASK 0x00000040U -#define R_PORT_PA_DIR__dir5__dir5__MASK 0x00000020U -#define R_PORT_PA_DIR__dir4__dir4__MASK 0x00000010U -#define R_PORT_PA_DIR__dir3__dir3__MASK 0x00000008U -#define R_PORT_PA_DIR__dir2__dir2__MASK 0x00000004U -#define R_PORT_PA_DIR__dir1__dir1__MASK 0x00000002U -#define R_PORT_PA_DIR__dir0__dir0__MASK 0x00000001U - -#define R_PORT_PA_DIR__dir7__MAX 0x1 -#define R_PORT_PA_DIR__dir6__MAX 0x1 -#define R_PORT_PA_DIR__dir5__MAX 0x1 -#define R_PORT_PA_DIR__dir4__MAX 0x1 -#define R_PORT_PA_DIR__dir3__MAX 0x1 -#define R_PORT_PA_DIR__dir2__MAX 0x1 -#define R_PORT_PA_DIR__dir1__MAX 0x1 -#define R_PORT_PA_DIR__dir0__MAX 0x1 - -#define R_PORT_PA_DIR__dir7__MIN 0 -#define R_PORT_PA_DIR__dir6__MIN 0 -#define R_PORT_PA_DIR__dir5__MIN 0 -#define R_PORT_PA_DIR__dir4__MIN 0 -#define R_PORT_PA_DIR__dir3__MIN 0 -#define R_PORT_PA_DIR__dir2__MIN 0 -#define R_PORT_PA_DIR__dir1__MIN 0 -#define R_PORT_PA_DIR__dir0__MIN 0 - -#define R_PORT_PA_DIR__dir7__BITNR 7 -#define R_PORT_PA_DIR__dir6__BITNR 6 -#define R_PORT_PA_DIR__dir5__BITNR 5 -#define R_PORT_PA_DIR__dir4__BITNR 4 -#define R_PORT_PA_DIR__dir3__BITNR 3 -#define R_PORT_PA_DIR__dir2__BITNR 2 -#define R_PORT_PA_DIR__dir1__BITNR 1 -#define R_PORT_PA_DIR__dir0__BITNR 0 - -#define R_PORT_PA_DIR__dir7__dir7__VAL REG_VAL_ENUM -#define R_PORT_PA_DIR__dir6__dir6__VAL REG_VAL_ENUM -#define R_PORT_PA_DIR__dir5__dir5__VAL REG_VAL_ENUM -#define R_PORT_PA_DIR__dir4__dir4__VAL REG_VAL_ENUM -#define R_PORT_PA_DIR__dir3__dir3__VAL REG_VAL_ENUM -#define R_PORT_PA_DIR__dir2__dir2__VAL REG_VAL_ENUM -#define R_PORT_PA_DIR__dir1__dir1__VAL REG_VAL_ENUM -#define R_PORT_PA_DIR__dir0__dir0__VAL REG_VAL_ENUM - -#define R_PORT_PA_DIR__dir7__dir7__input 0 -#define R_PORT_PA_DIR__dir7__dir7__output 1 -#define R_PORT_PA_DIR__dir6__dir6__input 0 -#define R_PORT_PA_DIR__dir6__dir6__output 1 -#define R_PORT_PA_DIR__dir5__dir5__input 0 -#define R_PORT_PA_DIR__dir5__dir5__output 1 -#define R_PORT_PA_DIR__dir4__dir4__input 0 -#define R_PORT_PA_DIR__dir4__dir4__output 1 -#define R_PORT_PA_DIR__dir3__dir3__input 0 -#define R_PORT_PA_DIR__dir3__dir3__output 1 -#define R_PORT_PA_DIR__dir2__dir2__input 0 -#define R_PORT_PA_DIR__dir2__dir2__output 1 -#define R_PORT_PA_DIR__dir1__dir1__input 0 -#define R_PORT_PA_DIR__dir1__dir1__output 1 -#define R_PORT_PA_DIR__dir0__dir0__input 0 -#define R_PORT_PA_DIR__dir0__dir0__output 1 - -#endif - -/* - * R_PORT_PA_READ - * - type: RO - * - addr: 0xb0000030 - * - group: General port configuration registers - */ - -#if USE_GROUP__General_port_configuration_registers - -#define R_PORT_PA_READ__ADDR (REG_TYPECAST_UDWORD 0xb0000030) -#define R_PORT_PA_READ__SVAL REG_SVAL_SHADOW -#define R_PORT_PA_READ__SVAL_I REG_SVAL_I_SHADOW -#define R_PORT_PA_READ__TYPECAST REG_TYPECAST_UDWORD -#define R_PORT_PA_READ__TYPE (REG_UDWORD) -#define R_PORT_PA_READ__GET REG_GET_RO -#define R_PORT_PA_READ__IGET REG_IGET_RO -#define R_PORT_PA_READ__SET REG_SET_RO -#define R_PORT_PA_READ__ISET REG_ISET_RO -#define R_PORT_PA_READ__SET_VAL REG_SET_VAL_RO -#define R_PORT_PA_READ__EQL REG_EQL_RO -#define R_PORT_PA_READ__IEQL REG_IEQL_RO -#define R_PORT_PA_READ__RD REG_RD_RO -#define R_PORT_PA_READ__IRD REG_IRD_RO -#define R_PORT_PA_READ__WR REG_WR_RO -#define R_PORT_PA_READ__IWR REG_IWR_RO - -#define R_PORT_PA_READ__READ(addr) \ - (*(addr)) - -#define R_PORT_PA_READ__data_in__data_in__MASK 0x000000ffU - -#define R_PORT_PA_READ__data_in__MAX 255 - -#define R_PORT_PA_READ__data_in__MIN 0 - -#define R_PORT_PA_READ__data_in__BITNR 0 - -#define R_PORT_PA_READ__data_in__data_in__VAL REG_VAL_VAL - - -#endif - -/* - * R_PORT_PA_SET - * - type: WO - * - addr: 0xb0000030 - * - group: General port configuration registers - */ - -#if USE_GROUP__General_port_configuration_registers - -#define R_PORT_PA_SET__ADDR (REG_TYPECAST_UDWORD 0xb0000030) - -#ifndef REG_NO_SHADOW -#define R_PORT_PA_SET__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_PORT_PA_SET + 0)) -#define R_PORT_PA_SET__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_PORT_PA_SET + 0)) -#else /* REG_NO_SHADOW */ -#define R_PORT_PA_SET__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_PORT_PA_SET__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_PORT_PA_SET__STYPECAST REG_STYPECAST_UDWORD -#define R_PORT_PA_SET__SVAL REG_SVAL_SHADOW -#define R_PORT_PA_SET__SVAL_I REG_SVAL_I_SHADOW -#define R_PORT_PA_SET__TYPECAST REG_TYPECAST_UDWORD -#define R_PORT_PA_SET__TYPE (REG_UDWORD) -#define R_PORT_PA_SET__GET REG_GET_WO -#define R_PORT_PA_SET__IGET REG_IGET_WO -#define R_PORT_PA_SET__SET REG_SET_WO -#define R_PORT_PA_SET__ISET REG_ISET_WO -#define R_PORT_PA_SET__SET_VAL REG_SET_VAL_WO -#define R_PORT_PA_SET__EQL REG_EQL_WO -#define R_PORT_PA_SET__IEQL REG_IEQL_WO -#define R_PORT_PA_SET__RD REG_RD_WO -#define R_PORT_PA_SET__IRD REG_IRD_WO -#define R_PORT_PA_SET__WR REG_WR_WO -#define R_PORT_PA_SET__IWR REG_IWR_WO - -#define R_PORT_PA_SET__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_PORT_PA_SET__dir7__dir7__MASK 0x00008000U -#define R_PORT_PA_SET__dir6__dir6__MASK 0x00004000U -#define R_PORT_PA_SET__dir5__dir5__MASK 0x00002000U -#define R_PORT_PA_SET__dir4__dir4__MASK 0x00001000U -#define R_PORT_PA_SET__dir3__dir3__MASK 0x00000800U -#define R_PORT_PA_SET__dir2__dir2__MASK 0x00000400U -#define R_PORT_PA_SET__dir1__dir1__MASK 0x00000200U -#define R_PORT_PA_SET__dir0__dir0__MASK 0x00000100U -#define R_PORT_PA_SET__data_out__data_out__MASK 0x000000ffU - -#define R_PORT_PA_SET__dir7__MAX 0x1 -#define R_PORT_PA_SET__dir6__MAX 0x1 -#define R_PORT_PA_SET__dir5__MAX 0x1 -#define R_PORT_PA_SET__dir4__MAX 0x1 -#define R_PORT_PA_SET__dir3__MAX 0x1 -#define R_PORT_PA_SET__dir2__MAX 0x1 -#define R_PORT_PA_SET__dir1__MAX 0x1 -#define R_PORT_PA_SET__dir0__MAX 0x1 -#define R_PORT_PA_SET__data_out__MAX 255 - -#define R_PORT_PA_SET__dir7__MIN 0 -#define R_PORT_PA_SET__dir6__MIN 0 -#define R_PORT_PA_SET__dir5__MIN 0 -#define R_PORT_PA_SET__dir4__MIN 0 -#define R_PORT_PA_SET__dir3__MIN 0 -#define R_PORT_PA_SET__dir2__MIN 0 -#define R_PORT_PA_SET__dir1__MIN 0 -#define R_PORT_PA_SET__dir0__MIN 0 -#define R_PORT_PA_SET__data_out__MIN 0 - -#define R_PORT_PA_SET__dir7__BITNR 15 -#define R_PORT_PA_SET__dir6__BITNR 14 -#define R_PORT_PA_SET__dir5__BITNR 13 -#define R_PORT_PA_SET__dir4__BITNR 12 -#define R_PORT_PA_SET__dir3__BITNR 11 -#define R_PORT_PA_SET__dir2__BITNR 10 -#define R_PORT_PA_SET__dir1__BITNR 9 -#define R_PORT_PA_SET__dir0__BITNR 8 -#define R_PORT_PA_SET__data_out__BITNR 0 - -#define R_PORT_PA_SET__dir7__dir7__VAL REG_VAL_ENUM -#define R_PORT_PA_SET__dir6__dir6__VAL REG_VAL_ENUM -#define R_PORT_PA_SET__dir5__dir5__VAL REG_VAL_ENUM -#define R_PORT_PA_SET__dir4__dir4__VAL REG_VAL_ENUM -#define R_PORT_PA_SET__dir3__dir3__VAL REG_VAL_ENUM -#define R_PORT_PA_SET__dir2__dir2__VAL REG_VAL_ENUM -#define R_PORT_PA_SET__dir1__dir1__VAL REG_VAL_ENUM -#define R_PORT_PA_SET__dir0__dir0__VAL REG_VAL_ENUM -#define R_PORT_PA_SET__data_out__data_out__VAL REG_VAL_VAL - -#define R_PORT_PA_SET__dir7__dir7__input 0 -#define R_PORT_PA_SET__dir7__dir7__output 1 -#define R_PORT_PA_SET__dir6__dir6__input 0 -#define R_PORT_PA_SET__dir6__dir6__output 1 -#define R_PORT_PA_SET__dir5__dir5__input 0 -#define R_PORT_PA_SET__dir5__dir5__output 1 -#define R_PORT_PA_SET__dir4__dir4__input 0 -#define R_PORT_PA_SET__dir4__dir4__output 1 -#define R_PORT_PA_SET__dir3__dir3__input 0 -#define R_PORT_PA_SET__dir3__dir3__output 1 -#define R_PORT_PA_SET__dir2__dir2__input 0 -#define R_PORT_PA_SET__dir2__dir2__output 1 -#define R_PORT_PA_SET__dir1__dir1__input 0 -#define R_PORT_PA_SET__dir1__dir1__output 1 -#define R_PORT_PA_SET__dir0__dir0__input 0 -#define R_PORT_PA_SET__dir0__dir0__output 1 - -#endif - -/* - * R_PORT_PB_CONFIG - * - type: WO - * - addr: 0xb000003a - * - group: General port configuration registers - */ - -#if USE_GROUP__General_port_configuration_registers - -#define R_PORT_PB_CONFIG__ADDR (REG_TYPECAST_BYTE 0xb000003a) - -#ifndef REG_NO_SHADOW -#define R_PORT_PB_CONFIG__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_PORT_PB_SET + 2)) -#define R_PORT_PB_CONFIG__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_PORT_PB_SET + 2)) -#else /* REG_NO_SHADOW */ -#define R_PORT_PB_CONFIG__SADDR (REG_STYPECAST_BYTE (®_shadow__hwregs)) -#define R_PORT_PB_CONFIG__IADDR (REG_STYPECAST_BYTE (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_PORT_PB_CONFIG__STYPECAST REG_STYPECAST_BYTE -#define R_PORT_PB_CONFIG__SVAL REG_SVAL_SHADOW -#define R_PORT_PB_CONFIG__SVAL_I REG_SVAL_I_SHADOW -#define R_PORT_PB_CONFIG__TYPECAST REG_TYPECAST_BYTE -#define R_PORT_PB_CONFIG__TYPE (REG_BYTE) -#define R_PORT_PB_CONFIG__GET REG_GET_WO -#define R_PORT_PB_CONFIG__IGET REG_IGET_WO -#define R_PORT_PB_CONFIG__SET REG_SET_WO -#define R_PORT_PB_CONFIG__ISET REG_ISET_WO -#define R_PORT_PB_CONFIG__SET_VAL REG_SET_VAL_WO -#define R_PORT_PB_CONFIG__EQL REG_EQL_WO -#define R_PORT_PB_CONFIG__IEQL REG_IEQL_WO -#define R_PORT_PB_CONFIG__RD REG_RD_WO -#define R_PORT_PB_CONFIG__IRD REG_IRD_WO -#define R_PORT_PB_CONFIG__WR REG_WR_WO -#define R_PORT_PB_CONFIG__IWR REG_IWR_WO - -#define R_PORT_PB_CONFIG__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_PORT_PB_CONFIG__cs7__cs7__MASK 0x00000080U -#define R_PORT_PB_CONFIG__cs6__cs6__MASK 0x00000040U -#define R_PORT_PB_CONFIG__cs5__cs5__MASK 0x00000020U -#define R_PORT_PB_CONFIG__cs4__cs4__MASK 0x00000010U -#define R_PORT_PB_CONFIG__cs3__cs3__MASK 0x00000008U -#define R_PORT_PB_CONFIG__cs2__cs2__MASK 0x00000004U -#define R_PORT_PB_CONFIG__scsi1__scsi1__MASK 0x00000002U -#define R_PORT_PB_CONFIG__scsi0__scsi0__MASK 0x00000001U - -#define R_PORT_PB_CONFIG__cs7__MAX 0x1 -#define R_PORT_PB_CONFIG__cs6__MAX 0x1 -#define R_PORT_PB_CONFIG__cs5__MAX 0x1 -#define R_PORT_PB_CONFIG__cs4__MAX 0x1 -#define R_PORT_PB_CONFIG__cs3__MAX 0x1 -#define R_PORT_PB_CONFIG__cs2__MAX 0x1 -#define R_PORT_PB_CONFIG__scsi1__MAX 0x1 -#define R_PORT_PB_CONFIG__scsi0__MAX 0x1 - -#define R_PORT_PB_CONFIG__cs7__MIN 0 -#define R_PORT_PB_CONFIG__cs6__MIN 0 -#define R_PORT_PB_CONFIG__cs5__MIN 0 -#define R_PORT_PB_CONFIG__cs4__MIN 0 -#define R_PORT_PB_CONFIG__cs3__MIN 0 -#define R_PORT_PB_CONFIG__cs2__MIN 0 -#define R_PORT_PB_CONFIG__scsi1__MIN 0 -#define R_PORT_PB_CONFIG__scsi0__MIN 0 - -#define R_PORT_PB_CONFIG__cs7__BITNR 7 -#define R_PORT_PB_CONFIG__cs6__BITNR 6 -#define R_PORT_PB_CONFIG__cs5__BITNR 5 -#define R_PORT_PB_CONFIG__cs4__BITNR 4 -#define R_PORT_PB_CONFIG__cs3__BITNR 3 -#define R_PORT_PB_CONFIG__cs2__BITNR 2 -#define R_PORT_PB_CONFIG__scsi1__BITNR 1 -#define R_PORT_PB_CONFIG__scsi0__BITNR 0 - -#define R_PORT_PB_CONFIG__cs7__cs7__VAL REG_VAL_ENUM -#define R_PORT_PB_CONFIG__cs6__cs6__VAL REG_VAL_ENUM -#define R_PORT_PB_CONFIG__cs5__cs5__VAL REG_VAL_ENUM -#define R_PORT_PB_CONFIG__cs4__cs4__VAL REG_VAL_ENUM -#define R_PORT_PB_CONFIG__cs3__cs3__VAL REG_VAL_ENUM -#define R_PORT_PB_CONFIG__cs2__cs2__VAL REG_VAL_ENUM -#define R_PORT_PB_CONFIG__scsi1__scsi1__VAL REG_VAL_ENUM -#define R_PORT_PB_CONFIG__scsi0__scsi0__VAL REG_VAL_ENUM - -#define R_PORT_PB_CONFIG__cs7__cs7__cs 1 -#define R_PORT_PB_CONFIG__cs7__cs7__port 0 -#define R_PORT_PB_CONFIG__cs6__cs6__cs 1 -#define R_PORT_PB_CONFIG__cs6__cs6__port 0 -#define R_PORT_PB_CONFIG__cs5__cs5__cs 1 -#define R_PORT_PB_CONFIG__cs5__cs5__port 0 -#define R_PORT_PB_CONFIG__cs4__cs4__cs 1 -#define R_PORT_PB_CONFIG__cs4__cs4__port 0 -#define R_PORT_PB_CONFIG__cs3__cs3__cs 1 -#define R_PORT_PB_CONFIG__cs3__cs3__port 0 -#define R_PORT_PB_CONFIG__cs2__cs2__cs 1 -#define R_PORT_PB_CONFIG__cs2__cs2__port 0 -#define R_PORT_PB_CONFIG__scsi1__scsi1__enph 1 -#define R_PORT_PB_CONFIG__scsi1__scsi1__port_cs 0 -#define R_PORT_PB_CONFIG__scsi0__scsi0__enph 1 -#define R_PORT_PB_CONFIG__scsi0__scsi0__port_cs 0 - -#endif - -/* - * R_PORT_PB_DATA - * - type: WO - * - addr: 0xb0000038 - * - group: General port configuration registers - */ - -#if USE_GROUP__General_port_configuration_registers - -#define R_PORT_PB_DATA__ADDR (REG_TYPECAST_BYTE 0xb0000038) - -#ifndef REG_NO_SHADOW -#define R_PORT_PB_DATA__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_PORT_PB_SET + 0)) -#define R_PORT_PB_DATA__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_PORT_PB_SET + 0)) -#else /* REG_NO_SHADOW */ -#define R_PORT_PB_DATA__SADDR (REG_STYPECAST_BYTE (®_shadow__hwregs)) -#define R_PORT_PB_DATA__IADDR (REG_STYPECAST_BYTE (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_PORT_PB_DATA__STYPECAST REG_STYPECAST_BYTE -#define R_PORT_PB_DATA__SVAL REG_SVAL_SHADOW -#define R_PORT_PB_DATA__SVAL_I REG_SVAL_I_SHADOW -#define R_PORT_PB_DATA__TYPECAST REG_TYPECAST_BYTE -#define R_PORT_PB_DATA__TYPE (REG_BYTE) -#define R_PORT_PB_DATA__GET REG_GET_WO -#define R_PORT_PB_DATA__IGET REG_IGET_WO -#define R_PORT_PB_DATA__SET REG_SET_WO -#define R_PORT_PB_DATA__ISET REG_ISET_WO -#define R_PORT_PB_DATA__SET_VAL REG_SET_VAL_WO -#define R_PORT_PB_DATA__EQL REG_EQL_WO -#define R_PORT_PB_DATA__IEQL REG_IEQL_WO -#define R_PORT_PB_DATA__RD REG_RD_WO -#define R_PORT_PB_DATA__IRD REG_IRD_WO -#define R_PORT_PB_DATA__WR REG_WR_WO -#define R_PORT_PB_DATA__IWR REG_IWR_WO - -#define R_PORT_PB_DATA__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_PORT_PB_DATA__data_out__data_out__MASK 0x000000ffU - -#define R_PORT_PB_DATA__data_out__MAX 255 - -#define R_PORT_PB_DATA__data_out__MIN 0 - -#define R_PORT_PB_DATA__data_out__BITNR 0 - -#define R_PORT_PB_DATA__data_out__data_out__VAL REG_VAL_VAL - - -#endif - -/* - * R_PORT_PB_DIR - * - type: WO - * - addr: 0xb0000039 - * - group: General port configuration registers - */ - -#if USE_GROUP__General_port_configuration_registers - -#define R_PORT_PB_DIR__ADDR (REG_TYPECAST_BYTE 0xb0000039) - -#ifndef REG_NO_SHADOW -#define R_PORT_PB_DIR__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_PORT_PB_SET + 1)) -#define R_PORT_PB_DIR__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_PORT_PB_SET + 1)) -#else /* REG_NO_SHADOW */ -#define R_PORT_PB_DIR__SADDR (REG_STYPECAST_BYTE (®_shadow__hwregs)) -#define R_PORT_PB_DIR__IADDR (REG_STYPECAST_BYTE (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_PORT_PB_DIR__STYPECAST REG_STYPECAST_BYTE -#define R_PORT_PB_DIR__SVAL REG_SVAL_SHADOW -#define R_PORT_PB_DIR__SVAL_I REG_SVAL_I_SHADOW -#define R_PORT_PB_DIR__TYPECAST REG_TYPECAST_BYTE -#define R_PORT_PB_DIR__TYPE (REG_BYTE) -#define R_PORT_PB_DIR__GET REG_GET_WO -#define R_PORT_PB_DIR__IGET REG_IGET_WO -#define R_PORT_PB_DIR__SET REG_SET_WO -#define R_PORT_PB_DIR__ISET REG_ISET_WO -#define R_PORT_PB_DIR__SET_VAL REG_SET_VAL_WO -#define R_PORT_PB_DIR__EQL REG_EQL_WO -#define R_PORT_PB_DIR__IEQL REG_IEQL_WO -#define R_PORT_PB_DIR__RD REG_RD_WO -#define R_PORT_PB_DIR__IRD REG_IRD_WO -#define R_PORT_PB_DIR__WR REG_WR_WO -#define R_PORT_PB_DIR__IWR REG_IWR_WO - -#define R_PORT_PB_DIR__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_PORT_PB_DIR__dir7__dir7__MASK 0x00000080U -#define R_PORT_PB_DIR__dir6__dir6__MASK 0x00000040U -#define R_PORT_PB_DIR__dir5__dir5__MASK 0x00000020U -#define R_PORT_PB_DIR__dir4__dir4__MASK 0x00000010U -#define R_PORT_PB_DIR__dir3__dir3__MASK 0x00000008U -#define R_PORT_PB_DIR__dir2__dir2__MASK 0x00000004U -#define R_PORT_PB_DIR__dir1__dir1__MASK 0x00000002U -#define R_PORT_PB_DIR__dir0__dir0__MASK 0x00000001U - -#define R_PORT_PB_DIR__dir7__MAX 0x1 -#define R_PORT_PB_DIR__dir6__MAX 0x1 -#define R_PORT_PB_DIR__dir5__MAX 0x1 -#define R_PORT_PB_DIR__dir4__MAX 0x1 -#define R_PORT_PB_DIR__dir3__MAX 0x1 -#define R_PORT_PB_DIR__dir2__MAX 0x1 -#define R_PORT_PB_DIR__dir1__MAX 0x1 -#define R_PORT_PB_DIR__dir0__MAX 0x1 - -#define R_PORT_PB_DIR__dir7__MIN 0 -#define R_PORT_PB_DIR__dir6__MIN 0 -#define R_PORT_PB_DIR__dir5__MIN 0 -#define R_PORT_PB_DIR__dir4__MIN 0 -#define R_PORT_PB_DIR__dir3__MIN 0 -#define R_PORT_PB_DIR__dir2__MIN 0 -#define R_PORT_PB_DIR__dir1__MIN 0 -#define R_PORT_PB_DIR__dir0__MIN 0 - -#define R_PORT_PB_DIR__dir7__BITNR 7 -#define R_PORT_PB_DIR__dir6__BITNR 6 -#define R_PORT_PB_DIR__dir5__BITNR 5 -#define R_PORT_PB_DIR__dir4__BITNR 4 -#define R_PORT_PB_DIR__dir3__BITNR 3 -#define R_PORT_PB_DIR__dir2__BITNR 2 -#define R_PORT_PB_DIR__dir1__BITNR 1 -#define R_PORT_PB_DIR__dir0__BITNR 0 - -#define R_PORT_PB_DIR__dir7__dir7__VAL REG_VAL_ENUM -#define R_PORT_PB_DIR__dir6__dir6__VAL REG_VAL_ENUM -#define R_PORT_PB_DIR__dir5__dir5__VAL REG_VAL_ENUM -#define R_PORT_PB_DIR__dir4__dir4__VAL REG_VAL_ENUM -#define R_PORT_PB_DIR__dir3__dir3__VAL REG_VAL_ENUM -#define R_PORT_PB_DIR__dir2__dir2__VAL REG_VAL_ENUM -#define R_PORT_PB_DIR__dir1__dir1__VAL REG_VAL_ENUM -#define R_PORT_PB_DIR__dir0__dir0__VAL REG_VAL_ENUM - -#define R_PORT_PB_DIR__dir7__dir7__input 0 -#define R_PORT_PB_DIR__dir7__dir7__output 1 -#define R_PORT_PB_DIR__dir6__dir6__input 0 -#define R_PORT_PB_DIR__dir6__dir6__output 1 -#define R_PORT_PB_DIR__dir5__dir5__input 0 -#define R_PORT_PB_DIR__dir5__dir5__output 1 -#define R_PORT_PB_DIR__dir4__dir4__input 0 -#define R_PORT_PB_DIR__dir4__dir4__output 1 -#define R_PORT_PB_DIR__dir3__dir3__input 0 -#define R_PORT_PB_DIR__dir3__dir3__output 1 -#define R_PORT_PB_DIR__dir2__dir2__input 0 -#define R_PORT_PB_DIR__dir2__dir2__output 1 -#define R_PORT_PB_DIR__dir1__dir1__input 0 -#define R_PORT_PB_DIR__dir1__dir1__output 1 -#define R_PORT_PB_DIR__dir0__dir0__input 0 -#define R_PORT_PB_DIR__dir0__dir0__output 1 - -#endif - -/* - * R_PORT_PB_I2C - * - type: WO - * - addr: 0xb000003b - * - group: General port configuration registers - */ - -#if USE_GROUP__General_port_configuration_registers - -#define R_PORT_PB_I2C__ADDR (REG_TYPECAST_BYTE 0xb000003b) - -#ifndef REG_NO_SHADOW -#define R_PORT_PB_I2C__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_PORT_PB_SET + 3)) -#define R_PORT_PB_I2C__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_PORT_PB_SET + 3)) -#else /* REG_NO_SHADOW */ -#define R_PORT_PB_I2C__SADDR (REG_STYPECAST_BYTE (®_shadow__hwregs)) -#define R_PORT_PB_I2C__IADDR (REG_STYPECAST_BYTE (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_PORT_PB_I2C__STYPECAST REG_STYPECAST_BYTE -#define R_PORT_PB_I2C__SVAL REG_SVAL_SHADOW -#define R_PORT_PB_I2C__SVAL_I REG_SVAL_I_SHADOW -#define R_PORT_PB_I2C__TYPECAST REG_TYPECAST_BYTE -#define R_PORT_PB_I2C__TYPE (REG_BYTE) -#define R_PORT_PB_I2C__GET REG_GET_WO -#define R_PORT_PB_I2C__IGET REG_IGET_WO -#define R_PORT_PB_I2C__SET REG_SET_WO -#define R_PORT_PB_I2C__ISET REG_ISET_WO -#define R_PORT_PB_I2C__SET_VAL REG_SET_VAL_WO -#define R_PORT_PB_I2C__EQL REG_EQL_WO -#define R_PORT_PB_I2C__IEQL REG_IEQL_WO -#define R_PORT_PB_I2C__RD REG_RD_WO -#define R_PORT_PB_I2C__IRD REG_IRD_WO -#define R_PORT_PB_I2C__WR REG_WR_WO -#define R_PORT_PB_I2C__IWR REG_IWR_WO - -#define R_PORT_PB_I2C__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_PORT_PB_I2C__syncser3__syncser3__MASK 0x00000020U -#define R_PORT_PB_I2C__syncser1__syncser1__MASK 0x00000010U -#define R_PORT_PB_I2C__i2c_en__i2c_en__MASK 0x00000008U -#define R_PORT_PB_I2C__i2c_d__i2c_d__MASK 0x00000004U -#define R_PORT_PB_I2C__i2c_clk__i2c_clk__MASK 0x00000002U -#define R_PORT_PB_I2C__i2c_oe___i2c_oe___MASK 0x00000001U - -#define R_PORT_PB_I2C__syncser3__MAX 0x1 -#define R_PORT_PB_I2C__syncser1__MAX 0x1 -#define R_PORT_PB_I2C__i2c_en__MAX 0x1 -#define R_PORT_PB_I2C__i2c_d__MAX 1 -#define R_PORT_PB_I2C__i2c_clk__MAX 1 -#define R_PORT_PB_I2C__i2c_oe___MAX 0x1 - -#define R_PORT_PB_I2C__syncser3__MIN 0 -#define R_PORT_PB_I2C__syncser1__MIN 0 -#define R_PORT_PB_I2C__i2c_en__MIN 0 -#define R_PORT_PB_I2C__i2c_d__MIN 0 -#define R_PORT_PB_I2C__i2c_clk__MIN 0 -#define R_PORT_PB_I2C__i2c_oe___MIN 0 - -#define R_PORT_PB_I2C__syncser3__BITNR 5 -#define R_PORT_PB_I2C__syncser1__BITNR 4 -#define R_PORT_PB_I2C__i2c_en__BITNR 3 -#define R_PORT_PB_I2C__i2c_d__BITNR 2 -#define R_PORT_PB_I2C__i2c_clk__BITNR 1 -#define R_PORT_PB_I2C__i2c_oe___BITNR 0 - -#define R_PORT_PB_I2C__syncser3__syncser3__VAL REG_VAL_ENUM -#define R_PORT_PB_I2C__syncser1__syncser1__VAL REG_VAL_ENUM -#define R_PORT_PB_I2C__i2c_en__i2c_en__VAL REG_VAL_ENUM -#define R_PORT_PB_I2C__i2c_d__i2c_d__VAL REG_VAL_VAL -#define R_PORT_PB_I2C__i2c_clk__i2c_clk__VAL REG_VAL_VAL -#define R_PORT_PB_I2C__i2c_oe___i2c_oe___VAL REG_VAL_ENUM - -#define R_PORT_PB_I2C__syncser3__syncser3__port_cs 0 -#define R_PORT_PB_I2C__syncser3__syncser3__ss3extra 1 -#define R_PORT_PB_I2C__syncser1__syncser1__port_cs 0 -#define R_PORT_PB_I2C__syncser1__syncser1__ss1extra 1 -#define R_PORT_PB_I2C__i2c_en__i2c_en__off 0 -#define R_PORT_PB_I2C__i2c_en__i2c_en__on 1 -#define R_PORT_PB_I2C__i2c_oe___i2c_oe___disable 1 -#define R_PORT_PB_I2C__i2c_oe___i2c_oe___enable 0 - -#endif - -/* - * R_PORT_PB_READ - * - type: RO - * - addr: 0xb0000038 - * - group: General port configuration registers - */ - -#if USE_GROUP__General_port_configuration_registers - -#define R_PORT_PB_READ__ADDR (REG_TYPECAST_UDWORD 0xb0000038) -#define R_PORT_PB_READ__SVAL REG_SVAL_SHADOW -#define R_PORT_PB_READ__SVAL_I REG_SVAL_I_SHADOW -#define R_PORT_PB_READ__TYPECAST REG_TYPECAST_UDWORD -#define R_PORT_PB_READ__TYPE (REG_UDWORD) -#define R_PORT_PB_READ__GET REG_GET_RO -#define R_PORT_PB_READ__IGET REG_IGET_RO -#define R_PORT_PB_READ__SET REG_SET_RO -#define R_PORT_PB_READ__ISET REG_ISET_RO -#define R_PORT_PB_READ__SET_VAL REG_SET_VAL_RO -#define R_PORT_PB_READ__EQL REG_EQL_RO -#define R_PORT_PB_READ__IEQL REG_IEQL_RO -#define R_PORT_PB_READ__RD REG_RD_RO -#define R_PORT_PB_READ__IRD REG_IRD_RO -#define R_PORT_PB_READ__WR REG_WR_RO -#define R_PORT_PB_READ__IWR REG_IWR_RO - -#define R_PORT_PB_READ__READ(addr) \ - (*(addr)) - -#define R_PORT_PB_READ__data_in__data_in__MASK 0x000000ffU - -#define R_PORT_PB_READ__data_in__MAX 255 - -#define R_PORT_PB_READ__data_in__MIN 0 - -#define R_PORT_PB_READ__data_in__BITNR 0 - -#define R_PORT_PB_READ__data_in__data_in__VAL REG_VAL_VAL - - -#endif - -/* - * R_PORT_PB_SET - * - type: WO - * - addr: 0xb0000038 - * - group: General port configuration registers - */ - -#if USE_GROUP__General_port_configuration_registers - -#define R_PORT_PB_SET__ADDR (REG_TYPECAST_UDWORD 0xb0000038) - -#ifndef REG_NO_SHADOW -#define R_PORT_PB_SET__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_PORT_PB_SET + 0)) -#define R_PORT_PB_SET__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_PORT_PB_SET + 0)) -#else /* REG_NO_SHADOW */ -#define R_PORT_PB_SET__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_PORT_PB_SET__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_PORT_PB_SET__STYPECAST REG_STYPECAST_UDWORD -#define R_PORT_PB_SET__SVAL REG_SVAL_SHADOW -#define R_PORT_PB_SET__SVAL_I REG_SVAL_I_SHADOW -#define R_PORT_PB_SET__TYPECAST REG_TYPECAST_UDWORD -#define R_PORT_PB_SET__TYPE (REG_UDWORD) -#define R_PORT_PB_SET__GET REG_GET_WO -#define R_PORT_PB_SET__IGET REG_IGET_WO -#define R_PORT_PB_SET__SET REG_SET_WO -#define R_PORT_PB_SET__ISET REG_ISET_WO -#define R_PORT_PB_SET__SET_VAL REG_SET_VAL_WO -#define R_PORT_PB_SET__EQL REG_EQL_WO -#define R_PORT_PB_SET__IEQL REG_IEQL_WO -#define R_PORT_PB_SET__RD REG_RD_WO -#define R_PORT_PB_SET__IRD REG_IRD_WO -#define R_PORT_PB_SET__WR REG_WR_WO -#define R_PORT_PB_SET__IWR REG_IWR_WO - -#define R_PORT_PB_SET__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_PORT_PB_SET__syncser3__syncser3__MASK 0x20000000U -#define R_PORT_PB_SET__syncser1__syncser1__MASK 0x10000000U -#define R_PORT_PB_SET__i2c_en__i2c_en__MASK 0x08000000U -#define R_PORT_PB_SET__i2c_d__i2c_d__MASK 0x04000000U -#define R_PORT_PB_SET__i2c_clk__i2c_clk__MASK 0x02000000U -#define R_PORT_PB_SET__i2c_oe___i2c_oe___MASK 0x01000000U -#define R_PORT_PB_SET__cs7__cs7__MASK 0x00800000U -#define R_PORT_PB_SET__cs6__cs6__MASK 0x00400000U -#define R_PORT_PB_SET__cs5__cs5__MASK 0x00200000U -#define R_PORT_PB_SET__cs4__cs4__MASK 0x00100000U -#define R_PORT_PB_SET__cs3__cs3__MASK 0x00080000U -#define R_PORT_PB_SET__cs2__cs2__MASK 0x00040000U -#define R_PORT_PB_SET__scsi1__scsi1__MASK 0x00020000U -#define R_PORT_PB_SET__scsi0__scsi0__MASK 0x00010000U -#define R_PORT_PB_SET__dir7__dir7__MASK 0x00008000U -#define R_PORT_PB_SET__dir6__dir6__MASK 0x00004000U -#define R_PORT_PB_SET__dir5__dir5__MASK 0x00002000U -#define R_PORT_PB_SET__dir4__dir4__MASK 0x00001000U -#define R_PORT_PB_SET__dir3__dir3__MASK 0x00000800U -#define R_PORT_PB_SET__dir2__dir2__MASK 0x00000400U -#define R_PORT_PB_SET__dir1__dir1__MASK 0x00000200U -#define R_PORT_PB_SET__dir0__dir0__MASK 0x00000100U -#define R_PORT_PB_SET__data_out__data_out__MASK 0x000000ffU - -#define R_PORT_PB_SET__syncser3__MAX 0x1 -#define R_PORT_PB_SET__syncser1__MAX 0x1 -#define R_PORT_PB_SET__i2c_en__MAX 0x1 -#define R_PORT_PB_SET__i2c_d__MAX 1 -#define R_PORT_PB_SET__i2c_clk__MAX 1 -#define R_PORT_PB_SET__i2c_oe___MAX 0x1 -#define R_PORT_PB_SET__cs7__MAX 0x1 -#define R_PORT_PB_SET__cs6__MAX 0x1 -#define R_PORT_PB_SET__cs5__MAX 0x1 -#define R_PORT_PB_SET__cs4__MAX 0x1 -#define R_PORT_PB_SET__cs3__MAX 0x1 -#define R_PORT_PB_SET__cs2__MAX 0x1 -#define R_PORT_PB_SET__scsi1__MAX 0x1 -#define R_PORT_PB_SET__scsi0__MAX 0x1 -#define R_PORT_PB_SET__dir7__MAX 0x1 -#define R_PORT_PB_SET__dir6__MAX 0x1 -#define R_PORT_PB_SET__dir5__MAX 0x1 -#define R_PORT_PB_SET__dir4__MAX 0x1 -#define R_PORT_PB_SET__dir3__MAX 0x1 -#define R_PORT_PB_SET__dir2__MAX 0x1 -#define R_PORT_PB_SET__dir1__MAX 0x1 -#define R_PORT_PB_SET__dir0__MAX 0x1 -#define R_PORT_PB_SET__data_out__MAX 255 - -#define R_PORT_PB_SET__syncser3__MIN 0 -#define R_PORT_PB_SET__syncser1__MIN 0 -#define R_PORT_PB_SET__i2c_en__MIN 0 -#define R_PORT_PB_SET__i2c_d__MIN 0 -#define R_PORT_PB_SET__i2c_clk__MIN 0 -#define R_PORT_PB_SET__i2c_oe___MIN 0 -#define R_PORT_PB_SET__cs7__MIN 0 -#define R_PORT_PB_SET__cs6__MIN 0 -#define R_PORT_PB_SET__cs5__MIN 0 -#define R_PORT_PB_SET__cs4__MIN 0 -#define R_PORT_PB_SET__cs3__MIN 0 -#define R_PORT_PB_SET__cs2__MIN 0 -#define R_PORT_PB_SET__scsi1__MIN 0 -#define R_PORT_PB_SET__scsi0__MIN 0 -#define R_PORT_PB_SET__dir7__MIN 0 -#define R_PORT_PB_SET__dir6__MIN 0 -#define R_PORT_PB_SET__dir5__MIN 0 -#define R_PORT_PB_SET__dir4__MIN 0 -#define R_PORT_PB_SET__dir3__MIN 0 -#define R_PORT_PB_SET__dir2__MIN 0 -#define R_PORT_PB_SET__dir1__MIN 0 -#define R_PORT_PB_SET__dir0__MIN 0 -#define R_PORT_PB_SET__data_out__MIN 0 - -#define R_PORT_PB_SET__syncser3__BITNR 29 -#define R_PORT_PB_SET__syncser1__BITNR 28 -#define R_PORT_PB_SET__i2c_en__BITNR 27 -#define R_PORT_PB_SET__i2c_d__BITNR 26 -#define R_PORT_PB_SET__i2c_clk__BITNR 25 -#define R_PORT_PB_SET__i2c_oe___BITNR 24 -#define R_PORT_PB_SET__cs7__BITNR 23 -#define R_PORT_PB_SET__cs6__BITNR 22 -#define R_PORT_PB_SET__cs5__BITNR 21 -#define R_PORT_PB_SET__cs4__BITNR 20 -#define R_PORT_PB_SET__cs3__BITNR 19 -#define R_PORT_PB_SET__cs2__BITNR 18 -#define R_PORT_PB_SET__scsi1__BITNR 17 -#define R_PORT_PB_SET__scsi0__BITNR 16 -#define R_PORT_PB_SET__dir7__BITNR 15 -#define R_PORT_PB_SET__dir6__BITNR 14 -#define R_PORT_PB_SET__dir5__BITNR 13 -#define R_PORT_PB_SET__dir4__BITNR 12 -#define R_PORT_PB_SET__dir3__BITNR 11 -#define R_PORT_PB_SET__dir2__BITNR 10 -#define R_PORT_PB_SET__dir1__BITNR 9 -#define R_PORT_PB_SET__dir0__BITNR 8 -#define R_PORT_PB_SET__data_out__BITNR 0 - -#define R_PORT_PB_SET__syncser3__syncser3__VAL REG_VAL_ENUM -#define R_PORT_PB_SET__syncser1__syncser1__VAL REG_VAL_ENUM -#define R_PORT_PB_SET__i2c_en__i2c_en__VAL REG_VAL_ENUM -#define R_PORT_PB_SET__i2c_d__i2c_d__VAL REG_VAL_VAL -#define R_PORT_PB_SET__i2c_clk__i2c_clk__VAL REG_VAL_VAL -#define R_PORT_PB_SET__i2c_oe___i2c_oe___VAL REG_VAL_ENUM -#define R_PORT_PB_SET__cs7__cs7__VAL REG_VAL_ENUM -#define R_PORT_PB_SET__cs6__cs6__VAL REG_VAL_ENUM -#define R_PORT_PB_SET__cs5__cs5__VAL REG_VAL_ENUM -#define R_PORT_PB_SET__cs4__cs4__VAL REG_VAL_ENUM -#define R_PORT_PB_SET__cs3__cs3__VAL REG_VAL_ENUM -#define R_PORT_PB_SET__cs2__cs2__VAL REG_VAL_ENUM -#define R_PORT_PB_SET__scsi1__scsi1__VAL REG_VAL_ENUM -#define R_PORT_PB_SET__scsi0__scsi0__VAL REG_VAL_ENUM -#define R_PORT_PB_SET__dir7__dir7__VAL REG_VAL_ENUM -#define R_PORT_PB_SET__dir6__dir6__VAL REG_VAL_ENUM -#define R_PORT_PB_SET__dir5__dir5__VAL REG_VAL_ENUM -#define R_PORT_PB_SET__dir4__dir4__VAL REG_VAL_ENUM -#define R_PORT_PB_SET__dir3__dir3__VAL REG_VAL_ENUM -#define R_PORT_PB_SET__dir2__dir2__VAL REG_VAL_ENUM -#define R_PORT_PB_SET__dir1__dir1__VAL REG_VAL_ENUM -#define R_PORT_PB_SET__dir0__dir0__VAL REG_VAL_ENUM -#define R_PORT_PB_SET__data_out__data_out__VAL REG_VAL_VAL - -#define R_PORT_PB_SET__syncser3__syncser3__port_cs 0 -#define R_PORT_PB_SET__syncser3__syncser3__ss3extra 1 -#define R_PORT_PB_SET__syncser1__syncser1__port_cs 0 -#define R_PORT_PB_SET__syncser1__syncser1__ss1extra 1 -#define R_PORT_PB_SET__i2c_en__i2c_en__off 0 -#define R_PORT_PB_SET__i2c_en__i2c_en__on 1 -#define R_PORT_PB_SET__i2c_oe___i2c_oe___disable 1 -#define R_PORT_PB_SET__i2c_oe___i2c_oe___enable 0 -#define R_PORT_PB_SET__cs7__cs7__cs 1 -#define R_PORT_PB_SET__cs7__cs7__port 0 -#define R_PORT_PB_SET__cs6__cs6__cs 1 -#define R_PORT_PB_SET__cs6__cs6__port 0 -#define R_PORT_PB_SET__cs5__cs5__cs 1 -#define R_PORT_PB_SET__cs5__cs5__port 0 -#define R_PORT_PB_SET__cs4__cs4__cs 1 -#define R_PORT_PB_SET__cs4__cs4__port 0 -#define R_PORT_PB_SET__cs3__cs3__cs 1 -#define R_PORT_PB_SET__cs3__cs3__port 0 -#define R_PORT_PB_SET__cs2__cs2__cs 1 -#define R_PORT_PB_SET__cs2__cs2__port 0 -#define R_PORT_PB_SET__scsi1__scsi1__enph 1 -#define R_PORT_PB_SET__scsi1__scsi1__port_cs 0 -#define R_PORT_PB_SET__scsi0__scsi0__enph 1 -#define R_PORT_PB_SET__scsi0__scsi0__port_cs 0 -#define R_PORT_PB_SET__dir7__dir7__input 0 -#define R_PORT_PB_SET__dir7__dir7__output 1 -#define R_PORT_PB_SET__dir6__dir6__input 0 -#define R_PORT_PB_SET__dir6__dir6__output 1 -#define R_PORT_PB_SET__dir5__dir5__input 0 -#define R_PORT_PB_SET__dir5__dir5__output 1 -#define R_PORT_PB_SET__dir4__dir4__input 0 -#define R_PORT_PB_SET__dir4__dir4__output 1 -#define R_PORT_PB_SET__dir3__dir3__input 0 -#define R_PORT_PB_SET__dir3__dir3__output 1 -#define R_PORT_PB_SET__dir2__dir2__input 0 -#define R_PORT_PB_SET__dir2__dir2__output 1 -#define R_PORT_PB_SET__dir1__dir1__input 0 -#define R_PORT_PB_SET__dir1__dir1__output 1 -#define R_PORT_PB_SET__dir0__dir0__input 0 -#define R_PORT_PB_SET__dir0__dir0__output 1 - -#endif - -/* - * R_PRESCALE_STATUS - * - type: RO - * - addr: 0xb00000f0 - * - group: Timer registers - */ - -#if USE_GROUP__Timer_registers - -#define R_PRESCALE_STATUS__ADDR (REG_TYPECAST_UDWORD 0xb00000f0) -#define R_PRESCALE_STATUS__SVAL REG_SVAL_SHADOW -#define R_PRESCALE_STATUS__SVAL_I REG_SVAL_I_SHADOW -#define R_PRESCALE_STATUS__TYPECAST REG_TYPECAST_UDWORD -#define R_PRESCALE_STATUS__TYPE (REG_UDWORD) -#define R_PRESCALE_STATUS__GET REG_GET_RO -#define R_PRESCALE_STATUS__IGET REG_IGET_RO -#define R_PRESCALE_STATUS__SET REG_SET_RO -#define R_PRESCALE_STATUS__ISET REG_ISET_RO -#define R_PRESCALE_STATUS__SET_VAL REG_SET_VAL_RO -#define R_PRESCALE_STATUS__EQL REG_EQL_RO -#define R_PRESCALE_STATUS__IEQL REG_IEQL_RO -#define R_PRESCALE_STATUS__RD REG_RD_RO -#define R_PRESCALE_STATUS__IRD REG_IRD_RO -#define R_PRESCALE_STATUS__WR REG_WR_RO -#define R_PRESCALE_STATUS__IWR REG_IWR_RO - -#define R_PRESCALE_STATUS__READ(addr) \ - (*(addr)) - -#define R_PRESCALE_STATUS__ser_status__ser_status__MASK 0xffff0000U -#define R_PRESCALE_STATUS__tim_status__tim_status__MASK 0x0000ffffU - -#define R_PRESCALE_STATUS__ser_status__MAX 0xffff -#define R_PRESCALE_STATUS__tim_status__MAX 0xffff - -#define R_PRESCALE_STATUS__ser_status__MIN 0 -#define R_PRESCALE_STATUS__tim_status__MIN 0 - -#define R_PRESCALE_STATUS__ser_status__BITNR 16 -#define R_PRESCALE_STATUS__tim_status__BITNR 0 - -#define R_PRESCALE_STATUS__ser_status__ser_status__VAL REG_VAL_VAL -#define R_PRESCALE_STATUS__tim_status__tim_status__VAL REG_VAL_VAL - - -#endif - -/* - * R_REC_COUNTERS - * - type: RO - * - addr: 0xb00000a4 - * - group: Network interface registers - */ - -#if USE_GROUP__Network_interface_registers - -#define R_REC_COUNTERS__ADDR (REG_TYPECAST_UDWORD 0xb00000a4) -#define R_REC_COUNTERS__SVAL REG_SVAL_SHADOW -#define R_REC_COUNTERS__SVAL_I REG_SVAL_I_SHADOW -#define R_REC_COUNTERS__TYPECAST REG_TYPECAST_UDWORD -#define R_REC_COUNTERS__TYPE (REG_UDWORD) -#define R_REC_COUNTERS__GET REG_GET_RO -#define R_REC_COUNTERS__IGET REG_IGET_RO -#define R_REC_COUNTERS__SET REG_SET_RO -#define R_REC_COUNTERS__ISET REG_ISET_RO -#define R_REC_COUNTERS__SET_VAL REG_SET_VAL_RO -#define R_REC_COUNTERS__EQL REG_EQL_RO -#define R_REC_COUNTERS__IEQL REG_IEQL_RO -#define R_REC_COUNTERS__RD REG_RD_RO -#define R_REC_COUNTERS__IRD REG_IRD_RO -#define R_REC_COUNTERS__WR REG_WR_RO -#define R_REC_COUNTERS__IWR REG_IWR_RO - -#define R_REC_COUNTERS__READ(addr) \ - (*(addr)) - -#define R_REC_COUNTERS__congestion__congestion__MASK 0xff000000U -#define R_REC_COUNTERS__oversize__oversize__MASK 0x00ff0000U -#define R_REC_COUNTERS__alignment_error__alignment_error__MASK 0x0000ff00U -#define R_REC_COUNTERS__crc_error__crc_error__MASK 0x000000ffU - -#define R_REC_COUNTERS__congestion__MAX 0xff -#define R_REC_COUNTERS__oversize__MAX 0xff -#define R_REC_COUNTERS__alignment_error__MAX 0xff -#define R_REC_COUNTERS__crc_error__MAX 0xff - -#define R_REC_COUNTERS__congestion__MIN 0 -#define R_REC_COUNTERS__oversize__MIN 0 -#define R_REC_COUNTERS__alignment_error__MIN 0 -#define R_REC_COUNTERS__crc_error__MIN 0 - -#define R_REC_COUNTERS__congestion__BITNR 24 -#define R_REC_COUNTERS__oversize__BITNR 16 -#define R_REC_COUNTERS__alignment_error__BITNR 8 -#define R_REC_COUNTERS__crc_error__BITNR 0 - -#define R_REC_COUNTERS__congestion__congestion__VAL REG_VAL_VAL -#define R_REC_COUNTERS__oversize__oversize__VAL REG_VAL_VAL -#define R_REC_COUNTERS__alignment_error__alignment_error__VAL REG_VAL_VAL -#define R_REC_COUNTERS__crc_error__crc_error__VAL REG_VAL_VAL - - -#endif - -/* - * R_SCSI0_CMD - * - type: WO - * - addr: 0xb0000042 - * - group: SCSI registers - */ - -#if USE_GROUP__SCSI_registers - -#define R_SCSI0_CMD__ADDR (REG_TYPECAST_BYTE 0xb0000042) - -#ifndef REG_NO_SHADOW -#define R_SCSI0_CMD__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_ATA_CTRL_DATA + 2)) -#define R_SCSI0_CMD__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_ATA_CTRL_DATA + 2)) -#else /* REG_NO_SHADOW */ -#define R_SCSI0_CMD__SADDR (REG_STYPECAST_BYTE (®_shadow__hwregs)) -#define R_SCSI0_CMD__IADDR (REG_STYPECAST_BYTE (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_SCSI0_CMD__STYPECAST REG_STYPECAST_BYTE -#define R_SCSI0_CMD__SVAL REG_SVAL_SHADOW -#define R_SCSI0_CMD__SVAL_I REG_SVAL_I_SHADOW -#define R_SCSI0_CMD__TYPECAST REG_TYPECAST_BYTE -#define R_SCSI0_CMD__TYPE (REG_BYTE) -#define R_SCSI0_CMD__GET REG_GET_WO -#define R_SCSI0_CMD__IGET REG_IGET_WO -#define R_SCSI0_CMD__SET REG_SET_WO -#define R_SCSI0_CMD__ISET REG_ISET_WO -#define R_SCSI0_CMD__SET_VAL REG_SET_VAL_WO -#define R_SCSI0_CMD__EQL REG_EQL_WO -#define R_SCSI0_CMD__IEQL REG_IEQL_WO -#define R_SCSI0_CMD__RD REG_RD_WO -#define R_SCSI0_CMD__IRD REG_IRD_WO -#define R_SCSI0_CMD__WR REG_WR_WO -#define R_SCSI0_CMD__IWR REG_IWR_WO - -#define R_SCSI0_CMD__WRITE(addr,value) \ - (*(addr) = (value)) - -/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */ -#define R_SCSI0_CMD__FIRST 0 -#define R_SCSI0_CMD__IOFFSET 12 -#define R_SCSI0_CMD__LAST 1 -#define R_SCSI0_CMD__OFFSET 16 -#define R_SCSI0_CMD__SOFFSET 12 -/* end */ - -#define R_SCSI0_CMD__asynch_setup__asynch_setup__MASK 0x000000f0U -#define R_SCSI0_CMD__command__command__MASK 0x0000000fU - -#define R_SCSI0_CMD__asynch_setup__MAX 0xf -#define R_SCSI0_CMD__command__MAX 0xf - -#define R_SCSI0_CMD__asynch_setup__MIN 0 -#define R_SCSI0_CMD__command__MIN 0 - -#define R_SCSI0_CMD__asynch_setup__BITNR 4 -#define R_SCSI0_CMD__command__BITNR 0 - -#define R_SCSI0_CMD__asynch_setup__asynch_setup__VAL REG_VAL_VAL -#define R_SCSI0_CMD__command__command__VAL REG_VAL_ENUM - -#define R_SCSI0_CMD__command__command__arb_only 6 -#define R_SCSI0_CMD__command__command__full_din_1 0 -#define R_SCSI0_CMD__command__command__full_din_3 8 -#define R_SCSI0_CMD__command__command__full_dout_1 1 -#define R_SCSI0_CMD__command__command__full_dout_3 9 -#define R_SCSI0_CMD__command__command__full_stat_1 2 -#define R_SCSI0_CMD__command__command__full_stat_3 10 -#define R_SCSI0_CMD__command__command__man_data_in 11 -#define R_SCSI0_CMD__command__command__man_data_out 12 -#define R_SCSI0_CMD__command__command__man_rat 13 -#define R_SCSI0_CMD__command__command__resel_din 3 -#define R_SCSI0_CMD__command__command__resel_dout 4 -#define R_SCSI0_CMD__command__command__resel_stat 5 - -#endif - -/* - * R_SCSI0_CMD_DATA - * - type: WO - * - addr: 0xb0000040 - * - group: SCSI registers - */ - -#if USE_GROUP__SCSI_registers - -#define R_SCSI0_CMD_DATA__ADDR (REG_TYPECAST_UDWORD 0xb0000040) - -#ifndef REG_NO_SHADOW -#define R_SCSI0_CMD_DATA__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_ATA_CTRL_DATA + 0)) -#define R_SCSI0_CMD_DATA__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_ATA_CTRL_DATA + 0)) -#else /* REG_NO_SHADOW */ -#define R_SCSI0_CMD_DATA__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_SCSI0_CMD_DATA__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_SCSI0_CMD_DATA__STYPECAST REG_STYPECAST_UDWORD -#define R_SCSI0_CMD_DATA__SVAL REG_SVAL_SHADOW -#define R_SCSI0_CMD_DATA__SVAL_I REG_SVAL_I_SHADOW -#define R_SCSI0_CMD_DATA__TYPECAST REG_TYPECAST_UDWORD -#define R_SCSI0_CMD_DATA__TYPE (REG_UDWORD) -#define R_SCSI0_CMD_DATA__GET REG_GET_WO -#define R_SCSI0_CMD_DATA__IGET REG_IGET_WO -#define R_SCSI0_CMD_DATA__SET REG_SET_WO -#define R_SCSI0_CMD_DATA__ISET REG_ISET_WO -#define R_SCSI0_CMD_DATA__SET_VAL REG_SET_VAL_WO -#define R_SCSI0_CMD_DATA__EQL REG_EQL_WO -#define R_SCSI0_CMD_DATA__IEQL REG_IEQL_WO -#define R_SCSI0_CMD_DATA__RD REG_RD_WO -#define R_SCSI0_CMD_DATA__IRD REG_IRD_WO -#define R_SCSI0_CMD_DATA__WR REG_WR_WO -#define R_SCSI0_CMD_DATA__IWR REG_IWR_WO - -#define R_SCSI0_CMD_DATA__WRITE(addr,value) \ - (*(addr) = (value)) - -/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */ -#define R_SCSI0_CMD_DATA__FIRST 0 -#define R_SCSI0_CMD_DATA__IOFFSET 12 -#define R_SCSI0_CMD_DATA__LAST 1 -#define R_SCSI0_CMD_DATA__OFFSET 16 -#define R_SCSI0_CMD_DATA__SOFFSET 12 -/* end */ - -#define R_SCSI0_CMD_DATA__parity_in__parity_in__MASK 0x04000000U -#define R_SCSI0_CMD_DATA__skip__skip__MASK 0x02000000U -#define R_SCSI0_CMD_DATA__clr_status__clr_status__MASK 0x01000000U -#define R_SCSI0_CMD_DATA__asynch_setup__asynch_setup__MASK 0x00f00000U -#define R_SCSI0_CMD_DATA__command__command__MASK 0x000f0000U -#define R_SCSI0_CMD_DATA__data_out__data_out__MASK 0x0000ffffU - -#define R_SCSI0_CMD_DATA__parity_in__MAX 0x1 -#define R_SCSI0_CMD_DATA__skip__MAX 0x1 -#define R_SCSI0_CMD_DATA__clr_status__MAX 0x1 -#define R_SCSI0_CMD_DATA__asynch_setup__MAX 0xf -#define R_SCSI0_CMD_DATA__command__MAX 0xf -#define R_SCSI0_CMD_DATA__data_out__MAX 0xffff - -#define R_SCSI0_CMD_DATA__parity_in__MIN 0 -#define R_SCSI0_CMD_DATA__skip__MIN 0 -#define R_SCSI0_CMD_DATA__clr_status__MIN 0 -#define R_SCSI0_CMD_DATA__asynch_setup__MIN 0 -#define R_SCSI0_CMD_DATA__command__MIN 0 -#define R_SCSI0_CMD_DATA__data_out__MIN 0 - -#define R_SCSI0_CMD_DATA__parity_in__BITNR 26 -#define R_SCSI0_CMD_DATA__skip__BITNR 25 -#define R_SCSI0_CMD_DATA__clr_status__BITNR 24 -#define R_SCSI0_CMD_DATA__asynch_setup__BITNR 20 -#define R_SCSI0_CMD_DATA__command__BITNR 16 -#define R_SCSI0_CMD_DATA__data_out__BITNR 0 - -#define R_SCSI0_CMD_DATA__parity_in__parity_in__VAL REG_VAL_ENUM -#define R_SCSI0_CMD_DATA__skip__skip__VAL REG_VAL_ENUM -#define R_SCSI0_CMD_DATA__clr_status__clr_status__VAL REG_VAL_ENUM -#define R_SCSI0_CMD_DATA__asynch_setup__asynch_setup__VAL REG_VAL_VAL -#define R_SCSI0_CMD_DATA__command__command__VAL REG_VAL_ENUM -#define R_SCSI0_CMD_DATA__data_out__data_out__VAL REG_VAL_VAL - -#define R_SCSI0_CMD_DATA__parity_in__parity_in__off 1 -#define R_SCSI0_CMD_DATA__parity_in__parity_in__on 0 -#define R_SCSI0_CMD_DATA__skip__skip__off 0 -#define R_SCSI0_CMD_DATA__skip__skip__on 1 -#define R_SCSI0_CMD_DATA__clr_status__clr_status__nop 0 -#define R_SCSI0_CMD_DATA__clr_status__clr_status__yes 1 -#define R_SCSI0_CMD_DATA__command__command__arb_only 6 -#define R_SCSI0_CMD_DATA__command__command__full_din_1 0 -#define R_SCSI0_CMD_DATA__command__command__full_din_3 8 -#define R_SCSI0_CMD_DATA__command__command__full_dout_1 1 -#define R_SCSI0_CMD_DATA__command__command__full_dout_3 9 -#define R_SCSI0_CMD_DATA__command__command__full_stat_1 2 -#define R_SCSI0_CMD_DATA__command__command__full_stat_3 10 -#define R_SCSI0_CMD_DATA__command__command__man_data_in 11 -#define R_SCSI0_CMD_DATA__command__command__man_data_out 12 -#define R_SCSI0_CMD_DATA__command__command__man_rat 13 -#define R_SCSI0_CMD_DATA__command__command__resel_din 3 -#define R_SCSI0_CMD_DATA__command__command__resel_dout 4 -#define R_SCSI0_CMD_DATA__command__command__resel_stat 5 - -#endif - -/* - * R_SCSI0_CTRL - * - type: WO - * - addr: 0xb0000044 - * - group: SCSI registers - */ - -#if USE_GROUP__SCSI_registers - -#define R_SCSI0_CTRL__ADDR (REG_TYPECAST_UDWORD 0xb0000044) - -#ifndef REG_NO_SHADOW -#define R_SCSI0_CTRL__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_ATA_CONFIG + 0)) -#define R_SCSI0_CTRL__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_ATA_CONFIG + 0)) -#else /* REG_NO_SHADOW */ -#define R_SCSI0_CTRL__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_SCSI0_CTRL__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_SCSI0_CTRL__STYPECAST REG_STYPECAST_UDWORD -#define R_SCSI0_CTRL__SVAL REG_SVAL_SHADOW -#define R_SCSI0_CTRL__SVAL_I REG_SVAL_I_SHADOW -#define R_SCSI0_CTRL__TYPECAST REG_TYPECAST_UDWORD -#define R_SCSI0_CTRL__TYPE (REG_UDWORD) -#define R_SCSI0_CTRL__GET REG_GET_WO -#define R_SCSI0_CTRL__IGET REG_IGET_WO -#define R_SCSI0_CTRL__SET REG_SET_WO -#define R_SCSI0_CTRL__ISET REG_ISET_WO -#define R_SCSI0_CTRL__SET_VAL REG_SET_VAL_WO -#define R_SCSI0_CTRL__EQL REG_EQL_WO -#define R_SCSI0_CTRL__IEQL REG_IEQL_WO -#define R_SCSI0_CTRL__RD REG_RD_WO -#define R_SCSI0_CTRL__IRD REG_IRD_WO -#define R_SCSI0_CTRL__WR REG_WR_WO -#define R_SCSI0_CTRL__IWR REG_IWR_WO - -#define R_SCSI0_CTRL__WRITE(addr,value) \ - (*(addr) = (value)) - -/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */ -#define R_SCSI0_CTRL__FIRST 0 -#define R_SCSI0_CTRL__IOFFSET 12 -#define R_SCSI0_CTRL__LAST 1 -#define R_SCSI0_CTRL__OFFSET 16 -#define R_SCSI0_CTRL__SOFFSET 12 -/* end */ - -#define R_SCSI0_CTRL__id_type__id_type__MASK 0x80000000U -#define R_SCSI0_CTRL__sel_timeout__sel_timeout__MASK 0x7f000000U -#define R_SCSI0_CTRL__synch_per__synch_per__MASK 0x00ff0000U -#define R_SCSI0_CTRL__rst__rst__MASK 0x00008000U -#define R_SCSI0_CTRL__atn__atn__MASK 0x00004000U -#define R_SCSI0_CTRL__my_id__my_id__MASK 0x00001e00U -#define R_SCSI0_CTRL__target_id__target_id__MASK 0x000000f0U -#define R_SCSI0_CTRL__fast_20__fast_20__MASK 0x00000008U -#define R_SCSI0_CTRL__bus_width__bus_width__MASK 0x00000004U -#define R_SCSI0_CTRL__synch__synch__MASK 0x00000002U -#define R_SCSI0_CTRL__enable__enable__MASK 0x00000001U - -#define R_SCSI0_CTRL__id_type__MAX 0x1 -#define R_SCSI0_CTRL__sel_timeout__MAX 0x7f -#define R_SCSI0_CTRL__synch_per__MAX 0xff -#define R_SCSI0_CTRL__rst__MAX 0x1 -#define R_SCSI0_CTRL__atn__MAX 0x1 -#define R_SCSI0_CTRL__my_id__MAX 0xf -#define R_SCSI0_CTRL__target_id__MAX 0xf -#define R_SCSI0_CTRL__fast_20__MAX 0x1 -#define R_SCSI0_CTRL__bus_width__MAX 0x1 -#define R_SCSI0_CTRL__synch__MAX 0x1 -#define R_SCSI0_CTRL__enable__MAX 0x1 - -#define R_SCSI0_CTRL__id_type__MIN 0 -#define R_SCSI0_CTRL__sel_timeout__MIN 0 -#define R_SCSI0_CTRL__synch_per__MIN 0 -#define R_SCSI0_CTRL__rst__MIN 0 -#define R_SCSI0_CTRL__atn__MIN 0 -#define R_SCSI0_CTRL__my_id__MIN 0 -#define R_SCSI0_CTRL__target_id__MIN 0 -#define R_SCSI0_CTRL__fast_20__MIN 0 -#define R_SCSI0_CTRL__bus_width__MIN 0 -#define R_SCSI0_CTRL__synch__MIN 0 -#define R_SCSI0_CTRL__enable__MIN 0 - -#define R_SCSI0_CTRL__id_type__BITNR 31 -#define R_SCSI0_CTRL__sel_timeout__BITNR 24 -#define R_SCSI0_CTRL__synch_per__BITNR 16 -#define R_SCSI0_CTRL__rst__BITNR 15 -#define R_SCSI0_CTRL__atn__BITNR 14 -#define R_SCSI0_CTRL__my_id__BITNR 9 -#define R_SCSI0_CTRL__target_id__BITNR 4 -#define R_SCSI0_CTRL__fast_20__BITNR 3 -#define R_SCSI0_CTRL__bus_width__BITNR 2 -#define R_SCSI0_CTRL__synch__BITNR 1 -#define R_SCSI0_CTRL__enable__BITNR 0 - -#define R_SCSI0_CTRL__id_type__id_type__VAL REG_VAL_ENUM -#define R_SCSI0_CTRL__sel_timeout__sel_timeout__VAL REG_VAL_VAL -#define R_SCSI0_CTRL__synch_per__synch_per__VAL REG_VAL_VAL -#define R_SCSI0_CTRL__rst__rst__VAL REG_VAL_ENUM -#define R_SCSI0_CTRL__atn__atn__VAL REG_VAL_ENUM -#define R_SCSI0_CTRL__my_id__my_id__VAL REG_VAL_VAL -#define R_SCSI0_CTRL__target_id__target_id__VAL REG_VAL_VAL -#define R_SCSI0_CTRL__fast_20__fast_20__VAL REG_VAL_ENUM -#define R_SCSI0_CTRL__bus_width__bus_width__VAL REG_VAL_ENUM -#define R_SCSI0_CTRL__synch__synch__VAL REG_VAL_ENUM -#define R_SCSI0_CTRL__enable__enable__VAL REG_VAL_ENUM - -#define R_SCSI0_CTRL__id_type__id_type__hardware 0 -#define R_SCSI0_CTRL__id_type__id_type__software 1 -#define R_SCSI0_CTRL__rst__rst__no 0 -#define R_SCSI0_CTRL__rst__rst__yes 1 -#define R_SCSI0_CTRL__atn__atn__no 0 -#define R_SCSI0_CTRL__atn__atn__yes 1 -#define R_SCSI0_CTRL__fast_20__fast_20__no 0 -#define R_SCSI0_CTRL__fast_20__fast_20__yes 1 -#define R_SCSI0_CTRL__bus_width__bus_width__narrow 0 -#define R_SCSI0_CTRL__bus_width__bus_width__wide 1 -#define R_SCSI0_CTRL__synch__synch__asynch 0 -#define R_SCSI0_CTRL__synch__synch__synch 1 -#define R_SCSI0_CTRL__enable__enable__off 0 -#define R_SCSI0_CTRL__enable__enable__on 1 - -#endif - -/* - * R_SCSI0_DATA - * - type: WO - * - addr: 0xb0000040 - * - group: SCSI registers - */ - -#if USE_GROUP__SCSI_registers - -#define R_SCSI0_DATA__ADDR (REG_TYPECAST_UWORD 0xb0000040) - -#ifndef REG_NO_SHADOW -#define R_SCSI0_DATA__SADDR (REG_STYPECAST_UWORD (reg_shadow__hwregs.R_ATA_CTRL_DATA + 0)) -#define R_SCSI0_DATA__IADDR (REG_STYPECAST_UWORD (reg_initiated__hwregs.R_ATA_CTRL_DATA + 0)) -#else /* REG_NO_SHADOW */ -#define R_SCSI0_DATA__SADDR (REG_STYPECAST_UWORD (®_shadow__hwregs)) -#define R_SCSI0_DATA__IADDR (REG_STYPECAST_UWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_SCSI0_DATA__STYPECAST REG_STYPECAST_UWORD -#define R_SCSI0_DATA__SVAL REG_SVAL_SHADOW -#define R_SCSI0_DATA__SVAL_I REG_SVAL_I_SHADOW -#define R_SCSI0_DATA__TYPECAST REG_TYPECAST_UWORD -#define R_SCSI0_DATA__TYPE (REG_UWORD) -#define R_SCSI0_DATA__GET REG_GET_WO -#define R_SCSI0_DATA__IGET REG_IGET_WO -#define R_SCSI0_DATA__SET REG_SET_WO -#define R_SCSI0_DATA__ISET REG_ISET_WO -#define R_SCSI0_DATA__SET_VAL REG_SET_VAL_WO -#define R_SCSI0_DATA__EQL REG_EQL_WO -#define R_SCSI0_DATA__IEQL REG_IEQL_WO -#define R_SCSI0_DATA__RD REG_RD_WO -#define R_SCSI0_DATA__IRD REG_IRD_WO -#define R_SCSI0_DATA__WR REG_WR_WO -#define R_SCSI0_DATA__IWR REG_IWR_WO - -#define R_SCSI0_DATA__WRITE(addr,value) \ - (*(addr) = (value)) - -/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */ -#define R_SCSI0_DATA__FIRST 0 -#define R_SCSI0_DATA__IOFFSET 12 -#define R_SCSI0_DATA__LAST 1 -#define R_SCSI0_DATA__OFFSET 16 -#define R_SCSI0_DATA__SOFFSET 12 -/* end */ - -#define R_SCSI0_DATA__data_out__data_out__MASK 0x0000ffffU - -#define R_SCSI0_DATA__data_out__MAX 0xffff - -#define R_SCSI0_DATA__data_out__MIN 0 - -#define R_SCSI0_DATA__data_out__BITNR 0 - -#define R_SCSI0_DATA__data_out__data_out__VAL REG_VAL_VAL - - -#endif - -/* - * R_SCSI0_DATA_IN - * - type: RO - * - addr: 0xb0000040 - * - group: SCSI registers - */ - -#if USE_GROUP__SCSI_registers - -#define R_SCSI0_DATA_IN__ADDR (REG_TYPECAST_UWORD 0xb0000040) -#define R_SCSI0_DATA_IN__SVAL REG_SVAL_SHADOW -#define R_SCSI0_DATA_IN__SVAL_I REG_SVAL_I_SHADOW -#define R_SCSI0_DATA_IN__TYPECAST REG_TYPECAST_UWORD -#define R_SCSI0_DATA_IN__TYPE (REG_UWORD) -#define R_SCSI0_DATA_IN__GET REG_GET_RO -#define R_SCSI0_DATA_IN__IGET REG_IGET_RO -#define R_SCSI0_DATA_IN__SET REG_SET_RO -#define R_SCSI0_DATA_IN__ISET REG_ISET_RO -#define R_SCSI0_DATA_IN__SET_VAL REG_SET_VAL_RO -#define R_SCSI0_DATA_IN__EQL REG_EQL_RO -#define R_SCSI0_DATA_IN__IEQL REG_IEQL_RO -#define R_SCSI0_DATA_IN__RD REG_RD_RO -#define R_SCSI0_DATA_IN__IRD REG_IRD_RO -#define R_SCSI0_DATA_IN__WR REG_WR_RO -#define R_SCSI0_DATA_IN__IWR REG_IWR_RO - -#define R_SCSI0_DATA_IN__READ(addr) \ - (*(addr)) - -/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */ -#define R_SCSI0_DATA_IN__FIRST 0 -#define R_SCSI0_DATA_IN__LAST 1 -#define R_SCSI0_DATA_IN__OFFSET 16 -/* end */ - -#define R_SCSI0_DATA_IN__data_in__data_in__MASK 0x0000ffffU - -#define R_SCSI0_DATA_IN__data_in__MAX 0xffff - -#define R_SCSI0_DATA_IN__data_in__MIN 0 - -#define R_SCSI0_DATA_IN__data_in__BITNR 0 - -#define R_SCSI0_DATA_IN__data_in__data_in__VAL REG_VAL_VAL - - -#endif - -/* - * R_SCSI0_STATUS - * - type: RO - * - addr: 0xb0000048 - * - group: SCSI registers - */ - -#if USE_GROUP__SCSI_registers - -#define R_SCSI0_STATUS__ADDR (REG_TYPECAST_UDWORD 0xb0000048) -#define R_SCSI0_STATUS__SVAL REG_SVAL_SHADOW -#define R_SCSI0_STATUS__SVAL_I REG_SVAL_I_SHADOW -#define R_SCSI0_STATUS__TYPECAST REG_TYPECAST_UDWORD -#define R_SCSI0_STATUS__TYPE (REG_UDWORD) -#define R_SCSI0_STATUS__GET REG_GET_RO -#define R_SCSI0_STATUS__IGET REG_IGET_RO -#define R_SCSI0_STATUS__SET REG_SET_RO -#define R_SCSI0_STATUS__ISET REG_ISET_RO -#define R_SCSI0_STATUS__SET_VAL REG_SET_VAL_RO -#define R_SCSI0_STATUS__EQL REG_EQL_RO -#define R_SCSI0_STATUS__IEQL REG_IEQL_RO -#define R_SCSI0_STATUS__RD REG_RD_RO -#define R_SCSI0_STATUS__IRD REG_IRD_RO -#define R_SCSI0_STATUS__WR REG_WR_RO -#define R_SCSI0_STATUS__IWR REG_IWR_RO - -#define R_SCSI0_STATUS__READ(addr) \ - (*(addr)) - -/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */ -#define R_SCSI0_STATUS__FIRST 0 -#define R_SCSI0_STATUS__LAST 1 -#define R_SCSI0_STATUS__OFFSET 16 -/* end */ - -#define R_SCSI0_STATUS__tst_arb_won__tst_arb_won__MASK 0x00800000U -#define R_SCSI0_STATUS__tst_resel__tst_resel__MASK 0x00400000U -#define R_SCSI0_STATUS__parity_error__parity_error__MASK 0x00200000U -#define R_SCSI0_STATUS__bus_reset__bus_reset__MASK 0x00100000U -#define R_SCSI0_STATUS__resel_target__resel_target__MASK 0x00078000U -#define R_SCSI0_STATUS__resel__resel__MASK 0x00004000U -#define R_SCSI0_STATUS__curr_phase__curr_phase__MASK 0x00003800U -#define R_SCSI0_STATUS__last_seq_step__last_seq_step__MASK 0x000007c0U -#define R_SCSI0_STATUS__valid_status__valid_status__MASK 0x00000020U -#define R_SCSI0_STATUS__seq_status__seq_status__MASK 0x0000001fU - -#define R_SCSI0_STATUS__tst_arb_won__MAX 0x1 -#define R_SCSI0_STATUS__tst_resel__MAX 0x1 -#define R_SCSI0_STATUS__parity_error__MAX 0x1 -#define R_SCSI0_STATUS__bus_reset__MAX 0x1 -#define R_SCSI0_STATUS__resel_target__MAX 0xf -#define R_SCSI0_STATUS__resel__MAX 0x1 -#define R_SCSI0_STATUS__curr_phase__MAX 0x7 -#define R_SCSI0_STATUS__last_seq_step__MAX 0x1f -#define R_SCSI0_STATUS__valid_status__MAX 0x1 -#define R_SCSI0_STATUS__seq_status__MAX 0x1f - -#define R_SCSI0_STATUS__tst_arb_won__MIN 0 -#define R_SCSI0_STATUS__tst_resel__MIN 0 -#define R_SCSI0_STATUS__parity_error__MIN 0 -#define R_SCSI0_STATUS__bus_reset__MIN 0 -#define R_SCSI0_STATUS__resel_target__MIN 0 -#define R_SCSI0_STATUS__resel__MIN 0 -#define R_SCSI0_STATUS__curr_phase__MIN 0 -#define R_SCSI0_STATUS__last_seq_step__MIN 0 -#define R_SCSI0_STATUS__valid_status__MIN 0 -#define R_SCSI0_STATUS__seq_status__MIN 0 - -#define R_SCSI0_STATUS__tst_arb_won__BITNR 23 -#define R_SCSI0_STATUS__tst_resel__BITNR 22 -#define R_SCSI0_STATUS__parity_error__BITNR 21 -#define R_SCSI0_STATUS__bus_reset__BITNR 20 -#define R_SCSI0_STATUS__resel_target__BITNR 15 -#define R_SCSI0_STATUS__resel__BITNR 14 -#define R_SCSI0_STATUS__curr_phase__BITNR 11 -#define R_SCSI0_STATUS__last_seq_step__BITNR 6 -#define R_SCSI0_STATUS__valid_status__BITNR 5 -#define R_SCSI0_STATUS__seq_status__BITNR 0 - -#define R_SCSI0_STATUS__tst_arb_won__tst_arb_won__VAL REG_VAL_VAL -#define R_SCSI0_STATUS__tst_resel__tst_resel__VAL REG_VAL_VAL -#define R_SCSI0_STATUS__parity_error__parity_error__VAL REG_VAL_VAL -#define R_SCSI0_STATUS__bus_reset__bus_reset__VAL REG_VAL_ENUM -#define R_SCSI0_STATUS__resel_target__resel_target__VAL REG_VAL_VAL -#define R_SCSI0_STATUS__resel__resel__VAL REG_VAL_ENUM -#define R_SCSI0_STATUS__curr_phase__curr_phase__VAL REG_VAL_ENUM -#define R_SCSI0_STATUS__last_seq_step__last_seq_step__VAL REG_VAL_ENUM -#define R_SCSI0_STATUS__valid_status__valid_status__VAL REG_VAL_ENUM -#define R_SCSI0_STATUS__seq_status__seq_status__VAL REG_VAL_ENUM - -#define R_SCSI0_STATUS__bus_reset__bus_reset__no 0 -#define R_SCSI0_STATUS__bus_reset__bus_reset__yes 1 -#define R_SCSI0_STATUS__resel__resel__no 0 -#define R_SCSI0_STATUS__resel__resel__yes 1 -#define R_SCSI0_STATUS__curr_phase__curr_phase__ph_command 2 -#define R_SCSI0_STATUS__curr_phase__curr_phase__ph_data_in 5 -#define R_SCSI0_STATUS__curr_phase__curr_phase__ph_data_out 4 -#define R_SCSI0_STATUS__curr_phase__curr_phase__ph_msg_in 7 -#define R_SCSI0_STATUS__curr_phase__curr_phase__ph_msg_out 6 -#define R_SCSI0_STATUS__curr_phase__curr_phase__ph_resel 1 -#define R_SCSI0_STATUS__curr_phase__curr_phase__ph_status 3 -#define R_SCSI0_STATUS__curr_phase__curr_phase__ph_undef 0 -#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_answer 3 -#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_arbitrate 8 -#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_asynch_din 9 -#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_asynch_dout 25 -#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_asynch_dout_end 11 -#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_bus_free 24 -#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_cc 31 -#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_iwr 27 -#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_iwr_cc 23 -#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_iwr_good 14 -#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_manual 28 -#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_manual_din_prot 18 -#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_manual_req 10 -#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_msg_1 2 -#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_msg_2 6 -#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_msg_3 22 -#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_resel_req 29 -#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_sdp_disc 7 -#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_synch_din 13 -#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_synch_din_ack 12 -#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_synch_din_ack_perr 5 -#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_synch_din_perr 1 -#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_synch_dout 0 -#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_synch_dout_ack 4 -#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_transf_cmd 30 -#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_transfer_done 15 -#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_wait_free_cc 20 -#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_wait_free_disc 21 -#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_wait_free_iwr_cc 17 -#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_wait_free_sdp_disc 16 -#define R_SCSI0_STATUS__valid_status__valid_status__no 0 -#define R_SCSI0_STATUS__valid_status__valid_status__yes 1 -#define R_SCSI0_STATUS__seq_status__seq_status__info_arb_lost 4 -#define R_SCSI0_STATUS__seq_status__seq_status__info_bus_free 13 -#define R_SCSI0_STATUS__seq_status__seq_status__info_bus_reset 11 -#define R_SCSI0_STATUS__seq_status__seq_status__info_illegal_bf 12 -#define R_SCSI0_STATUS__seq_status__seq_status__info_illegal_op 7 -#define R_SCSI0_STATUS__seq_status__seq_status__info_parity_error 1 -#define R_SCSI0_STATUS__seq_status__seq_status__info_rec_recvd 8 -#define R_SCSI0_STATUS__seq_status__seq_status__info_reselected 9 -#define R_SCSI0_STATUS__seq_status__seq_status__info_sel_timeout 5 -#define R_SCSI0_STATUS__seq_status__seq_status__info_seq_complete 0 -#define R_SCSI0_STATUS__seq_status__seq_status__info_unexp_bf 6 -#define R_SCSI0_STATUS__seq_status__seq_status__info_unexp_ph_change 3 -#define R_SCSI0_STATUS__seq_status__seq_status__info_unhandled_msg_in 2 -#define R_SCSI0_STATUS__seq_status__seq_status__info_unhandled_status 10 - -#endif - -/* - * R_SCSI0_STATUS_CTRL - * - type: WO - * - addr: 0xb0000043 - * - group: SCSI registers - */ - -#if USE_GROUP__SCSI_registers - -#define R_SCSI0_STATUS_CTRL__ADDR (REG_TYPECAST_BYTE 0xb0000043) - -#ifndef REG_NO_SHADOW -#define R_SCSI0_STATUS_CTRL__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_ATA_CTRL_DATA + 3)) -#define R_SCSI0_STATUS_CTRL__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_ATA_CTRL_DATA + 3)) -#else /* REG_NO_SHADOW */ -#define R_SCSI0_STATUS_CTRL__SADDR (REG_STYPECAST_BYTE (®_shadow__hwregs)) -#define R_SCSI0_STATUS_CTRL__IADDR (REG_STYPECAST_BYTE (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_SCSI0_STATUS_CTRL__STYPECAST REG_STYPECAST_BYTE -#define R_SCSI0_STATUS_CTRL__SVAL REG_SVAL_SHADOW -#define R_SCSI0_STATUS_CTRL__SVAL_I REG_SVAL_I_SHADOW -#define R_SCSI0_STATUS_CTRL__TYPECAST REG_TYPECAST_BYTE -#define R_SCSI0_STATUS_CTRL__TYPE (REG_BYTE) -#define R_SCSI0_STATUS_CTRL__GET REG_GET_WO -#define R_SCSI0_STATUS_CTRL__IGET REG_IGET_WO -#define R_SCSI0_STATUS_CTRL__SET REG_SET_WO -#define R_SCSI0_STATUS_CTRL__ISET REG_ISET_WO -#define R_SCSI0_STATUS_CTRL__SET_VAL REG_SET_VAL_WO -#define R_SCSI0_STATUS_CTRL__EQL REG_EQL_WO -#define R_SCSI0_STATUS_CTRL__IEQL REG_IEQL_WO -#define R_SCSI0_STATUS_CTRL__RD REG_RD_WO -#define R_SCSI0_STATUS_CTRL__IRD REG_IRD_WO -#define R_SCSI0_STATUS_CTRL__WR REG_WR_WO -#define R_SCSI0_STATUS_CTRL__IWR REG_IWR_WO - -#define R_SCSI0_STATUS_CTRL__WRITE(addr,value) \ - (*(addr) = (value)) - -/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */ -#define R_SCSI0_STATUS_CTRL__FIRST 0 -#define R_SCSI0_STATUS_CTRL__IOFFSET 12 -#define R_SCSI0_STATUS_CTRL__LAST 1 -#define R_SCSI0_STATUS_CTRL__OFFSET 16 -#define R_SCSI0_STATUS_CTRL__SOFFSET 12 -/* end */ - -#define R_SCSI0_STATUS_CTRL__parity_in__parity_in__MASK 0x00000004U -#define R_SCSI0_STATUS_CTRL__skip__skip__MASK 0x00000002U -#define R_SCSI0_STATUS_CTRL__clr_status__clr_status__MASK 0x00000001U - -#define R_SCSI0_STATUS_CTRL__parity_in__MAX 0x1 -#define R_SCSI0_STATUS_CTRL__skip__MAX 0x1 -#define R_SCSI0_STATUS_CTRL__clr_status__MAX 0x1 - -#define R_SCSI0_STATUS_CTRL__parity_in__MIN 0 -#define R_SCSI0_STATUS_CTRL__skip__MIN 0 -#define R_SCSI0_STATUS_CTRL__clr_status__MIN 0 - -#define R_SCSI0_STATUS_CTRL__parity_in__BITNR 2 -#define R_SCSI0_STATUS_CTRL__skip__BITNR 1 -#define R_SCSI0_STATUS_CTRL__clr_status__BITNR 0 - -#define R_SCSI0_STATUS_CTRL__parity_in__parity_in__VAL REG_VAL_ENUM -#define R_SCSI0_STATUS_CTRL__skip__skip__VAL REG_VAL_ENUM -#define R_SCSI0_STATUS_CTRL__clr_status__clr_status__VAL REG_VAL_ENUM - -#define R_SCSI0_STATUS_CTRL__parity_in__parity_in__off 1 -#define R_SCSI0_STATUS_CTRL__parity_in__parity_in__on 0 -#define R_SCSI0_STATUS_CTRL__skip__skip__off 0 -#define R_SCSI0_STATUS_CTRL__skip__skip__on 1 -#define R_SCSI0_STATUS_CTRL__clr_status__clr_status__nop 0 -#define R_SCSI0_STATUS_CTRL__clr_status__clr_status__yes 1 - -#endif - -/* - * R_SCSI1_CMD - * - type: WO - * - addr: 0xb0000052 - * - group: SCSI registers - */ - -#if USE_GROUP__SCSI_registers - -#define R_SCSI1_CMD__ADDR (REG_TYPECAST_BYTE 0xb0000052) - -#ifndef REG_NO_SHADOW -#define R_SCSI1_CMD__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_PAR1_CTRL_DATA + 2)) -#define R_SCSI1_CMD__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_PAR1_CTRL_DATA + 2)) -#else /* REG_NO_SHADOW */ -#define R_SCSI1_CMD__SADDR (REG_STYPECAST_BYTE (®_shadow__hwregs)) -#define R_SCSI1_CMD__IADDR (REG_STYPECAST_BYTE (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_SCSI1_CMD__STYPECAST REG_STYPECAST_BYTE -#define R_SCSI1_CMD__SVAL REG_SVAL_SHADOW -#define R_SCSI1_CMD__SVAL_I REG_SVAL_I_SHADOW -#define R_SCSI1_CMD__TYPECAST REG_TYPECAST_BYTE -#define R_SCSI1_CMD__TYPE (REG_BYTE) -#define R_SCSI1_CMD__GET REG_GET_WO -#define R_SCSI1_CMD__IGET REG_IGET_WO -#define R_SCSI1_CMD__SET REG_SET_WO -#define R_SCSI1_CMD__ISET REG_ISET_WO -#define R_SCSI1_CMD__SET_VAL REG_SET_VAL_WO -#define R_SCSI1_CMD__EQL REG_EQL_WO -#define R_SCSI1_CMD__IEQL REG_IEQL_WO -#define R_SCSI1_CMD__RD REG_RD_WO -#define R_SCSI1_CMD__IRD REG_IRD_WO -#define R_SCSI1_CMD__WR REG_WR_WO -#define R_SCSI1_CMD__IWR REG_IWR_WO - -#define R_SCSI1_CMD__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_SCSI1_CMD__asynch_setup__asynch_setup__MASK 0x000000f0U -#define R_SCSI1_CMD__command__command__MASK 0x0000000fU - -#define R_SCSI1_CMD__asynch_setup__MAX 0xf -#define R_SCSI1_CMD__command__MAX 0xf - -#define R_SCSI1_CMD__asynch_setup__MIN 0 -#define R_SCSI1_CMD__command__MIN 0 - -#define R_SCSI1_CMD__asynch_setup__BITNR 4 -#define R_SCSI1_CMD__command__BITNR 0 - -#define R_SCSI1_CMD__asynch_setup__asynch_setup__VAL REG_VAL_VAL -#define R_SCSI1_CMD__command__command__VAL REG_VAL_ENUM - -#define R_SCSI1_CMD__command__command__arb_only 6 -#define R_SCSI1_CMD__command__command__full_din_1 0 -#define R_SCSI1_CMD__command__command__full_din_3 8 -#define R_SCSI1_CMD__command__command__full_dout_1 1 -#define R_SCSI1_CMD__command__command__full_dout_3 9 -#define R_SCSI1_CMD__command__command__full_stat_1 2 -#define R_SCSI1_CMD__command__command__full_stat_3 10 -#define R_SCSI1_CMD__command__command__man_data_in 11 -#define R_SCSI1_CMD__command__command__man_data_out 12 -#define R_SCSI1_CMD__command__command__man_rat 13 -#define R_SCSI1_CMD__command__command__resel_din 3 -#define R_SCSI1_CMD__command__command__resel_dout 4 -#define R_SCSI1_CMD__command__command__resel_stat 5 - -#endif - -/* - * R_SCSI1_CMD_DATA - * - type: WO - * - addr: 0xb0000050 - * - group: SCSI registers - */ - -#if USE_GROUP__SCSI_registers - -#define R_SCSI1_CMD_DATA__ADDR (REG_TYPECAST_UDWORD 0xb0000050) - -#ifndef REG_NO_SHADOW -#define R_SCSI1_CMD_DATA__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_PAR1_CTRL_DATA + 0)) -#define R_SCSI1_CMD_DATA__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_PAR1_CTRL_DATA + 0)) -#else /* REG_NO_SHADOW */ -#define R_SCSI1_CMD_DATA__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_SCSI1_CMD_DATA__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_SCSI1_CMD_DATA__STYPECAST REG_STYPECAST_UDWORD -#define R_SCSI1_CMD_DATA__SVAL REG_SVAL_SHADOW -#define R_SCSI1_CMD_DATA__SVAL_I REG_SVAL_I_SHADOW -#define R_SCSI1_CMD_DATA__TYPECAST REG_TYPECAST_UDWORD -#define R_SCSI1_CMD_DATA__TYPE (REG_UDWORD) -#define R_SCSI1_CMD_DATA__GET REG_GET_WO -#define R_SCSI1_CMD_DATA__IGET REG_IGET_WO -#define R_SCSI1_CMD_DATA__SET REG_SET_WO -#define R_SCSI1_CMD_DATA__ISET REG_ISET_WO -#define R_SCSI1_CMD_DATA__SET_VAL REG_SET_VAL_WO -#define R_SCSI1_CMD_DATA__EQL REG_EQL_WO -#define R_SCSI1_CMD_DATA__IEQL REG_IEQL_WO -#define R_SCSI1_CMD_DATA__RD REG_RD_WO -#define R_SCSI1_CMD_DATA__IRD REG_IRD_WO -#define R_SCSI1_CMD_DATA__WR REG_WR_WO -#define R_SCSI1_CMD_DATA__IWR REG_IWR_WO - -#define R_SCSI1_CMD_DATA__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_SCSI1_CMD_DATA__parity_in__parity_in__MASK 0x04000000U -#define R_SCSI1_CMD_DATA__skip__skip__MASK 0x02000000U -#define R_SCSI1_CMD_DATA__clr_status__clr_status__MASK 0x01000000U -#define R_SCSI1_CMD_DATA__asynch_setup__asynch_setup__MASK 0x00f00000U -#define R_SCSI1_CMD_DATA__command__command__MASK 0x000f0000U -#define R_SCSI1_CMD_DATA__data_out__data_out__MASK 0x0000ffffU - -#define R_SCSI1_CMD_DATA__parity_in__MAX 0x1 -#define R_SCSI1_CMD_DATA__skip__MAX 0x1 -#define R_SCSI1_CMD_DATA__clr_status__MAX 0x1 -#define R_SCSI1_CMD_DATA__asynch_setup__MAX 0xf -#define R_SCSI1_CMD_DATA__command__MAX 0xf -#define R_SCSI1_CMD_DATA__data_out__MAX 0xffff - -#define R_SCSI1_CMD_DATA__parity_in__MIN 0 -#define R_SCSI1_CMD_DATA__skip__MIN 0 -#define R_SCSI1_CMD_DATA__clr_status__MIN 0 -#define R_SCSI1_CMD_DATA__asynch_setup__MIN 0 -#define R_SCSI1_CMD_DATA__command__MIN 0 -#define R_SCSI1_CMD_DATA__data_out__MIN 0 - -#define R_SCSI1_CMD_DATA__parity_in__BITNR 26 -#define R_SCSI1_CMD_DATA__skip__BITNR 25 -#define R_SCSI1_CMD_DATA__clr_status__BITNR 24 -#define R_SCSI1_CMD_DATA__asynch_setup__BITNR 20 -#define R_SCSI1_CMD_DATA__command__BITNR 16 -#define R_SCSI1_CMD_DATA__data_out__BITNR 0 - -#define R_SCSI1_CMD_DATA__parity_in__parity_in__VAL REG_VAL_ENUM -#define R_SCSI1_CMD_DATA__skip__skip__VAL REG_VAL_ENUM -#define R_SCSI1_CMD_DATA__clr_status__clr_status__VAL REG_VAL_ENUM -#define R_SCSI1_CMD_DATA__asynch_setup__asynch_setup__VAL REG_VAL_VAL -#define R_SCSI1_CMD_DATA__command__command__VAL REG_VAL_ENUM -#define R_SCSI1_CMD_DATA__data_out__data_out__VAL REG_VAL_VAL - -#define R_SCSI1_CMD_DATA__parity_in__parity_in__off 1 -#define R_SCSI1_CMD_DATA__parity_in__parity_in__on 0 -#define R_SCSI1_CMD_DATA__skip__skip__off 0 -#define R_SCSI1_CMD_DATA__skip__skip__on 1 -#define R_SCSI1_CMD_DATA__clr_status__clr_status__nop 0 -#define R_SCSI1_CMD_DATA__clr_status__clr_status__yes 1 -#define R_SCSI1_CMD_DATA__command__command__arb_only 6 -#define R_SCSI1_CMD_DATA__command__command__full_din_1 0 -#define R_SCSI1_CMD_DATA__command__command__full_din_3 8 -#define R_SCSI1_CMD_DATA__command__command__full_dout_1 1 -#define R_SCSI1_CMD_DATA__command__command__full_dout_3 9 -#define R_SCSI1_CMD_DATA__command__command__full_stat_1 2 -#define R_SCSI1_CMD_DATA__command__command__full_stat_3 10 -#define R_SCSI1_CMD_DATA__command__command__man_data_in 11 -#define R_SCSI1_CMD_DATA__command__command__man_data_out 12 -#define R_SCSI1_CMD_DATA__command__command__man_rat 13 -#define R_SCSI1_CMD_DATA__command__command__resel_din 3 -#define R_SCSI1_CMD_DATA__command__command__resel_dout 4 -#define R_SCSI1_CMD_DATA__command__command__resel_stat 5 - -#endif - -/* - * R_SCSI1_CTRL - * - type: WO - * - addr: 0xb0000054 - * - group: SCSI registers - */ - -#if USE_GROUP__SCSI_registers - -#define R_SCSI1_CTRL__ADDR (REG_TYPECAST_UDWORD 0xb0000054) - -#ifndef REG_NO_SHADOW -#define R_SCSI1_CTRL__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_PAR1_CONFIG + 0)) -#define R_SCSI1_CTRL__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_PAR1_CONFIG + 0)) -#else /* REG_NO_SHADOW */ -#define R_SCSI1_CTRL__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_SCSI1_CTRL__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_SCSI1_CTRL__STYPECAST REG_STYPECAST_UDWORD -#define R_SCSI1_CTRL__SVAL REG_SVAL_SHADOW -#define R_SCSI1_CTRL__SVAL_I REG_SVAL_I_SHADOW -#define R_SCSI1_CTRL__TYPECAST REG_TYPECAST_UDWORD -#define R_SCSI1_CTRL__TYPE (REG_UDWORD) -#define R_SCSI1_CTRL__GET REG_GET_WO -#define R_SCSI1_CTRL__IGET REG_IGET_WO -#define R_SCSI1_CTRL__SET REG_SET_WO -#define R_SCSI1_CTRL__ISET REG_ISET_WO -#define R_SCSI1_CTRL__SET_VAL REG_SET_VAL_WO -#define R_SCSI1_CTRL__EQL REG_EQL_WO -#define R_SCSI1_CTRL__IEQL REG_IEQL_WO -#define R_SCSI1_CTRL__RD REG_RD_WO -#define R_SCSI1_CTRL__IRD REG_IRD_WO -#define R_SCSI1_CTRL__WR REG_WR_WO -#define R_SCSI1_CTRL__IWR REG_IWR_WO - -#define R_SCSI1_CTRL__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_SCSI1_CTRL__id_type__id_type__MASK 0x80000000U -#define R_SCSI1_CTRL__sel_timeout__sel_timeout__MASK 0x7f000000U -#define R_SCSI1_CTRL__synch_per__synch_per__MASK 0x00ff0000U -#define R_SCSI1_CTRL__rst__rst__MASK 0x00008000U -#define R_SCSI1_CTRL__atn__atn__MASK 0x00004000U -#define R_SCSI1_CTRL__my_id__my_id__MASK 0x00001e00U -#define R_SCSI1_CTRL__target_id__target_id__MASK 0x000000f0U -#define R_SCSI1_CTRL__fast_20__fast_20__MASK 0x00000008U -#define R_SCSI1_CTRL__bus_width__bus_width__MASK 0x00000004U -#define R_SCSI1_CTRL__synch__synch__MASK 0x00000002U -#define R_SCSI1_CTRL__enable__enable__MASK 0x00000001U - -#define R_SCSI1_CTRL__id_type__MAX 0x1 -#define R_SCSI1_CTRL__sel_timeout__MAX 0x7f -#define R_SCSI1_CTRL__synch_per__MAX 0xff -#define R_SCSI1_CTRL__rst__MAX 0x1 -#define R_SCSI1_CTRL__atn__MAX 0x1 -#define R_SCSI1_CTRL__my_id__MAX 0xf -#define R_SCSI1_CTRL__target_id__MAX 0xf -#define R_SCSI1_CTRL__fast_20__MAX 0x1 -#define R_SCSI1_CTRL__bus_width__MAX 0x1 -#define R_SCSI1_CTRL__synch__MAX 0x1 -#define R_SCSI1_CTRL__enable__MAX 0x1 - -#define R_SCSI1_CTRL__id_type__MIN 0 -#define R_SCSI1_CTRL__sel_timeout__MIN 0 -#define R_SCSI1_CTRL__synch_per__MIN 0 -#define R_SCSI1_CTRL__rst__MIN 0 -#define R_SCSI1_CTRL__atn__MIN 0 -#define R_SCSI1_CTRL__my_id__MIN 0 -#define R_SCSI1_CTRL__target_id__MIN 0 -#define R_SCSI1_CTRL__fast_20__MIN 0 -#define R_SCSI1_CTRL__bus_width__MIN 0 -#define R_SCSI1_CTRL__synch__MIN 0 -#define R_SCSI1_CTRL__enable__MIN 0 - -#define R_SCSI1_CTRL__id_type__BITNR 31 -#define R_SCSI1_CTRL__sel_timeout__BITNR 24 -#define R_SCSI1_CTRL__synch_per__BITNR 16 -#define R_SCSI1_CTRL__rst__BITNR 15 -#define R_SCSI1_CTRL__atn__BITNR 14 -#define R_SCSI1_CTRL__my_id__BITNR 9 -#define R_SCSI1_CTRL__target_id__BITNR 4 -#define R_SCSI1_CTRL__fast_20__BITNR 3 -#define R_SCSI1_CTRL__bus_width__BITNR 2 -#define R_SCSI1_CTRL__synch__BITNR 1 -#define R_SCSI1_CTRL__enable__BITNR 0 - -#define R_SCSI1_CTRL__id_type__id_type__VAL REG_VAL_ENUM -#define R_SCSI1_CTRL__sel_timeout__sel_timeout__VAL REG_VAL_VAL -#define R_SCSI1_CTRL__synch_per__synch_per__VAL REG_VAL_VAL -#define R_SCSI1_CTRL__rst__rst__VAL REG_VAL_ENUM -#define R_SCSI1_CTRL__atn__atn__VAL REG_VAL_ENUM -#define R_SCSI1_CTRL__my_id__my_id__VAL REG_VAL_VAL -#define R_SCSI1_CTRL__target_id__target_id__VAL REG_VAL_VAL -#define R_SCSI1_CTRL__fast_20__fast_20__VAL REG_VAL_ENUM -#define R_SCSI1_CTRL__bus_width__bus_width__VAL REG_VAL_ENUM -#define R_SCSI1_CTRL__synch__synch__VAL REG_VAL_ENUM -#define R_SCSI1_CTRL__enable__enable__VAL REG_VAL_ENUM - -#define R_SCSI1_CTRL__id_type__id_type__hardware 0 -#define R_SCSI1_CTRL__id_type__id_type__software 1 -#define R_SCSI1_CTRL__rst__rst__no 0 -#define R_SCSI1_CTRL__rst__rst__yes 1 -#define R_SCSI1_CTRL__atn__atn__no 0 -#define R_SCSI1_CTRL__atn__atn__yes 1 -#define R_SCSI1_CTRL__fast_20__fast_20__no 0 -#define R_SCSI1_CTRL__fast_20__fast_20__yes 1 -#define R_SCSI1_CTRL__bus_width__bus_width__narrow 0 -#define R_SCSI1_CTRL__bus_width__bus_width__wide 1 -#define R_SCSI1_CTRL__synch__synch__asynch 0 -#define R_SCSI1_CTRL__synch__synch__synch 1 -#define R_SCSI1_CTRL__enable__enable__off 0 -#define R_SCSI1_CTRL__enable__enable__on 1 - -#endif - -/* - * R_SCSI1_DATA - * - type: WO - * - addr: 0xb0000050 - * - group: SCSI registers - */ - -#if USE_GROUP__SCSI_registers - -#define R_SCSI1_DATA__ADDR (REG_TYPECAST_UWORD 0xb0000050) - -#ifndef REG_NO_SHADOW -#define R_SCSI1_DATA__SADDR (REG_STYPECAST_UWORD (reg_shadow__hwregs.R_PAR1_CTRL_DATA + 0)) -#define R_SCSI1_DATA__IADDR (REG_STYPECAST_UWORD (reg_initiated__hwregs.R_PAR1_CTRL_DATA + 0)) -#else /* REG_NO_SHADOW */ -#define R_SCSI1_DATA__SADDR (REG_STYPECAST_UWORD (®_shadow__hwregs)) -#define R_SCSI1_DATA__IADDR (REG_STYPECAST_UWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_SCSI1_DATA__STYPECAST REG_STYPECAST_UWORD -#define R_SCSI1_DATA__SVAL REG_SVAL_SHADOW -#define R_SCSI1_DATA__SVAL_I REG_SVAL_I_SHADOW -#define R_SCSI1_DATA__TYPECAST REG_TYPECAST_UWORD -#define R_SCSI1_DATA__TYPE (REG_UWORD) -#define R_SCSI1_DATA__GET REG_GET_WO -#define R_SCSI1_DATA__IGET REG_IGET_WO -#define R_SCSI1_DATA__SET REG_SET_WO -#define R_SCSI1_DATA__ISET REG_ISET_WO -#define R_SCSI1_DATA__SET_VAL REG_SET_VAL_WO -#define R_SCSI1_DATA__EQL REG_EQL_WO -#define R_SCSI1_DATA__IEQL REG_IEQL_WO -#define R_SCSI1_DATA__RD REG_RD_WO -#define R_SCSI1_DATA__IRD REG_IRD_WO -#define R_SCSI1_DATA__WR REG_WR_WO -#define R_SCSI1_DATA__IWR REG_IWR_WO - -#define R_SCSI1_DATA__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_SCSI1_DATA__data_out__data_out__MASK 0x0000ffffU - -#define R_SCSI1_DATA__data_out__MAX 0xffff - -#define R_SCSI1_DATA__data_out__MIN 0 - -#define R_SCSI1_DATA__data_out__BITNR 0 - -#define R_SCSI1_DATA__data_out__data_out__VAL REG_VAL_VAL - - -#endif - -/* - * R_SCSI1_DATA_IN - * - type: RO - * - addr: 0xb0000050 - * - group: SCSI registers - */ - -#if USE_GROUP__SCSI_registers - -#define R_SCSI1_DATA_IN__ADDR (REG_TYPECAST_UWORD 0xb0000050) -#define R_SCSI1_DATA_IN__SVAL REG_SVAL_SHADOW -#define R_SCSI1_DATA_IN__SVAL_I REG_SVAL_I_SHADOW -#define R_SCSI1_DATA_IN__TYPECAST REG_TYPECAST_UWORD -#define R_SCSI1_DATA_IN__TYPE (REG_UWORD) -#define R_SCSI1_DATA_IN__GET REG_GET_RO -#define R_SCSI1_DATA_IN__IGET REG_IGET_RO -#define R_SCSI1_DATA_IN__SET REG_SET_RO -#define R_SCSI1_DATA_IN__ISET REG_ISET_RO -#define R_SCSI1_DATA_IN__SET_VAL REG_SET_VAL_RO -#define R_SCSI1_DATA_IN__EQL REG_EQL_RO -#define R_SCSI1_DATA_IN__IEQL REG_IEQL_RO -#define R_SCSI1_DATA_IN__RD REG_RD_RO -#define R_SCSI1_DATA_IN__IRD REG_IRD_RO -#define R_SCSI1_DATA_IN__WR REG_WR_RO -#define R_SCSI1_DATA_IN__IWR REG_IWR_RO - -#define R_SCSI1_DATA_IN__READ(addr) \ - (*(addr)) - -#define R_SCSI1_DATA_IN__data_in__data_in__MASK 0x0000ffffU - -#define R_SCSI1_DATA_IN__data_in__MAX 0xffff - -#define R_SCSI1_DATA_IN__data_in__MIN 0 - -#define R_SCSI1_DATA_IN__data_in__BITNR 0 - -#define R_SCSI1_DATA_IN__data_in__data_in__VAL REG_VAL_VAL - - -#endif - -/* - * R_SCSI1_STATUS - * - type: RO - * - addr: 0xb0000058 - * - group: SCSI registers - */ - -#if USE_GROUP__SCSI_registers - -#define R_SCSI1_STATUS__ADDR (REG_TYPECAST_UDWORD 0xb0000058) -#define R_SCSI1_STATUS__SVAL REG_SVAL_SHADOW -#define R_SCSI1_STATUS__SVAL_I REG_SVAL_I_SHADOW -#define R_SCSI1_STATUS__TYPECAST REG_TYPECAST_UDWORD -#define R_SCSI1_STATUS__TYPE (REG_UDWORD) -#define R_SCSI1_STATUS__GET REG_GET_RO -#define R_SCSI1_STATUS__IGET REG_IGET_RO -#define R_SCSI1_STATUS__SET REG_SET_RO -#define R_SCSI1_STATUS__ISET REG_ISET_RO -#define R_SCSI1_STATUS__SET_VAL REG_SET_VAL_RO -#define R_SCSI1_STATUS__EQL REG_EQL_RO -#define R_SCSI1_STATUS__IEQL REG_IEQL_RO -#define R_SCSI1_STATUS__RD REG_RD_RO -#define R_SCSI1_STATUS__IRD REG_IRD_RO -#define R_SCSI1_STATUS__WR REG_WR_RO -#define R_SCSI1_STATUS__IWR REG_IWR_RO - -#define R_SCSI1_STATUS__READ(addr) \ - (*(addr)) - -#define R_SCSI1_STATUS__tst_arb_won__tst_arb_won__MASK 0x00800000U -#define R_SCSI1_STATUS__tst_resel__tst_resel__MASK 0x00400000U -#define R_SCSI1_STATUS__parity_error__parity_error__MASK 0x00200000U -#define R_SCSI1_STATUS__bus_reset__bus_reset__MASK 0x00100000U -#define R_SCSI1_STATUS__resel_target__resel_target__MASK 0x00078000U -#define R_SCSI1_STATUS__resel__resel__MASK 0x00004000U -#define R_SCSI1_STATUS__curr_phase__curr_phase__MASK 0x00003800U -#define R_SCSI1_STATUS__last_seq_step__last_seq_step__MASK 0x000007c0U -#define R_SCSI1_STATUS__valid_status__valid_status__MASK 0x00000020U -#define R_SCSI1_STATUS__seq_status__seq_status__MASK 0x0000001fU - -#define R_SCSI1_STATUS__tst_arb_won__MAX 0x1 -#define R_SCSI1_STATUS__tst_resel__MAX 0x1 -#define R_SCSI1_STATUS__parity_error__MAX 0x1 -#define R_SCSI1_STATUS__bus_reset__MAX 0x1 -#define R_SCSI1_STATUS__resel_target__MAX 0xf -#define R_SCSI1_STATUS__resel__MAX 0x1 -#define R_SCSI1_STATUS__curr_phase__MAX 0x7 -#define R_SCSI1_STATUS__last_seq_step__MAX 0x1f -#define R_SCSI1_STATUS__valid_status__MAX 0x1 -#define R_SCSI1_STATUS__seq_status__MAX 0x1f - -#define R_SCSI1_STATUS__tst_arb_won__MIN 0 -#define R_SCSI1_STATUS__tst_resel__MIN 0 -#define R_SCSI1_STATUS__parity_error__MIN 0 -#define R_SCSI1_STATUS__bus_reset__MIN 0 -#define R_SCSI1_STATUS__resel_target__MIN 0 -#define R_SCSI1_STATUS__resel__MIN 0 -#define R_SCSI1_STATUS__curr_phase__MIN 0 -#define R_SCSI1_STATUS__last_seq_step__MIN 0 -#define R_SCSI1_STATUS__valid_status__MIN 0 -#define R_SCSI1_STATUS__seq_status__MIN 0 - -#define R_SCSI1_STATUS__tst_arb_won__BITNR 23 -#define R_SCSI1_STATUS__tst_resel__BITNR 22 -#define R_SCSI1_STATUS__parity_error__BITNR 21 -#define R_SCSI1_STATUS__bus_reset__BITNR 20 -#define R_SCSI1_STATUS__resel_target__BITNR 15 -#define R_SCSI1_STATUS__resel__BITNR 14 -#define R_SCSI1_STATUS__curr_phase__BITNR 11 -#define R_SCSI1_STATUS__last_seq_step__BITNR 6 -#define R_SCSI1_STATUS__valid_status__BITNR 5 -#define R_SCSI1_STATUS__seq_status__BITNR 0 - -#define R_SCSI1_STATUS__tst_arb_won__tst_arb_won__VAL REG_VAL_VAL -#define R_SCSI1_STATUS__tst_resel__tst_resel__VAL REG_VAL_VAL -#define R_SCSI1_STATUS__parity_error__parity_error__VAL REG_VAL_VAL -#define R_SCSI1_STATUS__bus_reset__bus_reset__VAL REG_VAL_ENUM -#define R_SCSI1_STATUS__resel_target__resel_target__VAL REG_VAL_VAL -#define R_SCSI1_STATUS__resel__resel__VAL REG_VAL_ENUM -#define R_SCSI1_STATUS__curr_phase__curr_phase__VAL REG_VAL_ENUM -#define R_SCSI1_STATUS__last_seq_step__last_seq_step__VAL REG_VAL_ENUM -#define R_SCSI1_STATUS__valid_status__valid_status__VAL REG_VAL_ENUM -#define R_SCSI1_STATUS__seq_status__seq_status__VAL REG_VAL_ENUM - -#define R_SCSI1_STATUS__bus_reset__bus_reset__no 0 -#define R_SCSI1_STATUS__bus_reset__bus_reset__yes 1 -#define R_SCSI1_STATUS__resel__resel__no 0 -#define R_SCSI1_STATUS__resel__resel__yes 1 -#define R_SCSI1_STATUS__curr_phase__curr_phase__ph_command 2 -#define R_SCSI1_STATUS__curr_phase__curr_phase__ph_data_in 5 -#define R_SCSI1_STATUS__curr_phase__curr_phase__ph_data_out 4 -#define R_SCSI1_STATUS__curr_phase__curr_phase__ph_msg_in 7 -#define R_SCSI1_STATUS__curr_phase__curr_phase__ph_msg_out 6 -#define R_SCSI1_STATUS__curr_phase__curr_phase__ph_resel 1 -#define R_SCSI1_STATUS__curr_phase__curr_phase__ph_status 3 -#define R_SCSI1_STATUS__curr_phase__curr_phase__ph_undef 0 -#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_answer 3 -#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_arbitrate 8 -#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_asynch_din 9 -#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_asynch_dout 25 -#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_asynch_dout_end 11 -#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_bus_free 24 -#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_cc 31 -#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_iwr 27 -#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_iwr_cc 23 -#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_iwr_good 14 -#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_manual 28 -#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_manual_din_prot 18 -#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_manual_req 10 -#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_msg_1 2 -#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_msg_2 6 -#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_msg_3 22 -#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_resel_req 29 -#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_sdp_disc 7 -#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_synch_din 13 -#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_synch_din_ack 12 -#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_synch_din_ack_perr 5 -#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_synch_din_perr 1 -#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_synch_dout 0 -#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_synch_dout_ack 4 -#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_transf_cmd 30 -#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_transfer_done 15 -#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_wait_free_cc 20 -#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_wait_free_disc 21 -#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_wait_free_iwr_cc 17 -#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_wait_free_sdp_disc 16 -#define R_SCSI1_STATUS__valid_status__valid_status__no 0 -#define R_SCSI1_STATUS__valid_status__valid_status__yes 1 -#define R_SCSI1_STATUS__seq_status__seq_status__info_arb_lost 4 -#define R_SCSI1_STATUS__seq_status__seq_status__info_bus_free 13 -#define R_SCSI1_STATUS__seq_status__seq_status__info_bus_reset 11 -#define R_SCSI1_STATUS__seq_status__seq_status__info_illegal_bf 12 -#define R_SCSI1_STATUS__seq_status__seq_status__info_illegal_op 7 -#define R_SCSI1_STATUS__seq_status__seq_status__info_parity_error 1 -#define R_SCSI1_STATUS__seq_status__seq_status__info_rec_recvd 8 -#define R_SCSI1_STATUS__seq_status__seq_status__info_reselected 9 -#define R_SCSI1_STATUS__seq_status__seq_status__info_sel_timeout 5 -#define R_SCSI1_STATUS__seq_status__seq_status__info_seq_complete 0 -#define R_SCSI1_STATUS__seq_status__seq_status__info_unexp_bf 6 -#define R_SCSI1_STATUS__seq_status__seq_status__info_unexp_ph_change 3 -#define R_SCSI1_STATUS__seq_status__seq_status__info_unhandled_msg_in 2 -#define R_SCSI1_STATUS__seq_status__seq_status__info_unhandled_status 10 - -#endif - -/* - * R_SCSI1_STATUS_CTRL - * - type: WO - * - addr: 0xb0000053 - * - group: SCSI registers - */ - -#if USE_GROUP__SCSI_registers - -#define R_SCSI1_STATUS_CTRL__ADDR (REG_TYPECAST_BYTE 0xb0000053) - -#ifndef REG_NO_SHADOW -#define R_SCSI1_STATUS_CTRL__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_PAR1_CTRL_DATA + 3)) -#define R_SCSI1_STATUS_CTRL__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_PAR1_CTRL_DATA + 3)) -#else /* REG_NO_SHADOW */ -#define R_SCSI1_STATUS_CTRL__SADDR (REG_STYPECAST_BYTE (®_shadow__hwregs)) -#define R_SCSI1_STATUS_CTRL__IADDR (REG_STYPECAST_BYTE (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_SCSI1_STATUS_CTRL__STYPECAST REG_STYPECAST_BYTE -#define R_SCSI1_STATUS_CTRL__SVAL REG_SVAL_SHADOW -#define R_SCSI1_STATUS_CTRL__SVAL_I REG_SVAL_I_SHADOW -#define R_SCSI1_STATUS_CTRL__TYPECAST REG_TYPECAST_BYTE -#define R_SCSI1_STATUS_CTRL__TYPE (REG_BYTE) -#define R_SCSI1_STATUS_CTRL__GET REG_GET_WO -#define R_SCSI1_STATUS_CTRL__IGET REG_IGET_WO -#define R_SCSI1_STATUS_CTRL__SET REG_SET_WO -#define R_SCSI1_STATUS_CTRL__ISET REG_ISET_WO -#define R_SCSI1_STATUS_CTRL__SET_VAL REG_SET_VAL_WO -#define R_SCSI1_STATUS_CTRL__EQL REG_EQL_WO -#define R_SCSI1_STATUS_CTRL__IEQL REG_IEQL_WO -#define R_SCSI1_STATUS_CTRL__RD REG_RD_WO -#define R_SCSI1_STATUS_CTRL__IRD REG_IRD_WO -#define R_SCSI1_STATUS_CTRL__WR REG_WR_WO -#define R_SCSI1_STATUS_CTRL__IWR REG_IWR_WO - -#define R_SCSI1_STATUS_CTRL__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_SCSI1_STATUS_CTRL__parity_in__parity_in__MASK 0x00000004U -#define R_SCSI1_STATUS_CTRL__skip__skip__MASK 0x00000002U -#define R_SCSI1_STATUS_CTRL__clr_status__clr_status__MASK 0x00000001U - -#define R_SCSI1_STATUS_CTRL__parity_in__MAX 0x1 -#define R_SCSI1_STATUS_CTRL__skip__MAX 0x1 -#define R_SCSI1_STATUS_CTRL__clr_status__MAX 0x1 - -#define R_SCSI1_STATUS_CTRL__parity_in__MIN 0 -#define R_SCSI1_STATUS_CTRL__skip__MIN 0 -#define R_SCSI1_STATUS_CTRL__clr_status__MIN 0 - -#define R_SCSI1_STATUS_CTRL__parity_in__BITNR 2 -#define R_SCSI1_STATUS_CTRL__skip__BITNR 1 -#define R_SCSI1_STATUS_CTRL__clr_status__BITNR 0 - -#define R_SCSI1_STATUS_CTRL__parity_in__parity_in__VAL REG_VAL_ENUM -#define R_SCSI1_STATUS_CTRL__skip__skip__VAL REG_VAL_ENUM -#define R_SCSI1_STATUS_CTRL__clr_status__clr_status__VAL REG_VAL_ENUM - -#define R_SCSI1_STATUS_CTRL__parity_in__parity_in__off 1 -#define R_SCSI1_STATUS_CTRL__parity_in__parity_in__on 0 -#define R_SCSI1_STATUS_CTRL__skip__skip__off 0 -#define R_SCSI1_STATUS_CTRL__skip__skip__on 1 -#define R_SCSI1_STATUS_CTRL__clr_status__clr_status__nop 0 -#define R_SCSI1_STATUS_CTRL__clr_status__clr_status__yes 1 - -#endif - -/* - * R_SDRAM_CONFIG - * - type: WO - * - addr: 0xb000000c - * - group: Bus interface configuration registers - */ - -#if USE_GROUP__Bus_interface_configuration_registers - -#define R_SDRAM_CONFIG__ADDR (REG_TYPECAST_UDWORD 0xb000000c) - -#ifndef REG_NO_SHADOW -#define R_SDRAM_CONFIG__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_DRAM_CONFIG + 0)) -#define R_SDRAM_CONFIG__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_DRAM_CONFIG + 0)) -#else /* REG_NO_SHADOW */ -#define R_SDRAM_CONFIG__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_SDRAM_CONFIG__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_SDRAM_CONFIG__STYPECAST REG_STYPECAST_UDWORD -#define R_SDRAM_CONFIG__SVAL REG_SVAL_SHADOW -#define R_SDRAM_CONFIG__SVAL_I REG_SVAL_I_SHADOW -#define R_SDRAM_CONFIG__TYPECAST REG_TYPECAST_UDWORD -#define R_SDRAM_CONFIG__TYPE (REG_UDWORD) -#define R_SDRAM_CONFIG__GET REG_GET_WO -#define R_SDRAM_CONFIG__IGET REG_IGET_WO -#define R_SDRAM_CONFIG__SET REG_SET_WO -#define R_SDRAM_CONFIG__ISET REG_ISET_WO -#define R_SDRAM_CONFIG__SET_VAL REG_SET_VAL_WO -#define R_SDRAM_CONFIG__EQL REG_EQL_WO -#define R_SDRAM_CONFIG__IEQL REG_IEQL_WO -#define R_SDRAM_CONFIG__RD REG_RD_WO -#define R_SDRAM_CONFIG__IRD REG_IRD_WO -#define R_SDRAM_CONFIG__WR REG_WR_WO -#define R_SDRAM_CONFIG__IWR REG_IWR_WO - -#define R_SDRAM_CONFIG__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_SDRAM_CONFIG__wmm1__wmm1__MASK 0x80000000U -#define R_SDRAM_CONFIG__wmm0__wmm0__MASK 0x40000000U -#define R_SDRAM_CONFIG__sh1__sh1__MASK 0x38000000U -#define R_SDRAM_CONFIG__sh0__sh0__MASK 0x07000000U -#define R_SDRAM_CONFIG__w__w__MASK 0x00800000U -#define R_SDRAM_CONFIG__type1__type1__MASK 0x00400000U -#define R_SDRAM_CONFIG__type0__type0__MASK 0x00200000U -#define R_SDRAM_CONFIG__group_sel__group_sel__MASK 0x001f0000U -#define R_SDRAM_CONFIG__ca1__ca1__MASK 0x0000e000U -#define R_SDRAM_CONFIG__bank_sel1__bank_sel1__MASK 0x00001f00U -#define R_SDRAM_CONFIG__ca0__ca0__MASK 0x000000e0U -#define R_SDRAM_CONFIG__bank_sel0__bank_sel0__MASK 0x0000001fU - -#define R_SDRAM_CONFIG__wmm1__MAX 0x1 -#define R_SDRAM_CONFIG__wmm0__MAX 0x1 -#define R_SDRAM_CONFIG__sh1__MAX 7 -#define R_SDRAM_CONFIG__sh0__MAX 7 -#define R_SDRAM_CONFIG__w__MAX 0x1 -#define R_SDRAM_CONFIG__type1__MAX 0x1 -#define R_SDRAM_CONFIG__type0__MAX 0x1 -#define R_SDRAM_CONFIG__group_sel__MAX 0x1f -#define R_SDRAM_CONFIG__ca1__MAX 7 -#define R_SDRAM_CONFIG__bank_sel1__MAX 0x1f -#define R_SDRAM_CONFIG__ca0__MAX 7 -#define R_SDRAM_CONFIG__bank_sel0__MAX 0x1f - -#define R_SDRAM_CONFIG__wmm1__MIN 0 -#define R_SDRAM_CONFIG__wmm0__MIN 0 -#define R_SDRAM_CONFIG__sh1__MIN 0 -#define R_SDRAM_CONFIG__sh0__MIN 0 -#define R_SDRAM_CONFIG__w__MIN 0 -#define R_SDRAM_CONFIG__type1__MIN 0 -#define R_SDRAM_CONFIG__type0__MIN 0 -#define R_SDRAM_CONFIG__group_sel__MIN 0 -#define R_SDRAM_CONFIG__ca1__MIN 0 -#define R_SDRAM_CONFIG__bank_sel1__MIN 0 -#define R_SDRAM_CONFIG__ca0__MIN 0 -#define R_SDRAM_CONFIG__bank_sel0__MIN 0 - -#define R_SDRAM_CONFIG__wmm1__BITNR 31 -#define R_SDRAM_CONFIG__wmm0__BITNR 30 -#define R_SDRAM_CONFIG__sh1__BITNR 27 -#define R_SDRAM_CONFIG__sh0__BITNR 24 -#define R_SDRAM_CONFIG__w__BITNR 23 -#define R_SDRAM_CONFIG__type1__BITNR 22 -#define R_SDRAM_CONFIG__type0__BITNR 21 -#define R_SDRAM_CONFIG__group_sel__BITNR 16 -#define R_SDRAM_CONFIG__ca1__BITNR 13 -#define R_SDRAM_CONFIG__bank_sel1__BITNR 8 -#define R_SDRAM_CONFIG__ca0__BITNR 5 -#define R_SDRAM_CONFIG__bank_sel0__BITNR 0 - -#define R_SDRAM_CONFIG__wmm1__wmm1__VAL REG_VAL_ENUM -#define R_SDRAM_CONFIG__wmm0__wmm0__VAL REG_VAL_ENUM -#define R_SDRAM_CONFIG__sh1__sh1__VAL REG_VAL_VAL -#define R_SDRAM_CONFIG__sh0__sh0__VAL REG_VAL_VAL -#define R_SDRAM_CONFIG__w__w__VAL REG_VAL_ENUM -#define R_SDRAM_CONFIG__type1__type1__VAL REG_VAL_ENUM -#define R_SDRAM_CONFIG__type0__type0__VAL REG_VAL_ENUM -#define R_SDRAM_CONFIG__group_sel__group_sel__VAL REG_VAL_ENUM -#define R_SDRAM_CONFIG__ca1__ca1__VAL REG_VAL_VAL -#define R_SDRAM_CONFIG__bank_sel1__bank_sel1__VAL REG_VAL_ENUM -#define R_SDRAM_CONFIG__ca0__ca0__VAL REG_VAL_VAL -#define R_SDRAM_CONFIG__bank_sel0__bank_sel0__VAL REG_VAL_ENUM - -#define R_SDRAM_CONFIG__wmm1__wmm1__norm 0 -#define R_SDRAM_CONFIG__wmm1__wmm1__wmm 1 -#define R_SDRAM_CONFIG__wmm0__wmm0__norm 0 -#define R_SDRAM_CONFIG__wmm0__wmm0__wmm 1 -#define R_SDRAM_CONFIG__w__w__bw16 0 -#define R_SDRAM_CONFIG__w__w__bw32 1 -#define R_SDRAM_CONFIG__type1__type1__bank2 0 -#define R_SDRAM_CONFIG__type1__type1__bank4 1 -#define R_SDRAM_CONFIG__type0__type0__bank2 0 -#define R_SDRAM_CONFIG__type0__type0__bank4 1 -#define R_SDRAM_CONFIG__group_sel__group_sel__bit10 10 -#define R_SDRAM_CONFIG__group_sel__group_sel__bit11 11 -#define R_SDRAM_CONFIG__group_sel__group_sel__bit12 12 -#define R_SDRAM_CONFIG__group_sel__group_sel__bit13 13 -#define R_SDRAM_CONFIG__group_sel__group_sel__bit14 14 -#define R_SDRAM_CONFIG__group_sel__group_sel__bit15 15 -#define R_SDRAM_CONFIG__group_sel__group_sel__bit16 16 -#define R_SDRAM_CONFIG__group_sel__group_sel__bit17 17 -#define R_SDRAM_CONFIG__group_sel__group_sel__bit18 18 -#define R_SDRAM_CONFIG__group_sel__group_sel__bit19 19 -#define R_SDRAM_CONFIG__group_sel__group_sel__bit20 20 -#define R_SDRAM_CONFIG__group_sel__group_sel__bit21 21 -#define R_SDRAM_CONFIG__group_sel__group_sel__bit22 22 -#define R_SDRAM_CONFIG__group_sel__group_sel__bit23 23 -#define R_SDRAM_CONFIG__group_sel__group_sel__bit24 24 -#define R_SDRAM_CONFIG__group_sel__group_sel__bit25 25 -#define R_SDRAM_CONFIG__group_sel__group_sel__bit26 26 -#define R_SDRAM_CONFIG__group_sel__group_sel__bit27 27 -#define R_SDRAM_CONFIG__group_sel__group_sel__bit28 28 -#define R_SDRAM_CONFIG__group_sel__group_sel__bit29 29 -#define R_SDRAM_CONFIG__group_sel__group_sel__bit9 9 -#define R_SDRAM_CONFIG__group_sel__group_sel__grp0 0 -#define R_SDRAM_CONFIG__group_sel__group_sel__grp1 1 -#define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit10 10 -#define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit11 11 -#define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit12 12 -#define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit13 13 -#define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit14 14 -#define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit15 15 -#define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit16 16 -#define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit17 17 -#define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit18 18 -#define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit19 19 -#define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit20 20 -#define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit21 21 -#define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit22 22 -#define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit23 23 -#define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit24 24 -#define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit25 25 -#define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit26 26 -#define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit27 27 -#define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit28 28 -#define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit29 29 -#define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit9 9 -#define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit10 10 -#define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit11 11 -#define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit12 12 -#define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit13 13 -#define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit14 14 -#define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit15 15 -#define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit16 16 -#define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit17 17 -#define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit18 18 -#define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit19 19 -#define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit20 20 -#define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit21 21 -#define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit22 22 -#define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit23 23 -#define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit24 24 -#define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit25 25 -#define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit26 26 -#define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit27 27 -#define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit28 28 -#define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit29 29 -#define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit9 9 - -#endif - -/* - * R_SDRAM_TIMING - * - type: WO - * - addr: 0xb0000008 - * - group: Bus interface configuration registers - */ - -#if USE_GROUP__Bus_interface_configuration_registers - -#define R_SDRAM_TIMING__ADDR (REG_TYPECAST_UDWORD 0xb0000008) - -#ifndef REG_NO_SHADOW -#define R_SDRAM_TIMING__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_DRAM_TIMING + 0)) -#define R_SDRAM_TIMING__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_DRAM_TIMING + 0)) -#else /* REG_NO_SHADOW */ -#define R_SDRAM_TIMING__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_SDRAM_TIMING__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_SDRAM_TIMING__STYPECAST REG_STYPECAST_UDWORD -#define R_SDRAM_TIMING__SVAL REG_SVAL_SHADOW -#define R_SDRAM_TIMING__SVAL_I REG_SVAL_I_SHADOW -#define R_SDRAM_TIMING__TYPECAST REG_TYPECAST_UDWORD -#define R_SDRAM_TIMING__TYPE (REG_UDWORD) -#define R_SDRAM_TIMING__GET REG_GET_WO -#define R_SDRAM_TIMING__IGET REG_IGET_WO -#define R_SDRAM_TIMING__SET REG_SET_WO -#define R_SDRAM_TIMING__ISET REG_ISET_WO -#define R_SDRAM_TIMING__SET_VAL REG_SET_VAL_WO -#define R_SDRAM_TIMING__EQL REG_EQL_WO -#define R_SDRAM_TIMING__IEQL REG_IEQL_WO -#define R_SDRAM_TIMING__RD REG_RD_WO -#define R_SDRAM_TIMING__IRD REG_IRD_WO -#define R_SDRAM_TIMING__WR REG_WR_WO -#define R_SDRAM_TIMING__IWR REG_IWR_WO - -#define R_SDRAM_TIMING__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_SDRAM_TIMING__sdram__sdram__MASK 0x80000000U -#define R_SDRAM_TIMING__mrs_data__mrs_data__MASK 0x7fff0000U -#define R_SDRAM_TIMING__ref__ref__MASK 0x0000c000U -#define R_SDRAM_TIMING__ddr__ddr__MASK 0x00002000U -#define R_SDRAM_TIMING__clk100__clk100__MASK 0x00001000U -#define R_SDRAM_TIMING__ps__ps__MASK 0x00000800U -#define R_SDRAM_TIMING__cmd__cmd__MASK 0x00000600U -#define R_SDRAM_TIMING__pde__pde__MASK 0x00000100U -#define R_SDRAM_TIMING__rc__rc__MASK 0x000000c0U -#define R_SDRAM_TIMING__rp__rp__MASK 0x00000030U -#define R_SDRAM_TIMING__rcd__rcd__MASK 0x0000000cU -#define R_SDRAM_TIMING__cl__cl__MASK 0x00000003U - -#define R_SDRAM_TIMING__sdram__MAX 0x1 -#define R_SDRAM_TIMING__mrs_data__MAX 0x7fff -#define R_SDRAM_TIMING__ref__MAX 0x3 -#define R_SDRAM_TIMING__ddr__MAX 0x1 -#define R_SDRAM_TIMING__clk100__MAX 0x1 -#define R_SDRAM_TIMING__ps__MAX 0x1 -#define R_SDRAM_TIMING__cmd__MAX 0x3 -#define R_SDRAM_TIMING__pde__MAX 1 -#define R_SDRAM_TIMING__rc__MAX 3 -#define R_SDRAM_TIMING__rp__MAX 3 -#define R_SDRAM_TIMING__rcd__MAX 3 -#define R_SDRAM_TIMING__cl__MAX 2 - -#define R_SDRAM_TIMING__sdram__MIN 0 -#define R_SDRAM_TIMING__mrs_data__MIN 0 -#define R_SDRAM_TIMING__ref__MIN 0 -#define R_SDRAM_TIMING__ddr__MIN 0 -#define R_SDRAM_TIMING__clk100__MIN 0 -#define R_SDRAM_TIMING__ps__MIN 0 -#define R_SDRAM_TIMING__cmd__MIN 0 -#define R_SDRAM_TIMING__pde__MIN 0 -#define R_SDRAM_TIMING__rc__MIN 0 -#define R_SDRAM_TIMING__rp__MIN 0 -#define R_SDRAM_TIMING__rcd__MIN 0 -#define R_SDRAM_TIMING__cl__MIN 0 - -#define R_SDRAM_TIMING__sdram__BITNR 31 -#define R_SDRAM_TIMING__mrs_data__BITNR 16 -#define R_SDRAM_TIMING__ref__BITNR 14 -#define R_SDRAM_TIMING__ddr__BITNR 13 -#define R_SDRAM_TIMING__clk100__BITNR 12 -#define R_SDRAM_TIMING__ps__BITNR 11 -#define R_SDRAM_TIMING__cmd__BITNR 9 -#define R_SDRAM_TIMING__pde__BITNR 8 -#define R_SDRAM_TIMING__rc__BITNR 6 -#define R_SDRAM_TIMING__rp__BITNR 4 -#define R_SDRAM_TIMING__rcd__BITNR 2 -#define R_SDRAM_TIMING__cl__BITNR 0 - -#define R_SDRAM_TIMING__sdram__sdram__VAL REG_VAL_ENUM -#define R_SDRAM_TIMING__mrs_data__mrs_data__VAL REG_VAL_VAL -#define R_SDRAM_TIMING__ref__ref__VAL REG_VAL_ENUM -#define R_SDRAM_TIMING__ddr__ddr__VAL REG_VAL_ENUM -#define R_SDRAM_TIMING__clk100__clk100__VAL REG_VAL_ENUM -#define R_SDRAM_TIMING__ps__ps__VAL REG_VAL_ENUM -#define R_SDRAM_TIMING__cmd__cmd__VAL REG_VAL_ENUM -#define R_SDRAM_TIMING__pde__pde__VAL REG_VAL_VAL -#define R_SDRAM_TIMING__rc__rc__VAL REG_VAL_VAL -#define R_SDRAM_TIMING__rp__rp__VAL REG_VAL_VAL -#define R_SDRAM_TIMING__rcd__rcd__VAL REG_VAL_VAL -#define R_SDRAM_TIMING__cl__cl__VAL REG_VAL_VAL - -#define R_SDRAM_TIMING__sdram__sdram__disable 0 -#define R_SDRAM_TIMING__sdram__sdram__enable 1 -#define R_SDRAM_TIMING__ref__ref__disable 3 -#define R_SDRAM_TIMING__ref__ref__e13us 1 -#define R_SDRAM_TIMING__ref__ref__e52us 0 -#define R_SDRAM_TIMING__ref__ref__e6500ns 2 -#define R_SDRAM_TIMING__ddr__ddr__off 0 -#define R_SDRAM_TIMING__ddr__ddr__on 1 -#define R_SDRAM_TIMING__clk100__clk100__off 0 -#define R_SDRAM_TIMING__clk100__clk100__on 1 -#define R_SDRAM_TIMING__ps__ps__off 0 -#define R_SDRAM_TIMING__ps__ps__on 1 -#define R_SDRAM_TIMING__cmd__cmd__mrs 1 -#define R_SDRAM_TIMING__cmd__cmd__nop 0 -#define R_SDRAM_TIMING__cmd__cmd__pre 3 -#define R_SDRAM_TIMING__cmd__cmd__ref 2 - -#endif - -/* - * R_SERIAL0_BAUD - * - type: WO - * - addr: 0xb0000063 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -#define R_SERIAL0_BAUD__ADDR (REG_TYPECAST_BYTE 0xb0000063) - -#ifndef REG_NO_SHADOW -#define R_SERIAL0_BAUD__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL0_CTRL + 3)) -#define R_SERIAL0_BAUD__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL0_CTRL + 3)) -#else /* REG_NO_SHADOW */ -#define R_SERIAL0_BAUD__SADDR (REG_STYPECAST_BYTE (®_shadow__hwregs)) -#define R_SERIAL0_BAUD__IADDR (REG_STYPECAST_BYTE (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_SERIAL0_BAUD__STYPECAST REG_STYPECAST_BYTE -#define R_SERIAL0_BAUD__SVAL REG_SVAL_SHADOW -#define R_SERIAL0_BAUD__SVAL_I REG_SVAL_I_SHADOW -#define R_SERIAL0_BAUD__TYPECAST REG_TYPECAST_BYTE -#define R_SERIAL0_BAUD__TYPE (REG_BYTE) -#define R_SERIAL0_BAUD__GET REG_GET_WO -#define R_SERIAL0_BAUD__IGET REG_IGET_WO -#define R_SERIAL0_BAUD__SET REG_SET_WO -#define R_SERIAL0_BAUD__ISET REG_ISET_WO -#define R_SERIAL0_BAUD__SET_VAL REG_SET_VAL_WO -#define R_SERIAL0_BAUD__EQL REG_EQL_WO -#define R_SERIAL0_BAUD__IEQL REG_IEQL_WO -#define R_SERIAL0_BAUD__RD REG_RD_WO -#define R_SERIAL0_BAUD__IRD REG_IRD_WO -#define R_SERIAL0_BAUD__WR REG_WR_WO -#define R_SERIAL0_BAUD__IWR REG_IWR_WO - -#define R_SERIAL0_BAUD__WRITE(addr,value) \ - (*(addr) = (value)) - -/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */ -#define R_SERIAL0_BAUD__FIRST 0 -#define R_SERIAL0_BAUD__IOFFSET 8 -#define R_SERIAL0_BAUD__LAST 3 -#define R_SERIAL0_BAUD__OFFSET 8 -#define R_SERIAL0_BAUD__SOFFSET 8 -/* end */ - -#define R_SERIAL0_BAUD__tr_baud__tr_baud__MASK 0x000000f0U -#define R_SERIAL0_BAUD__rec_baud__rec_baud__MASK 0x0000000fU - -#define R_SERIAL0_BAUD__tr_baud__MAX 0xf -#define R_SERIAL0_BAUD__rec_baud__MAX 0xf - -#define R_SERIAL0_BAUD__tr_baud__MIN 0 -#define R_SERIAL0_BAUD__rec_baud__MIN 0 - -#define R_SERIAL0_BAUD__tr_baud__BITNR 4 -#define R_SERIAL0_BAUD__rec_baud__BITNR 0 - -#define R_SERIAL0_BAUD__tr_baud__tr_baud__VAL REG_VAL_ENUM -#define R_SERIAL0_BAUD__rec_baud__rec_baud__VAL REG_VAL_ENUM - -#define R_SERIAL0_BAUD__tr_baud__tr_baud__c115k2Hz 9 -#define R_SERIAL0_BAUD__tr_baud__tr_baud__c1200Hz 2 -#define R_SERIAL0_BAUD__tr_baud__tr_baud__c1843k2Hz 13 -#define R_SERIAL0_BAUD__tr_baud__tr_baud__c19k2Hz 6 -#define R_SERIAL0_BAUD__tr_baud__tr_baud__c230k4Hz 10 -#define R_SERIAL0_BAUD__tr_baud__tr_baud__c2400Hz 3 -#define R_SERIAL0_BAUD__tr_baud__tr_baud__c300Hz 0 -#define R_SERIAL0_BAUD__tr_baud__tr_baud__c38k4Hz 7 -#define R_SERIAL0_BAUD__tr_baud__tr_baud__c460k8Hz 11 -#define R_SERIAL0_BAUD__tr_baud__tr_baud__c4800Hz 4 -#define R_SERIAL0_BAUD__tr_baud__tr_baud__c57k6Hz 8 -#define R_SERIAL0_BAUD__tr_baud__tr_baud__c600Hz 1 -#define R_SERIAL0_BAUD__tr_baud__tr_baud__c6250kHz 14 -#define R_SERIAL0_BAUD__tr_baud__tr_baud__c921k6Hz 12 -#define R_SERIAL0_BAUD__tr_baud__tr_baud__c9600Hz 5 -#define R_SERIAL0_BAUD__rec_baud__rec_baud__c115k2Hz 9 -#define R_SERIAL0_BAUD__rec_baud__rec_baud__c1200Hz 2 -#define R_SERIAL0_BAUD__rec_baud__rec_baud__c1843k2Hz 13 -#define R_SERIAL0_BAUD__rec_baud__rec_baud__c19k2Hz 6 -#define R_SERIAL0_BAUD__rec_baud__rec_baud__c230k4Hz 10 -#define R_SERIAL0_BAUD__rec_baud__rec_baud__c2400Hz 3 -#define R_SERIAL0_BAUD__rec_baud__rec_baud__c300Hz 0 -#define R_SERIAL0_BAUD__rec_baud__rec_baud__c38k4Hz 7 -#define R_SERIAL0_BAUD__rec_baud__rec_baud__c460k8Hz 11 -#define R_SERIAL0_BAUD__rec_baud__rec_baud__c4800Hz 4 -#define R_SERIAL0_BAUD__rec_baud__rec_baud__c57k6Hz 8 -#define R_SERIAL0_BAUD__rec_baud__rec_baud__c600Hz 1 -#define R_SERIAL0_BAUD__rec_baud__rec_baud__c6250kHz 14 -#define R_SERIAL0_BAUD__rec_baud__rec_baud__c921k6Hz 12 -#define R_SERIAL0_BAUD__rec_baud__rec_baud__c9600Hz 5 - -#endif - -/* - * R_SERIAL0_CTRL - * - type: WO - * - addr: 0xb0000060 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -#define R_SERIAL0_CTRL__ADDR (REG_TYPECAST_UDWORD 0xb0000060) - -#ifndef REG_NO_SHADOW -#define R_SERIAL0_CTRL__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_SERIAL0_CTRL + 0)) -#define R_SERIAL0_CTRL__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_SERIAL0_CTRL + 0)) -#else /* REG_NO_SHADOW */ -#define R_SERIAL0_CTRL__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_SERIAL0_CTRL__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_SERIAL0_CTRL__STYPECAST REG_STYPECAST_UDWORD -#define R_SERIAL0_CTRL__SVAL REG_SVAL_SHADOW -#define R_SERIAL0_CTRL__SVAL_I REG_SVAL_I_SHADOW -#define R_SERIAL0_CTRL__TYPECAST REG_TYPECAST_UDWORD -#define R_SERIAL0_CTRL__TYPE (REG_UDWORD) -#define R_SERIAL0_CTRL__GET REG_GET_WO -#define R_SERIAL0_CTRL__IGET REG_IGET_WO -#define R_SERIAL0_CTRL__SET REG_SET_WO -#define R_SERIAL0_CTRL__ISET REG_ISET_WO -#define R_SERIAL0_CTRL__SET_VAL REG_SET_VAL_WO -#define R_SERIAL0_CTRL__EQL REG_EQL_WO -#define R_SERIAL0_CTRL__IEQL REG_IEQL_WO -#define R_SERIAL0_CTRL__RD REG_RD_WO -#define R_SERIAL0_CTRL__IRD REG_IRD_WO -#define R_SERIAL0_CTRL__WR REG_WR_WO -#define R_SERIAL0_CTRL__IWR REG_IWR_WO - -#define R_SERIAL0_CTRL__WRITE(addr,value) \ - (*(addr) = (value)) - -/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */ -#define R_SERIAL0_CTRL__FIRST 0 -#define R_SERIAL0_CTRL__IOFFSET 8 -#define R_SERIAL0_CTRL__LAST 3 -#define R_SERIAL0_CTRL__OFFSET 8 -#define R_SERIAL0_CTRL__SOFFSET 8 -/* end */ - -#define R_SERIAL0_CTRL__tr_baud__tr_baud__MASK 0xf0000000U -#define R_SERIAL0_CTRL__rec_baud__rec_baud__MASK 0x0f000000U -#define R_SERIAL0_CTRL__dma_err__dma_err__MASK 0x00800000U -#define R_SERIAL0_CTRL__rec_enable__rec_enable__MASK 0x00400000U -#define R_SERIAL0_CTRL__rts___rts___MASK 0x00200000U -#define R_SERIAL0_CTRL__sampling__sampling__MASK 0x00100000U -#define R_SERIAL0_CTRL__rec_stick_par__rec_stick_par__MASK 0x00080000U -#define R_SERIAL0_CTRL__rec_par__rec_par__MASK 0x00040000U -#define R_SERIAL0_CTRL__rec_par_en__rec_par_en__MASK 0x00020000U -#define R_SERIAL0_CTRL__rec_bitnr__rec_bitnr__MASK 0x00010000U -#define R_SERIAL0_CTRL__txd__txd__MASK 0x00008000U -#define R_SERIAL0_CTRL__tr_enable__tr_enable__MASK 0x00004000U -#define R_SERIAL0_CTRL__auto_cts__auto_cts__MASK 0x00002000U -#define R_SERIAL0_CTRL__stop_bits__stop_bits__MASK 0x00001000U -#define R_SERIAL0_CTRL__tr_stick_par__tr_stick_par__MASK 0x00000800U -#define R_SERIAL0_CTRL__tr_par__tr_par__MASK 0x00000400U -#define R_SERIAL0_CTRL__tr_par_en__tr_par_en__MASK 0x00000200U -#define R_SERIAL0_CTRL__tr_bitnr__tr_bitnr__MASK 0x00000100U -#define R_SERIAL0_CTRL__data_out__data_out__MASK 0x000000ffU - -#define R_SERIAL0_CTRL__tr_baud__MAX 0xf -#define R_SERIAL0_CTRL__rec_baud__MAX 0xf -#define R_SERIAL0_CTRL__dma_err__MAX 0x1 -#define R_SERIAL0_CTRL__rec_enable__MAX 0x1 -#define R_SERIAL0_CTRL__rts___MAX 0x1 -#define R_SERIAL0_CTRL__sampling__MAX 0x1 -#define R_SERIAL0_CTRL__rec_stick_par__MAX 0x1 -#define R_SERIAL0_CTRL__rec_par__MAX 0x1 -#define R_SERIAL0_CTRL__rec_par_en__MAX 0x1 -#define R_SERIAL0_CTRL__rec_bitnr__MAX 0x1 -#define R_SERIAL0_CTRL__txd__MAX 0x1 -#define R_SERIAL0_CTRL__tr_enable__MAX 0x1 -#define R_SERIAL0_CTRL__auto_cts__MAX 0x1 -#define R_SERIAL0_CTRL__stop_bits__MAX 0x1 -#define R_SERIAL0_CTRL__tr_stick_par__MAX 0x1 -#define R_SERIAL0_CTRL__tr_par__MAX 0x1 -#define R_SERIAL0_CTRL__tr_par_en__MAX 0x1 -#define R_SERIAL0_CTRL__tr_bitnr__MAX 0x1 -#define R_SERIAL0_CTRL__data_out__MAX 0xff - -#define R_SERIAL0_CTRL__tr_baud__MIN 0 -#define R_SERIAL0_CTRL__rec_baud__MIN 0 -#define R_SERIAL0_CTRL__dma_err__MIN 0 -#define R_SERIAL0_CTRL__rec_enable__MIN 0 -#define R_SERIAL0_CTRL__rts___MIN 0 -#define R_SERIAL0_CTRL__sampling__MIN 0 -#define R_SERIAL0_CTRL__rec_stick_par__MIN 0 -#define R_SERIAL0_CTRL__rec_par__MIN 0 -#define R_SERIAL0_CTRL__rec_par_en__MIN 0 -#define R_SERIAL0_CTRL__rec_bitnr__MIN 0 -#define R_SERIAL0_CTRL__txd__MIN 0 -#define R_SERIAL0_CTRL__tr_enable__MIN 0 -#define R_SERIAL0_CTRL__auto_cts__MIN 0 -#define R_SERIAL0_CTRL__stop_bits__MIN 0 -#define R_SERIAL0_CTRL__tr_stick_par__MIN 0 -#define R_SERIAL0_CTRL__tr_par__MIN 0 -#define R_SERIAL0_CTRL__tr_par_en__MIN 0 -#define R_SERIAL0_CTRL__tr_bitnr__MIN 0 -#define R_SERIAL0_CTRL__data_out__MIN 0 - -#define R_SERIAL0_CTRL__tr_baud__BITNR 28 -#define R_SERIAL0_CTRL__rec_baud__BITNR 24 -#define R_SERIAL0_CTRL__dma_err__BITNR 23 -#define R_SERIAL0_CTRL__rec_enable__BITNR 22 -#define R_SERIAL0_CTRL__rts___BITNR 21 -#define R_SERIAL0_CTRL__sampling__BITNR 20 -#define R_SERIAL0_CTRL__rec_stick_par__BITNR 19 -#define R_SERIAL0_CTRL__rec_par__BITNR 18 -#define R_SERIAL0_CTRL__rec_par_en__BITNR 17 -#define R_SERIAL0_CTRL__rec_bitnr__BITNR 16 -#define R_SERIAL0_CTRL__txd__BITNR 15 -#define R_SERIAL0_CTRL__tr_enable__BITNR 14 -#define R_SERIAL0_CTRL__auto_cts__BITNR 13 -#define R_SERIAL0_CTRL__stop_bits__BITNR 12 -#define R_SERIAL0_CTRL__tr_stick_par__BITNR 11 -#define R_SERIAL0_CTRL__tr_par__BITNR 10 -#define R_SERIAL0_CTRL__tr_par_en__BITNR 9 -#define R_SERIAL0_CTRL__tr_bitnr__BITNR 8 -#define R_SERIAL0_CTRL__data_out__BITNR 0 - -#define R_SERIAL0_CTRL__tr_baud__tr_baud__VAL REG_VAL_ENUM -#define R_SERIAL0_CTRL__rec_baud__rec_baud__VAL REG_VAL_ENUM -#define R_SERIAL0_CTRL__dma_err__dma_err__VAL REG_VAL_ENUM -#define R_SERIAL0_CTRL__rec_enable__rec_enable__VAL REG_VAL_ENUM -#define R_SERIAL0_CTRL__rts___rts___VAL REG_VAL_ENUM -#define R_SERIAL0_CTRL__sampling__sampling__VAL REG_VAL_ENUM -#define R_SERIAL0_CTRL__rec_stick_par__rec_stick_par__VAL REG_VAL_ENUM -#define R_SERIAL0_CTRL__rec_par__rec_par__VAL REG_VAL_ENUM -#define R_SERIAL0_CTRL__rec_par_en__rec_par_en__VAL REG_VAL_ENUM -#define R_SERIAL0_CTRL__rec_bitnr__rec_bitnr__VAL REG_VAL_ENUM -#define R_SERIAL0_CTRL__txd__txd__VAL REG_VAL_VAL -#define R_SERIAL0_CTRL__tr_enable__tr_enable__VAL REG_VAL_ENUM -#define R_SERIAL0_CTRL__auto_cts__auto_cts__VAL REG_VAL_ENUM -#define R_SERIAL0_CTRL__stop_bits__stop_bits__VAL REG_VAL_ENUM -#define R_SERIAL0_CTRL__tr_stick_par__tr_stick_par__VAL REG_VAL_ENUM -#define R_SERIAL0_CTRL__tr_par__tr_par__VAL REG_VAL_ENUM -#define R_SERIAL0_CTRL__tr_par_en__tr_par_en__VAL REG_VAL_ENUM -#define R_SERIAL0_CTRL__tr_bitnr__tr_bitnr__VAL REG_VAL_ENUM -#define R_SERIAL0_CTRL__data_out__data_out__VAL REG_VAL_VAL - -#define R_SERIAL0_CTRL__tr_baud__tr_baud__c115k2Hz 9 -#define R_SERIAL0_CTRL__tr_baud__tr_baud__c1200Hz 2 -#define R_SERIAL0_CTRL__tr_baud__tr_baud__c1843k2Hz 13 -#define R_SERIAL0_CTRL__tr_baud__tr_baud__c19k2Hz 6 -#define R_SERIAL0_CTRL__tr_baud__tr_baud__c230k4Hz 10 -#define R_SERIAL0_CTRL__tr_baud__tr_baud__c2400Hz 3 -#define R_SERIAL0_CTRL__tr_baud__tr_baud__c300Hz 0 -#define R_SERIAL0_CTRL__tr_baud__tr_baud__c38k4Hz 7 -#define R_SERIAL0_CTRL__tr_baud__tr_baud__c460k8Hz 11 -#define R_SERIAL0_CTRL__tr_baud__tr_baud__c4800Hz 4 -#define R_SERIAL0_CTRL__tr_baud__tr_baud__c57k6Hz 8 -#define R_SERIAL0_CTRL__tr_baud__tr_baud__c600Hz 1 -#define R_SERIAL0_CTRL__tr_baud__tr_baud__c6250kHz 14 -#define R_SERIAL0_CTRL__tr_baud__tr_baud__c921k6Hz 12 -#define R_SERIAL0_CTRL__tr_baud__tr_baud__c9600Hz 5 -#define R_SERIAL0_CTRL__rec_baud__rec_baud__c115k2Hz 9 -#define R_SERIAL0_CTRL__rec_baud__rec_baud__c1200Hz 2 -#define R_SERIAL0_CTRL__rec_baud__rec_baud__c1843k2Hz 13 -#define R_SERIAL0_CTRL__rec_baud__rec_baud__c19k2Hz 6 -#define R_SERIAL0_CTRL__rec_baud__rec_baud__c230k4Hz 10 -#define R_SERIAL0_CTRL__rec_baud__rec_baud__c2400Hz 3 -#define R_SERIAL0_CTRL__rec_baud__rec_baud__c300Hz 0 -#define R_SERIAL0_CTRL__rec_baud__rec_baud__c38k4Hz 7 -#define R_SERIAL0_CTRL__rec_baud__rec_baud__c460k8Hz 11 -#define R_SERIAL0_CTRL__rec_baud__rec_baud__c4800Hz 4 -#define R_SERIAL0_CTRL__rec_baud__rec_baud__c57k6Hz 8 -#define R_SERIAL0_CTRL__rec_baud__rec_baud__c600Hz 1 -#define R_SERIAL0_CTRL__rec_baud__rec_baud__c6250kHz 14 -#define R_SERIAL0_CTRL__rec_baud__rec_baud__c921k6Hz 12 -#define R_SERIAL0_CTRL__rec_baud__rec_baud__c9600Hz 5 -#define R_SERIAL0_CTRL__dma_err__dma_err__ignore 1 -#define R_SERIAL0_CTRL__dma_err__dma_err__stop 0 -#define R_SERIAL0_CTRL__rec_enable__rec_enable__disable 0 -#define R_SERIAL0_CTRL__rec_enable__rec_enable__enable 1 -#define R_SERIAL0_CTRL__rts___rts___active 0 -#define R_SERIAL0_CTRL__rts___rts___inactive 1 -#define R_SERIAL0_CTRL__sampling__sampling__majority 1 -#define R_SERIAL0_CTRL__sampling__sampling__middle 0 -#define R_SERIAL0_CTRL__rec_stick_par__rec_stick_par__normal 0 -#define R_SERIAL0_CTRL__rec_stick_par__rec_stick_par__stick 1 -#define R_SERIAL0_CTRL__rec_par__rec_par__even 0 -#define R_SERIAL0_CTRL__rec_par__rec_par__odd 1 -#define R_SERIAL0_CTRL__rec_par_en__rec_par_en__disable 0 -#define R_SERIAL0_CTRL__rec_par_en__rec_par_en__enable 1 -#define R_SERIAL0_CTRL__rec_bitnr__rec_bitnr__rec_7bit 1 -#define R_SERIAL0_CTRL__rec_bitnr__rec_bitnr__rec_8bit 0 -#define R_SERIAL0_CTRL__tr_enable__tr_enable__disable 0 -#define R_SERIAL0_CTRL__tr_enable__tr_enable__enable 1 -#define R_SERIAL0_CTRL__auto_cts__auto_cts__active 1 -#define R_SERIAL0_CTRL__auto_cts__auto_cts__disabled 0 -#define R_SERIAL0_CTRL__stop_bits__stop_bits__one_bit 0 -#define R_SERIAL0_CTRL__stop_bits__stop_bits__two_bits 1 -#define R_SERIAL0_CTRL__tr_stick_par__tr_stick_par__normal 0 -#define R_SERIAL0_CTRL__tr_stick_par__tr_stick_par__stick 1 -#define R_SERIAL0_CTRL__tr_par__tr_par__even 0 -#define R_SERIAL0_CTRL__tr_par__tr_par__odd 1 -#define R_SERIAL0_CTRL__tr_par_en__tr_par_en__disable 0 -#define R_SERIAL0_CTRL__tr_par_en__tr_par_en__enable 1 -#define R_SERIAL0_CTRL__tr_bitnr__tr_bitnr__tr_7bit 1 -#define R_SERIAL0_CTRL__tr_bitnr__tr_bitnr__tr_8bit 0 - -#endif - -/* - * R_SERIAL0_READ - * - type: RO - * - addr: 0xb0000060 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -#define R_SERIAL0_READ__ADDR (REG_TYPECAST_UDWORD 0xb0000060) -#define R_SERIAL0_READ__SVAL REG_SVAL_SHADOW -#define R_SERIAL0_READ__SVAL_I REG_SVAL_I_SHADOW -#define R_SERIAL0_READ__TYPECAST REG_TYPECAST_UDWORD -#define R_SERIAL0_READ__TYPE (REG_UDWORD) -#define R_SERIAL0_READ__GET REG_GET_RO -#define R_SERIAL0_READ__IGET REG_IGET_RO -#define R_SERIAL0_READ__SET REG_SET_RO -#define R_SERIAL0_READ__ISET REG_ISET_RO -#define R_SERIAL0_READ__SET_VAL REG_SET_VAL_RO -#define R_SERIAL0_READ__EQL REG_EQL_RO -#define R_SERIAL0_READ__IEQL REG_IEQL_RO -#define R_SERIAL0_READ__RD REG_RD_RO -#define R_SERIAL0_READ__IRD REG_IRD_RO -#define R_SERIAL0_READ__WR REG_WR_RO -#define R_SERIAL0_READ__IWR REG_IWR_RO - -#define R_SERIAL0_READ__READ(addr) \ - (*(addr)) - -/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */ -#define R_SERIAL0_READ__FIRST 0 -#define R_SERIAL0_READ__LAST 3 -#define R_SERIAL0_READ__OFFSET 8 -/* end */ - -#define R_SERIAL0_READ__xoff_detect__xoff_detect__MASK 0x00008000U -#define R_SERIAL0_READ__cts___cts___MASK 0x00004000U -#define R_SERIAL0_READ__tr_ready__tr_ready__MASK 0x00002000U -#define R_SERIAL0_READ__rxd__rxd__MASK 0x00001000U -#define R_SERIAL0_READ__overrun__overrun__MASK 0x00000800U -#define R_SERIAL0_READ__par_err__par_err__MASK 0x00000400U -#define R_SERIAL0_READ__framing_err__framing_err__MASK 0x00000200U -#define R_SERIAL0_READ__data_avail__data_avail__MASK 0x00000100U -#define R_SERIAL0_READ__data_in__data_in__MASK 0x000000ffU - -#define R_SERIAL0_READ__xoff_detect__MAX 0x1 -#define R_SERIAL0_READ__cts___MAX 0x1 -#define R_SERIAL0_READ__tr_ready__MAX 0x1 -#define R_SERIAL0_READ__rxd__MAX 0x1 -#define R_SERIAL0_READ__overrun__MAX 0x1 -#define R_SERIAL0_READ__par_err__MAX 0x1 -#define R_SERIAL0_READ__framing_err__MAX 0x1 -#define R_SERIAL0_READ__data_avail__MAX 0x1 -#define R_SERIAL0_READ__data_in__MAX 0xff - -#define R_SERIAL0_READ__xoff_detect__MIN 0 -#define R_SERIAL0_READ__cts___MIN 0 -#define R_SERIAL0_READ__tr_ready__MIN 0 -#define R_SERIAL0_READ__rxd__MIN 0 -#define R_SERIAL0_READ__overrun__MIN 0 -#define R_SERIAL0_READ__par_err__MIN 0 -#define R_SERIAL0_READ__framing_err__MIN 0 -#define R_SERIAL0_READ__data_avail__MIN 0 -#define R_SERIAL0_READ__data_in__MIN 0 - -#define R_SERIAL0_READ__xoff_detect__BITNR 15 -#define R_SERIAL0_READ__cts___BITNR 14 -#define R_SERIAL0_READ__tr_ready__BITNR 13 -#define R_SERIAL0_READ__rxd__BITNR 12 -#define R_SERIAL0_READ__overrun__BITNR 11 -#define R_SERIAL0_READ__par_err__BITNR 10 -#define R_SERIAL0_READ__framing_err__BITNR 9 -#define R_SERIAL0_READ__data_avail__BITNR 8 -#define R_SERIAL0_READ__data_in__BITNR 0 - -#define R_SERIAL0_READ__xoff_detect__xoff_detect__VAL REG_VAL_ENUM -#define R_SERIAL0_READ__cts___cts___VAL REG_VAL_ENUM -#define R_SERIAL0_READ__tr_ready__tr_ready__VAL REG_VAL_ENUM -#define R_SERIAL0_READ__rxd__rxd__VAL REG_VAL_VAL -#define R_SERIAL0_READ__overrun__overrun__VAL REG_VAL_ENUM -#define R_SERIAL0_READ__par_err__par_err__VAL REG_VAL_ENUM -#define R_SERIAL0_READ__framing_err__framing_err__VAL REG_VAL_ENUM -#define R_SERIAL0_READ__data_avail__data_avail__VAL REG_VAL_ENUM -#define R_SERIAL0_READ__data_in__data_in__VAL REG_VAL_VAL - -#define R_SERIAL0_READ__xoff_detect__xoff_detect__no_xoff 0 -#define R_SERIAL0_READ__xoff_detect__xoff_detect__xoff 1 -#define R_SERIAL0_READ__cts___cts___active 0 -#define R_SERIAL0_READ__cts___cts___inactive 1 -#define R_SERIAL0_READ__tr_ready__tr_ready__full 0 -#define R_SERIAL0_READ__tr_ready__tr_ready__ready 1 -#define R_SERIAL0_READ__overrun__overrun__no 0 -#define R_SERIAL0_READ__overrun__overrun__yes 1 -#define R_SERIAL0_READ__par_err__par_err__no 0 -#define R_SERIAL0_READ__par_err__par_err__yes 1 -#define R_SERIAL0_READ__framing_err__framing_err__no 0 -#define R_SERIAL0_READ__framing_err__framing_err__yes 1 -#define R_SERIAL0_READ__data_avail__data_avail__no 0 -#define R_SERIAL0_READ__data_avail__data_avail__yes 1 - -#endif - -/* - * R_SERIAL0_REC_CTRL - * - type: WO - * - addr: 0xb0000062 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -#define R_SERIAL0_REC_CTRL__ADDR (REG_TYPECAST_BYTE 0xb0000062) - -#ifndef REG_NO_SHADOW -#define R_SERIAL0_REC_CTRL__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL0_CTRL + 2)) -#define R_SERIAL0_REC_CTRL__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL0_CTRL + 2)) -#else /* REG_NO_SHADOW */ -#define R_SERIAL0_REC_CTRL__SADDR (REG_STYPECAST_BYTE (®_shadow__hwregs)) -#define R_SERIAL0_REC_CTRL__IADDR (REG_STYPECAST_BYTE (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_SERIAL0_REC_CTRL__STYPECAST REG_STYPECAST_BYTE -#define R_SERIAL0_REC_CTRL__SVAL REG_SVAL_SHADOW -#define R_SERIAL0_REC_CTRL__SVAL_I REG_SVAL_I_SHADOW -#define R_SERIAL0_REC_CTRL__TYPECAST REG_TYPECAST_BYTE -#define R_SERIAL0_REC_CTRL__TYPE (REG_BYTE) -#define R_SERIAL0_REC_CTRL__GET REG_GET_WO -#define R_SERIAL0_REC_CTRL__IGET REG_IGET_WO -#define R_SERIAL0_REC_CTRL__SET REG_SET_WO -#define R_SERIAL0_REC_CTRL__ISET REG_ISET_WO -#define R_SERIAL0_REC_CTRL__SET_VAL REG_SET_VAL_WO -#define R_SERIAL0_REC_CTRL__EQL REG_EQL_WO -#define R_SERIAL0_REC_CTRL__IEQL REG_IEQL_WO -#define R_SERIAL0_REC_CTRL__RD REG_RD_WO -#define R_SERIAL0_REC_CTRL__IRD REG_IRD_WO -#define R_SERIAL0_REC_CTRL__WR REG_WR_WO -#define R_SERIAL0_REC_CTRL__IWR REG_IWR_WO - -#define R_SERIAL0_REC_CTRL__WRITE(addr,value) \ - (*(addr) = (value)) - -/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */ -#define R_SERIAL0_REC_CTRL__FIRST 0 -#define R_SERIAL0_REC_CTRL__IOFFSET 8 -#define R_SERIAL0_REC_CTRL__LAST 3 -#define R_SERIAL0_REC_CTRL__OFFSET 8 -#define R_SERIAL0_REC_CTRL__SOFFSET 8 -/* end */ - -#define R_SERIAL0_REC_CTRL__dma_err__dma_err__MASK 0x00000080U -#define R_SERIAL0_REC_CTRL__rec_enable__rec_enable__MASK 0x00000040U -#define R_SERIAL0_REC_CTRL__rts___rts___MASK 0x00000020U -#define R_SERIAL0_REC_CTRL__sampling__sampling__MASK 0x00000010U -#define R_SERIAL0_REC_CTRL__rec_stick_par__rec_stick_par__MASK 0x00000008U -#define R_SERIAL0_REC_CTRL__rec_par__rec_par__MASK 0x00000004U -#define R_SERIAL0_REC_CTRL__rec_par_en__rec_par_en__MASK 0x00000002U -#define R_SERIAL0_REC_CTRL__rec_bitnr__rec_bitnr__MASK 0x00000001U - -#define R_SERIAL0_REC_CTRL__dma_err__MAX 0x1 -#define R_SERIAL0_REC_CTRL__rec_enable__MAX 0x1 -#define R_SERIAL0_REC_CTRL__rts___MAX 0x1 -#define R_SERIAL0_REC_CTRL__sampling__MAX 0x1 -#define R_SERIAL0_REC_CTRL__rec_stick_par__MAX 0x1 -#define R_SERIAL0_REC_CTRL__rec_par__MAX 0x1 -#define R_SERIAL0_REC_CTRL__rec_par_en__MAX 0x1 -#define R_SERIAL0_REC_CTRL__rec_bitnr__MAX 0x1 - -#define R_SERIAL0_REC_CTRL__dma_err__MIN 0 -#define R_SERIAL0_REC_CTRL__rec_enable__MIN 0 -#define R_SERIAL0_REC_CTRL__rts___MIN 0 -#define R_SERIAL0_REC_CTRL__sampling__MIN 0 -#define R_SERIAL0_REC_CTRL__rec_stick_par__MIN 0 -#define R_SERIAL0_REC_CTRL__rec_par__MIN 0 -#define R_SERIAL0_REC_CTRL__rec_par_en__MIN 0 -#define R_SERIAL0_REC_CTRL__rec_bitnr__MIN 0 - -#define R_SERIAL0_REC_CTRL__dma_err__BITNR 7 -#define R_SERIAL0_REC_CTRL__rec_enable__BITNR 6 -#define R_SERIAL0_REC_CTRL__rts___BITNR 5 -#define R_SERIAL0_REC_CTRL__sampling__BITNR 4 -#define R_SERIAL0_REC_CTRL__rec_stick_par__BITNR 3 -#define R_SERIAL0_REC_CTRL__rec_par__BITNR 2 -#define R_SERIAL0_REC_CTRL__rec_par_en__BITNR 1 -#define R_SERIAL0_REC_CTRL__rec_bitnr__BITNR 0 - -#define R_SERIAL0_REC_CTRL__dma_err__dma_err__VAL REG_VAL_ENUM -#define R_SERIAL0_REC_CTRL__rec_enable__rec_enable__VAL REG_VAL_ENUM -#define R_SERIAL0_REC_CTRL__rts___rts___VAL REG_VAL_ENUM -#define R_SERIAL0_REC_CTRL__sampling__sampling__VAL REG_VAL_ENUM -#define R_SERIAL0_REC_CTRL__rec_stick_par__rec_stick_par__VAL REG_VAL_ENUM -#define R_SERIAL0_REC_CTRL__rec_par__rec_par__VAL REG_VAL_ENUM -#define R_SERIAL0_REC_CTRL__rec_par_en__rec_par_en__VAL REG_VAL_ENUM -#define R_SERIAL0_REC_CTRL__rec_bitnr__rec_bitnr__VAL REG_VAL_ENUM - -#define R_SERIAL0_REC_CTRL__dma_err__dma_err__ignore 1 -#define R_SERIAL0_REC_CTRL__dma_err__dma_err__stop 0 -#define R_SERIAL0_REC_CTRL__rec_enable__rec_enable__disable 0 -#define R_SERIAL0_REC_CTRL__rec_enable__rec_enable__enable 1 -#define R_SERIAL0_REC_CTRL__rts___rts___active 0 -#define R_SERIAL0_REC_CTRL__rts___rts___inactive 1 -#define R_SERIAL0_REC_CTRL__sampling__sampling__majority 1 -#define R_SERIAL0_REC_CTRL__sampling__sampling__middle 0 -#define R_SERIAL0_REC_CTRL__rec_stick_par__rec_stick_par__normal 0 -#define R_SERIAL0_REC_CTRL__rec_stick_par__rec_stick_par__stick 1 -#define R_SERIAL0_REC_CTRL__rec_par__rec_par__even 0 -#define R_SERIAL0_REC_CTRL__rec_par__rec_par__odd 1 -#define R_SERIAL0_REC_CTRL__rec_par_en__rec_par_en__disable 0 -#define R_SERIAL0_REC_CTRL__rec_par_en__rec_par_en__enable 1 -#define R_SERIAL0_REC_CTRL__rec_bitnr__rec_bitnr__rec_7bit 1 -#define R_SERIAL0_REC_CTRL__rec_bitnr__rec_bitnr__rec_8bit 0 - -#endif - -/* - * R_SERIAL0_REC_DATA - * - type: RO - * - addr: 0xb0000060 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -#define R_SERIAL0_REC_DATA__ADDR (REG_TYPECAST_BYTE 0xb0000060) -#define R_SERIAL0_REC_DATA__SVAL REG_SVAL_SHADOW -#define R_SERIAL0_REC_DATA__SVAL_I REG_SVAL_I_SHADOW -#define R_SERIAL0_REC_DATA__TYPECAST REG_TYPECAST_BYTE -#define R_SERIAL0_REC_DATA__TYPE (REG_BYTE) -#define R_SERIAL0_REC_DATA__GET REG_GET_RO -#define R_SERIAL0_REC_DATA__IGET REG_IGET_RO -#define R_SERIAL0_REC_DATA__SET REG_SET_RO -#define R_SERIAL0_REC_DATA__ISET REG_ISET_RO -#define R_SERIAL0_REC_DATA__SET_VAL REG_SET_VAL_RO -#define R_SERIAL0_REC_DATA__EQL REG_EQL_RO -#define R_SERIAL0_REC_DATA__IEQL REG_IEQL_RO -#define R_SERIAL0_REC_DATA__RD REG_RD_RO -#define R_SERIAL0_REC_DATA__IRD REG_IRD_RO -#define R_SERIAL0_REC_DATA__WR REG_WR_RO -#define R_SERIAL0_REC_DATA__IWR REG_IWR_RO - -#define R_SERIAL0_REC_DATA__READ(addr) \ - (*(addr)) - -/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */ -#define R_SERIAL0_REC_DATA__FIRST 0 -#define R_SERIAL0_REC_DATA__LAST 3 -#define R_SERIAL0_REC_DATA__OFFSET 8 -/* end */ - -#define R_SERIAL0_REC_DATA__data_in__data_in__MASK 0x000000ffU - -#define R_SERIAL0_REC_DATA__data_in__MAX 0xff - -#define R_SERIAL0_REC_DATA__data_in__MIN 0 - -#define R_SERIAL0_REC_DATA__data_in__BITNR 0 - -#define R_SERIAL0_REC_DATA__data_in__data_in__VAL REG_VAL_VAL - - -#endif - -/* - * R_SERIAL0_STATUS - * - type: RO - * - addr: 0xb0000061 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -#define R_SERIAL0_STATUS__ADDR (REG_TYPECAST_BYTE 0xb0000061) -#define R_SERIAL0_STATUS__SVAL REG_SVAL_SHADOW -#define R_SERIAL0_STATUS__SVAL_I REG_SVAL_I_SHADOW -#define R_SERIAL0_STATUS__TYPECAST REG_TYPECAST_BYTE -#define R_SERIAL0_STATUS__TYPE (REG_BYTE) -#define R_SERIAL0_STATUS__GET REG_GET_RO -#define R_SERIAL0_STATUS__IGET REG_IGET_RO -#define R_SERIAL0_STATUS__SET REG_SET_RO -#define R_SERIAL0_STATUS__ISET REG_ISET_RO -#define R_SERIAL0_STATUS__SET_VAL REG_SET_VAL_RO -#define R_SERIAL0_STATUS__EQL REG_EQL_RO -#define R_SERIAL0_STATUS__IEQL REG_IEQL_RO -#define R_SERIAL0_STATUS__RD REG_RD_RO -#define R_SERIAL0_STATUS__IRD REG_IRD_RO -#define R_SERIAL0_STATUS__WR REG_WR_RO -#define R_SERIAL0_STATUS__IWR REG_IWR_RO - -#define R_SERIAL0_STATUS__READ(addr) \ - (*(addr)) - -/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */ -#define R_SERIAL0_STATUS__FIRST 0 -#define R_SERIAL0_STATUS__LAST 3 -#define R_SERIAL0_STATUS__OFFSET 8 -/* end */ - -#define R_SERIAL0_STATUS__xoff_detect__xoff_detect__MASK 0x00000080U -#define R_SERIAL0_STATUS__cts___cts___MASK 0x00000040U -#define R_SERIAL0_STATUS__tr_ready__tr_ready__MASK 0x00000020U -#define R_SERIAL0_STATUS__rxd__rxd__MASK 0x00000010U -#define R_SERIAL0_STATUS__overrun__overrun__MASK 0x00000008U -#define R_SERIAL0_STATUS__par_err__par_err__MASK 0x00000004U -#define R_SERIAL0_STATUS__framing_err__framing_err__MASK 0x00000002U -#define R_SERIAL0_STATUS__data_avail__data_avail__MASK 0x00000001U - -#define R_SERIAL0_STATUS__xoff_detect__MAX 0x1 -#define R_SERIAL0_STATUS__cts___MAX 0x1 -#define R_SERIAL0_STATUS__tr_ready__MAX 0x1 -#define R_SERIAL0_STATUS__rxd__MAX 0x1 -#define R_SERIAL0_STATUS__overrun__MAX 0x1 -#define R_SERIAL0_STATUS__par_err__MAX 0x1 -#define R_SERIAL0_STATUS__framing_err__MAX 0x1 -#define R_SERIAL0_STATUS__data_avail__MAX 0x1 - -#define R_SERIAL0_STATUS__xoff_detect__MIN 0 -#define R_SERIAL0_STATUS__cts___MIN 0 -#define R_SERIAL0_STATUS__tr_ready__MIN 0 -#define R_SERIAL0_STATUS__rxd__MIN 0 -#define R_SERIAL0_STATUS__overrun__MIN 0 -#define R_SERIAL0_STATUS__par_err__MIN 0 -#define R_SERIAL0_STATUS__framing_err__MIN 0 -#define R_SERIAL0_STATUS__data_avail__MIN 0 - -#define R_SERIAL0_STATUS__xoff_detect__BITNR 7 -#define R_SERIAL0_STATUS__cts___BITNR 6 -#define R_SERIAL0_STATUS__tr_ready__BITNR 5 -#define R_SERIAL0_STATUS__rxd__BITNR 4 -#define R_SERIAL0_STATUS__overrun__BITNR 3 -#define R_SERIAL0_STATUS__par_err__BITNR 2 -#define R_SERIAL0_STATUS__framing_err__BITNR 1 -#define R_SERIAL0_STATUS__data_avail__BITNR 0 - -#define R_SERIAL0_STATUS__xoff_detect__xoff_detect__VAL REG_VAL_ENUM -#define R_SERIAL0_STATUS__cts___cts___VAL REG_VAL_ENUM -#define R_SERIAL0_STATUS__tr_ready__tr_ready__VAL REG_VAL_ENUM -#define R_SERIAL0_STATUS__rxd__rxd__VAL REG_VAL_VAL -#define R_SERIAL0_STATUS__overrun__overrun__VAL REG_VAL_ENUM -#define R_SERIAL0_STATUS__par_err__par_err__VAL REG_VAL_ENUM -#define R_SERIAL0_STATUS__framing_err__framing_err__VAL REG_VAL_ENUM -#define R_SERIAL0_STATUS__data_avail__data_avail__VAL REG_VAL_ENUM - -#define R_SERIAL0_STATUS__xoff_detect__xoff_detect__no_xoff 0 -#define R_SERIAL0_STATUS__xoff_detect__xoff_detect__xoff 1 -#define R_SERIAL0_STATUS__cts___cts___active 0 -#define R_SERIAL0_STATUS__cts___cts___inactive 1 -#define R_SERIAL0_STATUS__tr_ready__tr_ready__full 0 -#define R_SERIAL0_STATUS__tr_ready__tr_ready__ready 1 -#define R_SERIAL0_STATUS__overrun__overrun__no 0 -#define R_SERIAL0_STATUS__overrun__overrun__yes 1 -#define R_SERIAL0_STATUS__par_err__par_err__no 0 -#define R_SERIAL0_STATUS__par_err__par_err__yes 1 -#define R_SERIAL0_STATUS__framing_err__framing_err__no 0 -#define R_SERIAL0_STATUS__framing_err__framing_err__yes 1 -#define R_SERIAL0_STATUS__data_avail__data_avail__no 0 -#define R_SERIAL0_STATUS__data_avail__data_avail__yes 1 - -#endif - -/* - * R_SERIAL0_TR_CTRL - * - type: WO - * - addr: 0xb0000061 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -#define R_SERIAL0_TR_CTRL__ADDR (REG_TYPECAST_BYTE 0xb0000061) - -#ifndef REG_NO_SHADOW -#define R_SERIAL0_TR_CTRL__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL0_CTRL + 1)) -#define R_SERIAL0_TR_CTRL__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL0_CTRL + 1)) -#else /* REG_NO_SHADOW */ -#define R_SERIAL0_TR_CTRL__SADDR (REG_STYPECAST_BYTE (®_shadow__hwregs)) -#define R_SERIAL0_TR_CTRL__IADDR (REG_STYPECAST_BYTE (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_SERIAL0_TR_CTRL__STYPECAST REG_STYPECAST_BYTE -#define R_SERIAL0_TR_CTRL__SVAL REG_SVAL_SHADOW -#define R_SERIAL0_TR_CTRL__SVAL_I REG_SVAL_I_SHADOW -#define R_SERIAL0_TR_CTRL__TYPECAST REG_TYPECAST_BYTE -#define R_SERIAL0_TR_CTRL__TYPE (REG_BYTE) -#define R_SERIAL0_TR_CTRL__GET REG_GET_WO -#define R_SERIAL0_TR_CTRL__IGET REG_IGET_WO -#define R_SERIAL0_TR_CTRL__SET REG_SET_WO -#define R_SERIAL0_TR_CTRL__ISET REG_ISET_WO -#define R_SERIAL0_TR_CTRL__SET_VAL REG_SET_VAL_WO -#define R_SERIAL0_TR_CTRL__EQL REG_EQL_WO -#define R_SERIAL0_TR_CTRL__IEQL REG_IEQL_WO -#define R_SERIAL0_TR_CTRL__RD REG_RD_WO -#define R_SERIAL0_TR_CTRL__IRD REG_IRD_WO -#define R_SERIAL0_TR_CTRL__WR REG_WR_WO -#define R_SERIAL0_TR_CTRL__IWR REG_IWR_WO - -#define R_SERIAL0_TR_CTRL__WRITE(addr,value) \ - (*(addr) = (value)) - -/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */ -#define R_SERIAL0_TR_CTRL__FIRST 0 -#define R_SERIAL0_TR_CTRL__IOFFSET 8 -#define R_SERIAL0_TR_CTRL__LAST 3 -#define R_SERIAL0_TR_CTRL__OFFSET 8 -#define R_SERIAL0_TR_CTRL__SOFFSET 8 -/* end */ - -#define R_SERIAL0_TR_CTRL__txd__txd__MASK 0x00000080U -#define R_SERIAL0_TR_CTRL__tr_enable__tr_enable__MASK 0x00000040U -#define R_SERIAL0_TR_CTRL__auto_cts__auto_cts__MASK 0x00000020U -#define R_SERIAL0_TR_CTRL__stop_bits__stop_bits__MASK 0x00000010U -#define R_SERIAL0_TR_CTRL__tr_stick_par__tr_stick_par__MASK 0x00000008U -#define R_SERIAL0_TR_CTRL__tr_par__tr_par__MASK 0x00000004U -#define R_SERIAL0_TR_CTRL__tr_par_en__tr_par_en__MASK 0x00000002U -#define R_SERIAL0_TR_CTRL__tr_bitnr__tr_bitnr__MASK 0x00000001U - -#define R_SERIAL0_TR_CTRL__txd__MAX 0x1 -#define R_SERIAL0_TR_CTRL__tr_enable__MAX 0x1 -#define R_SERIAL0_TR_CTRL__auto_cts__MAX 0x1 -#define R_SERIAL0_TR_CTRL__stop_bits__MAX 0x1 -#define R_SERIAL0_TR_CTRL__tr_stick_par__MAX 0x1 -#define R_SERIAL0_TR_CTRL__tr_par__MAX 0x1 -#define R_SERIAL0_TR_CTRL__tr_par_en__MAX 0x1 -#define R_SERIAL0_TR_CTRL__tr_bitnr__MAX 0x1 - -#define R_SERIAL0_TR_CTRL__txd__MIN 0 -#define R_SERIAL0_TR_CTRL__tr_enable__MIN 0 -#define R_SERIAL0_TR_CTRL__auto_cts__MIN 0 -#define R_SERIAL0_TR_CTRL__stop_bits__MIN 0 -#define R_SERIAL0_TR_CTRL__tr_stick_par__MIN 0 -#define R_SERIAL0_TR_CTRL__tr_par__MIN 0 -#define R_SERIAL0_TR_CTRL__tr_par_en__MIN 0 -#define R_SERIAL0_TR_CTRL__tr_bitnr__MIN 0 - -#define R_SERIAL0_TR_CTRL__txd__BITNR 7 -#define R_SERIAL0_TR_CTRL__tr_enable__BITNR 6 -#define R_SERIAL0_TR_CTRL__auto_cts__BITNR 5 -#define R_SERIAL0_TR_CTRL__stop_bits__BITNR 4 -#define R_SERIAL0_TR_CTRL__tr_stick_par__BITNR 3 -#define R_SERIAL0_TR_CTRL__tr_par__BITNR 2 -#define R_SERIAL0_TR_CTRL__tr_par_en__BITNR 1 -#define R_SERIAL0_TR_CTRL__tr_bitnr__BITNR 0 - -#define R_SERIAL0_TR_CTRL__txd__txd__VAL REG_VAL_VAL -#define R_SERIAL0_TR_CTRL__tr_enable__tr_enable__VAL REG_VAL_ENUM -#define R_SERIAL0_TR_CTRL__auto_cts__auto_cts__VAL REG_VAL_ENUM -#define R_SERIAL0_TR_CTRL__stop_bits__stop_bits__VAL REG_VAL_ENUM -#define R_SERIAL0_TR_CTRL__tr_stick_par__tr_stick_par__VAL REG_VAL_ENUM -#define R_SERIAL0_TR_CTRL__tr_par__tr_par__VAL REG_VAL_ENUM -#define R_SERIAL0_TR_CTRL__tr_par_en__tr_par_en__VAL REG_VAL_ENUM -#define R_SERIAL0_TR_CTRL__tr_bitnr__tr_bitnr__VAL REG_VAL_ENUM - -#define R_SERIAL0_TR_CTRL__tr_enable__tr_enable__disable 0 -#define R_SERIAL0_TR_CTRL__tr_enable__tr_enable__enable 1 -#define R_SERIAL0_TR_CTRL__auto_cts__auto_cts__active 1 -#define R_SERIAL0_TR_CTRL__auto_cts__auto_cts__disabled 0 -#define R_SERIAL0_TR_CTRL__stop_bits__stop_bits__one_bit 0 -#define R_SERIAL0_TR_CTRL__stop_bits__stop_bits__two_bits 1 -#define R_SERIAL0_TR_CTRL__tr_stick_par__tr_stick_par__normal 0 -#define R_SERIAL0_TR_CTRL__tr_stick_par__tr_stick_par__stick 1 -#define R_SERIAL0_TR_CTRL__tr_par__tr_par__even 0 -#define R_SERIAL0_TR_CTRL__tr_par__tr_par__odd 1 -#define R_SERIAL0_TR_CTRL__tr_par_en__tr_par_en__disable 0 -#define R_SERIAL0_TR_CTRL__tr_par_en__tr_par_en__enable 1 -#define R_SERIAL0_TR_CTRL__tr_bitnr__tr_bitnr__tr_7bit 1 -#define R_SERIAL0_TR_CTRL__tr_bitnr__tr_bitnr__tr_8bit 0 - -#endif - -/* - * R_SERIAL0_TR_DATA - * - type: WO - * - addr: 0xb0000060 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -#define R_SERIAL0_TR_DATA__ADDR (REG_TYPECAST_BYTE 0xb0000060) - -#ifndef REG_NO_SHADOW -#define R_SERIAL0_TR_DATA__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL0_CTRL + 0)) -#define R_SERIAL0_TR_DATA__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL0_CTRL + 0)) -#else /* REG_NO_SHADOW */ -#define R_SERIAL0_TR_DATA__SADDR (REG_STYPECAST_BYTE (®_shadow__hwregs)) -#define R_SERIAL0_TR_DATA__IADDR (REG_STYPECAST_BYTE (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_SERIAL0_TR_DATA__STYPECAST REG_STYPECAST_BYTE -#define R_SERIAL0_TR_DATA__SVAL REG_SVAL_SHADOW -#define R_SERIAL0_TR_DATA__SVAL_I REG_SVAL_I_SHADOW -#define R_SERIAL0_TR_DATA__TYPECAST REG_TYPECAST_BYTE -#define R_SERIAL0_TR_DATA__TYPE (REG_BYTE) -#define R_SERIAL0_TR_DATA__GET REG_GET_WO -#define R_SERIAL0_TR_DATA__IGET REG_IGET_WO -#define R_SERIAL0_TR_DATA__SET REG_SET_WO -#define R_SERIAL0_TR_DATA__ISET REG_ISET_WO -#define R_SERIAL0_TR_DATA__SET_VAL REG_SET_VAL_WO -#define R_SERIAL0_TR_DATA__EQL REG_EQL_WO -#define R_SERIAL0_TR_DATA__IEQL REG_IEQL_WO -#define R_SERIAL0_TR_DATA__RD REG_RD_WO -#define R_SERIAL0_TR_DATA__IRD REG_IRD_WO -#define R_SERIAL0_TR_DATA__WR REG_WR_WO -#define R_SERIAL0_TR_DATA__IWR REG_IWR_WO - -#define R_SERIAL0_TR_DATA__WRITE(addr,value) \ - (*(addr) = (value)) - -/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */ -#define R_SERIAL0_TR_DATA__FIRST 0 -#define R_SERIAL0_TR_DATA__IOFFSET 8 -#define R_SERIAL0_TR_DATA__LAST 3 -#define R_SERIAL0_TR_DATA__OFFSET 8 -#define R_SERIAL0_TR_DATA__SOFFSET 8 -/* end */ - -#define R_SERIAL0_TR_DATA__data_out__data_out__MASK 0x000000ffU - -#define R_SERIAL0_TR_DATA__data_out__MAX 0xff - -#define R_SERIAL0_TR_DATA__data_out__MIN 0 - -#define R_SERIAL0_TR_DATA__data_out__BITNR 0 - -#define R_SERIAL0_TR_DATA__data_out__data_out__VAL REG_VAL_VAL - - -#endif - -/* - * R_SERIAL0_XOFF - * - type: WO - * - addr: 0xb0000064 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -#define R_SERIAL0_XOFF__ADDR (REG_TYPECAST_UDWORD 0xb0000064) - -#ifndef REG_NO_SHADOW -#define R_SERIAL0_XOFF__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_SERIAL0_XOFF + 0)) -#define R_SERIAL0_XOFF__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_SERIAL0_XOFF + 0)) -#else /* REG_NO_SHADOW */ -#define R_SERIAL0_XOFF__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_SERIAL0_XOFF__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_SERIAL0_XOFF__STYPECAST REG_STYPECAST_UDWORD -#define R_SERIAL0_XOFF__SVAL REG_SVAL_SHADOW -#define R_SERIAL0_XOFF__SVAL_I REG_SVAL_I_SHADOW -#define R_SERIAL0_XOFF__TYPECAST REG_TYPECAST_UDWORD -#define R_SERIAL0_XOFF__TYPE (REG_UDWORD) -#define R_SERIAL0_XOFF__GET REG_GET_WO -#define R_SERIAL0_XOFF__IGET REG_IGET_WO -#define R_SERIAL0_XOFF__SET REG_SET_WO -#define R_SERIAL0_XOFF__ISET REG_ISET_WO -#define R_SERIAL0_XOFF__SET_VAL REG_SET_VAL_WO -#define R_SERIAL0_XOFF__EQL REG_EQL_WO -#define R_SERIAL0_XOFF__IEQL REG_IEQL_WO -#define R_SERIAL0_XOFF__RD REG_RD_WO -#define R_SERIAL0_XOFF__IRD REG_IRD_WO -#define R_SERIAL0_XOFF__WR REG_WR_WO -#define R_SERIAL0_XOFF__IWR REG_IWR_WO - -#define R_SERIAL0_XOFF__WRITE(addr,value) \ - (*(addr) = (value)) - -/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */ -#define R_SERIAL0_XOFF__FIRST 0 -#define R_SERIAL0_XOFF__IOFFSET 8 -#define R_SERIAL0_XOFF__LAST 3 -#define R_SERIAL0_XOFF__OFFSET 8 -#define R_SERIAL0_XOFF__SOFFSET 8 -/* end */ - -#define R_SERIAL0_XOFF__tx_stop__tx_stop__MASK 0x00000200U -#define R_SERIAL0_XOFF__auto_xoff__auto_xoff__MASK 0x00000100U -#define R_SERIAL0_XOFF__xoff_char__xoff_char__MASK 0x000000ffU - -#define R_SERIAL0_XOFF__tx_stop__MAX 0x1 -#define R_SERIAL0_XOFF__auto_xoff__MAX 0x1 -#define R_SERIAL0_XOFF__xoff_char__MAX 0xff - -#define R_SERIAL0_XOFF__tx_stop__MIN 0 -#define R_SERIAL0_XOFF__auto_xoff__MIN 0 -#define R_SERIAL0_XOFF__xoff_char__MIN 0 - -#define R_SERIAL0_XOFF__tx_stop__BITNR 9 -#define R_SERIAL0_XOFF__auto_xoff__BITNR 8 -#define R_SERIAL0_XOFF__xoff_char__BITNR 0 - -#define R_SERIAL0_XOFF__tx_stop__tx_stop__VAL REG_VAL_ENUM -#define R_SERIAL0_XOFF__auto_xoff__auto_xoff__VAL REG_VAL_ENUM -#define R_SERIAL0_XOFF__xoff_char__xoff_char__VAL REG_VAL_VAL - -#define R_SERIAL0_XOFF__tx_stop__tx_stop__enable 0 -#define R_SERIAL0_XOFF__tx_stop__tx_stop__stop 1 -#define R_SERIAL0_XOFF__auto_xoff__auto_xoff__disable 0 -#define R_SERIAL0_XOFF__auto_xoff__auto_xoff__enable 1 - -#endif - -/* - * R_SERIAL1_BAUD - * - type: WO - * - addr: 0xb000006b - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -#define R_SERIAL1_BAUD__ADDR (REG_TYPECAST_BYTE 0xb000006b) - -#ifndef REG_NO_SHADOW -#define R_SERIAL1_BAUD__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL1_CTRL + 3)) -#define R_SERIAL1_BAUD__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL1_CTRL + 3)) -#else /* REG_NO_SHADOW */ -#define R_SERIAL1_BAUD__SADDR (REG_STYPECAST_BYTE (®_shadow__hwregs)) -#define R_SERIAL1_BAUD__IADDR (REG_STYPECAST_BYTE (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_SERIAL1_BAUD__STYPECAST REG_STYPECAST_BYTE -#define R_SERIAL1_BAUD__SVAL REG_SVAL_SHADOW -#define R_SERIAL1_BAUD__SVAL_I REG_SVAL_I_SHADOW -#define R_SERIAL1_BAUD__TYPECAST REG_TYPECAST_BYTE -#define R_SERIAL1_BAUD__TYPE (REG_BYTE) -#define R_SERIAL1_BAUD__GET REG_GET_WO -#define R_SERIAL1_BAUD__IGET REG_IGET_WO -#define R_SERIAL1_BAUD__SET REG_SET_WO -#define R_SERIAL1_BAUD__ISET REG_ISET_WO -#define R_SERIAL1_BAUD__SET_VAL REG_SET_VAL_WO -#define R_SERIAL1_BAUD__EQL REG_EQL_WO -#define R_SERIAL1_BAUD__IEQL REG_IEQL_WO -#define R_SERIAL1_BAUD__RD REG_RD_WO -#define R_SERIAL1_BAUD__IRD REG_IRD_WO -#define R_SERIAL1_BAUD__WR REG_WR_WO -#define R_SERIAL1_BAUD__IWR REG_IWR_WO - -#define R_SERIAL1_BAUD__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_SERIAL1_BAUD__tr_baud__tr_baud__MASK 0x000000f0U -#define R_SERIAL1_BAUD__rec_baud__rec_baud__MASK 0x0000000fU - -#define R_SERIAL1_BAUD__tr_baud__MAX 0xf -#define R_SERIAL1_BAUD__rec_baud__MAX 0xf - -#define R_SERIAL1_BAUD__tr_baud__MIN 0 -#define R_SERIAL1_BAUD__rec_baud__MIN 0 - -#define R_SERIAL1_BAUD__tr_baud__BITNR 4 -#define R_SERIAL1_BAUD__rec_baud__BITNR 0 - -#define R_SERIAL1_BAUD__tr_baud__tr_baud__VAL REG_VAL_ENUM -#define R_SERIAL1_BAUD__rec_baud__rec_baud__VAL REG_VAL_ENUM - -#define R_SERIAL1_BAUD__tr_baud__tr_baud__c115k2Hz 9 -#define R_SERIAL1_BAUD__tr_baud__tr_baud__c1200Hz 2 -#define R_SERIAL1_BAUD__tr_baud__tr_baud__c1843k2Hz 13 -#define R_SERIAL1_BAUD__tr_baud__tr_baud__c19k2Hz 6 -#define R_SERIAL1_BAUD__tr_baud__tr_baud__c230k4Hz 10 -#define R_SERIAL1_BAUD__tr_baud__tr_baud__c2400Hz 3 -#define R_SERIAL1_BAUD__tr_baud__tr_baud__c300Hz 0 -#define R_SERIAL1_BAUD__tr_baud__tr_baud__c38k4Hz 7 -#define R_SERIAL1_BAUD__tr_baud__tr_baud__c460k8Hz 11 -#define R_SERIAL1_BAUD__tr_baud__tr_baud__c4800Hz 4 -#define R_SERIAL1_BAUD__tr_baud__tr_baud__c57k6Hz 8 -#define R_SERIAL1_BAUD__tr_baud__tr_baud__c600Hz 1 -#define R_SERIAL1_BAUD__tr_baud__tr_baud__c6250kHz 14 -#define R_SERIAL1_BAUD__tr_baud__tr_baud__c921k6Hz 12 -#define R_SERIAL1_BAUD__tr_baud__tr_baud__c9600Hz 5 -#define R_SERIAL1_BAUD__rec_baud__rec_baud__c115k2Hz 9 -#define R_SERIAL1_BAUD__rec_baud__rec_baud__c1200Hz 2 -#define R_SERIAL1_BAUD__rec_baud__rec_baud__c1843k2Hz 13 -#define R_SERIAL1_BAUD__rec_baud__rec_baud__c19k2Hz 6 -#define R_SERIAL1_BAUD__rec_baud__rec_baud__c230k4Hz 10 -#define R_SERIAL1_BAUD__rec_baud__rec_baud__c2400Hz 3 -#define R_SERIAL1_BAUD__rec_baud__rec_baud__c300Hz 0 -#define R_SERIAL1_BAUD__rec_baud__rec_baud__c38k4Hz 7 -#define R_SERIAL1_BAUD__rec_baud__rec_baud__c460k8Hz 11 -#define R_SERIAL1_BAUD__rec_baud__rec_baud__c4800Hz 4 -#define R_SERIAL1_BAUD__rec_baud__rec_baud__c57k6Hz 8 -#define R_SERIAL1_BAUD__rec_baud__rec_baud__c600Hz 1 -#define R_SERIAL1_BAUD__rec_baud__rec_baud__c6250kHz 14 -#define R_SERIAL1_BAUD__rec_baud__rec_baud__c921k6Hz 12 -#define R_SERIAL1_BAUD__rec_baud__rec_baud__c9600Hz 5 - -#endif - -/* - * R_SERIAL1_CTRL - * - type: WO - * - addr: 0xb0000068 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -#define R_SERIAL1_CTRL__ADDR (REG_TYPECAST_UDWORD 0xb0000068) - -#ifndef REG_NO_SHADOW -#define R_SERIAL1_CTRL__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_SERIAL1_CTRL + 0)) -#define R_SERIAL1_CTRL__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_SERIAL1_CTRL + 0)) -#else /* REG_NO_SHADOW */ -#define R_SERIAL1_CTRL__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_SERIAL1_CTRL__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_SERIAL1_CTRL__STYPECAST REG_STYPECAST_UDWORD -#define R_SERIAL1_CTRL__SVAL REG_SVAL_SHADOW -#define R_SERIAL1_CTRL__SVAL_I REG_SVAL_I_SHADOW -#define R_SERIAL1_CTRL__TYPECAST REG_TYPECAST_UDWORD -#define R_SERIAL1_CTRL__TYPE (REG_UDWORD) -#define R_SERIAL1_CTRL__GET REG_GET_WO -#define R_SERIAL1_CTRL__IGET REG_IGET_WO -#define R_SERIAL1_CTRL__SET REG_SET_WO -#define R_SERIAL1_CTRL__ISET REG_ISET_WO -#define R_SERIAL1_CTRL__SET_VAL REG_SET_VAL_WO -#define R_SERIAL1_CTRL__EQL REG_EQL_WO -#define R_SERIAL1_CTRL__IEQL REG_IEQL_WO -#define R_SERIAL1_CTRL__RD REG_RD_WO -#define R_SERIAL1_CTRL__IRD REG_IRD_WO -#define R_SERIAL1_CTRL__WR REG_WR_WO -#define R_SERIAL1_CTRL__IWR REG_IWR_WO - -#define R_SERIAL1_CTRL__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_SERIAL1_CTRL__tr_baud__tr_baud__MASK 0xf0000000U -#define R_SERIAL1_CTRL__rec_baud__rec_baud__MASK 0x0f000000U -#define R_SERIAL1_CTRL__dma_err__dma_err__MASK 0x00800000U -#define R_SERIAL1_CTRL__rec_enable__rec_enable__MASK 0x00400000U -#define R_SERIAL1_CTRL__rts___rts___MASK 0x00200000U -#define R_SERIAL1_CTRL__sampling__sampling__MASK 0x00100000U -#define R_SERIAL1_CTRL__rec_stick_par__rec_stick_par__MASK 0x00080000U -#define R_SERIAL1_CTRL__rec_par__rec_par__MASK 0x00040000U -#define R_SERIAL1_CTRL__rec_par_en__rec_par_en__MASK 0x00020000U -#define R_SERIAL1_CTRL__rec_bitnr__rec_bitnr__MASK 0x00010000U -#define R_SERIAL1_CTRL__txd__txd__MASK 0x00008000U -#define R_SERIAL1_CTRL__tr_enable__tr_enable__MASK 0x00004000U -#define R_SERIAL1_CTRL__auto_cts__auto_cts__MASK 0x00002000U -#define R_SERIAL1_CTRL__stop_bits__stop_bits__MASK 0x00001000U -#define R_SERIAL1_CTRL__tr_stick_par__tr_stick_par__MASK 0x00000800U -#define R_SERIAL1_CTRL__tr_par__tr_par__MASK 0x00000400U -#define R_SERIAL1_CTRL__tr_par_en__tr_par_en__MASK 0x00000200U -#define R_SERIAL1_CTRL__tr_bitnr__tr_bitnr__MASK 0x00000100U -#define R_SERIAL1_CTRL__data_out__data_out__MASK 0x000000ffU - -#define R_SERIAL1_CTRL__tr_baud__MAX 0xf -#define R_SERIAL1_CTRL__rec_baud__MAX 0xf -#define R_SERIAL1_CTRL__dma_err__MAX 0x1 -#define R_SERIAL1_CTRL__rec_enable__MAX 0x1 -#define R_SERIAL1_CTRL__rts___MAX 0x1 -#define R_SERIAL1_CTRL__sampling__MAX 0x1 -#define R_SERIAL1_CTRL__rec_stick_par__MAX 0x1 -#define R_SERIAL1_CTRL__rec_par__MAX 0x1 -#define R_SERIAL1_CTRL__rec_par_en__MAX 0x1 -#define R_SERIAL1_CTRL__rec_bitnr__MAX 0x1 -#define R_SERIAL1_CTRL__txd__MAX 0x1 -#define R_SERIAL1_CTRL__tr_enable__MAX 0x1 -#define R_SERIAL1_CTRL__auto_cts__MAX 0x1 -#define R_SERIAL1_CTRL__stop_bits__MAX 0x1 -#define R_SERIAL1_CTRL__tr_stick_par__MAX 0x1 -#define R_SERIAL1_CTRL__tr_par__MAX 0x1 -#define R_SERIAL1_CTRL__tr_par_en__MAX 0x1 -#define R_SERIAL1_CTRL__tr_bitnr__MAX 0x1 -#define R_SERIAL1_CTRL__data_out__MAX 0xff - -#define R_SERIAL1_CTRL__tr_baud__MIN 0 -#define R_SERIAL1_CTRL__rec_baud__MIN 0 -#define R_SERIAL1_CTRL__dma_err__MIN 0 -#define R_SERIAL1_CTRL__rec_enable__MIN 0 -#define R_SERIAL1_CTRL__rts___MIN 0 -#define R_SERIAL1_CTRL__sampling__MIN 0 -#define R_SERIAL1_CTRL__rec_stick_par__MIN 0 -#define R_SERIAL1_CTRL__rec_par__MIN 0 -#define R_SERIAL1_CTRL__rec_par_en__MIN 0 -#define R_SERIAL1_CTRL__rec_bitnr__MIN 0 -#define R_SERIAL1_CTRL__txd__MIN 0 -#define R_SERIAL1_CTRL__tr_enable__MIN 0 -#define R_SERIAL1_CTRL__auto_cts__MIN 0 -#define R_SERIAL1_CTRL__stop_bits__MIN 0 -#define R_SERIAL1_CTRL__tr_stick_par__MIN 0 -#define R_SERIAL1_CTRL__tr_par__MIN 0 -#define R_SERIAL1_CTRL__tr_par_en__MIN 0 -#define R_SERIAL1_CTRL__tr_bitnr__MIN 0 -#define R_SERIAL1_CTRL__data_out__MIN 0 - -#define R_SERIAL1_CTRL__tr_baud__BITNR 28 -#define R_SERIAL1_CTRL__rec_baud__BITNR 24 -#define R_SERIAL1_CTRL__dma_err__BITNR 23 -#define R_SERIAL1_CTRL__rec_enable__BITNR 22 -#define R_SERIAL1_CTRL__rts___BITNR 21 -#define R_SERIAL1_CTRL__sampling__BITNR 20 -#define R_SERIAL1_CTRL__rec_stick_par__BITNR 19 -#define R_SERIAL1_CTRL__rec_par__BITNR 18 -#define R_SERIAL1_CTRL__rec_par_en__BITNR 17 -#define R_SERIAL1_CTRL__rec_bitnr__BITNR 16 -#define R_SERIAL1_CTRL__txd__BITNR 15 -#define R_SERIAL1_CTRL__tr_enable__BITNR 14 -#define R_SERIAL1_CTRL__auto_cts__BITNR 13 -#define R_SERIAL1_CTRL__stop_bits__BITNR 12 -#define R_SERIAL1_CTRL__tr_stick_par__BITNR 11 -#define R_SERIAL1_CTRL__tr_par__BITNR 10 -#define R_SERIAL1_CTRL__tr_par_en__BITNR 9 -#define R_SERIAL1_CTRL__tr_bitnr__BITNR 8 -#define R_SERIAL1_CTRL__data_out__BITNR 0 - -#define R_SERIAL1_CTRL__tr_baud__tr_baud__VAL REG_VAL_ENUM -#define R_SERIAL1_CTRL__rec_baud__rec_baud__VAL REG_VAL_ENUM -#define R_SERIAL1_CTRL__dma_err__dma_err__VAL REG_VAL_ENUM -#define R_SERIAL1_CTRL__rec_enable__rec_enable__VAL REG_VAL_ENUM -#define R_SERIAL1_CTRL__rts___rts___VAL REG_VAL_ENUM -#define R_SERIAL1_CTRL__sampling__sampling__VAL REG_VAL_ENUM -#define R_SERIAL1_CTRL__rec_stick_par__rec_stick_par__VAL REG_VAL_ENUM -#define R_SERIAL1_CTRL__rec_par__rec_par__VAL REG_VAL_ENUM -#define R_SERIAL1_CTRL__rec_par_en__rec_par_en__VAL REG_VAL_ENUM -#define R_SERIAL1_CTRL__rec_bitnr__rec_bitnr__VAL REG_VAL_ENUM -#define R_SERIAL1_CTRL__txd__txd__VAL REG_VAL_VAL -#define R_SERIAL1_CTRL__tr_enable__tr_enable__VAL REG_VAL_ENUM -#define R_SERIAL1_CTRL__auto_cts__auto_cts__VAL REG_VAL_ENUM -#define R_SERIAL1_CTRL__stop_bits__stop_bits__VAL REG_VAL_ENUM -#define R_SERIAL1_CTRL__tr_stick_par__tr_stick_par__VAL REG_VAL_ENUM -#define R_SERIAL1_CTRL__tr_par__tr_par__VAL REG_VAL_ENUM -#define R_SERIAL1_CTRL__tr_par_en__tr_par_en__VAL REG_VAL_ENUM -#define R_SERIAL1_CTRL__tr_bitnr__tr_bitnr__VAL REG_VAL_ENUM -#define R_SERIAL1_CTRL__data_out__data_out__VAL REG_VAL_VAL - -#define R_SERIAL1_CTRL__tr_baud__tr_baud__c115k2Hz 9 -#define R_SERIAL1_CTRL__tr_baud__tr_baud__c1200Hz 2 -#define R_SERIAL1_CTRL__tr_baud__tr_baud__c1843k2Hz 13 -#define R_SERIAL1_CTRL__tr_baud__tr_baud__c19k2Hz 6 -#define R_SERIAL1_CTRL__tr_baud__tr_baud__c230k4Hz 10 -#define R_SERIAL1_CTRL__tr_baud__tr_baud__c2400Hz 3 -#define R_SERIAL1_CTRL__tr_baud__tr_baud__c300Hz 0 -#define R_SERIAL1_CTRL__tr_baud__tr_baud__c38k4Hz 7 -#define R_SERIAL1_CTRL__tr_baud__tr_baud__c460k8Hz 11 -#define R_SERIAL1_CTRL__tr_baud__tr_baud__c4800Hz 4 -#define R_SERIAL1_CTRL__tr_baud__tr_baud__c57k6Hz 8 -#define R_SERIAL1_CTRL__tr_baud__tr_baud__c600Hz 1 -#define R_SERIAL1_CTRL__tr_baud__tr_baud__c6250kHz 14 -#define R_SERIAL1_CTRL__tr_baud__tr_baud__c921k6Hz 12 -#define R_SERIAL1_CTRL__tr_baud__tr_baud__c9600Hz 5 -#define R_SERIAL1_CTRL__rec_baud__rec_baud__c115k2Hz 9 -#define R_SERIAL1_CTRL__rec_baud__rec_baud__c1200Hz 2 -#define R_SERIAL1_CTRL__rec_baud__rec_baud__c1843k2Hz 13 -#define R_SERIAL1_CTRL__rec_baud__rec_baud__c19k2Hz 6 -#define R_SERIAL1_CTRL__rec_baud__rec_baud__c230k4Hz 10 -#define R_SERIAL1_CTRL__rec_baud__rec_baud__c2400Hz 3 -#define R_SERIAL1_CTRL__rec_baud__rec_baud__c300Hz 0 -#define R_SERIAL1_CTRL__rec_baud__rec_baud__c38k4Hz 7 -#define R_SERIAL1_CTRL__rec_baud__rec_baud__c460k8Hz 11 -#define R_SERIAL1_CTRL__rec_baud__rec_baud__c4800Hz 4 -#define R_SERIAL1_CTRL__rec_baud__rec_baud__c57k6Hz 8 -#define R_SERIAL1_CTRL__rec_baud__rec_baud__c600Hz 1 -#define R_SERIAL1_CTRL__rec_baud__rec_baud__c6250kHz 14 -#define R_SERIAL1_CTRL__rec_baud__rec_baud__c921k6Hz 12 -#define R_SERIAL1_CTRL__rec_baud__rec_baud__c9600Hz 5 -#define R_SERIAL1_CTRL__dma_err__dma_err__ignore 1 -#define R_SERIAL1_CTRL__dma_err__dma_err__stop 0 -#define R_SERIAL1_CTRL__rec_enable__rec_enable__disable 0 -#define R_SERIAL1_CTRL__rec_enable__rec_enable__enable 1 -#define R_SERIAL1_CTRL__rts___rts___active 0 -#define R_SERIAL1_CTRL__rts___rts___inactive 1 -#define R_SERIAL1_CTRL__sampling__sampling__majority 1 -#define R_SERIAL1_CTRL__sampling__sampling__middle 0 -#define R_SERIAL1_CTRL__rec_stick_par__rec_stick_par__normal 0 -#define R_SERIAL1_CTRL__rec_stick_par__rec_stick_par__stick 1 -#define R_SERIAL1_CTRL__rec_par__rec_par__even 0 -#define R_SERIAL1_CTRL__rec_par__rec_par__odd 1 -#define R_SERIAL1_CTRL__rec_par_en__rec_par_en__disable 0 -#define R_SERIAL1_CTRL__rec_par_en__rec_par_en__enable 1 -#define R_SERIAL1_CTRL__rec_bitnr__rec_bitnr__rec_7bit 1 -#define R_SERIAL1_CTRL__rec_bitnr__rec_bitnr__rec_8bit 0 -#define R_SERIAL1_CTRL__tr_enable__tr_enable__disable 0 -#define R_SERIAL1_CTRL__tr_enable__tr_enable__enable 1 -#define R_SERIAL1_CTRL__auto_cts__auto_cts__active 1 -#define R_SERIAL1_CTRL__auto_cts__auto_cts__disabled 0 -#define R_SERIAL1_CTRL__stop_bits__stop_bits__one_bit 0 -#define R_SERIAL1_CTRL__stop_bits__stop_bits__two_bits 1 -#define R_SERIAL1_CTRL__tr_stick_par__tr_stick_par__normal 0 -#define R_SERIAL1_CTRL__tr_stick_par__tr_stick_par__stick 1 -#define R_SERIAL1_CTRL__tr_par__tr_par__even 0 -#define R_SERIAL1_CTRL__tr_par__tr_par__odd 1 -#define R_SERIAL1_CTRL__tr_par_en__tr_par_en__disable 0 -#define R_SERIAL1_CTRL__tr_par_en__tr_par_en__enable 1 -#define R_SERIAL1_CTRL__tr_bitnr__tr_bitnr__tr_7bit 1 -#define R_SERIAL1_CTRL__tr_bitnr__tr_bitnr__tr_8bit 0 - -#endif - -/* - * R_SERIAL1_READ - * - type: RO - * - addr: 0xb0000068 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -#define R_SERIAL1_READ__ADDR (REG_TYPECAST_UDWORD 0xb0000068) -#define R_SERIAL1_READ__SVAL REG_SVAL_SHADOW -#define R_SERIAL1_READ__SVAL_I REG_SVAL_I_SHADOW -#define R_SERIAL1_READ__TYPECAST REG_TYPECAST_UDWORD -#define R_SERIAL1_READ__TYPE (REG_UDWORD) -#define R_SERIAL1_READ__GET REG_GET_RO -#define R_SERIAL1_READ__IGET REG_IGET_RO -#define R_SERIAL1_READ__SET REG_SET_RO -#define R_SERIAL1_READ__ISET REG_ISET_RO -#define R_SERIAL1_READ__SET_VAL REG_SET_VAL_RO -#define R_SERIAL1_READ__EQL REG_EQL_RO -#define R_SERIAL1_READ__IEQL REG_IEQL_RO -#define R_SERIAL1_READ__RD REG_RD_RO -#define R_SERIAL1_READ__IRD REG_IRD_RO -#define R_SERIAL1_READ__WR REG_WR_RO -#define R_SERIAL1_READ__IWR REG_IWR_RO - -#define R_SERIAL1_READ__READ(addr) \ - (*(addr)) - -#define R_SERIAL1_READ__xoff_detect__xoff_detect__MASK 0x00008000U -#define R_SERIAL1_READ__cts___cts___MASK 0x00004000U -#define R_SERIAL1_READ__tr_ready__tr_ready__MASK 0x00002000U -#define R_SERIAL1_READ__rxd__rxd__MASK 0x00001000U -#define R_SERIAL1_READ__overrun__overrun__MASK 0x00000800U -#define R_SERIAL1_READ__par_err__par_err__MASK 0x00000400U -#define R_SERIAL1_READ__framing_err__framing_err__MASK 0x00000200U -#define R_SERIAL1_READ__data_avail__data_avail__MASK 0x00000100U -#define R_SERIAL1_READ__data_in__data_in__MASK 0x000000ffU - -#define R_SERIAL1_READ__xoff_detect__MAX 0x1 -#define R_SERIAL1_READ__cts___MAX 0x1 -#define R_SERIAL1_READ__tr_ready__MAX 0x1 -#define R_SERIAL1_READ__rxd__MAX 0x1 -#define R_SERIAL1_READ__overrun__MAX 0x1 -#define R_SERIAL1_READ__par_err__MAX 0x1 -#define R_SERIAL1_READ__framing_err__MAX 0x1 -#define R_SERIAL1_READ__data_avail__MAX 0x1 -#define R_SERIAL1_READ__data_in__MAX 0xff - -#define R_SERIAL1_READ__xoff_detect__MIN 0 -#define R_SERIAL1_READ__cts___MIN 0 -#define R_SERIAL1_READ__tr_ready__MIN 0 -#define R_SERIAL1_READ__rxd__MIN 0 -#define R_SERIAL1_READ__overrun__MIN 0 -#define R_SERIAL1_READ__par_err__MIN 0 -#define R_SERIAL1_READ__framing_err__MIN 0 -#define R_SERIAL1_READ__data_avail__MIN 0 -#define R_SERIAL1_READ__data_in__MIN 0 - -#define R_SERIAL1_READ__xoff_detect__BITNR 15 -#define R_SERIAL1_READ__cts___BITNR 14 -#define R_SERIAL1_READ__tr_ready__BITNR 13 -#define R_SERIAL1_READ__rxd__BITNR 12 -#define R_SERIAL1_READ__overrun__BITNR 11 -#define R_SERIAL1_READ__par_err__BITNR 10 -#define R_SERIAL1_READ__framing_err__BITNR 9 -#define R_SERIAL1_READ__data_avail__BITNR 8 -#define R_SERIAL1_READ__data_in__BITNR 0 - -#define R_SERIAL1_READ__xoff_detect__xoff_detect__VAL REG_VAL_ENUM -#define R_SERIAL1_READ__cts___cts___VAL REG_VAL_ENUM -#define R_SERIAL1_READ__tr_ready__tr_ready__VAL REG_VAL_ENUM -#define R_SERIAL1_READ__rxd__rxd__VAL REG_VAL_VAL -#define R_SERIAL1_READ__overrun__overrun__VAL REG_VAL_ENUM -#define R_SERIAL1_READ__par_err__par_err__VAL REG_VAL_ENUM -#define R_SERIAL1_READ__framing_err__framing_err__VAL REG_VAL_ENUM -#define R_SERIAL1_READ__data_avail__data_avail__VAL REG_VAL_ENUM -#define R_SERIAL1_READ__data_in__data_in__VAL REG_VAL_VAL - -#define R_SERIAL1_READ__xoff_detect__xoff_detect__no_xoff 0 -#define R_SERIAL1_READ__xoff_detect__xoff_detect__xoff 1 -#define R_SERIAL1_READ__cts___cts___active 0 -#define R_SERIAL1_READ__cts___cts___inactive 1 -#define R_SERIAL1_READ__tr_ready__tr_ready__full 0 -#define R_SERIAL1_READ__tr_ready__tr_ready__ready 1 -#define R_SERIAL1_READ__overrun__overrun__no 0 -#define R_SERIAL1_READ__overrun__overrun__yes 1 -#define R_SERIAL1_READ__par_err__par_err__no 0 -#define R_SERIAL1_READ__par_err__par_err__yes 1 -#define R_SERIAL1_READ__framing_err__framing_err__no 0 -#define R_SERIAL1_READ__framing_err__framing_err__yes 1 -#define R_SERIAL1_READ__data_avail__data_avail__no 0 -#define R_SERIAL1_READ__data_avail__data_avail__yes 1 - -#endif - -/* - * R_SERIAL1_REC_CTRL - * - type: WO - * - addr: 0xb000006a - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -#define R_SERIAL1_REC_CTRL__ADDR (REG_TYPECAST_BYTE 0xb000006a) - -#ifndef REG_NO_SHADOW -#define R_SERIAL1_REC_CTRL__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL1_CTRL + 2)) -#define R_SERIAL1_REC_CTRL__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL1_CTRL + 2)) -#else /* REG_NO_SHADOW */ -#define R_SERIAL1_REC_CTRL__SADDR (REG_STYPECAST_BYTE (®_shadow__hwregs)) -#define R_SERIAL1_REC_CTRL__IADDR (REG_STYPECAST_BYTE (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_SERIAL1_REC_CTRL__STYPECAST REG_STYPECAST_BYTE -#define R_SERIAL1_REC_CTRL__SVAL REG_SVAL_SHADOW -#define R_SERIAL1_REC_CTRL__SVAL_I REG_SVAL_I_SHADOW -#define R_SERIAL1_REC_CTRL__TYPECAST REG_TYPECAST_BYTE -#define R_SERIAL1_REC_CTRL__TYPE (REG_BYTE) -#define R_SERIAL1_REC_CTRL__GET REG_GET_WO -#define R_SERIAL1_REC_CTRL__IGET REG_IGET_WO -#define R_SERIAL1_REC_CTRL__SET REG_SET_WO -#define R_SERIAL1_REC_CTRL__ISET REG_ISET_WO -#define R_SERIAL1_REC_CTRL__SET_VAL REG_SET_VAL_WO -#define R_SERIAL1_REC_CTRL__EQL REG_EQL_WO -#define R_SERIAL1_REC_CTRL__IEQL REG_IEQL_WO -#define R_SERIAL1_REC_CTRL__RD REG_RD_WO -#define R_SERIAL1_REC_CTRL__IRD REG_IRD_WO -#define R_SERIAL1_REC_CTRL__WR REG_WR_WO -#define R_SERIAL1_REC_CTRL__IWR REG_IWR_WO - -#define R_SERIAL1_REC_CTRL__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_SERIAL1_REC_CTRL__dma_err__dma_err__MASK 0x00000080U -#define R_SERIAL1_REC_CTRL__rec_enable__rec_enable__MASK 0x00000040U -#define R_SERIAL1_REC_CTRL__rts___rts___MASK 0x00000020U -#define R_SERIAL1_REC_CTRL__sampling__sampling__MASK 0x00000010U -#define R_SERIAL1_REC_CTRL__rec_stick_par__rec_stick_par__MASK 0x00000008U -#define R_SERIAL1_REC_CTRL__rec_par__rec_par__MASK 0x00000004U -#define R_SERIAL1_REC_CTRL__rec_par_en__rec_par_en__MASK 0x00000002U -#define R_SERIAL1_REC_CTRL__rec_bitnr__rec_bitnr__MASK 0x00000001U - -#define R_SERIAL1_REC_CTRL__dma_err__MAX 0x1 -#define R_SERIAL1_REC_CTRL__rec_enable__MAX 0x1 -#define R_SERIAL1_REC_CTRL__rts___MAX 0x1 -#define R_SERIAL1_REC_CTRL__sampling__MAX 0x1 -#define R_SERIAL1_REC_CTRL__rec_stick_par__MAX 0x1 -#define R_SERIAL1_REC_CTRL__rec_par__MAX 0x1 -#define R_SERIAL1_REC_CTRL__rec_par_en__MAX 0x1 -#define R_SERIAL1_REC_CTRL__rec_bitnr__MAX 0x1 - -#define R_SERIAL1_REC_CTRL__dma_err__MIN 0 -#define R_SERIAL1_REC_CTRL__rec_enable__MIN 0 -#define R_SERIAL1_REC_CTRL__rts___MIN 0 -#define R_SERIAL1_REC_CTRL__sampling__MIN 0 -#define R_SERIAL1_REC_CTRL__rec_stick_par__MIN 0 -#define R_SERIAL1_REC_CTRL__rec_par__MIN 0 -#define R_SERIAL1_REC_CTRL__rec_par_en__MIN 0 -#define R_SERIAL1_REC_CTRL__rec_bitnr__MIN 0 - -#define R_SERIAL1_REC_CTRL__dma_err__BITNR 7 -#define R_SERIAL1_REC_CTRL__rec_enable__BITNR 6 -#define R_SERIAL1_REC_CTRL__rts___BITNR 5 -#define R_SERIAL1_REC_CTRL__sampling__BITNR 4 -#define R_SERIAL1_REC_CTRL__rec_stick_par__BITNR 3 -#define R_SERIAL1_REC_CTRL__rec_par__BITNR 2 -#define R_SERIAL1_REC_CTRL__rec_par_en__BITNR 1 -#define R_SERIAL1_REC_CTRL__rec_bitnr__BITNR 0 - -#define R_SERIAL1_REC_CTRL__dma_err__dma_err__VAL REG_VAL_ENUM -#define R_SERIAL1_REC_CTRL__rec_enable__rec_enable__VAL REG_VAL_ENUM -#define R_SERIAL1_REC_CTRL__rts___rts___VAL REG_VAL_ENUM -#define R_SERIAL1_REC_CTRL__sampling__sampling__VAL REG_VAL_ENUM -#define R_SERIAL1_REC_CTRL__rec_stick_par__rec_stick_par__VAL REG_VAL_ENUM -#define R_SERIAL1_REC_CTRL__rec_par__rec_par__VAL REG_VAL_ENUM -#define R_SERIAL1_REC_CTRL__rec_par_en__rec_par_en__VAL REG_VAL_ENUM -#define R_SERIAL1_REC_CTRL__rec_bitnr__rec_bitnr__VAL REG_VAL_ENUM - -#define R_SERIAL1_REC_CTRL__dma_err__dma_err__ignore 1 -#define R_SERIAL1_REC_CTRL__dma_err__dma_err__stop 0 -#define R_SERIAL1_REC_CTRL__rec_enable__rec_enable__disable 0 -#define R_SERIAL1_REC_CTRL__rec_enable__rec_enable__enable 1 -#define R_SERIAL1_REC_CTRL__rts___rts___active 0 -#define R_SERIAL1_REC_CTRL__rts___rts___inactive 1 -#define R_SERIAL1_REC_CTRL__sampling__sampling__majority 1 -#define R_SERIAL1_REC_CTRL__sampling__sampling__middle 0 -#define R_SERIAL1_REC_CTRL__rec_stick_par__rec_stick_par__normal 0 -#define R_SERIAL1_REC_CTRL__rec_stick_par__rec_stick_par__stick 1 -#define R_SERIAL1_REC_CTRL__rec_par__rec_par__even 0 -#define R_SERIAL1_REC_CTRL__rec_par__rec_par__odd 1 -#define R_SERIAL1_REC_CTRL__rec_par_en__rec_par_en__disable 0 -#define R_SERIAL1_REC_CTRL__rec_par_en__rec_par_en__enable 1 -#define R_SERIAL1_REC_CTRL__rec_bitnr__rec_bitnr__rec_7bit 1 -#define R_SERIAL1_REC_CTRL__rec_bitnr__rec_bitnr__rec_8bit 0 - -#endif - -/* - * R_SERIAL1_REC_DATA - * - type: RO - * - addr: 0xb0000068 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -#define R_SERIAL1_REC_DATA__ADDR (REG_TYPECAST_BYTE 0xb0000068) -#define R_SERIAL1_REC_DATA__SVAL REG_SVAL_SHADOW -#define R_SERIAL1_REC_DATA__SVAL_I REG_SVAL_I_SHADOW -#define R_SERIAL1_REC_DATA__TYPECAST REG_TYPECAST_BYTE -#define R_SERIAL1_REC_DATA__TYPE (REG_BYTE) -#define R_SERIAL1_REC_DATA__GET REG_GET_RO -#define R_SERIAL1_REC_DATA__IGET REG_IGET_RO -#define R_SERIAL1_REC_DATA__SET REG_SET_RO -#define R_SERIAL1_REC_DATA__ISET REG_ISET_RO -#define R_SERIAL1_REC_DATA__SET_VAL REG_SET_VAL_RO -#define R_SERIAL1_REC_DATA__EQL REG_EQL_RO -#define R_SERIAL1_REC_DATA__IEQL REG_IEQL_RO -#define R_SERIAL1_REC_DATA__RD REG_RD_RO -#define R_SERIAL1_REC_DATA__IRD REG_IRD_RO -#define R_SERIAL1_REC_DATA__WR REG_WR_RO -#define R_SERIAL1_REC_DATA__IWR REG_IWR_RO - -#define R_SERIAL1_REC_DATA__READ(addr) \ - (*(addr)) - -#define R_SERIAL1_REC_DATA__data_in__data_in__MASK 0x000000ffU - -#define R_SERIAL1_REC_DATA__data_in__MAX 0xff - -#define R_SERIAL1_REC_DATA__data_in__MIN 0 - -#define R_SERIAL1_REC_DATA__data_in__BITNR 0 - -#define R_SERIAL1_REC_DATA__data_in__data_in__VAL REG_VAL_VAL - - -#endif - -/* - * R_SERIAL1_STATUS - * - type: RO - * - addr: 0xb0000069 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -#define R_SERIAL1_STATUS__ADDR (REG_TYPECAST_BYTE 0xb0000069) -#define R_SERIAL1_STATUS__SVAL REG_SVAL_SHADOW -#define R_SERIAL1_STATUS__SVAL_I REG_SVAL_I_SHADOW -#define R_SERIAL1_STATUS__TYPECAST REG_TYPECAST_BYTE -#define R_SERIAL1_STATUS__TYPE (REG_BYTE) -#define R_SERIAL1_STATUS__GET REG_GET_RO -#define R_SERIAL1_STATUS__IGET REG_IGET_RO -#define R_SERIAL1_STATUS__SET REG_SET_RO -#define R_SERIAL1_STATUS__ISET REG_ISET_RO -#define R_SERIAL1_STATUS__SET_VAL REG_SET_VAL_RO -#define R_SERIAL1_STATUS__EQL REG_EQL_RO -#define R_SERIAL1_STATUS__IEQL REG_IEQL_RO -#define R_SERIAL1_STATUS__RD REG_RD_RO -#define R_SERIAL1_STATUS__IRD REG_IRD_RO -#define R_SERIAL1_STATUS__WR REG_WR_RO -#define R_SERIAL1_STATUS__IWR REG_IWR_RO - -#define R_SERIAL1_STATUS__READ(addr) \ - (*(addr)) - -#define R_SERIAL1_STATUS__xoff_detect__xoff_detect__MASK 0x00000080U -#define R_SERIAL1_STATUS__cts___cts___MASK 0x00000040U -#define R_SERIAL1_STATUS__tr_ready__tr_ready__MASK 0x00000020U -#define R_SERIAL1_STATUS__rxd__rxd__MASK 0x00000010U -#define R_SERIAL1_STATUS__overrun__overrun__MASK 0x00000008U -#define R_SERIAL1_STATUS__par_err__par_err__MASK 0x00000004U -#define R_SERIAL1_STATUS__framing_err__framing_err__MASK 0x00000002U -#define R_SERIAL1_STATUS__data_avail__data_avail__MASK 0x00000001U - -#define R_SERIAL1_STATUS__xoff_detect__MAX 0x1 -#define R_SERIAL1_STATUS__cts___MAX 0x1 -#define R_SERIAL1_STATUS__tr_ready__MAX 0x1 -#define R_SERIAL1_STATUS__rxd__MAX 0x1 -#define R_SERIAL1_STATUS__overrun__MAX 0x1 -#define R_SERIAL1_STATUS__par_err__MAX 0x1 -#define R_SERIAL1_STATUS__framing_err__MAX 0x1 -#define R_SERIAL1_STATUS__data_avail__MAX 0x1 - -#define R_SERIAL1_STATUS__xoff_detect__MIN 0 -#define R_SERIAL1_STATUS__cts___MIN 0 -#define R_SERIAL1_STATUS__tr_ready__MIN 0 -#define R_SERIAL1_STATUS__rxd__MIN 0 -#define R_SERIAL1_STATUS__overrun__MIN 0 -#define R_SERIAL1_STATUS__par_err__MIN 0 -#define R_SERIAL1_STATUS__framing_err__MIN 0 -#define R_SERIAL1_STATUS__data_avail__MIN 0 - -#define R_SERIAL1_STATUS__xoff_detect__BITNR 7 -#define R_SERIAL1_STATUS__cts___BITNR 6 -#define R_SERIAL1_STATUS__tr_ready__BITNR 5 -#define R_SERIAL1_STATUS__rxd__BITNR 4 -#define R_SERIAL1_STATUS__overrun__BITNR 3 -#define R_SERIAL1_STATUS__par_err__BITNR 2 -#define R_SERIAL1_STATUS__framing_err__BITNR 1 -#define R_SERIAL1_STATUS__data_avail__BITNR 0 - -#define R_SERIAL1_STATUS__xoff_detect__xoff_detect__VAL REG_VAL_ENUM -#define R_SERIAL1_STATUS__cts___cts___VAL REG_VAL_ENUM -#define R_SERIAL1_STATUS__tr_ready__tr_ready__VAL REG_VAL_ENUM -#define R_SERIAL1_STATUS__rxd__rxd__VAL REG_VAL_VAL -#define R_SERIAL1_STATUS__overrun__overrun__VAL REG_VAL_ENUM -#define R_SERIAL1_STATUS__par_err__par_err__VAL REG_VAL_ENUM -#define R_SERIAL1_STATUS__framing_err__framing_err__VAL REG_VAL_ENUM -#define R_SERIAL1_STATUS__data_avail__data_avail__VAL REG_VAL_ENUM - -#define R_SERIAL1_STATUS__xoff_detect__xoff_detect__no_xoff 0 -#define R_SERIAL1_STATUS__xoff_detect__xoff_detect__xoff 1 -#define R_SERIAL1_STATUS__cts___cts___active 0 -#define R_SERIAL1_STATUS__cts___cts___inactive 1 -#define R_SERIAL1_STATUS__tr_ready__tr_ready__full 0 -#define R_SERIAL1_STATUS__tr_ready__tr_ready__ready 1 -#define R_SERIAL1_STATUS__overrun__overrun__no 0 -#define R_SERIAL1_STATUS__overrun__overrun__yes 1 -#define R_SERIAL1_STATUS__par_err__par_err__no 0 -#define R_SERIAL1_STATUS__par_err__par_err__yes 1 -#define R_SERIAL1_STATUS__framing_err__framing_err__no 0 -#define R_SERIAL1_STATUS__framing_err__framing_err__yes 1 -#define R_SERIAL1_STATUS__data_avail__data_avail__no 0 -#define R_SERIAL1_STATUS__data_avail__data_avail__yes 1 - -#endif - -/* - * R_SERIAL1_TR_CTRL - * - type: WO - * - addr: 0xb0000069 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -#define R_SERIAL1_TR_CTRL__ADDR (REG_TYPECAST_BYTE 0xb0000069) - -#ifndef REG_NO_SHADOW -#define R_SERIAL1_TR_CTRL__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL1_CTRL + 1)) -#define R_SERIAL1_TR_CTRL__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL1_CTRL + 1)) -#else /* REG_NO_SHADOW */ -#define R_SERIAL1_TR_CTRL__SADDR (REG_STYPECAST_BYTE (®_shadow__hwregs)) -#define R_SERIAL1_TR_CTRL__IADDR (REG_STYPECAST_BYTE (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_SERIAL1_TR_CTRL__STYPECAST REG_STYPECAST_BYTE -#define R_SERIAL1_TR_CTRL__SVAL REG_SVAL_SHADOW -#define R_SERIAL1_TR_CTRL__SVAL_I REG_SVAL_I_SHADOW -#define R_SERIAL1_TR_CTRL__TYPECAST REG_TYPECAST_BYTE -#define R_SERIAL1_TR_CTRL__TYPE (REG_BYTE) -#define R_SERIAL1_TR_CTRL__GET REG_GET_WO -#define R_SERIAL1_TR_CTRL__IGET REG_IGET_WO -#define R_SERIAL1_TR_CTRL__SET REG_SET_WO -#define R_SERIAL1_TR_CTRL__ISET REG_ISET_WO -#define R_SERIAL1_TR_CTRL__SET_VAL REG_SET_VAL_WO -#define R_SERIAL1_TR_CTRL__EQL REG_EQL_WO -#define R_SERIAL1_TR_CTRL__IEQL REG_IEQL_WO -#define R_SERIAL1_TR_CTRL__RD REG_RD_WO -#define R_SERIAL1_TR_CTRL__IRD REG_IRD_WO -#define R_SERIAL1_TR_CTRL__WR REG_WR_WO -#define R_SERIAL1_TR_CTRL__IWR REG_IWR_WO - -#define R_SERIAL1_TR_CTRL__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_SERIAL1_TR_CTRL__txd__txd__MASK 0x00000080U -#define R_SERIAL1_TR_CTRL__tr_enable__tr_enable__MASK 0x00000040U -#define R_SERIAL1_TR_CTRL__auto_cts__auto_cts__MASK 0x00000020U -#define R_SERIAL1_TR_CTRL__stop_bits__stop_bits__MASK 0x00000010U -#define R_SERIAL1_TR_CTRL__tr_stick_par__tr_stick_par__MASK 0x00000008U -#define R_SERIAL1_TR_CTRL__tr_par__tr_par__MASK 0x00000004U -#define R_SERIAL1_TR_CTRL__tr_par_en__tr_par_en__MASK 0x00000002U -#define R_SERIAL1_TR_CTRL__tr_bitnr__tr_bitnr__MASK 0x00000001U - -#define R_SERIAL1_TR_CTRL__txd__MAX 0x1 -#define R_SERIAL1_TR_CTRL__tr_enable__MAX 0x1 -#define R_SERIAL1_TR_CTRL__auto_cts__MAX 0x1 -#define R_SERIAL1_TR_CTRL__stop_bits__MAX 0x1 -#define R_SERIAL1_TR_CTRL__tr_stick_par__MAX 0x1 -#define R_SERIAL1_TR_CTRL__tr_par__MAX 0x1 -#define R_SERIAL1_TR_CTRL__tr_par_en__MAX 0x1 -#define R_SERIAL1_TR_CTRL__tr_bitnr__MAX 0x1 - -#define R_SERIAL1_TR_CTRL__txd__MIN 0 -#define R_SERIAL1_TR_CTRL__tr_enable__MIN 0 -#define R_SERIAL1_TR_CTRL__auto_cts__MIN 0 -#define R_SERIAL1_TR_CTRL__stop_bits__MIN 0 -#define R_SERIAL1_TR_CTRL__tr_stick_par__MIN 0 -#define R_SERIAL1_TR_CTRL__tr_par__MIN 0 -#define R_SERIAL1_TR_CTRL__tr_par_en__MIN 0 -#define R_SERIAL1_TR_CTRL__tr_bitnr__MIN 0 - -#define R_SERIAL1_TR_CTRL__txd__BITNR 7 -#define R_SERIAL1_TR_CTRL__tr_enable__BITNR 6 -#define R_SERIAL1_TR_CTRL__auto_cts__BITNR 5 -#define R_SERIAL1_TR_CTRL__stop_bits__BITNR 4 -#define R_SERIAL1_TR_CTRL__tr_stick_par__BITNR 3 -#define R_SERIAL1_TR_CTRL__tr_par__BITNR 2 -#define R_SERIAL1_TR_CTRL__tr_par_en__BITNR 1 -#define R_SERIAL1_TR_CTRL__tr_bitnr__BITNR 0 - -#define R_SERIAL1_TR_CTRL__txd__txd__VAL REG_VAL_VAL -#define R_SERIAL1_TR_CTRL__tr_enable__tr_enable__VAL REG_VAL_ENUM -#define R_SERIAL1_TR_CTRL__auto_cts__auto_cts__VAL REG_VAL_ENUM -#define R_SERIAL1_TR_CTRL__stop_bits__stop_bits__VAL REG_VAL_ENUM -#define R_SERIAL1_TR_CTRL__tr_stick_par__tr_stick_par__VAL REG_VAL_ENUM -#define R_SERIAL1_TR_CTRL__tr_par__tr_par__VAL REG_VAL_ENUM -#define R_SERIAL1_TR_CTRL__tr_par_en__tr_par_en__VAL REG_VAL_ENUM -#define R_SERIAL1_TR_CTRL__tr_bitnr__tr_bitnr__VAL REG_VAL_ENUM - -#define R_SERIAL1_TR_CTRL__tr_enable__tr_enable__disable 0 -#define R_SERIAL1_TR_CTRL__tr_enable__tr_enable__enable 1 -#define R_SERIAL1_TR_CTRL__auto_cts__auto_cts__active 1 -#define R_SERIAL1_TR_CTRL__auto_cts__auto_cts__disabled 0 -#define R_SERIAL1_TR_CTRL__stop_bits__stop_bits__one_bit 0 -#define R_SERIAL1_TR_CTRL__stop_bits__stop_bits__two_bits 1 -#define R_SERIAL1_TR_CTRL__tr_stick_par__tr_stick_par__normal 0 -#define R_SERIAL1_TR_CTRL__tr_stick_par__tr_stick_par__stick 1 -#define R_SERIAL1_TR_CTRL__tr_par__tr_par__even 0 -#define R_SERIAL1_TR_CTRL__tr_par__tr_par__odd 1 -#define R_SERIAL1_TR_CTRL__tr_par_en__tr_par_en__disable 0 -#define R_SERIAL1_TR_CTRL__tr_par_en__tr_par_en__enable 1 -#define R_SERIAL1_TR_CTRL__tr_bitnr__tr_bitnr__tr_7bit 1 -#define R_SERIAL1_TR_CTRL__tr_bitnr__tr_bitnr__tr_8bit 0 - -#endif - -/* - * R_SERIAL1_TR_DATA - * - type: WO - * - addr: 0xb0000068 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -#define R_SERIAL1_TR_DATA__ADDR (REG_TYPECAST_BYTE 0xb0000068) - -#ifndef REG_NO_SHADOW -#define R_SERIAL1_TR_DATA__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL1_CTRL + 0)) -#define R_SERIAL1_TR_DATA__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL1_CTRL + 0)) -#else /* REG_NO_SHADOW */ -#define R_SERIAL1_TR_DATA__SADDR (REG_STYPECAST_BYTE (®_shadow__hwregs)) -#define R_SERIAL1_TR_DATA__IADDR (REG_STYPECAST_BYTE (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_SERIAL1_TR_DATA__STYPECAST REG_STYPECAST_BYTE -#define R_SERIAL1_TR_DATA__SVAL REG_SVAL_SHADOW -#define R_SERIAL1_TR_DATA__SVAL_I REG_SVAL_I_SHADOW -#define R_SERIAL1_TR_DATA__TYPECAST REG_TYPECAST_BYTE -#define R_SERIAL1_TR_DATA__TYPE (REG_BYTE) -#define R_SERIAL1_TR_DATA__GET REG_GET_WO -#define R_SERIAL1_TR_DATA__IGET REG_IGET_WO -#define R_SERIAL1_TR_DATA__SET REG_SET_WO -#define R_SERIAL1_TR_DATA__ISET REG_ISET_WO -#define R_SERIAL1_TR_DATA__SET_VAL REG_SET_VAL_WO -#define R_SERIAL1_TR_DATA__EQL REG_EQL_WO -#define R_SERIAL1_TR_DATA__IEQL REG_IEQL_WO -#define R_SERIAL1_TR_DATA__RD REG_RD_WO -#define R_SERIAL1_TR_DATA__IRD REG_IRD_WO -#define R_SERIAL1_TR_DATA__WR REG_WR_WO -#define R_SERIAL1_TR_DATA__IWR REG_IWR_WO - -#define R_SERIAL1_TR_DATA__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_SERIAL1_TR_DATA__data_out__data_out__MASK 0x000000ffU - -#define R_SERIAL1_TR_DATA__data_out__MAX 0xff - -#define R_SERIAL1_TR_DATA__data_out__MIN 0 - -#define R_SERIAL1_TR_DATA__data_out__BITNR 0 - -#define R_SERIAL1_TR_DATA__data_out__data_out__VAL REG_VAL_VAL - - -#endif - -/* - * R_SERIAL1_XOFF - * - type: WO - * - addr: 0xb000006c - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -#define R_SERIAL1_XOFF__ADDR (REG_TYPECAST_UDWORD 0xb000006c) - -#ifndef REG_NO_SHADOW -#define R_SERIAL1_XOFF__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_SERIAL1_XOFF + 0)) -#define R_SERIAL1_XOFF__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_SERIAL1_XOFF + 0)) -#else /* REG_NO_SHADOW */ -#define R_SERIAL1_XOFF__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_SERIAL1_XOFF__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_SERIAL1_XOFF__STYPECAST REG_STYPECAST_UDWORD -#define R_SERIAL1_XOFF__SVAL REG_SVAL_SHADOW -#define R_SERIAL1_XOFF__SVAL_I REG_SVAL_I_SHADOW -#define R_SERIAL1_XOFF__TYPECAST REG_TYPECAST_UDWORD -#define R_SERIAL1_XOFF__TYPE (REG_UDWORD) -#define R_SERIAL1_XOFF__GET REG_GET_WO -#define R_SERIAL1_XOFF__IGET REG_IGET_WO -#define R_SERIAL1_XOFF__SET REG_SET_WO -#define R_SERIAL1_XOFF__ISET REG_ISET_WO -#define R_SERIAL1_XOFF__SET_VAL REG_SET_VAL_WO -#define R_SERIAL1_XOFF__EQL REG_EQL_WO -#define R_SERIAL1_XOFF__IEQL REG_IEQL_WO -#define R_SERIAL1_XOFF__RD REG_RD_WO -#define R_SERIAL1_XOFF__IRD REG_IRD_WO -#define R_SERIAL1_XOFF__WR REG_WR_WO -#define R_SERIAL1_XOFF__IWR REG_IWR_WO - -#define R_SERIAL1_XOFF__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_SERIAL1_XOFF__tx_stop__tx_stop__MASK 0x00000200U -#define R_SERIAL1_XOFF__auto_xoff__auto_xoff__MASK 0x00000100U -#define R_SERIAL1_XOFF__xoff_char__xoff_char__MASK 0x000000ffU - -#define R_SERIAL1_XOFF__tx_stop__MAX 0x1 -#define R_SERIAL1_XOFF__auto_xoff__MAX 0x1 -#define R_SERIAL1_XOFF__xoff_char__MAX 0xff - -#define R_SERIAL1_XOFF__tx_stop__MIN 0 -#define R_SERIAL1_XOFF__auto_xoff__MIN 0 -#define R_SERIAL1_XOFF__xoff_char__MIN 0 - -#define R_SERIAL1_XOFF__tx_stop__BITNR 9 -#define R_SERIAL1_XOFF__auto_xoff__BITNR 8 -#define R_SERIAL1_XOFF__xoff_char__BITNR 0 - -#define R_SERIAL1_XOFF__tx_stop__tx_stop__VAL REG_VAL_ENUM -#define R_SERIAL1_XOFF__auto_xoff__auto_xoff__VAL REG_VAL_ENUM -#define R_SERIAL1_XOFF__xoff_char__xoff_char__VAL REG_VAL_VAL - -#define R_SERIAL1_XOFF__tx_stop__tx_stop__enable 0 -#define R_SERIAL1_XOFF__tx_stop__tx_stop__stop 1 -#define R_SERIAL1_XOFF__auto_xoff__auto_xoff__disable 0 -#define R_SERIAL1_XOFF__auto_xoff__auto_xoff__enable 1 - -#endif - -/* - * R_SERIAL2_BAUD - * - type: WO - * - addr: 0xb0000073 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -#define R_SERIAL2_BAUD__ADDR (REG_TYPECAST_BYTE 0xb0000073) - -#ifndef REG_NO_SHADOW -#define R_SERIAL2_BAUD__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL2_CTRL + 3)) -#define R_SERIAL2_BAUD__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL2_CTRL + 3)) -#else /* REG_NO_SHADOW */ -#define R_SERIAL2_BAUD__SADDR (REG_STYPECAST_BYTE (®_shadow__hwregs)) -#define R_SERIAL2_BAUD__IADDR (REG_STYPECAST_BYTE (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_SERIAL2_BAUD__STYPECAST REG_STYPECAST_BYTE -#define R_SERIAL2_BAUD__SVAL REG_SVAL_SHADOW -#define R_SERIAL2_BAUD__SVAL_I REG_SVAL_I_SHADOW -#define R_SERIAL2_BAUD__TYPECAST REG_TYPECAST_BYTE -#define R_SERIAL2_BAUD__TYPE (REG_BYTE) -#define R_SERIAL2_BAUD__GET REG_GET_WO -#define R_SERIAL2_BAUD__IGET REG_IGET_WO -#define R_SERIAL2_BAUD__SET REG_SET_WO -#define R_SERIAL2_BAUD__ISET REG_ISET_WO -#define R_SERIAL2_BAUD__SET_VAL REG_SET_VAL_WO -#define R_SERIAL2_BAUD__EQL REG_EQL_WO -#define R_SERIAL2_BAUD__IEQL REG_IEQL_WO -#define R_SERIAL2_BAUD__RD REG_RD_WO -#define R_SERIAL2_BAUD__IRD REG_IRD_WO -#define R_SERIAL2_BAUD__WR REG_WR_WO -#define R_SERIAL2_BAUD__IWR REG_IWR_WO - -#define R_SERIAL2_BAUD__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_SERIAL2_BAUD__tr_baud__tr_baud__MASK 0x000000f0U -#define R_SERIAL2_BAUD__rec_baud__rec_baud__MASK 0x0000000fU - -#define R_SERIAL2_BAUD__tr_baud__MAX 0xf -#define R_SERIAL2_BAUD__rec_baud__MAX 0xf - -#define R_SERIAL2_BAUD__tr_baud__MIN 0 -#define R_SERIAL2_BAUD__rec_baud__MIN 0 - -#define R_SERIAL2_BAUD__tr_baud__BITNR 4 -#define R_SERIAL2_BAUD__rec_baud__BITNR 0 - -#define R_SERIAL2_BAUD__tr_baud__tr_baud__VAL REG_VAL_ENUM -#define R_SERIAL2_BAUD__rec_baud__rec_baud__VAL REG_VAL_ENUM - -#define R_SERIAL2_BAUD__tr_baud__tr_baud__c115k2Hz 9 -#define R_SERIAL2_BAUD__tr_baud__tr_baud__c1200Hz 2 -#define R_SERIAL2_BAUD__tr_baud__tr_baud__c1843k2Hz 13 -#define R_SERIAL2_BAUD__tr_baud__tr_baud__c19k2Hz 6 -#define R_SERIAL2_BAUD__tr_baud__tr_baud__c230k4Hz 10 -#define R_SERIAL2_BAUD__tr_baud__tr_baud__c2400Hz 3 -#define R_SERIAL2_BAUD__tr_baud__tr_baud__c300Hz 0 -#define R_SERIAL2_BAUD__tr_baud__tr_baud__c38k4Hz 7 -#define R_SERIAL2_BAUD__tr_baud__tr_baud__c460k8Hz 11 -#define R_SERIAL2_BAUD__tr_baud__tr_baud__c4800Hz 4 -#define R_SERIAL2_BAUD__tr_baud__tr_baud__c57k6Hz 8 -#define R_SERIAL2_BAUD__tr_baud__tr_baud__c600Hz 1 -#define R_SERIAL2_BAUD__tr_baud__tr_baud__c6250kHz 14 -#define R_SERIAL2_BAUD__tr_baud__tr_baud__c921k6Hz 12 -#define R_SERIAL2_BAUD__tr_baud__tr_baud__c9600Hz 5 -#define R_SERIAL2_BAUD__rec_baud__rec_baud__c115k2Hz 9 -#define R_SERIAL2_BAUD__rec_baud__rec_baud__c1200Hz 2 -#define R_SERIAL2_BAUD__rec_baud__rec_baud__c1843k2Hz 13 -#define R_SERIAL2_BAUD__rec_baud__rec_baud__c19k2Hz 6 -#define R_SERIAL2_BAUD__rec_baud__rec_baud__c230k4Hz 10 -#define R_SERIAL2_BAUD__rec_baud__rec_baud__c2400Hz 3 -#define R_SERIAL2_BAUD__rec_baud__rec_baud__c300Hz 0 -#define R_SERIAL2_BAUD__rec_baud__rec_baud__c38k4Hz 7 -#define R_SERIAL2_BAUD__rec_baud__rec_baud__c460k8Hz 11 -#define R_SERIAL2_BAUD__rec_baud__rec_baud__c4800Hz 4 -#define R_SERIAL2_BAUD__rec_baud__rec_baud__c57k6Hz 8 -#define R_SERIAL2_BAUD__rec_baud__rec_baud__c600Hz 1 -#define R_SERIAL2_BAUD__rec_baud__rec_baud__c6250kHz 14 -#define R_SERIAL2_BAUD__rec_baud__rec_baud__c921k6Hz 12 -#define R_SERIAL2_BAUD__rec_baud__rec_baud__c9600Hz 5 - -#endif - -/* - * R_SERIAL2_CTRL - * - type: WO - * - addr: 0xb0000070 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -#define R_SERIAL2_CTRL__ADDR (REG_TYPECAST_UDWORD 0xb0000070) - -#ifndef REG_NO_SHADOW -#define R_SERIAL2_CTRL__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_SERIAL2_CTRL + 0)) -#define R_SERIAL2_CTRL__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_SERIAL2_CTRL + 0)) -#else /* REG_NO_SHADOW */ -#define R_SERIAL2_CTRL__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_SERIAL2_CTRL__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_SERIAL2_CTRL__STYPECAST REG_STYPECAST_UDWORD -#define R_SERIAL2_CTRL__SVAL REG_SVAL_SHADOW -#define R_SERIAL2_CTRL__SVAL_I REG_SVAL_I_SHADOW -#define R_SERIAL2_CTRL__TYPECAST REG_TYPECAST_UDWORD -#define R_SERIAL2_CTRL__TYPE (REG_UDWORD) -#define R_SERIAL2_CTRL__GET REG_GET_WO -#define R_SERIAL2_CTRL__IGET REG_IGET_WO -#define R_SERIAL2_CTRL__SET REG_SET_WO -#define R_SERIAL2_CTRL__ISET REG_ISET_WO -#define R_SERIAL2_CTRL__SET_VAL REG_SET_VAL_WO -#define R_SERIAL2_CTRL__EQL REG_EQL_WO -#define R_SERIAL2_CTRL__IEQL REG_IEQL_WO -#define R_SERIAL2_CTRL__RD REG_RD_WO -#define R_SERIAL2_CTRL__IRD REG_IRD_WO -#define R_SERIAL2_CTRL__WR REG_WR_WO -#define R_SERIAL2_CTRL__IWR REG_IWR_WO - -#define R_SERIAL2_CTRL__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_SERIAL2_CTRL__tr_baud__tr_baud__MASK 0xf0000000U -#define R_SERIAL2_CTRL__rec_baud__rec_baud__MASK 0x0f000000U -#define R_SERIAL2_CTRL__dma_err__dma_err__MASK 0x00800000U -#define R_SERIAL2_CTRL__rec_enable__rec_enable__MASK 0x00400000U -#define R_SERIAL2_CTRL__rts___rts___MASK 0x00200000U -#define R_SERIAL2_CTRL__sampling__sampling__MASK 0x00100000U -#define R_SERIAL2_CTRL__rec_stick_par__rec_stick_par__MASK 0x00080000U -#define R_SERIAL2_CTRL__rec_par__rec_par__MASK 0x00040000U -#define R_SERIAL2_CTRL__rec_par_en__rec_par_en__MASK 0x00020000U -#define R_SERIAL2_CTRL__rec_bitnr__rec_bitnr__MASK 0x00010000U -#define R_SERIAL2_CTRL__txd__txd__MASK 0x00008000U -#define R_SERIAL2_CTRL__tr_enable__tr_enable__MASK 0x00004000U -#define R_SERIAL2_CTRL__auto_cts__auto_cts__MASK 0x00002000U -#define R_SERIAL2_CTRL__stop_bits__stop_bits__MASK 0x00001000U -#define R_SERIAL2_CTRL__tr_stick_par__tr_stick_par__MASK 0x00000800U -#define R_SERIAL2_CTRL__tr_par__tr_par__MASK 0x00000400U -#define R_SERIAL2_CTRL__tr_par_en__tr_par_en__MASK 0x00000200U -#define R_SERIAL2_CTRL__tr_bitnr__tr_bitnr__MASK 0x00000100U -#define R_SERIAL2_CTRL__data_out__data_out__MASK 0x000000ffU - -#define R_SERIAL2_CTRL__tr_baud__MAX 0xf -#define R_SERIAL2_CTRL__rec_baud__MAX 0xf -#define R_SERIAL2_CTRL__dma_err__MAX 0x1 -#define R_SERIAL2_CTRL__rec_enable__MAX 0x1 -#define R_SERIAL2_CTRL__rts___MAX 0x1 -#define R_SERIAL2_CTRL__sampling__MAX 0x1 -#define R_SERIAL2_CTRL__rec_stick_par__MAX 0x1 -#define R_SERIAL2_CTRL__rec_par__MAX 0x1 -#define R_SERIAL2_CTRL__rec_par_en__MAX 0x1 -#define R_SERIAL2_CTRL__rec_bitnr__MAX 0x1 -#define R_SERIAL2_CTRL__txd__MAX 0x1 -#define R_SERIAL2_CTRL__tr_enable__MAX 0x1 -#define R_SERIAL2_CTRL__auto_cts__MAX 0x1 -#define R_SERIAL2_CTRL__stop_bits__MAX 0x1 -#define R_SERIAL2_CTRL__tr_stick_par__MAX 0x1 -#define R_SERIAL2_CTRL__tr_par__MAX 0x1 -#define R_SERIAL2_CTRL__tr_par_en__MAX 0x1 -#define R_SERIAL2_CTRL__tr_bitnr__MAX 0x1 -#define R_SERIAL2_CTRL__data_out__MAX 0xff - -#define R_SERIAL2_CTRL__tr_baud__MIN 0 -#define R_SERIAL2_CTRL__rec_baud__MIN 0 -#define R_SERIAL2_CTRL__dma_err__MIN 0 -#define R_SERIAL2_CTRL__rec_enable__MIN 0 -#define R_SERIAL2_CTRL__rts___MIN 0 -#define R_SERIAL2_CTRL__sampling__MIN 0 -#define R_SERIAL2_CTRL__rec_stick_par__MIN 0 -#define R_SERIAL2_CTRL__rec_par__MIN 0 -#define R_SERIAL2_CTRL__rec_par_en__MIN 0 -#define R_SERIAL2_CTRL__rec_bitnr__MIN 0 -#define R_SERIAL2_CTRL__txd__MIN 0 -#define R_SERIAL2_CTRL__tr_enable__MIN 0 -#define R_SERIAL2_CTRL__auto_cts__MIN 0 -#define R_SERIAL2_CTRL__stop_bits__MIN 0 -#define R_SERIAL2_CTRL__tr_stick_par__MIN 0 -#define R_SERIAL2_CTRL__tr_par__MIN 0 -#define R_SERIAL2_CTRL__tr_par_en__MIN 0 -#define R_SERIAL2_CTRL__tr_bitnr__MIN 0 -#define R_SERIAL2_CTRL__data_out__MIN 0 - -#define R_SERIAL2_CTRL__tr_baud__BITNR 28 -#define R_SERIAL2_CTRL__rec_baud__BITNR 24 -#define R_SERIAL2_CTRL__dma_err__BITNR 23 -#define R_SERIAL2_CTRL__rec_enable__BITNR 22 -#define R_SERIAL2_CTRL__rts___BITNR 21 -#define R_SERIAL2_CTRL__sampling__BITNR 20 -#define R_SERIAL2_CTRL__rec_stick_par__BITNR 19 -#define R_SERIAL2_CTRL__rec_par__BITNR 18 -#define R_SERIAL2_CTRL__rec_par_en__BITNR 17 -#define R_SERIAL2_CTRL__rec_bitnr__BITNR 16 -#define R_SERIAL2_CTRL__txd__BITNR 15 -#define R_SERIAL2_CTRL__tr_enable__BITNR 14 -#define R_SERIAL2_CTRL__auto_cts__BITNR 13 -#define R_SERIAL2_CTRL__stop_bits__BITNR 12 -#define R_SERIAL2_CTRL__tr_stick_par__BITNR 11 -#define R_SERIAL2_CTRL__tr_par__BITNR 10 -#define R_SERIAL2_CTRL__tr_par_en__BITNR 9 -#define R_SERIAL2_CTRL__tr_bitnr__BITNR 8 -#define R_SERIAL2_CTRL__data_out__BITNR 0 - -#define R_SERIAL2_CTRL__tr_baud__tr_baud__VAL REG_VAL_ENUM -#define R_SERIAL2_CTRL__rec_baud__rec_baud__VAL REG_VAL_ENUM -#define R_SERIAL2_CTRL__dma_err__dma_err__VAL REG_VAL_ENUM -#define R_SERIAL2_CTRL__rec_enable__rec_enable__VAL REG_VAL_ENUM -#define R_SERIAL2_CTRL__rts___rts___VAL REG_VAL_ENUM -#define R_SERIAL2_CTRL__sampling__sampling__VAL REG_VAL_ENUM -#define R_SERIAL2_CTRL__rec_stick_par__rec_stick_par__VAL REG_VAL_ENUM -#define R_SERIAL2_CTRL__rec_par__rec_par__VAL REG_VAL_ENUM -#define R_SERIAL2_CTRL__rec_par_en__rec_par_en__VAL REG_VAL_ENUM -#define R_SERIAL2_CTRL__rec_bitnr__rec_bitnr__VAL REG_VAL_ENUM -#define R_SERIAL2_CTRL__txd__txd__VAL REG_VAL_VAL -#define R_SERIAL2_CTRL__tr_enable__tr_enable__VAL REG_VAL_ENUM -#define R_SERIAL2_CTRL__auto_cts__auto_cts__VAL REG_VAL_ENUM -#define R_SERIAL2_CTRL__stop_bits__stop_bits__VAL REG_VAL_ENUM -#define R_SERIAL2_CTRL__tr_stick_par__tr_stick_par__VAL REG_VAL_ENUM -#define R_SERIAL2_CTRL__tr_par__tr_par__VAL REG_VAL_ENUM -#define R_SERIAL2_CTRL__tr_par_en__tr_par_en__VAL REG_VAL_ENUM -#define R_SERIAL2_CTRL__tr_bitnr__tr_bitnr__VAL REG_VAL_ENUM -#define R_SERIAL2_CTRL__data_out__data_out__VAL REG_VAL_VAL - -#define R_SERIAL2_CTRL__tr_baud__tr_baud__c115k2Hz 9 -#define R_SERIAL2_CTRL__tr_baud__tr_baud__c1200Hz 2 -#define R_SERIAL2_CTRL__tr_baud__tr_baud__c1843k2Hz 13 -#define R_SERIAL2_CTRL__tr_baud__tr_baud__c19k2Hz 6 -#define R_SERIAL2_CTRL__tr_baud__tr_baud__c230k4Hz 10 -#define R_SERIAL2_CTRL__tr_baud__tr_baud__c2400Hz 3 -#define R_SERIAL2_CTRL__tr_baud__tr_baud__c300Hz 0 -#define R_SERIAL2_CTRL__tr_baud__tr_baud__c38k4Hz 7 -#define R_SERIAL2_CTRL__tr_baud__tr_baud__c460k8Hz 11 -#define R_SERIAL2_CTRL__tr_baud__tr_baud__c4800Hz 4 -#define R_SERIAL2_CTRL__tr_baud__tr_baud__c57k6Hz 8 -#define R_SERIAL2_CTRL__tr_baud__tr_baud__c600Hz 1 -#define R_SERIAL2_CTRL__tr_baud__tr_baud__c6250kHz 14 -#define R_SERIAL2_CTRL__tr_baud__tr_baud__c921k6Hz 12 -#define R_SERIAL2_CTRL__tr_baud__tr_baud__c9600Hz 5 -#define R_SERIAL2_CTRL__rec_baud__rec_baud__c115k2Hz 9 -#define R_SERIAL2_CTRL__rec_baud__rec_baud__c1200Hz 2 -#define R_SERIAL2_CTRL__rec_baud__rec_baud__c1843k2Hz 13 -#define R_SERIAL2_CTRL__rec_baud__rec_baud__c19k2Hz 6 -#define R_SERIAL2_CTRL__rec_baud__rec_baud__c230k4Hz 10 -#define R_SERIAL2_CTRL__rec_baud__rec_baud__c2400Hz 3 -#define R_SERIAL2_CTRL__rec_baud__rec_baud__c300Hz 0 -#define R_SERIAL2_CTRL__rec_baud__rec_baud__c38k4Hz 7 -#define R_SERIAL2_CTRL__rec_baud__rec_baud__c460k8Hz 11 -#define R_SERIAL2_CTRL__rec_baud__rec_baud__c4800Hz 4 -#define R_SERIAL2_CTRL__rec_baud__rec_baud__c57k6Hz 8 -#define R_SERIAL2_CTRL__rec_baud__rec_baud__c600Hz 1 -#define R_SERIAL2_CTRL__rec_baud__rec_baud__c6250kHz 14 -#define R_SERIAL2_CTRL__rec_baud__rec_baud__c921k6Hz 12 -#define R_SERIAL2_CTRL__rec_baud__rec_baud__c9600Hz 5 -#define R_SERIAL2_CTRL__dma_err__dma_err__ignore 1 -#define R_SERIAL2_CTRL__dma_err__dma_err__stop 0 -#define R_SERIAL2_CTRL__rec_enable__rec_enable__disable 0 -#define R_SERIAL2_CTRL__rec_enable__rec_enable__enable 1 -#define R_SERIAL2_CTRL__rts___rts___active 0 -#define R_SERIAL2_CTRL__rts___rts___inactive 1 -#define R_SERIAL2_CTRL__sampling__sampling__majority 1 -#define R_SERIAL2_CTRL__sampling__sampling__middle 0 -#define R_SERIAL2_CTRL__rec_stick_par__rec_stick_par__normal 0 -#define R_SERIAL2_CTRL__rec_stick_par__rec_stick_par__stick 1 -#define R_SERIAL2_CTRL__rec_par__rec_par__even 0 -#define R_SERIAL2_CTRL__rec_par__rec_par__odd 1 -#define R_SERIAL2_CTRL__rec_par_en__rec_par_en__disable 0 -#define R_SERIAL2_CTRL__rec_par_en__rec_par_en__enable 1 -#define R_SERIAL2_CTRL__rec_bitnr__rec_bitnr__rec_7bit 1 -#define R_SERIAL2_CTRL__rec_bitnr__rec_bitnr__rec_8bit 0 -#define R_SERIAL2_CTRL__tr_enable__tr_enable__disable 0 -#define R_SERIAL2_CTRL__tr_enable__tr_enable__enable 1 -#define R_SERIAL2_CTRL__auto_cts__auto_cts__active 1 -#define R_SERIAL2_CTRL__auto_cts__auto_cts__disabled 0 -#define R_SERIAL2_CTRL__stop_bits__stop_bits__one_bit 0 -#define R_SERIAL2_CTRL__stop_bits__stop_bits__two_bits 1 -#define R_SERIAL2_CTRL__tr_stick_par__tr_stick_par__normal 0 -#define R_SERIAL2_CTRL__tr_stick_par__tr_stick_par__stick 1 -#define R_SERIAL2_CTRL__tr_par__tr_par__even 0 -#define R_SERIAL2_CTRL__tr_par__tr_par__odd 1 -#define R_SERIAL2_CTRL__tr_par_en__tr_par_en__disable 0 -#define R_SERIAL2_CTRL__tr_par_en__tr_par_en__enable 1 -#define R_SERIAL2_CTRL__tr_bitnr__tr_bitnr__tr_7bit 1 -#define R_SERIAL2_CTRL__tr_bitnr__tr_bitnr__tr_8bit 0 - -#endif - -/* - * R_SERIAL2_READ - * - type: RO - * - addr: 0xb0000070 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -#define R_SERIAL2_READ__ADDR (REG_TYPECAST_UDWORD 0xb0000070) -#define R_SERIAL2_READ__SVAL REG_SVAL_SHADOW -#define R_SERIAL2_READ__SVAL_I REG_SVAL_I_SHADOW -#define R_SERIAL2_READ__TYPECAST REG_TYPECAST_UDWORD -#define R_SERIAL2_READ__TYPE (REG_UDWORD) -#define R_SERIAL2_READ__GET REG_GET_RO -#define R_SERIAL2_READ__IGET REG_IGET_RO -#define R_SERIAL2_READ__SET REG_SET_RO -#define R_SERIAL2_READ__ISET REG_ISET_RO -#define R_SERIAL2_READ__SET_VAL REG_SET_VAL_RO -#define R_SERIAL2_READ__EQL REG_EQL_RO -#define R_SERIAL2_READ__IEQL REG_IEQL_RO -#define R_SERIAL2_READ__RD REG_RD_RO -#define R_SERIAL2_READ__IRD REG_IRD_RO -#define R_SERIAL2_READ__WR REG_WR_RO -#define R_SERIAL2_READ__IWR REG_IWR_RO - -#define R_SERIAL2_READ__READ(addr) \ - (*(addr)) - -#define R_SERIAL2_READ__xoff_detect__xoff_detect__MASK 0x00008000U -#define R_SERIAL2_READ__cts___cts___MASK 0x00004000U -#define R_SERIAL2_READ__tr_ready__tr_ready__MASK 0x00002000U -#define R_SERIAL2_READ__rxd__rxd__MASK 0x00001000U -#define R_SERIAL2_READ__overrun__overrun__MASK 0x00000800U -#define R_SERIAL2_READ__par_err__par_err__MASK 0x00000400U -#define R_SERIAL2_READ__framing_err__framing_err__MASK 0x00000200U -#define R_SERIAL2_READ__data_avail__data_avail__MASK 0x00000100U -#define R_SERIAL2_READ__data_in__data_in__MASK 0x000000ffU - -#define R_SERIAL2_READ__xoff_detect__MAX 0x1 -#define R_SERIAL2_READ__cts___MAX 0x1 -#define R_SERIAL2_READ__tr_ready__MAX 0x1 -#define R_SERIAL2_READ__rxd__MAX 0x1 -#define R_SERIAL2_READ__overrun__MAX 0x1 -#define R_SERIAL2_READ__par_err__MAX 0x1 -#define R_SERIAL2_READ__framing_err__MAX 0x1 -#define R_SERIAL2_READ__data_avail__MAX 0x1 -#define R_SERIAL2_READ__data_in__MAX 0xff - -#define R_SERIAL2_READ__xoff_detect__MIN 0 -#define R_SERIAL2_READ__cts___MIN 0 -#define R_SERIAL2_READ__tr_ready__MIN 0 -#define R_SERIAL2_READ__rxd__MIN 0 -#define R_SERIAL2_READ__overrun__MIN 0 -#define R_SERIAL2_READ__par_err__MIN 0 -#define R_SERIAL2_READ__framing_err__MIN 0 -#define R_SERIAL2_READ__data_avail__MIN 0 -#define R_SERIAL2_READ__data_in__MIN 0 - -#define R_SERIAL2_READ__xoff_detect__BITNR 15 -#define R_SERIAL2_READ__cts___BITNR 14 -#define R_SERIAL2_READ__tr_ready__BITNR 13 -#define R_SERIAL2_READ__rxd__BITNR 12 -#define R_SERIAL2_READ__overrun__BITNR 11 -#define R_SERIAL2_READ__par_err__BITNR 10 -#define R_SERIAL2_READ__framing_err__BITNR 9 -#define R_SERIAL2_READ__data_avail__BITNR 8 -#define R_SERIAL2_READ__data_in__BITNR 0 - -#define R_SERIAL2_READ__xoff_detect__xoff_detect__VAL REG_VAL_ENUM -#define R_SERIAL2_READ__cts___cts___VAL REG_VAL_ENUM -#define R_SERIAL2_READ__tr_ready__tr_ready__VAL REG_VAL_ENUM -#define R_SERIAL2_READ__rxd__rxd__VAL REG_VAL_VAL -#define R_SERIAL2_READ__overrun__overrun__VAL REG_VAL_ENUM -#define R_SERIAL2_READ__par_err__par_err__VAL REG_VAL_ENUM -#define R_SERIAL2_READ__framing_err__framing_err__VAL REG_VAL_ENUM -#define R_SERIAL2_READ__data_avail__data_avail__VAL REG_VAL_ENUM -#define R_SERIAL2_READ__data_in__data_in__VAL REG_VAL_VAL - -#define R_SERIAL2_READ__xoff_detect__xoff_detect__no_xoff 0 -#define R_SERIAL2_READ__xoff_detect__xoff_detect__xoff 1 -#define R_SERIAL2_READ__cts___cts___active 0 -#define R_SERIAL2_READ__cts___cts___inactive 1 -#define R_SERIAL2_READ__tr_ready__tr_ready__full 0 -#define R_SERIAL2_READ__tr_ready__tr_ready__ready 1 -#define R_SERIAL2_READ__overrun__overrun__no 0 -#define R_SERIAL2_READ__overrun__overrun__yes 1 -#define R_SERIAL2_READ__par_err__par_err__no 0 -#define R_SERIAL2_READ__par_err__par_err__yes 1 -#define R_SERIAL2_READ__framing_err__framing_err__no 0 -#define R_SERIAL2_READ__framing_err__framing_err__yes 1 -#define R_SERIAL2_READ__data_avail__data_avail__no 0 -#define R_SERIAL2_READ__data_avail__data_avail__yes 1 - -#endif - -/* - * R_SERIAL2_REC_CTRL - * - type: WO - * - addr: 0xb0000072 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -#define R_SERIAL2_REC_CTRL__ADDR (REG_TYPECAST_BYTE 0xb0000072) - -#ifndef REG_NO_SHADOW -#define R_SERIAL2_REC_CTRL__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL2_CTRL + 2)) -#define R_SERIAL2_REC_CTRL__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL2_CTRL + 2)) -#else /* REG_NO_SHADOW */ -#define R_SERIAL2_REC_CTRL__SADDR (REG_STYPECAST_BYTE (®_shadow__hwregs)) -#define R_SERIAL2_REC_CTRL__IADDR (REG_STYPECAST_BYTE (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_SERIAL2_REC_CTRL__STYPECAST REG_STYPECAST_BYTE -#define R_SERIAL2_REC_CTRL__SVAL REG_SVAL_SHADOW -#define R_SERIAL2_REC_CTRL__SVAL_I REG_SVAL_I_SHADOW -#define R_SERIAL2_REC_CTRL__TYPECAST REG_TYPECAST_BYTE -#define R_SERIAL2_REC_CTRL__TYPE (REG_BYTE) -#define R_SERIAL2_REC_CTRL__GET REG_GET_WO -#define R_SERIAL2_REC_CTRL__IGET REG_IGET_WO -#define R_SERIAL2_REC_CTRL__SET REG_SET_WO -#define R_SERIAL2_REC_CTRL__ISET REG_ISET_WO -#define R_SERIAL2_REC_CTRL__SET_VAL REG_SET_VAL_WO -#define R_SERIAL2_REC_CTRL__EQL REG_EQL_WO -#define R_SERIAL2_REC_CTRL__IEQL REG_IEQL_WO -#define R_SERIAL2_REC_CTRL__RD REG_RD_WO -#define R_SERIAL2_REC_CTRL__IRD REG_IRD_WO -#define R_SERIAL2_REC_CTRL__WR REG_WR_WO -#define R_SERIAL2_REC_CTRL__IWR REG_IWR_WO - -#define R_SERIAL2_REC_CTRL__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_SERIAL2_REC_CTRL__dma_err__dma_err__MASK 0x00000080U -#define R_SERIAL2_REC_CTRL__rec_enable__rec_enable__MASK 0x00000040U -#define R_SERIAL2_REC_CTRL__rts___rts___MASK 0x00000020U -#define R_SERIAL2_REC_CTRL__sampling__sampling__MASK 0x00000010U -#define R_SERIAL2_REC_CTRL__rec_stick_par__rec_stick_par__MASK 0x00000008U -#define R_SERIAL2_REC_CTRL__rec_par__rec_par__MASK 0x00000004U -#define R_SERIAL2_REC_CTRL__rec_par_en__rec_par_en__MASK 0x00000002U -#define R_SERIAL2_REC_CTRL__rec_bitnr__rec_bitnr__MASK 0x00000001U - -#define R_SERIAL2_REC_CTRL__dma_err__MAX 0x1 -#define R_SERIAL2_REC_CTRL__rec_enable__MAX 0x1 -#define R_SERIAL2_REC_CTRL__rts___MAX 0x1 -#define R_SERIAL2_REC_CTRL__sampling__MAX 0x1 -#define R_SERIAL2_REC_CTRL__rec_stick_par__MAX 0x1 -#define R_SERIAL2_REC_CTRL__rec_par__MAX 0x1 -#define R_SERIAL2_REC_CTRL__rec_par_en__MAX 0x1 -#define R_SERIAL2_REC_CTRL__rec_bitnr__MAX 0x1 - -#define R_SERIAL2_REC_CTRL__dma_err__MIN 0 -#define R_SERIAL2_REC_CTRL__rec_enable__MIN 0 -#define R_SERIAL2_REC_CTRL__rts___MIN 0 -#define R_SERIAL2_REC_CTRL__sampling__MIN 0 -#define R_SERIAL2_REC_CTRL__rec_stick_par__MIN 0 -#define R_SERIAL2_REC_CTRL__rec_par__MIN 0 -#define R_SERIAL2_REC_CTRL__rec_par_en__MIN 0 -#define R_SERIAL2_REC_CTRL__rec_bitnr__MIN 0 - -#define R_SERIAL2_REC_CTRL__dma_err__BITNR 7 -#define R_SERIAL2_REC_CTRL__rec_enable__BITNR 6 -#define R_SERIAL2_REC_CTRL__rts___BITNR 5 -#define R_SERIAL2_REC_CTRL__sampling__BITNR 4 -#define R_SERIAL2_REC_CTRL__rec_stick_par__BITNR 3 -#define R_SERIAL2_REC_CTRL__rec_par__BITNR 2 -#define R_SERIAL2_REC_CTRL__rec_par_en__BITNR 1 -#define R_SERIAL2_REC_CTRL__rec_bitnr__BITNR 0 - -#define R_SERIAL2_REC_CTRL__dma_err__dma_err__VAL REG_VAL_ENUM -#define R_SERIAL2_REC_CTRL__rec_enable__rec_enable__VAL REG_VAL_ENUM -#define R_SERIAL2_REC_CTRL__rts___rts___VAL REG_VAL_ENUM -#define R_SERIAL2_REC_CTRL__sampling__sampling__VAL REG_VAL_ENUM -#define R_SERIAL2_REC_CTRL__rec_stick_par__rec_stick_par__VAL REG_VAL_ENUM -#define R_SERIAL2_REC_CTRL__rec_par__rec_par__VAL REG_VAL_ENUM -#define R_SERIAL2_REC_CTRL__rec_par_en__rec_par_en__VAL REG_VAL_ENUM -#define R_SERIAL2_REC_CTRL__rec_bitnr__rec_bitnr__VAL REG_VAL_ENUM - -#define R_SERIAL2_REC_CTRL__dma_err__dma_err__ignore 1 -#define R_SERIAL2_REC_CTRL__dma_err__dma_err__stop 0 -#define R_SERIAL2_REC_CTRL__rec_enable__rec_enable__disable 0 -#define R_SERIAL2_REC_CTRL__rec_enable__rec_enable__enable 1 -#define R_SERIAL2_REC_CTRL__rts___rts___active 0 -#define R_SERIAL2_REC_CTRL__rts___rts___inactive 1 -#define R_SERIAL2_REC_CTRL__sampling__sampling__majority 1 -#define R_SERIAL2_REC_CTRL__sampling__sampling__middle 0 -#define R_SERIAL2_REC_CTRL__rec_stick_par__rec_stick_par__normal 0 -#define R_SERIAL2_REC_CTRL__rec_stick_par__rec_stick_par__stick 1 -#define R_SERIAL2_REC_CTRL__rec_par__rec_par__even 0 -#define R_SERIAL2_REC_CTRL__rec_par__rec_par__odd 1 -#define R_SERIAL2_REC_CTRL__rec_par_en__rec_par_en__disable 0 -#define R_SERIAL2_REC_CTRL__rec_par_en__rec_par_en__enable 1 -#define R_SERIAL2_REC_CTRL__rec_bitnr__rec_bitnr__rec_7bit 1 -#define R_SERIAL2_REC_CTRL__rec_bitnr__rec_bitnr__rec_8bit 0 - -#endif - -/* - * R_SERIAL2_REC_DATA - * - type: RO - * - addr: 0xb0000070 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -#define R_SERIAL2_REC_DATA__ADDR (REG_TYPECAST_BYTE 0xb0000070) -#define R_SERIAL2_REC_DATA__SVAL REG_SVAL_SHADOW -#define R_SERIAL2_REC_DATA__SVAL_I REG_SVAL_I_SHADOW -#define R_SERIAL2_REC_DATA__TYPECAST REG_TYPECAST_BYTE -#define R_SERIAL2_REC_DATA__TYPE (REG_BYTE) -#define R_SERIAL2_REC_DATA__GET REG_GET_RO -#define R_SERIAL2_REC_DATA__IGET REG_IGET_RO -#define R_SERIAL2_REC_DATA__SET REG_SET_RO -#define R_SERIAL2_REC_DATA__ISET REG_ISET_RO -#define R_SERIAL2_REC_DATA__SET_VAL REG_SET_VAL_RO -#define R_SERIAL2_REC_DATA__EQL REG_EQL_RO -#define R_SERIAL2_REC_DATA__IEQL REG_IEQL_RO -#define R_SERIAL2_REC_DATA__RD REG_RD_RO -#define R_SERIAL2_REC_DATA__IRD REG_IRD_RO -#define R_SERIAL2_REC_DATA__WR REG_WR_RO -#define R_SERIAL2_REC_DATA__IWR REG_IWR_RO - -#define R_SERIAL2_REC_DATA__READ(addr) \ - (*(addr)) - -#define R_SERIAL2_REC_DATA__data_in__data_in__MASK 0x000000ffU - -#define R_SERIAL2_REC_DATA__data_in__MAX 0xff - -#define R_SERIAL2_REC_DATA__data_in__MIN 0 - -#define R_SERIAL2_REC_DATA__data_in__BITNR 0 - -#define R_SERIAL2_REC_DATA__data_in__data_in__VAL REG_VAL_VAL - - -#endif - -/* - * R_SERIAL2_STATUS - * - type: RO - * - addr: 0xb0000071 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -#define R_SERIAL2_STATUS__ADDR (REG_TYPECAST_BYTE 0xb0000071) -#define R_SERIAL2_STATUS__SVAL REG_SVAL_SHADOW -#define R_SERIAL2_STATUS__SVAL_I REG_SVAL_I_SHADOW -#define R_SERIAL2_STATUS__TYPECAST REG_TYPECAST_BYTE -#define R_SERIAL2_STATUS__TYPE (REG_BYTE) -#define R_SERIAL2_STATUS__GET REG_GET_RO -#define R_SERIAL2_STATUS__IGET REG_IGET_RO -#define R_SERIAL2_STATUS__SET REG_SET_RO -#define R_SERIAL2_STATUS__ISET REG_ISET_RO -#define R_SERIAL2_STATUS__SET_VAL REG_SET_VAL_RO -#define R_SERIAL2_STATUS__EQL REG_EQL_RO -#define R_SERIAL2_STATUS__IEQL REG_IEQL_RO -#define R_SERIAL2_STATUS__RD REG_RD_RO -#define R_SERIAL2_STATUS__IRD REG_IRD_RO -#define R_SERIAL2_STATUS__WR REG_WR_RO -#define R_SERIAL2_STATUS__IWR REG_IWR_RO - -#define R_SERIAL2_STATUS__READ(addr) \ - (*(addr)) - -#define R_SERIAL2_STATUS__xoff_detect__xoff_detect__MASK 0x00000080U -#define R_SERIAL2_STATUS__cts___cts___MASK 0x00000040U -#define R_SERIAL2_STATUS__tr_ready__tr_ready__MASK 0x00000020U -#define R_SERIAL2_STATUS__rxd__rxd__MASK 0x00000010U -#define R_SERIAL2_STATUS__overrun__overrun__MASK 0x00000008U -#define R_SERIAL2_STATUS__par_err__par_err__MASK 0x00000004U -#define R_SERIAL2_STATUS__framing_err__framing_err__MASK 0x00000002U -#define R_SERIAL2_STATUS__data_avail__data_avail__MASK 0x00000001U - -#define R_SERIAL2_STATUS__xoff_detect__MAX 0x1 -#define R_SERIAL2_STATUS__cts___MAX 0x1 -#define R_SERIAL2_STATUS__tr_ready__MAX 0x1 -#define R_SERIAL2_STATUS__rxd__MAX 0x1 -#define R_SERIAL2_STATUS__overrun__MAX 0x1 -#define R_SERIAL2_STATUS__par_err__MAX 0x1 -#define R_SERIAL2_STATUS__framing_err__MAX 0x1 -#define R_SERIAL2_STATUS__data_avail__MAX 0x1 - -#define R_SERIAL2_STATUS__xoff_detect__MIN 0 -#define R_SERIAL2_STATUS__cts___MIN 0 -#define R_SERIAL2_STATUS__tr_ready__MIN 0 -#define R_SERIAL2_STATUS__rxd__MIN 0 -#define R_SERIAL2_STATUS__overrun__MIN 0 -#define R_SERIAL2_STATUS__par_err__MIN 0 -#define R_SERIAL2_STATUS__framing_err__MIN 0 -#define R_SERIAL2_STATUS__data_avail__MIN 0 - -#define R_SERIAL2_STATUS__xoff_detect__BITNR 7 -#define R_SERIAL2_STATUS__cts___BITNR 6 -#define R_SERIAL2_STATUS__tr_ready__BITNR 5 -#define R_SERIAL2_STATUS__rxd__BITNR 4 -#define R_SERIAL2_STATUS__overrun__BITNR 3 -#define R_SERIAL2_STATUS__par_err__BITNR 2 -#define R_SERIAL2_STATUS__framing_err__BITNR 1 -#define R_SERIAL2_STATUS__data_avail__BITNR 0 - -#define R_SERIAL2_STATUS__xoff_detect__xoff_detect__VAL REG_VAL_ENUM -#define R_SERIAL2_STATUS__cts___cts___VAL REG_VAL_ENUM -#define R_SERIAL2_STATUS__tr_ready__tr_ready__VAL REG_VAL_ENUM -#define R_SERIAL2_STATUS__rxd__rxd__VAL REG_VAL_VAL -#define R_SERIAL2_STATUS__overrun__overrun__VAL REG_VAL_ENUM -#define R_SERIAL2_STATUS__par_err__par_err__VAL REG_VAL_ENUM -#define R_SERIAL2_STATUS__framing_err__framing_err__VAL REG_VAL_ENUM -#define R_SERIAL2_STATUS__data_avail__data_avail__VAL REG_VAL_ENUM - -#define R_SERIAL2_STATUS__xoff_detect__xoff_detect__no_xoff 0 -#define R_SERIAL2_STATUS__xoff_detect__xoff_detect__xoff 1 -#define R_SERIAL2_STATUS__cts___cts___active 0 -#define R_SERIAL2_STATUS__cts___cts___inactive 1 -#define R_SERIAL2_STATUS__tr_ready__tr_ready__full 0 -#define R_SERIAL2_STATUS__tr_ready__tr_ready__ready 1 -#define R_SERIAL2_STATUS__overrun__overrun__no 0 -#define R_SERIAL2_STATUS__overrun__overrun__yes 1 -#define R_SERIAL2_STATUS__par_err__par_err__no 0 -#define R_SERIAL2_STATUS__par_err__par_err__yes 1 -#define R_SERIAL2_STATUS__framing_err__framing_err__no 0 -#define R_SERIAL2_STATUS__framing_err__framing_err__yes 1 -#define R_SERIAL2_STATUS__data_avail__data_avail__no 0 -#define R_SERIAL2_STATUS__data_avail__data_avail__yes 1 - -#endif - -/* - * R_SERIAL2_TR_CTRL - * - type: WO - * - addr: 0xb0000071 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -#define R_SERIAL2_TR_CTRL__ADDR (REG_TYPECAST_BYTE 0xb0000071) - -#ifndef REG_NO_SHADOW -#define R_SERIAL2_TR_CTRL__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL2_CTRL + 1)) -#define R_SERIAL2_TR_CTRL__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL2_CTRL + 1)) -#else /* REG_NO_SHADOW */ -#define R_SERIAL2_TR_CTRL__SADDR (REG_STYPECAST_BYTE (®_shadow__hwregs)) -#define R_SERIAL2_TR_CTRL__IADDR (REG_STYPECAST_BYTE (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_SERIAL2_TR_CTRL__STYPECAST REG_STYPECAST_BYTE -#define R_SERIAL2_TR_CTRL__SVAL REG_SVAL_SHADOW -#define R_SERIAL2_TR_CTRL__SVAL_I REG_SVAL_I_SHADOW -#define R_SERIAL2_TR_CTRL__TYPECAST REG_TYPECAST_BYTE -#define R_SERIAL2_TR_CTRL__TYPE (REG_BYTE) -#define R_SERIAL2_TR_CTRL__GET REG_GET_WO -#define R_SERIAL2_TR_CTRL__IGET REG_IGET_WO -#define R_SERIAL2_TR_CTRL__SET REG_SET_WO -#define R_SERIAL2_TR_CTRL__ISET REG_ISET_WO -#define R_SERIAL2_TR_CTRL__SET_VAL REG_SET_VAL_WO -#define R_SERIAL2_TR_CTRL__EQL REG_EQL_WO -#define R_SERIAL2_TR_CTRL__IEQL REG_IEQL_WO -#define R_SERIAL2_TR_CTRL__RD REG_RD_WO -#define R_SERIAL2_TR_CTRL__IRD REG_IRD_WO -#define R_SERIAL2_TR_CTRL__WR REG_WR_WO -#define R_SERIAL2_TR_CTRL__IWR REG_IWR_WO - -#define R_SERIAL2_TR_CTRL__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_SERIAL2_TR_CTRL__txd__txd__MASK 0x00000080U -#define R_SERIAL2_TR_CTRL__tr_enable__tr_enable__MASK 0x00000040U -#define R_SERIAL2_TR_CTRL__auto_cts__auto_cts__MASK 0x00000020U -#define R_SERIAL2_TR_CTRL__stop_bits__stop_bits__MASK 0x00000010U -#define R_SERIAL2_TR_CTRL__tr_stick_par__tr_stick_par__MASK 0x00000008U -#define R_SERIAL2_TR_CTRL__tr_par__tr_par__MASK 0x00000004U -#define R_SERIAL2_TR_CTRL__tr_par_en__tr_par_en__MASK 0x00000002U -#define R_SERIAL2_TR_CTRL__tr_bitnr__tr_bitnr__MASK 0x00000001U - -#define R_SERIAL2_TR_CTRL__txd__MAX 0x1 -#define R_SERIAL2_TR_CTRL__tr_enable__MAX 0x1 -#define R_SERIAL2_TR_CTRL__auto_cts__MAX 0x1 -#define R_SERIAL2_TR_CTRL__stop_bits__MAX 0x1 -#define R_SERIAL2_TR_CTRL__tr_stick_par__MAX 0x1 -#define R_SERIAL2_TR_CTRL__tr_par__MAX 0x1 -#define R_SERIAL2_TR_CTRL__tr_par_en__MAX 0x1 -#define R_SERIAL2_TR_CTRL__tr_bitnr__MAX 0x1 - -#define R_SERIAL2_TR_CTRL__txd__MIN 0 -#define R_SERIAL2_TR_CTRL__tr_enable__MIN 0 -#define R_SERIAL2_TR_CTRL__auto_cts__MIN 0 -#define R_SERIAL2_TR_CTRL__stop_bits__MIN 0 -#define R_SERIAL2_TR_CTRL__tr_stick_par__MIN 0 -#define R_SERIAL2_TR_CTRL__tr_par__MIN 0 -#define R_SERIAL2_TR_CTRL__tr_par_en__MIN 0 -#define R_SERIAL2_TR_CTRL__tr_bitnr__MIN 0 - -#define R_SERIAL2_TR_CTRL__txd__BITNR 7 -#define R_SERIAL2_TR_CTRL__tr_enable__BITNR 6 -#define R_SERIAL2_TR_CTRL__auto_cts__BITNR 5 -#define R_SERIAL2_TR_CTRL__stop_bits__BITNR 4 -#define R_SERIAL2_TR_CTRL__tr_stick_par__BITNR 3 -#define R_SERIAL2_TR_CTRL__tr_par__BITNR 2 -#define R_SERIAL2_TR_CTRL__tr_par_en__BITNR 1 -#define R_SERIAL2_TR_CTRL__tr_bitnr__BITNR 0 - -#define R_SERIAL2_TR_CTRL__txd__txd__VAL REG_VAL_VAL -#define R_SERIAL2_TR_CTRL__tr_enable__tr_enable__VAL REG_VAL_ENUM -#define R_SERIAL2_TR_CTRL__auto_cts__auto_cts__VAL REG_VAL_ENUM -#define R_SERIAL2_TR_CTRL__stop_bits__stop_bits__VAL REG_VAL_ENUM -#define R_SERIAL2_TR_CTRL__tr_stick_par__tr_stick_par__VAL REG_VAL_ENUM -#define R_SERIAL2_TR_CTRL__tr_par__tr_par__VAL REG_VAL_ENUM -#define R_SERIAL2_TR_CTRL__tr_par_en__tr_par_en__VAL REG_VAL_ENUM -#define R_SERIAL2_TR_CTRL__tr_bitnr__tr_bitnr__VAL REG_VAL_ENUM - -#define R_SERIAL2_TR_CTRL__tr_enable__tr_enable__disable 0 -#define R_SERIAL2_TR_CTRL__tr_enable__tr_enable__enable 1 -#define R_SERIAL2_TR_CTRL__auto_cts__auto_cts__active 1 -#define R_SERIAL2_TR_CTRL__auto_cts__auto_cts__disabled 0 -#define R_SERIAL2_TR_CTRL__stop_bits__stop_bits__one_bit 0 -#define R_SERIAL2_TR_CTRL__stop_bits__stop_bits__two_bits 1 -#define R_SERIAL2_TR_CTRL__tr_stick_par__tr_stick_par__normal 0 -#define R_SERIAL2_TR_CTRL__tr_stick_par__tr_stick_par__stick 1 -#define R_SERIAL2_TR_CTRL__tr_par__tr_par__even 0 -#define R_SERIAL2_TR_CTRL__tr_par__tr_par__odd 1 -#define R_SERIAL2_TR_CTRL__tr_par_en__tr_par_en__disable 0 -#define R_SERIAL2_TR_CTRL__tr_par_en__tr_par_en__enable 1 -#define R_SERIAL2_TR_CTRL__tr_bitnr__tr_bitnr__tr_7bit 1 -#define R_SERIAL2_TR_CTRL__tr_bitnr__tr_bitnr__tr_8bit 0 - -#endif - -/* - * R_SERIAL2_TR_DATA - * - type: WO - * - addr: 0xb0000070 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -#define R_SERIAL2_TR_DATA__ADDR (REG_TYPECAST_BYTE 0xb0000070) - -#ifndef REG_NO_SHADOW -#define R_SERIAL2_TR_DATA__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL2_CTRL + 0)) -#define R_SERIAL2_TR_DATA__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL2_CTRL + 0)) -#else /* REG_NO_SHADOW */ -#define R_SERIAL2_TR_DATA__SADDR (REG_STYPECAST_BYTE (®_shadow__hwregs)) -#define R_SERIAL2_TR_DATA__IADDR (REG_STYPECAST_BYTE (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_SERIAL2_TR_DATA__STYPECAST REG_STYPECAST_BYTE -#define R_SERIAL2_TR_DATA__SVAL REG_SVAL_SHADOW -#define R_SERIAL2_TR_DATA__SVAL_I REG_SVAL_I_SHADOW -#define R_SERIAL2_TR_DATA__TYPECAST REG_TYPECAST_BYTE -#define R_SERIAL2_TR_DATA__TYPE (REG_BYTE) -#define R_SERIAL2_TR_DATA__GET REG_GET_WO -#define R_SERIAL2_TR_DATA__IGET REG_IGET_WO -#define R_SERIAL2_TR_DATA__SET REG_SET_WO -#define R_SERIAL2_TR_DATA__ISET REG_ISET_WO -#define R_SERIAL2_TR_DATA__SET_VAL REG_SET_VAL_WO -#define R_SERIAL2_TR_DATA__EQL REG_EQL_WO -#define R_SERIAL2_TR_DATA__IEQL REG_IEQL_WO -#define R_SERIAL2_TR_DATA__RD REG_RD_WO -#define R_SERIAL2_TR_DATA__IRD REG_IRD_WO -#define R_SERIAL2_TR_DATA__WR REG_WR_WO -#define R_SERIAL2_TR_DATA__IWR REG_IWR_WO - -#define R_SERIAL2_TR_DATA__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_SERIAL2_TR_DATA__data_out__data_out__MASK 0x000000ffU - -#define R_SERIAL2_TR_DATA__data_out__MAX 0xff - -#define R_SERIAL2_TR_DATA__data_out__MIN 0 - -#define R_SERIAL2_TR_DATA__data_out__BITNR 0 - -#define R_SERIAL2_TR_DATA__data_out__data_out__VAL REG_VAL_VAL - - -#endif - -/* - * R_SERIAL2_XOFF - * - type: WO - * - addr: 0xb0000074 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -#define R_SERIAL2_XOFF__ADDR (REG_TYPECAST_UDWORD 0xb0000074) - -#ifndef REG_NO_SHADOW -#define R_SERIAL2_XOFF__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_SERIAL2_XOFF + 0)) -#define R_SERIAL2_XOFF__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_SERIAL2_XOFF + 0)) -#else /* REG_NO_SHADOW */ -#define R_SERIAL2_XOFF__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_SERIAL2_XOFF__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_SERIAL2_XOFF__STYPECAST REG_STYPECAST_UDWORD -#define R_SERIAL2_XOFF__SVAL REG_SVAL_SHADOW -#define R_SERIAL2_XOFF__SVAL_I REG_SVAL_I_SHADOW -#define R_SERIAL2_XOFF__TYPECAST REG_TYPECAST_UDWORD -#define R_SERIAL2_XOFF__TYPE (REG_UDWORD) -#define R_SERIAL2_XOFF__GET REG_GET_WO -#define R_SERIAL2_XOFF__IGET REG_IGET_WO -#define R_SERIAL2_XOFF__SET REG_SET_WO -#define R_SERIAL2_XOFF__ISET REG_ISET_WO -#define R_SERIAL2_XOFF__SET_VAL REG_SET_VAL_WO -#define R_SERIAL2_XOFF__EQL REG_EQL_WO -#define R_SERIAL2_XOFF__IEQL REG_IEQL_WO -#define R_SERIAL2_XOFF__RD REG_RD_WO -#define R_SERIAL2_XOFF__IRD REG_IRD_WO -#define R_SERIAL2_XOFF__WR REG_WR_WO -#define R_SERIAL2_XOFF__IWR REG_IWR_WO - -#define R_SERIAL2_XOFF__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_SERIAL2_XOFF__tx_stop__tx_stop__MASK 0x00000200U -#define R_SERIAL2_XOFF__auto_xoff__auto_xoff__MASK 0x00000100U -#define R_SERIAL2_XOFF__xoff_char__xoff_char__MASK 0x000000ffU - -#define R_SERIAL2_XOFF__tx_stop__MAX 0x1 -#define R_SERIAL2_XOFF__auto_xoff__MAX 0x1 -#define R_SERIAL2_XOFF__xoff_char__MAX 0xff - -#define R_SERIAL2_XOFF__tx_stop__MIN 0 -#define R_SERIAL2_XOFF__auto_xoff__MIN 0 -#define R_SERIAL2_XOFF__xoff_char__MIN 0 - -#define R_SERIAL2_XOFF__tx_stop__BITNR 9 -#define R_SERIAL2_XOFF__auto_xoff__BITNR 8 -#define R_SERIAL2_XOFF__xoff_char__BITNR 0 - -#define R_SERIAL2_XOFF__tx_stop__tx_stop__VAL REG_VAL_ENUM -#define R_SERIAL2_XOFF__auto_xoff__auto_xoff__VAL REG_VAL_ENUM -#define R_SERIAL2_XOFF__xoff_char__xoff_char__VAL REG_VAL_VAL - -#define R_SERIAL2_XOFF__tx_stop__tx_stop__enable 0 -#define R_SERIAL2_XOFF__tx_stop__tx_stop__stop 1 -#define R_SERIAL2_XOFF__auto_xoff__auto_xoff__disable 0 -#define R_SERIAL2_XOFF__auto_xoff__auto_xoff__enable 1 - -#endif - -/* - * R_SERIAL3_BAUD - * - type: WO - * - addr: 0xb000007b - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -#define R_SERIAL3_BAUD__ADDR (REG_TYPECAST_BYTE 0xb000007b) - -#ifndef REG_NO_SHADOW -#define R_SERIAL3_BAUD__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL3_CTRL + 3)) -#define R_SERIAL3_BAUD__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL3_CTRL + 3)) -#else /* REG_NO_SHADOW */ -#define R_SERIAL3_BAUD__SADDR (REG_STYPECAST_BYTE (®_shadow__hwregs)) -#define R_SERIAL3_BAUD__IADDR (REG_STYPECAST_BYTE (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_SERIAL3_BAUD__STYPECAST REG_STYPECAST_BYTE -#define R_SERIAL3_BAUD__SVAL REG_SVAL_SHADOW -#define R_SERIAL3_BAUD__SVAL_I REG_SVAL_I_SHADOW -#define R_SERIAL3_BAUD__TYPECAST REG_TYPECAST_BYTE -#define R_SERIAL3_BAUD__TYPE (REG_BYTE) -#define R_SERIAL3_BAUD__GET REG_GET_WO -#define R_SERIAL3_BAUD__IGET REG_IGET_WO -#define R_SERIAL3_BAUD__SET REG_SET_WO -#define R_SERIAL3_BAUD__ISET REG_ISET_WO -#define R_SERIAL3_BAUD__SET_VAL REG_SET_VAL_WO -#define R_SERIAL3_BAUD__EQL REG_EQL_WO -#define R_SERIAL3_BAUD__IEQL REG_IEQL_WO -#define R_SERIAL3_BAUD__RD REG_RD_WO -#define R_SERIAL3_BAUD__IRD REG_IRD_WO -#define R_SERIAL3_BAUD__WR REG_WR_WO -#define R_SERIAL3_BAUD__IWR REG_IWR_WO - -#define R_SERIAL3_BAUD__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_SERIAL3_BAUD__tr_baud__tr_baud__MASK 0x000000f0U -#define R_SERIAL3_BAUD__rec_baud__rec_baud__MASK 0x0000000fU - -#define R_SERIAL3_BAUD__tr_baud__MAX 0xf -#define R_SERIAL3_BAUD__rec_baud__MAX 0xf - -#define R_SERIAL3_BAUD__tr_baud__MIN 0 -#define R_SERIAL3_BAUD__rec_baud__MIN 0 - -#define R_SERIAL3_BAUD__tr_baud__BITNR 4 -#define R_SERIAL3_BAUD__rec_baud__BITNR 0 - -#define R_SERIAL3_BAUD__tr_baud__tr_baud__VAL REG_VAL_ENUM -#define R_SERIAL3_BAUD__rec_baud__rec_baud__VAL REG_VAL_ENUM - -#define R_SERIAL3_BAUD__tr_baud__tr_baud__c115k2Hz 9 -#define R_SERIAL3_BAUD__tr_baud__tr_baud__c1200Hz 2 -#define R_SERIAL3_BAUD__tr_baud__tr_baud__c1843k2Hz 13 -#define R_SERIAL3_BAUD__tr_baud__tr_baud__c19k2Hz 6 -#define R_SERIAL3_BAUD__tr_baud__tr_baud__c230k4Hz 10 -#define R_SERIAL3_BAUD__tr_baud__tr_baud__c2400Hz 3 -#define R_SERIAL3_BAUD__tr_baud__tr_baud__c300Hz 0 -#define R_SERIAL3_BAUD__tr_baud__tr_baud__c38k4Hz 7 -#define R_SERIAL3_BAUD__tr_baud__tr_baud__c460k8Hz 11 -#define R_SERIAL3_BAUD__tr_baud__tr_baud__c4800Hz 4 -#define R_SERIAL3_BAUD__tr_baud__tr_baud__c57k6Hz 8 -#define R_SERIAL3_BAUD__tr_baud__tr_baud__c600Hz 1 -#define R_SERIAL3_BAUD__tr_baud__tr_baud__c6250kHz 14 -#define R_SERIAL3_BAUD__tr_baud__tr_baud__c921k6Hz 12 -#define R_SERIAL3_BAUD__tr_baud__tr_baud__c9600Hz 5 -#define R_SERIAL3_BAUD__rec_baud__rec_baud__c115k2Hz 9 -#define R_SERIAL3_BAUD__rec_baud__rec_baud__c1200Hz 2 -#define R_SERIAL3_BAUD__rec_baud__rec_baud__c1843k2Hz 13 -#define R_SERIAL3_BAUD__rec_baud__rec_baud__c19k2Hz 6 -#define R_SERIAL3_BAUD__rec_baud__rec_baud__c230k4Hz 10 -#define R_SERIAL3_BAUD__rec_baud__rec_baud__c2400Hz 3 -#define R_SERIAL3_BAUD__rec_baud__rec_baud__c300Hz 0 -#define R_SERIAL3_BAUD__rec_baud__rec_baud__c38k4Hz 7 -#define R_SERIAL3_BAUD__rec_baud__rec_baud__c460k8Hz 11 -#define R_SERIAL3_BAUD__rec_baud__rec_baud__c4800Hz 4 -#define R_SERIAL3_BAUD__rec_baud__rec_baud__c57k6Hz 8 -#define R_SERIAL3_BAUD__rec_baud__rec_baud__c600Hz 1 -#define R_SERIAL3_BAUD__rec_baud__rec_baud__c6250kHz 14 -#define R_SERIAL3_BAUD__rec_baud__rec_baud__c921k6Hz 12 -#define R_SERIAL3_BAUD__rec_baud__rec_baud__c9600Hz 5 - -#endif - -/* - * R_SERIAL3_CTRL - * - type: WO - * - addr: 0xb0000078 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -#define R_SERIAL3_CTRL__ADDR (REG_TYPECAST_UDWORD 0xb0000078) - -#ifndef REG_NO_SHADOW -#define R_SERIAL3_CTRL__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_SERIAL3_CTRL + 0)) -#define R_SERIAL3_CTRL__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_SERIAL3_CTRL + 0)) -#else /* REG_NO_SHADOW */ -#define R_SERIAL3_CTRL__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_SERIAL3_CTRL__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_SERIAL3_CTRL__STYPECAST REG_STYPECAST_UDWORD -#define R_SERIAL3_CTRL__SVAL REG_SVAL_SHADOW -#define R_SERIAL3_CTRL__SVAL_I REG_SVAL_I_SHADOW -#define R_SERIAL3_CTRL__TYPECAST REG_TYPECAST_UDWORD -#define R_SERIAL3_CTRL__TYPE (REG_UDWORD) -#define R_SERIAL3_CTRL__GET REG_GET_WO -#define R_SERIAL3_CTRL__IGET REG_IGET_WO -#define R_SERIAL3_CTRL__SET REG_SET_WO -#define R_SERIAL3_CTRL__ISET REG_ISET_WO -#define R_SERIAL3_CTRL__SET_VAL REG_SET_VAL_WO -#define R_SERIAL3_CTRL__EQL REG_EQL_WO -#define R_SERIAL3_CTRL__IEQL REG_IEQL_WO -#define R_SERIAL3_CTRL__RD REG_RD_WO -#define R_SERIAL3_CTRL__IRD REG_IRD_WO -#define R_SERIAL3_CTRL__WR REG_WR_WO -#define R_SERIAL3_CTRL__IWR REG_IWR_WO - -#define R_SERIAL3_CTRL__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_SERIAL3_CTRL__tr_baud__tr_baud__MASK 0xf0000000U -#define R_SERIAL3_CTRL__rec_baud__rec_baud__MASK 0x0f000000U -#define R_SERIAL3_CTRL__dma_err__dma_err__MASK 0x00800000U -#define R_SERIAL3_CTRL__rec_enable__rec_enable__MASK 0x00400000U -#define R_SERIAL3_CTRL__rts___rts___MASK 0x00200000U -#define R_SERIAL3_CTRL__sampling__sampling__MASK 0x00100000U -#define R_SERIAL3_CTRL__rec_stick_par__rec_stick_par__MASK 0x00080000U -#define R_SERIAL3_CTRL__rec_par__rec_par__MASK 0x00040000U -#define R_SERIAL3_CTRL__rec_par_en__rec_par_en__MASK 0x00020000U -#define R_SERIAL3_CTRL__rec_bitnr__rec_bitnr__MASK 0x00010000U -#define R_SERIAL3_CTRL__txd__txd__MASK 0x00008000U -#define R_SERIAL3_CTRL__tr_enable__tr_enable__MASK 0x00004000U -#define R_SERIAL3_CTRL__auto_cts__auto_cts__MASK 0x00002000U -#define R_SERIAL3_CTRL__stop_bits__stop_bits__MASK 0x00001000U -#define R_SERIAL3_CTRL__tr_stick_par__tr_stick_par__MASK 0x00000800U -#define R_SERIAL3_CTRL__tr_par__tr_par__MASK 0x00000400U -#define R_SERIAL3_CTRL__tr_par_en__tr_par_en__MASK 0x00000200U -#define R_SERIAL3_CTRL__tr_bitnr__tr_bitnr__MASK 0x00000100U -#define R_SERIAL3_CTRL__data_out__data_out__MASK 0x000000ffU - -#define R_SERIAL3_CTRL__tr_baud__MAX 0xf -#define R_SERIAL3_CTRL__rec_baud__MAX 0xf -#define R_SERIAL3_CTRL__dma_err__MAX 0x1 -#define R_SERIAL3_CTRL__rec_enable__MAX 0x1 -#define R_SERIAL3_CTRL__rts___MAX 0x1 -#define R_SERIAL3_CTRL__sampling__MAX 0x1 -#define R_SERIAL3_CTRL__rec_stick_par__MAX 0x1 -#define R_SERIAL3_CTRL__rec_par__MAX 0x1 -#define R_SERIAL3_CTRL__rec_par_en__MAX 0x1 -#define R_SERIAL3_CTRL__rec_bitnr__MAX 0x1 -#define R_SERIAL3_CTRL__txd__MAX 0x1 -#define R_SERIAL3_CTRL__tr_enable__MAX 0x1 -#define R_SERIAL3_CTRL__auto_cts__MAX 0x1 -#define R_SERIAL3_CTRL__stop_bits__MAX 0x1 -#define R_SERIAL3_CTRL__tr_stick_par__MAX 0x1 -#define R_SERIAL3_CTRL__tr_par__MAX 0x1 -#define R_SERIAL3_CTRL__tr_par_en__MAX 0x1 -#define R_SERIAL3_CTRL__tr_bitnr__MAX 0x1 -#define R_SERIAL3_CTRL__data_out__MAX 0xff - -#define R_SERIAL3_CTRL__tr_baud__MIN 0 -#define R_SERIAL3_CTRL__rec_baud__MIN 0 -#define R_SERIAL3_CTRL__dma_err__MIN 0 -#define R_SERIAL3_CTRL__rec_enable__MIN 0 -#define R_SERIAL3_CTRL__rts___MIN 0 -#define R_SERIAL3_CTRL__sampling__MIN 0 -#define R_SERIAL3_CTRL__rec_stick_par__MIN 0 -#define R_SERIAL3_CTRL__rec_par__MIN 0 -#define R_SERIAL3_CTRL__rec_par_en__MIN 0 -#define R_SERIAL3_CTRL__rec_bitnr__MIN 0 -#define R_SERIAL3_CTRL__txd__MIN 0 -#define R_SERIAL3_CTRL__tr_enable__MIN 0 -#define R_SERIAL3_CTRL__auto_cts__MIN 0 -#define R_SERIAL3_CTRL__stop_bits__MIN 0 -#define R_SERIAL3_CTRL__tr_stick_par__MIN 0 -#define R_SERIAL3_CTRL__tr_par__MIN 0 -#define R_SERIAL3_CTRL__tr_par_en__MIN 0 -#define R_SERIAL3_CTRL__tr_bitnr__MIN 0 -#define R_SERIAL3_CTRL__data_out__MIN 0 - -#define R_SERIAL3_CTRL__tr_baud__BITNR 28 -#define R_SERIAL3_CTRL__rec_baud__BITNR 24 -#define R_SERIAL3_CTRL__dma_err__BITNR 23 -#define R_SERIAL3_CTRL__rec_enable__BITNR 22 -#define R_SERIAL3_CTRL__rts___BITNR 21 -#define R_SERIAL3_CTRL__sampling__BITNR 20 -#define R_SERIAL3_CTRL__rec_stick_par__BITNR 19 -#define R_SERIAL3_CTRL__rec_par__BITNR 18 -#define R_SERIAL3_CTRL__rec_par_en__BITNR 17 -#define R_SERIAL3_CTRL__rec_bitnr__BITNR 16 -#define R_SERIAL3_CTRL__txd__BITNR 15 -#define R_SERIAL3_CTRL__tr_enable__BITNR 14 -#define R_SERIAL3_CTRL__auto_cts__BITNR 13 -#define R_SERIAL3_CTRL__stop_bits__BITNR 12 -#define R_SERIAL3_CTRL__tr_stick_par__BITNR 11 -#define R_SERIAL3_CTRL__tr_par__BITNR 10 -#define R_SERIAL3_CTRL__tr_par_en__BITNR 9 -#define R_SERIAL3_CTRL__tr_bitnr__BITNR 8 -#define R_SERIAL3_CTRL__data_out__BITNR 0 - -#define R_SERIAL3_CTRL__tr_baud__tr_baud__VAL REG_VAL_ENUM -#define R_SERIAL3_CTRL__rec_baud__rec_baud__VAL REG_VAL_ENUM -#define R_SERIAL3_CTRL__dma_err__dma_err__VAL REG_VAL_ENUM -#define R_SERIAL3_CTRL__rec_enable__rec_enable__VAL REG_VAL_ENUM -#define R_SERIAL3_CTRL__rts___rts___VAL REG_VAL_ENUM -#define R_SERIAL3_CTRL__sampling__sampling__VAL REG_VAL_ENUM -#define R_SERIAL3_CTRL__rec_stick_par__rec_stick_par__VAL REG_VAL_ENUM -#define R_SERIAL3_CTRL__rec_par__rec_par__VAL REG_VAL_ENUM -#define R_SERIAL3_CTRL__rec_par_en__rec_par_en__VAL REG_VAL_ENUM -#define R_SERIAL3_CTRL__rec_bitnr__rec_bitnr__VAL REG_VAL_ENUM -#define R_SERIAL3_CTRL__txd__txd__VAL REG_VAL_VAL -#define R_SERIAL3_CTRL__tr_enable__tr_enable__VAL REG_VAL_ENUM -#define R_SERIAL3_CTRL__auto_cts__auto_cts__VAL REG_VAL_ENUM -#define R_SERIAL3_CTRL__stop_bits__stop_bits__VAL REG_VAL_ENUM -#define R_SERIAL3_CTRL__tr_stick_par__tr_stick_par__VAL REG_VAL_ENUM -#define R_SERIAL3_CTRL__tr_par__tr_par__VAL REG_VAL_ENUM -#define R_SERIAL3_CTRL__tr_par_en__tr_par_en__VAL REG_VAL_ENUM -#define R_SERIAL3_CTRL__tr_bitnr__tr_bitnr__VAL REG_VAL_ENUM -#define R_SERIAL3_CTRL__data_out__data_out__VAL REG_VAL_VAL - -#define R_SERIAL3_CTRL__tr_baud__tr_baud__c115k2Hz 9 -#define R_SERIAL3_CTRL__tr_baud__tr_baud__c1200Hz 2 -#define R_SERIAL3_CTRL__tr_baud__tr_baud__c1843k2Hz 13 -#define R_SERIAL3_CTRL__tr_baud__tr_baud__c19k2Hz 6 -#define R_SERIAL3_CTRL__tr_baud__tr_baud__c230k4Hz 10 -#define R_SERIAL3_CTRL__tr_baud__tr_baud__c2400Hz 3 -#define R_SERIAL3_CTRL__tr_baud__tr_baud__c300Hz 0 -#define R_SERIAL3_CTRL__tr_baud__tr_baud__c38k4Hz 7 -#define R_SERIAL3_CTRL__tr_baud__tr_baud__c460k8Hz 11 -#define R_SERIAL3_CTRL__tr_baud__tr_baud__c4800Hz 4 -#define R_SERIAL3_CTRL__tr_baud__tr_baud__c57k6Hz 8 -#define R_SERIAL3_CTRL__tr_baud__tr_baud__c600Hz 1 -#define R_SERIAL3_CTRL__tr_baud__tr_baud__c6250kHz 14 -#define R_SERIAL3_CTRL__tr_baud__tr_baud__c921k6Hz 12 -#define R_SERIAL3_CTRL__tr_baud__tr_baud__c9600Hz 5 -#define R_SERIAL3_CTRL__rec_baud__rec_baud__c115k2Hz 9 -#define R_SERIAL3_CTRL__rec_baud__rec_baud__c1200Hz 2 -#define R_SERIAL3_CTRL__rec_baud__rec_baud__c1843k2Hz 13 -#define R_SERIAL3_CTRL__rec_baud__rec_baud__c19k2Hz 6 -#define R_SERIAL3_CTRL__rec_baud__rec_baud__c230k4Hz 10 -#define R_SERIAL3_CTRL__rec_baud__rec_baud__c2400Hz 3 -#define R_SERIAL3_CTRL__rec_baud__rec_baud__c300Hz 0 -#define R_SERIAL3_CTRL__rec_baud__rec_baud__c38k4Hz 7 -#define R_SERIAL3_CTRL__rec_baud__rec_baud__c460k8Hz 11 -#define R_SERIAL3_CTRL__rec_baud__rec_baud__c4800Hz 4 -#define R_SERIAL3_CTRL__rec_baud__rec_baud__c57k6Hz 8 -#define R_SERIAL3_CTRL__rec_baud__rec_baud__c600Hz 1 -#define R_SERIAL3_CTRL__rec_baud__rec_baud__c6250kHz 14 -#define R_SERIAL3_CTRL__rec_baud__rec_baud__c921k6Hz 12 -#define R_SERIAL3_CTRL__rec_baud__rec_baud__c9600Hz 5 -#define R_SERIAL3_CTRL__dma_err__dma_err__ignore 1 -#define R_SERIAL3_CTRL__dma_err__dma_err__stop 0 -#define R_SERIAL3_CTRL__rec_enable__rec_enable__disable 0 -#define R_SERIAL3_CTRL__rec_enable__rec_enable__enable 1 -#define R_SERIAL3_CTRL__rts___rts___active 0 -#define R_SERIAL3_CTRL__rts___rts___inactive 1 -#define R_SERIAL3_CTRL__sampling__sampling__majority 1 -#define R_SERIAL3_CTRL__sampling__sampling__middle 0 -#define R_SERIAL3_CTRL__rec_stick_par__rec_stick_par__normal 0 -#define R_SERIAL3_CTRL__rec_stick_par__rec_stick_par__stick 1 -#define R_SERIAL3_CTRL__rec_par__rec_par__even 0 -#define R_SERIAL3_CTRL__rec_par__rec_par__odd 1 -#define R_SERIAL3_CTRL__rec_par_en__rec_par_en__disable 0 -#define R_SERIAL3_CTRL__rec_par_en__rec_par_en__enable 1 -#define R_SERIAL3_CTRL__rec_bitnr__rec_bitnr__rec_7bit 1 -#define R_SERIAL3_CTRL__rec_bitnr__rec_bitnr__rec_8bit 0 -#define R_SERIAL3_CTRL__tr_enable__tr_enable__disable 0 -#define R_SERIAL3_CTRL__tr_enable__tr_enable__enable 1 -#define R_SERIAL3_CTRL__auto_cts__auto_cts__active 1 -#define R_SERIAL3_CTRL__auto_cts__auto_cts__disabled 0 -#define R_SERIAL3_CTRL__stop_bits__stop_bits__one_bit 0 -#define R_SERIAL3_CTRL__stop_bits__stop_bits__two_bits 1 -#define R_SERIAL3_CTRL__tr_stick_par__tr_stick_par__normal 0 -#define R_SERIAL3_CTRL__tr_stick_par__tr_stick_par__stick 1 -#define R_SERIAL3_CTRL__tr_par__tr_par__even 0 -#define R_SERIAL3_CTRL__tr_par__tr_par__odd 1 -#define R_SERIAL3_CTRL__tr_par_en__tr_par_en__disable 0 -#define R_SERIAL3_CTRL__tr_par_en__tr_par_en__enable 1 -#define R_SERIAL3_CTRL__tr_bitnr__tr_bitnr__tr_7bit 1 -#define R_SERIAL3_CTRL__tr_bitnr__tr_bitnr__tr_8bit 0 - -#endif - -/* - * R_SERIAL3_READ - * - type: RO - * - addr: 0xb0000078 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -#define R_SERIAL3_READ__ADDR (REG_TYPECAST_UDWORD 0xb0000078) -#define R_SERIAL3_READ__SVAL REG_SVAL_SHADOW -#define R_SERIAL3_READ__SVAL_I REG_SVAL_I_SHADOW -#define R_SERIAL3_READ__TYPECAST REG_TYPECAST_UDWORD -#define R_SERIAL3_READ__TYPE (REG_UDWORD) -#define R_SERIAL3_READ__GET REG_GET_RO -#define R_SERIAL3_READ__IGET REG_IGET_RO -#define R_SERIAL3_READ__SET REG_SET_RO -#define R_SERIAL3_READ__ISET REG_ISET_RO -#define R_SERIAL3_READ__SET_VAL REG_SET_VAL_RO -#define R_SERIAL3_READ__EQL REG_EQL_RO -#define R_SERIAL3_READ__IEQL REG_IEQL_RO -#define R_SERIAL3_READ__RD REG_RD_RO -#define R_SERIAL3_READ__IRD REG_IRD_RO -#define R_SERIAL3_READ__WR REG_WR_RO -#define R_SERIAL3_READ__IWR REG_IWR_RO - -#define R_SERIAL3_READ__READ(addr) \ - (*(addr)) - -#define R_SERIAL3_READ__xoff_detect__xoff_detect__MASK 0x00008000U -#define R_SERIAL3_READ__cts___cts___MASK 0x00004000U -#define R_SERIAL3_READ__tr_ready__tr_ready__MASK 0x00002000U -#define R_SERIAL3_READ__rxd__rxd__MASK 0x00001000U -#define R_SERIAL3_READ__overrun__overrun__MASK 0x00000800U -#define R_SERIAL3_READ__par_err__par_err__MASK 0x00000400U -#define R_SERIAL3_READ__framing_err__framing_err__MASK 0x00000200U -#define R_SERIAL3_READ__data_avail__data_avail__MASK 0x00000100U -#define R_SERIAL3_READ__data_in__data_in__MASK 0x000000ffU - -#define R_SERIAL3_READ__xoff_detect__MAX 0x1 -#define R_SERIAL3_READ__cts___MAX 0x1 -#define R_SERIAL3_READ__tr_ready__MAX 0x1 -#define R_SERIAL3_READ__rxd__MAX 0x1 -#define R_SERIAL3_READ__overrun__MAX 0x1 -#define R_SERIAL3_READ__par_err__MAX 0x1 -#define R_SERIAL3_READ__framing_err__MAX 0x1 -#define R_SERIAL3_READ__data_avail__MAX 0x1 -#define R_SERIAL3_READ__data_in__MAX 0xff - -#define R_SERIAL3_READ__xoff_detect__MIN 0 -#define R_SERIAL3_READ__cts___MIN 0 -#define R_SERIAL3_READ__tr_ready__MIN 0 -#define R_SERIAL3_READ__rxd__MIN 0 -#define R_SERIAL3_READ__overrun__MIN 0 -#define R_SERIAL3_READ__par_err__MIN 0 -#define R_SERIAL3_READ__framing_err__MIN 0 -#define R_SERIAL3_READ__data_avail__MIN 0 -#define R_SERIAL3_READ__data_in__MIN 0 - -#define R_SERIAL3_READ__xoff_detect__BITNR 15 -#define R_SERIAL3_READ__cts___BITNR 14 -#define R_SERIAL3_READ__tr_ready__BITNR 13 -#define R_SERIAL3_READ__rxd__BITNR 12 -#define R_SERIAL3_READ__overrun__BITNR 11 -#define R_SERIAL3_READ__par_err__BITNR 10 -#define R_SERIAL3_READ__framing_err__BITNR 9 -#define R_SERIAL3_READ__data_avail__BITNR 8 -#define R_SERIAL3_READ__data_in__BITNR 0 - -#define R_SERIAL3_READ__xoff_detect__xoff_detect__VAL REG_VAL_ENUM -#define R_SERIAL3_READ__cts___cts___VAL REG_VAL_ENUM -#define R_SERIAL3_READ__tr_ready__tr_ready__VAL REG_VAL_ENUM -#define R_SERIAL3_READ__rxd__rxd__VAL REG_VAL_VAL -#define R_SERIAL3_READ__overrun__overrun__VAL REG_VAL_ENUM -#define R_SERIAL3_READ__par_err__par_err__VAL REG_VAL_ENUM -#define R_SERIAL3_READ__framing_err__framing_err__VAL REG_VAL_ENUM -#define R_SERIAL3_READ__data_avail__data_avail__VAL REG_VAL_ENUM -#define R_SERIAL3_READ__data_in__data_in__VAL REG_VAL_VAL - -#define R_SERIAL3_READ__xoff_detect__xoff_detect__no_xoff 0 -#define R_SERIAL3_READ__xoff_detect__xoff_detect__xoff 1 -#define R_SERIAL3_READ__cts___cts___active 0 -#define R_SERIAL3_READ__cts___cts___inactive 1 -#define R_SERIAL3_READ__tr_ready__tr_ready__full 0 -#define R_SERIAL3_READ__tr_ready__tr_ready__ready 1 -#define R_SERIAL3_READ__overrun__overrun__no 0 -#define R_SERIAL3_READ__overrun__overrun__yes 1 -#define R_SERIAL3_READ__par_err__par_err__no 0 -#define R_SERIAL3_READ__par_err__par_err__yes 1 -#define R_SERIAL3_READ__framing_err__framing_err__no 0 -#define R_SERIAL3_READ__framing_err__framing_err__yes 1 -#define R_SERIAL3_READ__data_avail__data_avail__no 0 -#define R_SERIAL3_READ__data_avail__data_avail__yes 1 - -#endif - -/* - * R_SERIAL3_REC_CTRL - * - type: WO - * - addr: 0xb000007a - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -#define R_SERIAL3_REC_CTRL__ADDR (REG_TYPECAST_BYTE 0xb000007a) - -#ifndef REG_NO_SHADOW -#define R_SERIAL3_REC_CTRL__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL3_CTRL + 2)) -#define R_SERIAL3_REC_CTRL__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL3_CTRL + 2)) -#else /* REG_NO_SHADOW */ -#define R_SERIAL3_REC_CTRL__SADDR (REG_STYPECAST_BYTE (®_shadow__hwregs)) -#define R_SERIAL3_REC_CTRL__IADDR (REG_STYPECAST_BYTE (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_SERIAL3_REC_CTRL__STYPECAST REG_STYPECAST_BYTE -#define R_SERIAL3_REC_CTRL__SVAL REG_SVAL_SHADOW -#define R_SERIAL3_REC_CTRL__SVAL_I REG_SVAL_I_SHADOW -#define R_SERIAL3_REC_CTRL__TYPECAST REG_TYPECAST_BYTE -#define R_SERIAL3_REC_CTRL__TYPE (REG_BYTE) -#define R_SERIAL3_REC_CTRL__GET REG_GET_WO -#define R_SERIAL3_REC_CTRL__IGET REG_IGET_WO -#define R_SERIAL3_REC_CTRL__SET REG_SET_WO -#define R_SERIAL3_REC_CTRL__ISET REG_ISET_WO -#define R_SERIAL3_REC_CTRL__SET_VAL REG_SET_VAL_WO -#define R_SERIAL3_REC_CTRL__EQL REG_EQL_WO -#define R_SERIAL3_REC_CTRL__IEQL REG_IEQL_WO -#define R_SERIAL3_REC_CTRL__RD REG_RD_WO -#define R_SERIAL3_REC_CTRL__IRD REG_IRD_WO -#define R_SERIAL3_REC_CTRL__WR REG_WR_WO -#define R_SERIAL3_REC_CTRL__IWR REG_IWR_WO - -#define R_SERIAL3_REC_CTRL__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_SERIAL3_REC_CTRL__dma_err__dma_err__MASK 0x00000080U -#define R_SERIAL3_REC_CTRL__rec_enable__rec_enable__MASK 0x00000040U -#define R_SERIAL3_REC_CTRL__rts___rts___MASK 0x00000020U -#define R_SERIAL3_REC_CTRL__sampling__sampling__MASK 0x00000010U -#define R_SERIAL3_REC_CTRL__rec_stick_par__rec_stick_par__MASK 0x00000008U -#define R_SERIAL3_REC_CTRL__rec_par__rec_par__MASK 0x00000004U -#define R_SERIAL3_REC_CTRL__rec_par_en__rec_par_en__MASK 0x00000002U -#define R_SERIAL3_REC_CTRL__rec_bitnr__rec_bitnr__MASK 0x00000001U - -#define R_SERIAL3_REC_CTRL__dma_err__MAX 0x1 -#define R_SERIAL3_REC_CTRL__rec_enable__MAX 0x1 -#define R_SERIAL3_REC_CTRL__rts___MAX 0x1 -#define R_SERIAL3_REC_CTRL__sampling__MAX 0x1 -#define R_SERIAL3_REC_CTRL__rec_stick_par__MAX 0x1 -#define R_SERIAL3_REC_CTRL__rec_par__MAX 0x1 -#define R_SERIAL3_REC_CTRL__rec_par_en__MAX 0x1 -#define R_SERIAL3_REC_CTRL__rec_bitnr__MAX 0x1 - -#define R_SERIAL3_REC_CTRL__dma_err__MIN 0 -#define R_SERIAL3_REC_CTRL__rec_enable__MIN 0 -#define R_SERIAL3_REC_CTRL__rts___MIN 0 -#define R_SERIAL3_REC_CTRL__sampling__MIN 0 -#define R_SERIAL3_REC_CTRL__rec_stick_par__MIN 0 -#define R_SERIAL3_REC_CTRL__rec_par__MIN 0 -#define R_SERIAL3_REC_CTRL__rec_par_en__MIN 0 -#define R_SERIAL3_REC_CTRL__rec_bitnr__MIN 0 - -#define R_SERIAL3_REC_CTRL__dma_err__BITNR 7 -#define R_SERIAL3_REC_CTRL__rec_enable__BITNR 6 -#define R_SERIAL3_REC_CTRL__rts___BITNR 5 -#define R_SERIAL3_REC_CTRL__sampling__BITNR 4 -#define R_SERIAL3_REC_CTRL__rec_stick_par__BITNR 3 -#define R_SERIAL3_REC_CTRL__rec_par__BITNR 2 -#define R_SERIAL3_REC_CTRL__rec_par_en__BITNR 1 -#define R_SERIAL3_REC_CTRL__rec_bitnr__BITNR 0 - -#define R_SERIAL3_REC_CTRL__dma_err__dma_err__VAL REG_VAL_ENUM -#define R_SERIAL3_REC_CTRL__rec_enable__rec_enable__VAL REG_VAL_ENUM -#define R_SERIAL3_REC_CTRL__rts___rts___VAL REG_VAL_ENUM -#define R_SERIAL3_REC_CTRL__sampling__sampling__VAL REG_VAL_ENUM -#define R_SERIAL3_REC_CTRL__rec_stick_par__rec_stick_par__VAL REG_VAL_ENUM -#define R_SERIAL3_REC_CTRL__rec_par__rec_par__VAL REG_VAL_ENUM -#define R_SERIAL3_REC_CTRL__rec_par_en__rec_par_en__VAL REG_VAL_ENUM -#define R_SERIAL3_REC_CTRL__rec_bitnr__rec_bitnr__VAL REG_VAL_ENUM - -#define R_SERIAL3_REC_CTRL__dma_err__dma_err__ignore 1 -#define R_SERIAL3_REC_CTRL__dma_err__dma_err__stop 0 -#define R_SERIAL3_REC_CTRL__rec_enable__rec_enable__disable 0 -#define R_SERIAL3_REC_CTRL__rec_enable__rec_enable__enable 1 -#define R_SERIAL3_REC_CTRL__rts___rts___active 0 -#define R_SERIAL3_REC_CTRL__rts___rts___inactive 1 -#define R_SERIAL3_REC_CTRL__sampling__sampling__majority 1 -#define R_SERIAL3_REC_CTRL__sampling__sampling__middle 0 -#define R_SERIAL3_REC_CTRL__rec_stick_par__rec_stick_par__normal 0 -#define R_SERIAL3_REC_CTRL__rec_stick_par__rec_stick_par__stick 1 -#define R_SERIAL3_REC_CTRL__rec_par__rec_par__even 0 -#define R_SERIAL3_REC_CTRL__rec_par__rec_par__odd 1 -#define R_SERIAL3_REC_CTRL__rec_par_en__rec_par_en__disable 0 -#define R_SERIAL3_REC_CTRL__rec_par_en__rec_par_en__enable 1 -#define R_SERIAL3_REC_CTRL__rec_bitnr__rec_bitnr__rec_7bit 1 -#define R_SERIAL3_REC_CTRL__rec_bitnr__rec_bitnr__rec_8bit 0 - -#endif - -/* - * R_SERIAL3_REC_DATA - * - type: RO - * - addr: 0xb0000078 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -#define R_SERIAL3_REC_DATA__ADDR (REG_TYPECAST_BYTE 0xb0000078) -#define R_SERIAL3_REC_DATA__SVAL REG_SVAL_SHADOW -#define R_SERIAL3_REC_DATA__SVAL_I REG_SVAL_I_SHADOW -#define R_SERIAL3_REC_DATA__TYPECAST REG_TYPECAST_BYTE -#define R_SERIAL3_REC_DATA__TYPE (REG_BYTE) -#define R_SERIAL3_REC_DATA__GET REG_GET_RO -#define R_SERIAL3_REC_DATA__IGET REG_IGET_RO -#define R_SERIAL3_REC_DATA__SET REG_SET_RO -#define R_SERIAL3_REC_DATA__ISET REG_ISET_RO -#define R_SERIAL3_REC_DATA__SET_VAL REG_SET_VAL_RO -#define R_SERIAL3_REC_DATA__EQL REG_EQL_RO -#define R_SERIAL3_REC_DATA__IEQL REG_IEQL_RO -#define R_SERIAL3_REC_DATA__RD REG_RD_RO -#define R_SERIAL3_REC_DATA__IRD REG_IRD_RO -#define R_SERIAL3_REC_DATA__WR REG_WR_RO -#define R_SERIAL3_REC_DATA__IWR REG_IWR_RO - -#define R_SERIAL3_REC_DATA__READ(addr) \ - (*(addr)) - -#define R_SERIAL3_REC_DATA__data_in__data_in__MASK 0x000000ffU - -#define R_SERIAL3_REC_DATA__data_in__MAX 0xff - -#define R_SERIAL3_REC_DATA__data_in__MIN 0 - -#define R_SERIAL3_REC_DATA__data_in__BITNR 0 - -#define R_SERIAL3_REC_DATA__data_in__data_in__VAL REG_VAL_VAL - - -#endif - -/* - * R_SERIAL3_STATUS - * - type: RO - * - addr: 0xb0000079 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -#define R_SERIAL3_STATUS__ADDR (REG_TYPECAST_BYTE 0xb0000079) -#define R_SERIAL3_STATUS__SVAL REG_SVAL_SHADOW -#define R_SERIAL3_STATUS__SVAL_I REG_SVAL_I_SHADOW -#define R_SERIAL3_STATUS__TYPECAST REG_TYPECAST_BYTE -#define R_SERIAL3_STATUS__TYPE (REG_BYTE) -#define R_SERIAL3_STATUS__GET REG_GET_RO -#define R_SERIAL3_STATUS__IGET REG_IGET_RO -#define R_SERIAL3_STATUS__SET REG_SET_RO -#define R_SERIAL3_STATUS__ISET REG_ISET_RO -#define R_SERIAL3_STATUS__SET_VAL REG_SET_VAL_RO -#define R_SERIAL3_STATUS__EQL REG_EQL_RO -#define R_SERIAL3_STATUS__IEQL REG_IEQL_RO -#define R_SERIAL3_STATUS__RD REG_RD_RO -#define R_SERIAL3_STATUS__IRD REG_IRD_RO -#define R_SERIAL3_STATUS__WR REG_WR_RO -#define R_SERIAL3_STATUS__IWR REG_IWR_RO - -#define R_SERIAL3_STATUS__READ(addr) \ - (*(addr)) - -#define R_SERIAL3_STATUS__xoff_detect__xoff_detect__MASK 0x00000080U -#define R_SERIAL3_STATUS__cts___cts___MASK 0x00000040U -#define R_SERIAL3_STATUS__tr_ready__tr_ready__MASK 0x00000020U -#define R_SERIAL3_STATUS__rxd__rxd__MASK 0x00000010U -#define R_SERIAL3_STATUS__overrun__overrun__MASK 0x00000008U -#define R_SERIAL3_STATUS__par_err__par_err__MASK 0x00000004U -#define R_SERIAL3_STATUS__framing_err__framing_err__MASK 0x00000002U -#define R_SERIAL3_STATUS__data_avail__data_avail__MASK 0x00000001U - -#define R_SERIAL3_STATUS__xoff_detect__MAX 0x1 -#define R_SERIAL3_STATUS__cts___MAX 0x1 -#define R_SERIAL3_STATUS__tr_ready__MAX 0x1 -#define R_SERIAL3_STATUS__rxd__MAX 0x1 -#define R_SERIAL3_STATUS__overrun__MAX 0x1 -#define R_SERIAL3_STATUS__par_err__MAX 0x1 -#define R_SERIAL3_STATUS__framing_err__MAX 0x1 -#define R_SERIAL3_STATUS__data_avail__MAX 0x1 - -#define R_SERIAL3_STATUS__xoff_detect__MIN 0 -#define R_SERIAL3_STATUS__cts___MIN 0 -#define R_SERIAL3_STATUS__tr_ready__MIN 0 -#define R_SERIAL3_STATUS__rxd__MIN 0 -#define R_SERIAL3_STATUS__overrun__MIN 0 -#define R_SERIAL3_STATUS__par_err__MIN 0 -#define R_SERIAL3_STATUS__framing_err__MIN 0 -#define R_SERIAL3_STATUS__data_avail__MIN 0 - -#define R_SERIAL3_STATUS__xoff_detect__BITNR 7 -#define R_SERIAL3_STATUS__cts___BITNR 6 -#define R_SERIAL3_STATUS__tr_ready__BITNR 5 -#define R_SERIAL3_STATUS__rxd__BITNR 4 -#define R_SERIAL3_STATUS__overrun__BITNR 3 -#define R_SERIAL3_STATUS__par_err__BITNR 2 -#define R_SERIAL3_STATUS__framing_err__BITNR 1 -#define R_SERIAL3_STATUS__data_avail__BITNR 0 - -#define R_SERIAL3_STATUS__xoff_detect__xoff_detect__VAL REG_VAL_ENUM -#define R_SERIAL3_STATUS__cts___cts___VAL REG_VAL_ENUM -#define R_SERIAL3_STATUS__tr_ready__tr_ready__VAL REG_VAL_ENUM -#define R_SERIAL3_STATUS__rxd__rxd__VAL REG_VAL_VAL -#define R_SERIAL3_STATUS__overrun__overrun__VAL REG_VAL_ENUM -#define R_SERIAL3_STATUS__par_err__par_err__VAL REG_VAL_ENUM -#define R_SERIAL3_STATUS__framing_err__framing_err__VAL REG_VAL_ENUM -#define R_SERIAL3_STATUS__data_avail__data_avail__VAL REG_VAL_ENUM - -#define R_SERIAL3_STATUS__xoff_detect__xoff_detect__no_xoff 0 -#define R_SERIAL3_STATUS__xoff_detect__xoff_detect__xoff 1 -#define R_SERIAL3_STATUS__cts___cts___active 0 -#define R_SERIAL3_STATUS__cts___cts___inactive 1 -#define R_SERIAL3_STATUS__tr_ready__tr_ready__full 0 -#define R_SERIAL3_STATUS__tr_ready__tr_ready__ready 1 -#define R_SERIAL3_STATUS__overrun__overrun__no 0 -#define R_SERIAL3_STATUS__overrun__overrun__yes 1 -#define R_SERIAL3_STATUS__par_err__par_err__no 0 -#define R_SERIAL3_STATUS__par_err__par_err__yes 1 -#define R_SERIAL3_STATUS__framing_err__framing_err__no 0 -#define R_SERIAL3_STATUS__framing_err__framing_err__yes 1 -#define R_SERIAL3_STATUS__data_avail__data_avail__no 0 -#define R_SERIAL3_STATUS__data_avail__data_avail__yes 1 - -#endif - -/* - * R_SERIAL3_TR_CTRL - * - type: WO - * - addr: 0xb0000079 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -#define R_SERIAL3_TR_CTRL__ADDR (REG_TYPECAST_BYTE 0xb0000079) - -#ifndef REG_NO_SHADOW -#define R_SERIAL3_TR_CTRL__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL3_CTRL + 1)) -#define R_SERIAL3_TR_CTRL__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL3_CTRL + 1)) -#else /* REG_NO_SHADOW */ -#define R_SERIAL3_TR_CTRL__SADDR (REG_STYPECAST_BYTE (®_shadow__hwregs)) -#define R_SERIAL3_TR_CTRL__IADDR (REG_STYPECAST_BYTE (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_SERIAL3_TR_CTRL__STYPECAST REG_STYPECAST_BYTE -#define R_SERIAL3_TR_CTRL__SVAL REG_SVAL_SHADOW -#define R_SERIAL3_TR_CTRL__SVAL_I REG_SVAL_I_SHADOW -#define R_SERIAL3_TR_CTRL__TYPECAST REG_TYPECAST_BYTE -#define R_SERIAL3_TR_CTRL__TYPE (REG_BYTE) -#define R_SERIAL3_TR_CTRL__GET REG_GET_WO -#define R_SERIAL3_TR_CTRL__IGET REG_IGET_WO -#define R_SERIAL3_TR_CTRL__SET REG_SET_WO -#define R_SERIAL3_TR_CTRL__ISET REG_ISET_WO -#define R_SERIAL3_TR_CTRL__SET_VAL REG_SET_VAL_WO -#define R_SERIAL3_TR_CTRL__EQL REG_EQL_WO -#define R_SERIAL3_TR_CTRL__IEQL REG_IEQL_WO -#define R_SERIAL3_TR_CTRL__RD REG_RD_WO -#define R_SERIAL3_TR_CTRL__IRD REG_IRD_WO -#define R_SERIAL3_TR_CTRL__WR REG_WR_WO -#define R_SERIAL3_TR_CTRL__IWR REG_IWR_WO - -#define R_SERIAL3_TR_CTRL__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_SERIAL3_TR_CTRL__txd__txd__MASK 0x00000080U -#define R_SERIAL3_TR_CTRL__tr_enable__tr_enable__MASK 0x00000040U -#define R_SERIAL3_TR_CTRL__auto_cts__auto_cts__MASK 0x00000020U -#define R_SERIAL3_TR_CTRL__stop_bits__stop_bits__MASK 0x00000010U -#define R_SERIAL3_TR_CTRL__tr_stick_par__tr_stick_par__MASK 0x00000008U -#define R_SERIAL3_TR_CTRL__tr_par__tr_par__MASK 0x00000004U -#define R_SERIAL3_TR_CTRL__tr_par_en__tr_par_en__MASK 0x00000002U -#define R_SERIAL3_TR_CTRL__tr_bitnr__tr_bitnr__MASK 0x00000001U - -#define R_SERIAL3_TR_CTRL__txd__MAX 0x1 -#define R_SERIAL3_TR_CTRL__tr_enable__MAX 0x1 -#define R_SERIAL3_TR_CTRL__auto_cts__MAX 0x1 -#define R_SERIAL3_TR_CTRL__stop_bits__MAX 0x1 -#define R_SERIAL3_TR_CTRL__tr_stick_par__MAX 0x1 -#define R_SERIAL3_TR_CTRL__tr_par__MAX 0x1 -#define R_SERIAL3_TR_CTRL__tr_par_en__MAX 0x1 -#define R_SERIAL3_TR_CTRL__tr_bitnr__MAX 0x1 - -#define R_SERIAL3_TR_CTRL__txd__MIN 0 -#define R_SERIAL3_TR_CTRL__tr_enable__MIN 0 -#define R_SERIAL3_TR_CTRL__auto_cts__MIN 0 -#define R_SERIAL3_TR_CTRL__stop_bits__MIN 0 -#define R_SERIAL3_TR_CTRL__tr_stick_par__MIN 0 -#define R_SERIAL3_TR_CTRL__tr_par__MIN 0 -#define R_SERIAL3_TR_CTRL__tr_par_en__MIN 0 -#define R_SERIAL3_TR_CTRL__tr_bitnr__MIN 0 - -#define R_SERIAL3_TR_CTRL__txd__BITNR 7 -#define R_SERIAL3_TR_CTRL__tr_enable__BITNR 6 -#define R_SERIAL3_TR_CTRL__auto_cts__BITNR 5 -#define R_SERIAL3_TR_CTRL__stop_bits__BITNR 4 -#define R_SERIAL3_TR_CTRL__tr_stick_par__BITNR 3 -#define R_SERIAL3_TR_CTRL__tr_par__BITNR 2 -#define R_SERIAL3_TR_CTRL__tr_par_en__BITNR 1 -#define R_SERIAL3_TR_CTRL__tr_bitnr__BITNR 0 - -#define R_SERIAL3_TR_CTRL__txd__txd__VAL REG_VAL_VAL -#define R_SERIAL3_TR_CTRL__tr_enable__tr_enable__VAL REG_VAL_ENUM -#define R_SERIAL3_TR_CTRL__auto_cts__auto_cts__VAL REG_VAL_ENUM -#define R_SERIAL3_TR_CTRL__stop_bits__stop_bits__VAL REG_VAL_ENUM -#define R_SERIAL3_TR_CTRL__tr_stick_par__tr_stick_par__VAL REG_VAL_ENUM -#define R_SERIAL3_TR_CTRL__tr_par__tr_par__VAL REG_VAL_ENUM -#define R_SERIAL3_TR_CTRL__tr_par_en__tr_par_en__VAL REG_VAL_ENUM -#define R_SERIAL3_TR_CTRL__tr_bitnr__tr_bitnr__VAL REG_VAL_ENUM - -#define R_SERIAL3_TR_CTRL__tr_enable__tr_enable__disable 0 -#define R_SERIAL3_TR_CTRL__tr_enable__tr_enable__enable 1 -#define R_SERIAL3_TR_CTRL__auto_cts__auto_cts__active 1 -#define R_SERIAL3_TR_CTRL__auto_cts__auto_cts__disabled 0 -#define R_SERIAL3_TR_CTRL__stop_bits__stop_bits__one_bit 0 -#define R_SERIAL3_TR_CTRL__stop_bits__stop_bits__two_bits 1 -#define R_SERIAL3_TR_CTRL__tr_stick_par__tr_stick_par__normal 0 -#define R_SERIAL3_TR_CTRL__tr_stick_par__tr_stick_par__stick 1 -#define R_SERIAL3_TR_CTRL__tr_par__tr_par__even 0 -#define R_SERIAL3_TR_CTRL__tr_par__tr_par__odd 1 -#define R_SERIAL3_TR_CTRL__tr_par_en__tr_par_en__disable 0 -#define R_SERIAL3_TR_CTRL__tr_par_en__tr_par_en__enable 1 -#define R_SERIAL3_TR_CTRL__tr_bitnr__tr_bitnr__tr_7bit 1 -#define R_SERIAL3_TR_CTRL__tr_bitnr__tr_bitnr__tr_8bit 0 - -#endif - -/* - * R_SERIAL3_TR_DATA - * - type: WO - * - addr: 0xb0000078 - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -#define R_SERIAL3_TR_DATA__ADDR (REG_TYPECAST_BYTE 0xb0000078) - -#ifndef REG_NO_SHADOW -#define R_SERIAL3_TR_DATA__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL3_CTRL + 0)) -#define R_SERIAL3_TR_DATA__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL3_CTRL + 0)) -#else /* REG_NO_SHADOW */ -#define R_SERIAL3_TR_DATA__SADDR (REG_STYPECAST_BYTE (®_shadow__hwregs)) -#define R_SERIAL3_TR_DATA__IADDR (REG_STYPECAST_BYTE (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_SERIAL3_TR_DATA__STYPECAST REG_STYPECAST_BYTE -#define R_SERIAL3_TR_DATA__SVAL REG_SVAL_SHADOW -#define R_SERIAL3_TR_DATA__SVAL_I REG_SVAL_I_SHADOW -#define R_SERIAL3_TR_DATA__TYPECAST REG_TYPECAST_BYTE -#define R_SERIAL3_TR_DATA__TYPE (REG_BYTE) -#define R_SERIAL3_TR_DATA__GET REG_GET_WO -#define R_SERIAL3_TR_DATA__IGET REG_IGET_WO -#define R_SERIAL3_TR_DATA__SET REG_SET_WO -#define R_SERIAL3_TR_DATA__ISET REG_ISET_WO -#define R_SERIAL3_TR_DATA__SET_VAL REG_SET_VAL_WO -#define R_SERIAL3_TR_DATA__EQL REG_EQL_WO -#define R_SERIAL3_TR_DATA__IEQL REG_IEQL_WO -#define R_SERIAL3_TR_DATA__RD REG_RD_WO -#define R_SERIAL3_TR_DATA__IRD REG_IRD_WO -#define R_SERIAL3_TR_DATA__WR REG_WR_WO -#define R_SERIAL3_TR_DATA__IWR REG_IWR_WO - -#define R_SERIAL3_TR_DATA__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_SERIAL3_TR_DATA__data_out__data_out__MASK 0x000000ffU - -#define R_SERIAL3_TR_DATA__data_out__MAX 0xff - -#define R_SERIAL3_TR_DATA__data_out__MIN 0 - -#define R_SERIAL3_TR_DATA__data_out__BITNR 0 - -#define R_SERIAL3_TR_DATA__data_out__data_out__VAL REG_VAL_VAL - - -#endif - -/* - * R_SERIAL3_XOFF - * - type: WO - * - addr: 0xb000007c - * - group: Serial port registers - */ - -#if USE_GROUP__Serial_port_registers - -#define R_SERIAL3_XOFF__ADDR (REG_TYPECAST_UDWORD 0xb000007c) - -#ifndef REG_NO_SHADOW -#define R_SERIAL3_XOFF__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_SERIAL3_XOFF + 0)) -#define R_SERIAL3_XOFF__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_SERIAL3_XOFF + 0)) -#else /* REG_NO_SHADOW */ -#define R_SERIAL3_XOFF__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_SERIAL3_XOFF__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_SERIAL3_XOFF__STYPECAST REG_STYPECAST_UDWORD -#define R_SERIAL3_XOFF__SVAL REG_SVAL_SHADOW -#define R_SERIAL3_XOFF__SVAL_I REG_SVAL_I_SHADOW -#define R_SERIAL3_XOFF__TYPECAST REG_TYPECAST_UDWORD -#define R_SERIAL3_XOFF__TYPE (REG_UDWORD) -#define R_SERIAL3_XOFF__GET REG_GET_WO -#define R_SERIAL3_XOFF__IGET REG_IGET_WO -#define R_SERIAL3_XOFF__SET REG_SET_WO -#define R_SERIAL3_XOFF__ISET REG_ISET_WO -#define R_SERIAL3_XOFF__SET_VAL REG_SET_VAL_WO -#define R_SERIAL3_XOFF__EQL REG_EQL_WO -#define R_SERIAL3_XOFF__IEQL REG_IEQL_WO -#define R_SERIAL3_XOFF__RD REG_RD_WO -#define R_SERIAL3_XOFF__IRD REG_IRD_WO -#define R_SERIAL3_XOFF__WR REG_WR_WO -#define R_SERIAL3_XOFF__IWR REG_IWR_WO - -#define R_SERIAL3_XOFF__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_SERIAL3_XOFF__tx_stop__tx_stop__MASK 0x00000200U -#define R_SERIAL3_XOFF__auto_xoff__auto_xoff__MASK 0x00000100U -#define R_SERIAL3_XOFF__xoff_char__xoff_char__MASK 0x000000ffU - -#define R_SERIAL3_XOFF__tx_stop__MAX 0x1 -#define R_SERIAL3_XOFF__auto_xoff__MAX 0x1 -#define R_SERIAL3_XOFF__xoff_char__MAX 0xff - -#define R_SERIAL3_XOFF__tx_stop__MIN 0 -#define R_SERIAL3_XOFF__auto_xoff__MIN 0 -#define R_SERIAL3_XOFF__xoff_char__MIN 0 - -#define R_SERIAL3_XOFF__tx_stop__BITNR 9 -#define R_SERIAL3_XOFF__auto_xoff__BITNR 8 -#define R_SERIAL3_XOFF__xoff_char__BITNR 0 - -#define R_SERIAL3_XOFF__tx_stop__tx_stop__VAL REG_VAL_ENUM -#define R_SERIAL3_XOFF__auto_xoff__auto_xoff__VAL REG_VAL_ENUM -#define R_SERIAL3_XOFF__xoff_char__xoff_char__VAL REG_VAL_VAL - -#define R_SERIAL3_XOFF__tx_stop__tx_stop__enable 0 -#define R_SERIAL3_XOFF__tx_stop__tx_stop__stop 1 -#define R_SERIAL3_XOFF__auto_xoff__auto_xoff__disable 0 -#define R_SERIAL3_XOFF__auto_xoff__auto_xoff__enable 1 - -#endif - -/* - * R_SERIAL_PRESCALE - * - type: WO - * - addr: 0xb00000f2 - * - group: Timer registers - */ - -#if USE_GROUP__Timer_registers - -#define R_SERIAL_PRESCALE__ADDR (REG_TYPECAST_UWORD 0xb00000f2) - -#ifndef REG_NO_SHADOW -#define R_SERIAL_PRESCALE__SADDR (REG_STYPECAST_UWORD (reg_shadow__hwregs.R_CLOCK_PRESCALE + 2)) -#define R_SERIAL_PRESCALE__IADDR (REG_STYPECAST_UWORD (reg_initiated__hwregs.R_CLOCK_PRESCALE + 2)) -#else /* REG_NO_SHADOW */ -#define R_SERIAL_PRESCALE__SADDR (REG_STYPECAST_UWORD (®_shadow__hwregs)) -#define R_SERIAL_PRESCALE__IADDR (REG_STYPECAST_UWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_SERIAL_PRESCALE__STYPECAST REG_STYPECAST_UWORD -#define R_SERIAL_PRESCALE__SVAL REG_SVAL_SHADOW -#define R_SERIAL_PRESCALE__SVAL_I REG_SVAL_I_SHADOW -#define R_SERIAL_PRESCALE__TYPECAST REG_TYPECAST_UWORD -#define R_SERIAL_PRESCALE__TYPE (REG_UWORD) -#define R_SERIAL_PRESCALE__GET REG_GET_WO -#define R_SERIAL_PRESCALE__IGET REG_IGET_WO -#define R_SERIAL_PRESCALE__SET REG_SET_WO -#define R_SERIAL_PRESCALE__ISET REG_ISET_WO -#define R_SERIAL_PRESCALE__SET_VAL REG_SET_VAL_WO -#define R_SERIAL_PRESCALE__EQL REG_EQL_WO -#define R_SERIAL_PRESCALE__IEQL REG_IEQL_WO -#define R_SERIAL_PRESCALE__RD REG_RD_WO -#define R_SERIAL_PRESCALE__IRD REG_IRD_WO -#define R_SERIAL_PRESCALE__WR REG_WR_WO -#define R_SERIAL_PRESCALE__IWR REG_IWR_WO - -#define R_SERIAL_PRESCALE__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_SERIAL_PRESCALE__ser_presc__ser_presc__MASK 0x0000ffffU - -#define R_SERIAL_PRESCALE__ser_presc__MAX 0xffff - -#define R_SERIAL_PRESCALE__ser_presc__MIN 0 - -#define R_SERIAL_PRESCALE__ser_presc__BITNR 0 - -#define R_SERIAL_PRESCALE__ser_presc__ser_presc__VAL REG_VAL_VAL - - -#endif - -/* - * R_SER_PRESC_STATUS - * - type: RO - * - addr: 0xb00000f2 - * - group: Timer registers - */ - -#if USE_GROUP__Timer_registers - -#define R_SER_PRESC_STATUS__ADDR (REG_TYPECAST_UWORD 0xb00000f2) -#define R_SER_PRESC_STATUS__SVAL REG_SVAL_SHADOW -#define R_SER_PRESC_STATUS__SVAL_I REG_SVAL_I_SHADOW -#define R_SER_PRESC_STATUS__TYPECAST REG_TYPECAST_UWORD -#define R_SER_PRESC_STATUS__TYPE (REG_UWORD) -#define R_SER_PRESC_STATUS__GET REG_GET_RO -#define R_SER_PRESC_STATUS__IGET REG_IGET_RO -#define R_SER_PRESC_STATUS__SET REG_SET_RO -#define R_SER_PRESC_STATUS__ISET REG_ISET_RO -#define R_SER_PRESC_STATUS__SET_VAL REG_SET_VAL_RO -#define R_SER_PRESC_STATUS__EQL REG_EQL_RO -#define R_SER_PRESC_STATUS__IEQL REG_IEQL_RO -#define R_SER_PRESC_STATUS__RD REG_RD_RO -#define R_SER_PRESC_STATUS__IRD REG_IRD_RO -#define R_SER_PRESC_STATUS__WR REG_WR_RO -#define R_SER_PRESC_STATUS__IWR REG_IWR_RO - -#define R_SER_PRESC_STATUS__READ(addr) \ - (*(addr)) - -#define R_SER_PRESC_STATUS__ser_status__ser_status__MASK 0x0000ffffU - -#define R_SER_PRESC_STATUS__ser_status__MAX 0xffff - -#define R_SER_PRESC_STATUS__ser_status__MIN 0 - -#define R_SER_PRESC_STATUS__ser_status__BITNR 0 - -#define R_SER_PRESC_STATUS__ser_status__ser_status__VAL REG_VAL_VAL - - -#endif - -/* - * R_SET_EOP - * - type: WO - * - addr: 0xb000003c - * - group: DMA registers - */ - -#if USE_GROUP__DMA_registers - -#define R_SET_EOP__ADDR (REG_TYPECAST_UDWORD 0xb000003c) - -#ifndef REG_NO_SHADOW -#define R_SET_EOP__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_SET_EOP + 0)) -#define R_SET_EOP__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_SET_EOP + 0)) -#else /* REG_NO_SHADOW */ -#define R_SET_EOP__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_SET_EOP__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_SET_EOP__STYPECAST REG_STYPECAST_UDWORD -#define R_SET_EOP__SVAL REG_SVAL_ZERO -#define R_SET_EOP__SVAL_I REG_SVAL_I_ZERO -#define R_SET_EOP__TYPECAST REG_TYPECAST_UDWORD -#define R_SET_EOP__TYPE (REG_UDWORD) -#define R_SET_EOP__GET REG_GET_WO -#define R_SET_EOP__IGET REG_IGET_WO -#define R_SET_EOP__SET REG_SET_WO -#define R_SET_EOP__ISET REG_ISET_WO -#define R_SET_EOP__SET_VAL REG_SET_VAL_WO -#define R_SET_EOP__EQL REG_EQL_WO -#define R_SET_EOP__IEQL REG_IEQL_WO -#define R_SET_EOP__RD REG_RD_WO -#define R_SET_EOP__IRD REG_IRD_WO -#define R_SET_EOP__WR REG_WR_WO -#define R_SET_EOP__IWR REG_IWR_WO - -#define R_SET_EOP__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_SET_EOP__ch9_eop__ch9_eop__MASK 0x00000008U -#define R_SET_EOP__ch7_eop__ch7_eop__MASK 0x00000004U -#define R_SET_EOP__ch5_eop__ch5_eop__MASK 0x00000002U -#define R_SET_EOP__ch3_eop__ch3_eop__MASK 0x00000001U - -#define R_SET_EOP__ch9_eop__MAX 0x1 -#define R_SET_EOP__ch7_eop__MAX 0x1 -#define R_SET_EOP__ch5_eop__MAX 0x1 -#define R_SET_EOP__ch3_eop__MAX 0x1 - -#define R_SET_EOP__ch9_eop__MIN 0 -#define R_SET_EOP__ch7_eop__MIN 0 -#define R_SET_EOP__ch5_eop__MIN 0 -#define R_SET_EOP__ch3_eop__MIN 0 - -#define R_SET_EOP__ch9_eop__BITNR 3 -#define R_SET_EOP__ch7_eop__BITNR 2 -#define R_SET_EOP__ch5_eop__BITNR 1 -#define R_SET_EOP__ch3_eop__BITNR 0 - -#define R_SET_EOP__ch9_eop__ch9_eop__VAL REG_VAL_ENUM -#define R_SET_EOP__ch7_eop__ch7_eop__VAL REG_VAL_ENUM -#define R_SET_EOP__ch5_eop__ch5_eop__VAL REG_VAL_ENUM -#define R_SET_EOP__ch3_eop__ch3_eop__VAL REG_VAL_ENUM - -#define R_SET_EOP__ch9_eop__ch9_eop__nop 0 -#define R_SET_EOP__ch9_eop__ch9_eop__set 1 -#define R_SET_EOP__ch7_eop__ch7_eop__nop 0 -#define R_SET_EOP__ch7_eop__ch7_eop__set 1 -#define R_SET_EOP__ch5_eop__ch5_eop__nop 0 -#define R_SET_EOP__ch5_eop__ch5_eop__set 1 -#define R_SET_EOP__ch3_eop__ch3_eop__nop 0 -#define R_SET_EOP__ch3_eop__ch3_eop__set 1 - -#endif - -/* - * R_SHARED_RAM_ADDR - * - type: WO - * - addr: 0xb0000044 - * - group: Shared RAM interface registers - */ - -#if USE_GROUP__Shared_RAM_interface_registers - -#define R_SHARED_RAM_ADDR__ADDR (REG_TYPECAST_UDWORD 0xb0000044) - -#ifndef REG_NO_SHADOW -#define R_SHARED_RAM_ADDR__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_ATA_CONFIG + 0)) -#define R_SHARED_RAM_ADDR__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_ATA_CONFIG + 0)) -#else /* REG_NO_SHADOW */ -#define R_SHARED_RAM_ADDR__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_SHARED_RAM_ADDR__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_SHARED_RAM_ADDR__STYPECAST REG_STYPECAST_UDWORD -#define R_SHARED_RAM_ADDR__SVAL REG_SVAL_SHADOW -#define R_SHARED_RAM_ADDR__SVAL_I REG_SVAL_I_SHADOW -#define R_SHARED_RAM_ADDR__TYPECAST REG_TYPECAST_UDWORD -#define R_SHARED_RAM_ADDR__TYPE (REG_UDWORD) -#define R_SHARED_RAM_ADDR__GET REG_GET_WO -#define R_SHARED_RAM_ADDR__IGET REG_IGET_WO -#define R_SHARED_RAM_ADDR__SET REG_SET_WO -#define R_SHARED_RAM_ADDR__ISET REG_ISET_WO -#define R_SHARED_RAM_ADDR__SET_VAL REG_SET_VAL_WO -#define R_SHARED_RAM_ADDR__EQL REG_EQL_WO -#define R_SHARED_RAM_ADDR__IEQL REG_IEQL_WO -#define R_SHARED_RAM_ADDR__RD REG_RD_WO -#define R_SHARED_RAM_ADDR__IRD REG_IRD_WO -#define R_SHARED_RAM_ADDR__WR REG_WR_WO -#define R_SHARED_RAM_ADDR__IWR REG_IWR_WO - -#define R_SHARED_RAM_ADDR__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_SHARED_RAM_ADDR__base_addr__base_addr__MASK 0x3fffff00U - -#define R_SHARED_RAM_ADDR__base_addr__MAX 0x3fffff - -#define R_SHARED_RAM_ADDR__base_addr__MIN 0 - -#define R_SHARED_RAM_ADDR__base_addr__BITNR 8 - -#define R_SHARED_RAM_ADDR__base_addr__base_addr__VAL REG_VAL_VAL - - -#endif - -/* - * R_SHARED_RAM_CONFIG - * - type: WO - * - addr: 0xb0000040 - * - group: Shared RAM interface registers - */ - -#if USE_GROUP__Shared_RAM_interface_registers - -#define R_SHARED_RAM_CONFIG__ADDR (REG_TYPECAST_UDWORD 0xb0000040) - -#ifndef REG_NO_SHADOW -#define R_SHARED_RAM_CONFIG__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_ATA_CTRL_DATA + 0)) -#define R_SHARED_RAM_CONFIG__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_ATA_CTRL_DATA + 0)) -#else /* REG_NO_SHADOW */ -#define R_SHARED_RAM_CONFIG__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_SHARED_RAM_CONFIG__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_SHARED_RAM_CONFIG__STYPECAST REG_STYPECAST_UDWORD -#define R_SHARED_RAM_CONFIG__SVAL REG_SVAL_SHADOW -#define R_SHARED_RAM_CONFIG__SVAL_I REG_SVAL_I_SHADOW -#define R_SHARED_RAM_CONFIG__TYPECAST REG_TYPECAST_UDWORD -#define R_SHARED_RAM_CONFIG__TYPE (REG_UDWORD) -#define R_SHARED_RAM_CONFIG__GET REG_GET_WO -#define R_SHARED_RAM_CONFIG__IGET REG_IGET_WO -#define R_SHARED_RAM_CONFIG__SET REG_SET_WO -#define R_SHARED_RAM_CONFIG__ISET REG_ISET_WO -#define R_SHARED_RAM_CONFIG__SET_VAL REG_SET_VAL_WO -#define R_SHARED_RAM_CONFIG__EQL REG_EQL_WO -#define R_SHARED_RAM_CONFIG__IEQL REG_IEQL_WO -#define R_SHARED_RAM_CONFIG__RD REG_RD_WO -#define R_SHARED_RAM_CONFIG__IRD REG_IRD_WO -#define R_SHARED_RAM_CONFIG__WR REG_WR_WO -#define R_SHARED_RAM_CONFIG__IWR REG_IWR_WO - -#define R_SHARED_RAM_CONFIG__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_SHARED_RAM_CONFIG__width__width__MASK 0x00000008U -#define R_SHARED_RAM_CONFIG__enable__enable__MASK 0x00000004U -#define R_SHARED_RAM_CONFIG__pint__pint__MASK 0x00000002U -#define R_SHARED_RAM_CONFIG__clri__clri__MASK 0x00000001U - -#define R_SHARED_RAM_CONFIG__width__MAX 0x1 -#define R_SHARED_RAM_CONFIG__enable__MAX 0x1 -#define R_SHARED_RAM_CONFIG__pint__MAX 0x1 -#define R_SHARED_RAM_CONFIG__clri__MAX 0x1 - -#define R_SHARED_RAM_CONFIG__width__MIN 0 -#define R_SHARED_RAM_CONFIG__enable__MIN 0 -#define R_SHARED_RAM_CONFIG__pint__MIN 0 -#define R_SHARED_RAM_CONFIG__clri__MIN 0 - -#define R_SHARED_RAM_CONFIG__width__BITNR 3 -#define R_SHARED_RAM_CONFIG__enable__BITNR 2 -#define R_SHARED_RAM_CONFIG__pint__BITNR 1 -#define R_SHARED_RAM_CONFIG__clri__BITNR 0 - -#define R_SHARED_RAM_CONFIG__width__width__VAL REG_VAL_ENUM -#define R_SHARED_RAM_CONFIG__enable__enable__VAL REG_VAL_ENUM -#define R_SHARED_RAM_CONFIG__pint__pint__VAL REG_VAL_ENUM -#define R_SHARED_RAM_CONFIG__clri__clri__VAL REG_VAL_ENUM - -#define R_SHARED_RAM_CONFIG__width__width__byte 0 -#define R_SHARED_RAM_CONFIG__width__width__word 1 -#define R_SHARED_RAM_CONFIG__enable__enable__no 0 -#define R_SHARED_RAM_CONFIG__enable__enable__yes 1 -#define R_SHARED_RAM_CONFIG__pint__pint__int 1 -#define R_SHARED_RAM_CONFIG__pint__pint__nop 0 -#define R_SHARED_RAM_CONFIG__clri__clri__clr 1 -#define R_SHARED_RAM_CONFIG__clri__clri__nop 0 - -#endif - -/* - * R_SINGLE_STEP - * - type: WO - * - addr: 0xb00000fe - * - group: Test mode registers - */ - -#if USE_GROUP__Test_mode_registers - -#define R_SINGLE_STEP__ADDR (REG_TYPECAST_BYTE 0xb00000fe) - -#ifndef REG_NO_SHADOW -#define R_SINGLE_STEP__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_TEST_MODE + 2)) -#define R_SINGLE_STEP__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_TEST_MODE + 2)) -#else /* REG_NO_SHADOW */ -#define R_SINGLE_STEP__SADDR (REG_STYPECAST_BYTE (®_shadow__hwregs)) -#define R_SINGLE_STEP__IADDR (REG_STYPECAST_BYTE (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_SINGLE_STEP__STYPECAST REG_STYPECAST_BYTE -#define R_SINGLE_STEP__SVAL REG_SVAL_SHADOW -#define R_SINGLE_STEP__SVAL_I REG_SVAL_I_SHADOW -#define R_SINGLE_STEP__TYPECAST REG_TYPECAST_BYTE -#define R_SINGLE_STEP__TYPE (REG_BYTE) -#define R_SINGLE_STEP__GET REG_GET_WO -#define R_SINGLE_STEP__IGET REG_IGET_WO -#define R_SINGLE_STEP__SET REG_SET_WO -#define R_SINGLE_STEP__ISET REG_ISET_WO -#define R_SINGLE_STEP__SET_VAL REG_SET_VAL_WO -#define R_SINGLE_STEP__EQL REG_EQL_WO -#define R_SINGLE_STEP__IEQL REG_IEQL_WO -#define R_SINGLE_STEP__RD REG_RD_WO -#define R_SINGLE_STEP__IRD REG_IRD_WO -#define R_SINGLE_STEP__WR REG_WR_WO -#define R_SINGLE_STEP__IWR REG_IWR_WO - -#define R_SINGLE_STEP__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_SINGLE_STEP__single_step__single_step__MASK 0x00000008U -#define R_SINGLE_STEP__step_wr__step_wr__MASK 0x00000004U -#define R_SINGLE_STEP__step_rd__step_rd__MASK 0x00000002U -#define R_SINGLE_STEP__step_fetch__step_fetch__MASK 0x00000001U - -#define R_SINGLE_STEP__single_step__MAX 0x1 -#define R_SINGLE_STEP__step_wr__MAX 0x1 -#define R_SINGLE_STEP__step_rd__MAX 0x1 -#define R_SINGLE_STEP__step_fetch__MAX 0x1 - -#define R_SINGLE_STEP__single_step__MIN 0 -#define R_SINGLE_STEP__step_wr__MIN 0 -#define R_SINGLE_STEP__step_rd__MIN 0 -#define R_SINGLE_STEP__step_fetch__MIN 0 - -#define R_SINGLE_STEP__single_step__BITNR 3 -#define R_SINGLE_STEP__step_wr__BITNR 2 -#define R_SINGLE_STEP__step_rd__BITNR 1 -#define R_SINGLE_STEP__step_fetch__BITNR 0 - -#define R_SINGLE_STEP__single_step__single_step__VAL REG_VAL_ENUM -#define R_SINGLE_STEP__step_wr__step_wr__VAL REG_VAL_ENUM -#define R_SINGLE_STEP__step_rd__step_rd__VAL REG_VAL_ENUM -#define R_SINGLE_STEP__step_fetch__step_fetch__VAL REG_VAL_ENUM - -#define R_SINGLE_STEP__single_step__single_step__off 0 -#define R_SINGLE_STEP__single_step__single_step__on 1 -#define R_SINGLE_STEP__step_wr__step_wr__off 0 -#define R_SINGLE_STEP__step_wr__step_wr__on 1 -#define R_SINGLE_STEP__step_rd__step_rd__off 0 -#define R_SINGLE_STEP__step_rd__step_rd__on 1 -#define R_SINGLE_STEP__step_fetch__step_fetch__off 0 -#define R_SINGLE_STEP__step_fetch__step_fetch__on 1 - -#endif - -/* - * R_SYNC_SERIAL1_CTRL - * - type: WO - * - addr: 0xb0000068 - * - group: Syncrounous serial port registers - */ - -#if USE_GROUP__Syncrounous_serial_port_registers - -#define R_SYNC_SERIAL1_CTRL__ADDR (REG_TYPECAST_UDWORD 0xb0000068) - -#ifndef REG_NO_SHADOW -#define R_SYNC_SERIAL1_CTRL__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_SERIAL1_CTRL + 0)) -#define R_SYNC_SERIAL1_CTRL__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_SERIAL1_CTRL + 0)) -#else /* REG_NO_SHADOW */ -#define R_SYNC_SERIAL1_CTRL__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_SYNC_SERIAL1_CTRL__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_SYNC_SERIAL1_CTRL__STYPECAST REG_STYPECAST_UDWORD -#define R_SYNC_SERIAL1_CTRL__SVAL REG_SVAL_SHADOW -#define R_SYNC_SERIAL1_CTRL__SVAL_I REG_SVAL_I_SHADOW -#define R_SYNC_SERIAL1_CTRL__TYPECAST REG_TYPECAST_UDWORD -#define R_SYNC_SERIAL1_CTRL__TYPE (REG_UDWORD) -#define R_SYNC_SERIAL1_CTRL__GET REG_GET_WO -#define R_SYNC_SERIAL1_CTRL__IGET REG_IGET_WO -#define R_SYNC_SERIAL1_CTRL__SET REG_SET_WO -#define R_SYNC_SERIAL1_CTRL__ISET REG_ISET_WO -#define R_SYNC_SERIAL1_CTRL__SET_VAL REG_SET_VAL_WO -#define R_SYNC_SERIAL1_CTRL__EQL REG_EQL_WO -#define R_SYNC_SERIAL1_CTRL__IEQL REG_IEQL_WO -#define R_SYNC_SERIAL1_CTRL__RD REG_RD_WO -#define R_SYNC_SERIAL1_CTRL__IRD REG_IRD_WO -#define R_SYNC_SERIAL1_CTRL__WR REG_WR_WO -#define R_SYNC_SERIAL1_CTRL__IWR REG_IWR_WO - -#define R_SYNC_SERIAL1_CTRL__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_SYNC_SERIAL1_CTRL__tr_baud__tr_baud__MASK 0xf0000000U -#define R_SYNC_SERIAL1_CTRL__dma_enable__dma_enable__MASK 0x08000000U -#define R_SYNC_SERIAL1_CTRL__mode__mode__MASK 0x07000000U -#define R_SYNC_SERIAL1_CTRL__error__error__MASK 0x00800000U -#define R_SYNC_SERIAL1_CTRL__rec_enable__rec_enable__MASK 0x00400000U -#define R_SYNC_SERIAL1_CTRL__f_synctype__f_synctype__MASK 0x00200000U -#define R_SYNC_SERIAL1_CTRL__f_syncsize__f_syncsize__MASK 0x00180000U -#define R_SYNC_SERIAL1_CTRL__f_sync__f_sync__MASK 0x00040000U -#define R_SYNC_SERIAL1_CTRL__clk_mode__clk_mode__MASK 0x00020000U -#define R_SYNC_SERIAL1_CTRL__clk_halt__clk_halt__MASK 0x00010000U -#define R_SYNC_SERIAL1_CTRL__bitorder__bitorder__MASK 0x00008000U -#define R_SYNC_SERIAL1_CTRL__tr_enable__tr_enable__MASK 0x00004000U -#define R_SYNC_SERIAL1_CTRL__wordsize__wordsize__MASK 0x00003800U -#define R_SYNC_SERIAL1_CTRL__buf_empty__buf_empty__MASK 0x00000400U -#define R_SYNC_SERIAL1_CTRL__buf_full__buf_full__MASK 0x00000200U -#define R_SYNC_SERIAL1_CTRL__flow_ctrl__flow_ctrl__MASK 0x00000100U -#define R_SYNC_SERIAL1_CTRL__clk_polarity__clk_polarity__MASK 0x00000040U -#define R_SYNC_SERIAL1_CTRL__frame_polarity__frame_polarity__MASK 0x00000020U -#define R_SYNC_SERIAL1_CTRL__status_polarity__status_polarity__MASK 0x00000010U -#define R_SYNC_SERIAL1_CTRL__clk_driver__clk_driver__MASK 0x00000008U -#define R_SYNC_SERIAL1_CTRL__frame_driver__frame_driver__MASK 0x00000004U -#define R_SYNC_SERIAL1_CTRL__status_driver__status_driver__MASK 0x00000002U -#define R_SYNC_SERIAL1_CTRL__def_out0__def_out0__MASK 0x00000001U - -#define R_SYNC_SERIAL1_CTRL__tr_baud__MAX 0xf -#define R_SYNC_SERIAL1_CTRL__dma_enable__MAX 0x1 -#define R_SYNC_SERIAL1_CTRL__mode__MAX 0x7 -#define R_SYNC_SERIAL1_CTRL__error__MAX 0x1 -#define R_SYNC_SERIAL1_CTRL__rec_enable__MAX 0x1 -#define R_SYNC_SERIAL1_CTRL__f_synctype__MAX 0x1 -#define R_SYNC_SERIAL1_CTRL__f_syncsize__MAX 0x3 -#define R_SYNC_SERIAL1_CTRL__f_sync__MAX 0x1 -#define R_SYNC_SERIAL1_CTRL__clk_mode__MAX 0x1 -#define R_SYNC_SERIAL1_CTRL__clk_halt__MAX 0x1 -#define R_SYNC_SERIAL1_CTRL__bitorder__MAX 0x1 -#define R_SYNC_SERIAL1_CTRL__tr_enable__MAX 0x1 -#define R_SYNC_SERIAL1_CTRL__wordsize__MAX 0x7 -#define R_SYNC_SERIAL1_CTRL__buf_empty__MAX 0x1 -#define R_SYNC_SERIAL1_CTRL__buf_full__MAX 0x1 -#define R_SYNC_SERIAL1_CTRL__flow_ctrl__MAX 0x1 -#define R_SYNC_SERIAL1_CTRL__clk_polarity__MAX 0x1 -#define R_SYNC_SERIAL1_CTRL__frame_polarity__MAX 0x1 -#define R_SYNC_SERIAL1_CTRL__status_polarity__MAX 0x1 -#define R_SYNC_SERIAL1_CTRL__clk_driver__MAX 0x1 -#define R_SYNC_SERIAL1_CTRL__frame_driver__MAX 0x1 -#define R_SYNC_SERIAL1_CTRL__status_driver__MAX 0x1 -#define R_SYNC_SERIAL1_CTRL__def_out0__MAX 0x1 - -#define R_SYNC_SERIAL1_CTRL__tr_baud__MIN 0 -#define R_SYNC_SERIAL1_CTRL__dma_enable__MIN 0 -#define R_SYNC_SERIAL1_CTRL__mode__MIN 0 -#define R_SYNC_SERIAL1_CTRL__error__MIN 0 -#define R_SYNC_SERIAL1_CTRL__rec_enable__MIN 0 -#define R_SYNC_SERIAL1_CTRL__f_synctype__MIN 0 -#define R_SYNC_SERIAL1_CTRL__f_syncsize__MIN 0 -#define R_SYNC_SERIAL1_CTRL__f_sync__MIN 0 -#define R_SYNC_SERIAL1_CTRL__clk_mode__MIN 0 -#define R_SYNC_SERIAL1_CTRL__clk_halt__MIN 0 -#define R_SYNC_SERIAL1_CTRL__bitorder__MIN 0 -#define R_SYNC_SERIAL1_CTRL__tr_enable__MIN 0 -#define R_SYNC_SERIAL1_CTRL__wordsize__MIN 0 -#define R_SYNC_SERIAL1_CTRL__buf_empty__MIN 0 -#define R_SYNC_SERIAL1_CTRL__buf_full__MIN 0 -#define R_SYNC_SERIAL1_CTRL__flow_ctrl__MIN 0 -#define R_SYNC_SERIAL1_CTRL__clk_polarity__MIN 0 -#define R_SYNC_SERIAL1_CTRL__frame_polarity__MIN 0 -#define R_SYNC_SERIAL1_CTRL__status_polarity__MIN 0 -#define R_SYNC_SERIAL1_CTRL__clk_driver__MIN 0 -#define R_SYNC_SERIAL1_CTRL__frame_driver__MIN 0 -#define R_SYNC_SERIAL1_CTRL__status_driver__MIN 0 -#define R_SYNC_SERIAL1_CTRL__def_out0__MIN 0 - -#define R_SYNC_SERIAL1_CTRL__tr_baud__BITNR 28 -#define R_SYNC_SERIAL1_CTRL__dma_enable__BITNR 27 -#define R_SYNC_SERIAL1_CTRL__mode__BITNR 24 -#define R_SYNC_SERIAL1_CTRL__error__BITNR 23 -#define R_SYNC_SERIAL1_CTRL__rec_enable__BITNR 22 -#define R_SYNC_SERIAL1_CTRL__f_synctype__BITNR 21 -#define R_SYNC_SERIAL1_CTRL__f_syncsize__BITNR 19 -#define R_SYNC_SERIAL1_CTRL__f_sync__BITNR 18 -#define R_SYNC_SERIAL1_CTRL__clk_mode__BITNR 17 -#define R_SYNC_SERIAL1_CTRL__clk_halt__BITNR 16 -#define R_SYNC_SERIAL1_CTRL__bitorder__BITNR 15 -#define R_SYNC_SERIAL1_CTRL__tr_enable__BITNR 14 -#define R_SYNC_SERIAL1_CTRL__wordsize__BITNR 11 -#define R_SYNC_SERIAL1_CTRL__buf_empty__BITNR 10 -#define R_SYNC_SERIAL1_CTRL__buf_full__BITNR 9 -#define R_SYNC_SERIAL1_CTRL__flow_ctrl__BITNR 8 -#define R_SYNC_SERIAL1_CTRL__clk_polarity__BITNR 6 -#define R_SYNC_SERIAL1_CTRL__frame_polarity__BITNR 5 -#define R_SYNC_SERIAL1_CTRL__status_polarity__BITNR 4 -#define R_SYNC_SERIAL1_CTRL__clk_driver__BITNR 3 -#define R_SYNC_SERIAL1_CTRL__frame_driver__BITNR 2 -#define R_SYNC_SERIAL1_CTRL__status_driver__BITNR 1 -#define R_SYNC_SERIAL1_CTRL__def_out0__BITNR 0 - -#define R_SYNC_SERIAL1_CTRL__tr_baud__tr_baud__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL1_CTRL__dma_enable__dma_enable__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL1_CTRL__mode__mode__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL1_CTRL__error__error__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL1_CTRL__rec_enable__rec_enable__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL1_CTRL__f_synctype__f_synctype__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL1_CTRL__f_syncsize__f_syncsize__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL1_CTRL__f_sync__f_sync__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL1_CTRL__clk_mode__clk_mode__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL1_CTRL__clk_halt__clk_halt__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL1_CTRL__bitorder__bitorder__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL1_CTRL__tr_enable__tr_enable__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL1_CTRL__wordsize__wordsize__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL1_CTRL__buf_empty__buf_empty__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL1_CTRL__buf_full__buf_full__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL1_CTRL__flow_ctrl__flow_ctrl__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL1_CTRL__clk_polarity__clk_polarity__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL1_CTRL__frame_polarity__frame_polarity__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL1_CTRL__status_polarity__status_polarity__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL1_CTRL__clk_driver__clk_driver__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL1_CTRL__frame_driver__frame_driver__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL1_CTRL__status_driver__status_driver__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL1_CTRL__def_out0__def_out0__VAL REG_VAL_ENUM - -#define R_SYNC_SERIAL1_CTRL__tr_baud__tr_baud__c115k2Hz 10 -#define R_SYNC_SERIAL1_CTRL__tr_baud__tr_baud__c1200Hz 3 -#define R_SYNC_SERIAL1_CTRL__tr_baud__tr_baud__c150Hz 0 -#define R_SYNC_SERIAL1_CTRL__tr_baud__tr_baud__c19k2Hz 7 -#define R_SYNC_SERIAL1_CTRL__tr_baud__tr_baud__c230k4Hz 11 -#define R_SYNC_SERIAL1_CTRL__tr_baud__tr_baud__c2400Hz 4 -#define R_SYNC_SERIAL1_CTRL__tr_baud__tr_baud__c28k8Hz 8 -#define R_SYNC_SERIAL1_CTRL__tr_baud__tr_baud__c300Hz 1 -#define R_SYNC_SERIAL1_CTRL__tr_baud__tr_baud__c3125kHz 14 -#define R_SYNC_SERIAL1_CTRL__tr_baud__tr_baud__c460k8Hz 12 -#define R_SYNC_SERIAL1_CTRL__tr_baud__tr_baud__c4800Hz 5 -#define R_SYNC_SERIAL1_CTRL__tr_baud__tr_baud__c57k6Hz 9 -#define R_SYNC_SERIAL1_CTRL__tr_baud__tr_baud__c600Hz 2 -#define R_SYNC_SERIAL1_CTRL__tr_baud__tr_baud__c921k6Hz 13 -#define R_SYNC_SERIAL1_CTRL__tr_baud__tr_baud__c9600Hz 6 -#define R_SYNC_SERIAL1_CTRL__dma_enable__dma_enable__off 0 -#define R_SYNC_SERIAL1_CTRL__dma_enable__dma_enable__on 1 -#define R_SYNC_SERIAL1_CTRL__mode__mode__master_bidir 4 -#define R_SYNC_SERIAL1_CTRL__mode__mode__master_input 2 -#define R_SYNC_SERIAL1_CTRL__mode__mode__master_output 0 -#define R_SYNC_SERIAL1_CTRL__mode__mode__slave_bidir 5 -#define R_SYNC_SERIAL1_CTRL__mode__mode__slave_input 3 -#define R_SYNC_SERIAL1_CTRL__mode__mode__slave_output 1 -#define R_SYNC_SERIAL1_CTRL__error__error__ignore 1 -#define R_SYNC_SERIAL1_CTRL__error__error__normal 0 -#define R_SYNC_SERIAL1_CTRL__rec_enable__rec_enable__disable 0 -#define R_SYNC_SERIAL1_CTRL__rec_enable__rec_enable__enable 1 -#define R_SYNC_SERIAL1_CTRL__f_synctype__f_synctype__early 1 -#define R_SYNC_SERIAL1_CTRL__f_synctype__f_synctype__normal 0 -#define R_SYNC_SERIAL1_CTRL__f_syncsize__f_syncsize__bit 0 -#define R_SYNC_SERIAL1_CTRL__f_syncsize__f_syncsize__extended 2 -#define R_SYNC_SERIAL1_CTRL__f_syncsize__f_syncsize__word 1 -#define R_SYNC_SERIAL1_CTRL__f_sync__f_sync__off 1 -#define R_SYNC_SERIAL1_CTRL__f_sync__f_sync__on 0 -#define R_SYNC_SERIAL1_CTRL__clk_mode__clk_mode__gated 1 -#define R_SYNC_SERIAL1_CTRL__clk_mode__clk_mode__normal 0 -#define R_SYNC_SERIAL1_CTRL__clk_halt__clk_halt__running 0 -#define R_SYNC_SERIAL1_CTRL__clk_halt__clk_halt__stopped 1 -#define R_SYNC_SERIAL1_CTRL__bitorder__bitorder__lsb 0 -#define R_SYNC_SERIAL1_CTRL__bitorder__bitorder__msb 1 -#define R_SYNC_SERIAL1_CTRL__tr_enable__tr_enable__disable 0 -#define R_SYNC_SERIAL1_CTRL__tr_enable__tr_enable__enable 1 -#define R_SYNC_SERIAL1_CTRL__wordsize__wordsize__size12bit 1 -#define R_SYNC_SERIAL1_CTRL__wordsize__wordsize__size16bit 2 -#define R_SYNC_SERIAL1_CTRL__wordsize__wordsize__size24bit 3 -#define R_SYNC_SERIAL1_CTRL__wordsize__wordsize__size32bit 4 -#define R_SYNC_SERIAL1_CTRL__wordsize__wordsize__size8bit 0 -#define R_SYNC_SERIAL1_CTRL__buf_empty__buf_empty__lmt_0 1 -#define R_SYNC_SERIAL1_CTRL__buf_empty__buf_empty__lmt_8 0 -#define R_SYNC_SERIAL1_CTRL__buf_full__buf_full__lmt_32 0 -#define R_SYNC_SERIAL1_CTRL__buf_full__buf_full__lmt_8 1 -#define R_SYNC_SERIAL1_CTRL__flow_ctrl__flow_ctrl__disabled 0 -#define R_SYNC_SERIAL1_CTRL__flow_ctrl__flow_ctrl__enabled 1 -#define R_SYNC_SERIAL1_CTRL__clk_polarity__clk_polarity__neg 1 -#define R_SYNC_SERIAL1_CTRL__clk_polarity__clk_polarity__pos 0 -#define R_SYNC_SERIAL1_CTRL__frame_polarity__frame_polarity__inverted 1 -#define R_SYNC_SERIAL1_CTRL__frame_polarity__frame_polarity__normal 0 -#define R_SYNC_SERIAL1_CTRL__status_polarity__status_polarity__inverted 1 -#define R_SYNC_SERIAL1_CTRL__status_polarity__status_polarity__normal 0 -#define R_SYNC_SERIAL1_CTRL__clk_driver__clk_driver__inverted 1 -#define R_SYNC_SERIAL1_CTRL__clk_driver__clk_driver__normal 0 -#define R_SYNC_SERIAL1_CTRL__frame_driver__frame_driver__inverted 1 -#define R_SYNC_SERIAL1_CTRL__frame_driver__frame_driver__normal 0 -#define R_SYNC_SERIAL1_CTRL__status_driver__status_driver__inverted 1 -#define R_SYNC_SERIAL1_CTRL__status_driver__status_driver__normal 0 -#define R_SYNC_SERIAL1_CTRL__def_out0__def_out0__high 1 -#define R_SYNC_SERIAL1_CTRL__def_out0__def_out0__low 0 - -#endif - -/* - * R_SYNC_SERIAL1_REC_BYTE - * - type: RO - * - addr: 0xb000006c - * - group: Syncrounous serial port registers - */ - -#if USE_GROUP__Syncrounous_serial_port_registers - -#define R_SYNC_SERIAL1_REC_BYTE__ADDR (REG_TYPECAST_BYTE 0xb000006c) -#define R_SYNC_SERIAL1_REC_BYTE__SVAL REG_SVAL_SHADOW -#define R_SYNC_SERIAL1_REC_BYTE__SVAL_I REG_SVAL_I_SHADOW -#define R_SYNC_SERIAL1_REC_BYTE__TYPECAST REG_TYPECAST_BYTE -#define R_SYNC_SERIAL1_REC_BYTE__TYPE (REG_BYTE) -#define R_SYNC_SERIAL1_REC_BYTE__GET REG_GET_RO -#define R_SYNC_SERIAL1_REC_BYTE__IGET REG_IGET_RO -#define R_SYNC_SERIAL1_REC_BYTE__SET REG_SET_RO -#define R_SYNC_SERIAL1_REC_BYTE__ISET REG_ISET_RO -#define R_SYNC_SERIAL1_REC_BYTE__SET_VAL REG_SET_VAL_RO -#define R_SYNC_SERIAL1_REC_BYTE__EQL REG_EQL_RO -#define R_SYNC_SERIAL1_REC_BYTE__IEQL REG_IEQL_RO -#define R_SYNC_SERIAL1_REC_BYTE__RD REG_RD_RO -#define R_SYNC_SERIAL1_REC_BYTE__IRD REG_IRD_RO -#define R_SYNC_SERIAL1_REC_BYTE__WR REG_WR_RO -#define R_SYNC_SERIAL1_REC_BYTE__IWR REG_IWR_RO - -#define R_SYNC_SERIAL1_REC_BYTE__READ(addr) \ - (*(addr)) - -#define R_SYNC_SERIAL1_REC_BYTE__data_in__data_in__MASK 0x000000ffU - -#define R_SYNC_SERIAL1_REC_BYTE__data_in__MAX 0xff - -#define R_SYNC_SERIAL1_REC_BYTE__data_in__MIN 0 - -#define R_SYNC_SERIAL1_REC_BYTE__data_in__BITNR 0 - -#define R_SYNC_SERIAL1_REC_BYTE__data_in__data_in__VAL REG_VAL_VAL - - -#endif - -/* - * R_SYNC_SERIAL1_REC_DATA - * - type: RO - * - addr: 0xb000006c - * - group: Syncrounous serial port registers - */ - -#if USE_GROUP__Syncrounous_serial_port_registers - -#define R_SYNC_SERIAL1_REC_DATA__ADDR (REG_TYPECAST_UDWORD 0xb000006c) -#define R_SYNC_SERIAL1_REC_DATA__SVAL REG_SVAL_SHADOW -#define R_SYNC_SERIAL1_REC_DATA__SVAL_I REG_SVAL_I_SHADOW -#define R_SYNC_SERIAL1_REC_DATA__TYPECAST REG_TYPECAST_UDWORD -#define R_SYNC_SERIAL1_REC_DATA__TYPE (REG_UDWORD) -#define R_SYNC_SERIAL1_REC_DATA__GET REG_GET_RO -#define R_SYNC_SERIAL1_REC_DATA__IGET REG_IGET_RO -#define R_SYNC_SERIAL1_REC_DATA__SET REG_SET_RO -#define R_SYNC_SERIAL1_REC_DATA__ISET REG_ISET_RO -#define R_SYNC_SERIAL1_REC_DATA__SET_VAL REG_SET_VAL_RO -#define R_SYNC_SERIAL1_REC_DATA__EQL REG_EQL_RO -#define R_SYNC_SERIAL1_REC_DATA__IEQL REG_IEQL_RO -#define R_SYNC_SERIAL1_REC_DATA__RD REG_RD_RO -#define R_SYNC_SERIAL1_REC_DATA__IRD REG_IRD_RO -#define R_SYNC_SERIAL1_REC_DATA__WR REG_WR_RO -#define R_SYNC_SERIAL1_REC_DATA__IWR REG_IWR_RO - -#define R_SYNC_SERIAL1_REC_DATA__READ(addr) \ - (*(addr)) - -#define R_SYNC_SERIAL1_REC_DATA__data_in__data_in__MASK 0xffffffffU - -#define R_SYNC_SERIAL1_REC_DATA__data_in__MAX 0xffffffff - -#define R_SYNC_SERIAL1_REC_DATA__data_in__MIN 0 - -#define R_SYNC_SERIAL1_REC_DATA__data_in__BITNR 0 - -#define R_SYNC_SERIAL1_REC_DATA__data_in__data_in__VAL REG_VAL_VAL - - -#endif - -/* - * R_SYNC_SERIAL1_REC_WORD - * - type: RO - * - addr: 0xb000006c - * - group: Syncrounous serial port registers - */ - -#if USE_GROUP__Syncrounous_serial_port_registers - -#define R_SYNC_SERIAL1_REC_WORD__ADDR (REG_TYPECAST_UWORD 0xb000006c) -#define R_SYNC_SERIAL1_REC_WORD__SVAL REG_SVAL_SHADOW -#define R_SYNC_SERIAL1_REC_WORD__SVAL_I REG_SVAL_I_SHADOW -#define R_SYNC_SERIAL1_REC_WORD__TYPECAST REG_TYPECAST_UWORD -#define R_SYNC_SERIAL1_REC_WORD__TYPE (REG_UWORD) -#define R_SYNC_SERIAL1_REC_WORD__GET REG_GET_RO -#define R_SYNC_SERIAL1_REC_WORD__IGET REG_IGET_RO -#define R_SYNC_SERIAL1_REC_WORD__SET REG_SET_RO -#define R_SYNC_SERIAL1_REC_WORD__ISET REG_ISET_RO -#define R_SYNC_SERIAL1_REC_WORD__SET_VAL REG_SET_VAL_RO -#define R_SYNC_SERIAL1_REC_WORD__EQL REG_EQL_RO -#define R_SYNC_SERIAL1_REC_WORD__IEQL REG_IEQL_RO -#define R_SYNC_SERIAL1_REC_WORD__RD REG_RD_RO -#define R_SYNC_SERIAL1_REC_WORD__IRD REG_IRD_RO -#define R_SYNC_SERIAL1_REC_WORD__WR REG_WR_RO -#define R_SYNC_SERIAL1_REC_WORD__IWR REG_IWR_RO - -#define R_SYNC_SERIAL1_REC_WORD__READ(addr) \ - (*(addr)) - -#define R_SYNC_SERIAL1_REC_WORD__data_in__data_in__MASK 0x0000ffffU - -#define R_SYNC_SERIAL1_REC_WORD__data_in__MAX 0xffff - -#define R_SYNC_SERIAL1_REC_WORD__data_in__MIN 0 - -#define R_SYNC_SERIAL1_REC_WORD__data_in__BITNR 0 - -#define R_SYNC_SERIAL1_REC_WORD__data_in__data_in__VAL REG_VAL_VAL - - -#endif - -/* - * R_SYNC_SERIAL1_STATUS - * - type: RO - * - addr: 0xb0000068 - * - group: Syncrounous serial port registers - */ - -#if USE_GROUP__Syncrounous_serial_port_registers - -#define R_SYNC_SERIAL1_STATUS__ADDR (REG_TYPECAST_UDWORD 0xb0000068) -#define R_SYNC_SERIAL1_STATUS__SVAL REG_SVAL_SHADOW -#define R_SYNC_SERIAL1_STATUS__SVAL_I REG_SVAL_I_SHADOW -#define R_SYNC_SERIAL1_STATUS__TYPECAST REG_TYPECAST_UDWORD -#define R_SYNC_SERIAL1_STATUS__TYPE (REG_UDWORD) -#define R_SYNC_SERIAL1_STATUS__GET REG_GET_RO -#define R_SYNC_SERIAL1_STATUS__IGET REG_IGET_RO -#define R_SYNC_SERIAL1_STATUS__SET REG_SET_RO -#define R_SYNC_SERIAL1_STATUS__ISET REG_ISET_RO -#define R_SYNC_SERIAL1_STATUS__SET_VAL REG_SET_VAL_RO -#define R_SYNC_SERIAL1_STATUS__EQL REG_EQL_RO -#define R_SYNC_SERIAL1_STATUS__IEQL REG_IEQL_RO -#define R_SYNC_SERIAL1_STATUS__RD REG_RD_RO -#define R_SYNC_SERIAL1_STATUS__IRD REG_IRD_RO -#define R_SYNC_SERIAL1_STATUS__WR REG_WR_RO -#define R_SYNC_SERIAL1_STATUS__IWR REG_IWR_RO - -#define R_SYNC_SERIAL1_STATUS__READ(addr) \ - (*(addr)) - -#define R_SYNC_SERIAL1_STATUS__rec_status__rec_status__MASK 0x00008000U -#define R_SYNC_SERIAL1_STATUS__tr_empty__tr_empty__MASK 0x00004000U -#define R_SYNC_SERIAL1_STATUS__tr_ready__tr_ready__MASK 0x00002000U -#define R_SYNC_SERIAL1_STATUS__pin_1__pin_1__MASK 0x00001000U -#define R_SYNC_SERIAL1_STATUS__pin_0__pin_0__MASK 0x00000800U -#define R_SYNC_SERIAL1_STATUS__underflow__underflow__MASK 0x00000400U -#define R_SYNC_SERIAL1_STATUS__overrun__overrun__MASK 0x00000200U -#define R_SYNC_SERIAL1_STATUS__data_avail__data_avail__MASK 0x00000100U -#define R_SYNC_SERIAL1_STATUS__data__data__MASK 0x000000ffU - -#define R_SYNC_SERIAL1_STATUS__rec_status__MAX 0x1 -#define R_SYNC_SERIAL1_STATUS__tr_empty__MAX 0x1 -#define R_SYNC_SERIAL1_STATUS__tr_ready__MAX 0x1 -#define R_SYNC_SERIAL1_STATUS__pin_1__MAX 0x1 -#define R_SYNC_SERIAL1_STATUS__pin_0__MAX 0x1 -#define R_SYNC_SERIAL1_STATUS__underflow__MAX 0x1 -#define R_SYNC_SERIAL1_STATUS__overrun__MAX 0x1 -#define R_SYNC_SERIAL1_STATUS__data_avail__MAX 0x1 -#define R_SYNC_SERIAL1_STATUS__data__MAX 0xff - -#define R_SYNC_SERIAL1_STATUS__rec_status__MIN 0 -#define R_SYNC_SERIAL1_STATUS__tr_empty__MIN 0 -#define R_SYNC_SERIAL1_STATUS__tr_ready__MIN 0 -#define R_SYNC_SERIAL1_STATUS__pin_1__MIN 0 -#define R_SYNC_SERIAL1_STATUS__pin_0__MIN 0 -#define R_SYNC_SERIAL1_STATUS__underflow__MIN 0 -#define R_SYNC_SERIAL1_STATUS__overrun__MIN 0 -#define R_SYNC_SERIAL1_STATUS__data_avail__MIN 0 -#define R_SYNC_SERIAL1_STATUS__data__MIN 0 - -#define R_SYNC_SERIAL1_STATUS__rec_status__BITNR 15 -#define R_SYNC_SERIAL1_STATUS__tr_empty__BITNR 14 -#define R_SYNC_SERIAL1_STATUS__tr_ready__BITNR 13 -#define R_SYNC_SERIAL1_STATUS__pin_1__BITNR 12 -#define R_SYNC_SERIAL1_STATUS__pin_0__BITNR 11 -#define R_SYNC_SERIAL1_STATUS__underflow__BITNR 10 -#define R_SYNC_SERIAL1_STATUS__overrun__BITNR 9 -#define R_SYNC_SERIAL1_STATUS__data_avail__BITNR 8 -#define R_SYNC_SERIAL1_STATUS__data__BITNR 0 - -#define R_SYNC_SERIAL1_STATUS__rec_status__rec_status__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL1_STATUS__tr_empty__tr_empty__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL1_STATUS__tr_ready__tr_ready__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL1_STATUS__pin_1__pin_1__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL1_STATUS__pin_0__pin_0__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL1_STATUS__underflow__underflow__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL1_STATUS__overrun__overrun__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL1_STATUS__data_avail__data_avail__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL1_STATUS__data__data__VAL REG_VAL_VAL - -#define R_SYNC_SERIAL1_STATUS__rec_status__rec_status__idle 1 -#define R_SYNC_SERIAL1_STATUS__rec_status__rec_status__running 0 -#define R_SYNC_SERIAL1_STATUS__tr_empty__tr_empty__empty 1 -#define R_SYNC_SERIAL1_STATUS__tr_empty__tr_empty__not_empty 0 -#define R_SYNC_SERIAL1_STATUS__tr_ready__tr_ready__full 0 -#define R_SYNC_SERIAL1_STATUS__tr_ready__tr_ready__ready 1 -#define R_SYNC_SERIAL1_STATUS__pin_1__pin_1__high 1 -#define R_SYNC_SERIAL1_STATUS__pin_1__pin_1__low 0 -#define R_SYNC_SERIAL1_STATUS__pin_0__pin_0__high 1 -#define R_SYNC_SERIAL1_STATUS__pin_0__pin_0__low 0 -#define R_SYNC_SERIAL1_STATUS__underflow__underflow__no 0 -#define R_SYNC_SERIAL1_STATUS__underflow__underflow__yes 1 -#define R_SYNC_SERIAL1_STATUS__overrun__overrun__no 0 -#define R_SYNC_SERIAL1_STATUS__overrun__overrun__yes 1 -#define R_SYNC_SERIAL1_STATUS__data_avail__data_avail__no 0 -#define R_SYNC_SERIAL1_STATUS__data_avail__data_avail__yes 1 - -#endif - -/* - * R_SYNC_SERIAL1_TR_BYTE - * - type: WO - * - addr: 0xb000006c - * - group: Syncrounous serial port registers - */ - -#if USE_GROUP__Syncrounous_serial_port_registers - -#define R_SYNC_SERIAL1_TR_BYTE__ADDR (REG_TYPECAST_BYTE 0xb000006c) - -#ifndef REG_NO_SHADOW -#define R_SYNC_SERIAL1_TR_BYTE__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL1_XOFF + 0)) -#define R_SYNC_SERIAL1_TR_BYTE__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL1_XOFF + 0)) -#else /* REG_NO_SHADOW */ -#define R_SYNC_SERIAL1_TR_BYTE__SADDR (REG_STYPECAST_BYTE (®_shadow__hwregs)) -#define R_SYNC_SERIAL1_TR_BYTE__IADDR (REG_STYPECAST_BYTE (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_SYNC_SERIAL1_TR_BYTE__STYPECAST REG_STYPECAST_BYTE -#define R_SYNC_SERIAL1_TR_BYTE__SVAL REG_SVAL_SHADOW -#define R_SYNC_SERIAL1_TR_BYTE__SVAL_I REG_SVAL_I_SHADOW -#define R_SYNC_SERIAL1_TR_BYTE__TYPECAST REG_TYPECAST_BYTE -#define R_SYNC_SERIAL1_TR_BYTE__TYPE (REG_BYTE) -#define R_SYNC_SERIAL1_TR_BYTE__GET REG_GET_WO -#define R_SYNC_SERIAL1_TR_BYTE__IGET REG_IGET_WO -#define R_SYNC_SERIAL1_TR_BYTE__SET REG_SET_WO -#define R_SYNC_SERIAL1_TR_BYTE__ISET REG_ISET_WO -#define R_SYNC_SERIAL1_TR_BYTE__SET_VAL REG_SET_VAL_WO -#define R_SYNC_SERIAL1_TR_BYTE__EQL REG_EQL_WO -#define R_SYNC_SERIAL1_TR_BYTE__IEQL REG_IEQL_WO -#define R_SYNC_SERIAL1_TR_BYTE__RD REG_RD_WO -#define R_SYNC_SERIAL1_TR_BYTE__IRD REG_IRD_WO -#define R_SYNC_SERIAL1_TR_BYTE__WR REG_WR_WO -#define R_SYNC_SERIAL1_TR_BYTE__IWR REG_IWR_WO - -#define R_SYNC_SERIAL1_TR_BYTE__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_SYNC_SERIAL1_TR_BYTE__data_out__data_out__MASK 0x000000ffU - -#define R_SYNC_SERIAL1_TR_BYTE__data_out__MAX 0xff - -#define R_SYNC_SERIAL1_TR_BYTE__data_out__MIN 0 - -#define R_SYNC_SERIAL1_TR_BYTE__data_out__BITNR 0 - -#define R_SYNC_SERIAL1_TR_BYTE__data_out__data_out__VAL REG_VAL_VAL - - -#endif - -/* - * R_SYNC_SERIAL1_TR_DATA - * - type: WO - * - addr: 0xb000006c - * - group: Syncrounous serial port registers - */ - -#if USE_GROUP__Syncrounous_serial_port_registers - -#define R_SYNC_SERIAL1_TR_DATA__ADDR (REG_TYPECAST_UDWORD 0xb000006c) - -#ifndef REG_NO_SHADOW -#define R_SYNC_SERIAL1_TR_DATA__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_SERIAL1_XOFF + 0)) -#define R_SYNC_SERIAL1_TR_DATA__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_SERIAL1_XOFF + 0)) -#else /* REG_NO_SHADOW */ -#define R_SYNC_SERIAL1_TR_DATA__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_SYNC_SERIAL1_TR_DATA__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_SYNC_SERIAL1_TR_DATA__STYPECAST REG_STYPECAST_UDWORD -#define R_SYNC_SERIAL1_TR_DATA__SVAL REG_SVAL_SHADOW -#define R_SYNC_SERIAL1_TR_DATA__SVAL_I REG_SVAL_I_SHADOW -#define R_SYNC_SERIAL1_TR_DATA__TYPECAST REG_TYPECAST_UDWORD -#define R_SYNC_SERIAL1_TR_DATA__TYPE (REG_UDWORD) -#define R_SYNC_SERIAL1_TR_DATA__GET REG_GET_WO -#define R_SYNC_SERIAL1_TR_DATA__IGET REG_IGET_WO -#define R_SYNC_SERIAL1_TR_DATA__SET REG_SET_WO -#define R_SYNC_SERIAL1_TR_DATA__ISET REG_ISET_WO -#define R_SYNC_SERIAL1_TR_DATA__SET_VAL REG_SET_VAL_WO -#define R_SYNC_SERIAL1_TR_DATA__EQL REG_EQL_WO -#define R_SYNC_SERIAL1_TR_DATA__IEQL REG_IEQL_WO -#define R_SYNC_SERIAL1_TR_DATA__RD REG_RD_WO -#define R_SYNC_SERIAL1_TR_DATA__IRD REG_IRD_WO -#define R_SYNC_SERIAL1_TR_DATA__WR REG_WR_WO -#define R_SYNC_SERIAL1_TR_DATA__IWR REG_IWR_WO - -#define R_SYNC_SERIAL1_TR_DATA__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_SYNC_SERIAL1_TR_DATA__data_out__data_out__MASK 0xffffffffU - -#define R_SYNC_SERIAL1_TR_DATA__data_out__MAX 0xffffffff - -#define R_SYNC_SERIAL1_TR_DATA__data_out__MIN 0 - -#define R_SYNC_SERIAL1_TR_DATA__data_out__BITNR 0 - -#define R_SYNC_SERIAL1_TR_DATA__data_out__data_out__VAL REG_VAL_VAL - - -#endif - -/* - * R_SYNC_SERIAL1_TR_WORD - * - type: WO - * - addr: 0xb000006c - * - group: Syncrounous serial port registers - */ - -#if USE_GROUP__Syncrounous_serial_port_registers - -#define R_SYNC_SERIAL1_TR_WORD__ADDR (REG_TYPECAST_UWORD 0xb000006c) - -#ifndef REG_NO_SHADOW -#define R_SYNC_SERIAL1_TR_WORD__SADDR (REG_STYPECAST_UWORD (reg_shadow__hwregs.R_SERIAL1_XOFF + 0)) -#define R_SYNC_SERIAL1_TR_WORD__IADDR (REG_STYPECAST_UWORD (reg_initiated__hwregs.R_SERIAL1_XOFF + 0)) -#else /* REG_NO_SHADOW */ -#define R_SYNC_SERIAL1_TR_WORD__SADDR (REG_STYPECAST_UWORD (®_shadow__hwregs)) -#define R_SYNC_SERIAL1_TR_WORD__IADDR (REG_STYPECAST_UWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_SYNC_SERIAL1_TR_WORD__STYPECAST REG_STYPECAST_UWORD -#define R_SYNC_SERIAL1_TR_WORD__SVAL REG_SVAL_SHADOW -#define R_SYNC_SERIAL1_TR_WORD__SVAL_I REG_SVAL_I_SHADOW -#define R_SYNC_SERIAL1_TR_WORD__TYPECAST REG_TYPECAST_UWORD -#define R_SYNC_SERIAL1_TR_WORD__TYPE (REG_UWORD) -#define R_SYNC_SERIAL1_TR_WORD__GET REG_GET_WO -#define R_SYNC_SERIAL1_TR_WORD__IGET REG_IGET_WO -#define R_SYNC_SERIAL1_TR_WORD__SET REG_SET_WO -#define R_SYNC_SERIAL1_TR_WORD__ISET REG_ISET_WO -#define R_SYNC_SERIAL1_TR_WORD__SET_VAL REG_SET_VAL_WO -#define R_SYNC_SERIAL1_TR_WORD__EQL REG_EQL_WO -#define R_SYNC_SERIAL1_TR_WORD__IEQL REG_IEQL_WO -#define R_SYNC_SERIAL1_TR_WORD__RD REG_RD_WO -#define R_SYNC_SERIAL1_TR_WORD__IRD REG_IRD_WO -#define R_SYNC_SERIAL1_TR_WORD__WR REG_WR_WO -#define R_SYNC_SERIAL1_TR_WORD__IWR REG_IWR_WO - -#define R_SYNC_SERIAL1_TR_WORD__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_SYNC_SERIAL1_TR_WORD__data_out__data_out__MASK 0x0000ffffU - -#define R_SYNC_SERIAL1_TR_WORD__data_out__MAX 0xffff - -#define R_SYNC_SERIAL1_TR_WORD__data_out__MIN 0 - -#define R_SYNC_SERIAL1_TR_WORD__data_out__BITNR 0 - -#define R_SYNC_SERIAL1_TR_WORD__data_out__data_out__VAL REG_VAL_VAL - - -#endif - -/* - * R_SYNC_SERIAL3_CTRL - * - type: WO - * - addr: 0xb0000078 - * - group: Syncrounous serial port registers - */ - -#if USE_GROUP__Syncrounous_serial_port_registers - -#define R_SYNC_SERIAL3_CTRL__ADDR (REG_TYPECAST_UDWORD 0xb0000078) - -#ifndef REG_NO_SHADOW -#define R_SYNC_SERIAL3_CTRL__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_SERIAL3_CTRL + 0)) -#define R_SYNC_SERIAL3_CTRL__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_SERIAL3_CTRL + 0)) -#else /* REG_NO_SHADOW */ -#define R_SYNC_SERIAL3_CTRL__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_SYNC_SERIAL3_CTRL__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_SYNC_SERIAL3_CTRL__STYPECAST REG_STYPECAST_UDWORD -#define R_SYNC_SERIAL3_CTRL__SVAL REG_SVAL_SHADOW -#define R_SYNC_SERIAL3_CTRL__SVAL_I REG_SVAL_I_SHADOW -#define R_SYNC_SERIAL3_CTRL__TYPECAST REG_TYPECAST_UDWORD -#define R_SYNC_SERIAL3_CTRL__TYPE (REG_UDWORD) -#define R_SYNC_SERIAL3_CTRL__GET REG_GET_WO -#define R_SYNC_SERIAL3_CTRL__IGET REG_IGET_WO -#define R_SYNC_SERIAL3_CTRL__SET REG_SET_WO -#define R_SYNC_SERIAL3_CTRL__ISET REG_ISET_WO -#define R_SYNC_SERIAL3_CTRL__SET_VAL REG_SET_VAL_WO -#define R_SYNC_SERIAL3_CTRL__EQL REG_EQL_WO -#define R_SYNC_SERIAL3_CTRL__IEQL REG_IEQL_WO -#define R_SYNC_SERIAL3_CTRL__RD REG_RD_WO -#define R_SYNC_SERIAL3_CTRL__IRD REG_IRD_WO -#define R_SYNC_SERIAL3_CTRL__WR REG_WR_WO -#define R_SYNC_SERIAL3_CTRL__IWR REG_IWR_WO - -#define R_SYNC_SERIAL3_CTRL__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_SYNC_SERIAL3_CTRL__tr_baud__tr_baud__MASK 0xf0000000U -#define R_SYNC_SERIAL3_CTRL__dma_enable__dma_enable__MASK 0x08000000U -#define R_SYNC_SERIAL3_CTRL__mode__mode__MASK 0x07000000U -#define R_SYNC_SERIAL3_CTRL__error__error__MASK 0x00800000U -#define R_SYNC_SERIAL3_CTRL__rec_enable__rec_enable__MASK 0x00400000U -#define R_SYNC_SERIAL3_CTRL__f_synctype__f_synctype__MASK 0x00200000U -#define R_SYNC_SERIAL3_CTRL__f_syncsize__f_syncsize__MASK 0x00180000U -#define R_SYNC_SERIAL3_CTRL__f_sync__f_sync__MASK 0x00040000U -#define R_SYNC_SERIAL3_CTRL__clk_mode__clk_mode__MASK 0x00020000U -#define R_SYNC_SERIAL3_CTRL__clk_halt__clk_halt__MASK 0x00010000U -#define R_SYNC_SERIAL3_CTRL__bitorder__bitorder__MASK 0x00008000U -#define R_SYNC_SERIAL3_CTRL__tr_enable__tr_enable__MASK 0x00004000U -#define R_SYNC_SERIAL3_CTRL__wordsize__wordsize__MASK 0x00003800U -#define R_SYNC_SERIAL3_CTRL__buf_empty__buf_empty__MASK 0x00000400U -#define R_SYNC_SERIAL3_CTRL__buf_full__buf_full__MASK 0x00000200U -#define R_SYNC_SERIAL3_CTRL__flow_ctrl__flow_ctrl__MASK 0x00000100U -#define R_SYNC_SERIAL3_CTRL__clk_polarity__clk_polarity__MASK 0x00000040U -#define R_SYNC_SERIAL3_CTRL__frame_polarity__frame_polarity__MASK 0x00000020U -#define R_SYNC_SERIAL3_CTRL__status_polarity__status_polarity__MASK 0x00000010U -#define R_SYNC_SERIAL3_CTRL__clk_driver__clk_driver__MASK 0x00000008U -#define R_SYNC_SERIAL3_CTRL__frame_driver__frame_driver__MASK 0x00000004U -#define R_SYNC_SERIAL3_CTRL__status_driver__status_driver__MASK 0x00000002U -#define R_SYNC_SERIAL3_CTRL__def_out0__def_out0__MASK 0x00000001U - -#define R_SYNC_SERIAL3_CTRL__tr_baud__MAX 0xf -#define R_SYNC_SERIAL3_CTRL__dma_enable__MAX 0x1 -#define R_SYNC_SERIAL3_CTRL__mode__MAX 0x7 -#define R_SYNC_SERIAL3_CTRL__error__MAX 0x1 -#define R_SYNC_SERIAL3_CTRL__rec_enable__MAX 0x1 -#define R_SYNC_SERIAL3_CTRL__f_synctype__MAX 0x1 -#define R_SYNC_SERIAL3_CTRL__f_syncsize__MAX 0x3 -#define R_SYNC_SERIAL3_CTRL__f_sync__MAX 0x1 -#define R_SYNC_SERIAL3_CTRL__clk_mode__MAX 0x1 -#define R_SYNC_SERIAL3_CTRL__clk_halt__MAX 0x1 -#define R_SYNC_SERIAL3_CTRL__bitorder__MAX 0x1 -#define R_SYNC_SERIAL3_CTRL__tr_enable__MAX 0x1 -#define R_SYNC_SERIAL3_CTRL__wordsize__MAX 0x7 -#define R_SYNC_SERIAL3_CTRL__buf_empty__MAX 0x1 -#define R_SYNC_SERIAL3_CTRL__buf_full__MAX 0x1 -#define R_SYNC_SERIAL3_CTRL__flow_ctrl__MAX 0x1 -#define R_SYNC_SERIAL3_CTRL__clk_polarity__MAX 0x1 -#define R_SYNC_SERIAL3_CTRL__frame_polarity__MAX 0x1 -#define R_SYNC_SERIAL3_CTRL__status_polarity__MAX 0x1 -#define R_SYNC_SERIAL3_CTRL__clk_driver__MAX 0x1 -#define R_SYNC_SERIAL3_CTRL__frame_driver__MAX 0x1 -#define R_SYNC_SERIAL3_CTRL__status_driver__MAX 0x1 -#define R_SYNC_SERIAL3_CTRL__def_out0__MAX 0x1 - -#define R_SYNC_SERIAL3_CTRL__tr_baud__MIN 0 -#define R_SYNC_SERIAL3_CTRL__dma_enable__MIN 0 -#define R_SYNC_SERIAL3_CTRL__mode__MIN 0 -#define R_SYNC_SERIAL3_CTRL__error__MIN 0 -#define R_SYNC_SERIAL3_CTRL__rec_enable__MIN 0 -#define R_SYNC_SERIAL3_CTRL__f_synctype__MIN 0 -#define R_SYNC_SERIAL3_CTRL__f_syncsize__MIN 0 -#define R_SYNC_SERIAL3_CTRL__f_sync__MIN 0 -#define R_SYNC_SERIAL3_CTRL__clk_mode__MIN 0 -#define R_SYNC_SERIAL3_CTRL__clk_halt__MIN 0 -#define R_SYNC_SERIAL3_CTRL__bitorder__MIN 0 -#define R_SYNC_SERIAL3_CTRL__tr_enable__MIN 0 -#define R_SYNC_SERIAL3_CTRL__wordsize__MIN 0 -#define R_SYNC_SERIAL3_CTRL__buf_empty__MIN 0 -#define R_SYNC_SERIAL3_CTRL__buf_full__MIN 0 -#define R_SYNC_SERIAL3_CTRL__flow_ctrl__MIN 0 -#define R_SYNC_SERIAL3_CTRL__clk_polarity__MIN 0 -#define R_SYNC_SERIAL3_CTRL__frame_polarity__MIN 0 -#define R_SYNC_SERIAL3_CTRL__status_polarity__MIN 0 -#define R_SYNC_SERIAL3_CTRL__clk_driver__MIN 0 -#define R_SYNC_SERIAL3_CTRL__frame_driver__MIN 0 -#define R_SYNC_SERIAL3_CTRL__status_driver__MIN 0 -#define R_SYNC_SERIAL3_CTRL__def_out0__MIN 0 - -#define R_SYNC_SERIAL3_CTRL__tr_baud__BITNR 28 -#define R_SYNC_SERIAL3_CTRL__dma_enable__BITNR 27 -#define R_SYNC_SERIAL3_CTRL__mode__BITNR 24 -#define R_SYNC_SERIAL3_CTRL__error__BITNR 23 -#define R_SYNC_SERIAL3_CTRL__rec_enable__BITNR 22 -#define R_SYNC_SERIAL3_CTRL__f_synctype__BITNR 21 -#define R_SYNC_SERIAL3_CTRL__f_syncsize__BITNR 19 -#define R_SYNC_SERIAL3_CTRL__f_sync__BITNR 18 -#define R_SYNC_SERIAL3_CTRL__clk_mode__BITNR 17 -#define R_SYNC_SERIAL3_CTRL__clk_halt__BITNR 16 -#define R_SYNC_SERIAL3_CTRL__bitorder__BITNR 15 -#define R_SYNC_SERIAL3_CTRL__tr_enable__BITNR 14 -#define R_SYNC_SERIAL3_CTRL__wordsize__BITNR 11 -#define R_SYNC_SERIAL3_CTRL__buf_empty__BITNR 10 -#define R_SYNC_SERIAL3_CTRL__buf_full__BITNR 9 -#define R_SYNC_SERIAL3_CTRL__flow_ctrl__BITNR 8 -#define R_SYNC_SERIAL3_CTRL__clk_polarity__BITNR 6 -#define R_SYNC_SERIAL3_CTRL__frame_polarity__BITNR 5 -#define R_SYNC_SERIAL3_CTRL__status_polarity__BITNR 4 -#define R_SYNC_SERIAL3_CTRL__clk_driver__BITNR 3 -#define R_SYNC_SERIAL3_CTRL__frame_driver__BITNR 2 -#define R_SYNC_SERIAL3_CTRL__status_driver__BITNR 1 -#define R_SYNC_SERIAL3_CTRL__def_out0__BITNR 0 - -#define R_SYNC_SERIAL3_CTRL__tr_baud__tr_baud__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL3_CTRL__dma_enable__dma_enable__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL3_CTRL__mode__mode__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL3_CTRL__error__error__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL3_CTRL__rec_enable__rec_enable__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL3_CTRL__f_synctype__f_synctype__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL3_CTRL__f_syncsize__f_syncsize__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL3_CTRL__f_sync__f_sync__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL3_CTRL__clk_mode__clk_mode__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL3_CTRL__clk_halt__clk_halt__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL3_CTRL__bitorder__bitorder__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL3_CTRL__tr_enable__tr_enable__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL3_CTRL__wordsize__wordsize__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL3_CTRL__buf_empty__buf_empty__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL3_CTRL__buf_full__buf_full__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL3_CTRL__flow_ctrl__flow_ctrl__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL3_CTRL__clk_polarity__clk_polarity__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL3_CTRL__frame_polarity__frame_polarity__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL3_CTRL__status_polarity__status_polarity__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL3_CTRL__clk_driver__clk_driver__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL3_CTRL__frame_driver__frame_driver__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL3_CTRL__status_driver__status_driver__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL3_CTRL__def_out0__def_out0__VAL REG_VAL_ENUM - -#define R_SYNC_SERIAL3_CTRL__tr_baud__tr_baud__c115k2Hz 10 -#define R_SYNC_SERIAL3_CTRL__tr_baud__tr_baud__c1200Hz 3 -#define R_SYNC_SERIAL3_CTRL__tr_baud__tr_baud__c150Hz 0 -#define R_SYNC_SERIAL3_CTRL__tr_baud__tr_baud__c19k2Hz 7 -#define R_SYNC_SERIAL3_CTRL__tr_baud__tr_baud__c230k4Hz 11 -#define R_SYNC_SERIAL3_CTRL__tr_baud__tr_baud__c2400Hz 4 -#define R_SYNC_SERIAL3_CTRL__tr_baud__tr_baud__c28k8Hz 8 -#define R_SYNC_SERIAL3_CTRL__tr_baud__tr_baud__c300Hz 1 -#define R_SYNC_SERIAL3_CTRL__tr_baud__tr_baud__c3125kHz 14 -#define R_SYNC_SERIAL3_CTRL__tr_baud__tr_baud__c460k8Hz 12 -#define R_SYNC_SERIAL3_CTRL__tr_baud__tr_baud__c4800Hz 5 -#define R_SYNC_SERIAL3_CTRL__tr_baud__tr_baud__c57k6Hz 9 -#define R_SYNC_SERIAL3_CTRL__tr_baud__tr_baud__c600Hz 2 -#define R_SYNC_SERIAL3_CTRL__tr_baud__tr_baud__c921k6Hz 13 -#define R_SYNC_SERIAL3_CTRL__tr_baud__tr_baud__c9600Hz 6 -#define R_SYNC_SERIAL3_CTRL__dma_enable__dma_enable__off 0 -#define R_SYNC_SERIAL3_CTRL__dma_enable__dma_enable__on 1 -#define R_SYNC_SERIAL3_CTRL__mode__mode__master_bidir 4 -#define R_SYNC_SERIAL3_CTRL__mode__mode__master_input 2 -#define R_SYNC_SERIAL3_CTRL__mode__mode__master_output 0 -#define R_SYNC_SERIAL3_CTRL__mode__mode__slave_bidir 5 -#define R_SYNC_SERIAL3_CTRL__mode__mode__slave_input 3 -#define R_SYNC_SERIAL3_CTRL__mode__mode__slave_output 1 -#define R_SYNC_SERIAL3_CTRL__error__error__ignore 1 -#define R_SYNC_SERIAL3_CTRL__error__error__normal 0 -#define R_SYNC_SERIAL3_CTRL__rec_enable__rec_enable__disable 0 -#define R_SYNC_SERIAL3_CTRL__rec_enable__rec_enable__enable 1 -#define R_SYNC_SERIAL3_CTRL__f_synctype__f_synctype__early 1 -#define R_SYNC_SERIAL3_CTRL__f_synctype__f_synctype__normal 0 -#define R_SYNC_SERIAL3_CTRL__f_syncsize__f_syncsize__bit 0 -#define R_SYNC_SERIAL3_CTRL__f_syncsize__f_syncsize__extended 2 -#define R_SYNC_SERIAL3_CTRL__f_syncsize__f_syncsize__word 1 -#define R_SYNC_SERIAL3_CTRL__f_sync__f_sync__off 1 -#define R_SYNC_SERIAL3_CTRL__f_sync__f_sync__on 0 -#define R_SYNC_SERIAL3_CTRL__clk_mode__clk_mode__gated 1 -#define R_SYNC_SERIAL3_CTRL__clk_mode__clk_mode__normal 0 -#define R_SYNC_SERIAL3_CTRL__clk_halt__clk_halt__running 0 -#define R_SYNC_SERIAL3_CTRL__clk_halt__clk_halt__stopped 1 -#define R_SYNC_SERIAL3_CTRL__bitorder__bitorder__lsb 0 -#define R_SYNC_SERIAL3_CTRL__bitorder__bitorder__msb 1 -#define R_SYNC_SERIAL3_CTRL__tr_enable__tr_enable__disable 0 -#define R_SYNC_SERIAL3_CTRL__tr_enable__tr_enable__enable 1 -#define R_SYNC_SERIAL3_CTRL__wordsize__wordsize__size12bit 1 -#define R_SYNC_SERIAL3_CTRL__wordsize__wordsize__size16bit 2 -#define R_SYNC_SERIAL3_CTRL__wordsize__wordsize__size24bit 3 -#define R_SYNC_SERIAL3_CTRL__wordsize__wordsize__size32bit 4 -#define R_SYNC_SERIAL3_CTRL__wordsize__wordsize__size8bit 0 -#define R_SYNC_SERIAL3_CTRL__buf_empty__buf_empty__lmt_0 1 -#define R_SYNC_SERIAL3_CTRL__buf_empty__buf_empty__lmt_8 0 -#define R_SYNC_SERIAL3_CTRL__buf_full__buf_full__lmt_32 0 -#define R_SYNC_SERIAL3_CTRL__buf_full__buf_full__lmt_8 1 -#define R_SYNC_SERIAL3_CTRL__flow_ctrl__flow_ctrl__disabled 0 -#define R_SYNC_SERIAL3_CTRL__flow_ctrl__flow_ctrl__enabled 1 -#define R_SYNC_SERIAL3_CTRL__clk_polarity__clk_polarity__neg 1 -#define R_SYNC_SERIAL3_CTRL__clk_polarity__clk_polarity__pos 0 -#define R_SYNC_SERIAL3_CTRL__frame_polarity__frame_polarity__inverted 1 -#define R_SYNC_SERIAL3_CTRL__frame_polarity__frame_polarity__normal 0 -#define R_SYNC_SERIAL3_CTRL__status_polarity__status_polarity__inverted 1 -#define R_SYNC_SERIAL3_CTRL__status_polarity__status_polarity__normal 0 -#define R_SYNC_SERIAL3_CTRL__clk_driver__clk_driver__inverted 1 -#define R_SYNC_SERIAL3_CTRL__clk_driver__clk_driver__normal 0 -#define R_SYNC_SERIAL3_CTRL__frame_driver__frame_driver__inverted 1 -#define R_SYNC_SERIAL3_CTRL__frame_driver__frame_driver__normal 0 -#define R_SYNC_SERIAL3_CTRL__status_driver__status_driver__inverted 1 -#define R_SYNC_SERIAL3_CTRL__status_driver__status_driver__normal 0 -#define R_SYNC_SERIAL3_CTRL__def_out0__def_out0__high 1 -#define R_SYNC_SERIAL3_CTRL__def_out0__def_out0__low 0 - -#endif - -/* - * R_SYNC_SERIAL3_REC_BYTE - * - type: RO - * - addr: 0xb000007c - * - group: Syncrounous serial port registers - */ - -#if USE_GROUP__Syncrounous_serial_port_registers - -#define R_SYNC_SERIAL3_REC_BYTE__ADDR (REG_TYPECAST_BYTE 0xb000007c) -#define R_SYNC_SERIAL3_REC_BYTE__SVAL REG_SVAL_SHADOW -#define R_SYNC_SERIAL3_REC_BYTE__SVAL_I REG_SVAL_I_SHADOW -#define R_SYNC_SERIAL3_REC_BYTE__TYPECAST REG_TYPECAST_BYTE -#define R_SYNC_SERIAL3_REC_BYTE__TYPE (REG_BYTE) -#define R_SYNC_SERIAL3_REC_BYTE__GET REG_GET_RO -#define R_SYNC_SERIAL3_REC_BYTE__IGET REG_IGET_RO -#define R_SYNC_SERIAL3_REC_BYTE__SET REG_SET_RO -#define R_SYNC_SERIAL3_REC_BYTE__ISET REG_ISET_RO -#define R_SYNC_SERIAL3_REC_BYTE__SET_VAL REG_SET_VAL_RO -#define R_SYNC_SERIAL3_REC_BYTE__EQL REG_EQL_RO -#define R_SYNC_SERIAL3_REC_BYTE__IEQL REG_IEQL_RO -#define R_SYNC_SERIAL3_REC_BYTE__RD REG_RD_RO -#define R_SYNC_SERIAL3_REC_BYTE__IRD REG_IRD_RO -#define R_SYNC_SERIAL3_REC_BYTE__WR REG_WR_RO -#define R_SYNC_SERIAL3_REC_BYTE__IWR REG_IWR_RO - -#define R_SYNC_SERIAL3_REC_BYTE__READ(addr) \ - (*(addr)) - -#define R_SYNC_SERIAL3_REC_BYTE__data_in__data_in__MASK 0x000000ffU - -#define R_SYNC_SERIAL3_REC_BYTE__data_in__MAX 0xff - -#define R_SYNC_SERIAL3_REC_BYTE__data_in__MIN 0 - -#define R_SYNC_SERIAL3_REC_BYTE__data_in__BITNR 0 - -#define R_SYNC_SERIAL3_REC_BYTE__data_in__data_in__VAL REG_VAL_VAL - - -#endif - -/* - * R_SYNC_SERIAL3_REC_DATA - * - type: RO - * - addr: 0xb000007c - * - group: Syncrounous serial port registers - */ - -#if USE_GROUP__Syncrounous_serial_port_registers - -#define R_SYNC_SERIAL3_REC_DATA__ADDR (REG_TYPECAST_UDWORD 0xb000007c) -#define R_SYNC_SERIAL3_REC_DATA__SVAL REG_SVAL_SHADOW -#define R_SYNC_SERIAL3_REC_DATA__SVAL_I REG_SVAL_I_SHADOW -#define R_SYNC_SERIAL3_REC_DATA__TYPECAST REG_TYPECAST_UDWORD -#define R_SYNC_SERIAL3_REC_DATA__TYPE (REG_UDWORD) -#define R_SYNC_SERIAL3_REC_DATA__GET REG_GET_RO -#define R_SYNC_SERIAL3_REC_DATA__IGET REG_IGET_RO -#define R_SYNC_SERIAL3_REC_DATA__SET REG_SET_RO -#define R_SYNC_SERIAL3_REC_DATA__ISET REG_ISET_RO -#define R_SYNC_SERIAL3_REC_DATA__SET_VAL REG_SET_VAL_RO -#define R_SYNC_SERIAL3_REC_DATA__EQL REG_EQL_RO -#define R_SYNC_SERIAL3_REC_DATA__IEQL REG_IEQL_RO -#define R_SYNC_SERIAL3_REC_DATA__RD REG_RD_RO -#define R_SYNC_SERIAL3_REC_DATA__IRD REG_IRD_RO -#define R_SYNC_SERIAL3_REC_DATA__WR REG_WR_RO -#define R_SYNC_SERIAL3_REC_DATA__IWR REG_IWR_RO - -#define R_SYNC_SERIAL3_REC_DATA__READ(addr) \ - (*(addr)) - -#define R_SYNC_SERIAL3_REC_DATA__data_in__data_in__MASK 0xffffffffU - -#define R_SYNC_SERIAL3_REC_DATA__data_in__MAX 0xffffffff - -#define R_SYNC_SERIAL3_REC_DATA__data_in__MIN 0 - -#define R_SYNC_SERIAL3_REC_DATA__data_in__BITNR 0 - -#define R_SYNC_SERIAL3_REC_DATA__data_in__data_in__VAL REG_VAL_VAL - - -#endif - -/* - * R_SYNC_SERIAL3_REC_WORD - * - type: RO - * - addr: 0xb000007c - * - group: Syncrounous serial port registers - */ - -#if USE_GROUP__Syncrounous_serial_port_registers - -#define R_SYNC_SERIAL3_REC_WORD__ADDR (REG_TYPECAST_UWORD 0xb000007c) -#define R_SYNC_SERIAL3_REC_WORD__SVAL REG_SVAL_SHADOW -#define R_SYNC_SERIAL3_REC_WORD__SVAL_I REG_SVAL_I_SHADOW -#define R_SYNC_SERIAL3_REC_WORD__TYPECAST REG_TYPECAST_UWORD -#define R_SYNC_SERIAL3_REC_WORD__TYPE (REG_UWORD) -#define R_SYNC_SERIAL3_REC_WORD__GET REG_GET_RO -#define R_SYNC_SERIAL3_REC_WORD__IGET REG_IGET_RO -#define R_SYNC_SERIAL3_REC_WORD__SET REG_SET_RO -#define R_SYNC_SERIAL3_REC_WORD__ISET REG_ISET_RO -#define R_SYNC_SERIAL3_REC_WORD__SET_VAL REG_SET_VAL_RO -#define R_SYNC_SERIAL3_REC_WORD__EQL REG_EQL_RO -#define R_SYNC_SERIAL3_REC_WORD__IEQL REG_IEQL_RO -#define R_SYNC_SERIAL3_REC_WORD__RD REG_RD_RO -#define R_SYNC_SERIAL3_REC_WORD__IRD REG_IRD_RO -#define R_SYNC_SERIAL3_REC_WORD__WR REG_WR_RO -#define R_SYNC_SERIAL3_REC_WORD__IWR REG_IWR_RO - -#define R_SYNC_SERIAL3_REC_WORD__READ(addr) \ - (*(addr)) - -#define R_SYNC_SERIAL3_REC_WORD__data_in__data_in__MASK 0x0000ffffU - -#define R_SYNC_SERIAL3_REC_WORD__data_in__MAX 0xffff - -#define R_SYNC_SERIAL3_REC_WORD__data_in__MIN 0 - -#define R_SYNC_SERIAL3_REC_WORD__data_in__BITNR 0 - -#define R_SYNC_SERIAL3_REC_WORD__data_in__data_in__VAL REG_VAL_VAL - - -#endif - -/* - * R_SYNC_SERIAL3_STATUS - * - type: RO - * - addr: 0xb0000078 - * - group: Syncrounous serial port registers - */ - -#if USE_GROUP__Syncrounous_serial_port_registers - -#define R_SYNC_SERIAL3_STATUS__ADDR (REG_TYPECAST_UDWORD 0xb0000078) -#define R_SYNC_SERIAL3_STATUS__SVAL REG_SVAL_SHADOW -#define R_SYNC_SERIAL3_STATUS__SVAL_I REG_SVAL_I_SHADOW -#define R_SYNC_SERIAL3_STATUS__TYPECAST REG_TYPECAST_UDWORD -#define R_SYNC_SERIAL3_STATUS__TYPE (REG_UDWORD) -#define R_SYNC_SERIAL3_STATUS__GET REG_GET_RO -#define R_SYNC_SERIAL3_STATUS__IGET REG_IGET_RO -#define R_SYNC_SERIAL3_STATUS__SET REG_SET_RO -#define R_SYNC_SERIAL3_STATUS__ISET REG_ISET_RO -#define R_SYNC_SERIAL3_STATUS__SET_VAL REG_SET_VAL_RO -#define R_SYNC_SERIAL3_STATUS__EQL REG_EQL_RO -#define R_SYNC_SERIAL3_STATUS__IEQL REG_IEQL_RO -#define R_SYNC_SERIAL3_STATUS__RD REG_RD_RO -#define R_SYNC_SERIAL3_STATUS__IRD REG_IRD_RO -#define R_SYNC_SERIAL3_STATUS__WR REG_WR_RO -#define R_SYNC_SERIAL3_STATUS__IWR REG_IWR_RO - -#define R_SYNC_SERIAL3_STATUS__READ(addr) \ - (*(addr)) - -#define R_SYNC_SERIAL3_STATUS__rec_status__rec_status__MASK 0x00008000U -#define R_SYNC_SERIAL3_STATUS__tr_empty__tr_empty__MASK 0x00004000U -#define R_SYNC_SERIAL3_STATUS__tr_ready__tr_ready__MASK 0x00002000U -#define R_SYNC_SERIAL3_STATUS__pin_1__pin_1__MASK 0x00001000U -#define R_SYNC_SERIAL3_STATUS__pin_0__pin_0__MASK 0x00000800U -#define R_SYNC_SERIAL3_STATUS__underflow__underflow__MASK 0x00000400U -#define R_SYNC_SERIAL3_STATUS__overrun__overrun__MASK 0x00000200U -#define R_SYNC_SERIAL3_STATUS__data_avail__data_avail__MASK 0x00000100U -#define R_SYNC_SERIAL3_STATUS__data__data__MASK 0x000000ffU - -#define R_SYNC_SERIAL3_STATUS__rec_status__MAX 0x1 -#define R_SYNC_SERIAL3_STATUS__tr_empty__MAX 0x1 -#define R_SYNC_SERIAL3_STATUS__tr_ready__MAX 0x1 -#define R_SYNC_SERIAL3_STATUS__pin_1__MAX 0x1 -#define R_SYNC_SERIAL3_STATUS__pin_0__MAX 0x1 -#define R_SYNC_SERIAL3_STATUS__underflow__MAX 0x1 -#define R_SYNC_SERIAL3_STATUS__overrun__MAX 0x1 -#define R_SYNC_SERIAL3_STATUS__data_avail__MAX 0x1 -#define R_SYNC_SERIAL3_STATUS__data__MAX 0xff - -#define R_SYNC_SERIAL3_STATUS__rec_status__MIN 0 -#define R_SYNC_SERIAL3_STATUS__tr_empty__MIN 0 -#define R_SYNC_SERIAL3_STATUS__tr_ready__MIN 0 -#define R_SYNC_SERIAL3_STATUS__pin_1__MIN 0 -#define R_SYNC_SERIAL3_STATUS__pin_0__MIN 0 -#define R_SYNC_SERIAL3_STATUS__underflow__MIN 0 -#define R_SYNC_SERIAL3_STATUS__overrun__MIN 0 -#define R_SYNC_SERIAL3_STATUS__data_avail__MIN 0 -#define R_SYNC_SERIAL3_STATUS__data__MIN 0 - -#define R_SYNC_SERIAL3_STATUS__rec_status__BITNR 15 -#define R_SYNC_SERIAL3_STATUS__tr_empty__BITNR 14 -#define R_SYNC_SERIAL3_STATUS__tr_ready__BITNR 13 -#define R_SYNC_SERIAL3_STATUS__pin_1__BITNR 12 -#define R_SYNC_SERIAL3_STATUS__pin_0__BITNR 11 -#define R_SYNC_SERIAL3_STATUS__underflow__BITNR 10 -#define R_SYNC_SERIAL3_STATUS__overrun__BITNR 9 -#define R_SYNC_SERIAL3_STATUS__data_avail__BITNR 8 -#define R_SYNC_SERIAL3_STATUS__data__BITNR 0 - -#define R_SYNC_SERIAL3_STATUS__rec_status__rec_status__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL3_STATUS__tr_empty__tr_empty__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL3_STATUS__tr_ready__tr_ready__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL3_STATUS__pin_1__pin_1__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL3_STATUS__pin_0__pin_0__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL3_STATUS__underflow__underflow__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL3_STATUS__overrun__overrun__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL3_STATUS__data_avail__data_avail__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL3_STATUS__data__data__VAL REG_VAL_VAL - -#define R_SYNC_SERIAL3_STATUS__rec_status__rec_status__idle 1 -#define R_SYNC_SERIAL3_STATUS__rec_status__rec_status__running 0 -#define R_SYNC_SERIAL3_STATUS__tr_empty__tr_empty__empty 1 -#define R_SYNC_SERIAL3_STATUS__tr_empty__tr_empty__not_empty 0 -#define R_SYNC_SERIAL3_STATUS__tr_ready__tr_ready__full 0 -#define R_SYNC_SERIAL3_STATUS__tr_ready__tr_ready__ready 1 -#define R_SYNC_SERIAL3_STATUS__pin_1__pin_1__high 1 -#define R_SYNC_SERIAL3_STATUS__pin_1__pin_1__low 0 -#define R_SYNC_SERIAL3_STATUS__pin_0__pin_0__high 1 -#define R_SYNC_SERIAL3_STATUS__pin_0__pin_0__low 0 -#define R_SYNC_SERIAL3_STATUS__underflow__underflow__no 0 -#define R_SYNC_SERIAL3_STATUS__underflow__underflow__yes 1 -#define R_SYNC_SERIAL3_STATUS__overrun__overrun__no 0 -#define R_SYNC_SERIAL3_STATUS__overrun__overrun__yes 1 -#define R_SYNC_SERIAL3_STATUS__data_avail__data_avail__no 0 -#define R_SYNC_SERIAL3_STATUS__data_avail__data_avail__yes 1 - -#endif - -/* - * R_SYNC_SERIAL3_TR_BYTE - * - type: WO - * - addr: 0xb000007c - * - group: Syncrounous serial port registers - */ - -#if USE_GROUP__Syncrounous_serial_port_registers - -#define R_SYNC_SERIAL3_TR_BYTE__ADDR (REG_TYPECAST_BYTE 0xb000007c) - -#ifndef REG_NO_SHADOW -#define R_SYNC_SERIAL3_TR_BYTE__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL3_XOFF + 0)) -#define R_SYNC_SERIAL3_TR_BYTE__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL3_XOFF + 0)) -#else /* REG_NO_SHADOW */ -#define R_SYNC_SERIAL3_TR_BYTE__SADDR (REG_STYPECAST_BYTE (®_shadow__hwregs)) -#define R_SYNC_SERIAL3_TR_BYTE__IADDR (REG_STYPECAST_BYTE (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_SYNC_SERIAL3_TR_BYTE__STYPECAST REG_STYPECAST_BYTE -#define R_SYNC_SERIAL3_TR_BYTE__SVAL REG_SVAL_SHADOW -#define R_SYNC_SERIAL3_TR_BYTE__SVAL_I REG_SVAL_I_SHADOW -#define R_SYNC_SERIAL3_TR_BYTE__TYPECAST REG_TYPECAST_BYTE -#define R_SYNC_SERIAL3_TR_BYTE__TYPE (REG_BYTE) -#define R_SYNC_SERIAL3_TR_BYTE__GET REG_GET_WO -#define R_SYNC_SERIAL3_TR_BYTE__IGET REG_IGET_WO -#define R_SYNC_SERIAL3_TR_BYTE__SET REG_SET_WO -#define R_SYNC_SERIAL3_TR_BYTE__ISET REG_ISET_WO -#define R_SYNC_SERIAL3_TR_BYTE__SET_VAL REG_SET_VAL_WO -#define R_SYNC_SERIAL3_TR_BYTE__EQL REG_EQL_WO -#define R_SYNC_SERIAL3_TR_BYTE__IEQL REG_IEQL_WO -#define R_SYNC_SERIAL3_TR_BYTE__RD REG_RD_WO -#define R_SYNC_SERIAL3_TR_BYTE__IRD REG_IRD_WO -#define R_SYNC_SERIAL3_TR_BYTE__WR REG_WR_WO -#define R_SYNC_SERIAL3_TR_BYTE__IWR REG_IWR_WO - -#define R_SYNC_SERIAL3_TR_BYTE__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_SYNC_SERIAL3_TR_BYTE__data_out__data_out__MASK 0x000000ffU - -#define R_SYNC_SERIAL3_TR_BYTE__data_out__MAX 0xff - -#define R_SYNC_SERIAL3_TR_BYTE__data_out__MIN 0 - -#define R_SYNC_SERIAL3_TR_BYTE__data_out__BITNR 0 - -#define R_SYNC_SERIAL3_TR_BYTE__data_out__data_out__VAL REG_VAL_VAL - - -#endif - -/* - * R_SYNC_SERIAL3_TR_DATA - * - type: WO - * - addr: 0xb000007c - * - group: Syncrounous serial port registers - */ - -#if USE_GROUP__Syncrounous_serial_port_registers - -#define R_SYNC_SERIAL3_TR_DATA__ADDR (REG_TYPECAST_UDWORD 0xb000007c) - -#ifndef REG_NO_SHADOW -#define R_SYNC_SERIAL3_TR_DATA__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_SERIAL3_XOFF + 0)) -#define R_SYNC_SERIAL3_TR_DATA__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_SERIAL3_XOFF + 0)) -#else /* REG_NO_SHADOW */ -#define R_SYNC_SERIAL3_TR_DATA__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_SYNC_SERIAL3_TR_DATA__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_SYNC_SERIAL3_TR_DATA__STYPECAST REG_STYPECAST_UDWORD -#define R_SYNC_SERIAL3_TR_DATA__SVAL REG_SVAL_SHADOW -#define R_SYNC_SERIAL3_TR_DATA__SVAL_I REG_SVAL_I_SHADOW -#define R_SYNC_SERIAL3_TR_DATA__TYPECAST REG_TYPECAST_UDWORD -#define R_SYNC_SERIAL3_TR_DATA__TYPE (REG_UDWORD) -#define R_SYNC_SERIAL3_TR_DATA__GET REG_GET_WO -#define R_SYNC_SERIAL3_TR_DATA__IGET REG_IGET_WO -#define R_SYNC_SERIAL3_TR_DATA__SET REG_SET_WO -#define R_SYNC_SERIAL3_TR_DATA__ISET REG_ISET_WO -#define R_SYNC_SERIAL3_TR_DATA__SET_VAL REG_SET_VAL_WO -#define R_SYNC_SERIAL3_TR_DATA__EQL REG_EQL_WO -#define R_SYNC_SERIAL3_TR_DATA__IEQL REG_IEQL_WO -#define R_SYNC_SERIAL3_TR_DATA__RD REG_RD_WO -#define R_SYNC_SERIAL3_TR_DATA__IRD REG_IRD_WO -#define R_SYNC_SERIAL3_TR_DATA__WR REG_WR_WO -#define R_SYNC_SERIAL3_TR_DATA__IWR REG_IWR_WO - -#define R_SYNC_SERIAL3_TR_DATA__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_SYNC_SERIAL3_TR_DATA__data_out__data_out__MASK 0xffffffffU - -#define R_SYNC_SERIAL3_TR_DATA__data_out__MAX 0xffffffff - -#define R_SYNC_SERIAL3_TR_DATA__data_out__MIN 0 - -#define R_SYNC_SERIAL3_TR_DATA__data_out__BITNR 0 - -#define R_SYNC_SERIAL3_TR_DATA__data_out__data_out__VAL REG_VAL_VAL - - -#endif - -/* - * R_SYNC_SERIAL3_TR_WORD - * - type: WO - * - addr: 0xb000007c - * - group: Syncrounous serial port registers - */ - -#if USE_GROUP__Syncrounous_serial_port_registers - -#define R_SYNC_SERIAL3_TR_WORD__ADDR (REG_TYPECAST_UWORD 0xb000007c) - -#ifndef REG_NO_SHADOW -#define R_SYNC_SERIAL3_TR_WORD__SADDR (REG_STYPECAST_UWORD (reg_shadow__hwregs.R_SERIAL3_XOFF + 0)) -#define R_SYNC_SERIAL3_TR_WORD__IADDR (REG_STYPECAST_UWORD (reg_initiated__hwregs.R_SERIAL3_XOFF + 0)) -#else /* REG_NO_SHADOW */ -#define R_SYNC_SERIAL3_TR_WORD__SADDR (REG_STYPECAST_UWORD (®_shadow__hwregs)) -#define R_SYNC_SERIAL3_TR_WORD__IADDR (REG_STYPECAST_UWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_SYNC_SERIAL3_TR_WORD__STYPECAST REG_STYPECAST_UWORD -#define R_SYNC_SERIAL3_TR_WORD__SVAL REG_SVAL_SHADOW -#define R_SYNC_SERIAL3_TR_WORD__SVAL_I REG_SVAL_I_SHADOW -#define R_SYNC_SERIAL3_TR_WORD__TYPECAST REG_TYPECAST_UWORD -#define R_SYNC_SERIAL3_TR_WORD__TYPE (REG_UWORD) -#define R_SYNC_SERIAL3_TR_WORD__GET REG_GET_WO -#define R_SYNC_SERIAL3_TR_WORD__IGET REG_IGET_WO -#define R_SYNC_SERIAL3_TR_WORD__SET REG_SET_WO -#define R_SYNC_SERIAL3_TR_WORD__ISET REG_ISET_WO -#define R_SYNC_SERIAL3_TR_WORD__SET_VAL REG_SET_VAL_WO -#define R_SYNC_SERIAL3_TR_WORD__EQL REG_EQL_WO -#define R_SYNC_SERIAL3_TR_WORD__IEQL REG_IEQL_WO -#define R_SYNC_SERIAL3_TR_WORD__RD REG_RD_WO -#define R_SYNC_SERIAL3_TR_WORD__IRD REG_IRD_WO -#define R_SYNC_SERIAL3_TR_WORD__WR REG_WR_WO -#define R_SYNC_SERIAL3_TR_WORD__IWR REG_IWR_WO - -#define R_SYNC_SERIAL3_TR_WORD__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_SYNC_SERIAL3_TR_WORD__data_out__data_out__MASK 0x0000ffffU - -#define R_SYNC_SERIAL3_TR_WORD__data_out__MAX 0xffff - -#define R_SYNC_SERIAL3_TR_WORD__data_out__MIN 0 - -#define R_SYNC_SERIAL3_TR_WORD__data_out__BITNR 0 - -#define R_SYNC_SERIAL3_TR_WORD__data_out__data_out__VAL REG_VAL_VAL - - -#endif - -/* - * R_SYNC_SERIAL_PRESCALE - * - type: WO - * - addr: 0xb00000f4 - * - group: Timer registers - */ - -#if USE_GROUP__Timer_registers - -#define R_SYNC_SERIAL_PRESCALE__ADDR (REG_TYPECAST_UDWORD 0xb00000f4) - -#ifndef REG_NO_SHADOW -#define R_SYNC_SERIAL_PRESCALE__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_SYNC_SERIAL_PRESCALE + 0)) -#define R_SYNC_SERIAL_PRESCALE__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_SYNC_SERIAL_PRESCALE + 0)) -#else /* REG_NO_SHADOW */ -#define R_SYNC_SERIAL_PRESCALE__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_SYNC_SERIAL_PRESCALE__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_SYNC_SERIAL_PRESCALE__STYPECAST REG_STYPECAST_UDWORD -#define R_SYNC_SERIAL_PRESCALE__SVAL REG_SVAL_SHADOW -#define R_SYNC_SERIAL_PRESCALE__SVAL_I REG_SVAL_I_SHADOW -#define R_SYNC_SERIAL_PRESCALE__TYPECAST REG_TYPECAST_UDWORD -#define R_SYNC_SERIAL_PRESCALE__TYPE (REG_UDWORD) -#define R_SYNC_SERIAL_PRESCALE__GET REG_GET_WO -#define R_SYNC_SERIAL_PRESCALE__IGET REG_IGET_WO -#define R_SYNC_SERIAL_PRESCALE__SET REG_SET_WO -#define R_SYNC_SERIAL_PRESCALE__ISET REG_ISET_WO -#define R_SYNC_SERIAL_PRESCALE__SET_VAL REG_SET_VAL_WO -#define R_SYNC_SERIAL_PRESCALE__EQL REG_EQL_WO -#define R_SYNC_SERIAL_PRESCALE__IEQL REG_IEQL_WO -#define R_SYNC_SERIAL_PRESCALE__RD REG_RD_WO -#define R_SYNC_SERIAL_PRESCALE__IRD REG_IRD_WO -#define R_SYNC_SERIAL_PRESCALE__WR REG_WR_WO -#define R_SYNC_SERIAL_PRESCALE__IWR REG_IWR_WO - -#define R_SYNC_SERIAL_PRESCALE__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__clk_sel_u3__MASK 0x00800000U -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__word_stb_sel_u3__MASK 0x00400000U -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__clk_sel_u1__MASK 0x00200000U -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__word_stb_sel_u1__MASK 0x00100000U -#define R_SYNC_SERIAL_PRESCALE__prescaler__prescaler__MASK 0x00070000U -#define R_SYNC_SERIAL_PRESCALE__warp_mode__warp_mode__MASK 0x00008000U -#define R_SYNC_SERIAL_PRESCALE__frame_rate__frame_rate__MASK 0x00007800U -#define R_SYNC_SERIAL_PRESCALE__word_rate__word_rate__MASK 0x000003ffU - -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__MAX 0x1 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__MAX 0x1 -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__MAX 0x1 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__MAX 0x1 -#define R_SYNC_SERIAL_PRESCALE__prescaler__MAX 0x7 -#define R_SYNC_SERIAL_PRESCALE__warp_mode__MAX 0x1 -#define R_SYNC_SERIAL_PRESCALE__frame_rate__MAX 0xf -#define R_SYNC_SERIAL_PRESCALE__word_rate__MAX 0x3ff - -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__MIN 0 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__MIN 0 -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__MIN 0 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__MIN 0 -#define R_SYNC_SERIAL_PRESCALE__prescaler__MIN 0 -#define R_SYNC_SERIAL_PRESCALE__warp_mode__MIN 0 -#define R_SYNC_SERIAL_PRESCALE__frame_rate__MIN 0 -#define R_SYNC_SERIAL_PRESCALE__word_rate__MIN 0 - -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__BITNR 23 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__BITNR 22 -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__BITNR 21 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__BITNR 20 -#define R_SYNC_SERIAL_PRESCALE__prescaler__BITNR 16 -#define R_SYNC_SERIAL_PRESCALE__warp_mode__BITNR 15 -#define R_SYNC_SERIAL_PRESCALE__frame_rate__BITNR 11 -#define R_SYNC_SERIAL_PRESCALE__word_rate__BITNR 0 - -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__clk_sel_u3__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__word_stb_sel_u3__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__clk_sel_u1__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__word_stb_sel_u1__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL_PRESCALE__prescaler__prescaler__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL_PRESCALE__warp_mode__warp_mode__VAL REG_VAL_ENUM -#define R_SYNC_SERIAL_PRESCALE__frame_rate__frame_rate__VAL REG_VAL_VAL -#define R_SYNC_SERIAL_PRESCALE__word_rate__word_rate__VAL REG_VAL_VAL - -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__clk_sel_u3__baudrate 1 -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__clk_sel_u3__codec 0 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__word_stb_sel_u3__external 0 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__word_stb_sel_u3__internal 1 -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__clk_sel_u1__baudrate 1 -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__clk_sel_u1__codec 0 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__word_stb_sel_u1__external 0 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__word_stb_sel_u1__internal 1 -#define R_SYNC_SERIAL_PRESCALE__prescaler__prescaler__div1 0 -#define R_SYNC_SERIAL_PRESCALE__prescaler__prescaler__div128 7 -#define R_SYNC_SERIAL_PRESCALE__prescaler__prescaler__div16 4 -#define R_SYNC_SERIAL_PRESCALE__prescaler__prescaler__div2 1 -#define R_SYNC_SERIAL_PRESCALE__prescaler__prescaler__div32 5 -#define R_SYNC_SERIAL_PRESCALE__prescaler__prescaler__div4 2 -#define R_SYNC_SERIAL_PRESCALE__prescaler__prescaler__div64 6 -#define R_SYNC_SERIAL_PRESCALE__prescaler__prescaler__div8 3 -#define R_SYNC_SERIAL_PRESCALE__warp_mode__warp_mode__enabled 1 -#define R_SYNC_SERIAL_PRESCALE__warp_mode__warp_mode__normal 0 - -#endif - -/* - * R_TEST_MODE - * - type: WO - * - addr: 0xb00000fc - * - group: Test mode registers - */ - -#if USE_GROUP__Test_mode_registers - -#define R_TEST_MODE__ADDR (REG_TYPECAST_UDWORD 0xb00000fc) - -#ifndef REG_NO_SHADOW -#define R_TEST_MODE__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_TEST_MODE + 0)) -#define R_TEST_MODE__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_TEST_MODE + 0)) -#else /* REG_NO_SHADOW */ -#define R_TEST_MODE__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_TEST_MODE__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_TEST_MODE__STYPECAST REG_STYPECAST_UDWORD -#define R_TEST_MODE__SVAL REG_SVAL_SHADOW -#define R_TEST_MODE__SVAL_I REG_SVAL_I_SHADOW -#define R_TEST_MODE__TYPECAST REG_TYPECAST_UDWORD -#define R_TEST_MODE__TYPE (REG_UDWORD) -#define R_TEST_MODE__GET REG_GET_WO -#define R_TEST_MODE__IGET REG_IGET_WO -#define R_TEST_MODE__SET REG_SET_WO -#define R_TEST_MODE__ISET REG_ISET_WO -#define R_TEST_MODE__SET_VAL REG_SET_VAL_WO -#define R_TEST_MODE__EQL REG_EQL_WO -#define R_TEST_MODE__IEQL REG_IEQL_WO -#define R_TEST_MODE__RD REG_RD_WO -#define R_TEST_MODE__IRD REG_IRD_WO -#define R_TEST_MODE__WR REG_WR_WO -#define R_TEST_MODE__IWR REG_IWR_WO - -#define R_TEST_MODE__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_TEST_MODE__single_step__single_step__MASK 0x00080000U -#define R_TEST_MODE__step_wr__step_wr__MASK 0x00040000U -#define R_TEST_MODE__step_rd__step_rd__MASK 0x00020000U -#define R_TEST_MODE__step_fetch__step_fetch__MASK 0x00010000U -#define R_TEST_MODE__mmu_test__mmu_test__MASK 0x00001000U -#define R_TEST_MODE__usb_test__usb_test__MASK 0x00000800U -#define R_TEST_MODE__scsi_timer_test__scsi_timer_test__MASK 0x00000400U -#define R_TEST_MODE__backoff__backoff__MASK 0x00000200U -#define R_TEST_MODE__snmp_test__snmp_test__MASK 0x00000100U -#define R_TEST_MODE__snmp_inc__snmp_inc__MASK 0x00000080U -#define R_TEST_MODE__ser_loop__ser_loop__MASK 0x00000040U -#define R_TEST_MODE__baudrate__baudrate__MASK 0x00000020U -#define R_TEST_MODE__timer__timer__MASK 0x00000018U -#define R_TEST_MODE__cache_test__cache_test__MASK 0x00000004U -#define R_TEST_MODE__tag_test__tag_test__MASK 0x00000002U -#define R_TEST_MODE__cache_enable__cache_enable__MASK 0x00000001U - -#define R_TEST_MODE__single_step__MAX 0x1 -#define R_TEST_MODE__step_wr__MAX 0x1 -#define R_TEST_MODE__step_rd__MAX 0x1 -#define R_TEST_MODE__step_fetch__MAX 0x1 -#define R_TEST_MODE__mmu_test__MAX 0x1 -#define R_TEST_MODE__usb_test__MAX 0x1 -#define R_TEST_MODE__scsi_timer_test__MAX 0x1 -#define R_TEST_MODE__backoff__MAX 0x1 -#define R_TEST_MODE__snmp_test__MAX 0x1 -#define R_TEST_MODE__snmp_inc__MAX 0x1 -#define R_TEST_MODE__ser_loop__MAX 0x1 -#define R_TEST_MODE__baudrate__MAX 0x1 -#define R_TEST_MODE__timer__MAX 0x3 -#define R_TEST_MODE__cache_test__MAX 0x1 -#define R_TEST_MODE__tag_test__MAX 0x1 -#define R_TEST_MODE__cache_enable__MAX 0x1 - -#define R_TEST_MODE__single_step__MIN 0 -#define R_TEST_MODE__step_wr__MIN 0 -#define R_TEST_MODE__step_rd__MIN 0 -#define R_TEST_MODE__step_fetch__MIN 0 -#define R_TEST_MODE__mmu_test__MIN 0 -#define R_TEST_MODE__usb_test__MIN 0 -#define R_TEST_MODE__scsi_timer_test__MIN 0 -#define R_TEST_MODE__backoff__MIN 0 -#define R_TEST_MODE__snmp_test__MIN 0 -#define R_TEST_MODE__snmp_inc__MIN 0 -#define R_TEST_MODE__ser_loop__MIN 0 -#define R_TEST_MODE__baudrate__MIN 0 -#define R_TEST_MODE__timer__MIN 0 -#define R_TEST_MODE__cache_test__MIN 0 -#define R_TEST_MODE__tag_test__MIN 0 -#define R_TEST_MODE__cache_enable__MIN 0 - -#define R_TEST_MODE__single_step__BITNR 19 -#define R_TEST_MODE__step_wr__BITNR 18 -#define R_TEST_MODE__step_rd__BITNR 17 -#define R_TEST_MODE__step_fetch__BITNR 16 -#define R_TEST_MODE__mmu_test__BITNR 12 -#define R_TEST_MODE__usb_test__BITNR 11 -#define R_TEST_MODE__scsi_timer_test__BITNR 10 -#define R_TEST_MODE__backoff__BITNR 9 -#define R_TEST_MODE__snmp_test__BITNR 8 -#define R_TEST_MODE__snmp_inc__BITNR 7 -#define R_TEST_MODE__ser_loop__BITNR 6 -#define R_TEST_MODE__baudrate__BITNR 5 -#define R_TEST_MODE__timer__BITNR 3 -#define R_TEST_MODE__cache_test__BITNR 2 -#define R_TEST_MODE__tag_test__BITNR 1 -#define R_TEST_MODE__cache_enable__BITNR 0 - -#define R_TEST_MODE__single_step__single_step__VAL REG_VAL_ENUM -#define R_TEST_MODE__step_wr__step_wr__VAL REG_VAL_ENUM -#define R_TEST_MODE__step_rd__step_rd__VAL REG_VAL_ENUM -#define R_TEST_MODE__step_fetch__step_fetch__VAL REG_VAL_ENUM -#define R_TEST_MODE__mmu_test__mmu_test__VAL REG_VAL_ENUM -#define R_TEST_MODE__usb_test__usb_test__VAL REG_VAL_ENUM -#define R_TEST_MODE__scsi_timer_test__scsi_timer_test__VAL REG_VAL_ENUM -#define R_TEST_MODE__backoff__backoff__VAL REG_VAL_ENUM -#define R_TEST_MODE__snmp_test__snmp_test__VAL REG_VAL_ENUM -#define R_TEST_MODE__snmp_inc__snmp_inc__VAL REG_VAL_ENUM -#define R_TEST_MODE__ser_loop__ser_loop__VAL REG_VAL_ENUM -#define R_TEST_MODE__baudrate__baudrate__VAL REG_VAL_ENUM -#define R_TEST_MODE__timer__timer__VAL REG_VAL_ENUM -#define R_TEST_MODE__cache_test__cache_test__VAL REG_VAL_ENUM -#define R_TEST_MODE__tag_test__tag_test__VAL REG_VAL_ENUM -#define R_TEST_MODE__cache_enable__cache_enable__VAL REG_VAL_ENUM - -#define R_TEST_MODE__single_step__single_step__off 0 -#define R_TEST_MODE__single_step__single_step__on 1 -#define R_TEST_MODE__step_wr__step_wr__off 0 -#define R_TEST_MODE__step_wr__step_wr__on 1 -#define R_TEST_MODE__step_rd__step_rd__off 0 -#define R_TEST_MODE__step_rd__step_rd__on 1 -#define R_TEST_MODE__step_fetch__step_fetch__off 0 -#define R_TEST_MODE__step_fetch__step_fetch__on 1 -#define R_TEST_MODE__mmu_test__mmu_test__off 0 -#define R_TEST_MODE__mmu_test__mmu_test__on 1 -#define R_TEST_MODE__usb_test__usb_test__off 0 -#define R_TEST_MODE__usb_test__usb_test__on 1 -#define R_TEST_MODE__scsi_timer_test__scsi_timer_test__off 0 -#define R_TEST_MODE__scsi_timer_test__scsi_timer_test__on 1 -#define R_TEST_MODE__backoff__backoff__off 0 -#define R_TEST_MODE__backoff__backoff__on 1 -#define R_TEST_MODE__snmp_test__snmp_test__off 0 -#define R_TEST_MODE__snmp_test__snmp_test__on 1 -#define R_TEST_MODE__snmp_inc__snmp_inc__do 1 -#define R_TEST_MODE__snmp_inc__snmp_inc__dont 0 -#define R_TEST_MODE__ser_loop__ser_loop__off 0 -#define R_TEST_MODE__ser_loop__ser_loop__on 1 -#define R_TEST_MODE__baudrate__baudrate__off 0 -#define R_TEST_MODE__baudrate__baudrate__on 1 -#define R_TEST_MODE__timer__timer__all 3 -#define R_TEST_MODE__timer__timer__even 1 -#define R_TEST_MODE__timer__timer__odd 2 -#define R_TEST_MODE__timer__timer__off 0 -#define R_TEST_MODE__cache_test__cache_test__normal 0 -#define R_TEST_MODE__cache_test__cache_test__test 1 -#define R_TEST_MODE__tag_test__tag_test__normal 0 -#define R_TEST_MODE__tag_test__tag_test__test 1 -#define R_TEST_MODE__cache_enable__cache_enable__disable 0 -#define R_TEST_MODE__cache_enable__cache_enable__enable 1 - -#endif - -/* - * R_TIMER01_DATA - * - type: RO - * - addr: 0xb0000022 - * - group: Timer registers - */ - -#if USE_GROUP__Timer_registers - -#define R_TIMER01_DATA__ADDR (REG_TYPECAST_UWORD 0xb0000022) -#define R_TIMER01_DATA__SVAL REG_SVAL_SHADOW -#define R_TIMER01_DATA__SVAL_I REG_SVAL_I_SHADOW -#define R_TIMER01_DATA__TYPECAST REG_TYPECAST_UWORD -#define R_TIMER01_DATA__TYPE (REG_UWORD) -#define R_TIMER01_DATA__GET REG_GET_RO -#define R_TIMER01_DATA__IGET REG_IGET_RO -#define R_TIMER01_DATA__SET REG_SET_RO -#define R_TIMER01_DATA__ISET REG_ISET_RO -#define R_TIMER01_DATA__SET_VAL REG_SET_VAL_RO -#define R_TIMER01_DATA__EQL REG_EQL_RO -#define R_TIMER01_DATA__IEQL REG_IEQL_RO -#define R_TIMER01_DATA__RD REG_RD_RO -#define R_TIMER01_DATA__IRD REG_IRD_RO -#define R_TIMER01_DATA__WR REG_WR_RO -#define R_TIMER01_DATA__IWR REG_IWR_RO - -#define R_TIMER01_DATA__READ(addr) \ - (*(addr)) - -#define R_TIMER01_DATA__count__count__MASK 0x0000ffffU - -#define R_TIMER01_DATA__count__MAX 0xffff - -#define R_TIMER01_DATA__count__MIN 0 - -#define R_TIMER01_DATA__count__BITNR 0 - -#define R_TIMER01_DATA__count__count__VAL REG_VAL_VAL - - -#endif - -/* - * R_TIMER0_DATA - * - type: RO - * - addr: 0xb0000022 - * - group: Timer registers - */ - -#if USE_GROUP__Timer_registers - -#define R_TIMER0_DATA__ADDR (REG_TYPECAST_BYTE 0xb0000022) -#define R_TIMER0_DATA__SVAL REG_SVAL_SHADOW -#define R_TIMER0_DATA__SVAL_I REG_SVAL_I_SHADOW -#define R_TIMER0_DATA__TYPECAST REG_TYPECAST_BYTE -#define R_TIMER0_DATA__TYPE (REG_BYTE) -#define R_TIMER0_DATA__GET REG_GET_RO -#define R_TIMER0_DATA__IGET REG_IGET_RO -#define R_TIMER0_DATA__SET REG_SET_RO -#define R_TIMER0_DATA__ISET REG_ISET_RO -#define R_TIMER0_DATA__SET_VAL REG_SET_VAL_RO -#define R_TIMER0_DATA__EQL REG_EQL_RO -#define R_TIMER0_DATA__IEQL REG_IEQL_RO -#define R_TIMER0_DATA__RD REG_RD_RO -#define R_TIMER0_DATA__IRD REG_IRD_RO -#define R_TIMER0_DATA__WR REG_WR_RO -#define R_TIMER0_DATA__IWR REG_IWR_RO - -#define R_TIMER0_DATA__READ(addr) \ - (*(addr)) - -#define R_TIMER0_DATA__count__count__MASK 0x000000ffU - -#define R_TIMER0_DATA__count__MAX 0xff - -#define R_TIMER0_DATA__count__MIN 0 - -#define R_TIMER0_DATA__count__BITNR 0 - -#define R_TIMER0_DATA__count__count__VAL REG_VAL_VAL - - -#endif - -/* - * R_TIMER1_DATA - * - type: RO - * - addr: 0xb0000023 - * - group: Timer registers - */ - -#if USE_GROUP__Timer_registers - -#define R_TIMER1_DATA__ADDR (REG_TYPECAST_BYTE 0xb0000023) -#define R_TIMER1_DATA__SVAL REG_SVAL_SHADOW -#define R_TIMER1_DATA__SVAL_I REG_SVAL_I_SHADOW -#define R_TIMER1_DATA__TYPECAST REG_TYPECAST_BYTE -#define R_TIMER1_DATA__TYPE (REG_BYTE) -#define R_TIMER1_DATA__GET REG_GET_RO -#define R_TIMER1_DATA__IGET REG_IGET_RO -#define R_TIMER1_DATA__SET REG_SET_RO -#define R_TIMER1_DATA__ISET REG_ISET_RO -#define R_TIMER1_DATA__SET_VAL REG_SET_VAL_RO -#define R_TIMER1_DATA__EQL REG_EQL_RO -#define R_TIMER1_DATA__IEQL REG_IEQL_RO -#define R_TIMER1_DATA__RD REG_RD_RO -#define R_TIMER1_DATA__IRD REG_IRD_RO -#define R_TIMER1_DATA__WR REG_WR_RO -#define R_TIMER1_DATA__IWR REG_IWR_RO - -#define R_TIMER1_DATA__READ(addr) \ - (*(addr)) - -#define R_TIMER1_DATA__count__count__MASK 0x000000ffU - -#define R_TIMER1_DATA__count__MAX 0xff - -#define R_TIMER1_DATA__count__MIN 0 - -#define R_TIMER1_DATA__count__BITNR 0 - -#define R_TIMER1_DATA__count__count__VAL REG_VAL_VAL - - -#endif - -/* - * R_TIMER_CTRL - * - type: WO - * - addr: 0xb0000020 - * - group: Timer registers - */ - -#if USE_GROUP__Timer_registers - -#define R_TIMER_CTRL__ADDR (REG_TYPECAST_UDWORD 0xb0000020) - -#ifndef REG_NO_SHADOW -#define R_TIMER_CTRL__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_TIMER_CTRL + 0)) -#define R_TIMER_CTRL__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_TIMER_CTRL + 0)) -#else /* REG_NO_SHADOW */ -#define R_TIMER_CTRL__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_TIMER_CTRL__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_TIMER_CTRL__STYPECAST REG_STYPECAST_UDWORD -#define R_TIMER_CTRL__SVAL REG_SVAL_SHADOW -#define R_TIMER_CTRL__SVAL_I REG_SVAL_I_SHADOW -#define R_TIMER_CTRL__TYPECAST REG_TYPECAST_UDWORD -#define R_TIMER_CTRL__TYPE (REG_UDWORD) -#define R_TIMER_CTRL__GET REG_GET_WO -#define R_TIMER_CTRL__IGET REG_IGET_WO -#define R_TIMER_CTRL__SET REG_SET_WO -#define R_TIMER_CTRL__ISET REG_ISET_WO -#define R_TIMER_CTRL__SET_VAL REG_SET_VAL_WO -#define R_TIMER_CTRL__EQL REG_EQL_WO -#define R_TIMER_CTRL__IEQL REG_IEQL_WO -#define R_TIMER_CTRL__RD REG_RD_WO -#define R_TIMER_CTRL__IRD REG_IRD_WO -#define R_TIMER_CTRL__WR REG_WR_WO -#define R_TIMER_CTRL__IWR REG_IWR_WO - -#define R_TIMER_CTRL__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_TIMER_CTRL__timerdiv1__timerdiv1__MASK 0xff000000U -#define R_TIMER_CTRL__timerdiv0__timerdiv0__MASK 0x00ff0000U -#define R_TIMER_CTRL__presc_timer1__presc_timer1__MASK 0x00008000U -#define R_TIMER_CTRL__i1__i1__MASK 0x00004000U -#define R_TIMER_CTRL__tm1__tm1__MASK 0x00003000U -#define R_TIMER_CTRL__clksel1__clksel1__MASK 0x00000f00U -#define R_TIMER_CTRL__presc_ext__presc_ext__MASK 0x00000080U -#define R_TIMER_CTRL__i0__i0__MASK 0x00000040U -#define R_TIMER_CTRL__tm0__tm0__MASK 0x00000030U -#define R_TIMER_CTRL__clksel0__clksel0__MASK 0x0000000fU - -#define R_TIMER_CTRL__timerdiv1__MAX 0xff -#define R_TIMER_CTRL__timerdiv0__MAX 0xff -#define R_TIMER_CTRL__presc_timer1__MAX 0x1 -#define R_TIMER_CTRL__i1__MAX 0x1 -#define R_TIMER_CTRL__tm1__MAX 0x3 -#define R_TIMER_CTRL__clksel1__MAX 0xf -#define R_TIMER_CTRL__presc_ext__MAX 0x1 -#define R_TIMER_CTRL__i0__MAX 0x1 -#define R_TIMER_CTRL__tm0__MAX 0x3 -#define R_TIMER_CTRL__clksel0__MAX 0xf - -#define R_TIMER_CTRL__timerdiv1__MIN 0 -#define R_TIMER_CTRL__timerdiv0__MIN 0 -#define R_TIMER_CTRL__presc_timer1__MIN 0 -#define R_TIMER_CTRL__i1__MIN 0 -#define R_TIMER_CTRL__tm1__MIN 0 -#define R_TIMER_CTRL__clksel1__MIN 0 -#define R_TIMER_CTRL__presc_ext__MIN 0 -#define R_TIMER_CTRL__i0__MIN 0 -#define R_TIMER_CTRL__tm0__MIN 0 -#define R_TIMER_CTRL__clksel0__MIN 0 - -#define R_TIMER_CTRL__timerdiv1__BITNR 24 -#define R_TIMER_CTRL__timerdiv0__BITNR 16 -#define R_TIMER_CTRL__presc_timer1__BITNR 15 -#define R_TIMER_CTRL__i1__BITNR 14 -#define R_TIMER_CTRL__tm1__BITNR 12 -#define R_TIMER_CTRL__clksel1__BITNR 8 -#define R_TIMER_CTRL__presc_ext__BITNR 7 -#define R_TIMER_CTRL__i0__BITNR 6 -#define R_TIMER_CTRL__tm0__BITNR 4 -#define R_TIMER_CTRL__clksel0__BITNR 0 - -#define R_TIMER_CTRL__timerdiv1__timerdiv1__VAL REG_VAL_VAL -#define R_TIMER_CTRL__timerdiv0__timerdiv0__VAL REG_VAL_VAL -#define R_TIMER_CTRL__presc_timer1__presc_timer1__VAL REG_VAL_ENUM -#define R_TIMER_CTRL__i1__i1__VAL REG_VAL_ENUM -#define R_TIMER_CTRL__tm1__tm1__VAL REG_VAL_ENUM -#define R_TIMER_CTRL__clksel1__clksel1__VAL REG_VAL_ENUM -#define R_TIMER_CTRL__presc_ext__presc_ext__VAL REG_VAL_ENUM -#define R_TIMER_CTRL__i0__i0__VAL REG_VAL_ENUM -#define R_TIMER_CTRL__tm0__tm0__VAL REG_VAL_ENUM -#define R_TIMER_CTRL__clksel0__clksel0__VAL REG_VAL_ENUM - -#define R_TIMER_CTRL__presc_timer1__presc_timer1__normal 0 -#define R_TIMER_CTRL__presc_timer1__presc_timer1__prescale 1 -#define R_TIMER_CTRL__i1__i1__clr 1 -#define R_TIMER_CTRL__i1__i1__nop 0 -#define R_TIMER_CTRL__tm1__tm1__freeze 1 -#define R_TIMER_CTRL__tm1__tm1__run 2 -#define R_TIMER_CTRL__tm1__tm1__stop_ld 0 -#define R_TIMER_CTRL__clksel1__clksel1__c115k2Hz 9 -#define R_TIMER_CTRL__clksel1__clksel1__c1200Hz 2 -#define R_TIMER_CTRL__clksel1__clksel1__c1843k2Hz 13 -#define R_TIMER_CTRL__clksel1__clksel1__c19k2Hz 6 -#define R_TIMER_CTRL__clksel1__clksel1__c230k4Hz 10 -#define R_TIMER_CTRL__clksel1__clksel1__c2400Hz 3 -#define R_TIMER_CTRL__clksel1__clksel1__c300Hz 0 -#define R_TIMER_CTRL__clksel1__clksel1__c38k4Hz 7 -#define R_TIMER_CTRL__clksel1__clksel1__c460k8Hz 11 -#define R_TIMER_CTRL__clksel1__clksel1__c4800Hz 4 -#define R_TIMER_CTRL__clksel1__clksel1__c57k6Hz 8 -#define R_TIMER_CTRL__clksel1__clksel1__c600Hz 1 -#define R_TIMER_CTRL__clksel1__clksel1__c6250kHz 14 -#define R_TIMER_CTRL__clksel1__clksel1__c921k6Hz 12 -#define R_TIMER_CTRL__clksel1__clksel1__c9600Hz 5 -#define R_TIMER_CTRL__clksel1__clksel1__cascade0 15 -#define R_TIMER_CTRL__presc_ext__presc_ext__external 1 -#define R_TIMER_CTRL__presc_ext__presc_ext__prescale 0 -#define R_TIMER_CTRL__i0__i0__clr 1 -#define R_TIMER_CTRL__i0__i0__nop 0 -#define R_TIMER_CTRL__tm0__tm0__freeze 1 -#define R_TIMER_CTRL__tm0__tm0__run 2 -#define R_TIMER_CTRL__tm0__tm0__stop_ld 0 -#define R_TIMER_CTRL__clksel0__clksel0__c115k2Hz 9 -#define R_TIMER_CTRL__clksel0__clksel0__c1200Hz 2 -#define R_TIMER_CTRL__clksel0__clksel0__c1843k2Hz 13 -#define R_TIMER_CTRL__clksel0__clksel0__c19k2Hz 6 -#define R_TIMER_CTRL__clksel0__clksel0__c230k4Hz 10 -#define R_TIMER_CTRL__clksel0__clksel0__c2400Hz 3 -#define R_TIMER_CTRL__clksel0__clksel0__c300Hz 0 -#define R_TIMER_CTRL__clksel0__clksel0__c38k4Hz 7 -#define R_TIMER_CTRL__clksel0__clksel0__c460k8Hz 11 -#define R_TIMER_CTRL__clksel0__clksel0__c4800Hz 4 -#define R_TIMER_CTRL__clksel0__clksel0__c57k6Hz 8 -#define R_TIMER_CTRL__clksel0__clksel0__c600Hz 1 -#define R_TIMER_CTRL__clksel0__clksel0__c6250kHz 14 -#define R_TIMER_CTRL__clksel0__clksel0__c921k6Hz 12 -#define R_TIMER_CTRL__clksel0__clksel0__c9600Hz 5 -#define R_TIMER_CTRL__clksel0__clksel0__flexible 15 - -#endif - -/* - * R_TIMER_DATA - * - type: RO - * - addr: 0xb0000020 - * - group: Timer registers - */ - -#if USE_GROUP__Timer_registers - -#define R_TIMER_DATA__ADDR (REG_TYPECAST_UDWORD 0xb0000020) -#define R_TIMER_DATA__SVAL REG_SVAL_SHADOW -#define R_TIMER_DATA__SVAL_I REG_SVAL_I_SHADOW -#define R_TIMER_DATA__TYPECAST REG_TYPECAST_UDWORD -#define R_TIMER_DATA__TYPE (REG_UDWORD) -#define R_TIMER_DATA__GET REG_GET_RO -#define R_TIMER_DATA__IGET REG_IGET_RO -#define R_TIMER_DATA__SET REG_SET_RO -#define R_TIMER_DATA__ISET REG_ISET_RO -#define R_TIMER_DATA__SET_VAL REG_SET_VAL_RO -#define R_TIMER_DATA__EQL REG_EQL_RO -#define R_TIMER_DATA__IEQL REG_IEQL_RO -#define R_TIMER_DATA__RD REG_RD_RO -#define R_TIMER_DATA__IRD REG_IRD_RO -#define R_TIMER_DATA__WR REG_WR_RO -#define R_TIMER_DATA__IWR REG_IWR_RO - -#define R_TIMER_DATA__READ(addr) \ - (*(addr)) - -#define R_TIMER_DATA__timer1__timer1__MASK 0xff000000U -#define R_TIMER_DATA__timer0__timer0__MASK 0x00ff0000U -#define R_TIMER_DATA__clkdiv_high__clkdiv_high__MASK 0x0000ff00U -#define R_TIMER_DATA__clkdiv_low__clkdiv_low__MASK 0x000000ffU - -#define R_TIMER_DATA__timer1__MAX 0xff -#define R_TIMER_DATA__timer0__MAX 0xff -#define R_TIMER_DATA__clkdiv_high__MAX 0xff -#define R_TIMER_DATA__clkdiv_low__MAX 0xff - -#define R_TIMER_DATA__timer1__MIN 0 -#define R_TIMER_DATA__timer0__MIN 0 -#define R_TIMER_DATA__clkdiv_high__MIN 0 -#define R_TIMER_DATA__clkdiv_low__MIN 0 - -#define R_TIMER_DATA__timer1__BITNR 24 -#define R_TIMER_DATA__timer0__BITNR 16 -#define R_TIMER_DATA__clkdiv_high__BITNR 8 -#define R_TIMER_DATA__clkdiv_low__BITNR 0 - -#define R_TIMER_DATA__timer1__timer1__VAL REG_VAL_VAL -#define R_TIMER_DATA__timer0__timer0__VAL REG_VAL_VAL -#define R_TIMER_DATA__clkdiv_high__clkdiv_high__VAL REG_VAL_VAL -#define R_TIMER_DATA__clkdiv_low__clkdiv_low__VAL REG_VAL_VAL - - -#endif - -/* - * R_TIMER_PRESCALE - * - type: WO - * - addr: 0xb00000f0 - * - group: Timer registers - */ - -#if USE_GROUP__Timer_registers - -#define R_TIMER_PRESCALE__ADDR (REG_TYPECAST_UWORD 0xb00000f0) - -#ifndef REG_NO_SHADOW -#define R_TIMER_PRESCALE__SADDR (REG_STYPECAST_UWORD (reg_shadow__hwregs.R_CLOCK_PRESCALE + 0)) -#define R_TIMER_PRESCALE__IADDR (REG_STYPECAST_UWORD (reg_initiated__hwregs.R_CLOCK_PRESCALE + 0)) -#else /* REG_NO_SHADOW */ -#define R_TIMER_PRESCALE__SADDR (REG_STYPECAST_UWORD (®_shadow__hwregs)) -#define R_TIMER_PRESCALE__IADDR (REG_STYPECAST_UWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_TIMER_PRESCALE__STYPECAST REG_STYPECAST_UWORD -#define R_TIMER_PRESCALE__SVAL REG_SVAL_SHADOW -#define R_TIMER_PRESCALE__SVAL_I REG_SVAL_I_SHADOW -#define R_TIMER_PRESCALE__TYPECAST REG_TYPECAST_UWORD -#define R_TIMER_PRESCALE__TYPE (REG_UWORD) -#define R_TIMER_PRESCALE__GET REG_GET_WO -#define R_TIMER_PRESCALE__IGET REG_IGET_WO -#define R_TIMER_PRESCALE__SET REG_SET_WO -#define R_TIMER_PRESCALE__ISET REG_ISET_WO -#define R_TIMER_PRESCALE__SET_VAL REG_SET_VAL_WO -#define R_TIMER_PRESCALE__EQL REG_EQL_WO -#define R_TIMER_PRESCALE__IEQL REG_IEQL_WO -#define R_TIMER_PRESCALE__RD REG_RD_WO -#define R_TIMER_PRESCALE__IRD REG_IRD_WO -#define R_TIMER_PRESCALE__WR REG_WR_WO -#define R_TIMER_PRESCALE__IWR REG_IWR_WO - -#define R_TIMER_PRESCALE__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_TIMER_PRESCALE__tim_presc__tim_presc__MASK 0x0000ffffU - -#define R_TIMER_PRESCALE__tim_presc__MAX 0xffff - -#define R_TIMER_PRESCALE__tim_presc__MIN 0 - -#define R_TIMER_PRESCALE__tim_presc__BITNR 0 - -#define R_TIMER_PRESCALE__tim_presc__tim_presc__VAL REG_VAL_VAL - - -#endif - -/* - * R_TIM_PRESC_STATUS - * - type: RO - * - addr: 0xb00000f0 - * - group: Timer registers - */ - -#if USE_GROUP__Timer_registers - -#define R_TIM_PRESC_STATUS__ADDR (REG_TYPECAST_UWORD 0xb00000f0) -#define R_TIM_PRESC_STATUS__SVAL REG_SVAL_SHADOW -#define R_TIM_PRESC_STATUS__SVAL_I REG_SVAL_I_SHADOW -#define R_TIM_PRESC_STATUS__TYPECAST REG_TYPECAST_UWORD -#define R_TIM_PRESC_STATUS__TYPE (REG_UWORD) -#define R_TIM_PRESC_STATUS__GET REG_GET_RO -#define R_TIM_PRESC_STATUS__IGET REG_IGET_RO -#define R_TIM_PRESC_STATUS__SET REG_SET_RO -#define R_TIM_PRESC_STATUS__ISET REG_ISET_RO -#define R_TIM_PRESC_STATUS__SET_VAL REG_SET_VAL_RO -#define R_TIM_PRESC_STATUS__EQL REG_EQL_RO -#define R_TIM_PRESC_STATUS__IEQL REG_IEQL_RO -#define R_TIM_PRESC_STATUS__RD REG_RD_RO -#define R_TIM_PRESC_STATUS__IRD REG_IRD_RO -#define R_TIM_PRESC_STATUS__WR REG_WR_RO -#define R_TIM_PRESC_STATUS__IWR REG_IWR_RO - -#define R_TIM_PRESC_STATUS__READ(addr) \ - (*(addr)) - -#define R_TIM_PRESC_STATUS__tim_status__tim_status__MASK 0x0000ffffU - -#define R_TIM_PRESC_STATUS__tim_status__MAX 0xffff - -#define R_TIM_PRESC_STATUS__tim_status__MIN 0 - -#define R_TIM_PRESC_STATUS__tim_status__BITNR 0 - -#define R_TIM_PRESC_STATUS__tim_status__tim_status__VAL REG_VAL_VAL - - -#endif - -/* - * R_TLB_HI - * - type: RW - * - addr: 0xb000025c - * - group: MMU registers - */ - -#if USE_GROUP__MMU_registers - -#define R_TLB_HI__ADDR (REG_TYPECAST_UDWORD 0xb000025c) -#define R_TLB_HI__SVAL REG_SVAL_SHADOW -#define R_TLB_HI__SVAL_I REG_SVAL_I_SHADOW -#define R_TLB_HI__TYPECAST REG_TYPECAST_UDWORD -#define R_TLB_HI__TYPE (REG_UDWORD) -#define R_TLB_HI__GET REG_GET_RW -#define R_TLB_HI__IGET REG_IGET_RW -#define R_TLB_HI__SET REG_SET_RW -#define R_TLB_HI__ISET REG_ISET_RW -#define R_TLB_HI__SET_VAL REG_SET_VAL_RW -#define R_TLB_HI__EQL REG_EQL_RW -#define R_TLB_HI__IEQL REG_IEQL_RW -#define R_TLB_HI__RD REG_RD_RW -#define R_TLB_HI__IRD REG_IRD_RW -#define R_TLB_HI__WR REG_WR_RW -#define R_TLB_HI__IWR REG_IWR_RW - -#define R_TLB_HI__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_TLB_HI__READ(addr) \ - (*(addr)) - -#define R_TLB_HI__vpn__vpn__MASK 0xffffe000U -#define R_TLB_HI__page_id__page_id__MASK 0x0000003fU - -#define R_TLB_HI__vpn__MAX 0x7ffff -#define R_TLB_HI__page_id__MAX 63 - -#define R_TLB_HI__vpn__MIN 0 -#define R_TLB_HI__page_id__MIN 0 - -#define R_TLB_HI__vpn__BITNR 13 -#define R_TLB_HI__page_id__BITNR 0 - -#define R_TLB_HI__vpn__vpn__VAL REG_VAL_VAL -#define R_TLB_HI__page_id__page_id__VAL REG_VAL_VAL - - -#endif - -/* - * R_TLB_LO - * - type: RW - * - addr: 0xb0000258 - * - group: MMU registers - */ - -#if USE_GROUP__MMU_registers - -#define R_TLB_LO__ADDR (REG_TYPECAST_UDWORD 0xb0000258) -#define R_TLB_LO__SVAL REG_SVAL_SHADOW -#define R_TLB_LO__SVAL_I REG_SVAL_I_SHADOW -#define R_TLB_LO__TYPECAST REG_TYPECAST_UDWORD -#define R_TLB_LO__TYPE (REG_UDWORD) -#define R_TLB_LO__GET REG_GET_RW -#define R_TLB_LO__IGET REG_IGET_RW -#define R_TLB_LO__SET REG_SET_RW -#define R_TLB_LO__ISET REG_ISET_RW -#define R_TLB_LO__SET_VAL REG_SET_VAL_RW -#define R_TLB_LO__EQL REG_EQL_RW -#define R_TLB_LO__IEQL REG_IEQL_RW -#define R_TLB_LO__RD REG_RD_RW -#define R_TLB_LO__IRD REG_IRD_RW -#define R_TLB_LO__WR REG_WR_RW -#define R_TLB_LO__IWR REG_IWR_RW - -#define R_TLB_LO__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_TLB_LO__READ(addr) \ - (*(addr)) - -#define R_TLB_LO__pfn__pfn__MASK 0xffffe000U -#define R_TLB_LO__global__global__MASK 0x00000008U -#define R_TLB_LO__valid__valid__MASK 0x00000004U -#define R_TLB_LO__kernel__kernel__MASK 0x00000002U -#define R_TLB_LO__we__we__MASK 0x00000001U - -#define R_TLB_LO__pfn__MAX 0x7ffff -#define R_TLB_LO__global__MAX 0x1 -#define R_TLB_LO__valid__MAX 0x1 -#define R_TLB_LO__kernel__MAX 0x1 -#define R_TLB_LO__we__MAX 0x1 - -#define R_TLB_LO__pfn__MIN 0 -#define R_TLB_LO__global__MIN 0 -#define R_TLB_LO__valid__MIN 0 -#define R_TLB_LO__kernel__MIN 0 -#define R_TLB_LO__we__MIN 0 - -#define R_TLB_LO__pfn__BITNR 13 -#define R_TLB_LO__global__BITNR 3 -#define R_TLB_LO__valid__BITNR 2 -#define R_TLB_LO__kernel__BITNR 1 -#define R_TLB_LO__we__BITNR 0 - -#define R_TLB_LO__pfn__pfn__VAL REG_VAL_VAL -#define R_TLB_LO__global__global__VAL REG_VAL_ENUM -#define R_TLB_LO__valid__valid__VAL REG_VAL_ENUM -#define R_TLB_LO__kernel__kernel__VAL REG_VAL_ENUM -#define R_TLB_LO__we__we__VAL REG_VAL_ENUM - -#define R_TLB_LO__global__global__no 0 -#define R_TLB_LO__global__global__yes 1 -#define R_TLB_LO__valid__valid__no 0 -#define R_TLB_LO__valid__valid__yes 1 -#define R_TLB_LO__kernel__kernel__no 0 -#define R_TLB_LO__kernel__kernel__yes 1 -#define R_TLB_LO__we__we__no 0 -#define R_TLB_LO__we__we__yes 1 - -#endif - -/* - * R_TLB_SELECT - * - type: RW - * - addr: 0xb0000254 - * - group: MMU registers - */ - -#if USE_GROUP__MMU_registers - -#define R_TLB_SELECT__ADDR (REG_TYPECAST_BYTE 0xb0000254) -#define R_TLB_SELECT__SVAL REG_SVAL_SHADOW -#define R_TLB_SELECT__SVAL_I REG_SVAL_I_SHADOW -#define R_TLB_SELECT__TYPECAST REG_TYPECAST_BYTE -#define R_TLB_SELECT__TYPE (REG_BYTE) -#define R_TLB_SELECT__GET REG_GET_RW -#define R_TLB_SELECT__IGET REG_IGET_RW -#define R_TLB_SELECT__SET REG_SET_RW -#define R_TLB_SELECT__ISET REG_ISET_RW -#define R_TLB_SELECT__SET_VAL REG_SET_VAL_RW -#define R_TLB_SELECT__EQL REG_EQL_RW -#define R_TLB_SELECT__IEQL REG_IEQL_RW -#define R_TLB_SELECT__RD REG_RD_RW -#define R_TLB_SELECT__IRD REG_IRD_RW -#define R_TLB_SELECT__WR REG_WR_RW -#define R_TLB_SELECT__IWR REG_IWR_RW - -#define R_TLB_SELECT__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_TLB_SELECT__READ(addr) \ - (*(addr)) - -#define R_TLB_SELECT__index__index__MASK 0x0000003fU - -#define R_TLB_SELECT__index__MAX 63 - -#define R_TLB_SELECT__index__MIN 0 - -#define R_TLB_SELECT__index__BITNR 0 - -#define R_TLB_SELECT__index__index__VAL REG_VAL_VAL - - -#endif - -/* - * R_TR_COUNTERS - * - type: RO - * - addr: 0xb00000a8 - * - group: Network interface registers - */ - -#if USE_GROUP__Network_interface_registers - -#define R_TR_COUNTERS__ADDR (REG_TYPECAST_UDWORD 0xb00000a8) -#define R_TR_COUNTERS__SVAL REG_SVAL_SHADOW -#define R_TR_COUNTERS__SVAL_I REG_SVAL_I_SHADOW -#define R_TR_COUNTERS__TYPECAST REG_TYPECAST_UDWORD -#define R_TR_COUNTERS__TYPE (REG_UDWORD) -#define R_TR_COUNTERS__GET REG_GET_RO -#define R_TR_COUNTERS__IGET REG_IGET_RO -#define R_TR_COUNTERS__SET REG_SET_RO -#define R_TR_COUNTERS__ISET REG_ISET_RO -#define R_TR_COUNTERS__SET_VAL REG_SET_VAL_RO -#define R_TR_COUNTERS__EQL REG_EQL_RO -#define R_TR_COUNTERS__IEQL REG_IEQL_RO -#define R_TR_COUNTERS__RD REG_RD_RO -#define R_TR_COUNTERS__IRD REG_IRD_RO -#define R_TR_COUNTERS__WR REG_WR_RO -#define R_TR_COUNTERS__IWR REG_IWR_RO - -#define R_TR_COUNTERS__READ(addr) \ - (*(addr)) - -#define R_TR_COUNTERS__deferred__deferred__MASK 0xff000000U -#define R_TR_COUNTERS__late_col__late_col__MASK 0x00ff0000U -#define R_TR_COUNTERS__multiple_col__multiple_col__MASK 0x0000ff00U -#define R_TR_COUNTERS__single_col__single_col__MASK 0x000000ffU - -#define R_TR_COUNTERS__deferred__MAX 0xff -#define R_TR_COUNTERS__late_col__MAX 0xff -#define R_TR_COUNTERS__multiple_col__MAX 0xff -#define R_TR_COUNTERS__single_col__MAX 0xff - -#define R_TR_COUNTERS__deferred__MIN 0 -#define R_TR_COUNTERS__late_col__MIN 0 -#define R_TR_COUNTERS__multiple_col__MIN 0 -#define R_TR_COUNTERS__single_col__MIN 0 - -#define R_TR_COUNTERS__deferred__BITNR 24 -#define R_TR_COUNTERS__late_col__BITNR 16 -#define R_TR_COUNTERS__multiple_col__BITNR 8 -#define R_TR_COUNTERS__single_col__BITNR 0 - -#define R_TR_COUNTERS__deferred__deferred__VAL REG_VAL_VAL -#define R_TR_COUNTERS__late_col__late_col__VAL REG_VAL_VAL -#define R_TR_COUNTERS__multiple_col__multiple_col__VAL REG_VAL_VAL -#define R_TR_COUNTERS__single_col__single_col__VAL REG_VAL_VAL - - -#endif - -/* - * R_USB_COMMAND - * - type: RW - * - addr: 0xb0000201 - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -#define R_USB_COMMAND__ADDR (REG_TYPECAST_BYTE 0xb0000201) -#define R_USB_COMMAND__SVAL REG_SVAL_SHADOW -#define R_USB_COMMAND__SVAL_I REG_SVAL_I_SHADOW -#define R_USB_COMMAND__TYPECAST REG_TYPECAST_BYTE -#define R_USB_COMMAND__TYPE (REG_BYTE) -#define R_USB_COMMAND__GET REG_GET_RW -#define R_USB_COMMAND__IGET REG_IGET_RW -#define R_USB_COMMAND__SET REG_SET_RW -#define R_USB_COMMAND__ISET REG_ISET_RW -#define R_USB_COMMAND__SET_VAL REG_SET_VAL_RW -#define R_USB_COMMAND__EQL REG_EQL_RW -#define R_USB_COMMAND__IEQL REG_IEQL_RW -#define R_USB_COMMAND__RD REG_RD_RW -#define R_USB_COMMAND__IRD REG_IRD_RW -#define R_USB_COMMAND__WR REG_WR_RW -#define R_USB_COMMAND__IWR REG_IWR_RW - -#define R_USB_COMMAND__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_USB_COMMAND__READ(addr) \ - (*(addr)) - -#define R_USB_COMMAND__port_sel__port_sel__MASK 0x000000c0U -#define R_USB_COMMAND__port_cmd__port_cmd__MASK 0x00000030U -#define R_USB_COMMAND__busy__busy__MASK 0x00000008U -#define R_USB_COMMAND__ctrl_cmd__ctrl_cmd__MASK 0x00000007U - -#define R_USB_COMMAND__port_sel__MAX 0x3 -#define R_USB_COMMAND__port_cmd__MAX 0x3 -#define R_USB_COMMAND__busy__MAX 0x1 -#define R_USB_COMMAND__ctrl_cmd__MAX 0x7 - -#define R_USB_COMMAND__port_sel__MIN 0 -#define R_USB_COMMAND__port_cmd__MIN 0 -#define R_USB_COMMAND__busy__MIN 0 -#define R_USB_COMMAND__ctrl_cmd__MIN 0 - -#define R_USB_COMMAND__port_sel__BITNR 6 -#define R_USB_COMMAND__port_cmd__BITNR 4 -#define R_USB_COMMAND__busy__BITNR 3 -#define R_USB_COMMAND__ctrl_cmd__BITNR 0 - -#define R_USB_COMMAND__port_sel__port_sel__VAL REG_VAL_ENUM -#define R_USB_COMMAND__port_cmd__port_cmd__VAL REG_VAL_ENUM -#define R_USB_COMMAND__busy__busy__VAL REG_VAL_ENUM -#define R_USB_COMMAND__ctrl_cmd__ctrl_cmd__VAL REG_VAL_ENUM - -#define R_USB_COMMAND__port_sel__port_sel__both 3 -#define R_USB_COMMAND__port_sel__port_sel__nop 0 -#define R_USB_COMMAND__port_sel__port_sel__port1 1 -#define R_USB_COMMAND__port_sel__port_sel__port2 2 -#define R_USB_COMMAND__port_cmd__port_cmd__disable 1 -#define R_USB_COMMAND__port_cmd__port_cmd__reset 0 -#define R_USB_COMMAND__port_cmd__port_cmd__resume 3 -#define R_USB_COMMAND__port_cmd__port_cmd__suspend 2 -#define R_USB_COMMAND__busy__busy__no 0 -#define R_USB_COMMAND__busy__busy__yes 1 -#define R_USB_COMMAND__ctrl_cmd__ctrl_cmd__deconfig 2 -#define R_USB_COMMAND__ctrl_cmd__ctrl_cmd__dev_config 4 -#define R_USB_COMMAND__ctrl_cmd__ctrl_cmd__host_config 3 -#define R_USB_COMMAND__ctrl_cmd__ctrl_cmd__host_nop 5 -#define R_USB_COMMAND__ctrl_cmd__ctrl_cmd__host_run 6 -#define R_USB_COMMAND__ctrl_cmd__ctrl_cmd__host_stop 7 -#define R_USB_COMMAND__ctrl_cmd__ctrl_cmd__nop 0 -#define R_USB_COMMAND__ctrl_cmd__ctrl_cmd__reset 1 - -#endif - -/* - * R_USB_COMMAND_DEV - * - type: RW - * - addr: 0xb0000201 - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -#define R_USB_COMMAND_DEV__ADDR (REG_TYPECAST_BYTE 0xb0000201) -#define R_USB_COMMAND_DEV__SVAL REG_SVAL_SHADOW -#define R_USB_COMMAND_DEV__SVAL_I REG_SVAL_I_SHADOW -#define R_USB_COMMAND_DEV__TYPECAST REG_TYPECAST_BYTE -#define R_USB_COMMAND_DEV__TYPE (REG_BYTE) -#define R_USB_COMMAND_DEV__GET REG_GET_RW -#define R_USB_COMMAND_DEV__IGET REG_IGET_RW -#define R_USB_COMMAND_DEV__SET REG_SET_RW -#define R_USB_COMMAND_DEV__ISET REG_ISET_RW -#define R_USB_COMMAND_DEV__SET_VAL REG_SET_VAL_RW -#define R_USB_COMMAND_DEV__EQL REG_EQL_RW -#define R_USB_COMMAND_DEV__IEQL REG_IEQL_RW -#define R_USB_COMMAND_DEV__RD REG_RD_RW -#define R_USB_COMMAND_DEV__IRD REG_IRD_RW -#define R_USB_COMMAND_DEV__WR REG_WR_RW -#define R_USB_COMMAND_DEV__IWR REG_IWR_RW - -#define R_USB_COMMAND_DEV__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_USB_COMMAND_DEV__READ(addr) \ - (*(addr)) - -#define R_USB_COMMAND_DEV__port_sel__port_sel__MASK 0x000000c0U -#define R_USB_COMMAND_DEV__port_cmd__port_cmd__MASK 0x00000030U -#define R_USB_COMMAND_DEV__busy__busy__MASK 0x00000008U -#define R_USB_COMMAND_DEV__ctrl_cmd__ctrl_cmd__MASK 0x00000007U - -#define R_USB_COMMAND_DEV__port_sel__MAX 0x3 -#define R_USB_COMMAND_DEV__port_cmd__MAX 0x3 -#define R_USB_COMMAND_DEV__busy__MAX 0x1 -#define R_USB_COMMAND_DEV__ctrl_cmd__MAX 0x7 - -#define R_USB_COMMAND_DEV__port_sel__MIN 0 -#define R_USB_COMMAND_DEV__port_cmd__MIN 0 -#define R_USB_COMMAND_DEV__busy__MIN 0 -#define R_USB_COMMAND_DEV__ctrl_cmd__MIN 0 - -#define R_USB_COMMAND_DEV__port_sel__BITNR 6 -#define R_USB_COMMAND_DEV__port_cmd__BITNR 4 -#define R_USB_COMMAND_DEV__busy__BITNR 3 -#define R_USB_COMMAND_DEV__ctrl_cmd__BITNR 0 - -#define R_USB_COMMAND_DEV__port_sel__port_sel__VAL REG_VAL_ENUM -#define R_USB_COMMAND_DEV__port_cmd__port_cmd__VAL REG_VAL_ENUM -#define R_USB_COMMAND_DEV__busy__busy__VAL REG_VAL_ENUM -#define R_USB_COMMAND_DEV__ctrl_cmd__ctrl_cmd__VAL REG_VAL_ENUM - -#define R_USB_COMMAND_DEV__port_sel__port_sel__any 3 -#define R_USB_COMMAND_DEV__port_sel__port_sel__dummy1 1 -#define R_USB_COMMAND_DEV__port_sel__port_sel__dummy2 2 -#define R_USB_COMMAND_DEV__port_sel__port_sel__nop 0 -#define R_USB_COMMAND_DEV__port_cmd__port_cmd__active 0 -#define R_USB_COMMAND_DEV__port_cmd__port_cmd__nop 2 -#define R_USB_COMMAND_DEV__port_cmd__port_cmd__passive 1 -#define R_USB_COMMAND_DEV__port_cmd__port_cmd__wakeup 3 -#define R_USB_COMMAND_DEV__busy__busy__no 0 -#define R_USB_COMMAND_DEV__busy__busy__yes 1 -#define R_USB_COMMAND_DEV__ctrl_cmd__ctrl_cmd__deconfig 2 -#define R_USB_COMMAND_DEV__ctrl_cmd__ctrl_cmd__dev_config 4 -#define R_USB_COMMAND_DEV__ctrl_cmd__ctrl_cmd__dev_nop 1 -#define R_USB_COMMAND_DEV__ctrl_cmd__ctrl_cmd__dev_nop2 5 -#define R_USB_COMMAND_DEV__ctrl_cmd__ctrl_cmd__dev_nop3 6 -#define R_USB_COMMAND_DEV__ctrl_cmd__ctrl_cmd__dev_nop4 7 -#define R_USB_COMMAND_DEV__ctrl_cmd__ctrl_cmd__host_config 3 -#define R_USB_COMMAND_DEV__ctrl_cmd__ctrl_cmd__nop 0 - -#endif - -/* - * R_USB_EPID_ATTN - * - type: RO - * - addr: 0xb0000224 - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -#define R_USB_EPID_ATTN__ADDR (REG_TYPECAST_UDWORD 0xb0000224) -#define R_USB_EPID_ATTN__SVAL REG_SVAL_SHADOW -#define R_USB_EPID_ATTN__SVAL_I REG_SVAL_I_SHADOW -#define R_USB_EPID_ATTN__TYPECAST REG_TYPECAST_UDWORD -#define R_USB_EPID_ATTN__TYPE (REG_UDWORD) -#define R_USB_EPID_ATTN__GET REG_GET_RO -#define R_USB_EPID_ATTN__IGET REG_IGET_RO -#define R_USB_EPID_ATTN__SET REG_SET_RO -#define R_USB_EPID_ATTN__ISET REG_ISET_RO -#define R_USB_EPID_ATTN__SET_VAL REG_SET_VAL_RO -#define R_USB_EPID_ATTN__EQL REG_EQL_RO -#define R_USB_EPID_ATTN__IEQL REG_IEQL_RO -#define R_USB_EPID_ATTN__RD REG_RD_RO -#define R_USB_EPID_ATTN__IRD REG_IRD_RO -#define R_USB_EPID_ATTN__WR REG_WR_RO -#define R_USB_EPID_ATTN__IWR REG_IWR_RO - -#define R_USB_EPID_ATTN__READ(addr) \ - (*(addr)) - -#define R_USB_EPID_ATTN__value__value__MASK 0xffffffffU - -#define R_USB_EPID_ATTN__value__MAX 0xffffffff - -#define R_USB_EPID_ATTN__value__MIN 0 - -#define R_USB_EPID_ATTN__value__BITNR 0 - -#define R_USB_EPID_ATTN__value__value__VAL REG_VAL_VAL - - -#endif - -/* - * R_USB_EPT_DATA - * - type: RW - * - addr: 0xb000021c - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -#define R_USB_EPT_DATA__ADDR (REG_TYPECAST_UDWORD 0xb000021c) -#define R_USB_EPT_DATA__SVAL REG_SVAL_SHADOW -#define R_USB_EPT_DATA__SVAL_I REG_SVAL_I_SHADOW -#define R_USB_EPT_DATA__TYPECAST REG_TYPECAST_UDWORD -#define R_USB_EPT_DATA__TYPE (REG_UDWORD) -#define R_USB_EPT_DATA__GET REG_GET_RW -#define R_USB_EPT_DATA__IGET REG_IGET_RW -#define R_USB_EPT_DATA__SET REG_SET_RW -#define R_USB_EPT_DATA__ISET REG_ISET_RW -#define R_USB_EPT_DATA__SET_VAL REG_SET_VAL_RW -#define R_USB_EPT_DATA__EQL REG_EQL_RW -#define R_USB_EPT_DATA__IEQL REG_IEQL_RW -#define R_USB_EPT_DATA__RD REG_RD_RW -#define R_USB_EPT_DATA__IRD REG_IRD_RW -#define R_USB_EPT_DATA__WR REG_WR_RW -#define R_USB_EPT_DATA__IWR REG_IWR_RW - -#define R_USB_EPT_DATA__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_USB_EPT_DATA__READ(addr) \ - (*(addr)) - -#define R_USB_EPT_DATA__valid__valid__MASK 0x80000000U -#define R_USB_EPT_DATA__hold__hold__MASK 0x40000000U -#define R_USB_EPT_DATA__error_count_in__error_count_in__MASK 0x30000000U -#define R_USB_EPT_DATA__t_in__t_in__MASK 0x08000000U -#define R_USB_EPT_DATA__low_speed__low_speed__MASK 0x04000000U -#define R_USB_EPT_DATA__port__port__MASK 0x03000000U -#define R_USB_EPT_DATA__error_code__error_code__MASK 0x00c00000U -#define R_USB_EPT_DATA__t_out__t_out__MASK 0x00200000U -#define R_USB_EPT_DATA__error_count_out__error_count_out__MASK 0x00180000U -#define R_USB_EPT_DATA__max_len__max_len__MASK 0x0003f800U -#define R_USB_EPT_DATA__ep__ep__MASK 0x00000780U -#define R_USB_EPT_DATA__dev__dev__MASK 0x0000007fU - -#define R_USB_EPT_DATA__valid__MAX 0x1 -#define R_USB_EPT_DATA__hold__MAX 0x1 -#define R_USB_EPT_DATA__error_count_in__MAX 3 -#define R_USB_EPT_DATA__t_in__MAX 1 -#define R_USB_EPT_DATA__low_speed__MAX 0x1 -#define R_USB_EPT_DATA__port__MAX 0x3 -#define R_USB_EPT_DATA__error_code__MAX 0x3 -#define R_USB_EPT_DATA__t_out__MAX 1 -#define R_USB_EPT_DATA__error_count_out__MAX 3 -#define R_USB_EPT_DATA__max_len__MAX 64 -#define R_USB_EPT_DATA__ep__MAX 0xf -#define R_USB_EPT_DATA__dev__MAX 0x7f - -#define R_USB_EPT_DATA__valid__MIN 0 -#define R_USB_EPT_DATA__hold__MIN 0 -#define R_USB_EPT_DATA__error_count_in__MIN 0 -#define R_USB_EPT_DATA__t_in__MIN 0 -#define R_USB_EPT_DATA__low_speed__MIN 0 -#define R_USB_EPT_DATA__port__MIN 0 -#define R_USB_EPT_DATA__error_code__MIN 0 -#define R_USB_EPT_DATA__t_out__MIN 0 -#define R_USB_EPT_DATA__error_count_out__MIN 0 -#define R_USB_EPT_DATA__max_len__MIN 1 -#define R_USB_EPT_DATA__ep__MIN 0 -#define R_USB_EPT_DATA__dev__MIN 0 - -#define R_USB_EPT_DATA__valid__BITNR 31 -#define R_USB_EPT_DATA__hold__BITNR 30 -#define R_USB_EPT_DATA__error_count_in__BITNR 28 -#define R_USB_EPT_DATA__t_in__BITNR 27 -#define R_USB_EPT_DATA__low_speed__BITNR 26 -#define R_USB_EPT_DATA__port__BITNR 24 -#define R_USB_EPT_DATA__error_code__BITNR 22 -#define R_USB_EPT_DATA__t_out__BITNR 21 -#define R_USB_EPT_DATA__error_count_out__BITNR 19 -#define R_USB_EPT_DATA__max_len__BITNR 11 -#define R_USB_EPT_DATA__ep__BITNR 7 -#define R_USB_EPT_DATA__dev__BITNR 0 - -#define R_USB_EPT_DATA__valid__valid__VAL REG_VAL_ENUM -#define R_USB_EPT_DATA__hold__hold__VAL REG_VAL_ENUM -#define R_USB_EPT_DATA__error_count_in__error_count_in__VAL REG_VAL_VAL -#define R_USB_EPT_DATA__t_in__t_in__VAL REG_VAL_VAL -#define R_USB_EPT_DATA__low_speed__low_speed__VAL REG_VAL_ENUM -#define R_USB_EPT_DATA__port__port__VAL REG_VAL_ENUM -#define R_USB_EPT_DATA__error_code__error_code__VAL REG_VAL_ENUM -#define R_USB_EPT_DATA__t_out__t_out__VAL REG_VAL_VAL -#define R_USB_EPT_DATA__error_count_out__error_count_out__VAL REG_VAL_VAL -#define R_USB_EPT_DATA__max_len__max_len__VAL REG_VAL_VAL -#define R_USB_EPT_DATA__ep__ep__VAL REG_VAL_VAL -#define R_USB_EPT_DATA__dev__dev__VAL REG_VAL_VAL - -#define R_USB_EPT_DATA__valid__valid__no 0 -#define R_USB_EPT_DATA__valid__valid__yes 1 -#define R_USB_EPT_DATA__hold__hold__no 0 -#define R_USB_EPT_DATA__hold__hold__yes 1 -#define R_USB_EPT_DATA__low_speed__low_speed__no 0 -#define R_USB_EPT_DATA__low_speed__low_speed__yes 1 -#define R_USB_EPT_DATA__port__port__any 0 -#define R_USB_EPT_DATA__port__port__p1 1 -#define R_USB_EPT_DATA__port__port__p2 2 -#define R_USB_EPT_DATA__port__port__undef 3 -#define R_USB_EPT_DATA__error_code__error_code__buffer_error 3 -#define R_USB_EPT_DATA__error_code__error_code__bus_error 2 -#define R_USB_EPT_DATA__error_code__error_code__no_error 0 -#define R_USB_EPT_DATA__error_code__error_code__stall 1 - -#endif - -/* - * R_USB_EPT_DATA_DEV - * - type: RW - * - addr: 0xb000021c - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -#define R_USB_EPT_DATA_DEV__ADDR (REG_TYPECAST_UDWORD 0xb000021c) -#define R_USB_EPT_DATA_DEV__SVAL REG_SVAL_SHADOW -#define R_USB_EPT_DATA_DEV__SVAL_I REG_SVAL_I_SHADOW -#define R_USB_EPT_DATA_DEV__TYPECAST REG_TYPECAST_UDWORD -#define R_USB_EPT_DATA_DEV__TYPE (REG_UDWORD) -#define R_USB_EPT_DATA_DEV__GET REG_GET_RW -#define R_USB_EPT_DATA_DEV__IGET REG_IGET_RW -#define R_USB_EPT_DATA_DEV__SET REG_SET_RW -#define R_USB_EPT_DATA_DEV__ISET REG_ISET_RW -#define R_USB_EPT_DATA_DEV__SET_VAL REG_SET_VAL_RW -#define R_USB_EPT_DATA_DEV__EQL REG_EQL_RW -#define R_USB_EPT_DATA_DEV__IEQL REG_IEQL_RW -#define R_USB_EPT_DATA_DEV__RD REG_RD_RW -#define R_USB_EPT_DATA_DEV__IRD REG_IRD_RW -#define R_USB_EPT_DATA_DEV__WR REG_WR_RW -#define R_USB_EPT_DATA_DEV__IWR REG_IWR_RW - -#define R_USB_EPT_DATA_DEV__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_USB_EPT_DATA_DEV__READ(addr) \ - (*(addr)) - -#define R_USB_EPT_DATA_DEV__valid__valid__MASK 0x80000000U -#define R_USB_EPT_DATA_DEV__hold__hold__MASK 0x40000000U -#define R_USB_EPT_DATA_DEV__stall__stall__MASK 0x20000000U -#define R_USB_EPT_DATA_DEV__iso_resp__iso_resp__MASK 0x10000000U -#define R_USB_EPT_DATA_DEV__ctrl__ctrl__MASK 0x08000000U -#define R_USB_EPT_DATA_DEV__iso__iso__MASK 0x04000000U -#define R_USB_EPT_DATA_DEV__port__port__MASK 0x03000000U -#define R_USB_EPT_DATA_DEV__control_phase__control_phase__MASK 0x00400000U -#define R_USB_EPT_DATA_DEV__t__t__MASK 0x00200000U -#define R_USB_EPT_DATA_DEV__max_len__max_len__MASK 0x001ff800U -#define R_USB_EPT_DATA_DEV__ep__ep__MASK 0x00000780U -#define R_USB_EPT_DATA_DEV__dev__dev__MASK 0x0000007fU - -#define R_USB_EPT_DATA_DEV__valid__MAX 0x1 -#define R_USB_EPT_DATA_DEV__hold__MAX 0x1 -#define R_USB_EPT_DATA_DEV__stall__MAX 0x1 -#define R_USB_EPT_DATA_DEV__iso_resp__MAX 0x1 -#define R_USB_EPT_DATA_DEV__ctrl__MAX 0x1 -#define R_USB_EPT_DATA_DEV__iso__MAX 0x1 -#define R_USB_EPT_DATA_DEV__port__MAX 0x3 -#define R_USB_EPT_DATA_DEV__control_phase__MAX 0x1 -#define R_USB_EPT_DATA_DEV__t__MAX 1 -#define R_USB_EPT_DATA_DEV__max_len__MAX 1023 -#define R_USB_EPT_DATA_DEV__ep__MAX 15 -#define R_USB_EPT_DATA_DEV__dev__MAX 127 - -#define R_USB_EPT_DATA_DEV__valid__MIN 0 -#define R_USB_EPT_DATA_DEV__hold__MIN 0 -#define R_USB_EPT_DATA_DEV__stall__MIN 0 -#define R_USB_EPT_DATA_DEV__iso_resp__MIN 0 -#define R_USB_EPT_DATA_DEV__ctrl__MIN 0 -#define R_USB_EPT_DATA_DEV__iso__MIN 0 -#define R_USB_EPT_DATA_DEV__port__MIN 0 -#define R_USB_EPT_DATA_DEV__control_phase__MIN 0 -#define R_USB_EPT_DATA_DEV__t__MIN 0 -#define R_USB_EPT_DATA_DEV__max_len__MIN 1 -#define R_USB_EPT_DATA_DEV__ep__MIN 0 -#define R_USB_EPT_DATA_DEV__dev__MIN 0 - -#define R_USB_EPT_DATA_DEV__valid__BITNR 31 -#define R_USB_EPT_DATA_DEV__hold__BITNR 30 -#define R_USB_EPT_DATA_DEV__stall__BITNR 29 -#define R_USB_EPT_DATA_DEV__iso_resp__BITNR 28 -#define R_USB_EPT_DATA_DEV__ctrl__BITNR 27 -#define R_USB_EPT_DATA_DEV__iso__BITNR 26 -#define R_USB_EPT_DATA_DEV__port__BITNR 24 -#define R_USB_EPT_DATA_DEV__control_phase__BITNR 22 -#define R_USB_EPT_DATA_DEV__t__BITNR 21 -#define R_USB_EPT_DATA_DEV__max_len__BITNR 11 -#define R_USB_EPT_DATA_DEV__ep__BITNR 7 -#define R_USB_EPT_DATA_DEV__dev__BITNR 0 - -#define R_USB_EPT_DATA_DEV__valid__valid__VAL REG_VAL_ENUM -#define R_USB_EPT_DATA_DEV__hold__hold__VAL REG_VAL_ENUM -#define R_USB_EPT_DATA_DEV__stall__stall__VAL REG_VAL_ENUM -#define R_USB_EPT_DATA_DEV__iso_resp__iso_resp__VAL REG_VAL_ENUM -#define R_USB_EPT_DATA_DEV__ctrl__ctrl__VAL REG_VAL_ENUM -#define R_USB_EPT_DATA_DEV__iso__iso__VAL REG_VAL_ENUM -#define R_USB_EPT_DATA_DEV__port__port__VAL REG_VAL_VAL -#define R_USB_EPT_DATA_DEV__control_phase__control_phase__VAL REG_VAL_VAL -#define R_USB_EPT_DATA_DEV__t__t__VAL REG_VAL_VAL -#define R_USB_EPT_DATA_DEV__max_len__max_len__VAL REG_VAL_VAL -#define R_USB_EPT_DATA_DEV__ep__ep__VAL REG_VAL_VAL -#define R_USB_EPT_DATA_DEV__dev__dev__VAL REG_VAL_VAL - -#define R_USB_EPT_DATA_DEV__valid__valid__no 0 -#define R_USB_EPT_DATA_DEV__valid__valid__yes 1 -#define R_USB_EPT_DATA_DEV__hold__hold__no 0 -#define R_USB_EPT_DATA_DEV__hold__hold__yes 1 -#define R_USB_EPT_DATA_DEV__stall__stall__no 0 -#define R_USB_EPT_DATA_DEV__stall__stall__yes 1 -#define R_USB_EPT_DATA_DEV__iso_resp__iso_resp__quiet 0 -#define R_USB_EPT_DATA_DEV__iso_resp__iso_resp__yes 1 -#define R_USB_EPT_DATA_DEV__ctrl__ctrl__no 0 -#define R_USB_EPT_DATA_DEV__ctrl__ctrl__yes 1 -#define R_USB_EPT_DATA_DEV__iso__iso__no 0 -#define R_USB_EPT_DATA_DEV__iso__iso__yes 1 - -#endif - -/* - * R_USB_EPT_DATA_ISO - * - type: RW - * - addr: 0xb000021c - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -#define R_USB_EPT_DATA_ISO__ADDR (REG_TYPECAST_UDWORD 0xb000021c) -#define R_USB_EPT_DATA_ISO__SVAL REG_SVAL_SHADOW -#define R_USB_EPT_DATA_ISO__SVAL_I REG_SVAL_I_SHADOW -#define R_USB_EPT_DATA_ISO__TYPECAST REG_TYPECAST_UDWORD -#define R_USB_EPT_DATA_ISO__TYPE (REG_UDWORD) -#define R_USB_EPT_DATA_ISO__GET REG_GET_RW -#define R_USB_EPT_DATA_ISO__IGET REG_IGET_RW -#define R_USB_EPT_DATA_ISO__SET REG_SET_RW -#define R_USB_EPT_DATA_ISO__ISET REG_ISET_RW -#define R_USB_EPT_DATA_ISO__SET_VAL REG_SET_VAL_RW -#define R_USB_EPT_DATA_ISO__EQL REG_EQL_RW -#define R_USB_EPT_DATA_ISO__IEQL REG_IEQL_RW -#define R_USB_EPT_DATA_ISO__RD REG_RD_RW -#define R_USB_EPT_DATA_ISO__IRD REG_IRD_RW -#define R_USB_EPT_DATA_ISO__WR REG_WR_RW -#define R_USB_EPT_DATA_ISO__IWR REG_IWR_RW - -#define R_USB_EPT_DATA_ISO__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_USB_EPT_DATA_ISO__READ(addr) \ - (*(addr)) - -#define R_USB_EPT_DATA_ISO__valid__valid__MASK 0x80000000U -#define R_USB_EPT_DATA_ISO__port__port__MASK 0x03000000U -#define R_USB_EPT_DATA_ISO__error_code__error_code__MASK 0x00c00000U -#define R_USB_EPT_DATA_ISO__max_len__max_len__MASK 0x001ff800U -#define R_USB_EPT_DATA_ISO__ep__ep__MASK 0x00000780U -#define R_USB_EPT_DATA_ISO__dev__dev__MASK 0x0000007fU - -#define R_USB_EPT_DATA_ISO__valid__MAX 0x1 -#define R_USB_EPT_DATA_ISO__port__MAX 0x3 -#define R_USB_EPT_DATA_ISO__error_code__MAX 0x3 -#define R_USB_EPT_DATA_ISO__max_len__MAX 1023 -#define R_USB_EPT_DATA_ISO__ep__MAX 0xf -#define R_USB_EPT_DATA_ISO__dev__MAX 0x7f - -#define R_USB_EPT_DATA_ISO__valid__MIN 0 -#define R_USB_EPT_DATA_ISO__port__MIN 0 -#define R_USB_EPT_DATA_ISO__error_code__MIN 0 -#define R_USB_EPT_DATA_ISO__max_len__MIN 1 -#define R_USB_EPT_DATA_ISO__ep__MIN 0 -#define R_USB_EPT_DATA_ISO__dev__MIN 0 - -#define R_USB_EPT_DATA_ISO__valid__BITNR 31 -#define R_USB_EPT_DATA_ISO__port__BITNR 24 -#define R_USB_EPT_DATA_ISO__error_code__BITNR 22 -#define R_USB_EPT_DATA_ISO__max_len__BITNR 11 -#define R_USB_EPT_DATA_ISO__ep__BITNR 7 -#define R_USB_EPT_DATA_ISO__dev__BITNR 0 - -#define R_USB_EPT_DATA_ISO__valid__valid__VAL REG_VAL_ENUM -#define R_USB_EPT_DATA_ISO__port__port__VAL REG_VAL_ENUM -#define R_USB_EPT_DATA_ISO__error_code__error_code__VAL REG_VAL_ENUM -#define R_USB_EPT_DATA_ISO__max_len__max_len__VAL REG_VAL_VAL -#define R_USB_EPT_DATA_ISO__ep__ep__VAL REG_VAL_VAL -#define R_USB_EPT_DATA_ISO__dev__dev__VAL REG_VAL_VAL - -#define R_USB_EPT_DATA_ISO__valid__valid__no 0 -#define R_USB_EPT_DATA_ISO__valid__valid__yes 1 -#define R_USB_EPT_DATA_ISO__port__port__any 0 -#define R_USB_EPT_DATA_ISO__port__port__p1 1 -#define R_USB_EPT_DATA_ISO__port__port__p2 2 -#define R_USB_EPT_DATA_ISO__port__port__undef 3 -#define R_USB_EPT_DATA_ISO__error_code__error_code__TBD3 3 -#define R_USB_EPT_DATA_ISO__error_code__error_code__bus_error 2 -#define R_USB_EPT_DATA_ISO__error_code__error_code__no_error 0 -#define R_USB_EPT_DATA_ISO__error_code__error_code__stall 1 - -#endif - -/* - * R_USB_EPT_INDEX - * - type: RW - * - addr: 0xb0000208 - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -#define R_USB_EPT_INDEX__ADDR (REG_TYPECAST_BYTE 0xb0000208) -#define R_USB_EPT_INDEX__SVAL REG_SVAL_SHADOW -#define R_USB_EPT_INDEX__SVAL_I REG_SVAL_I_SHADOW -#define R_USB_EPT_INDEX__TYPECAST REG_TYPECAST_BYTE -#define R_USB_EPT_INDEX__TYPE (REG_BYTE) -#define R_USB_EPT_INDEX__GET REG_GET_RW -#define R_USB_EPT_INDEX__IGET REG_IGET_RW -#define R_USB_EPT_INDEX__SET REG_SET_RW -#define R_USB_EPT_INDEX__ISET REG_ISET_RW -#define R_USB_EPT_INDEX__SET_VAL REG_SET_VAL_RW -#define R_USB_EPT_INDEX__EQL REG_EQL_RW -#define R_USB_EPT_INDEX__IEQL REG_IEQL_RW -#define R_USB_EPT_INDEX__RD REG_RD_RW -#define R_USB_EPT_INDEX__IRD REG_IRD_RW -#define R_USB_EPT_INDEX__WR REG_WR_RW -#define R_USB_EPT_INDEX__IWR REG_IWR_RW - -#define R_USB_EPT_INDEX__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_USB_EPT_INDEX__READ(addr) \ - (*(addr)) - -#define R_USB_EPT_INDEX__value__value__MASK 0x0000001fU - -#define R_USB_EPT_INDEX__value__MAX 31 - -#define R_USB_EPT_INDEX__value__MIN 0 - -#define R_USB_EPT_INDEX__value__BITNR 0 - -#define R_USB_EPT_INDEX__value__value__VAL REG_VAL_VAL - - -#endif - -/* - * R_USB_FM_INTERVAL - * - type: RW - * - addr: 0xb0000210 - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -#define R_USB_FM_INTERVAL__ADDR (REG_TYPECAST_UWORD 0xb0000210) -#define R_USB_FM_INTERVAL__SVAL REG_SVAL_SHADOW -#define R_USB_FM_INTERVAL__SVAL_I REG_SVAL_I_SHADOW -#define R_USB_FM_INTERVAL__TYPECAST REG_TYPECAST_UWORD -#define R_USB_FM_INTERVAL__TYPE (REG_UWORD) -#define R_USB_FM_INTERVAL__GET REG_GET_RW -#define R_USB_FM_INTERVAL__IGET REG_IGET_RW -#define R_USB_FM_INTERVAL__SET REG_SET_RW -#define R_USB_FM_INTERVAL__ISET REG_ISET_RW -#define R_USB_FM_INTERVAL__SET_VAL REG_SET_VAL_RW -#define R_USB_FM_INTERVAL__EQL REG_EQL_RW -#define R_USB_FM_INTERVAL__IEQL REG_IEQL_RW -#define R_USB_FM_INTERVAL__RD REG_RD_RW -#define R_USB_FM_INTERVAL__IRD REG_IRD_RW -#define R_USB_FM_INTERVAL__WR REG_WR_RW -#define R_USB_FM_INTERVAL__IWR REG_IWR_RW - -#define R_USB_FM_INTERVAL__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_USB_FM_INTERVAL__READ(addr) \ - (*(addr)) - -#define R_USB_FM_INTERVAL__fixed__fixed__MASK 0x00003fc0U -#define R_USB_FM_INTERVAL__adj__adj__MASK 0x0000003fU - -#define R_USB_FM_INTERVAL__fixed__MAX 0xff -#define R_USB_FM_INTERVAL__adj__MAX 63 - -#define R_USB_FM_INTERVAL__fixed__MIN 0 -#define R_USB_FM_INTERVAL__adj__MIN 0 - -#define R_USB_FM_INTERVAL__fixed__BITNR 6 -#define R_USB_FM_INTERVAL__adj__BITNR 0 - -#define R_USB_FM_INTERVAL__fixed__fixed__VAL REG_VAL_VAL -#define R_USB_FM_INTERVAL__adj__adj__VAL REG_VAL_VAL - - -#endif - -/* - * R_USB_FM_NUMBER - * - type: RW - * - addr: 0xb000020c - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -#define R_USB_FM_NUMBER__ADDR (REG_TYPECAST_UDWORD 0xb000020c) -#define R_USB_FM_NUMBER__SVAL REG_SVAL_SHADOW -#define R_USB_FM_NUMBER__SVAL_I REG_SVAL_I_SHADOW -#define R_USB_FM_NUMBER__TYPECAST REG_TYPECAST_UDWORD -#define R_USB_FM_NUMBER__TYPE (REG_UDWORD) -#define R_USB_FM_NUMBER__GET REG_GET_RW -#define R_USB_FM_NUMBER__IGET REG_IGET_RW -#define R_USB_FM_NUMBER__SET REG_SET_RW -#define R_USB_FM_NUMBER__ISET REG_ISET_RW -#define R_USB_FM_NUMBER__SET_VAL REG_SET_VAL_RW -#define R_USB_FM_NUMBER__EQL REG_EQL_RW -#define R_USB_FM_NUMBER__IEQL REG_IEQL_RW -#define R_USB_FM_NUMBER__RD REG_RD_RW -#define R_USB_FM_NUMBER__IRD REG_IRD_RW -#define R_USB_FM_NUMBER__WR REG_WR_RW -#define R_USB_FM_NUMBER__IWR REG_IWR_RW - -#define R_USB_FM_NUMBER__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_USB_FM_NUMBER__READ(addr) \ - (*(addr)) - -#define R_USB_FM_NUMBER__value__value__MASK 0xffffffffU - -#define R_USB_FM_NUMBER__value__MAX 0xffffffff - -#define R_USB_FM_NUMBER__value__MIN 0 - -#define R_USB_FM_NUMBER__value__BITNR 0 - -#define R_USB_FM_NUMBER__value__value__VAL REG_VAL_VAL - - -#endif - -/* - * R_USB_FM_NUMBER_DEV - * - type: RW - * - addr: 0xb000020c - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -#define R_USB_FM_NUMBER_DEV__ADDR (REG_TYPECAST_UDWORD 0xb000020c) -#define R_USB_FM_NUMBER_DEV__SVAL REG_SVAL_SHADOW -#define R_USB_FM_NUMBER_DEV__SVAL_I REG_SVAL_I_SHADOW -#define R_USB_FM_NUMBER_DEV__TYPECAST REG_TYPECAST_UDWORD -#define R_USB_FM_NUMBER_DEV__TYPE (REG_UDWORD) -#define R_USB_FM_NUMBER_DEV__GET REG_GET_RW -#define R_USB_FM_NUMBER_DEV__IGET REG_IGET_RW -#define R_USB_FM_NUMBER_DEV__SET REG_SET_RW -#define R_USB_FM_NUMBER_DEV__ISET REG_ISET_RW -#define R_USB_FM_NUMBER_DEV__SET_VAL REG_SET_VAL_RW -#define R_USB_FM_NUMBER_DEV__EQL REG_EQL_RW -#define R_USB_FM_NUMBER_DEV__IEQL REG_IEQL_RW -#define R_USB_FM_NUMBER_DEV__RD REG_RD_RW -#define R_USB_FM_NUMBER_DEV__IRD REG_IRD_RW -#define R_USB_FM_NUMBER_DEV__WR REG_WR_RW -#define R_USB_FM_NUMBER_DEV__IWR REG_IWR_RW - -#define R_USB_FM_NUMBER_DEV__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_USB_FM_NUMBER_DEV__READ(addr) \ - (*(addr)) - -#define R_USB_FM_NUMBER_DEV__sign__sign__MASK 0x80000000U -#define R_USB_FM_NUMBER_DEV__deviation__deviation__MASK 0x7f000000U -#define R_USB_FM_NUMBER_DEV__fm_number__fm_number__MASK 0x000007ffU - -#define R_USB_FM_NUMBER_DEV__sign__MAX 0x1 -#define R_USB_FM_NUMBER_DEV__deviation__MAX 127 -#define R_USB_FM_NUMBER_DEV__fm_number__MAX 0x7ff - -#define R_USB_FM_NUMBER_DEV__sign__MIN 0 -#define R_USB_FM_NUMBER_DEV__deviation__MIN 0 -#define R_USB_FM_NUMBER_DEV__fm_number__MIN 0 - -#define R_USB_FM_NUMBER_DEV__sign__BITNR 31 -#define R_USB_FM_NUMBER_DEV__deviation__BITNR 24 -#define R_USB_FM_NUMBER_DEV__fm_number__BITNR 0 - -#define R_USB_FM_NUMBER_DEV__sign__sign__VAL REG_VAL_ENUM -#define R_USB_FM_NUMBER_DEV__deviation__deviation__VAL REG_VAL_VAL -#define R_USB_FM_NUMBER_DEV__fm_number__fm_number__VAL REG_VAL_VAL - -#define R_USB_FM_NUMBER_DEV__sign__sign__early 0 -#define R_USB_FM_NUMBER_DEV__sign__sign__late 1 - -#endif - -/* - * R_USB_FM_PSTART - * - type: RW - * - addr: 0xb0000214 - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -#define R_USB_FM_PSTART__ADDR (REG_TYPECAST_UWORD 0xb0000214) -#define R_USB_FM_PSTART__SVAL REG_SVAL_SHADOW -#define R_USB_FM_PSTART__SVAL_I REG_SVAL_I_SHADOW -#define R_USB_FM_PSTART__TYPECAST REG_TYPECAST_UWORD -#define R_USB_FM_PSTART__TYPE (REG_UWORD) -#define R_USB_FM_PSTART__GET REG_GET_RW -#define R_USB_FM_PSTART__IGET REG_IGET_RW -#define R_USB_FM_PSTART__SET REG_SET_RW -#define R_USB_FM_PSTART__ISET REG_ISET_RW -#define R_USB_FM_PSTART__SET_VAL REG_SET_VAL_RW -#define R_USB_FM_PSTART__EQL REG_EQL_RW -#define R_USB_FM_PSTART__IEQL REG_IEQL_RW -#define R_USB_FM_PSTART__RD REG_RD_RW -#define R_USB_FM_PSTART__IRD REG_IRD_RW -#define R_USB_FM_PSTART__WR REG_WR_RW -#define R_USB_FM_PSTART__IWR REG_IWR_RW - -#define R_USB_FM_PSTART__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_USB_FM_PSTART__READ(addr) \ - (*(addr)) - -#define R_USB_FM_PSTART__value__value__MASK 0x00003fffU - -#define R_USB_FM_PSTART__value__MAX 0x3fff - -#define R_USB_FM_PSTART__value__MIN 0 - -#define R_USB_FM_PSTART__value__BITNR 0 - -#define R_USB_FM_PSTART__value__value__VAL REG_VAL_VAL - - -#endif - -/* - * R_USB_FM_REMAINING - * - type: RO - * - addr: 0xb0000212 - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -#define R_USB_FM_REMAINING__ADDR (REG_TYPECAST_UWORD 0xb0000212) -#define R_USB_FM_REMAINING__SVAL REG_SVAL_SHADOW -#define R_USB_FM_REMAINING__SVAL_I REG_SVAL_I_SHADOW -#define R_USB_FM_REMAINING__TYPECAST REG_TYPECAST_UWORD -#define R_USB_FM_REMAINING__TYPE (REG_UWORD) -#define R_USB_FM_REMAINING__GET REG_GET_RO -#define R_USB_FM_REMAINING__IGET REG_IGET_RO -#define R_USB_FM_REMAINING__SET REG_SET_RO -#define R_USB_FM_REMAINING__ISET REG_ISET_RO -#define R_USB_FM_REMAINING__SET_VAL REG_SET_VAL_RO -#define R_USB_FM_REMAINING__EQL REG_EQL_RO -#define R_USB_FM_REMAINING__IEQL REG_IEQL_RO -#define R_USB_FM_REMAINING__RD REG_RD_RO -#define R_USB_FM_REMAINING__IRD REG_IRD_RO -#define R_USB_FM_REMAINING__WR REG_WR_RO -#define R_USB_FM_REMAINING__IWR REG_IWR_RO - -#define R_USB_FM_REMAINING__READ(addr) \ - (*(addr)) - -#define R_USB_FM_REMAINING__value__value__MASK 0x00003fffU - -#define R_USB_FM_REMAINING__value__MAX 0x3fff - -#define R_USB_FM_REMAINING__value__MIN 0 - -#define R_USB_FM_REMAINING__value__BITNR 0 - -#define R_USB_FM_REMAINING__value__value__VAL REG_VAL_VAL - - -#endif - -/* - * R_USB_IRQ_MASK_CLR - * - type: WO - * - addr: 0xb0000206 - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -#define R_USB_IRQ_MASK_CLR__ADDR (REG_TYPECAST_UWORD 0xb0000206) - -#ifndef REG_NO_SHADOW -#define R_USB_IRQ_MASK_CLR__SADDR (REG_STYPECAST_UWORD (reg_shadow__hwregs.R_USB_IRQ_MASK_CLR + 0)) -#define R_USB_IRQ_MASK_CLR__IADDR (REG_STYPECAST_UWORD (reg_initiated__hwregs.R_USB_IRQ_MASK_CLR + 0)) -#else /* REG_NO_SHADOW */ -#define R_USB_IRQ_MASK_CLR__SADDR (REG_STYPECAST_UWORD (®_shadow__hwregs)) -#define R_USB_IRQ_MASK_CLR__IADDR (REG_STYPECAST_UWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_USB_IRQ_MASK_CLR__STYPECAST REG_STYPECAST_UWORD -#define R_USB_IRQ_MASK_CLR__SVAL REG_SVAL_ZERO -#define R_USB_IRQ_MASK_CLR__SVAL_I REG_SVAL_I_ZERO -#define R_USB_IRQ_MASK_CLR__TYPECAST REG_TYPECAST_UWORD -#define R_USB_IRQ_MASK_CLR__TYPE (REG_UWORD) -#define R_USB_IRQ_MASK_CLR__GET REG_GET_WO -#define R_USB_IRQ_MASK_CLR__IGET REG_IGET_WO -#define R_USB_IRQ_MASK_CLR__SET REG_SET_WO -#define R_USB_IRQ_MASK_CLR__ISET REG_ISET_WO -#define R_USB_IRQ_MASK_CLR__SET_VAL REG_SET_VAL_WO -#define R_USB_IRQ_MASK_CLR__EQL REG_EQL_WO -#define R_USB_IRQ_MASK_CLR__IEQL REG_IEQL_WO -#define R_USB_IRQ_MASK_CLR__RD REG_RD_WO -#define R_USB_IRQ_MASK_CLR__IRD REG_IRD_WO -#define R_USB_IRQ_MASK_CLR__WR REG_WR_WO -#define R_USB_IRQ_MASK_CLR__IWR REG_IWR_WO - -#define R_USB_IRQ_MASK_CLR__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_USB_IRQ_MASK_CLR__iso_eof__iso_eof__MASK 0x00002000U -#define R_USB_IRQ_MASK_CLR__intr_eof__intr_eof__MASK 0x00001000U -#define R_USB_IRQ_MASK_CLR__iso_eot__iso_eot__MASK 0x00000800U -#define R_USB_IRQ_MASK_CLR__intr_eot__intr_eot__MASK 0x00000400U -#define R_USB_IRQ_MASK_CLR__ctl_eot__ctl_eot__MASK 0x00000200U -#define R_USB_IRQ_MASK_CLR__bulk_eot__bulk_eot__MASK 0x00000100U -#define R_USB_IRQ_MASK_CLR__epid_attn__epid_attn__MASK 0x00000008U -#define R_USB_IRQ_MASK_CLR__sof__sof__MASK 0x00000004U -#define R_USB_IRQ_MASK_CLR__port_status__port_status__MASK 0x00000002U -#define R_USB_IRQ_MASK_CLR__ctl_status__ctl_status__MASK 0x00000001U - -#define R_USB_IRQ_MASK_CLR__iso_eof__MAX 0x1 -#define R_USB_IRQ_MASK_CLR__intr_eof__MAX 0x1 -#define R_USB_IRQ_MASK_CLR__iso_eot__MAX 0x1 -#define R_USB_IRQ_MASK_CLR__intr_eot__MAX 0x1 -#define R_USB_IRQ_MASK_CLR__ctl_eot__MAX 0x1 -#define R_USB_IRQ_MASK_CLR__bulk_eot__MAX 0x1 -#define R_USB_IRQ_MASK_CLR__epid_attn__MAX 0x1 -#define R_USB_IRQ_MASK_CLR__sof__MAX 0x1 -#define R_USB_IRQ_MASK_CLR__port_status__MAX 0x1 -#define R_USB_IRQ_MASK_CLR__ctl_status__MAX 0x1 - -#define R_USB_IRQ_MASK_CLR__iso_eof__MIN 0 -#define R_USB_IRQ_MASK_CLR__intr_eof__MIN 0 -#define R_USB_IRQ_MASK_CLR__iso_eot__MIN 0 -#define R_USB_IRQ_MASK_CLR__intr_eot__MIN 0 -#define R_USB_IRQ_MASK_CLR__ctl_eot__MIN 0 -#define R_USB_IRQ_MASK_CLR__bulk_eot__MIN 0 -#define R_USB_IRQ_MASK_CLR__epid_attn__MIN 0 -#define R_USB_IRQ_MASK_CLR__sof__MIN 0 -#define R_USB_IRQ_MASK_CLR__port_status__MIN 0 -#define R_USB_IRQ_MASK_CLR__ctl_status__MIN 0 - -#define R_USB_IRQ_MASK_CLR__iso_eof__BITNR 13 -#define R_USB_IRQ_MASK_CLR__intr_eof__BITNR 12 -#define R_USB_IRQ_MASK_CLR__iso_eot__BITNR 11 -#define R_USB_IRQ_MASK_CLR__intr_eot__BITNR 10 -#define R_USB_IRQ_MASK_CLR__ctl_eot__BITNR 9 -#define R_USB_IRQ_MASK_CLR__bulk_eot__BITNR 8 -#define R_USB_IRQ_MASK_CLR__epid_attn__BITNR 3 -#define R_USB_IRQ_MASK_CLR__sof__BITNR 2 -#define R_USB_IRQ_MASK_CLR__port_status__BITNR 1 -#define R_USB_IRQ_MASK_CLR__ctl_status__BITNR 0 - -#define R_USB_IRQ_MASK_CLR__iso_eof__iso_eof__VAL REG_VAL_ENUM -#define R_USB_IRQ_MASK_CLR__intr_eof__intr_eof__VAL REG_VAL_ENUM -#define R_USB_IRQ_MASK_CLR__iso_eot__iso_eot__VAL REG_VAL_ENUM -#define R_USB_IRQ_MASK_CLR__intr_eot__intr_eot__VAL REG_VAL_ENUM -#define R_USB_IRQ_MASK_CLR__ctl_eot__ctl_eot__VAL REG_VAL_ENUM -#define R_USB_IRQ_MASK_CLR__bulk_eot__bulk_eot__VAL REG_VAL_ENUM -#define R_USB_IRQ_MASK_CLR__epid_attn__epid_attn__VAL REG_VAL_ENUM -#define R_USB_IRQ_MASK_CLR__sof__sof__VAL REG_VAL_ENUM -#define R_USB_IRQ_MASK_CLR__port_status__port_status__VAL REG_VAL_ENUM -#define R_USB_IRQ_MASK_CLR__ctl_status__ctl_status__VAL REG_VAL_ENUM - -#define R_USB_IRQ_MASK_CLR__iso_eof__iso_eof__clr 1 -#define R_USB_IRQ_MASK_CLR__iso_eof__iso_eof__nop 0 -#define R_USB_IRQ_MASK_CLR__intr_eof__intr_eof__clr 1 -#define R_USB_IRQ_MASK_CLR__intr_eof__intr_eof__nop 0 -#define R_USB_IRQ_MASK_CLR__iso_eot__iso_eot__clr 1 -#define R_USB_IRQ_MASK_CLR__iso_eot__iso_eot__nop 0 -#define R_USB_IRQ_MASK_CLR__intr_eot__intr_eot__clr 1 -#define R_USB_IRQ_MASK_CLR__intr_eot__intr_eot__nop 0 -#define R_USB_IRQ_MASK_CLR__ctl_eot__ctl_eot__clr 1 -#define R_USB_IRQ_MASK_CLR__ctl_eot__ctl_eot__nop 0 -#define R_USB_IRQ_MASK_CLR__bulk_eot__bulk_eot__clr 1 -#define R_USB_IRQ_MASK_CLR__bulk_eot__bulk_eot__nop 0 -#define R_USB_IRQ_MASK_CLR__epid_attn__epid_attn__clr 1 -#define R_USB_IRQ_MASK_CLR__epid_attn__epid_attn__nop 0 -#define R_USB_IRQ_MASK_CLR__sof__sof__clr 1 -#define R_USB_IRQ_MASK_CLR__sof__sof__nop 0 -#define R_USB_IRQ_MASK_CLR__port_status__port_status__clr 1 -#define R_USB_IRQ_MASK_CLR__port_status__port_status__nop 0 -#define R_USB_IRQ_MASK_CLR__ctl_status__ctl_status__clr 1 -#define R_USB_IRQ_MASK_CLR__ctl_status__ctl_status__nop 0 - -#endif - -/* - * R_USB_IRQ_MASK_CLR_DEV - * - type: WO - * - addr: 0xb0000206 - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -#define R_USB_IRQ_MASK_CLR_DEV__ADDR (REG_TYPECAST_UWORD 0xb0000206) - -#ifndef REG_NO_SHADOW -#define R_USB_IRQ_MASK_CLR_DEV__SADDR (REG_STYPECAST_UWORD (reg_shadow__hwregs.R_USB_IRQ_MASK_CLR + 0)) -#define R_USB_IRQ_MASK_CLR_DEV__IADDR (REG_STYPECAST_UWORD (reg_initiated__hwregs.R_USB_IRQ_MASK_CLR + 0)) -#else /* REG_NO_SHADOW */ -#define R_USB_IRQ_MASK_CLR_DEV__SADDR (REG_STYPECAST_UWORD (®_shadow__hwregs)) -#define R_USB_IRQ_MASK_CLR_DEV__IADDR (REG_STYPECAST_UWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_USB_IRQ_MASK_CLR_DEV__STYPECAST REG_STYPECAST_UWORD -#define R_USB_IRQ_MASK_CLR_DEV__SVAL REG_SVAL_SHADOW -#define R_USB_IRQ_MASK_CLR_DEV__SVAL_I REG_SVAL_I_SHADOW -#define R_USB_IRQ_MASK_CLR_DEV__TYPECAST REG_TYPECAST_UWORD -#define R_USB_IRQ_MASK_CLR_DEV__TYPE (REG_UWORD) -#define R_USB_IRQ_MASK_CLR_DEV__GET REG_GET_WO -#define R_USB_IRQ_MASK_CLR_DEV__IGET REG_IGET_WO -#define R_USB_IRQ_MASK_CLR_DEV__SET REG_SET_WO -#define R_USB_IRQ_MASK_CLR_DEV__ISET REG_ISET_WO -#define R_USB_IRQ_MASK_CLR_DEV__SET_VAL REG_SET_VAL_WO -#define R_USB_IRQ_MASK_CLR_DEV__EQL REG_EQL_WO -#define R_USB_IRQ_MASK_CLR_DEV__IEQL REG_IEQL_WO -#define R_USB_IRQ_MASK_CLR_DEV__RD REG_RD_WO -#define R_USB_IRQ_MASK_CLR_DEV__IRD REG_IRD_WO -#define R_USB_IRQ_MASK_CLR_DEV__WR REG_WR_WO -#define R_USB_IRQ_MASK_CLR_DEV__IWR REG_IWR_WO - -#define R_USB_IRQ_MASK_CLR_DEV__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_USB_IRQ_MASK_CLR_DEV__out_eot__out_eot__MASK 0x00001000U -#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__ep3_in_eot__MASK 0x00000800U -#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__ep2_in_eot__MASK 0x00000400U -#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__ep1_in_eot__MASK 0x00000200U -#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__ep0_in_eot__MASK 0x00000100U -#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__epid_attn__MASK 0x00000008U -#define R_USB_IRQ_MASK_CLR_DEV__sof__sof__MASK 0x00000004U -#define R_USB_IRQ_MASK_CLR_DEV__port_status__port_status__MASK 0x00000002U -#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__ctl_status__MASK 0x00000001U - -#define R_USB_IRQ_MASK_CLR_DEV__out_eot__MAX 0x1 -#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__MAX 0x1 -#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__MAX 0x1 -#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__MAX 0x1 -#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__MAX 0x1 -#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__MAX 0x1 -#define R_USB_IRQ_MASK_CLR_DEV__sof__MAX 0x1 -#define R_USB_IRQ_MASK_CLR_DEV__port_status__MAX 0x1 -#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__MAX 0x1 - -#define R_USB_IRQ_MASK_CLR_DEV__out_eot__MIN 0 -#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__MIN 0 -#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__MIN 0 -#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__MIN 0 -#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__MIN 0 -#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__MIN 0 -#define R_USB_IRQ_MASK_CLR_DEV__sof__MIN 0 -#define R_USB_IRQ_MASK_CLR_DEV__port_status__MIN 0 -#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__MIN 0 - -#define R_USB_IRQ_MASK_CLR_DEV__out_eot__BITNR 12 -#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__BITNR 11 -#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__BITNR 10 -#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__BITNR 9 -#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__BITNR 8 -#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__BITNR 3 -#define R_USB_IRQ_MASK_CLR_DEV__sof__BITNR 2 -#define R_USB_IRQ_MASK_CLR_DEV__port_status__BITNR 1 -#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__BITNR 0 - -#define R_USB_IRQ_MASK_CLR_DEV__out_eot__out_eot__VAL REG_VAL_ENUM -#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__ep3_in_eot__VAL REG_VAL_ENUM -#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__ep2_in_eot__VAL REG_VAL_ENUM -#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__ep1_in_eot__VAL REG_VAL_ENUM -#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__ep0_in_eot__VAL REG_VAL_ENUM -#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__epid_attn__VAL REG_VAL_ENUM -#define R_USB_IRQ_MASK_CLR_DEV__sof__sof__VAL REG_VAL_ENUM -#define R_USB_IRQ_MASK_CLR_DEV__port_status__port_status__VAL REG_VAL_ENUM -#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__ctl_status__VAL REG_VAL_ENUM - -#define R_USB_IRQ_MASK_CLR_DEV__out_eot__out_eot__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__out_eot__out_eot__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__ep3_in_eot__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__ep3_in_eot__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__ep2_in_eot__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__ep2_in_eot__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__ep1_in_eot__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__ep1_in_eot__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__ep0_in_eot__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__ep0_in_eot__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__epid_attn__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__epid_attn__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__sof__sof__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__sof__sof__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__port_status__port_status__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__port_status__port_status__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__ctl_status__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__ctl_status__nop 0 - -#endif - -/* - * R_USB_IRQ_MASK_READ - * - type: RO - * - addr: 0xb0000204 - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -#define R_USB_IRQ_MASK_READ__ADDR (REG_TYPECAST_UWORD 0xb0000204) -#define R_USB_IRQ_MASK_READ__SVAL REG_SVAL_SHADOW -#define R_USB_IRQ_MASK_READ__SVAL_I REG_SVAL_I_SHADOW -#define R_USB_IRQ_MASK_READ__TYPECAST REG_TYPECAST_UWORD -#define R_USB_IRQ_MASK_READ__TYPE (REG_UWORD) -#define R_USB_IRQ_MASK_READ__GET REG_GET_RO -#define R_USB_IRQ_MASK_READ__IGET REG_IGET_RO -#define R_USB_IRQ_MASK_READ__SET REG_SET_RO -#define R_USB_IRQ_MASK_READ__ISET REG_ISET_RO -#define R_USB_IRQ_MASK_READ__SET_VAL REG_SET_VAL_RO -#define R_USB_IRQ_MASK_READ__EQL REG_EQL_RO -#define R_USB_IRQ_MASK_READ__IEQL REG_IEQL_RO -#define R_USB_IRQ_MASK_READ__RD REG_RD_RO -#define R_USB_IRQ_MASK_READ__IRD REG_IRD_RO -#define R_USB_IRQ_MASK_READ__WR REG_WR_RO -#define R_USB_IRQ_MASK_READ__IWR REG_IWR_RO - -#define R_USB_IRQ_MASK_READ__READ(addr) \ - (*(addr)) - -#define R_USB_IRQ_MASK_READ__iso_eof__iso_eof__MASK 0x00002000U -#define R_USB_IRQ_MASK_READ__intr_eof__intr_eof__MASK 0x00001000U -#define R_USB_IRQ_MASK_READ__iso_eot__iso_eot__MASK 0x00000800U -#define R_USB_IRQ_MASK_READ__intr_eot__intr_eot__MASK 0x00000400U -#define R_USB_IRQ_MASK_READ__ctl_eot__ctl_eot__MASK 0x00000200U -#define R_USB_IRQ_MASK_READ__bulk_eot__bulk_eot__MASK 0x00000100U -#define R_USB_IRQ_MASK_READ__epid_attn__epid_attn__MASK 0x00000008U -#define R_USB_IRQ_MASK_READ__sof__sof__MASK 0x00000004U -#define R_USB_IRQ_MASK_READ__port_status__port_status__MASK 0x00000002U -#define R_USB_IRQ_MASK_READ__ctl_status__ctl_status__MASK 0x00000001U - -#define R_USB_IRQ_MASK_READ__iso_eof__MAX 0x1 -#define R_USB_IRQ_MASK_READ__intr_eof__MAX 0x1 -#define R_USB_IRQ_MASK_READ__iso_eot__MAX 0x1 -#define R_USB_IRQ_MASK_READ__intr_eot__MAX 0x1 -#define R_USB_IRQ_MASK_READ__ctl_eot__MAX 0x1 -#define R_USB_IRQ_MASK_READ__bulk_eot__MAX 0x1 -#define R_USB_IRQ_MASK_READ__epid_attn__MAX 0x1 -#define R_USB_IRQ_MASK_READ__sof__MAX 0x1 -#define R_USB_IRQ_MASK_READ__port_status__MAX 0x1 -#define R_USB_IRQ_MASK_READ__ctl_status__MAX 0x1 - -#define R_USB_IRQ_MASK_READ__iso_eof__MIN 0 -#define R_USB_IRQ_MASK_READ__intr_eof__MIN 0 -#define R_USB_IRQ_MASK_READ__iso_eot__MIN 0 -#define R_USB_IRQ_MASK_READ__intr_eot__MIN 0 -#define R_USB_IRQ_MASK_READ__ctl_eot__MIN 0 -#define R_USB_IRQ_MASK_READ__bulk_eot__MIN 0 -#define R_USB_IRQ_MASK_READ__epid_attn__MIN 0 -#define R_USB_IRQ_MASK_READ__sof__MIN 0 -#define R_USB_IRQ_MASK_READ__port_status__MIN 0 -#define R_USB_IRQ_MASK_READ__ctl_status__MIN 0 - -#define R_USB_IRQ_MASK_READ__iso_eof__BITNR 13 -#define R_USB_IRQ_MASK_READ__intr_eof__BITNR 12 -#define R_USB_IRQ_MASK_READ__iso_eot__BITNR 11 -#define R_USB_IRQ_MASK_READ__intr_eot__BITNR 10 -#define R_USB_IRQ_MASK_READ__ctl_eot__BITNR 9 -#define R_USB_IRQ_MASK_READ__bulk_eot__BITNR 8 -#define R_USB_IRQ_MASK_READ__epid_attn__BITNR 3 -#define R_USB_IRQ_MASK_READ__sof__BITNR 2 -#define R_USB_IRQ_MASK_READ__port_status__BITNR 1 -#define R_USB_IRQ_MASK_READ__ctl_status__BITNR 0 - -#define R_USB_IRQ_MASK_READ__iso_eof__iso_eof__VAL REG_VAL_ENUM -#define R_USB_IRQ_MASK_READ__intr_eof__intr_eof__VAL REG_VAL_ENUM -#define R_USB_IRQ_MASK_READ__iso_eot__iso_eot__VAL REG_VAL_ENUM -#define R_USB_IRQ_MASK_READ__intr_eot__intr_eot__VAL REG_VAL_ENUM -#define R_USB_IRQ_MASK_READ__ctl_eot__ctl_eot__VAL REG_VAL_ENUM -#define R_USB_IRQ_MASK_READ__bulk_eot__bulk_eot__VAL REG_VAL_ENUM -#define R_USB_IRQ_MASK_READ__epid_attn__epid_attn__VAL REG_VAL_ENUM -#define R_USB_IRQ_MASK_READ__sof__sof__VAL REG_VAL_ENUM -#define R_USB_IRQ_MASK_READ__port_status__port_status__VAL REG_VAL_ENUM -#define R_USB_IRQ_MASK_READ__ctl_status__ctl_status__VAL REG_VAL_ENUM - -#define R_USB_IRQ_MASK_READ__iso_eof__iso_eof__no_pend 0 -#define R_USB_IRQ_MASK_READ__iso_eof__iso_eof__pend 1 -#define R_USB_IRQ_MASK_READ__intr_eof__intr_eof__no_pend 0 -#define R_USB_IRQ_MASK_READ__intr_eof__intr_eof__pend 1 -#define R_USB_IRQ_MASK_READ__iso_eot__iso_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ__iso_eot__iso_eot__pend 1 -#define R_USB_IRQ_MASK_READ__intr_eot__intr_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ__intr_eot__intr_eot__pend 1 -#define R_USB_IRQ_MASK_READ__ctl_eot__ctl_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ__ctl_eot__ctl_eot__pend 1 -#define R_USB_IRQ_MASK_READ__bulk_eot__bulk_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ__bulk_eot__bulk_eot__pend 1 -#define R_USB_IRQ_MASK_READ__epid_attn__epid_attn__no_pend 0 -#define R_USB_IRQ_MASK_READ__epid_attn__epid_attn__pend 1 -#define R_USB_IRQ_MASK_READ__sof__sof__no_pend 0 -#define R_USB_IRQ_MASK_READ__sof__sof__pend 1 -#define R_USB_IRQ_MASK_READ__port_status__port_status__no_pend 0 -#define R_USB_IRQ_MASK_READ__port_status__port_status__pend 1 -#define R_USB_IRQ_MASK_READ__ctl_status__ctl_status__no_pend 0 -#define R_USB_IRQ_MASK_READ__ctl_status__ctl_status__pend 1 - -#endif - -/* - * R_USB_IRQ_MASK_READ_DEV - * - type: RO - * - addr: 0xb0000204 - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -#define R_USB_IRQ_MASK_READ_DEV__ADDR (REG_TYPECAST_UWORD 0xb0000204) -#define R_USB_IRQ_MASK_READ_DEV__SVAL REG_SVAL_SHADOW -#define R_USB_IRQ_MASK_READ_DEV__SVAL_I REG_SVAL_I_SHADOW -#define R_USB_IRQ_MASK_READ_DEV__TYPECAST REG_TYPECAST_UWORD -#define R_USB_IRQ_MASK_READ_DEV__TYPE (REG_UWORD) -#define R_USB_IRQ_MASK_READ_DEV__GET REG_GET_RO -#define R_USB_IRQ_MASK_READ_DEV__IGET REG_IGET_RO -#define R_USB_IRQ_MASK_READ_DEV__SET REG_SET_RO -#define R_USB_IRQ_MASK_READ_DEV__ISET REG_ISET_RO -#define R_USB_IRQ_MASK_READ_DEV__SET_VAL REG_SET_VAL_RO -#define R_USB_IRQ_MASK_READ_DEV__EQL REG_EQL_RO -#define R_USB_IRQ_MASK_READ_DEV__IEQL REG_IEQL_RO -#define R_USB_IRQ_MASK_READ_DEV__RD REG_RD_RO -#define R_USB_IRQ_MASK_READ_DEV__IRD REG_IRD_RO -#define R_USB_IRQ_MASK_READ_DEV__WR REG_WR_RO -#define R_USB_IRQ_MASK_READ_DEV__IWR REG_IWR_RO - -#define R_USB_IRQ_MASK_READ_DEV__READ(addr) \ - (*(addr)) - -#define R_USB_IRQ_MASK_READ_DEV__out_eot__out_eot__MASK 0x00001000U -#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__ep3_in_eot__MASK 0x00000800U -#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__ep2_in_eot__MASK 0x00000400U -#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__ep1_in_eot__MASK 0x00000200U -#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__ep0_in_eot__MASK 0x00000100U -#define R_USB_IRQ_MASK_READ_DEV__epid_attn__epid_attn__MASK 0x00000008U -#define R_USB_IRQ_MASK_READ_DEV__sof__sof__MASK 0x00000004U -#define R_USB_IRQ_MASK_READ_DEV__port_status__port_status__MASK 0x00000002U -#define R_USB_IRQ_MASK_READ_DEV__ctl_status__ctl_status__MASK 0x00000001U - -#define R_USB_IRQ_MASK_READ_DEV__out_eot__MAX 0x1 -#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__MAX 0x1 -#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__MAX 0x1 -#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__MAX 0x1 -#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__MAX 0x1 -#define R_USB_IRQ_MASK_READ_DEV__epid_attn__MAX 0x1 -#define R_USB_IRQ_MASK_READ_DEV__sof__MAX 0x1 -#define R_USB_IRQ_MASK_READ_DEV__port_status__MAX 0x1 -#define R_USB_IRQ_MASK_READ_DEV__ctl_status__MAX 0x1 - -#define R_USB_IRQ_MASK_READ_DEV__out_eot__MIN 0 -#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__MIN 0 -#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__MIN 0 -#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__MIN 0 -#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__MIN 0 -#define R_USB_IRQ_MASK_READ_DEV__epid_attn__MIN 0 -#define R_USB_IRQ_MASK_READ_DEV__sof__MIN 0 -#define R_USB_IRQ_MASK_READ_DEV__port_status__MIN 0 -#define R_USB_IRQ_MASK_READ_DEV__ctl_status__MIN 0 - -#define R_USB_IRQ_MASK_READ_DEV__out_eot__BITNR 12 -#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__BITNR 11 -#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__BITNR 10 -#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__BITNR 9 -#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__BITNR 8 -#define R_USB_IRQ_MASK_READ_DEV__epid_attn__BITNR 3 -#define R_USB_IRQ_MASK_READ_DEV__sof__BITNR 2 -#define R_USB_IRQ_MASK_READ_DEV__port_status__BITNR 1 -#define R_USB_IRQ_MASK_READ_DEV__ctl_status__BITNR 0 - -#define R_USB_IRQ_MASK_READ_DEV__out_eot__out_eot__VAL REG_VAL_ENUM -#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__ep3_in_eot__VAL REG_VAL_ENUM -#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__ep2_in_eot__VAL REG_VAL_ENUM -#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__ep1_in_eot__VAL REG_VAL_ENUM -#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__ep0_in_eot__VAL REG_VAL_ENUM -#define R_USB_IRQ_MASK_READ_DEV__epid_attn__epid_attn__VAL REG_VAL_ENUM -#define R_USB_IRQ_MASK_READ_DEV__sof__sof__VAL REG_VAL_ENUM -#define R_USB_IRQ_MASK_READ_DEV__port_status__port_status__VAL REG_VAL_ENUM -#define R_USB_IRQ_MASK_READ_DEV__ctl_status__ctl_status__VAL REG_VAL_ENUM - -#define R_USB_IRQ_MASK_READ_DEV__out_eot__out_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__out_eot__out_eot__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__ep3_in_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__ep3_in_eot__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__ep2_in_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__ep2_in_eot__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__ep1_in_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__ep1_in_eot__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__ep0_in_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__ep0_in_eot__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__epid_attn__epid_attn__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__epid_attn__epid_attn__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__sof__sof__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__sof__sof__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__port_status__port_status__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__port_status__port_status__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__ctl_status__ctl_status__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__ctl_status__ctl_status__pend 1 - -#endif - -/* - * R_USB_IRQ_MASK_SET - * - type: WO - * - addr: 0xb0000204 - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -#define R_USB_IRQ_MASK_SET__ADDR (REG_TYPECAST_UWORD 0xb0000204) - -#ifndef REG_NO_SHADOW -#define R_USB_IRQ_MASK_SET__SADDR (REG_STYPECAST_UWORD (reg_shadow__hwregs.R_USB_IRQ_MASK_SET + 0)) -#define R_USB_IRQ_MASK_SET__IADDR (REG_STYPECAST_UWORD (reg_initiated__hwregs.R_USB_IRQ_MASK_SET + 0)) -#else /* REG_NO_SHADOW */ -#define R_USB_IRQ_MASK_SET__SADDR (REG_STYPECAST_UWORD (®_shadow__hwregs)) -#define R_USB_IRQ_MASK_SET__IADDR (REG_STYPECAST_UWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_USB_IRQ_MASK_SET__STYPECAST REG_STYPECAST_UWORD -#define R_USB_IRQ_MASK_SET__SVAL REG_SVAL_ZERO -#define R_USB_IRQ_MASK_SET__SVAL_I REG_SVAL_I_ZERO -#define R_USB_IRQ_MASK_SET__TYPECAST REG_TYPECAST_UWORD -#define R_USB_IRQ_MASK_SET__TYPE (REG_UWORD) -#define R_USB_IRQ_MASK_SET__GET REG_GET_WO -#define R_USB_IRQ_MASK_SET__IGET REG_IGET_WO -#define R_USB_IRQ_MASK_SET__SET REG_SET_WO -#define R_USB_IRQ_MASK_SET__ISET REG_ISET_WO -#define R_USB_IRQ_MASK_SET__SET_VAL REG_SET_VAL_WO -#define R_USB_IRQ_MASK_SET__EQL REG_EQL_WO -#define R_USB_IRQ_MASK_SET__IEQL REG_IEQL_WO -#define R_USB_IRQ_MASK_SET__RD REG_RD_WO -#define R_USB_IRQ_MASK_SET__IRD REG_IRD_WO -#define R_USB_IRQ_MASK_SET__WR REG_WR_WO -#define R_USB_IRQ_MASK_SET__IWR REG_IWR_WO - -#define R_USB_IRQ_MASK_SET__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_USB_IRQ_MASK_SET__iso_eof__iso_eof__MASK 0x00002000U -#define R_USB_IRQ_MASK_SET__intr_eof__intr_eof__MASK 0x00001000U -#define R_USB_IRQ_MASK_SET__iso_eot__iso_eot__MASK 0x00000800U -#define R_USB_IRQ_MASK_SET__intr_eot__intr_eot__MASK 0x00000400U -#define R_USB_IRQ_MASK_SET__ctl_eot__ctl_eot__MASK 0x00000200U -#define R_USB_IRQ_MASK_SET__bulk_eot__bulk_eot__MASK 0x00000100U -#define R_USB_IRQ_MASK_SET__epid_attn__epid_attn__MASK 0x00000008U -#define R_USB_IRQ_MASK_SET__sof__sof__MASK 0x00000004U -#define R_USB_IRQ_MASK_SET__port_status__port_status__MASK 0x00000002U -#define R_USB_IRQ_MASK_SET__ctl_status__ctl_status__MASK 0x00000001U - -#define R_USB_IRQ_MASK_SET__iso_eof__MAX 0x1 -#define R_USB_IRQ_MASK_SET__intr_eof__MAX 0x1 -#define R_USB_IRQ_MASK_SET__iso_eot__MAX 0x1 -#define R_USB_IRQ_MASK_SET__intr_eot__MAX 0x1 -#define R_USB_IRQ_MASK_SET__ctl_eot__MAX 0x1 -#define R_USB_IRQ_MASK_SET__bulk_eot__MAX 0x1 -#define R_USB_IRQ_MASK_SET__epid_attn__MAX 0x1 -#define R_USB_IRQ_MASK_SET__sof__MAX 0x1 -#define R_USB_IRQ_MASK_SET__port_status__MAX 0x1 -#define R_USB_IRQ_MASK_SET__ctl_status__MAX 0x1 - -#define R_USB_IRQ_MASK_SET__iso_eof__MIN 0 -#define R_USB_IRQ_MASK_SET__intr_eof__MIN 0 -#define R_USB_IRQ_MASK_SET__iso_eot__MIN 0 -#define R_USB_IRQ_MASK_SET__intr_eot__MIN 0 -#define R_USB_IRQ_MASK_SET__ctl_eot__MIN 0 -#define R_USB_IRQ_MASK_SET__bulk_eot__MIN 0 -#define R_USB_IRQ_MASK_SET__epid_attn__MIN 0 -#define R_USB_IRQ_MASK_SET__sof__MIN 0 -#define R_USB_IRQ_MASK_SET__port_status__MIN 0 -#define R_USB_IRQ_MASK_SET__ctl_status__MIN 0 - -#define R_USB_IRQ_MASK_SET__iso_eof__BITNR 13 -#define R_USB_IRQ_MASK_SET__intr_eof__BITNR 12 -#define R_USB_IRQ_MASK_SET__iso_eot__BITNR 11 -#define R_USB_IRQ_MASK_SET__intr_eot__BITNR 10 -#define R_USB_IRQ_MASK_SET__ctl_eot__BITNR 9 -#define R_USB_IRQ_MASK_SET__bulk_eot__BITNR 8 -#define R_USB_IRQ_MASK_SET__epid_attn__BITNR 3 -#define R_USB_IRQ_MASK_SET__sof__BITNR 2 -#define R_USB_IRQ_MASK_SET__port_status__BITNR 1 -#define R_USB_IRQ_MASK_SET__ctl_status__BITNR 0 - -#define R_USB_IRQ_MASK_SET__iso_eof__iso_eof__VAL REG_VAL_ENUM -#define R_USB_IRQ_MASK_SET__intr_eof__intr_eof__VAL REG_VAL_ENUM -#define R_USB_IRQ_MASK_SET__iso_eot__iso_eot__VAL REG_VAL_ENUM -#define R_USB_IRQ_MASK_SET__intr_eot__intr_eot__VAL REG_VAL_ENUM -#define R_USB_IRQ_MASK_SET__ctl_eot__ctl_eot__VAL REG_VAL_ENUM -#define R_USB_IRQ_MASK_SET__bulk_eot__bulk_eot__VAL REG_VAL_ENUM -#define R_USB_IRQ_MASK_SET__epid_attn__epid_attn__VAL REG_VAL_ENUM -#define R_USB_IRQ_MASK_SET__sof__sof__VAL REG_VAL_ENUM -#define R_USB_IRQ_MASK_SET__port_status__port_status__VAL REG_VAL_ENUM -#define R_USB_IRQ_MASK_SET__ctl_status__ctl_status__VAL REG_VAL_ENUM - -#define R_USB_IRQ_MASK_SET__iso_eof__iso_eof__nop 0 -#define R_USB_IRQ_MASK_SET__iso_eof__iso_eof__set 1 -#define R_USB_IRQ_MASK_SET__intr_eof__intr_eof__nop 0 -#define R_USB_IRQ_MASK_SET__intr_eof__intr_eof__set 1 -#define R_USB_IRQ_MASK_SET__iso_eot__iso_eot__nop 0 -#define R_USB_IRQ_MASK_SET__iso_eot__iso_eot__set 1 -#define R_USB_IRQ_MASK_SET__intr_eot__intr_eot__nop 0 -#define R_USB_IRQ_MASK_SET__intr_eot__intr_eot__set 1 -#define R_USB_IRQ_MASK_SET__ctl_eot__ctl_eot__nop 0 -#define R_USB_IRQ_MASK_SET__ctl_eot__ctl_eot__set 1 -#define R_USB_IRQ_MASK_SET__bulk_eot__bulk_eot__nop 0 -#define R_USB_IRQ_MASK_SET__bulk_eot__bulk_eot__set 1 -#define R_USB_IRQ_MASK_SET__epid_attn__epid_attn__nop 0 -#define R_USB_IRQ_MASK_SET__epid_attn__epid_attn__set 1 -#define R_USB_IRQ_MASK_SET__sof__sof__nop 0 -#define R_USB_IRQ_MASK_SET__sof__sof__set 1 -#define R_USB_IRQ_MASK_SET__port_status__port_status__nop 0 -#define R_USB_IRQ_MASK_SET__port_status__port_status__set 1 -#define R_USB_IRQ_MASK_SET__ctl_status__ctl_status__nop 0 -#define R_USB_IRQ_MASK_SET__ctl_status__ctl_status__set 1 - -#endif - -/* - * R_USB_IRQ_MASK_SET_DEV - * - type: WO - * - addr: 0xb0000204 - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -#define R_USB_IRQ_MASK_SET_DEV__ADDR (REG_TYPECAST_UWORD 0xb0000204) - -#ifndef REG_NO_SHADOW -#define R_USB_IRQ_MASK_SET_DEV__SADDR (REG_STYPECAST_UWORD (reg_shadow__hwregs.R_USB_IRQ_MASK_SET + 0)) -#define R_USB_IRQ_MASK_SET_DEV__IADDR (REG_STYPECAST_UWORD (reg_initiated__hwregs.R_USB_IRQ_MASK_SET + 0)) -#else /* REG_NO_SHADOW */ -#define R_USB_IRQ_MASK_SET_DEV__SADDR (REG_STYPECAST_UWORD (®_shadow__hwregs)) -#define R_USB_IRQ_MASK_SET_DEV__IADDR (REG_STYPECAST_UWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_USB_IRQ_MASK_SET_DEV__STYPECAST REG_STYPECAST_UWORD -#define R_USB_IRQ_MASK_SET_DEV__SVAL REG_SVAL_SHADOW -#define R_USB_IRQ_MASK_SET_DEV__SVAL_I REG_SVAL_I_SHADOW -#define R_USB_IRQ_MASK_SET_DEV__TYPECAST REG_TYPECAST_UWORD -#define R_USB_IRQ_MASK_SET_DEV__TYPE (REG_UWORD) -#define R_USB_IRQ_MASK_SET_DEV__GET REG_GET_WO -#define R_USB_IRQ_MASK_SET_DEV__IGET REG_IGET_WO -#define R_USB_IRQ_MASK_SET_DEV__SET REG_SET_WO -#define R_USB_IRQ_MASK_SET_DEV__ISET REG_ISET_WO -#define R_USB_IRQ_MASK_SET_DEV__SET_VAL REG_SET_VAL_WO -#define R_USB_IRQ_MASK_SET_DEV__EQL REG_EQL_WO -#define R_USB_IRQ_MASK_SET_DEV__IEQL REG_IEQL_WO -#define R_USB_IRQ_MASK_SET_DEV__RD REG_RD_WO -#define R_USB_IRQ_MASK_SET_DEV__IRD REG_IRD_WO -#define R_USB_IRQ_MASK_SET_DEV__WR REG_WR_WO -#define R_USB_IRQ_MASK_SET_DEV__IWR REG_IWR_WO - -#define R_USB_IRQ_MASK_SET_DEV__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_USB_IRQ_MASK_SET_DEV__out_eot__out_eot__MASK 0x00001000U -#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__ep3_in_eot__MASK 0x00000800U -#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__ep2_in_eot__MASK 0x00000400U -#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__ep1_in_eot__MASK 0x00000200U -#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__ep0_in_eot__MASK 0x00000100U -#define R_USB_IRQ_MASK_SET_DEV__epid_attn__epid_attn__MASK 0x00000008U -#define R_USB_IRQ_MASK_SET_DEV__sof__sof__MASK 0x00000004U -#define R_USB_IRQ_MASK_SET_DEV__port_status__port_status__MASK 0x00000002U -#define R_USB_IRQ_MASK_SET_DEV__ctl_status__ctl_status__MASK 0x00000001U - -#define R_USB_IRQ_MASK_SET_DEV__out_eot__MAX 0x1 -#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__MAX 0x1 -#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__MAX 0x1 -#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__MAX 0x1 -#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__MAX 0x1 -#define R_USB_IRQ_MASK_SET_DEV__epid_attn__MAX 0x1 -#define R_USB_IRQ_MASK_SET_DEV__sof__MAX 0x1 -#define R_USB_IRQ_MASK_SET_DEV__port_status__MAX 0x1 -#define R_USB_IRQ_MASK_SET_DEV__ctl_status__MAX 0x1 - -#define R_USB_IRQ_MASK_SET_DEV__out_eot__MIN 0 -#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__MIN 0 -#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__MIN 0 -#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__MIN 0 -#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__MIN 0 -#define R_USB_IRQ_MASK_SET_DEV__epid_attn__MIN 0 -#define R_USB_IRQ_MASK_SET_DEV__sof__MIN 0 -#define R_USB_IRQ_MASK_SET_DEV__port_status__MIN 0 -#define R_USB_IRQ_MASK_SET_DEV__ctl_status__MIN 0 - -#define R_USB_IRQ_MASK_SET_DEV__out_eot__BITNR 12 -#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__BITNR 11 -#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__BITNR 10 -#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__BITNR 9 -#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__BITNR 8 -#define R_USB_IRQ_MASK_SET_DEV__epid_attn__BITNR 3 -#define R_USB_IRQ_MASK_SET_DEV__sof__BITNR 2 -#define R_USB_IRQ_MASK_SET_DEV__port_status__BITNR 1 -#define R_USB_IRQ_MASK_SET_DEV__ctl_status__BITNR 0 - -#define R_USB_IRQ_MASK_SET_DEV__out_eot__out_eot__VAL REG_VAL_ENUM -#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__ep3_in_eot__VAL REG_VAL_ENUM -#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__ep2_in_eot__VAL REG_VAL_ENUM -#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__ep1_in_eot__VAL REG_VAL_ENUM -#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__ep0_in_eot__VAL REG_VAL_ENUM -#define R_USB_IRQ_MASK_SET_DEV__epid_attn__epid_attn__VAL REG_VAL_ENUM -#define R_USB_IRQ_MASK_SET_DEV__sof__sof__VAL REG_VAL_ENUM -#define R_USB_IRQ_MASK_SET_DEV__port_status__port_status__VAL REG_VAL_ENUM -#define R_USB_IRQ_MASK_SET_DEV__ctl_status__ctl_status__VAL REG_VAL_ENUM - -#define R_USB_IRQ_MASK_SET_DEV__out_eot__out_eot__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__out_eot__out_eot__set 1 -#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__ep3_in_eot__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__ep3_in_eot__set 1 -#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__ep2_in_eot__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__ep2_in_eot__set 1 -#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__ep1_in_eot__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__ep1_in_eot__set 1 -#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__ep0_in_eot__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__ep0_in_eot__set 1 -#define R_USB_IRQ_MASK_SET_DEV__epid_attn__epid_attn__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__epid_attn__epid_attn__set 1 -#define R_USB_IRQ_MASK_SET_DEV__sof__sof__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__sof__sof__set 1 -#define R_USB_IRQ_MASK_SET_DEV__port_status__port_status__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__port_status__port_status__set 1 -#define R_USB_IRQ_MASK_SET_DEV__ctl_status__ctl_status__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__ctl_status__ctl_status__set 1 - -#endif - -/* - * R_USB_IRQ_READ - * - type: RO - * - addr: 0xb0000206 - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -#define R_USB_IRQ_READ__ADDR (REG_TYPECAST_UWORD 0xb0000206) -#define R_USB_IRQ_READ__SVAL REG_SVAL_SHADOW -#define R_USB_IRQ_READ__SVAL_I REG_SVAL_I_SHADOW -#define R_USB_IRQ_READ__TYPECAST REG_TYPECAST_UWORD -#define R_USB_IRQ_READ__TYPE (REG_UWORD) -#define R_USB_IRQ_READ__GET REG_GET_RO -#define R_USB_IRQ_READ__IGET REG_IGET_RO -#define R_USB_IRQ_READ__SET REG_SET_RO -#define R_USB_IRQ_READ__ISET REG_ISET_RO -#define R_USB_IRQ_READ__SET_VAL REG_SET_VAL_RO -#define R_USB_IRQ_READ__EQL REG_EQL_RO -#define R_USB_IRQ_READ__IEQL REG_IEQL_RO -#define R_USB_IRQ_READ__RD REG_RD_RO -#define R_USB_IRQ_READ__IRD REG_IRD_RO -#define R_USB_IRQ_READ__WR REG_WR_RO -#define R_USB_IRQ_READ__IWR REG_IWR_RO - -#define R_USB_IRQ_READ__READ(addr) \ - (*(addr)) - -#define R_USB_IRQ_READ__iso_eof__iso_eof__MASK 0x00002000U -#define R_USB_IRQ_READ__intr_eof__intr_eof__MASK 0x00001000U -#define R_USB_IRQ_READ__iso_eot__iso_eot__MASK 0x00000800U -#define R_USB_IRQ_READ__intr_eot__intr_eot__MASK 0x00000400U -#define R_USB_IRQ_READ__ctl_eot__ctl_eot__MASK 0x00000200U -#define R_USB_IRQ_READ__bulk_eot__bulk_eot__MASK 0x00000100U -#define R_USB_IRQ_READ__epid_attn__epid_attn__MASK 0x00000008U -#define R_USB_IRQ_READ__sof__sof__MASK 0x00000004U -#define R_USB_IRQ_READ__port_status__port_status__MASK 0x00000002U -#define R_USB_IRQ_READ__ctl_status__ctl_status__MASK 0x00000001U - -#define R_USB_IRQ_READ__iso_eof__MAX 0x1 -#define R_USB_IRQ_READ__intr_eof__MAX 0x1 -#define R_USB_IRQ_READ__iso_eot__MAX 0x1 -#define R_USB_IRQ_READ__intr_eot__MAX 0x1 -#define R_USB_IRQ_READ__ctl_eot__MAX 0x1 -#define R_USB_IRQ_READ__bulk_eot__MAX 0x1 -#define R_USB_IRQ_READ__epid_attn__MAX 0x1 -#define R_USB_IRQ_READ__sof__MAX 0x1 -#define R_USB_IRQ_READ__port_status__MAX 0x1 -#define R_USB_IRQ_READ__ctl_status__MAX 0x1 - -#define R_USB_IRQ_READ__iso_eof__MIN 0 -#define R_USB_IRQ_READ__intr_eof__MIN 0 -#define R_USB_IRQ_READ__iso_eot__MIN 0 -#define R_USB_IRQ_READ__intr_eot__MIN 0 -#define R_USB_IRQ_READ__ctl_eot__MIN 0 -#define R_USB_IRQ_READ__bulk_eot__MIN 0 -#define R_USB_IRQ_READ__epid_attn__MIN 0 -#define R_USB_IRQ_READ__sof__MIN 0 -#define R_USB_IRQ_READ__port_status__MIN 0 -#define R_USB_IRQ_READ__ctl_status__MIN 0 - -#define R_USB_IRQ_READ__iso_eof__BITNR 13 -#define R_USB_IRQ_READ__intr_eof__BITNR 12 -#define R_USB_IRQ_READ__iso_eot__BITNR 11 -#define R_USB_IRQ_READ__intr_eot__BITNR 10 -#define R_USB_IRQ_READ__ctl_eot__BITNR 9 -#define R_USB_IRQ_READ__bulk_eot__BITNR 8 -#define R_USB_IRQ_READ__epid_attn__BITNR 3 -#define R_USB_IRQ_READ__sof__BITNR 2 -#define R_USB_IRQ_READ__port_status__BITNR 1 -#define R_USB_IRQ_READ__ctl_status__BITNR 0 - -#define R_USB_IRQ_READ__iso_eof__iso_eof__VAL REG_VAL_ENUM -#define R_USB_IRQ_READ__intr_eof__intr_eof__VAL REG_VAL_ENUM -#define R_USB_IRQ_READ__iso_eot__iso_eot__VAL REG_VAL_ENUM -#define R_USB_IRQ_READ__intr_eot__intr_eot__VAL REG_VAL_ENUM -#define R_USB_IRQ_READ__ctl_eot__ctl_eot__VAL REG_VAL_ENUM -#define R_USB_IRQ_READ__bulk_eot__bulk_eot__VAL REG_VAL_ENUM -#define R_USB_IRQ_READ__epid_attn__epid_attn__VAL REG_VAL_ENUM -#define R_USB_IRQ_READ__sof__sof__VAL REG_VAL_ENUM -#define R_USB_IRQ_READ__port_status__port_status__VAL REG_VAL_ENUM -#define R_USB_IRQ_READ__ctl_status__ctl_status__VAL REG_VAL_ENUM - -#define R_USB_IRQ_READ__iso_eof__iso_eof__no_pend 0 -#define R_USB_IRQ_READ__iso_eof__iso_eof__pend 1 -#define R_USB_IRQ_READ__intr_eof__intr_eof__no_pend 0 -#define R_USB_IRQ_READ__intr_eof__intr_eof__pend 1 -#define R_USB_IRQ_READ__iso_eot__iso_eot__no_pend 0 -#define R_USB_IRQ_READ__iso_eot__iso_eot__pend 1 -#define R_USB_IRQ_READ__intr_eot__intr_eot__no_pend 0 -#define R_USB_IRQ_READ__intr_eot__intr_eot__pend 1 -#define R_USB_IRQ_READ__ctl_eot__ctl_eot__no_pend 0 -#define R_USB_IRQ_READ__ctl_eot__ctl_eot__pend 1 -#define R_USB_IRQ_READ__bulk_eot__bulk_eot__no_pend 0 -#define R_USB_IRQ_READ__bulk_eot__bulk_eot__pend 1 -#define R_USB_IRQ_READ__epid_attn__epid_attn__no_pend 0 -#define R_USB_IRQ_READ__epid_attn__epid_attn__pend 1 -#define R_USB_IRQ_READ__sof__sof__no_pend 0 -#define R_USB_IRQ_READ__sof__sof__pend 1 -#define R_USB_IRQ_READ__port_status__port_status__no_pend 0 -#define R_USB_IRQ_READ__port_status__port_status__pend 1 -#define R_USB_IRQ_READ__ctl_status__ctl_status__no_pend 0 -#define R_USB_IRQ_READ__ctl_status__ctl_status__pend 1 - -#endif - -/* - * R_USB_IRQ_READ_DEV - * - type: RO - * - addr: 0xb0000206 - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -#define R_USB_IRQ_READ_DEV__ADDR (REG_TYPECAST_UWORD 0xb0000206) -#define R_USB_IRQ_READ_DEV__SVAL REG_SVAL_SHADOW -#define R_USB_IRQ_READ_DEV__SVAL_I REG_SVAL_I_SHADOW -#define R_USB_IRQ_READ_DEV__TYPECAST REG_TYPECAST_UWORD -#define R_USB_IRQ_READ_DEV__TYPE (REG_UWORD) -#define R_USB_IRQ_READ_DEV__GET REG_GET_RO -#define R_USB_IRQ_READ_DEV__IGET REG_IGET_RO -#define R_USB_IRQ_READ_DEV__SET REG_SET_RO -#define R_USB_IRQ_READ_DEV__ISET REG_ISET_RO -#define R_USB_IRQ_READ_DEV__SET_VAL REG_SET_VAL_RO -#define R_USB_IRQ_READ_DEV__EQL REG_EQL_RO -#define R_USB_IRQ_READ_DEV__IEQL REG_IEQL_RO -#define R_USB_IRQ_READ_DEV__RD REG_RD_RO -#define R_USB_IRQ_READ_DEV__IRD REG_IRD_RO -#define R_USB_IRQ_READ_DEV__WR REG_WR_RO -#define R_USB_IRQ_READ_DEV__IWR REG_IWR_RO - -#define R_USB_IRQ_READ_DEV__READ(addr) \ - (*(addr)) - -#define R_USB_IRQ_READ_DEV__out_eot__out_eot__MASK 0x00001000U -#define R_USB_IRQ_READ_DEV__ep3_in_eot__ep3_in_eot__MASK 0x00000800U -#define R_USB_IRQ_READ_DEV__ep2_in_eot__ep2_in_eot__MASK 0x00000400U -#define R_USB_IRQ_READ_DEV__ep1_in_eot__ep1_in_eot__MASK 0x00000200U -#define R_USB_IRQ_READ_DEV__ep0_in_eot__ep0_in_eot__MASK 0x00000100U -#define R_USB_IRQ_READ_DEV__epid_attn__epid_attn__MASK 0x00000008U -#define R_USB_IRQ_READ_DEV__sof__sof__MASK 0x00000004U -#define R_USB_IRQ_READ_DEV__port_status__port_status__MASK 0x00000002U -#define R_USB_IRQ_READ_DEV__ctl_status__ctl_status__MASK 0x00000001U - -#define R_USB_IRQ_READ_DEV__out_eot__MAX 0x1 -#define R_USB_IRQ_READ_DEV__ep3_in_eot__MAX 0x1 -#define R_USB_IRQ_READ_DEV__ep2_in_eot__MAX 0x1 -#define R_USB_IRQ_READ_DEV__ep1_in_eot__MAX 0x1 -#define R_USB_IRQ_READ_DEV__ep0_in_eot__MAX 0x1 -#define R_USB_IRQ_READ_DEV__epid_attn__MAX 0x1 -#define R_USB_IRQ_READ_DEV__sof__MAX 0x1 -#define R_USB_IRQ_READ_DEV__port_status__MAX 0x1 -#define R_USB_IRQ_READ_DEV__ctl_status__MAX 0x1 - -#define R_USB_IRQ_READ_DEV__out_eot__MIN 0 -#define R_USB_IRQ_READ_DEV__ep3_in_eot__MIN 0 -#define R_USB_IRQ_READ_DEV__ep2_in_eot__MIN 0 -#define R_USB_IRQ_READ_DEV__ep1_in_eot__MIN 0 -#define R_USB_IRQ_READ_DEV__ep0_in_eot__MIN 0 -#define R_USB_IRQ_READ_DEV__epid_attn__MIN 0 -#define R_USB_IRQ_READ_DEV__sof__MIN 0 -#define R_USB_IRQ_READ_DEV__port_status__MIN 0 -#define R_USB_IRQ_READ_DEV__ctl_status__MIN 0 - -#define R_USB_IRQ_READ_DEV__out_eot__BITNR 12 -#define R_USB_IRQ_READ_DEV__ep3_in_eot__BITNR 11 -#define R_USB_IRQ_READ_DEV__ep2_in_eot__BITNR 10 -#define R_USB_IRQ_READ_DEV__ep1_in_eot__BITNR 9 -#define R_USB_IRQ_READ_DEV__ep0_in_eot__BITNR 8 -#define R_USB_IRQ_READ_DEV__epid_attn__BITNR 3 -#define R_USB_IRQ_READ_DEV__sof__BITNR 2 -#define R_USB_IRQ_READ_DEV__port_status__BITNR 1 -#define R_USB_IRQ_READ_DEV__ctl_status__BITNR 0 - -#define R_USB_IRQ_READ_DEV__out_eot__out_eot__VAL REG_VAL_ENUM -#define R_USB_IRQ_READ_DEV__ep3_in_eot__ep3_in_eot__VAL REG_VAL_ENUM -#define R_USB_IRQ_READ_DEV__ep2_in_eot__ep2_in_eot__VAL REG_VAL_ENUM -#define R_USB_IRQ_READ_DEV__ep1_in_eot__ep1_in_eot__VAL REG_VAL_ENUM -#define R_USB_IRQ_READ_DEV__ep0_in_eot__ep0_in_eot__VAL REG_VAL_ENUM -#define R_USB_IRQ_READ_DEV__epid_attn__epid_attn__VAL REG_VAL_ENUM -#define R_USB_IRQ_READ_DEV__sof__sof__VAL REG_VAL_ENUM -#define R_USB_IRQ_READ_DEV__port_status__port_status__VAL REG_VAL_ENUM -#define R_USB_IRQ_READ_DEV__ctl_status__ctl_status__VAL REG_VAL_ENUM - -#define R_USB_IRQ_READ_DEV__out_eot__out_eot__no_pend 0 -#define R_USB_IRQ_READ_DEV__out_eot__out_eot__pend 1 -#define R_USB_IRQ_READ_DEV__ep3_in_eot__ep3_in_eot__no_pend 0 -#define R_USB_IRQ_READ_DEV__ep3_in_eot__ep3_in_eot__pend 1 -#define R_USB_IRQ_READ_DEV__ep2_in_eot__ep2_in_eot__no_pend 0 -#define R_USB_IRQ_READ_DEV__ep2_in_eot__ep2_in_eot__pend 1 -#define R_USB_IRQ_READ_DEV__ep1_in_eot__ep1_in_eot__no_pend 0 -#define R_USB_IRQ_READ_DEV__ep1_in_eot__ep1_in_eot__pend 1 -#define R_USB_IRQ_READ_DEV__ep0_in_eot__ep0_in_eot__no_pend 0 -#define R_USB_IRQ_READ_DEV__ep0_in_eot__ep0_in_eot__pend 1 -#define R_USB_IRQ_READ_DEV__epid_attn__epid_attn__no_pend 0 -#define R_USB_IRQ_READ_DEV__epid_attn__epid_attn__pend 1 -#define R_USB_IRQ_READ_DEV__sof__sof__no_pend 0 -#define R_USB_IRQ_READ_DEV__sof__sof__pend 1 -#define R_USB_IRQ_READ_DEV__port_status__port_status__no_pend 0 -#define R_USB_IRQ_READ_DEV__port_status__port_status__pend 1 -#define R_USB_IRQ_READ_DEV__ctl_status__ctl_status__no_pend 0 -#define R_USB_IRQ_READ_DEV__ctl_status__ctl_status__pend 1 - -#endif - -/* - * R_USB_PORT1_DISABLE - * - type: WO - * - addr: 0xb000006a - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -#define R_USB_PORT1_DISABLE__ADDR (REG_TYPECAST_BYTE 0xb000006a) - -#ifndef REG_NO_SHADOW -#define R_USB_PORT1_DISABLE__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL1_CTRL + 2)) -#define R_USB_PORT1_DISABLE__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL1_CTRL + 2)) -#else /* REG_NO_SHADOW */ -#define R_USB_PORT1_DISABLE__SADDR (REG_STYPECAST_BYTE (®_shadow__hwregs)) -#define R_USB_PORT1_DISABLE__IADDR (REG_STYPECAST_BYTE (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_USB_PORT1_DISABLE__STYPECAST REG_STYPECAST_BYTE -#define R_USB_PORT1_DISABLE__SVAL REG_SVAL_SHADOW -#define R_USB_PORT1_DISABLE__SVAL_I REG_SVAL_I_SHADOW -#define R_USB_PORT1_DISABLE__TYPECAST REG_TYPECAST_BYTE -#define R_USB_PORT1_DISABLE__TYPE (REG_BYTE) -#define R_USB_PORT1_DISABLE__GET REG_GET_WO -#define R_USB_PORT1_DISABLE__IGET REG_IGET_WO -#define R_USB_PORT1_DISABLE__SET REG_SET_WO -#define R_USB_PORT1_DISABLE__ISET REG_ISET_WO -#define R_USB_PORT1_DISABLE__SET_VAL REG_SET_VAL_WO -#define R_USB_PORT1_DISABLE__EQL REG_EQL_WO -#define R_USB_PORT1_DISABLE__IEQL REG_IEQL_WO -#define R_USB_PORT1_DISABLE__RD REG_RD_WO -#define R_USB_PORT1_DISABLE__IRD REG_IRD_WO -#define R_USB_PORT1_DISABLE__WR REG_WR_WO -#define R_USB_PORT1_DISABLE__IWR REG_IWR_WO - -#define R_USB_PORT1_DISABLE__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_USB_PORT1_DISABLE__disable__disable__MASK 0x00000001U - -#define R_USB_PORT1_DISABLE__disable__MAX 0x1 - -#define R_USB_PORT1_DISABLE__disable__MIN 0 - -#define R_USB_PORT1_DISABLE__disable__BITNR 0 - -#define R_USB_PORT1_DISABLE__disable__disable__VAL REG_VAL_ENUM - -#define R_USB_PORT1_DISABLE__disable__disable__no 1 -#define R_USB_PORT1_DISABLE__disable__disable__yes 0 - -#endif - -/* - * R_USB_PORT2_DISABLE - * - type: WO - * - addr: 0xb0000052 - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -#define R_USB_PORT2_DISABLE__ADDR (REG_TYPECAST_BYTE 0xb0000052) - -#ifndef REG_NO_SHADOW -#define R_USB_PORT2_DISABLE__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_PAR1_CTRL_DATA + 2)) -#define R_USB_PORT2_DISABLE__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_PAR1_CTRL_DATA + 2)) -#else /* REG_NO_SHADOW */ -#define R_USB_PORT2_DISABLE__SADDR (REG_STYPECAST_BYTE (®_shadow__hwregs)) -#define R_USB_PORT2_DISABLE__IADDR (REG_STYPECAST_BYTE (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_USB_PORT2_DISABLE__STYPECAST REG_STYPECAST_BYTE -#define R_USB_PORT2_DISABLE__SVAL REG_SVAL_SHADOW -#define R_USB_PORT2_DISABLE__SVAL_I REG_SVAL_I_SHADOW -#define R_USB_PORT2_DISABLE__TYPECAST REG_TYPECAST_BYTE -#define R_USB_PORT2_DISABLE__TYPE (REG_BYTE) -#define R_USB_PORT2_DISABLE__GET REG_GET_WO -#define R_USB_PORT2_DISABLE__IGET REG_IGET_WO -#define R_USB_PORT2_DISABLE__SET REG_SET_WO -#define R_USB_PORT2_DISABLE__ISET REG_ISET_WO -#define R_USB_PORT2_DISABLE__SET_VAL REG_SET_VAL_WO -#define R_USB_PORT2_DISABLE__EQL REG_EQL_WO -#define R_USB_PORT2_DISABLE__IEQL REG_IEQL_WO -#define R_USB_PORT2_DISABLE__RD REG_RD_WO -#define R_USB_PORT2_DISABLE__IRD REG_IRD_WO -#define R_USB_PORT2_DISABLE__WR REG_WR_WO -#define R_USB_PORT2_DISABLE__IWR REG_IWR_WO - -#define R_USB_PORT2_DISABLE__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_USB_PORT2_DISABLE__disable__disable__MASK 0x00000001U - -#define R_USB_PORT2_DISABLE__disable__MAX 0x1 - -#define R_USB_PORT2_DISABLE__disable__MIN 0 - -#define R_USB_PORT2_DISABLE__disable__BITNR 0 - -#define R_USB_PORT2_DISABLE__disable__disable__VAL REG_VAL_ENUM - -#define R_USB_PORT2_DISABLE__disable__disable__no 1 -#define R_USB_PORT2_DISABLE__disable__disable__yes 0 - -#endif - -/* - * R_USB_REVISION - * - type: RO - * - addr: 0xb0000200 - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -#define R_USB_REVISION__ADDR (REG_TYPECAST_BYTE 0xb0000200) -#define R_USB_REVISION__SVAL REG_SVAL_SHADOW -#define R_USB_REVISION__SVAL_I REG_SVAL_I_SHADOW -#define R_USB_REVISION__TYPECAST REG_TYPECAST_BYTE -#define R_USB_REVISION__TYPE (REG_BYTE) -#define R_USB_REVISION__GET REG_GET_RO -#define R_USB_REVISION__IGET REG_IGET_RO -#define R_USB_REVISION__SET REG_SET_RO -#define R_USB_REVISION__ISET REG_ISET_RO -#define R_USB_REVISION__SET_VAL REG_SET_VAL_RO -#define R_USB_REVISION__EQL REG_EQL_RO -#define R_USB_REVISION__IEQL REG_IEQL_RO -#define R_USB_REVISION__RD REG_RD_RO -#define R_USB_REVISION__IRD REG_IRD_RO -#define R_USB_REVISION__WR REG_WR_RO -#define R_USB_REVISION__IWR REG_IWR_RO - -#define R_USB_REVISION__READ(addr) \ - (*(addr)) - -#define R_USB_REVISION__major__major__MASK 0x000000f0U -#define R_USB_REVISION__minor__minor__MASK 0x0000000fU - -#define R_USB_REVISION__major__MAX 0xf -#define R_USB_REVISION__minor__MAX 0xf - -#define R_USB_REVISION__major__MIN 0 -#define R_USB_REVISION__minor__MIN 0 - -#define R_USB_REVISION__major__BITNR 4 -#define R_USB_REVISION__minor__BITNR 0 - -#define R_USB_REVISION__major__major__VAL REG_VAL_VAL -#define R_USB_REVISION__minor__minor__VAL REG_VAL_ENUM - -#define R_USB_REVISION__minor__minor__v1_v2 1 -#define R_USB_REVISION__minor__minor__v3 0 - -#endif - -/* - * R_USB_RH_PORT_STATUS_1 - * - type: RO - * - addr: 0xb0000218 - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -#define R_USB_RH_PORT_STATUS_1__ADDR (REG_TYPECAST_UWORD 0xb0000218) -#define R_USB_RH_PORT_STATUS_1__SVAL REG_SVAL_SHADOW -#define R_USB_RH_PORT_STATUS_1__SVAL_I REG_SVAL_I_SHADOW -#define R_USB_RH_PORT_STATUS_1__TYPECAST REG_TYPECAST_UWORD -#define R_USB_RH_PORT_STATUS_1__TYPE (REG_UWORD) -#define R_USB_RH_PORT_STATUS_1__GET REG_GET_RO -#define R_USB_RH_PORT_STATUS_1__IGET REG_IGET_RO -#define R_USB_RH_PORT_STATUS_1__SET REG_SET_RO -#define R_USB_RH_PORT_STATUS_1__ISET REG_ISET_RO -#define R_USB_RH_PORT_STATUS_1__SET_VAL REG_SET_VAL_RO -#define R_USB_RH_PORT_STATUS_1__EQL REG_EQL_RO -#define R_USB_RH_PORT_STATUS_1__IEQL REG_IEQL_RO -#define R_USB_RH_PORT_STATUS_1__RD REG_RD_RO -#define R_USB_RH_PORT_STATUS_1__IRD REG_IRD_RO -#define R_USB_RH_PORT_STATUS_1__WR REG_WR_RO -#define R_USB_RH_PORT_STATUS_1__IWR REG_IWR_RO - -#define R_USB_RH_PORT_STATUS_1__READ(addr) \ - (*(addr)) - -#define R_USB_RH_PORT_STATUS_1__speed__speed__MASK 0x00000200U -#define R_USB_RH_PORT_STATUS_1__power__power__MASK 0x00000100U -#define R_USB_RH_PORT_STATUS_1__reset__reset__MASK 0x00000010U -#define R_USB_RH_PORT_STATUS_1__overcurrent__overcurrent__MASK 0x00000008U -#define R_USB_RH_PORT_STATUS_1__suspended__suspended__MASK 0x00000004U -#define R_USB_RH_PORT_STATUS_1__enabled__enabled__MASK 0x00000002U -#define R_USB_RH_PORT_STATUS_1__connected__connected__MASK 0x00000001U - -#define R_USB_RH_PORT_STATUS_1__speed__MAX 0x1 -#define R_USB_RH_PORT_STATUS_1__power__MAX 0x1 -#define R_USB_RH_PORT_STATUS_1__reset__MAX 0x1 -#define R_USB_RH_PORT_STATUS_1__overcurrent__MAX 0x1 -#define R_USB_RH_PORT_STATUS_1__suspended__MAX 0x1 -#define R_USB_RH_PORT_STATUS_1__enabled__MAX 0x1 -#define R_USB_RH_PORT_STATUS_1__connected__MAX 0x1 - -#define R_USB_RH_PORT_STATUS_1__speed__MIN 0 -#define R_USB_RH_PORT_STATUS_1__power__MIN 0 -#define R_USB_RH_PORT_STATUS_1__reset__MIN 0 -#define R_USB_RH_PORT_STATUS_1__overcurrent__MIN 0 -#define R_USB_RH_PORT_STATUS_1__suspended__MIN 0 -#define R_USB_RH_PORT_STATUS_1__enabled__MIN 0 -#define R_USB_RH_PORT_STATUS_1__connected__MIN 0 - -#define R_USB_RH_PORT_STATUS_1__speed__BITNR 9 -#define R_USB_RH_PORT_STATUS_1__power__BITNR 8 -#define R_USB_RH_PORT_STATUS_1__reset__BITNR 4 -#define R_USB_RH_PORT_STATUS_1__overcurrent__BITNR 3 -#define R_USB_RH_PORT_STATUS_1__suspended__BITNR 2 -#define R_USB_RH_PORT_STATUS_1__enabled__BITNR 1 -#define R_USB_RH_PORT_STATUS_1__connected__BITNR 0 - -#define R_USB_RH_PORT_STATUS_1__speed__speed__VAL REG_VAL_ENUM -#define R_USB_RH_PORT_STATUS_1__power__power__VAL REG_VAL_VAL -#define R_USB_RH_PORT_STATUS_1__reset__reset__VAL REG_VAL_ENUM -#define R_USB_RH_PORT_STATUS_1__overcurrent__overcurrent__VAL REG_VAL_ENUM -#define R_USB_RH_PORT_STATUS_1__suspended__suspended__VAL REG_VAL_ENUM -#define R_USB_RH_PORT_STATUS_1__enabled__enabled__VAL REG_VAL_ENUM -#define R_USB_RH_PORT_STATUS_1__connected__connected__VAL REG_VAL_ENUM - -#define R_USB_RH_PORT_STATUS_1__speed__speed__full 0 -#define R_USB_RH_PORT_STATUS_1__speed__speed__low 1 -#define R_USB_RH_PORT_STATUS_1__reset__reset__no 0 -#define R_USB_RH_PORT_STATUS_1__reset__reset__yes 1 -#define R_USB_RH_PORT_STATUS_1__overcurrent__overcurrent__no 0 -#define R_USB_RH_PORT_STATUS_1__overcurrent__overcurrent__yes 1 -#define R_USB_RH_PORT_STATUS_1__suspended__suspended__no 0 -#define R_USB_RH_PORT_STATUS_1__suspended__suspended__yes 1 -#define R_USB_RH_PORT_STATUS_1__enabled__enabled__no 0 -#define R_USB_RH_PORT_STATUS_1__enabled__enabled__yes 1 -#define R_USB_RH_PORT_STATUS_1__connected__connected__no 0 -#define R_USB_RH_PORT_STATUS_1__connected__connected__yes 1 - -#endif - -/* - * R_USB_RH_PORT_STATUS_2 - * - type: RO - * - addr: 0xb000021a - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -#define R_USB_RH_PORT_STATUS_2__ADDR (REG_TYPECAST_UWORD 0xb000021a) -#define R_USB_RH_PORT_STATUS_2__SVAL REG_SVAL_SHADOW -#define R_USB_RH_PORT_STATUS_2__SVAL_I REG_SVAL_I_SHADOW -#define R_USB_RH_PORT_STATUS_2__TYPECAST REG_TYPECAST_UWORD -#define R_USB_RH_PORT_STATUS_2__TYPE (REG_UWORD) -#define R_USB_RH_PORT_STATUS_2__GET REG_GET_RO -#define R_USB_RH_PORT_STATUS_2__IGET REG_IGET_RO -#define R_USB_RH_PORT_STATUS_2__SET REG_SET_RO -#define R_USB_RH_PORT_STATUS_2__ISET REG_ISET_RO -#define R_USB_RH_PORT_STATUS_2__SET_VAL REG_SET_VAL_RO -#define R_USB_RH_PORT_STATUS_2__EQL REG_EQL_RO -#define R_USB_RH_PORT_STATUS_2__IEQL REG_IEQL_RO -#define R_USB_RH_PORT_STATUS_2__RD REG_RD_RO -#define R_USB_RH_PORT_STATUS_2__IRD REG_IRD_RO -#define R_USB_RH_PORT_STATUS_2__WR REG_WR_RO -#define R_USB_RH_PORT_STATUS_2__IWR REG_IWR_RO - -#define R_USB_RH_PORT_STATUS_2__READ(addr) \ - (*(addr)) - -#define R_USB_RH_PORT_STATUS_2__speed__speed__MASK 0x00000200U -#define R_USB_RH_PORT_STATUS_2__power__power__MASK 0x00000100U -#define R_USB_RH_PORT_STATUS_2__reset__reset__MASK 0x00000010U -#define R_USB_RH_PORT_STATUS_2__overcurrent__overcurrent__MASK 0x00000008U -#define R_USB_RH_PORT_STATUS_2__suspended__suspended__MASK 0x00000004U -#define R_USB_RH_PORT_STATUS_2__enabled__enabled__MASK 0x00000002U -#define R_USB_RH_PORT_STATUS_2__connected__connected__MASK 0x00000001U - -#define R_USB_RH_PORT_STATUS_2__speed__MAX 0x1 -#define R_USB_RH_PORT_STATUS_2__power__MAX 0x1 -#define R_USB_RH_PORT_STATUS_2__reset__MAX 0x1 -#define R_USB_RH_PORT_STATUS_2__overcurrent__MAX 0x1 -#define R_USB_RH_PORT_STATUS_2__suspended__MAX 0x1 -#define R_USB_RH_PORT_STATUS_2__enabled__MAX 0x1 -#define R_USB_RH_PORT_STATUS_2__connected__MAX 0x1 - -#define R_USB_RH_PORT_STATUS_2__speed__MIN 0 -#define R_USB_RH_PORT_STATUS_2__power__MIN 0 -#define R_USB_RH_PORT_STATUS_2__reset__MIN 0 -#define R_USB_RH_PORT_STATUS_2__overcurrent__MIN 0 -#define R_USB_RH_PORT_STATUS_2__suspended__MIN 0 -#define R_USB_RH_PORT_STATUS_2__enabled__MIN 0 -#define R_USB_RH_PORT_STATUS_2__connected__MIN 0 - -#define R_USB_RH_PORT_STATUS_2__speed__BITNR 9 -#define R_USB_RH_PORT_STATUS_2__power__BITNR 8 -#define R_USB_RH_PORT_STATUS_2__reset__BITNR 4 -#define R_USB_RH_PORT_STATUS_2__overcurrent__BITNR 3 -#define R_USB_RH_PORT_STATUS_2__suspended__BITNR 2 -#define R_USB_RH_PORT_STATUS_2__enabled__BITNR 1 -#define R_USB_RH_PORT_STATUS_2__connected__BITNR 0 - -#define R_USB_RH_PORT_STATUS_2__speed__speed__VAL REG_VAL_ENUM -#define R_USB_RH_PORT_STATUS_2__power__power__VAL REG_VAL_VAL -#define R_USB_RH_PORT_STATUS_2__reset__reset__VAL REG_VAL_ENUM -#define R_USB_RH_PORT_STATUS_2__overcurrent__overcurrent__VAL REG_VAL_ENUM -#define R_USB_RH_PORT_STATUS_2__suspended__suspended__VAL REG_VAL_ENUM -#define R_USB_RH_PORT_STATUS_2__enabled__enabled__VAL REG_VAL_ENUM -#define R_USB_RH_PORT_STATUS_2__connected__connected__VAL REG_VAL_ENUM - -#define R_USB_RH_PORT_STATUS_2__speed__speed__full 0 -#define R_USB_RH_PORT_STATUS_2__speed__speed__low 1 -#define R_USB_RH_PORT_STATUS_2__reset__reset__no 0 -#define R_USB_RH_PORT_STATUS_2__reset__reset__yes 1 -#define R_USB_RH_PORT_STATUS_2__overcurrent__overcurrent__no 0 -#define R_USB_RH_PORT_STATUS_2__overcurrent__overcurrent__yes 1 -#define R_USB_RH_PORT_STATUS_2__suspended__suspended__no 0 -#define R_USB_RH_PORT_STATUS_2__suspended__suspended__yes 1 -#define R_USB_RH_PORT_STATUS_2__enabled__enabled__no 0 -#define R_USB_RH_PORT_STATUS_2__enabled__enabled__yes 1 -#define R_USB_RH_PORT_STATUS_2__connected__connected__no 0 -#define R_USB_RH_PORT_STATUS_2__connected__connected__yes 1 - -#endif - -/* - * R_USB_RH_STATUS - * - type: RO - * - addr: 0xb0000203 - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -#define R_USB_RH_STATUS__ADDR (REG_TYPECAST_BYTE 0xb0000203) -#define R_USB_RH_STATUS__SVAL REG_SVAL_SHADOW -#define R_USB_RH_STATUS__SVAL_I REG_SVAL_I_SHADOW -#define R_USB_RH_STATUS__TYPECAST REG_TYPECAST_BYTE -#define R_USB_RH_STATUS__TYPE (REG_BYTE) -#define R_USB_RH_STATUS__GET REG_GET_RO -#define R_USB_RH_STATUS__IGET REG_IGET_RO -#define R_USB_RH_STATUS__SET REG_SET_RO -#define R_USB_RH_STATUS__ISET REG_ISET_RO -#define R_USB_RH_STATUS__SET_VAL REG_SET_VAL_RO -#define R_USB_RH_STATUS__EQL REG_EQL_RO -#define R_USB_RH_STATUS__IEQL REG_IEQL_RO -#define R_USB_RH_STATUS__RD REG_RD_RO -#define R_USB_RH_STATUS__IRD REG_IRD_RO -#define R_USB_RH_STATUS__WR REG_WR_RO -#define R_USB_RH_STATUS__IWR REG_IWR_RO - -#define R_USB_RH_STATUS__READ(addr) \ - (*(addr)) - -#define R_USB_RH_STATUS__babble2__babble2__MASK 0x00000080U -#define R_USB_RH_STATUS__babble1__babble1__MASK 0x00000040U -#define R_USB_RH_STATUS__bus1__bus1__MASK 0x00000030U -#define R_USB_RH_STATUS__bus2__bus2__MASK 0x0000000cU -#define R_USB_RH_STATUS__nports__nports__MASK 0x00000003U - -#define R_USB_RH_STATUS__babble2__MAX 0x1 -#define R_USB_RH_STATUS__babble1__MAX 0x1 -#define R_USB_RH_STATUS__bus1__MAX 0x3 -#define R_USB_RH_STATUS__bus2__MAX 0x3 -#define R_USB_RH_STATUS__nports__MAX 3 - -#define R_USB_RH_STATUS__babble2__MIN 0 -#define R_USB_RH_STATUS__babble1__MIN 0 -#define R_USB_RH_STATUS__bus1__MIN 0 -#define R_USB_RH_STATUS__bus2__MIN 0 -#define R_USB_RH_STATUS__nports__MIN 0 - -#define R_USB_RH_STATUS__babble2__BITNR 7 -#define R_USB_RH_STATUS__babble1__BITNR 6 -#define R_USB_RH_STATUS__bus1__BITNR 4 -#define R_USB_RH_STATUS__bus2__BITNR 2 -#define R_USB_RH_STATUS__nports__BITNR 0 - -#define R_USB_RH_STATUS__babble2__babble2__VAL REG_VAL_ENUM -#define R_USB_RH_STATUS__babble1__babble1__VAL REG_VAL_ENUM -#define R_USB_RH_STATUS__bus1__bus1__VAL REG_VAL_ENUM -#define R_USB_RH_STATUS__bus2__bus2__VAL REG_VAL_ENUM -#define R_USB_RH_STATUS__nports__nports__VAL REG_VAL_VAL - -#define R_USB_RH_STATUS__babble2__babble2__no 0 -#define R_USB_RH_STATUS__babble2__babble2__yes 1 -#define R_USB_RH_STATUS__babble1__babble1__no 0 -#define R_USB_RH_STATUS__babble1__babble1__yes 1 -#define R_USB_RH_STATUS__bus1__bus1__Diff0 1 -#define R_USB_RH_STATUS__bus1__bus1__Diff1 2 -#define R_USB_RH_STATUS__bus1__bus1__SE0 0 -#define R_USB_RH_STATUS__bus1__bus1__SE1 3 -#define R_USB_RH_STATUS__bus2__bus2__Diff0 1 -#define R_USB_RH_STATUS__bus2__bus2__Diff1 2 -#define R_USB_RH_STATUS__bus2__bus2__SE0 0 -#define R_USB_RH_STATUS__bus2__bus2__SE1 3 - -#endif - -/* - * R_USB_SNMP_TERROR - * - type: RW - * - addr: 0xb0000220 - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -#define R_USB_SNMP_TERROR__ADDR (REG_TYPECAST_UDWORD 0xb0000220) -#define R_USB_SNMP_TERROR__SVAL REG_SVAL_SHADOW -#define R_USB_SNMP_TERROR__SVAL_I REG_SVAL_I_SHADOW -#define R_USB_SNMP_TERROR__TYPECAST REG_TYPECAST_UDWORD -#define R_USB_SNMP_TERROR__TYPE (REG_UDWORD) -#define R_USB_SNMP_TERROR__GET REG_GET_RW -#define R_USB_SNMP_TERROR__IGET REG_IGET_RW -#define R_USB_SNMP_TERROR__SET REG_SET_RW -#define R_USB_SNMP_TERROR__ISET REG_ISET_RW -#define R_USB_SNMP_TERROR__SET_VAL REG_SET_VAL_RW -#define R_USB_SNMP_TERROR__EQL REG_EQL_RW -#define R_USB_SNMP_TERROR__IEQL REG_IEQL_RW -#define R_USB_SNMP_TERROR__RD REG_RD_RW -#define R_USB_SNMP_TERROR__IRD REG_IRD_RW -#define R_USB_SNMP_TERROR__WR REG_WR_RW -#define R_USB_SNMP_TERROR__IWR REG_IWR_RW - -#define R_USB_SNMP_TERROR__WRITE(addr,value) \ - (*(addr) = (value)) -#define R_USB_SNMP_TERROR__READ(addr) \ - (*(addr)) - -#define R_USB_SNMP_TERROR__value__value__MASK 0xffffffffU - -#define R_USB_SNMP_TERROR__value__MAX 0xffffffff - -#define R_USB_SNMP_TERROR__value__MIN 0 - -#define R_USB_SNMP_TERROR__value__BITNR 0 - -#define R_USB_SNMP_TERROR__value__value__VAL REG_VAL_VAL - - -#endif - -/* - * R_USB_STATUS - * - type: RO - * - addr: 0xb0000202 - * - group: USB interface control registers - */ - -#if USE_GROUP__USB_interface_control_registers - -#define R_USB_STATUS__ADDR (REG_TYPECAST_BYTE 0xb0000202) -#define R_USB_STATUS__SVAL REG_SVAL_SHADOW -#define R_USB_STATUS__SVAL_I REG_SVAL_I_SHADOW -#define R_USB_STATUS__TYPECAST REG_TYPECAST_BYTE -#define R_USB_STATUS__TYPE (REG_BYTE) -#define R_USB_STATUS__GET REG_GET_RO -#define R_USB_STATUS__IGET REG_IGET_RO -#define R_USB_STATUS__SET REG_SET_RO -#define R_USB_STATUS__ISET REG_ISET_RO -#define R_USB_STATUS__SET_VAL REG_SET_VAL_RO -#define R_USB_STATUS__EQL REG_EQL_RO -#define R_USB_STATUS__IEQL REG_IEQL_RO -#define R_USB_STATUS__RD REG_RD_RO -#define R_USB_STATUS__IRD REG_IRD_RO -#define R_USB_STATUS__WR REG_WR_RO -#define R_USB_STATUS__IWR REG_IWR_RO - -#define R_USB_STATUS__READ(addr) \ - (*(addr)) - -#define R_USB_STATUS__ourun__ourun__MASK 0x00000020U -#define R_USB_STATUS__perror__perror__MASK 0x00000010U -#define R_USB_STATUS__device_mode__device_mode__MASK 0x00000008U -#define R_USB_STATUS__host_mode__host_mode__MASK 0x00000004U -#define R_USB_STATUS__started__started__MASK 0x00000002U -#define R_USB_STATUS__running__running__MASK 0x00000001U - -#define R_USB_STATUS__ourun__MAX 0x1 -#define R_USB_STATUS__perror__MAX 0x1 -#define R_USB_STATUS__device_mode__MAX 0x1 -#define R_USB_STATUS__host_mode__MAX 0x1 -#define R_USB_STATUS__started__MAX 0x1 -#define R_USB_STATUS__running__MAX 0x1 - -#define R_USB_STATUS__ourun__MIN 0 -#define R_USB_STATUS__perror__MIN 0 -#define R_USB_STATUS__device_mode__MIN 0 -#define R_USB_STATUS__host_mode__MIN 0 -#define R_USB_STATUS__started__MIN 0 -#define R_USB_STATUS__running__MIN 0 - -#define R_USB_STATUS__ourun__BITNR 5 -#define R_USB_STATUS__perror__BITNR 4 -#define R_USB_STATUS__device_mode__BITNR 3 -#define R_USB_STATUS__host_mode__BITNR 2 -#define R_USB_STATUS__started__BITNR 1 -#define R_USB_STATUS__running__BITNR 0 - -#define R_USB_STATUS__ourun__ourun__VAL REG_VAL_ENUM -#define R_USB_STATUS__perror__perror__VAL REG_VAL_ENUM -#define R_USB_STATUS__device_mode__device_mode__VAL REG_VAL_ENUM -#define R_USB_STATUS__host_mode__host_mode__VAL REG_VAL_ENUM -#define R_USB_STATUS__started__started__VAL REG_VAL_ENUM -#define R_USB_STATUS__running__running__VAL REG_VAL_ENUM - -#define R_USB_STATUS__ourun__ourun__no 0 -#define R_USB_STATUS__ourun__ourun__yes 1 -#define R_USB_STATUS__perror__perror__no 0 -#define R_USB_STATUS__perror__perror__yes 1 -#define R_USB_STATUS__device_mode__device_mode__no 0 -#define R_USB_STATUS__device_mode__device_mode__yes 1 -#define R_USB_STATUS__host_mode__host_mode__no 0 -#define R_USB_STATUS__host_mode__host_mode__yes 1 -#define R_USB_STATUS__started__started__no 0 -#define R_USB_STATUS__started__started__yes 1 -#define R_USB_STATUS__running__running__no 0 -#define R_USB_STATUS__running__running__yes 1 - -#endif - -/* - * R_VECT_MASK_CLR - * - type: WO - * - addr: 0xb00000d8 - * - group: Interrupt mask and status registers - */ - -#if USE_GROUP__Interrupt_mask_and_status_registers - -#define R_VECT_MASK_CLR__ADDR (REG_TYPECAST_UDWORD 0xb00000d8) - -#ifndef REG_NO_SHADOW -#define R_VECT_MASK_CLR__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_VECT_MASK_CLR + 0)) -#define R_VECT_MASK_CLR__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_VECT_MASK_CLR + 0)) -#else /* REG_NO_SHADOW */ -#define R_VECT_MASK_CLR__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_VECT_MASK_CLR__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_VECT_MASK_CLR__STYPECAST REG_STYPECAST_UDWORD -#define R_VECT_MASK_CLR__SVAL REG_SVAL_ZERO -#define R_VECT_MASK_CLR__SVAL_I REG_SVAL_I_ZERO -#define R_VECT_MASK_CLR__TYPECAST REG_TYPECAST_UDWORD -#define R_VECT_MASK_CLR__TYPE (REG_UDWORD) -#define R_VECT_MASK_CLR__GET REG_GET_WO -#define R_VECT_MASK_CLR__IGET REG_IGET_WO -#define R_VECT_MASK_CLR__SET REG_SET_WO -#define R_VECT_MASK_CLR__ISET REG_ISET_WO -#define R_VECT_MASK_CLR__SET_VAL REG_SET_VAL_WO -#define R_VECT_MASK_CLR__EQL REG_EQL_WO -#define R_VECT_MASK_CLR__IEQL REG_IEQL_WO -#define R_VECT_MASK_CLR__RD REG_RD_WO -#define R_VECT_MASK_CLR__IRD REG_IRD_WO -#define R_VECT_MASK_CLR__WR REG_WR_WO -#define R_VECT_MASK_CLR__IWR REG_IWR_WO - -#define R_VECT_MASK_CLR__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_VECT_MASK_CLR__usb__usb__MASK 0x80000000U -#define R_VECT_MASK_CLR__dma9__dma9__MASK 0x02000000U -#define R_VECT_MASK_CLR__dma8__dma8__MASK 0x01000000U -#define R_VECT_MASK_CLR__dma7__dma7__MASK 0x00800000U -#define R_VECT_MASK_CLR__dma6__dma6__MASK 0x00400000U -#define R_VECT_MASK_CLR__dma5__dma5__MASK 0x00200000U -#define R_VECT_MASK_CLR__dma4__dma4__MASK 0x00100000U -#define R_VECT_MASK_CLR__dma3__dma3__MASK 0x00080000U -#define R_VECT_MASK_CLR__dma2__dma2__MASK 0x00040000U -#define R_VECT_MASK_CLR__dma1__dma1__MASK 0x00020000U -#define R_VECT_MASK_CLR__dma0__dma0__MASK 0x00010000U -#define R_VECT_MASK_CLR__ext_dma1__ext_dma1__MASK 0x00002000U -#define R_VECT_MASK_CLR__ext_dma0__ext_dma0__MASK 0x00001000U -#define R_VECT_MASK_CLR__pa__pa__MASK 0x00000800U -#define R_VECT_MASK_CLR__irq_intnr__irq_intnr__MASK 0x00000400U -#define R_VECT_MASK_CLR__sw__sw__MASK 0x00000200U -#define R_VECT_MASK_CLR__serial__serial__MASK 0x00000100U -#define R_VECT_MASK_CLR__snmp__snmp__MASK 0x00000080U -#define R_VECT_MASK_CLR__network__network__MASK 0x00000040U -#define R_VECT_MASK_CLR__scsi1__scsi1__MASK 0x00000020U -#define R_VECT_MASK_CLR__par1__par1__MASK 0x00000020U -#define R_VECT_MASK_CLR__scsi1__par1__MASK 0x00000020U -#define R_VECT_MASK_CLR__scsi0__scsi0__MASK 0x00000010U -#define R_VECT_MASK_CLR__par0__par0__MASK 0x00000010U -#define R_VECT_MASK_CLR__scsi0__par0__MASK 0x00000010U -#define R_VECT_MASK_CLR__ata__ata__MASK 0x00000010U -#define R_VECT_MASK_CLR__scsi0__ata__MASK 0x00000010U -#define R_VECT_MASK_CLR__mio__mio__MASK 0x00000010U -#define R_VECT_MASK_CLR__scsi0__mio__MASK 0x00000010U -#define R_VECT_MASK_CLR__timer1__timer1__MASK 0x00000008U -#define R_VECT_MASK_CLR__timer0__timer0__MASK 0x00000004U -#define R_VECT_MASK_CLR__nmi__nmi__MASK 0x00000002U -#define R_VECT_MASK_CLR__some__some__MASK 0x00000001U - -#define R_VECT_MASK_CLR__usb__MAX 0x1 -#define R_VECT_MASK_CLR__dma9__MAX 0x1 -#define R_VECT_MASK_CLR__dma8__MAX 0x1 -#define R_VECT_MASK_CLR__dma7__MAX 0x1 -#define R_VECT_MASK_CLR__dma6__MAX 0x1 -#define R_VECT_MASK_CLR__dma5__MAX 0x1 -#define R_VECT_MASK_CLR__dma4__MAX 0x1 -#define R_VECT_MASK_CLR__dma3__MAX 0x1 -#define R_VECT_MASK_CLR__dma2__MAX 0x1 -#define R_VECT_MASK_CLR__dma1__MAX 0x1 -#define R_VECT_MASK_CLR__dma0__MAX 0x1 -#define R_VECT_MASK_CLR__ext_dma1__MAX 0x1 -#define R_VECT_MASK_CLR__ext_dma0__MAX 0x1 -#define R_VECT_MASK_CLR__pa__MAX 0x1 -#define R_VECT_MASK_CLR__irq_intnr__MAX 0x1 -#define R_VECT_MASK_CLR__sw__MAX 0x1 -#define R_VECT_MASK_CLR__serial__MAX 0x1 -#define R_VECT_MASK_CLR__snmp__MAX 0x1 -#define R_VECT_MASK_CLR__network__MAX 0x1 -#define R_VECT_MASK_CLR__scsi1__MAX 0x1 -#define R_VECT_MASK_CLR__par1__MAX 0x1 -#define R_VECT_MASK_CLR__scsi0__MAX 0x1 -#define R_VECT_MASK_CLR__par0__MAX 0x1 -#define R_VECT_MASK_CLR__ata__MAX 0x1 -#define R_VECT_MASK_CLR__mio__MAX 0x1 -#define R_VECT_MASK_CLR__timer1__MAX 0x1 -#define R_VECT_MASK_CLR__timer0__MAX 0x1 -#define R_VECT_MASK_CLR__nmi__MAX 0x1 -#define R_VECT_MASK_CLR__some__MAX 0x1 - -#define R_VECT_MASK_CLR__usb__MIN 0 -#define R_VECT_MASK_CLR__dma9__MIN 0 -#define R_VECT_MASK_CLR__dma8__MIN 0 -#define R_VECT_MASK_CLR__dma7__MIN 0 -#define R_VECT_MASK_CLR__dma6__MIN 0 -#define R_VECT_MASK_CLR__dma5__MIN 0 -#define R_VECT_MASK_CLR__dma4__MIN 0 -#define R_VECT_MASK_CLR__dma3__MIN 0 -#define R_VECT_MASK_CLR__dma2__MIN 0 -#define R_VECT_MASK_CLR__dma1__MIN 0 -#define R_VECT_MASK_CLR__dma0__MIN 0 -#define R_VECT_MASK_CLR__ext_dma1__MIN 0 -#define R_VECT_MASK_CLR__ext_dma0__MIN 0 -#define R_VECT_MASK_CLR__pa__MIN 0 -#define R_VECT_MASK_CLR__irq_intnr__MIN 0 -#define R_VECT_MASK_CLR__sw__MIN 0 -#define R_VECT_MASK_CLR__serial__MIN 0 -#define R_VECT_MASK_CLR__snmp__MIN 0 -#define R_VECT_MASK_CLR__network__MIN 0 -#define R_VECT_MASK_CLR__scsi1__MIN 0 -#define R_VECT_MASK_CLR__par1__MIN 0 -#define R_VECT_MASK_CLR__scsi0__MIN 0 -#define R_VECT_MASK_CLR__par0__MIN 0 -#define R_VECT_MASK_CLR__ata__MIN 0 -#define R_VECT_MASK_CLR__mio__MIN 0 -#define R_VECT_MASK_CLR__timer1__MIN 0 -#define R_VECT_MASK_CLR__timer0__MIN 0 -#define R_VECT_MASK_CLR__nmi__MIN 0 -#define R_VECT_MASK_CLR__some__MIN 0 - -#define R_VECT_MASK_CLR__usb__BITNR 31 -#define R_VECT_MASK_CLR__dma9__BITNR 25 -#define R_VECT_MASK_CLR__dma8__BITNR 24 -#define R_VECT_MASK_CLR__dma7__BITNR 23 -#define R_VECT_MASK_CLR__dma6__BITNR 22 -#define R_VECT_MASK_CLR__dma5__BITNR 21 -#define R_VECT_MASK_CLR__dma4__BITNR 20 -#define R_VECT_MASK_CLR__dma3__BITNR 19 -#define R_VECT_MASK_CLR__dma2__BITNR 18 -#define R_VECT_MASK_CLR__dma1__BITNR 17 -#define R_VECT_MASK_CLR__dma0__BITNR 16 -#define R_VECT_MASK_CLR__ext_dma1__BITNR 13 -#define R_VECT_MASK_CLR__ext_dma0__BITNR 12 -#define R_VECT_MASK_CLR__pa__BITNR 11 -#define R_VECT_MASK_CLR__irq_intnr__BITNR 10 -#define R_VECT_MASK_CLR__sw__BITNR 9 -#define R_VECT_MASK_CLR__serial__BITNR 8 -#define R_VECT_MASK_CLR__snmp__BITNR 7 -#define R_VECT_MASK_CLR__network__BITNR 6 -#define R_VECT_MASK_CLR__scsi1__BITNR 5 -#define R_VECT_MASK_CLR__par1__BITNR 5 -#define R_VECT_MASK_CLR__scsi0__BITNR 4 -#define R_VECT_MASK_CLR__par0__BITNR 4 -#define R_VECT_MASK_CLR__ata__BITNR 4 -#define R_VECT_MASK_CLR__mio__BITNR 4 -#define R_VECT_MASK_CLR__timer1__BITNR 3 -#define R_VECT_MASK_CLR__timer0__BITNR 2 -#define R_VECT_MASK_CLR__nmi__BITNR 1 -#define R_VECT_MASK_CLR__some__BITNR 0 - -#define R_VECT_MASK_CLR__usb__usb__VAL REG_VAL_ENUM -#define R_VECT_MASK_CLR__dma9__dma9__VAL REG_VAL_ENUM -#define R_VECT_MASK_CLR__dma8__dma8__VAL REG_VAL_ENUM -#define R_VECT_MASK_CLR__dma7__dma7__VAL REG_VAL_ENUM -#define R_VECT_MASK_CLR__dma6__dma6__VAL REG_VAL_ENUM -#define R_VECT_MASK_CLR__dma5__dma5__VAL REG_VAL_ENUM -#define R_VECT_MASK_CLR__dma4__dma4__VAL REG_VAL_ENUM -#define R_VECT_MASK_CLR__dma3__dma3__VAL REG_VAL_ENUM -#define R_VECT_MASK_CLR__dma2__dma2__VAL REG_VAL_ENUM -#define R_VECT_MASK_CLR__dma1__dma1__VAL REG_VAL_ENUM -#define R_VECT_MASK_CLR__dma0__dma0__VAL REG_VAL_ENUM -#define R_VECT_MASK_CLR__ext_dma1__ext_dma1__VAL REG_VAL_ENUM -#define R_VECT_MASK_CLR__ext_dma0__ext_dma0__VAL REG_VAL_ENUM -#define R_VECT_MASK_CLR__pa__pa__VAL REG_VAL_ENUM -#define R_VECT_MASK_CLR__irq_intnr__irq_intnr__VAL REG_VAL_ENUM -#define R_VECT_MASK_CLR__sw__sw__VAL REG_VAL_ENUM -#define R_VECT_MASK_CLR__serial__serial__VAL REG_VAL_ENUM -#define R_VECT_MASK_CLR__snmp__snmp__VAL REG_VAL_ENUM -#define R_VECT_MASK_CLR__network__network__VAL REG_VAL_ENUM -#define R_VECT_MASK_CLR__scsi1__scsi1__VAL REG_VAL_ENUM -#define R_VECT_MASK_CLR__par1__par1__VAL REG_VAL_ENUM -#define R_VECT_MASK_CLR__scsi1__par1__VAL REG_VAL_ENUM -#define R_VECT_MASK_CLR__scsi0__scsi0__VAL REG_VAL_ENUM -#define R_VECT_MASK_CLR__par0__par0__VAL REG_VAL_ENUM -#define R_VECT_MASK_CLR__scsi0__par0__VAL REG_VAL_ENUM -#define R_VECT_MASK_CLR__ata__ata__VAL REG_VAL_ENUM -#define R_VECT_MASK_CLR__scsi0__ata__VAL REG_VAL_ENUM -#define R_VECT_MASK_CLR__mio__mio__VAL REG_VAL_ENUM -#define R_VECT_MASK_CLR__scsi0__mio__VAL REG_VAL_ENUM -#define R_VECT_MASK_CLR__timer1__timer1__VAL REG_VAL_ENUM -#define R_VECT_MASK_CLR__timer0__timer0__VAL REG_VAL_ENUM -#define R_VECT_MASK_CLR__nmi__nmi__VAL REG_VAL_ENUM -#define R_VECT_MASK_CLR__some__some__VAL REG_VAL_ENUM - -#define R_VECT_MASK_CLR__usb__usb__clr 1 -#define R_VECT_MASK_CLR__usb__usb__nop 0 -#define R_VECT_MASK_CLR__dma9__dma9__clr 1 -#define R_VECT_MASK_CLR__dma9__dma9__nop 0 -#define R_VECT_MASK_CLR__dma8__dma8__clr 1 -#define R_VECT_MASK_CLR__dma8__dma8__nop 0 -#define R_VECT_MASK_CLR__dma7__dma7__clr 1 -#define R_VECT_MASK_CLR__dma7__dma7__nop 0 -#define R_VECT_MASK_CLR__dma6__dma6__clr 1 -#define R_VECT_MASK_CLR__dma6__dma6__nop 0 -#define R_VECT_MASK_CLR__dma5__dma5__clr 1 -#define R_VECT_MASK_CLR__dma5__dma5__nop 0 -#define R_VECT_MASK_CLR__dma4__dma4__clr 1 -#define R_VECT_MASK_CLR__dma4__dma4__nop 0 -#define R_VECT_MASK_CLR__dma3__dma3__clr 1 -#define R_VECT_MASK_CLR__dma3__dma3__nop 0 -#define R_VECT_MASK_CLR__dma2__dma2__clr 1 -#define R_VECT_MASK_CLR__dma2__dma2__nop 0 -#define R_VECT_MASK_CLR__dma1__dma1__clr 1 -#define R_VECT_MASK_CLR__dma1__dma1__nop 0 -#define R_VECT_MASK_CLR__dma0__dma0__clr 1 -#define R_VECT_MASK_CLR__dma0__dma0__nop 0 -#define R_VECT_MASK_CLR__ext_dma1__ext_dma1__clr 1 -#define R_VECT_MASK_CLR__ext_dma1__ext_dma1__nop 0 -#define R_VECT_MASK_CLR__ext_dma0__ext_dma0__clr 1 -#define R_VECT_MASK_CLR__ext_dma0__ext_dma0__nop 0 -#define R_VECT_MASK_CLR__pa__pa__clr 1 -#define R_VECT_MASK_CLR__pa__pa__nop 0 -#define R_VECT_MASK_CLR__irq_intnr__irq_intnr__clr 1 -#define R_VECT_MASK_CLR__irq_intnr__irq_intnr__nop 0 -#define R_VECT_MASK_CLR__sw__sw__clr 1 -#define R_VECT_MASK_CLR__sw__sw__nop 0 -#define R_VECT_MASK_CLR__serial__serial__clr 1 -#define R_VECT_MASK_CLR__serial__serial__nop 0 -#define R_VECT_MASK_CLR__snmp__snmp__clr 1 -#define R_VECT_MASK_CLR__snmp__snmp__nop 0 -#define R_VECT_MASK_CLR__network__network__clr 1 -#define R_VECT_MASK_CLR__network__network__nop 0 -#define R_VECT_MASK_CLR__scsi1__scsi1__clr 1 -#define R_VECT_MASK_CLR__scsi1__scsi1__nop 0 -#define R_VECT_MASK_CLR__par1__par1__clr 1 -#define R_VECT_MASK_CLR__par1__par1__nop 0 -#define R_VECT_MASK_CLR__scsi0__scsi0__clr 1 -#define R_VECT_MASK_CLR__scsi0__scsi0__nop 0 -#define R_VECT_MASK_CLR__par0__par0__clr 1 -#define R_VECT_MASK_CLR__par0__par0__nop 0 -#define R_VECT_MASK_CLR__ata__ata__clr 1 -#define R_VECT_MASK_CLR__ata__ata__nop 0 -#define R_VECT_MASK_CLR__mio__mio__clr 1 -#define R_VECT_MASK_CLR__mio__mio__nop 0 -#define R_VECT_MASK_CLR__timer1__timer1__clr 1 -#define R_VECT_MASK_CLR__timer1__timer1__nop 0 -#define R_VECT_MASK_CLR__timer0__timer0__clr 1 -#define R_VECT_MASK_CLR__timer0__timer0__nop 0 -#define R_VECT_MASK_CLR__nmi__nmi__clr 1 -#define R_VECT_MASK_CLR__nmi__nmi__nop 0 -#define R_VECT_MASK_CLR__some__some__clr 1 -#define R_VECT_MASK_CLR__some__some__nop 0 - -#endif - -/* - * R_VECT_MASK_RD - * - type: RO - * - addr: 0xb00000d8 - * - group: Interrupt mask and status registers - */ - -#if USE_GROUP__Interrupt_mask_and_status_registers - -#define R_VECT_MASK_RD__ADDR (REG_TYPECAST_UDWORD 0xb00000d8) -#define R_VECT_MASK_RD__SVAL REG_SVAL_SHADOW -#define R_VECT_MASK_RD__SVAL_I REG_SVAL_I_SHADOW -#define R_VECT_MASK_RD__TYPECAST REG_TYPECAST_UDWORD -#define R_VECT_MASK_RD__TYPE (REG_UDWORD) -#define R_VECT_MASK_RD__GET REG_GET_RO -#define R_VECT_MASK_RD__IGET REG_IGET_RO -#define R_VECT_MASK_RD__SET REG_SET_RO -#define R_VECT_MASK_RD__ISET REG_ISET_RO -#define R_VECT_MASK_RD__SET_VAL REG_SET_VAL_RO -#define R_VECT_MASK_RD__EQL REG_EQL_RO -#define R_VECT_MASK_RD__IEQL REG_IEQL_RO -#define R_VECT_MASK_RD__RD REG_RD_RO -#define R_VECT_MASK_RD__IRD REG_IRD_RO -#define R_VECT_MASK_RD__WR REG_WR_RO -#define R_VECT_MASK_RD__IWR REG_IWR_RO - -#define R_VECT_MASK_RD__READ(addr) \ - (*(addr)) - -#define R_VECT_MASK_RD__usb__usb__MASK 0x80000000U -#define R_VECT_MASK_RD__dma9__dma9__MASK 0x02000000U -#define R_VECT_MASK_RD__dma8__dma8__MASK 0x01000000U -#define R_VECT_MASK_RD__dma7__dma7__MASK 0x00800000U -#define R_VECT_MASK_RD__dma6__dma6__MASK 0x00400000U -#define R_VECT_MASK_RD__dma5__dma5__MASK 0x00200000U -#define R_VECT_MASK_RD__dma4__dma4__MASK 0x00100000U -#define R_VECT_MASK_RD__dma3__dma3__MASK 0x00080000U -#define R_VECT_MASK_RD__dma2__dma2__MASK 0x00040000U -#define R_VECT_MASK_RD__dma1__dma1__MASK 0x00020000U -#define R_VECT_MASK_RD__dma0__dma0__MASK 0x00010000U -#define R_VECT_MASK_RD__ext_dma1__ext_dma1__MASK 0x00002000U -#define R_VECT_MASK_RD__ext_dma0__ext_dma0__MASK 0x00001000U -#define R_VECT_MASK_RD__pa__pa__MASK 0x00000800U -#define R_VECT_MASK_RD__irq_intnr__irq_intnr__MASK 0x00000400U -#define R_VECT_MASK_RD__sw__sw__MASK 0x00000200U -#define R_VECT_MASK_RD__serial__serial__MASK 0x00000100U -#define R_VECT_MASK_RD__snmp__snmp__MASK 0x00000080U -#define R_VECT_MASK_RD__network__network__MASK 0x00000040U -#define R_VECT_MASK_RD__scsi1__scsi1__MASK 0x00000020U -#define R_VECT_MASK_RD__par1__par1__MASK 0x00000020U -#define R_VECT_MASK_RD__scsi1__par1__MASK 0x00000020U -#define R_VECT_MASK_RD__scsi0__scsi0__MASK 0x00000010U -#define R_VECT_MASK_RD__par0__par0__MASK 0x00000010U -#define R_VECT_MASK_RD__scsi0__par0__MASK 0x00000010U -#define R_VECT_MASK_RD__ata__ata__MASK 0x00000010U -#define R_VECT_MASK_RD__scsi0__ata__MASK 0x00000010U -#define R_VECT_MASK_RD__mio__mio__MASK 0x00000010U -#define R_VECT_MASK_RD__scsi0__mio__MASK 0x00000010U -#define R_VECT_MASK_RD__timer1__timer1__MASK 0x00000008U -#define R_VECT_MASK_RD__timer0__timer0__MASK 0x00000004U -#define R_VECT_MASK_RD__nmi__nmi__MASK 0x00000002U -#define R_VECT_MASK_RD__some__some__MASK 0x00000001U - -#define R_VECT_MASK_RD__usb__MAX 0x1 -#define R_VECT_MASK_RD__dma9__MAX 0x1 -#define R_VECT_MASK_RD__dma8__MAX 0x1 -#define R_VECT_MASK_RD__dma7__MAX 0x1 -#define R_VECT_MASK_RD__dma6__MAX 0x1 -#define R_VECT_MASK_RD__dma5__MAX 0x1 -#define R_VECT_MASK_RD__dma4__MAX 0x1 -#define R_VECT_MASK_RD__dma3__MAX 0x1 -#define R_VECT_MASK_RD__dma2__MAX 0x1 -#define R_VECT_MASK_RD__dma1__MAX 0x1 -#define R_VECT_MASK_RD__dma0__MAX 0x1 -#define R_VECT_MASK_RD__ext_dma1__MAX 0x1 -#define R_VECT_MASK_RD__ext_dma0__MAX 0x1 -#define R_VECT_MASK_RD__pa__MAX 0x1 -#define R_VECT_MASK_RD__irq_intnr__MAX 0x1 -#define R_VECT_MASK_RD__sw__MAX 0x1 -#define R_VECT_MASK_RD__serial__MAX 0x1 -#define R_VECT_MASK_RD__snmp__MAX 0x1 -#define R_VECT_MASK_RD__network__MAX 0x1 -#define R_VECT_MASK_RD__scsi1__MAX 0x1 -#define R_VECT_MASK_RD__par1__MAX 0x1 -#define R_VECT_MASK_RD__scsi0__MAX 0x1 -#define R_VECT_MASK_RD__par0__MAX 0x1 -#define R_VECT_MASK_RD__ata__MAX 0x1 -#define R_VECT_MASK_RD__mio__MAX 0x1 -#define R_VECT_MASK_RD__timer1__MAX 0x1 -#define R_VECT_MASK_RD__timer0__MAX 0x1 -#define R_VECT_MASK_RD__nmi__MAX 0x1 -#define R_VECT_MASK_RD__some__MAX 0x1 - -#define R_VECT_MASK_RD__usb__MIN 0 -#define R_VECT_MASK_RD__dma9__MIN 0 -#define R_VECT_MASK_RD__dma8__MIN 0 -#define R_VECT_MASK_RD__dma7__MIN 0 -#define R_VECT_MASK_RD__dma6__MIN 0 -#define R_VECT_MASK_RD__dma5__MIN 0 -#define R_VECT_MASK_RD__dma4__MIN 0 -#define R_VECT_MASK_RD__dma3__MIN 0 -#define R_VECT_MASK_RD__dma2__MIN 0 -#define R_VECT_MASK_RD__dma1__MIN 0 -#define R_VECT_MASK_RD__dma0__MIN 0 -#define R_VECT_MASK_RD__ext_dma1__MIN 0 -#define R_VECT_MASK_RD__ext_dma0__MIN 0 -#define R_VECT_MASK_RD__pa__MIN 0 -#define R_VECT_MASK_RD__irq_intnr__MIN 0 -#define R_VECT_MASK_RD__sw__MIN 0 -#define R_VECT_MASK_RD__serial__MIN 0 -#define R_VECT_MASK_RD__snmp__MIN 0 -#define R_VECT_MASK_RD__network__MIN 0 -#define R_VECT_MASK_RD__scsi1__MIN 0 -#define R_VECT_MASK_RD__par1__MIN 0 -#define R_VECT_MASK_RD__scsi0__MIN 0 -#define R_VECT_MASK_RD__par0__MIN 0 -#define R_VECT_MASK_RD__ata__MIN 0 -#define R_VECT_MASK_RD__mio__MIN 0 -#define R_VECT_MASK_RD__timer1__MIN 0 -#define R_VECT_MASK_RD__timer0__MIN 0 -#define R_VECT_MASK_RD__nmi__MIN 0 -#define R_VECT_MASK_RD__some__MIN 0 - -#define R_VECT_MASK_RD__usb__BITNR 31 -#define R_VECT_MASK_RD__dma9__BITNR 25 -#define R_VECT_MASK_RD__dma8__BITNR 24 -#define R_VECT_MASK_RD__dma7__BITNR 23 -#define R_VECT_MASK_RD__dma6__BITNR 22 -#define R_VECT_MASK_RD__dma5__BITNR 21 -#define R_VECT_MASK_RD__dma4__BITNR 20 -#define R_VECT_MASK_RD__dma3__BITNR 19 -#define R_VECT_MASK_RD__dma2__BITNR 18 -#define R_VECT_MASK_RD__dma1__BITNR 17 -#define R_VECT_MASK_RD__dma0__BITNR 16 -#define R_VECT_MASK_RD__ext_dma1__BITNR 13 -#define R_VECT_MASK_RD__ext_dma0__BITNR 12 -#define R_VECT_MASK_RD__pa__BITNR 11 -#define R_VECT_MASK_RD__irq_intnr__BITNR 10 -#define R_VECT_MASK_RD__sw__BITNR 9 -#define R_VECT_MASK_RD__serial__BITNR 8 -#define R_VECT_MASK_RD__snmp__BITNR 7 -#define R_VECT_MASK_RD__network__BITNR 6 -#define R_VECT_MASK_RD__scsi1__BITNR 5 -#define R_VECT_MASK_RD__par1__BITNR 5 -#define R_VECT_MASK_RD__scsi0__BITNR 4 -#define R_VECT_MASK_RD__par0__BITNR 4 -#define R_VECT_MASK_RD__ata__BITNR 4 -#define R_VECT_MASK_RD__mio__BITNR 4 -#define R_VECT_MASK_RD__timer1__BITNR 3 -#define R_VECT_MASK_RD__timer0__BITNR 2 -#define R_VECT_MASK_RD__nmi__BITNR 1 -#define R_VECT_MASK_RD__some__BITNR 0 - -#define R_VECT_MASK_RD__usb__usb__VAL REG_VAL_ENUM -#define R_VECT_MASK_RD__dma9__dma9__VAL REG_VAL_ENUM -#define R_VECT_MASK_RD__dma8__dma8__VAL REG_VAL_ENUM -#define R_VECT_MASK_RD__dma7__dma7__VAL REG_VAL_ENUM -#define R_VECT_MASK_RD__dma6__dma6__VAL REG_VAL_ENUM -#define R_VECT_MASK_RD__dma5__dma5__VAL REG_VAL_ENUM -#define R_VECT_MASK_RD__dma4__dma4__VAL REG_VAL_ENUM -#define R_VECT_MASK_RD__dma3__dma3__VAL REG_VAL_ENUM -#define R_VECT_MASK_RD__dma2__dma2__VAL REG_VAL_ENUM -#define R_VECT_MASK_RD__dma1__dma1__VAL REG_VAL_ENUM -#define R_VECT_MASK_RD__dma0__dma0__VAL REG_VAL_ENUM -#define R_VECT_MASK_RD__ext_dma1__ext_dma1__VAL REG_VAL_ENUM -#define R_VECT_MASK_RD__ext_dma0__ext_dma0__VAL REG_VAL_ENUM -#define R_VECT_MASK_RD__pa__pa__VAL REG_VAL_ENUM -#define R_VECT_MASK_RD__irq_intnr__irq_intnr__VAL REG_VAL_ENUM -#define R_VECT_MASK_RD__sw__sw__VAL REG_VAL_ENUM -#define R_VECT_MASK_RD__serial__serial__VAL REG_VAL_ENUM -#define R_VECT_MASK_RD__snmp__snmp__VAL REG_VAL_ENUM -#define R_VECT_MASK_RD__network__network__VAL REG_VAL_ENUM -#define R_VECT_MASK_RD__scsi1__scsi1__VAL REG_VAL_ENUM -#define R_VECT_MASK_RD__par1__par1__VAL REG_VAL_ENUM -#define R_VECT_MASK_RD__scsi1__par1__VAL REG_VAL_ENUM -#define R_VECT_MASK_RD__scsi0__scsi0__VAL REG_VAL_ENUM -#define R_VECT_MASK_RD__par0__par0__VAL REG_VAL_ENUM -#define R_VECT_MASK_RD__scsi0__par0__VAL REG_VAL_ENUM -#define R_VECT_MASK_RD__ata__ata__VAL REG_VAL_ENUM -#define R_VECT_MASK_RD__scsi0__ata__VAL REG_VAL_ENUM -#define R_VECT_MASK_RD__mio__mio__VAL REG_VAL_ENUM -#define R_VECT_MASK_RD__scsi0__mio__VAL REG_VAL_ENUM -#define R_VECT_MASK_RD__timer1__timer1__VAL REG_VAL_ENUM -#define R_VECT_MASK_RD__timer0__timer0__VAL REG_VAL_ENUM -#define R_VECT_MASK_RD__nmi__nmi__VAL REG_VAL_ENUM -#define R_VECT_MASK_RD__some__some__VAL REG_VAL_ENUM - -#define R_VECT_MASK_RD__usb__usb__active 1 -#define R_VECT_MASK_RD__usb__usb__inactive 0 -#define R_VECT_MASK_RD__dma9__dma9__active 1 -#define R_VECT_MASK_RD__dma9__dma9__inactive 0 -#define R_VECT_MASK_RD__dma8__dma8__active 1 -#define R_VECT_MASK_RD__dma8__dma8__inactive 0 -#define R_VECT_MASK_RD__dma7__dma7__active 1 -#define R_VECT_MASK_RD__dma7__dma7__inactive 0 -#define R_VECT_MASK_RD__dma6__dma6__active 1 -#define R_VECT_MASK_RD__dma6__dma6__inactive 0 -#define R_VECT_MASK_RD__dma5__dma5__active 1 -#define R_VECT_MASK_RD__dma5__dma5__inactive 0 -#define R_VECT_MASK_RD__dma4__dma4__active 1 -#define R_VECT_MASK_RD__dma4__dma4__inactive 0 -#define R_VECT_MASK_RD__dma3__dma3__active 1 -#define R_VECT_MASK_RD__dma3__dma3__inactive 0 -#define R_VECT_MASK_RD__dma2__dma2__active 1 -#define R_VECT_MASK_RD__dma2__dma2__inactive 0 -#define R_VECT_MASK_RD__dma1__dma1__active 1 -#define R_VECT_MASK_RD__dma1__dma1__inactive 0 -#define R_VECT_MASK_RD__dma0__dma0__active 1 -#define R_VECT_MASK_RD__dma0__dma0__inactive 0 -#define R_VECT_MASK_RD__ext_dma1__ext_dma1__active 1 -#define R_VECT_MASK_RD__ext_dma1__ext_dma1__inactive 0 -#define R_VECT_MASK_RD__ext_dma0__ext_dma0__active 1 -#define R_VECT_MASK_RD__ext_dma0__ext_dma0__inactive 0 -#define R_VECT_MASK_RD__pa__pa__active 1 -#define R_VECT_MASK_RD__pa__pa__inactive 0 -#define R_VECT_MASK_RD__irq_intnr__irq_intnr__active 1 -#define R_VECT_MASK_RD__irq_intnr__irq_intnr__inactive 0 -#define R_VECT_MASK_RD__sw__sw__active 1 -#define R_VECT_MASK_RD__sw__sw__inactive 0 -#define R_VECT_MASK_RD__serial__serial__active 1 -#define R_VECT_MASK_RD__serial__serial__inactive 0 -#define R_VECT_MASK_RD__snmp__snmp__active 1 -#define R_VECT_MASK_RD__snmp__snmp__inactive 0 -#define R_VECT_MASK_RD__network__network__active 1 -#define R_VECT_MASK_RD__network__network__inactive 0 -#define R_VECT_MASK_RD__scsi1__scsi1__active 1 -#define R_VECT_MASK_RD__scsi1__scsi1__inactive 0 -#define R_VECT_MASK_RD__par1__par1__active 1 -#define R_VECT_MASK_RD__par1__par1__inactive 0 -#define R_VECT_MASK_RD__scsi0__scsi0__active 1 -#define R_VECT_MASK_RD__scsi0__scsi0__inactive 0 -#define R_VECT_MASK_RD__par0__par0__active 1 -#define R_VECT_MASK_RD__par0__par0__inactive 0 -#define R_VECT_MASK_RD__ata__ata__active 1 -#define R_VECT_MASK_RD__ata__ata__inactive 0 -#define R_VECT_MASK_RD__mio__mio__active 1 -#define R_VECT_MASK_RD__mio__mio__inactive 0 -#define R_VECT_MASK_RD__timer1__timer1__active 1 -#define R_VECT_MASK_RD__timer1__timer1__inactive 0 -#define R_VECT_MASK_RD__timer0__timer0__active 1 -#define R_VECT_MASK_RD__timer0__timer0__inactive 0 -#define R_VECT_MASK_RD__nmi__nmi__active 1 -#define R_VECT_MASK_RD__nmi__nmi__inactive 0 -#define R_VECT_MASK_RD__some__some__active 1 -#define R_VECT_MASK_RD__some__some__inactive 0 - -#endif - -/* - * R_VECT_MASK_SET - * - type: WO - * - addr: 0xb00000dc - * - group: Interrupt mask and status registers - */ - -#if USE_GROUP__Interrupt_mask_and_status_registers - -#define R_VECT_MASK_SET__ADDR (REG_TYPECAST_UDWORD 0xb00000dc) - -#ifndef REG_NO_SHADOW -#define R_VECT_MASK_SET__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_VECT_MASK_SET + 0)) -#define R_VECT_MASK_SET__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_VECT_MASK_SET + 0)) -#else /* REG_NO_SHADOW */ -#define R_VECT_MASK_SET__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_VECT_MASK_SET__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_VECT_MASK_SET__STYPECAST REG_STYPECAST_UDWORD -#define R_VECT_MASK_SET__SVAL REG_SVAL_ZERO -#define R_VECT_MASK_SET__SVAL_I REG_SVAL_I_ZERO -#define R_VECT_MASK_SET__TYPECAST REG_TYPECAST_UDWORD -#define R_VECT_MASK_SET__TYPE (REG_UDWORD) -#define R_VECT_MASK_SET__GET REG_GET_WO -#define R_VECT_MASK_SET__IGET REG_IGET_WO -#define R_VECT_MASK_SET__SET REG_SET_WO -#define R_VECT_MASK_SET__ISET REG_ISET_WO -#define R_VECT_MASK_SET__SET_VAL REG_SET_VAL_WO -#define R_VECT_MASK_SET__EQL REG_EQL_WO -#define R_VECT_MASK_SET__IEQL REG_IEQL_WO -#define R_VECT_MASK_SET__RD REG_RD_WO -#define R_VECT_MASK_SET__IRD REG_IRD_WO -#define R_VECT_MASK_SET__WR REG_WR_WO -#define R_VECT_MASK_SET__IWR REG_IWR_WO - -#define R_VECT_MASK_SET__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_VECT_MASK_SET__usb__usb__MASK 0x80000000U -#define R_VECT_MASK_SET__dma9__dma9__MASK 0x02000000U -#define R_VECT_MASK_SET__dma8__dma8__MASK 0x01000000U -#define R_VECT_MASK_SET__dma7__dma7__MASK 0x00800000U -#define R_VECT_MASK_SET__dma6__dma6__MASK 0x00400000U -#define R_VECT_MASK_SET__dma5__dma5__MASK 0x00200000U -#define R_VECT_MASK_SET__dma4__dma4__MASK 0x00100000U -#define R_VECT_MASK_SET__dma3__dma3__MASK 0x00080000U -#define R_VECT_MASK_SET__dma2__dma2__MASK 0x00040000U -#define R_VECT_MASK_SET__dma1__dma1__MASK 0x00020000U -#define R_VECT_MASK_SET__dma0__dma0__MASK 0x00010000U -#define R_VECT_MASK_SET__ext_dma1__ext_dma1__MASK 0x00002000U -#define R_VECT_MASK_SET__ext_dma0__ext_dma0__MASK 0x00001000U -#define R_VECT_MASK_SET__pa__pa__MASK 0x00000800U -#define R_VECT_MASK_SET__irq_intnr__irq_intnr__MASK 0x00000400U -#define R_VECT_MASK_SET__sw__sw__MASK 0x00000200U -#define R_VECT_MASK_SET__serial__serial__MASK 0x00000100U -#define R_VECT_MASK_SET__snmp__snmp__MASK 0x00000080U -#define R_VECT_MASK_SET__network__network__MASK 0x00000040U -#define R_VECT_MASK_SET__scsi1__scsi1__MASK 0x00000020U -#define R_VECT_MASK_SET__par1__par1__MASK 0x00000020U -#define R_VECT_MASK_SET__scsi1__par1__MASK 0x00000020U -#define R_VECT_MASK_SET__scsi0__scsi0__MASK 0x00000010U -#define R_VECT_MASK_SET__par0__par0__MASK 0x00000010U -#define R_VECT_MASK_SET__scsi0__par0__MASK 0x00000010U -#define R_VECT_MASK_SET__ata__ata__MASK 0x00000010U -#define R_VECT_MASK_SET__scsi0__ata__MASK 0x00000010U -#define R_VECT_MASK_SET__mio__mio__MASK 0x00000010U -#define R_VECT_MASK_SET__scsi0__mio__MASK 0x00000010U -#define R_VECT_MASK_SET__timer1__timer1__MASK 0x00000008U -#define R_VECT_MASK_SET__timer0__timer0__MASK 0x00000004U -#define R_VECT_MASK_SET__nmi__nmi__MASK 0x00000002U -#define R_VECT_MASK_SET__some__some__MASK 0x00000001U - -#define R_VECT_MASK_SET__usb__MAX 0x1 -#define R_VECT_MASK_SET__dma9__MAX 0x1 -#define R_VECT_MASK_SET__dma8__MAX 0x1 -#define R_VECT_MASK_SET__dma7__MAX 0x1 -#define R_VECT_MASK_SET__dma6__MAX 0x1 -#define R_VECT_MASK_SET__dma5__MAX 0x1 -#define R_VECT_MASK_SET__dma4__MAX 0x1 -#define R_VECT_MASK_SET__dma3__MAX 0x1 -#define R_VECT_MASK_SET__dma2__MAX 0x1 -#define R_VECT_MASK_SET__dma1__MAX 0x1 -#define R_VECT_MASK_SET__dma0__MAX 0x1 -#define R_VECT_MASK_SET__ext_dma1__MAX 0x1 -#define R_VECT_MASK_SET__ext_dma0__MAX 0x1 -#define R_VECT_MASK_SET__pa__MAX 0x1 -#define R_VECT_MASK_SET__irq_intnr__MAX 0x1 -#define R_VECT_MASK_SET__sw__MAX 0x1 -#define R_VECT_MASK_SET__serial__MAX 0x1 -#define R_VECT_MASK_SET__snmp__MAX 0x1 -#define R_VECT_MASK_SET__network__MAX 0x1 -#define R_VECT_MASK_SET__scsi1__MAX 0x1 -#define R_VECT_MASK_SET__par1__MAX 0x1 -#define R_VECT_MASK_SET__scsi0__MAX 0x1 -#define R_VECT_MASK_SET__par0__MAX 0x1 -#define R_VECT_MASK_SET__ata__MAX 0x1 -#define R_VECT_MASK_SET__mio__MAX 0x1 -#define R_VECT_MASK_SET__timer1__MAX 0x1 -#define R_VECT_MASK_SET__timer0__MAX 0x1 -#define R_VECT_MASK_SET__nmi__MAX 0x1 -#define R_VECT_MASK_SET__some__MAX 0x1 - -#define R_VECT_MASK_SET__usb__MIN 0 -#define R_VECT_MASK_SET__dma9__MIN 0 -#define R_VECT_MASK_SET__dma8__MIN 0 -#define R_VECT_MASK_SET__dma7__MIN 0 -#define R_VECT_MASK_SET__dma6__MIN 0 -#define R_VECT_MASK_SET__dma5__MIN 0 -#define R_VECT_MASK_SET__dma4__MIN 0 -#define R_VECT_MASK_SET__dma3__MIN 0 -#define R_VECT_MASK_SET__dma2__MIN 0 -#define R_VECT_MASK_SET__dma1__MIN 0 -#define R_VECT_MASK_SET__dma0__MIN 0 -#define R_VECT_MASK_SET__ext_dma1__MIN 0 -#define R_VECT_MASK_SET__ext_dma0__MIN 0 -#define R_VECT_MASK_SET__pa__MIN 0 -#define R_VECT_MASK_SET__irq_intnr__MIN 0 -#define R_VECT_MASK_SET__sw__MIN 0 -#define R_VECT_MASK_SET__serial__MIN 0 -#define R_VECT_MASK_SET__snmp__MIN 0 -#define R_VECT_MASK_SET__network__MIN 0 -#define R_VECT_MASK_SET__scsi1__MIN 0 -#define R_VECT_MASK_SET__par1__MIN 0 -#define R_VECT_MASK_SET__scsi0__MIN 0 -#define R_VECT_MASK_SET__par0__MIN 0 -#define R_VECT_MASK_SET__ata__MIN 0 -#define R_VECT_MASK_SET__mio__MIN 0 -#define R_VECT_MASK_SET__timer1__MIN 0 -#define R_VECT_MASK_SET__timer0__MIN 0 -#define R_VECT_MASK_SET__nmi__MIN 0 -#define R_VECT_MASK_SET__some__MIN 0 - -#define R_VECT_MASK_SET__usb__BITNR 31 -#define R_VECT_MASK_SET__dma9__BITNR 25 -#define R_VECT_MASK_SET__dma8__BITNR 24 -#define R_VECT_MASK_SET__dma7__BITNR 23 -#define R_VECT_MASK_SET__dma6__BITNR 22 -#define R_VECT_MASK_SET__dma5__BITNR 21 -#define R_VECT_MASK_SET__dma4__BITNR 20 -#define R_VECT_MASK_SET__dma3__BITNR 19 -#define R_VECT_MASK_SET__dma2__BITNR 18 -#define R_VECT_MASK_SET__dma1__BITNR 17 -#define R_VECT_MASK_SET__dma0__BITNR 16 -#define R_VECT_MASK_SET__ext_dma1__BITNR 13 -#define R_VECT_MASK_SET__ext_dma0__BITNR 12 -#define R_VECT_MASK_SET__pa__BITNR 11 -#define R_VECT_MASK_SET__irq_intnr__BITNR 10 -#define R_VECT_MASK_SET__sw__BITNR 9 -#define R_VECT_MASK_SET__serial__BITNR 8 -#define R_VECT_MASK_SET__snmp__BITNR 7 -#define R_VECT_MASK_SET__network__BITNR 6 -#define R_VECT_MASK_SET__scsi1__BITNR 5 -#define R_VECT_MASK_SET__par1__BITNR 5 -#define R_VECT_MASK_SET__scsi0__BITNR 4 -#define R_VECT_MASK_SET__par0__BITNR 4 -#define R_VECT_MASK_SET__ata__BITNR 4 -#define R_VECT_MASK_SET__mio__BITNR 4 -#define R_VECT_MASK_SET__timer1__BITNR 3 -#define R_VECT_MASK_SET__timer0__BITNR 2 -#define R_VECT_MASK_SET__nmi__BITNR 1 -#define R_VECT_MASK_SET__some__BITNR 0 - -#define R_VECT_MASK_SET__usb__usb__VAL REG_VAL_ENUM -#define R_VECT_MASK_SET__dma9__dma9__VAL REG_VAL_ENUM -#define R_VECT_MASK_SET__dma8__dma8__VAL REG_VAL_ENUM -#define R_VECT_MASK_SET__dma7__dma7__VAL REG_VAL_ENUM -#define R_VECT_MASK_SET__dma6__dma6__VAL REG_VAL_ENUM -#define R_VECT_MASK_SET__dma5__dma5__VAL REG_VAL_ENUM -#define R_VECT_MASK_SET__dma4__dma4__VAL REG_VAL_ENUM -#define R_VECT_MASK_SET__dma3__dma3__VAL REG_VAL_ENUM -#define R_VECT_MASK_SET__dma2__dma2__VAL REG_VAL_ENUM -#define R_VECT_MASK_SET__dma1__dma1__VAL REG_VAL_ENUM -#define R_VECT_MASK_SET__dma0__dma0__VAL REG_VAL_ENUM -#define R_VECT_MASK_SET__ext_dma1__ext_dma1__VAL REG_VAL_ENUM -#define R_VECT_MASK_SET__ext_dma0__ext_dma0__VAL REG_VAL_ENUM -#define R_VECT_MASK_SET__pa__pa__VAL REG_VAL_ENUM -#define R_VECT_MASK_SET__irq_intnr__irq_intnr__VAL REG_VAL_ENUM -#define R_VECT_MASK_SET__sw__sw__VAL REG_VAL_ENUM -#define R_VECT_MASK_SET__serial__serial__VAL REG_VAL_ENUM -#define R_VECT_MASK_SET__snmp__snmp__VAL REG_VAL_ENUM -#define R_VECT_MASK_SET__network__network__VAL REG_VAL_ENUM -#define R_VECT_MASK_SET__scsi1__scsi1__VAL REG_VAL_ENUM -#define R_VECT_MASK_SET__par1__par1__VAL REG_VAL_ENUM -#define R_VECT_MASK_SET__scsi1__par1__VAL REG_VAL_ENUM -#define R_VECT_MASK_SET__scsi0__scsi0__VAL REG_VAL_ENUM -#define R_VECT_MASK_SET__par0__par0__VAL REG_VAL_ENUM -#define R_VECT_MASK_SET__scsi0__par0__VAL REG_VAL_ENUM -#define R_VECT_MASK_SET__ata__ata__VAL REG_VAL_ENUM -#define R_VECT_MASK_SET__scsi0__ata__VAL REG_VAL_ENUM -#define R_VECT_MASK_SET__mio__mio__VAL REG_VAL_ENUM -#define R_VECT_MASK_SET__scsi0__mio__VAL REG_VAL_ENUM -#define R_VECT_MASK_SET__timer1__timer1__VAL REG_VAL_ENUM -#define R_VECT_MASK_SET__timer0__timer0__VAL REG_VAL_ENUM -#define R_VECT_MASK_SET__nmi__nmi__VAL REG_VAL_ENUM -#define R_VECT_MASK_SET__some__some__VAL REG_VAL_ENUM - -#define R_VECT_MASK_SET__usb__usb__nop 0 -#define R_VECT_MASK_SET__usb__usb__set 1 -#define R_VECT_MASK_SET__dma9__dma9__nop 0 -#define R_VECT_MASK_SET__dma9__dma9__set 1 -#define R_VECT_MASK_SET__dma8__dma8__nop 0 -#define R_VECT_MASK_SET__dma8__dma8__set 1 -#define R_VECT_MASK_SET__dma7__dma7__nop 0 -#define R_VECT_MASK_SET__dma7__dma7__set 1 -#define R_VECT_MASK_SET__dma6__dma6__nop 0 -#define R_VECT_MASK_SET__dma6__dma6__set 1 -#define R_VECT_MASK_SET__dma5__dma5__nop 0 -#define R_VECT_MASK_SET__dma5__dma5__set 1 -#define R_VECT_MASK_SET__dma4__dma4__nop 0 -#define R_VECT_MASK_SET__dma4__dma4__set 1 -#define R_VECT_MASK_SET__dma3__dma3__nop 0 -#define R_VECT_MASK_SET__dma3__dma3__set 1 -#define R_VECT_MASK_SET__dma2__dma2__nop 0 -#define R_VECT_MASK_SET__dma2__dma2__set 1 -#define R_VECT_MASK_SET__dma1__dma1__nop 0 -#define R_VECT_MASK_SET__dma1__dma1__set 1 -#define R_VECT_MASK_SET__dma0__dma0__nop 0 -#define R_VECT_MASK_SET__dma0__dma0__set 1 -#define R_VECT_MASK_SET__ext_dma1__ext_dma1__nop 0 -#define R_VECT_MASK_SET__ext_dma1__ext_dma1__set 1 -#define R_VECT_MASK_SET__ext_dma0__ext_dma0__nop 0 -#define R_VECT_MASK_SET__ext_dma0__ext_dma0__set 1 -#define R_VECT_MASK_SET__pa__pa__nop 0 -#define R_VECT_MASK_SET__pa__pa__set 1 -#define R_VECT_MASK_SET__irq_intnr__irq_intnr__nop 0 -#define R_VECT_MASK_SET__irq_intnr__irq_intnr__set 1 -#define R_VECT_MASK_SET__sw__sw__nop 0 -#define R_VECT_MASK_SET__sw__sw__set 1 -#define R_VECT_MASK_SET__serial__serial__nop 0 -#define R_VECT_MASK_SET__serial__serial__set 1 -#define R_VECT_MASK_SET__snmp__snmp__nop 0 -#define R_VECT_MASK_SET__snmp__snmp__set 1 -#define R_VECT_MASK_SET__network__network__nop 0 -#define R_VECT_MASK_SET__network__network__set 1 -#define R_VECT_MASK_SET__scsi1__scsi1__nop 0 -#define R_VECT_MASK_SET__scsi1__scsi1__set 1 -#define R_VECT_MASK_SET__par1__par1__nop 0 -#define R_VECT_MASK_SET__par1__par1__set 1 -#define R_VECT_MASK_SET__scsi0__scsi0__nop 0 -#define R_VECT_MASK_SET__scsi0__scsi0__set 1 -#define R_VECT_MASK_SET__par0__par0__nop 0 -#define R_VECT_MASK_SET__par0__par0__set 1 -#define R_VECT_MASK_SET__ata__ata__nop 0 -#define R_VECT_MASK_SET__ata__ata__set 1 -#define R_VECT_MASK_SET__mio__mio__nop 0 -#define R_VECT_MASK_SET__mio__mio__set 1 -#define R_VECT_MASK_SET__timer1__timer1__nop 0 -#define R_VECT_MASK_SET__timer1__timer1__set 1 -#define R_VECT_MASK_SET__timer0__timer0__nop 0 -#define R_VECT_MASK_SET__timer0__timer0__set 1 -#define R_VECT_MASK_SET__nmi__nmi__nop 0 -#define R_VECT_MASK_SET__nmi__nmi__set 1 -#define R_VECT_MASK_SET__some__some__nop 0 -#define R_VECT_MASK_SET__some__some__set 1 - -#endif - -/* - * R_VECT_READ - * - type: RO - * - addr: 0xb00000dc - * - group: Interrupt mask and status registers - */ - -#if USE_GROUP__Interrupt_mask_and_status_registers - -#define R_VECT_READ__ADDR (REG_TYPECAST_UDWORD 0xb00000dc) -#define R_VECT_READ__SVAL REG_SVAL_SHADOW -#define R_VECT_READ__SVAL_I REG_SVAL_I_SHADOW -#define R_VECT_READ__TYPECAST REG_TYPECAST_UDWORD -#define R_VECT_READ__TYPE (REG_UDWORD) -#define R_VECT_READ__GET REG_GET_RO -#define R_VECT_READ__IGET REG_IGET_RO -#define R_VECT_READ__SET REG_SET_RO -#define R_VECT_READ__ISET REG_ISET_RO -#define R_VECT_READ__SET_VAL REG_SET_VAL_RO -#define R_VECT_READ__EQL REG_EQL_RO -#define R_VECT_READ__IEQL REG_IEQL_RO -#define R_VECT_READ__RD REG_RD_RO -#define R_VECT_READ__IRD REG_IRD_RO -#define R_VECT_READ__WR REG_WR_RO -#define R_VECT_READ__IWR REG_IWR_RO - -#define R_VECT_READ__READ(addr) \ - (*(addr)) - -#define R_VECT_READ__usb__usb__MASK 0x80000000U -#define R_VECT_READ__dma9__dma9__MASK 0x02000000U -#define R_VECT_READ__dma8__dma8__MASK 0x01000000U -#define R_VECT_READ__dma7__dma7__MASK 0x00800000U -#define R_VECT_READ__dma6__dma6__MASK 0x00400000U -#define R_VECT_READ__dma5__dma5__MASK 0x00200000U -#define R_VECT_READ__dma4__dma4__MASK 0x00100000U -#define R_VECT_READ__dma3__dma3__MASK 0x00080000U -#define R_VECT_READ__dma2__dma2__MASK 0x00040000U -#define R_VECT_READ__dma1__dma1__MASK 0x00020000U -#define R_VECT_READ__dma0__dma0__MASK 0x00010000U -#define R_VECT_READ__ext_dma1__ext_dma1__MASK 0x00002000U -#define R_VECT_READ__ext_dma0__ext_dma0__MASK 0x00001000U -#define R_VECT_READ__pa__pa__MASK 0x00000800U -#define R_VECT_READ__irq_intnr__irq_intnr__MASK 0x00000400U -#define R_VECT_READ__sw__sw__MASK 0x00000200U -#define R_VECT_READ__serial__serial__MASK 0x00000100U -#define R_VECT_READ__snmp__snmp__MASK 0x00000080U -#define R_VECT_READ__network__network__MASK 0x00000040U -#define R_VECT_READ__scsi1__scsi1__MASK 0x00000020U -#define R_VECT_READ__par1__par1__MASK 0x00000020U -#define R_VECT_READ__scsi1__par1__MASK 0x00000020U -#define R_VECT_READ__scsi0__scsi0__MASK 0x00000010U -#define R_VECT_READ__par0__par0__MASK 0x00000010U -#define R_VECT_READ__scsi0__par0__MASK 0x00000010U -#define R_VECT_READ__ata__ata__MASK 0x00000010U -#define R_VECT_READ__scsi0__ata__MASK 0x00000010U -#define R_VECT_READ__mio__mio__MASK 0x00000010U -#define R_VECT_READ__scsi0__mio__MASK 0x00000010U -#define R_VECT_READ__timer1__timer1__MASK 0x00000008U -#define R_VECT_READ__timer0__timer0__MASK 0x00000004U -#define R_VECT_READ__nmi__nmi__MASK 0x00000002U -#define R_VECT_READ__some__some__MASK 0x00000001U - -#define R_VECT_READ__usb__MAX 0x1 -#define R_VECT_READ__dma9__MAX 0x1 -#define R_VECT_READ__dma8__MAX 0x1 -#define R_VECT_READ__dma7__MAX 0x1 -#define R_VECT_READ__dma6__MAX 0x1 -#define R_VECT_READ__dma5__MAX 0x1 -#define R_VECT_READ__dma4__MAX 0x1 -#define R_VECT_READ__dma3__MAX 0x1 -#define R_VECT_READ__dma2__MAX 0x1 -#define R_VECT_READ__dma1__MAX 0x1 -#define R_VECT_READ__dma0__MAX 0x1 -#define R_VECT_READ__ext_dma1__MAX 0x1 -#define R_VECT_READ__ext_dma0__MAX 0x1 -#define R_VECT_READ__pa__MAX 0x1 -#define R_VECT_READ__irq_intnr__MAX 0x1 -#define R_VECT_READ__sw__MAX 0x1 -#define R_VECT_READ__serial__MAX 0x1 -#define R_VECT_READ__snmp__MAX 0x1 -#define R_VECT_READ__network__MAX 0x1 -#define R_VECT_READ__scsi1__MAX 0x1 -#define R_VECT_READ__par1__MAX 0x1 -#define R_VECT_READ__scsi0__MAX 0x1 -#define R_VECT_READ__par0__MAX 0x1 -#define R_VECT_READ__ata__MAX 0x1 -#define R_VECT_READ__mio__MAX 0x1 -#define R_VECT_READ__timer1__MAX 0x1 -#define R_VECT_READ__timer0__MAX 0x1 -#define R_VECT_READ__nmi__MAX 0x1 -#define R_VECT_READ__some__MAX 0x1 - -#define R_VECT_READ__usb__MIN 0 -#define R_VECT_READ__dma9__MIN 0 -#define R_VECT_READ__dma8__MIN 0 -#define R_VECT_READ__dma7__MIN 0 -#define R_VECT_READ__dma6__MIN 0 -#define R_VECT_READ__dma5__MIN 0 -#define R_VECT_READ__dma4__MIN 0 -#define R_VECT_READ__dma3__MIN 0 -#define R_VECT_READ__dma2__MIN 0 -#define R_VECT_READ__dma1__MIN 0 -#define R_VECT_READ__dma0__MIN 0 -#define R_VECT_READ__ext_dma1__MIN 0 -#define R_VECT_READ__ext_dma0__MIN 0 -#define R_VECT_READ__pa__MIN 0 -#define R_VECT_READ__irq_intnr__MIN 0 -#define R_VECT_READ__sw__MIN 0 -#define R_VECT_READ__serial__MIN 0 -#define R_VECT_READ__snmp__MIN 0 -#define R_VECT_READ__network__MIN 0 -#define R_VECT_READ__scsi1__MIN 0 -#define R_VECT_READ__par1__MIN 0 -#define R_VECT_READ__scsi0__MIN 0 -#define R_VECT_READ__par0__MIN 0 -#define R_VECT_READ__ata__MIN 0 -#define R_VECT_READ__mio__MIN 0 -#define R_VECT_READ__timer1__MIN 0 -#define R_VECT_READ__timer0__MIN 0 -#define R_VECT_READ__nmi__MIN 0 -#define R_VECT_READ__some__MIN 0 - -#define R_VECT_READ__usb__BITNR 31 -#define R_VECT_READ__dma9__BITNR 25 -#define R_VECT_READ__dma8__BITNR 24 -#define R_VECT_READ__dma7__BITNR 23 -#define R_VECT_READ__dma6__BITNR 22 -#define R_VECT_READ__dma5__BITNR 21 -#define R_VECT_READ__dma4__BITNR 20 -#define R_VECT_READ__dma3__BITNR 19 -#define R_VECT_READ__dma2__BITNR 18 -#define R_VECT_READ__dma1__BITNR 17 -#define R_VECT_READ__dma0__BITNR 16 -#define R_VECT_READ__ext_dma1__BITNR 13 -#define R_VECT_READ__ext_dma0__BITNR 12 -#define R_VECT_READ__pa__BITNR 11 -#define R_VECT_READ__irq_intnr__BITNR 10 -#define R_VECT_READ__sw__BITNR 9 -#define R_VECT_READ__serial__BITNR 8 -#define R_VECT_READ__snmp__BITNR 7 -#define R_VECT_READ__network__BITNR 6 -#define R_VECT_READ__scsi1__BITNR 5 -#define R_VECT_READ__par1__BITNR 5 -#define R_VECT_READ__scsi0__BITNR 4 -#define R_VECT_READ__par0__BITNR 4 -#define R_VECT_READ__ata__BITNR 4 -#define R_VECT_READ__mio__BITNR 4 -#define R_VECT_READ__timer1__BITNR 3 -#define R_VECT_READ__timer0__BITNR 2 -#define R_VECT_READ__nmi__BITNR 1 -#define R_VECT_READ__some__BITNR 0 - -#define R_VECT_READ__usb__usb__VAL REG_VAL_ENUM -#define R_VECT_READ__dma9__dma9__VAL REG_VAL_ENUM -#define R_VECT_READ__dma8__dma8__VAL REG_VAL_ENUM -#define R_VECT_READ__dma7__dma7__VAL REG_VAL_ENUM -#define R_VECT_READ__dma6__dma6__VAL REG_VAL_ENUM -#define R_VECT_READ__dma5__dma5__VAL REG_VAL_ENUM -#define R_VECT_READ__dma4__dma4__VAL REG_VAL_ENUM -#define R_VECT_READ__dma3__dma3__VAL REG_VAL_ENUM -#define R_VECT_READ__dma2__dma2__VAL REG_VAL_ENUM -#define R_VECT_READ__dma1__dma1__VAL REG_VAL_ENUM -#define R_VECT_READ__dma0__dma0__VAL REG_VAL_ENUM -#define R_VECT_READ__ext_dma1__ext_dma1__VAL REG_VAL_ENUM -#define R_VECT_READ__ext_dma0__ext_dma0__VAL REG_VAL_ENUM -#define R_VECT_READ__pa__pa__VAL REG_VAL_ENUM -#define R_VECT_READ__irq_intnr__irq_intnr__VAL REG_VAL_ENUM -#define R_VECT_READ__sw__sw__VAL REG_VAL_ENUM -#define R_VECT_READ__serial__serial__VAL REG_VAL_ENUM -#define R_VECT_READ__snmp__snmp__VAL REG_VAL_ENUM -#define R_VECT_READ__network__network__VAL REG_VAL_ENUM -#define R_VECT_READ__scsi1__scsi1__VAL REG_VAL_ENUM -#define R_VECT_READ__par1__par1__VAL REG_VAL_ENUM -#define R_VECT_READ__scsi1__par1__VAL REG_VAL_ENUM -#define R_VECT_READ__scsi0__scsi0__VAL REG_VAL_ENUM -#define R_VECT_READ__par0__par0__VAL REG_VAL_ENUM -#define R_VECT_READ__scsi0__par0__VAL REG_VAL_ENUM -#define R_VECT_READ__ata__ata__VAL REG_VAL_ENUM -#define R_VECT_READ__scsi0__ata__VAL REG_VAL_ENUM -#define R_VECT_READ__mio__mio__VAL REG_VAL_ENUM -#define R_VECT_READ__scsi0__mio__VAL REG_VAL_ENUM -#define R_VECT_READ__timer1__timer1__VAL REG_VAL_ENUM -#define R_VECT_READ__timer0__timer0__VAL REG_VAL_ENUM -#define R_VECT_READ__nmi__nmi__VAL REG_VAL_ENUM -#define R_VECT_READ__some__some__VAL REG_VAL_ENUM - -#define R_VECT_READ__usb__usb__active 1 -#define R_VECT_READ__usb__usb__inactive 0 -#define R_VECT_READ__dma9__dma9__active 1 -#define R_VECT_READ__dma9__dma9__inactive 0 -#define R_VECT_READ__dma8__dma8__active 1 -#define R_VECT_READ__dma8__dma8__inactive 0 -#define R_VECT_READ__dma7__dma7__active 1 -#define R_VECT_READ__dma7__dma7__inactive 0 -#define R_VECT_READ__dma6__dma6__active 1 -#define R_VECT_READ__dma6__dma6__inactive 0 -#define R_VECT_READ__dma5__dma5__active 1 -#define R_VECT_READ__dma5__dma5__inactive 0 -#define R_VECT_READ__dma4__dma4__active 1 -#define R_VECT_READ__dma4__dma4__inactive 0 -#define R_VECT_READ__dma3__dma3__active 1 -#define R_VECT_READ__dma3__dma3__inactive 0 -#define R_VECT_READ__dma2__dma2__active 1 -#define R_VECT_READ__dma2__dma2__inactive 0 -#define R_VECT_READ__dma1__dma1__active 1 -#define R_VECT_READ__dma1__dma1__inactive 0 -#define R_VECT_READ__dma0__dma0__active 1 -#define R_VECT_READ__dma0__dma0__inactive 0 -#define R_VECT_READ__ext_dma1__ext_dma1__active 1 -#define R_VECT_READ__ext_dma1__ext_dma1__inactive 0 -#define R_VECT_READ__ext_dma0__ext_dma0__active 1 -#define R_VECT_READ__ext_dma0__ext_dma0__inactive 0 -#define R_VECT_READ__pa__pa__active 1 -#define R_VECT_READ__pa__pa__inactive 0 -#define R_VECT_READ__irq_intnr__irq_intnr__active 1 -#define R_VECT_READ__irq_intnr__irq_intnr__inactive 0 -#define R_VECT_READ__sw__sw__active 1 -#define R_VECT_READ__sw__sw__inactive 0 -#define R_VECT_READ__serial__serial__active 1 -#define R_VECT_READ__serial__serial__inactive 0 -#define R_VECT_READ__snmp__snmp__active 1 -#define R_VECT_READ__snmp__snmp__inactive 0 -#define R_VECT_READ__network__network__active 1 -#define R_VECT_READ__network__network__inactive 0 -#define R_VECT_READ__scsi1__scsi1__active 1 -#define R_VECT_READ__scsi1__scsi1__inactive 0 -#define R_VECT_READ__par1__par1__active 1 -#define R_VECT_READ__par1__par1__inactive 0 -#define R_VECT_READ__scsi0__scsi0__active 1 -#define R_VECT_READ__scsi0__scsi0__inactive 0 -#define R_VECT_READ__par0__par0__active 1 -#define R_VECT_READ__par0__par0__inactive 0 -#define R_VECT_READ__ata__ata__active 1 -#define R_VECT_READ__ata__ata__inactive 0 -#define R_VECT_READ__mio__mio__active 1 -#define R_VECT_READ__mio__mio__inactive 0 -#define R_VECT_READ__timer1__timer1__active 1 -#define R_VECT_READ__timer1__timer1__inactive 0 -#define R_VECT_READ__timer0__timer0__active 1 -#define R_VECT_READ__timer0__timer0__inactive 0 -#define R_VECT_READ__nmi__nmi__active 1 -#define R_VECT_READ__nmi__nmi__inactive 0 -#define R_VECT_READ__some__some__active 1 -#define R_VECT_READ__some__some__inactive 0 - -#endif - -/* - * R_WAITSTATES - * - type: WO - * - addr: 0xb0000000 - * - group: Bus interface configuration registers - */ - -#if USE_GROUP__Bus_interface_configuration_registers - -#define R_WAITSTATES__ADDR (REG_TYPECAST_UDWORD 0xb0000000) - -#ifndef REG_NO_SHADOW -#define R_WAITSTATES__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_WAITSTATES + 0)) -#define R_WAITSTATES__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_WAITSTATES + 0)) -#else /* REG_NO_SHADOW */ -#define R_WAITSTATES__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_WAITSTATES__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_WAITSTATES__STYPECAST REG_STYPECAST_UDWORD -#define R_WAITSTATES__SVAL REG_SVAL_SHADOW -#define R_WAITSTATES__SVAL_I REG_SVAL_I_SHADOW -#define R_WAITSTATES__TYPECAST REG_TYPECAST_UDWORD -#define R_WAITSTATES__TYPE (REG_UDWORD) -#define R_WAITSTATES__GET REG_GET_WO -#define R_WAITSTATES__IGET REG_IGET_WO -#define R_WAITSTATES__SET REG_SET_WO -#define R_WAITSTATES__ISET REG_ISET_WO -#define R_WAITSTATES__SET_VAL REG_SET_VAL_WO -#define R_WAITSTATES__EQL REG_EQL_WO -#define R_WAITSTATES__IEQL REG_IEQL_WO -#define R_WAITSTATES__RD REG_RD_WO -#define R_WAITSTATES__IRD REG_IRD_WO -#define R_WAITSTATES__WR REG_WR_WO -#define R_WAITSTATES__IWR REG_IWR_WO - -#define R_WAITSTATES__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_WAITSTATES__pcs4_7_zw__pcs4_7_zw__MASK 0xc0000000U -#define R_WAITSTATES__pcs4_7_ew__pcs4_7_ew__MASK 0x30000000U -#define R_WAITSTATES__pcs4_7_lw__pcs4_7_lw__MASK 0x0f000000U -#define R_WAITSTATES__pcs0_3_zw__pcs0_3_zw__MASK 0x00c00000U -#define R_WAITSTATES__pcs0_3_ew__pcs0_3_ew__MASK 0x00300000U -#define R_WAITSTATES__pcs0_3_lw__pcs0_3_lw__MASK 0x000f0000U -#define R_WAITSTATES__sram_zw__sram_zw__MASK 0x0000c000U -#define R_WAITSTATES__sram_ew__sram_ew__MASK 0x00003000U -#define R_WAITSTATES__sram_lw__sram_lw__MASK 0x00000f00U -#define R_WAITSTATES__flash_zw__flash_zw__MASK 0x000000c0U -#define R_WAITSTATES__flash_ew__flash_ew__MASK 0x00000030U -#define R_WAITSTATES__flash_lw__flash_lw__MASK 0x0000000fU - -#define R_WAITSTATES__pcs4_7_zw__MAX 3 -#define R_WAITSTATES__pcs4_7_ew__MAX 3 -#define R_WAITSTATES__pcs4_7_lw__MAX 15 -#define R_WAITSTATES__pcs0_3_zw__MAX 3 -#define R_WAITSTATES__pcs0_3_ew__MAX 3 -#define R_WAITSTATES__pcs0_3_lw__MAX 15 -#define R_WAITSTATES__sram_zw__MAX 3 -#define R_WAITSTATES__sram_ew__MAX 3 -#define R_WAITSTATES__sram_lw__MAX 15 -#define R_WAITSTATES__flash_zw__MAX 3 -#define R_WAITSTATES__flash_ew__MAX 3 -#define R_WAITSTATES__flash_lw__MAX 15 - -#define R_WAITSTATES__pcs4_7_zw__MIN 0 -#define R_WAITSTATES__pcs4_7_ew__MIN 0 -#define R_WAITSTATES__pcs4_7_lw__MIN 0 -#define R_WAITSTATES__pcs0_3_zw__MIN 0 -#define R_WAITSTATES__pcs0_3_ew__MIN 0 -#define R_WAITSTATES__pcs0_3_lw__MIN 0 -#define R_WAITSTATES__sram_zw__MIN 0 -#define R_WAITSTATES__sram_ew__MIN 0 -#define R_WAITSTATES__sram_lw__MIN 0 -#define R_WAITSTATES__flash_zw__MIN 0 -#define R_WAITSTATES__flash_ew__MIN 0 -#define R_WAITSTATES__flash_lw__MIN 0 - -#define R_WAITSTATES__pcs4_7_zw__BITNR 30 -#define R_WAITSTATES__pcs4_7_ew__BITNR 28 -#define R_WAITSTATES__pcs4_7_lw__BITNR 24 -#define R_WAITSTATES__pcs0_3_zw__BITNR 22 -#define R_WAITSTATES__pcs0_3_ew__BITNR 20 -#define R_WAITSTATES__pcs0_3_lw__BITNR 16 -#define R_WAITSTATES__sram_zw__BITNR 14 -#define R_WAITSTATES__sram_ew__BITNR 12 -#define R_WAITSTATES__sram_lw__BITNR 8 -#define R_WAITSTATES__flash_zw__BITNR 6 -#define R_WAITSTATES__flash_ew__BITNR 4 -#define R_WAITSTATES__flash_lw__BITNR 0 - -#define R_WAITSTATES__pcs4_7_zw__pcs4_7_zw__VAL REG_VAL_VAL -#define R_WAITSTATES__pcs4_7_ew__pcs4_7_ew__VAL REG_VAL_VAL -#define R_WAITSTATES__pcs4_7_lw__pcs4_7_lw__VAL REG_VAL_VAL -#define R_WAITSTATES__pcs0_3_zw__pcs0_3_zw__VAL REG_VAL_VAL -#define R_WAITSTATES__pcs0_3_ew__pcs0_3_ew__VAL REG_VAL_VAL -#define R_WAITSTATES__pcs0_3_lw__pcs0_3_lw__VAL REG_VAL_VAL -#define R_WAITSTATES__sram_zw__sram_zw__VAL REG_VAL_VAL -#define R_WAITSTATES__sram_ew__sram_ew__VAL REG_VAL_VAL -#define R_WAITSTATES__sram_lw__sram_lw__VAL REG_VAL_VAL -#define R_WAITSTATES__flash_zw__flash_zw__VAL REG_VAL_VAL -#define R_WAITSTATES__flash_ew__flash_ew__VAL REG_VAL_VAL -#define R_WAITSTATES__flash_lw__flash_lw__VAL REG_VAL_VAL - - -#endif - -/* - * R_WATCHDOG - * - type: WO - * - addr: 0xb0000024 - * - group: Timer registers - */ - -#if USE_GROUP__Timer_registers - -#define R_WATCHDOG__ADDR (REG_TYPECAST_UDWORD 0xb0000024) - -#ifndef REG_NO_SHADOW -#define R_WATCHDOG__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_WATCHDOG + 0)) -#define R_WATCHDOG__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_WATCHDOG + 0)) -#else /* REG_NO_SHADOW */ -#define R_WATCHDOG__SADDR (REG_STYPECAST_UDWORD (®_shadow__hwregs)) -#define R_WATCHDOG__IADDR (REG_STYPECAST_UDWORD (®_initiated__hwregs)) -#endif /* REG_NO_SHADOW */ - -#define R_WATCHDOG__STYPECAST REG_STYPECAST_UDWORD -#define R_WATCHDOG__SVAL REG_SVAL_SHADOW -#define R_WATCHDOG__SVAL_I REG_SVAL_I_SHADOW -#define R_WATCHDOG__TYPECAST REG_TYPECAST_UDWORD -#define R_WATCHDOG__TYPE (REG_UDWORD) -#define R_WATCHDOG__GET REG_GET_WO -#define R_WATCHDOG__IGET REG_IGET_WO -#define R_WATCHDOG__SET REG_SET_WO -#define R_WATCHDOG__ISET REG_ISET_WO -#define R_WATCHDOG__SET_VAL REG_SET_VAL_WO -#define R_WATCHDOG__EQL REG_EQL_WO -#define R_WATCHDOG__IEQL REG_IEQL_WO -#define R_WATCHDOG__RD REG_RD_WO -#define R_WATCHDOG__IRD REG_IRD_WO -#define R_WATCHDOG__WR REG_WR_WO -#define R_WATCHDOG__IWR REG_IWR_WO - -#define R_WATCHDOG__WRITE(addr,value) \ - (*(addr) = (value)) - -#define R_WATCHDOG__key__key__MASK 0x0000000eU -#define R_WATCHDOG__enable__enable__MASK 0x00000001U - -#define R_WATCHDOG__key__MAX 7 -#define R_WATCHDOG__enable__MAX 0x1 - -#define R_WATCHDOG__key__MIN 0 -#define R_WATCHDOG__enable__MIN 0 - -#define R_WATCHDOG__key__BITNR 1 -#define R_WATCHDOG__enable__BITNR 0 - -#define R_WATCHDOG__key__key__VAL REG_VAL_VAL -#define R_WATCHDOG__enable__enable__VAL REG_VAL_ENUM - -#define R_WATCHDOG__enable__enable__start 1 -#define R_WATCHDOG__enable__enable__stop 0 - -#endif - -#endif diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/src/ldscript b/target/linux/etrax-2.6/image/e100boot/src/cbl/src/ldscript deleted file mode 100644 index 24c8a318ad..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/cbl/src/ldscript +++ /dev/null @@ -1,38 +0,0 @@ -SECTIONS -{ - . = 0x380000f0; - __Stext = .; - - .text : - { - KEEP (*(.startup)) - KEEP (*(.text)) - *(.text.*) - KEEP (*(.rodata)) - *(.rodata.*) - } =0 - - __Etext = .; - - .data : - { - __Sdata = .; - KEEP (*(.data)) - *(.data.*) - } - - __Edata = .; - . = ALIGN (4); - __Sbss = .; - .bss : - { - /* The network crc will land in the first four bytes of the - bss. Move the variables out of the way. */ - . = . + 12; - *(.bss.*) - *(COMMON) - } - - __Ebss = .; - -} diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/src/net_init.c b/target/linux/etrax-2.6/image/e100boot/src/cbl/src/net_init.c deleted file mode 100644 index b6a56ad3a7..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/cbl/src/net_init.c +++ /dev/null @@ -1,218 +0,0 @@ -#define net_init init_interface -#define handle_network_read handle_read -#define send_network_ack send_ack -#define send_network_string send_string -#define send_network_hex send_hex - -#include "sv_addr_ag.h" -#include "e100boot.h" - -static void start_network_trans(void); - -void -net_init(void) -{ - *R_NETWORK_GA_1 = *R_NETWORK_GA_0 = 0; - - SET_ETHER_ADDR(0x01,0x40,0x8c,0x00,0x01,0x00, - 0x01,0x40,0x8c,0x00,0x01,0x00); - - *R_NETWORK_REC_CONFIG = - IO_STATE (R_NETWORK_REC_CONFIG, duplex, half) | - IO_STATE (R_NETWORK_REC_CONFIG, bad_crc, discard) | - IO_STATE (R_NETWORK_REC_CONFIG, oversize, discard) | - IO_STATE (R_NETWORK_REC_CONFIG, undersize, discard) | - IO_STATE (R_NETWORK_REC_CONFIG, all_roots, discard) | - IO_STATE (R_NETWORK_REC_CONFIG, broadcast, discard) | - IO_STATE (R_NETWORK_REC_CONFIG, individual, discard) | - IO_STATE (R_NETWORK_REC_CONFIG, ma1, disable) | - IO_STATE (R_NETWORK_REC_CONFIG, ma0, enable); - - *R_NETWORK_MGM_CTRL = - IO_FIELD(R_NETWORK_MGM_CTRL, txd_pins, 0) | - IO_FIELD(R_NETWORK_MGM_CTRL, txer_pin, 0) | - IO_FIELD(R_NETWORK_MGM_CTRL, mdck, 0) | - IO_STATE(R_NETWORK_MGM_CTRL, mdoe, disable) | - IO_FIELD(R_NETWORK_MGM_CTRL, mdio, 0); - - *R_NETWORK_TR_CTRL = - (IO_STATE (R_NETWORK_TR_CTRL, clr_error, clr) | - IO_STATE (R_NETWORK_TR_CTRL, delay, none) | - IO_STATE (R_NETWORK_TR_CTRL, cancel, dont) | - IO_STATE (R_NETWORK_TR_CTRL, cd, enable) | - IO_STATE (R_NETWORK_TR_CTRL, pad, enable) | - IO_STATE (R_NETWORK_TR_CTRL, crc, enable) | - IO_STATE (R_NETWORK_TR_CTRL, retry, enable)); - - *R_NETWORK_GEN_CONFIG = - IO_STATE (R_NETWORK_GEN_CONFIG, loopback, off) | - IO_STATE (R_NETWORK_GEN_CONFIG, frame, ether) | - IO_STATE (R_NETWORK_GEN_CONFIG, vg, off) | - IO_STATE (R_NETWORK_GEN_CONFIG, phy, mii_clk) | - IO_STATE (R_NETWORK_GEN_CONFIG, enable, on); - - *R_DMA_CH0_CMD = IO_STATE(R_DMA_CH0_CMD, cmd, reset); - *R_DMA_CH1_CMD = IO_STATE(R_DMA_CH1_CMD, cmd, reset); - - rx_descr.sw_len = NETWORK_HEADER_LENGTH; - rx_descr.ctrl = TX_CTRL; - rx_descr.next = (udword)&rx_descr2; - rx_descr.buf = (udword)&rx_header; - - rx_descr2.sw_len = 1500; - rx_descr2.ctrl = TX_CTRL_EOP; - rx_descr2.buf = target_address; - - /* Endian dependent, but saves a few bytes... */ - *(udword*)&tx_header.src[0] = htonl(0x02408c00); - *(uword*)&tx_header.src[4] = htons(0x0100); - tx_header.length = htons(64); - tx_header.snap1 = htonl(0xaaaa0300); - tx_header.snap2 = htonl(0x408c8856); - tx_header.tag = htonl(0xfffffffe); - tx_header.seq = 0; - tx_header.type = 0; - - tx_descr.sw_len = NETWORK_HEADER_LENGTH; - tx_descr.ctrl = TX_CTRL_EOP; - tx_descr.buf = (udword)&tx_header; - - set_dest = FALSE; - seq = 0; - - *R_DMA_CH1_FIRST = (udword)&rx_descr; - *R_DMA_CH1_CMD = IO_STATE(R_DMA_CH1_CMD, cmd, start); -} - -int -handle_network_read(void) -{ - if (!(rx_descr2.status & d_eop)) { - return FALSE; - } - - /* Even if wasn't to us, we must do this... */ - rx_descr2.status = 0; - *R_DMA_CH1_FIRST = (udword)&rx_descr; - - /* Was it to me? */ - if (ntohl(rx_header.seq) == (seq+1)) { - interface = NETWORK; - last_timeout = *R_TIMER_DATA >> IO_BITNR(R_TIMER_DATA, timer0); - nbr_read += rx_descr2.hw_len - CRC_LEN; - rx_descr2.buf += rx_descr2.hw_len - CRC_LEN; - rx_descr2.sw_len = bytes_to_read - nbr_read - CRC_LEN < 1500 ? - bytes_to_read - nbr_read + CRC_LEN: 1500; /* FIX!!!!! */ - rx_descr2.sw_len = rx_descr2.sw_len + NETWORK_HEADER_LENGTH < 64 - ? 64 - NETWORK_HEADER_LENGTH : rx_descr2.sw_len; /* Less than minimum eth packet? */ - - seq++; - send_network_ack(); - } - - return TRUE; -} - -void -send_network_ack(void) -{ -/* send_serial_string(">send_network_ack.\r\n"); */ - - if (!set_dest) { /* Copy destination address from first received packet */ - set_dest = TRUE; - /* If we have done a bootrom network boot, source address is in a different - place... */ - if (((*R_BUS_STATUS & IO_MASK(R_BUS_STATUS, boot)) - >> IO_BITNR(R_BUS_STATUS, boot)) - 1 == NETWORK) { - *(udword*)&tx_header.dest[0] = *(udword*)0x380000dc; - *(uword*)&tx_header.dest[4] = *(uword*)0x380000e0; - } - else { - *(udword*)&tx_header.dest[0] = *(udword*)&rx_header.src[0]; - *(uword*)&tx_header.dest[4] = *(uword*)&rx_header.src[4]; - } - } - -#if 1 - tx_header.seq = htonl(seq); - tx_header.type = htonl(ACK); -#else - tx_header.seq = htonl(seq); - tx_header.type = htonl(bytes_to_read); - tx_header.id = htonl(target_address); - /* tx_header.id already set in start(). */ -#endif - - tx_descr.ctrl = TX_CTRL_EOP; - tx_descr.sw_len = NETWORK_HEADER_LENGTH; - - start_network_trans(); -} - -void -start_network_trans(void) -{ -/* send_serial_string(">start_network_trans\r\n"); */ - - /* Clear possible underrun or excessive retry errors */ -/* *R_NETWORK_TR_CTRL = */ -/* (IO_STATE (R_NETWORK_TR_CTRL, clr_error, clr) | */ -/* IO_STATE (R_NETWORK_TR_CTRL, delay, none) | */ -/* IO_STATE (R_NETWORK_TR_CTRL, cancel, dont) | */ -/* IO_STATE (R_NETWORK_TR_CTRL, cd, enable) | */ -/* IO_STATE (R_NETWORK_TR_CTRL, pad, enable) | */ -/* IO_STATE (R_NETWORK_TR_CTRL, crc, enable) | */ -/* IO_STATE (R_NETWORK_TR_CTRL, retry, enable)); */ - - *R_DMA_CH0_FIRST = (udword)&tx_descr; - *R_DMA_CH0_CMD = IO_STATE(R_DMA_CH0_CMD, cmd, start); - while(*R_DMA_CH0_FIRST) - ; -} - -void -send_network_string(char *str) -{ - int i; - - tx_descr.next = (udword)&tx_descr2; - tx_descr.ctrl = TX_CTRL; - for (i = 0; str[i]; i++) /* strlen */ - ; - - tx_header.type = STRING; - - tx_descr2.ctrl = TX_CTRL_EOP; - tx_descr2.buf = (udword)str; - tx_descr2.sw_len = i+1; - - start_network_trans(); -} - -void -send_network_hex(udword v, byte nl) -{ - tx_descr.next = (udword)&tx_descr2; - tx_descr.ctrl = TX_CTRL; - - tx_header.type = nl ? htonl(NET_INT_NL) : htonl(NET_INT); - - /* Pause so we don't saturate network. */ - /* Hehe, the asm will fool gcc to not remove the loop even though it - probably should. If we volatile i the code will be a few bytes - longer than this version. Well I really did it like this just - because it is possible... */ - { - udword i; - - for(i = 0; i != 16384; i++) - __asm__ (""); - } - - v = htonl(v); - tx_descr2.ctrl = TX_CTRL_EOP; - tx_descr2.buf = (udword)&v; - tx_descr2.sw_len = (uword)sizeof(udword); - - start_network_trans(); -} diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/src/project.h b/target/linux/etrax-2.6/image/e100boot/src/cbl/src/project.h deleted file mode 100644 index 0d54f8fa6d..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/cbl/src/project.h +++ /dev/null @@ -1,10 +0,0 @@ -#define REG_NO_SHADOW 1 -#define REG_NO_INIT_SHADOW 1 - -#define USE_GROUP__Serial_port_registers 1 -#define USE_GROUP__Network_interface_registers 1 -#define USE_GROUP__Parallel_printer_port_registers 1 -#define USE_GROUP__Timer_registers 1 -#define USE_GROUP__General_port_configuration_registers 1 -#define USE_GROUP__Bus_interface_configuration_registers 1 -#define USE_GROUP__DMA_registers 1 diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/src/ser_init.c b/target/linux/etrax-2.6/image/e100boot/src/cbl/src/ser_init.c deleted file mode 100644 index 2fcf4311cd..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/cbl/src/ser_init.c +++ /dev/null @@ -1,117 +0,0 @@ -#define ser_init init_interface -#define handle_serial_read handle_read -#define send_serial_ack send_ack -#define send_serial_string send_string -#define send_serial_hex send_hex - -#include "hwregs.h" -#include "sv_addr_ag.h" -#include "e100boot.h" - -void -ser_init(void) -{ - REG_SET__R_SERIAL0_XOFF - ( - tx_stop, enable, - auto_xoff, disable, - xoff_char, 0 - ); - - REG_SET__R_SERIAL0_BAUD - ( - tr_baud, c9600Hz, - rec_baud, c9600Hz - ); - - REG_SET__R_SERIAL0_REC_CTRL - ( - dma_err, stop, - rec_enable, enable, - rts_, inactive, - sampling, middle, - rec_stick_par, normal, - rec_par, even, - rec_par_en, disable, - rec_bitnr, rec_8bit - ); - - REG_SET__R_SERIAL0_TR_CTRL - ( - txd, 0, - tr_enable, enable, - auto_cts, disabled, - stop_bits, one_bit, - tr_stick_par, normal, - tr_par, even, - tr_par_en, disable, - tr_bitnr, tr_8bit - ); - - serial_up = TRUE; -} - -#define SER_MASK (IO_MASK(R_SERIAL0_READ, data_avail) | IO_MASK(R_SERIAL0_READ, data_in)) - -int -handle_serial_read(void) -{ - udword status_and_data_in = *R_SERIAL0_READ & SER_MASK; - - if (status_and_data_in & IO_STATE(R_SERIAL0_READ, data_avail, yes)) { - *(char*)(target_address + nbr_read++) = status_and_data_in & 0xff; /* ugly mask */ - last_timeout = REG_GET(R_TIMER0_DATA, count); - return TRUE; - } - - return FALSE; -} - -void -send_serial_ack(void) -{ - while (!REG_EQL(R_SERIAL0_STATUS, tr_ready, ready)) - ; - - REG_ISET(0, R_SERIAL0_TR_DATA, data_out, '+'); -} - -void -send_serial_string(char *str) -{ - int i; - - for (i = 0; str[i];) { - if (REG_IEQL(0, R_SERIAL0_STATUS, tr_ready, ready)) { - REG_ISET(0, R_SERIAL0_TR_DATA, data_out, str[i]); - i++; - } - } -} - -void -send_serial_hex(udword v, byte nl) -{ - int i; - byte buf[13]; - byte nybble; - - buf[0] = '0'; - buf[1] = 'x'; - buf[10] = '\r'; - buf[11] = '\n'; - buf[12] = '\0'; - - if (nl == FALSE) { - buf[10] = '\0'; - } - - for (i = 0; i != 8; i++) { - nybble = (v >> (i*4)) & 0xf; - if (nybble > 9) { - nybble += 7; - } - buf[7-i+2] = nybble + '0'; - } - send_serial_string(buf); -} diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/src/sv_addr.agh b/target/linux/etrax-2.6/image/e100boot/src/cbl/src/sv_addr.agh deleted file mode 100644 index 99c5c691d3..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/cbl/src/sv_addr.agh +++ /dev/null @@ -1,7323 +0,0 @@ -/* -!* This file was automatically generated by /n/asic/bin/reg_macro_gen -!* from the file `/n/asic/projects/etrax_ng/doc/work/etrax_ng_regs.rd', version 1.168. -!* Editing within this file is thus not recommended, -!* make the changes in `/n/asic/projects/etrax_ng/doc/work/etrax_ng_regs.rd' instead. -!* Created: Wed Oct 2 22:32:57 2002 By: Id: reg_macro_gen,v 1.12 2002/09/18 14:08:01 stefanl Exp -!*/ - - -/* -!* Bus interface configuration registers -!*/ - -#define R_WAITSTATES (IO_TYPECAST_UDWORD 0xb0000000) -#define R_WAITSTATES__pcs4_7_zw__BITNR 30 -#define R_WAITSTATES__pcs4_7_zw__WIDTH 2 -#define R_WAITSTATES__pcs4_7_ew__BITNR 28 -#define R_WAITSTATES__pcs4_7_ew__WIDTH 2 -#define R_WAITSTATES__pcs4_7_lw__BITNR 24 -#define R_WAITSTATES__pcs4_7_lw__WIDTH 4 -#define R_WAITSTATES__pcs0_3_zw__BITNR 22 -#define R_WAITSTATES__pcs0_3_zw__WIDTH 2 -#define R_WAITSTATES__pcs0_3_ew__BITNR 20 -#define R_WAITSTATES__pcs0_3_ew__WIDTH 2 -#define R_WAITSTATES__pcs0_3_lw__BITNR 16 -#define R_WAITSTATES__pcs0_3_lw__WIDTH 4 -#define R_WAITSTATES__sram_zw__BITNR 14 -#define R_WAITSTATES__sram_zw__WIDTH 2 -#define R_WAITSTATES__sram_ew__BITNR 12 -#define R_WAITSTATES__sram_ew__WIDTH 2 -#define R_WAITSTATES__sram_lw__BITNR 8 -#define R_WAITSTATES__sram_lw__WIDTH 4 -#define R_WAITSTATES__flash_zw__BITNR 6 -#define R_WAITSTATES__flash_zw__WIDTH 2 -#define R_WAITSTATES__flash_ew__BITNR 4 -#define R_WAITSTATES__flash_ew__WIDTH 2 -#define R_WAITSTATES__flash_lw__BITNR 0 -#define R_WAITSTATES__flash_lw__WIDTH 4 - -#define R_BUS_CONFIG (IO_TYPECAST_UDWORD 0xb0000004) -#define R_BUS_CONFIG__sram_type__BITNR 9 -#define R_BUS_CONFIG__sram_type__WIDTH 1 -#define R_BUS_CONFIG__sram_type__cwe 1 -#define R_BUS_CONFIG__sram_type__bwe 0 -#define R_BUS_CONFIG__dma_burst__BITNR 8 -#define R_BUS_CONFIG__dma_burst__WIDTH 1 -#define R_BUS_CONFIG__dma_burst__burst16 1 -#define R_BUS_CONFIG__dma_burst__burst32 0 -#define R_BUS_CONFIG__pcs4_7_wr__BITNR 7 -#define R_BUS_CONFIG__pcs4_7_wr__WIDTH 1 -#define R_BUS_CONFIG__pcs4_7_wr__ext 1 -#define R_BUS_CONFIG__pcs4_7_wr__norm 0 -#define R_BUS_CONFIG__pcs0_3_wr__BITNR 6 -#define R_BUS_CONFIG__pcs0_3_wr__WIDTH 1 -#define R_BUS_CONFIG__pcs0_3_wr__ext 1 -#define R_BUS_CONFIG__pcs0_3_wr__norm 0 -#define R_BUS_CONFIG__sram_wr__BITNR 5 -#define R_BUS_CONFIG__sram_wr__WIDTH 1 -#define R_BUS_CONFIG__sram_wr__ext 1 -#define R_BUS_CONFIG__sram_wr__norm 0 -#define R_BUS_CONFIG__flash_wr__BITNR 4 -#define R_BUS_CONFIG__flash_wr__WIDTH 1 -#define R_BUS_CONFIG__flash_wr__ext 1 -#define R_BUS_CONFIG__flash_wr__norm 0 -#define R_BUS_CONFIG__pcs4_7_bw__BITNR 3 -#define R_BUS_CONFIG__pcs4_7_bw__WIDTH 1 -#define R_BUS_CONFIG__pcs4_7_bw__bw32 1 -#define R_BUS_CONFIG__pcs4_7_bw__bw16 0 -#define R_BUS_CONFIG__pcs0_3_bw__BITNR 2 -#define R_BUS_CONFIG__pcs0_3_bw__WIDTH 1 -#define R_BUS_CONFIG__pcs0_3_bw__bw32 1 -#define R_BUS_CONFIG__pcs0_3_bw__bw16 0 -#define R_BUS_CONFIG__sram_bw__BITNR 1 -#define R_BUS_CONFIG__sram_bw__WIDTH 1 -#define R_BUS_CONFIG__sram_bw__bw32 1 -#define R_BUS_CONFIG__sram_bw__bw16 0 -#define R_BUS_CONFIG__flash_bw__BITNR 0 -#define R_BUS_CONFIG__flash_bw__WIDTH 1 -#define R_BUS_CONFIG__flash_bw__bw32 1 -#define R_BUS_CONFIG__flash_bw__bw16 0 - -#define R_BUS_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000004) -#define R_BUS_STATUS__pll_lock_tm__BITNR 5 -#define R_BUS_STATUS__pll_lock_tm__WIDTH 1 -#define R_BUS_STATUS__pll_lock_tm__expired 0 -#define R_BUS_STATUS__pll_lock_tm__counting 1 -#define R_BUS_STATUS__both_faults__BITNR 4 -#define R_BUS_STATUS__both_faults__WIDTH 1 -#define R_BUS_STATUS__both_faults__no 0 -#define R_BUS_STATUS__both_faults__yes 1 -#define R_BUS_STATUS__bsen___BITNR 3 -#define R_BUS_STATUS__bsen___WIDTH 1 -#define R_BUS_STATUS__bsen___enable 0 -#define R_BUS_STATUS__bsen___disable 1 -#define R_BUS_STATUS__boot__BITNR 1 -#define R_BUS_STATUS__boot__WIDTH 2 -#define R_BUS_STATUS__boot__uncached 0 -#define R_BUS_STATUS__boot__serial 1 -#define R_BUS_STATUS__boot__network 2 -#define R_BUS_STATUS__boot__parallel 3 -#define R_BUS_STATUS__flashw__BITNR 0 -#define R_BUS_STATUS__flashw__WIDTH 1 -#define R_BUS_STATUS__flashw__bw32 1 -#define R_BUS_STATUS__flashw__bw16 0 - -#define R_DRAM_TIMING (IO_TYPECAST_UDWORD 0xb0000008) -#define R_DRAM_TIMING__sdram__BITNR 31 -#define R_DRAM_TIMING__sdram__WIDTH 1 -#define R_DRAM_TIMING__sdram__enable 1 -#define R_DRAM_TIMING__sdram__disable 0 -#define R_DRAM_TIMING__ref__BITNR 14 -#define R_DRAM_TIMING__ref__WIDTH 2 -#define R_DRAM_TIMING__ref__e52us 0 -#define R_DRAM_TIMING__ref__e13us 1 -#define R_DRAM_TIMING__ref__e8700ns 2 -#define R_DRAM_TIMING__ref__disable 3 -#define R_DRAM_TIMING__rp__BITNR 12 -#define R_DRAM_TIMING__rp__WIDTH 2 -#define R_DRAM_TIMING__rs__BITNR 10 -#define R_DRAM_TIMING__rs__WIDTH 2 -#define R_DRAM_TIMING__rh__BITNR 8 -#define R_DRAM_TIMING__rh__WIDTH 2 -#define R_DRAM_TIMING__w__BITNR 7 -#define R_DRAM_TIMING__w__WIDTH 1 -#define R_DRAM_TIMING__w__norm 0 -#define R_DRAM_TIMING__w__ext 1 -#define R_DRAM_TIMING__c__BITNR 6 -#define R_DRAM_TIMING__c__WIDTH 1 -#define R_DRAM_TIMING__c__norm 0 -#define R_DRAM_TIMING__c__ext 1 -#define R_DRAM_TIMING__cz__BITNR 4 -#define R_DRAM_TIMING__cz__WIDTH 2 -#define R_DRAM_TIMING__cp__BITNR 2 -#define R_DRAM_TIMING__cp__WIDTH 2 -#define R_DRAM_TIMING__cw__BITNR 0 -#define R_DRAM_TIMING__cw__WIDTH 2 - -#define R_SDRAM_TIMING (IO_TYPECAST_UDWORD 0xb0000008) -#define R_SDRAM_TIMING__sdram__BITNR 31 -#define R_SDRAM_TIMING__sdram__WIDTH 1 -#define R_SDRAM_TIMING__sdram__enable 1 -#define R_SDRAM_TIMING__sdram__disable 0 -#define R_SDRAM_TIMING__mrs_data__BITNR 16 -#define R_SDRAM_TIMING__mrs_data__WIDTH 15 -#define R_SDRAM_TIMING__ref__BITNR 14 -#define R_SDRAM_TIMING__ref__WIDTH 2 -#define R_SDRAM_TIMING__ref__e52us 0 -#define R_SDRAM_TIMING__ref__e13us 1 -#define R_SDRAM_TIMING__ref__e6500ns 2 -#define R_SDRAM_TIMING__ref__disable 3 -#define R_SDRAM_TIMING__ddr__BITNR 13 -#define R_SDRAM_TIMING__ddr__WIDTH 1 -#define R_SDRAM_TIMING__ddr__on 1 -#define R_SDRAM_TIMING__ddr__off 0 -#define R_SDRAM_TIMING__clk100__BITNR 12 -#define R_SDRAM_TIMING__clk100__WIDTH 1 -#define R_SDRAM_TIMING__clk100__on 1 -#define R_SDRAM_TIMING__clk100__off 0 -#define R_SDRAM_TIMING__ps__BITNR 11 -#define R_SDRAM_TIMING__ps__WIDTH 1 -#define R_SDRAM_TIMING__ps__on 1 -#define R_SDRAM_TIMING__ps__off 0 -#define R_SDRAM_TIMING__cmd__BITNR 9 -#define R_SDRAM_TIMING__cmd__WIDTH 2 -#define R_SDRAM_TIMING__cmd__pre 3 -#define R_SDRAM_TIMING__cmd__ref 2 -#define R_SDRAM_TIMING__cmd__mrs 1 -#define R_SDRAM_TIMING__cmd__nop 0 -#define R_SDRAM_TIMING__pde__BITNR 8 -#define R_SDRAM_TIMING__pde__WIDTH 1 -#define R_SDRAM_TIMING__rc__BITNR 6 -#define R_SDRAM_TIMING__rc__WIDTH 2 -#define R_SDRAM_TIMING__rp__BITNR 4 -#define R_SDRAM_TIMING__rp__WIDTH 2 -#define R_SDRAM_TIMING__rcd__BITNR 2 -#define R_SDRAM_TIMING__rcd__WIDTH 2 -#define R_SDRAM_TIMING__cl__BITNR 0 -#define R_SDRAM_TIMING__cl__WIDTH 2 - -#define R_DRAM_CONFIG (IO_TYPECAST_UDWORD 0xb000000c) -#define R_DRAM_CONFIG__wmm1__BITNR 31 -#define R_DRAM_CONFIG__wmm1__WIDTH 1 -#define R_DRAM_CONFIG__wmm1__wmm 1 -#define R_DRAM_CONFIG__wmm1__norm 0 -#define R_DRAM_CONFIG__wmm0__BITNR 30 -#define R_DRAM_CONFIG__wmm0__WIDTH 1 -#define R_DRAM_CONFIG__wmm0__wmm 1 -#define R_DRAM_CONFIG__wmm0__norm 0 -#define R_DRAM_CONFIG__sh1__BITNR 27 -#define R_DRAM_CONFIG__sh1__WIDTH 3 -#define R_DRAM_CONFIG__sh0__BITNR 24 -#define R_DRAM_CONFIG__sh0__WIDTH 3 -#define R_DRAM_CONFIG__w__BITNR 23 -#define R_DRAM_CONFIG__w__WIDTH 1 -#define R_DRAM_CONFIG__w__bw16 0 -#define R_DRAM_CONFIG__w__bw32 1 -#define R_DRAM_CONFIG__c__BITNR 22 -#define R_DRAM_CONFIG__c__WIDTH 1 -#define R_DRAM_CONFIG__c__byte 0 -#define R_DRAM_CONFIG__c__bank 1 -#define R_DRAM_CONFIG__e__BITNR 21 -#define R_DRAM_CONFIG__e__WIDTH 1 -#define R_DRAM_CONFIG__e__fast 0 -#define R_DRAM_CONFIG__e__edo 1 -#define R_DRAM_CONFIG__group_sel__BITNR 16 -#define R_DRAM_CONFIG__group_sel__WIDTH 5 -#define R_DRAM_CONFIG__group_sel__grp0 0 -#define R_DRAM_CONFIG__group_sel__grp1 1 -#define R_DRAM_CONFIG__group_sel__bit9 9 -#define R_DRAM_CONFIG__group_sel__bit10 10 -#define R_DRAM_CONFIG__group_sel__bit11 11 -#define R_DRAM_CONFIG__group_sel__bit12 12 -#define R_DRAM_CONFIG__group_sel__bit13 13 -#define R_DRAM_CONFIG__group_sel__bit14 14 -#define R_DRAM_CONFIG__group_sel__bit15 15 -#define R_DRAM_CONFIG__group_sel__bit16 16 -#define R_DRAM_CONFIG__group_sel__bit17 17 -#define R_DRAM_CONFIG__group_sel__bit18 18 -#define R_DRAM_CONFIG__group_sel__bit19 19 -#define R_DRAM_CONFIG__group_sel__bit20 20 -#define R_DRAM_CONFIG__group_sel__bit21 21 -#define R_DRAM_CONFIG__group_sel__bit22 22 -#define R_DRAM_CONFIG__group_sel__bit23 23 -#define R_DRAM_CONFIG__group_sel__bit24 24 -#define R_DRAM_CONFIG__group_sel__bit25 25 -#define R_DRAM_CONFIG__group_sel__bit26 26 -#define R_DRAM_CONFIG__group_sel__bit27 27 -#define R_DRAM_CONFIG__group_sel__bit28 28 -#define R_DRAM_CONFIG__group_sel__bit29 29 -#define R_DRAM_CONFIG__ca1__BITNR 13 -#define R_DRAM_CONFIG__ca1__WIDTH 3 -#define R_DRAM_CONFIG__bank23sel__BITNR 8 -#define R_DRAM_CONFIG__bank23sel__WIDTH 5 -#define R_DRAM_CONFIG__bank23sel__bank0 0 -#define R_DRAM_CONFIG__bank23sel__bank1 1 -#define R_DRAM_CONFIG__bank23sel__bit9 9 -#define R_DRAM_CONFIG__bank23sel__bit10 10 -#define R_DRAM_CONFIG__bank23sel__bit11 11 -#define R_DRAM_CONFIG__bank23sel__bit12 12 -#define R_DRAM_CONFIG__bank23sel__bit13 13 -#define R_DRAM_CONFIG__bank23sel__bit14 14 -#define R_DRAM_CONFIG__bank23sel__bit15 15 -#define R_DRAM_CONFIG__bank23sel__bit16 16 -#define R_DRAM_CONFIG__bank23sel__bit17 17 -#define R_DRAM_CONFIG__bank23sel__bit18 18 -#define R_DRAM_CONFIG__bank23sel__bit19 19 -#define R_DRAM_CONFIG__bank23sel__bit20 20 -#define R_DRAM_CONFIG__bank23sel__bit21 21 -#define R_DRAM_CONFIG__bank23sel__bit22 22 -#define R_DRAM_CONFIG__bank23sel__bit23 23 -#define R_DRAM_CONFIG__bank23sel__bit24 24 -#define R_DRAM_CONFIG__bank23sel__bit25 25 -#define R_DRAM_CONFIG__bank23sel__bit26 26 -#define R_DRAM_CONFIG__bank23sel__bit27 27 -#define R_DRAM_CONFIG__bank23sel__bit28 28 -#define R_DRAM_CONFIG__bank23sel__bit29 29 -#define R_DRAM_CONFIG__ca0__BITNR 5 -#define R_DRAM_CONFIG__ca0__WIDTH 3 -#define R_DRAM_CONFIG__bank01sel__BITNR 0 -#define R_DRAM_CONFIG__bank01sel__WIDTH 5 -#define R_DRAM_CONFIG__bank01sel__bank0 0 -#define R_DRAM_CONFIG__bank01sel__bank1 1 -#define R_DRAM_CONFIG__bank01sel__bit9 9 -#define R_DRAM_CONFIG__bank01sel__bit10 10 -#define R_DRAM_CONFIG__bank01sel__bit11 11 -#define R_DRAM_CONFIG__bank01sel__bit12 12 -#define R_DRAM_CONFIG__bank01sel__bit13 13 -#define R_DRAM_CONFIG__bank01sel__bit14 14 -#define R_DRAM_CONFIG__bank01sel__bit15 15 -#define R_DRAM_CONFIG__bank01sel__bit16 16 -#define R_DRAM_CONFIG__bank01sel__bit17 17 -#define R_DRAM_CONFIG__bank01sel__bit18 18 -#define R_DRAM_CONFIG__bank01sel__bit19 19 -#define R_DRAM_CONFIG__bank01sel__bit20 20 -#define R_DRAM_CONFIG__bank01sel__bit21 21 -#define R_DRAM_CONFIG__bank01sel__bit22 22 -#define R_DRAM_CONFIG__bank01sel__bit23 23 -#define R_DRAM_CONFIG__bank01sel__bit24 24 -#define R_DRAM_CONFIG__bank01sel__bit25 25 -#define R_DRAM_CONFIG__bank01sel__bit26 26 -#define R_DRAM_CONFIG__bank01sel__bit27 27 -#define R_DRAM_CONFIG__bank01sel__bit28 28 -#define R_DRAM_CONFIG__bank01sel__bit29 29 - -#define R_SDRAM_CONFIG (IO_TYPECAST_UDWORD 0xb000000c) -#define R_SDRAM_CONFIG__wmm1__BITNR 31 -#define R_SDRAM_CONFIG__wmm1__WIDTH 1 -#define R_SDRAM_CONFIG__wmm1__wmm 1 -#define R_SDRAM_CONFIG__wmm1__norm 0 -#define R_SDRAM_CONFIG__wmm0__BITNR 30 -#define R_SDRAM_CONFIG__wmm0__WIDTH 1 -#define R_SDRAM_CONFIG__wmm0__wmm 1 -#define R_SDRAM_CONFIG__wmm0__norm 0 -#define R_SDRAM_CONFIG__sh1__BITNR 27 -#define R_SDRAM_CONFIG__sh1__WIDTH 3 -#define R_SDRAM_CONFIG__sh0__BITNR 24 -#define R_SDRAM_CONFIG__sh0__WIDTH 3 -#define R_SDRAM_CONFIG__w__BITNR 23 -#define R_SDRAM_CONFIG__w__WIDTH 1 -#define R_SDRAM_CONFIG__w__bw16 0 -#define R_SDRAM_CONFIG__w__bw32 1 -#define R_SDRAM_CONFIG__type1__BITNR 22 -#define R_SDRAM_CONFIG__type1__WIDTH 1 -#define R_SDRAM_CONFIG__type1__bank2 0 -#define R_SDRAM_CONFIG__type1__bank4 1 -#define R_SDRAM_CONFIG__type0__BITNR 21 -#define R_SDRAM_CONFIG__type0__WIDTH 1 -#define R_SDRAM_CONFIG__type0__bank2 0 -#define R_SDRAM_CONFIG__type0__bank4 1 -#define R_SDRAM_CONFIG__group_sel__BITNR 16 -#define R_SDRAM_CONFIG__group_sel__WIDTH 5 -#define R_SDRAM_CONFIG__group_sel__grp0 0 -#define R_SDRAM_CONFIG__group_sel__grp1 1 -#define R_SDRAM_CONFIG__group_sel__bit9 9 -#define R_SDRAM_CONFIG__group_sel__bit10 10 -#define R_SDRAM_CONFIG__group_sel__bit11 11 -#define R_SDRAM_CONFIG__group_sel__bit12 12 -#define R_SDRAM_CONFIG__group_sel__bit13 13 -#define R_SDRAM_CONFIG__group_sel__bit14 14 -#define R_SDRAM_CONFIG__group_sel__bit15 15 -#define R_SDRAM_CONFIG__group_sel__bit16 16 -#define R_SDRAM_CONFIG__group_sel__bit17 17 -#define R_SDRAM_CONFIG__group_sel__bit18 18 -#define R_SDRAM_CONFIG__group_sel__bit19 19 -#define R_SDRAM_CONFIG__group_sel__bit20 20 -#define R_SDRAM_CONFIG__group_sel__bit21 21 -#define R_SDRAM_CONFIG__group_sel__bit22 22 -#define R_SDRAM_CONFIG__group_sel__bit23 23 -#define R_SDRAM_CONFIG__group_sel__bit24 24 -#define R_SDRAM_CONFIG__group_sel__bit25 25 -#define R_SDRAM_CONFIG__group_sel__bit26 26 -#define R_SDRAM_CONFIG__group_sel__bit27 27 -#define R_SDRAM_CONFIG__group_sel__bit28 28 -#define R_SDRAM_CONFIG__group_sel__bit29 29 -#define R_SDRAM_CONFIG__ca1__BITNR 13 -#define R_SDRAM_CONFIG__ca1__WIDTH 3 -#define R_SDRAM_CONFIG__bank_sel1__BITNR 8 -#define R_SDRAM_CONFIG__bank_sel1__WIDTH 5 -#define R_SDRAM_CONFIG__bank_sel1__bit9 9 -#define R_SDRAM_CONFIG__bank_sel1__bit10 10 -#define R_SDRAM_CONFIG__bank_sel1__bit11 11 -#define R_SDRAM_CONFIG__bank_sel1__bit12 12 -#define R_SDRAM_CONFIG__bank_sel1__bit13 13 -#define R_SDRAM_CONFIG__bank_sel1__bit14 14 -#define R_SDRAM_CONFIG__bank_sel1__bit15 15 -#define R_SDRAM_CONFIG__bank_sel1__bit16 16 -#define R_SDRAM_CONFIG__bank_sel1__bit17 17 -#define R_SDRAM_CONFIG__bank_sel1__bit18 18 -#define R_SDRAM_CONFIG__bank_sel1__bit19 19 -#define R_SDRAM_CONFIG__bank_sel1__bit20 20 -#define R_SDRAM_CONFIG__bank_sel1__bit21 21 -#define R_SDRAM_CONFIG__bank_sel1__bit22 22 -#define R_SDRAM_CONFIG__bank_sel1__bit23 23 -#define R_SDRAM_CONFIG__bank_sel1__bit24 24 -#define R_SDRAM_CONFIG__bank_sel1__bit25 25 -#define R_SDRAM_CONFIG__bank_sel1__bit26 26 -#define R_SDRAM_CONFIG__bank_sel1__bit27 27 -#define R_SDRAM_CONFIG__bank_sel1__bit28 28 -#define R_SDRAM_CONFIG__bank_sel1__bit29 29 -#define R_SDRAM_CONFIG__ca0__BITNR 5 -#define R_SDRAM_CONFIG__ca0__WIDTH 3 -#define R_SDRAM_CONFIG__bank_sel0__BITNR 0 -#define R_SDRAM_CONFIG__bank_sel0__WIDTH 5 -#define R_SDRAM_CONFIG__bank_sel0__bit9 9 -#define R_SDRAM_CONFIG__bank_sel0__bit10 10 -#define R_SDRAM_CONFIG__bank_sel0__bit11 11 -#define R_SDRAM_CONFIG__bank_sel0__bit12 12 -#define R_SDRAM_CONFIG__bank_sel0__bit13 13 -#define R_SDRAM_CONFIG__bank_sel0__bit14 14 -#define R_SDRAM_CONFIG__bank_sel0__bit15 15 -#define R_SDRAM_CONFIG__bank_sel0__bit16 16 -#define R_SDRAM_CONFIG__bank_sel0__bit17 17 -#define R_SDRAM_CONFIG__bank_sel0__bit18 18 -#define R_SDRAM_CONFIG__bank_sel0__bit19 19 -#define R_SDRAM_CONFIG__bank_sel0__bit20 20 -#define R_SDRAM_CONFIG__bank_sel0__bit21 21 -#define R_SDRAM_CONFIG__bank_sel0__bit22 22 -#define R_SDRAM_CONFIG__bank_sel0__bit23 23 -#define R_SDRAM_CONFIG__bank_sel0__bit24 24 -#define R_SDRAM_CONFIG__bank_sel0__bit25 25 -#define R_SDRAM_CONFIG__bank_sel0__bit26 26 -#define R_SDRAM_CONFIG__bank_sel0__bit27 27 -#define R_SDRAM_CONFIG__bank_sel0__bit28 28 -#define R_SDRAM_CONFIG__bank_sel0__bit29 29 - -/* -!* External DMA registers -!*/ - -#define R_EXT_DMA_0_CMD (IO_TYPECAST_UDWORD 0xb0000010) -#define R_EXT_DMA_0_CMD__cnt__BITNR 23 -#define R_EXT_DMA_0_CMD__cnt__WIDTH 1 -#define R_EXT_DMA_0_CMD__cnt__enable 1 -#define R_EXT_DMA_0_CMD__cnt__disable 0 -#define R_EXT_DMA_0_CMD__rqpol__BITNR 22 -#define R_EXT_DMA_0_CMD__rqpol__WIDTH 1 -#define R_EXT_DMA_0_CMD__rqpol__ahigh 0 -#define R_EXT_DMA_0_CMD__rqpol__alow 1 -#define R_EXT_DMA_0_CMD__apol__BITNR 21 -#define R_EXT_DMA_0_CMD__apol__WIDTH 1 -#define R_EXT_DMA_0_CMD__apol__ahigh 0 -#define R_EXT_DMA_0_CMD__apol__alow 1 -#define R_EXT_DMA_0_CMD__rq_ack__BITNR 20 -#define R_EXT_DMA_0_CMD__rq_ack__WIDTH 1 -#define R_EXT_DMA_0_CMD__rq_ack__burst 0 -#define R_EXT_DMA_0_CMD__rq_ack__handsh 1 -#define R_EXT_DMA_0_CMD__wid__BITNR 18 -#define R_EXT_DMA_0_CMD__wid__WIDTH 2 -#define R_EXT_DMA_0_CMD__wid__byte 0 -#define R_EXT_DMA_0_CMD__wid__word 1 -#define R_EXT_DMA_0_CMD__wid__dword 2 -#define R_EXT_DMA_0_CMD__dir__BITNR 17 -#define R_EXT_DMA_0_CMD__dir__WIDTH 1 -#define R_EXT_DMA_0_CMD__dir__input 0 -#define R_EXT_DMA_0_CMD__dir__output 1 -#define R_EXT_DMA_0_CMD__run__BITNR 16 -#define R_EXT_DMA_0_CMD__run__WIDTH 1 -#define R_EXT_DMA_0_CMD__run__start 1 -#define R_EXT_DMA_0_CMD__run__stop 0 -#define R_EXT_DMA_0_CMD__trf_count__BITNR 0 -#define R_EXT_DMA_0_CMD__trf_count__WIDTH 16 - -#define R_EXT_DMA_0_STAT (IO_TYPECAST_RO_UDWORD 0xb0000010) -#define R_EXT_DMA_0_STAT__run__BITNR 16 -#define R_EXT_DMA_0_STAT__run__WIDTH 1 -#define R_EXT_DMA_0_STAT__run__start 1 -#define R_EXT_DMA_0_STAT__run__stop 0 -#define R_EXT_DMA_0_STAT__trf_count__BITNR 0 -#define R_EXT_DMA_0_STAT__trf_count__WIDTH 16 - -#define R_EXT_DMA_0_ADDR (IO_TYPECAST_UDWORD 0xb0000014) -#define R_EXT_DMA_0_ADDR__ext0_addr__BITNR 2 -#define R_EXT_DMA_0_ADDR__ext0_addr__WIDTH 28 - -#define R_EXT_DMA_1_CMD (IO_TYPECAST_UDWORD 0xb0000018) -#define R_EXT_DMA_1_CMD__cnt__BITNR 23 -#define R_EXT_DMA_1_CMD__cnt__WIDTH 1 -#define R_EXT_DMA_1_CMD__cnt__enable 1 -#define R_EXT_DMA_1_CMD__cnt__disable 0 -#define R_EXT_DMA_1_CMD__rqpol__BITNR 22 -#define R_EXT_DMA_1_CMD__rqpol__WIDTH 1 -#define R_EXT_DMA_1_CMD__rqpol__ahigh 0 -#define R_EXT_DMA_1_CMD__rqpol__alow 1 -#define R_EXT_DMA_1_CMD__apol__BITNR 21 -#define R_EXT_DMA_1_CMD__apol__WIDTH 1 -#define R_EXT_DMA_1_CMD__apol__ahigh 0 -#define R_EXT_DMA_1_CMD__apol__alow 1 -#define R_EXT_DMA_1_CMD__rq_ack__BITNR 20 -#define R_EXT_DMA_1_CMD__rq_ack__WIDTH 1 -#define R_EXT_DMA_1_CMD__rq_ack__burst 0 -#define R_EXT_DMA_1_CMD__rq_ack__handsh 1 -#define R_EXT_DMA_1_CMD__wid__BITNR 18 -#define R_EXT_DMA_1_CMD__wid__WIDTH 2 -#define R_EXT_DMA_1_CMD__wid__byte 0 -#define R_EXT_DMA_1_CMD__wid__word 1 -#define R_EXT_DMA_1_CMD__wid__dword 2 -#define R_EXT_DMA_1_CMD__dir__BITNR 17 -#define R_EXT_DMA_1_CMD__dir__WIDTH 1 -#define R_EXT_DMA_1_CMD__dir__input 0 -#define R_EXT_DMA_1_CMD__dir__output 1 -#define R_EXT_DMA_1_CMD__run__BITNR 16 -#define R_EXT_DMA_1_CMD__run__WIDTH 1 -#define R_EXT_DMA_1_CMD__run__start 1 -#define R_EXT_DMA_1_CMD__run__stop 0 -#define R_EXT_DMA_1_CMD__trf_count__BITNR 0 -#define R_EXT_DMA_1_CMD__trf_count__WIDTH 16 - -#define R_EXT_DMA_1_STAT (IO_TYPECAST_RO_UDWORD 0xb0000018) -#define R_EXT_DMA_1_STAT__run__BITNR 16 -#define R_EXT_DMA_1_STAT__run__WIDTH 1 -#define R_EXT_DMA_1_STAT__run__start 1 -#define R_EXT_DMA_1_STAT__run__stop 0 -#define R_EXT_DMA_1_STAT__trf_count__BITNR 0 -#define R_EXT_DMA_1_STAT__trf_count__WIDTH 16 - -#define R_EXT_DMA_1_ADDR (IO_TYPECAST_UDWORD 0xb000001c) -#define R_EXT_DMA_1_ADDR__ext0_addr__BITNR 2 -#define R_EXT_DMA_1_ADDR__ext0_addr__WIDTH 28 - -/* -!* Timer registers -!*/ - -#define R_TIMER_CTRL (IO_TYPECAST_UDWORD 0xb0000020) -#define R_TIMER_CTRL__timerdiv1__BITNR 24 -#define R_TIMER_CTRL__timerdiv1__WIDTH 8 -#define R_TIMER_CTRL__timerdiv0__BITNR 16 -#define R_TIMER_CTRL__timerdiv0__WIDTH 8 -#define R_TIMER_CTRL__presc_timer1__BITNR 15 -#define R_TIMER_CTRL__presc_timer1__WIDTH 1 -#define R_TIMER_CTRL__presc_timer1__normal 0 -#define R_TIMER_CTRL__presc_timer1__prescale 1 -#define R_TIMER_CTRL__i1__BITNR 14 -#define R_TIMER_CTRL__i1__WIDTH 1 -#define R_TIMER_CTRL__i1__clr 1 -#define R_TIMER_CTRL__i1__nop 0 -#define R_TIMER_CTRL__tm1__BITNR 12 -#define R_TIMER_CTRL__tm1__WIDTH 2 -#define R_TIMER_CTRL__tm1__stop_ld 0 -#define R_TIMER_CTRL__tm1__freeze 1 -#define R_TIMER_CTRL__tm1__run 2 -#define R_TIMER_CTRL__tm1__reserved 3 -#define R_TIMER_CTRL__clksel1__BITNR 8 -#define R_TIMER_CTRL__clksel1__WIDTH 4 -#define R_TIMER_CTRL__clksel1__c300Hz 0 -#define R_TIMER_CTRL__clksel1__c600Hz 1 -#define R_TIMER_CTRL__clksel1__c1200Hz 2 -#define R_TIMER_CTRL__clksel1__c2400Hz 3 -#define R_TIMER_CTRL__clksel1__c4800Hz 4 -#define R_TIMER_CTRL__clksel1__c9600Hz 5 -#define R_TIMER_CTRL__clksel1__c19k2Hz 6 -#define R_TIMER_CTRL__clksel1__c38k4Hz 7 -#define R_TIMER_CTRL__clksel1__c57k6Hz 8 -#define R_TIMER_CTRL__clksel1__c115k2Hz 9 -#define R_TIMER_CTRL__clksel1__c230k4Hz 10 -#define R_TIMER_CTRL__clksel1__c460k8Hz 11 -#define R_TIMER_CTRL__clksel1__c921k6Hz 12 -#define R_TIMER_CTRL__clksel1__c1843k2Hz 13 -#define R_TIMER_CTRL__clksel1__c6250kHz 14 -#define R_TIMER_CTRL__clksel1__cascade0 15 -#define R_TIMER_CTRL__presc_ext__BITNR 7 -#define R_TIMER_CTRL__presc_ext__WIDTH 1 -#define R_TIMER_CTRL__presc_ext__prescale 0 -#define R_TIMER_CTRL__presc_ext__external 1 -#define R_TIMER_CTRL__i0__BITNR 6 -#define R_TIMER_CTRL__i0__WIDTH 1 -#define R_TIMER_CTRL__i0__clr 1 -#define R_TIMER_CTRL__i0__nop 0 -#define R_TIMER_CTRL__tm0__BITNR 4 -#define R_TIMER_CTRL__tm0__WIDTH 2 -#define R_TIMER_CTRL__tm0__stop_ld 0 -#define R_TIMER_CTRL__tm0__freeze 1 -#define R_TIMER_CTRL__tm0__run 2 -#define R_TIMER_CTRL__tm0__reserved 3 -#define R_TIMER_CTRL__clksel0__BITNR 0 -#define R_TIMER_CTRL__clksel0__WIDTH 4 -#define R_TIMER_CTRL__clksel0__c300Hz 0 -#define R_TIMER_CTRL__clksel0__c600Hz 1 -#define R_TIMER_CTRL__clksel0__c1200Hz 2 -#define R_TIMER_CTRL__clksel0__c2400Hz 3 -#define R_TIMER_CTRL__clksel0__c4800Hz 4 -#define R_TIMER_CTRL__clksel0__c9600Hz 5 -#define R_TIMER_CTRL__clksel0__c19k2Hz 6 -#define R_TIMER_CTRL__clksel0__c38k4Hz 7 -#define R_TIMER_CTRL__clksel0__c57k6Hz 8 -#define R_TIMER_CTRL__clksel0__c115k2Hz 9 -#define R_TIMER_CTRL__clksel0__c230k4Hz 10 -#define R_TIMER_CTRL__clksel0__c460k8Hz 11 -#define R_TIMER_CTRL__clksel0__c921k6Hz 12 -#define R_TIMER_CTRL__clksel0__c1843k2Hz 13 -#define R_TIMER_CTRL__clksel0__c6250kHz 14 -#define R_TIMER_CTRL__clksel0__flexible 15 - -#define R_TIMER_DATA (IO_TYPECAST_RO_UDWORD 0xb0000020) -#define R_TIMER_DATA__timer1__BITNR 24 -#define R_TIMER_DATA__timer1__WIDTH 8 -#define R_TIMER_DATA__timer0__BITNR 16 -#define R_TIMER_DATA__timer0__WIDTH 8 -#define R_TIMER_DATA__clkdiv_high__BITNR 8 -#define R_TIMER_DATA__clkdiv_high__WIDTH 8 -#define R_TIMER_DATA__clkdiv_low__BITNR 0 -#define R_TIMER_DATA__clkdiv_low__WIDTH 8 - -#define R_TIMER01_DATA (IO_TYPECAST_RO_UWORD 0xb0000022) -#define R_TIMER01_DATA__count__BITNR 0 -#define R_TIMER01_DATA__count__WIDTH 16 - -#define R_TIMER0_DATA (IO_TYPECAST_RO_BYTE 0xb0000022) -#define R_TIMER0_DATA__count__BITNR 0 -#define R_TIMER0_DATA__count__WIDTH 8 - -#define R_TIMER1_DATA (IO_TYPECAST_RO_BYTE 0xb0000023) -#define R_TIMER1_DATA__count__BITNR 0 -#define R_TIMER1_DATA__count__WIDTH 8 - -#define R_WATCHDOG (IO_TYPECAST_UDWORD 0xb0000024) -#define R_WATCHDOG__key__BITNR 1 -#define R_WATCHDOG__key__WIDTH 3 -#define R_WATCHDOG__enable__BITNR 0 -#define R_WATCHDOG__enable__WIDTH 1 -#define R_WATCHDOG__enable__stop 0 -#define R_WATCHDOG__enable__start 1 - -#define R_CLOCK_PRESCALE (IO_TYPECAST_UDWORD 0xb00000f0) -#define R_CLOCK_PRESCALE__ser_presc__BITNR 16 -#define R_CLOCK_PRESCALE__ser_presc__WIDTH 16 -#define R_CLOCK_PRESCALE__tim_presc__BITNR 0 -#define R_CLOCK_PRESCALE__tim_presc__WIDTH 16 - -#define R_SERIAL_PRESCALE (IO_TYPECAST_UWORD 0xb00000f2) -#define R_SERIAL_PRESCALE__ser_presc__BITNR 0 -#define R_SERIAL_PRESCALE__ser_presc__WIDTH 16 - -#define R_TIMER_PRESCALE (IO_TYPECAST_UWORD 0xb00000f0) -#define R_TIMER_PRESCALE__tim_presc__BITNR 0 -#define R_TIMER_PRESCALE__tim_presc__WIDTH 16 - -#define R_PRESCALE_STATUS (IO_TYPECAST_RO_UDWORD 0xb00000f0) -#define R_PRESCALE_STATUS__ser_status__BITNR 16 -#define R_PRESCALE_STATUS__ser_status__WIDTH 16 -#define R_PRESCALE_STATUS__tim_status__BITNR 0 -#define R_PRESCALE_STATUS__tim_status__WIDTH 16 - -#define R_SER_PRESC_STATUS (IO_TYPECAST_RO_UWORD 0xb00000f2) -#define R_SER_PRESC_STATUS__ser_status__BITNR 0 -#define R_SER_PRESC_STATUS__ser_status__WIDTH 16 - -#define R_TIM_PRESC_STATUS (IO_TYPECAST_RO_UWORD 0xb00000f0) -#define R_TIM_PRESC_STATUS__tim_status__BITNR 0 -#define R_TIM_PRESC_STATUS__tim_status__WIDTH 16 - -#define R_SYNC_SERIAL_PRESCALE (IO_TYPECAST_UDWORD 0xb00000f4) -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__BITNR 23 -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__WIDTH 1 -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__codec 0 -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__baudrate 1 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__BITNR 22 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__WIDTH 1 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__external 0 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__internal 1 -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__BITNR 21 -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__WIDTH 1 -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__codec 0 -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__baudrate 1 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__BITNR 20 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__WIDTH 1 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__external 0 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__internal 1 -#define R_SYNC_SERIAL_PRESCALE__prescaler__BITNR 16 -#define R_SYNC_SERIAL_PRESCALE__prescaler__WIDTH 3 -#define R_SYNC_SERIAL_PRESCALE__prescaler__div1 0 -#define R_SYNC_SERIAL_PRESCALE__prescaler__div2 1 -#define R_SYNC_SERIAL_PRESCALE__prescaler__div4 2 -#define R_SYNC_SERIAL_PRESCALE__prescaler__div8 3 -#define R_SYNC_SERIAL_PRESCALE__prescaler__div16 4 -#define R_SYNC_SERIAL_PRESCALE__prescaler__div32 5 -#define R_SYNC_SERIAL_PRESCALE__prescaler__div64 6 -#define R_SYNC_SERIAL_PRESCALE__prescaler__div128 7 -#define R_SYNC_SERIAL_PRESCALE__warp_mode__BITNR 15 -#define R_SYNC_SERIAL_PRESCALE__warp_mode__WIDTH 1 -#define R_SYNC_SERIAL_PRESCALE__warp_mode__normal 0 -#define R_SYNC_SERIAL_PRESCALE__warp_mode__enabled 1 -#define R_SYNC_SERIAL_PRESCALE__frame_rate__BITNR 11 -#define R_SYNC_SERIAL_PRESCALE__frame_rate__WIDTH 4 -#define R_SYNC_SERIAL_PRESCALE__word_rate__BITNR 0 -#define R_SYNC_SERIAL_PRESCALE__word_rate__WIDTH 10 - -/* -!* Shared RAM interface registers -!*/ - -#define R_SHARED_RAM_CONFIG (IO_TYPECAST_UDWORD 0xb0000040) -#define R_SHARED_RAM_CONFIG__width__BITNR 3 -#define R_SHARED_RAM_CONFIG__width__WIDTH 1 -#define R_SHARED_RAM_CONFIG__width__byte 0 -#define R_SHARED_RAM_CONFIG__width__word 1 -#define R_SHARED_RAM_CONFIG__enable__BITNR 2 -#define R_SHARED_RAM_CONFIG__enable__WIDTH 1 -#define R_SHARED_RAM_CONFIG__enable__yes 1 -#define R_SHARED_RAM_CONFIG__enable__no 0 -#define R_SHARED_RAM_CONFIG__pint__BITNR 1 -#define R_SHARED_RAM_CONFIG__pint__WIDTH 1 -#define R_SHARED_RAM_CONFIG__pint__int 1 -#define R_SHARED_RAM_CONFIG__pint__nop 0 -#define R_SHARED_RAM_CONFIG__clri__BITNR 0 -#define R_SHARED_RAM_CONFIG__clri__WIDTH 1 -#define R_SHARED_RAM_CONFIG__clri__clr 1 -#define R_SHARED_RAM_CONFIG__clri__nop 0 - -#define R_SHARED_RAM_ADDR (IO_TYPECAST_UDWORD 0xb0000044) -#define R_SHARED_RAM_ADDR__base_addr__BITNR 8 -#define R_SHARED_RAM_ADDR__base_addr__WIDTH 22 - -/* -!* General config registers -!*/ - -#define R_GEN_CONFIG (IO_TYPECAST_UDWORD 0xb000002c) -#define R_GEN_CONFIG__par_w__BITNR 31 -#define R_GEN_CONFIG__par_w__WIDTH 1 -#define R_GEN_CONFIG__par_w__select 1 -#define R_GEN_CONFIG__par_w__disable 0 -#define R_GEN_CONFIG__usb2__BITNR 30 -#define R_GEN_CONFIG__usb2__WIDTH 1 -#define R_GEN_CONFIG__usb2__select 1 -#define R_GEN_CONFIG__usb2__disable 0 -#define R_GEN_CONFIG__usb1__BITNR 29 -#define R_GEN_CONFIG__usb1__WIDTH 1 -#define R_GEN_CONFIG__usb1__select 1 -#define R_GEN_CONFIG__usb1__disable 0 -#define R_GEN_CONFIG__g24dir__BITNR 27 -#define R_GEN_CONFIG__g24dir__WIDTH 1 -#define R_GEN_CONFIG__g24dir__in 0 -#define R_GEN_CONFIG__g24dir__out 1 -#define R_GEN_CONFIG__g16_23dir__BITNR 26 -#define R_GEN_CONFIG__g16_23dir__WIDTH 1 -#define R_GEN_CONFIG__g16_23dir__in 0 -#define R_GEN_CONFIG__g16_23dir__out 1 -#define R_GEN_CONFIG__g16_20dir__BITNR 26 -#define R_GEN_CONFIG__g16_20dir__WIDTH 1 -#define R_GEN_CONFIG__g16_20dir__in 0 -#define R_GEN_CONFIG__g16_20dir__out 1 -#define R_GEN_CONFIG__g8_15dir__BITNR 25 -#define R_GEN_CONFIG__g8_15dir__WIDTH 1 -#define R_GEN_CONFIG__g8_15dir__in 0 -#define R_GEN_CONFIG__g8_15dir__out 1 -#define R_GEN_CONFIG__g0dir__BITNR 24 -#define R_GEN_CONFIG__g0dir__WIDTH 1 -#define R_GEN_CONFIG__g0dir__in 0 -#define R_GEN_CONFIG__g0dir__out 1 -#define R_GEN_CONFIG__dma9__BITNR 23 -#define R_GEN_CONFIG__dma9__WIDTH 1 -#define R_GEN_CONFIG__dma9__usb 0 -#define R_GEN_CONFIG__dma9__serial1 1 -#define R_GEN_CONFIG__dma8__BITNR 22 -#define R_GEN_CONFIG__dma8__WIDTH 1 -#define R_GEN_CONFIG__dma8__usb 0 -#define R_GEN_CONFIG__dma8__serial1 1 -#define R_GEN_CONFIG__dma7__BITNR 20 -#define R_GEN_CONFIG__dma7__WIDTH 2 -#define R_GEN_CONFIG__dma7__unused 0 -#define R_GEN_CONFIG__dma7__serial0 1 -#define R_GEN_CONFIG__dma7__extdma1 2 -#define R_GEN_CONFIG__dma7__intdma6 3 -#define R_GEN_CONFIG__dma6__BITNR 18 -#define R_GEN_CONFIG__dma6__WIDTH 2 -#define R_GEN_CONFIG__dma6__unused 0 -#define R_GEN_CONFIG__dma6__serial0 1 -#define R_GEN_CONFIG__dma6__extdma1 2 -#define R_GEN_CONFIG__dma6__intdma7 3 -#define R_GEN_CONFIG__dma5__BITNR 16 -#define R_GEN_CONFIG__dma5__WIDTH 2 -#define R_GEN_CONFIG__dma5__par1 0 -#define R_GEN_CONFIG__dma5__scsi1 1 -#define R_GEN_CONFIG__dma5__serial3 2 -#define R_GEN_CONFIG__dma5__extdma0 3 -#define R_GEN_CONFIG__dma4__BITNR 14 -#define R_GEN_CONFIG__dma4__WIDTH 2 -#define R_GEN_CONFIG__dma4__par1 0 -#define R_GEN_CONFIG__dma4__scsi1 1 -#define R_GEN_CONFIG__dma4__serial3 2 -#define R_GEN_CONFIG__dma4__extdma0 3 -#define R_GEN_CONFIG__dma3__BITNR 12 -#define R_GEN_CONFIG__dma3__WIDTH 2 -#define R_GEN_CONFIG__dma3__par0 0 -#define R_GEN_CONFIG__dma3__scsi0 1 -#define R_GEN_CONFIG__dma3__serial2 2 -#define R_GEN_CONFIG__dma3__ata 3 -#define R_GEN_CONFIG__dma2__BITNR 10 -#define R_GEN_CONFIG__dma2__WIDTH 2 -#define R_GEN_CONFIG__dma2__par0 0 -#define R_GEN_CONFIG__dma2__scsi0 1 -#define R_GEN_CONFIG__dma2__serial2 2 -#define R_GEN_CONFIG__dma2__ata 3 -#define R_GEN_CONFIG__mio_w__BITNR 9 -#define R_GEN_CONFIG__mio_w__WIDTH 1 -#define R_GEN_CONFIG__mio_w__select 1 -#define R_GEN_CONFIG__mio_w__disable 0 -#define R_GEN_CONFIG__ser3__BITNR 8 -#define R_GEN_CONFIG__ser3__WIDTH 1 -#define R_GEN_CONFIG__ser3__select 1 -#define R_GEN_CONFIG__ser3__disable 0 -#define R_GEN_CONFIG__par1__BITNR 7 -#define R_GEN_CONFIG__par1__WIDTH 1 -#define R_GEN_CONFIG__par1__select 1 -#define R_GEN_CONFIG__par1__disable 0 -#define R_GEN_CONFIG__scsi0w__BITNR 6 -#define R_GEN_CONFIG__scsi0w__WIDTH 1 -#define R_GEN_CONFIG__scsi0w__select 1 -#define R_GEN_CONFIG__scsi0w__disable 0 -#define R_GEN_CONFIG__scsi1__BITNR 5 -#define R_GEN_CONFIG__scsi1__WIDTH 1 -#define R_GEN_CONFIG__scsi1__select 1 -#define R_GEN_CONFIG__scsi1__disable 0 -#define R_GEN_CONFIG__mio__BITNR 4 -#define R_GEN_CONFIG__mio__WIDTH 1 -#define R_GEN_CONFIG__mio__select 1 -#define R_GEN_CONFIG__mio__disable 0 -#define R_GEN_CONFIG__ser2__BITNR 3 -#define R_GEN_CONFIG__ser2__WIDTH 1 -#define R_GEN_CONFIG__ser2__select 1 -#define R_GEN_CONFIG__ser2__disable 0 -#define R_GEN_CONFIG__par0__BITNR 2 -#define R_GEN_CONFIG__par0__WIDTH 1 -#define R_GEN_CONFIG__par0__select 1 -#define R_GEN_CONFIG__par0__disable 0 -#define R_GEN_CONFIG__ata__BITNR 1 -#define R_GEN_CONFIG__ata__WIDTH 1 -#define R_GEN_CONFIG__ata__select 1 -#define R_GEN_CONFIG__ata__disable 0 -#define R_GEN_CONFIG__scsi0__BITNR 0 -#define R_GEN_CONFIG__scsi0__WIDTH 1 -#define R_GEN_CONFIG__scsi0__select 1 -#define R_GEN_CONFIG__scsi0__disable 0 - -#define R_GEN_CONFIG_II (IO_TYPECAST_UDWORD 0xb0000034) -#define R_GEN_CONFIG_II__sermode3__BITNR 6 -#define R_GEN_CONFIG_II__sermode3__WIDTH 1 -#define R_GEN_CONFIG_II__sermode3__async 0 -#define R_GEN_CONFIG_II__sermode3__sync 1 -#define R_GEN_CONFIG_II__sermode1__BITNR 4 -#define R_GEN_CONFIG_II__sermode1__WIDTH 1 -#define R_GEN_CONFIG_II__sermode1__async 0 -#define R_GEN_CONFIG_II__sermode1__sync 1 -#define R_GEN_CONFIG_II__ext_clk__BITNR 2 -#define R_GEN_CONFIG_II__ext_clk__WIDTH 1 -#define R_GEN_CONFIG_II__ext_clk__select 1 -#define R_GEN_CONFIG_II__ext_clk__disable 0 -#define R_GEN_CONFIG_II__ser3__BITNR 1 -#define R_GEN_CONFIG_II__ser3__WIDTH 1 -#define R_GEN_CONFIG_II__ser3__select 1 -#define R_GEN_CONFIG_II__ser3__disable 0 -#define R_GEN_CONFIG_II__ser2__BITNR 0 -#define R_GEN_CONFIG_II__ser2__WIDTH 1 -#define R_GEN_CONFIG_II__ser2__select 1 -#define R_GEN_CONFIG_II__ser2__disable 0 - -#define R_PORT_G_DATA (IO_TYPECAST_UDWORD 0xb0000028) -#define R_PORT_G_DATA__data__BITNR 0 -#define R_PORT_G_DATA__data__WIDTH 32 - -/* -!* General port configuration registers -!*/ - -#define R_PORT_PA_SET (IO_TYPECAST_UDWORD 0xb0000030) -#define R_PORT_PA_SET__dir7__BITNR 15 -#define R_PORT_PA_SET__dir7__WIDTH 1 -#define R_PORT_PA_SET__dir7__input 0 -#define R_PORT_PA_SET__dir7__output 1 -#define R_PORT_PA_SET__dir6__BITNR 14 -#define R_PORT_PA_SET__dir6__WIDTH 1 -#define R_PORT_PA_SET__dir6__input 0 -#define R_PORT_PA_SET__dir6__output 1 -#define R_PORT_PA_SET__dir5__BITNR 13 -#define R_PORT_PA_SET__dir5__WIDTH 1 -#define R_PORT_PA_SET__dir5__input 0 -#define R_PORT_PA_SET__dir5__output 1 -#define R_PORT_PA_SET__dir4__BITNR 12 -#define R_PORT_PA_SET__dir4__WIDTH 1 -#define R_PORT_PA_SET__dir4__input 0 -#define R_PORT_PA_SET__dir4__output 1 -#define R_PORT_PA_SET__dir3__BITNR 11 -#define R_PORT_PA_SET__dir3__WIDTH 1 -#define R_PORT_PA_SET__dir3__input 0 -#define R_PORT_PA_SET__dir3__output 1 -#define R_PORT_PA_SET__dir2__BITNR 10 -#define R_PORT_PA_SET__dir2__WIDTH 1 -#define R_PORT_PA_SET__dir2__input 0 -#define R_PORT_PA_SET__dir2__output 1 -#define R_PORT_PA_SET__dir1__BITNR 9 -#define R_PORT_PA_SET__dir1__WIDTH 1 -#define R_PORT_PA_SET__dir1__input 0 -#define R_PORT_PA_SET__dir1__output 1 -#define R_PORT_PA_SET__dir0__BITNR 8 -#define R_PORT_PA_SET__dir0__WIDTH 1 -#define R_PORT_PA_SET__dir0__input 0 -#define R_PORT_PA_SET__dir0__output 1 -#define R_PORT_PA_SET__data_out__BITNR 0 -#define R_PORT_PA_SET__data_out__WIDTH 8 - -#define R_PORT_PA_DATA (IO_TYPECAST_BYTE 0xb0000030) -#define R_PORT_PA_DATA__data_out__BITNR 0 -#define R_PORT_PA_DATA__data_out__WIDTH 8 - -#define R_PORT_PA_DIR (IO_TYPECAST_BYTE 0xb0000031) -#define R_PORT_PA_DIR__dir7__BITNR 7 -#define R_PORT_PA_DIR__dir7__WIDTH 1 -#define R_PORT_PA_DIR__dir7__input 0 -#define R_PORT_PA_DIR__dir7__output 1 -#define R_PORT_PA_DIR__dir6__BITNR 6 -#define R_PORT_PA_DIR__dir6__WIDTH 1 -#define R_PORT_PA_DIR__dir6__input 0 -#define R_PORT_PA_DIR__dir6__output 1 -#define R_PORT_PA_DIR__dir5__BITNR 5 -#define R_PORT_PA_DIR__dir5__WIDTH 1 -#define R_PORT_PA_DIR__dir5__input 0 -#define R_PORT_PA_DIR__dir5__output 1 -#define R_PORT_PA_DIR__dir4__BITNR 4 -#define R_PORT_PA_DIR__dir4__WIDTH 1 -#define R_PORT_PA_DIR__dir4__input 0 -#define R_PORT_PA_DIR__dir4__output 1 -#define R_PORT_PA_DIR__dir3__BITNR 3 -#define R_PORT_PA_DIR__dir3__WIDTH 1 -#define R_PORT_PA_DIR__dir3__input 0 -#define R_PORT_PA_DIR__dir3__output 1 -#define R_PORT_PA_DIR__dir2__BITNR 2 -#define R_PORT_PA_DIR__dir2__WIDTH 1 -#define R_PORT_PA_DIR__dir2__input 0 -#define R_PORT_PA_DIR__dir2__output 1 -#define R_PORT_PA_DIR__dir1__BITNR 1 -#define R_PORT_PA_DIR__dir1__WIDTH 1 -#define R_PORT_PA_DIR__dir1__input 0 -#define R_PORT_PA_DIR__dir1__output 1 -#define R_PORT_PA_DIR__dir0__BITNR 0 -#define R_PORT_PA_DIR__dir0__WIDTH 1 -#define R_PORT_PA_DIR__dir0__input 0 -#define R_PORT_PA_DIR__dir0__output 1 - -#define R_PORT_PA_READ (IO_TYPECAST_RO_UDWORD 0xb0000030) -#define R_PORT_PA_READ__data_in__BITNR 0 -#define R_PORT_PA_READ__data_in__WIDTH 8 - -#define R_PORT_PB_SET (IO_TYPECAST_UDWORD 0xb0000038) -#define R_PORT_PB_SET__syncser3__BITNR 29 -#define R_PORT_PB_SET__syncser3__WIDTH 1 -#define R_PORT_PB_SET__syncser3__port_cs 0 -#define R_PORT_PB_SET__syncser3__ss3extra 1 -#define R_PORT_PB_SET__syncser1__BITNR 28 -#define R_PORT_PB_SET__syncser1__WIDTH 1 -#define R_PORT_PB_SET__syncser1__port_cs 0 -#define R_PORT_PB_SET__syncser1__ss1extra 1 -#define R_PORT_PB_SET__i2c_en__BITNR 27 -#define R_PORT_PB_SET__i2c_en__WIDTH 1 -#define R_PORT_PB_SET__i2c_en__off 0 -#define R_PORT_PB_SET__i2c_en__on 1 -#define R_PORT_PB_SET__i2c_d__BITNR 26 -#define R_PORT_PB_SET__i2c_d__WIDTH 1 -#define R_PORT_PB_SET__i2c_clk__BITNR 25 -#define R_PORT_PB_SET__i2c_clk__WIDTH 1 -#define R_PORT_PB_SET__i2c_oe___BITNR 24 -#define R_PORT_PB_SET__i2c_oe___WIDTH 1 -#define R_PORT_PB_SET__i2c_oe___enable 0 -#define R_PORT_PB_SET__i2c_oe___disable 1 -#define R_PORT_PB_SET__cs7__BITNR 23 -#define R_PORT_PB_SET__cs7__WIDTH 1 -#define R_PORT_PB_SET__cs7__port 0 -#define R_PORT_PB_SET__cs7__cs 1 -#define R_PORT_PB_SET__cs6__BITNR 22 -#define R_PORT_PB_SET__cs6__WIDTH 1 -#define R_PORT_PB_SET__cs6__port 0 -#define R_PORT_PB_SET__cs6__cs 1 -#define R_PORT_PB_SET__cs5__BITNR 21 -#define R_PORT_PB_SET__cs5__WIDTH 1 -#define R_PORT_PB_SET__cs5__port 0 -#define R_PORT_PB_SET__cs5__cs 1 -#define R_PORT_PB_SET__cs4__BITNR 20 -#define R_PORT_PB_SET__cs4__WIDTH 1 -#define R_PORT_PB_SET__cs4__port 0 -#define R_PORT_PB_SET__cs4__cs 1 -#define R_PORT_PB_SET__cs3__BITNR 19 -#define R_PORT_PB_SET__cs3__WIDTH 1 -#define R_PORT_PB_SET__cs3__port 0 -#define R_PORT_PB_SET__cs3__cs 1 -#define R_PORT_PB_SET__cs2__BITNR 18 -#define R_PORT_PB_SET__cs2__WIDTH 1 -#define R_PORT_PB_SET__cs2__port 0 -#define R_PORT_PB_SET__cs2__cs 1 -#define R_PORT_PB_SET__scsi1__BITNR 17 -#define R_PORT_PB_SET__scsi1__WIDTH 1 -#define R_PORT_PB_SET__scsi1__port_cs 0 -#define R_PORT_PB_SET__scsi1__enph 1 -#define R_PORT_PB_SET__scsi0__BITNR 16 -#define R_PORT_PB_SET__scsi0__WIDTH 1 -#define R_PORT_PB_SET__scsi0__port_cs 0 -#define R_PORT_PB_SET__scsi0__enph 1 -#define R_PORT_PB_SET__dir7__BITNR 15 -#define R_PORT_PB_SET__dir7__WIDTH 1 -#define R_PORT_PB_SET__dir7__input 0 -#define R_PORT_PB_SET__dir7__output 1 -#define R_PORT_PB_SET__dir6__BITNR 14 -#define R_PORT_PB_SET__dir6__WIDTH 1 -#define R_PORT_PB_SET__dir6__input 0 -#define R_PORT_PB_SET__dir6__output 1 -#define R_PORT_PB_SET__dir5__BITNR 13 -#define R_PORT_PB_SET__dir5__WIDTH 1 -#define R_PORT_PB_SET__dir5__input 0 -#define R_PORT_PB_SET__dir5__output 1 -#define R_PORT_PB_SET__dir4__BITNR 12 -#define R_PORT_PB_SET__dir4__WIDTH 1 -#define R_PORT_PB_SET__dir4__input 0 -#define R_PORT_PB_SET__dir4__output 1 -#define R_PORT_PB_SET__dir3__BITNR 11 -#define R_PORT_PB_SET__dir3__WIDTH 1 -#define R_PORT_PB_SET__dir3__input 0 -#define R_PORT_PB_SET__dir3__output 1 -#define R_PORT_PB_SET__dir2__BITNR 10 -#define R_PORT_PB_SET__dir2__WIDTH 1 -#define R_PORT_PB_SET__dir2__input 0 -#define R_PORT_PB_SET__dir2__output 1 -#define R_PORT_PB_SET__dir1__BITNR 9 -#define R_PORT_PB_SET__dir1__WIDTH 1 -#define R_PORT_PB_SET__dir1__input 0 -#define R_PORT_PB_SET__dir1__output 1 -#define R_PORT_PB_SET__dir0__BITNR 8 -#define R_PORT_PB_SET__dir0__WIDTH 1 -#define R_PORT_PB_SET__dir0__input 0 -#define R_PORT_PB_SET__dir0__output 1 -#define R_PORT_PB_SET__data_out__BITNR 0 -#define R_PORT_PB_SET__data_out__WIDTH 8 - -#define R_PORT_PB_DATA (IO_TYPECAST_BYTE 0xb0000038) -#define R_PORT_PB_DATA__data_out__BITNR 0 -#define R_PORT_PB_DATA__data_out__WIDTH 8 - -#define R_PORT_PB_DIR (IO_TYPECAST_BYTE 0xb0000039) -#define R_PORT_PB_DIR__dir7__BITNR 7 -#define R_PORT_PB_DIR__dir7__WIDTH 1 -#define R_PORT_PB_DIR__dir7__input 0 -#define R_PORT_PB_DIR__dir7__output 1 -#define R_PORT_PB_DIR__dir6__BITNR 6 -#define R_PORT_PB_DIR__dir6__WIDTH 1 -#define R_PORT_PB_DIR__dir6__input 0 -#define R_PORT_PB_DIR__dir6__output 1 -#define R_PORT_PB_DIR__dir5__BITNR 5 -#define R_PORT_PB_DIR__dir5__WIDTH 1 -#define R_PORT_PB_DIR__dir5__input 0 -#define R_PORT_PB_DIR__dir5__output 1 -#define R_PORT_PB_DIR__dir4__BITNR 4 -#define R_PORT_PB_DIR__dir4__WIDTH 1 -#define R_PORT_PB_DIR__dir4__input 0 -#define R_PORT_PB_DIR__dir4__output 1 -#define R_PORT_PB_DIR__dir3__BITNR 3 -#define R_PORT_PB_DIR__dir3__WIDTH 1 -#define R_PORT_PB_DIR__dir3__input 0 -#define R_PORT_PB_DIR__dir3__output 1 -#define R_PORT_PB_DIR__dir2__BITNR 2 -#define R_PORT_PB_DIR__dir2__WIDTH 1 -#define R_PORT_PB_DIR__dir2__input 0 -#define R_PORT_PB_DIR__dir2__output 1 -#define R_PORT_PB_DIR__dir1__BITNR 1 -#define R_PORT_PB_DIR__dir1__WIDTH 1 -#define R_PORT_PB_DIR__dir1__input 0 -#define R_PORT_PB_DIR__dir1__output 1 -#define R_PORT_PB_DIR__dir0__BITNR 0 -#define R_PORT_PB_DIR__dir0__WIDTH 1 -#define R_PORT_PB_DIR__dir0__input 0 -#define R_PORT_PB_DIR__dir0__output 1 - -#define R_PORT_PB_CONFIG (IO_TYPECAST_BYTE 0xb000003a) -#define R_PORT_PB_CONFIG__cs7__BITNR 7 -#define R_PORT_PB_CONFIG__cs7__WIDTH 1 -#define R_PORT_PB_CONFIG__cs7__port 0 -#define R_PORT_PB_CONFIG__cs7__cs 1 -#define R_PORT_PB_CONFIG__cs6__BITNR 6 -#define R_PORT_PB_CONFIG__cs6__WIDTH 1 -#define R_PORT_PB_CONFIG__cs6__port 0 -#define R_PORT_PB_CONFIG__cs6__cs 1 -#define R_PORT_PB_CONFIG__cs5__BITNR 5 -#define R_PORT_PB_CONFIG__cs5__WIDTH 1 -#define R_PORT_PB_CONFIG__cs5__port 0 -#define R_PORT_PB_CONFIG__cs5__cs 1 -#define R_PORT_PB_CONFIG__cs4__BITNR 4 -#define R_PORT_PB_CONFIG__cs4__WIDTH 1 -#define R_PORT_PB_CONFIG__cs4__port 0 -#define R_PORT_PB_CONFIG__cs4__cs 1 -#define R_PORT_PB_CONFIG__cs3__BITNR 3 -#define R_PORT_PB_CONFIG__cs3__WIDTH 1 -#define R_PORT_PB_CONFIG__cs3__port 0 -#define R_PORT_PB_CONFIG__cs3__cs 1 -#define R_PORT_PB_CONFIG__cs2__BITNR 2 -#define R_PORT_PB_CONFIG__cs2__WIDTH 1 -#define R_PORT_PB_CONFIG__cs2__port 0 -#define R_PORT_PB_CONFIG__cs2__cs 1 -#define R_PORT_PB_CONFIG__scsi1__BITNR 1 -#define R_PORT_PB_CONFIG__scsi1__WIDTH 1 -#define R_PORT_PB_CONFIG__scsi1__port_cs 0 -#define R_PORT_PB_CONFIG__scsi1__enph 1 -#define R_PORT_PB_CONFIG__scsi0__BITNR 0 -#define R_PORT_PB_CONFIG__scsi0__WIDTH 1 -#define R_PORT_PB_CONFIG__scsi0__port_cs 0 -#define R_PORT_PB_CONFIG__scsi0__enph 1 - -#define R_PORT_PB_I2C (IO_TYPECAST_BYTE 0xb000003b) -#define R_PORT_PB_I2C__syncser3__BITNR 5 -#define R_PORT_PB_I2C__syncser3__WIDTH 1 -#define R_PORT_PB_I2C__syncser3__port_cs 0 -#define R_PORT_PB_I2C__syncser3__ss3extra 1 -#define R_PORT_PB_I2C__syncser1__BITNR 4 -#define R_PORT_PB_I2C__syncser1__WIDTH 1 -#define R_PORT_PB_I2C__syncser1__port_cs 0 -#define R_PORT_PB_I2C__syncser1__ss1extra 1 -#define R_PORT_PB_I2C__i2c_en__BITNR 3 -#define R_PORT_PB_I2C__i2c_en__WIDTH 1 -#define R_PORT_PB_I2C__i2c_en__off 0 -#define R_PORT_PB_I2C__i2c_en__on 1 -#define R_PORT_PB_I2C__i2c_d__BITNR 2 -#define R_PORT_PB_I2C__i2c_d__WIDTH 1 -#define R_PORT_PB_I2C__i2c_clk__BITNR 1 -#define R_PORT_PB_I2C__i2c_clk__WIDTH 1 -#define R_PORT_PB_I2C__i2c_oe___BITNR 0 -#define R_PORT_PB_I2C__i2c_oe___WIDTH 1 -#define R_PORT_PB_I2C__i2c_oe___enable 0 -#define R_PORT_PB_I2C__i2c_oe___disable 1 - -#define R_PORT_PB_READ (IO_TYPECAST_RO_UDWORD 0xb0000038) -#define R_PORT_PB_READ__data_in__BITNR 0 -#define R_PORT_PB_READ__data_in__WIDTH 8 - -/* -!* Serial port registers -!*/ - -#define R_SERIAL0_CTRL (IO_TYPECAST_UDWORD 0xb0000060) -#define R_SERIAL0_CTRL__tr_baud__BITNR 28 -#define R_SERIAL0_CTRL__tr_baud__WIDTH 4 -#define R_SERIAL0_CTRL__tr_baud__c300Hz 0 -#define R_SERIAL0_CTRL__tr_baud__c600Hz 1 -#define R_SERIAL0_CTRL__tr_baud__c1200Hz 2 -#define R_SERIAL0_CTRL__tr_baud__c2400Hz 3 -#define R_SERIAL0_CTRL__tr_baud__c4800Hz 4 -#define R_SERIAL0_CTRL__tr_baud__c9600Hz 5 -#define R_SERIAL0_CTRL__tr_baud__c19k2Hz 6 -#define R_SERIAL0_CTRL__tr_baud__c38k4Hz 7 -#define R_SERIAL0_CTRL__tr_baud__c57k6Hz 8 -#define R_SERIAL0_CTRL__tr_baud__c115k2Hz 9 -#define R_SERIAL0_CTRL__tr_baud__c230k4Hz 10 -#define R_SERIAL0_CTRL__tr_baud__c460k8Hz 11 -#define R_SERIAL0_CTRL__tr_baud__c921k6Hz 12 -#define R_SERIAL0_CTRL__tr_baud__c1843k2Hz 13 -#define R_SERIAL0_CTRL__tr_baud__c6250kHz 14 -#define R_SERIAL0_CTRL__tr_baud__reserved 15 -#define R_SERIAL0_CTRL__rec_baud__BITNR 24 -#define R_SERIAL0_CTRL__rec_baud__WIDTH 4 -#define R_SERIAL0_CTRL__rec_baud__c300Hz 0 -#define R_SERIAL0_CTRL__rec_baud__c600Hz 1 -#define R_SERIAL0_CTRL__rec_baud__c1200Hz 2 -#define R_SERIAL0_CTRL__rec_baud__c2400Hz 3 -#define R_SERIAL0_CTRL__rec_baud__c4800Hz 4 -#define R_SERIAL0_CTRL__rec_baud__c9600Hz 5 -#define R_SERIAL0_CTRL__rec_baud__c19k2Hz 6 -#define R_SERIAL0_CTRL__rec_baud__c38k4Hz 7 -#define R_SERIAL0_CTRL__rec_baud__c57k6Hz 8 -#define R_SERIAL0_CTRL__rec_baud__c115k2Hz 9 -#define R_SERIAL0_CTRL__rec_baud__c230k4Hz 10 -#define R_SERIAL0_CTRL__rec_baud__c460k8Hz 11 -#define R_SERIAL0_CTRL__rec_baud__c921k6Hz 12 -#define R_SERIAL0_CTRL__rec_baud__c1843k2Hz 13 -#define R_SERIAL0_CTRL__rec_baud__c6250kHz 14 -#define R_SERIAL0_CTRL__rec_baud__reserved 15 -#define R_SERIAL0_CTRL__dma_err__BITNR 23 -#define R_SERIAL0_CTRL__dma_err__WIDTH 1 -#define R_SERIAL0_CTRL__dma_err__stop 0 -#define R_SERIAL0_CTRL__dma_err__ignore 1 -#define R_SERIAL0_CTRL__rec_enable__BITNR 22 -#define R_SERIAL0_CTRL__rec_enable__WIDTH 1 -#define R_SERIAL0_CTRL__rec_enable__disable 0 -#define R_SERIAL0_CTRL__rec_enable__enable 1 -#define R_SERIAL0_CTRL__rts___BITNR 21 -#define R_SERIAL0_CTRL__rts___WIDTH 1 -#define R_SERIAL0_CTRL__rts___active 0 -#define R_SERIAL0_CTRL__rts___inactive 1 -#define R_SERIAL0_CTRL__sampling__BITNR 20 -#define R_SERIAL0_CTRL__sampling__WIDTH 1 -#define R_SERIAL0_CTRL__sampling__middle 0 -#define R_SERIAL0_CTRL__sampling__majority 1 -#define R_SERIAL0_CTRL__rec_stick_par__BITNR 19 -#define R_SERIAL0_CTRL__rec_stick_par__WIDTH 1 -#define R_SERIAL0_CTRL__rec_stick_par__normal 0 -#define R_SERIAL0_CTRL__rec_stick_par__stick 1 -#define R_SERIAL0_CTRL__rec_par__BITNR 18 -#define R_SERIAL0_CTRL__rec_par__WIDTH 1 -#define R_SERIAL0_CTRL__rec_par__even 0 -#define R_SERIAL0_CTRL__rec_par__odd 1 -#define R_SERIAL0_CTRL__rec_par_en__BITNR 17 -#define R_SERIAL0_CTRL__rec_par_en__WIDTH 1 -#define R_SERIAL0_CTRL__rec_par_en__disable 0 -#define R_SERIAL0_CTRL__rec_par_en__enable 1 -#define R_SERIAL0_CTRL__rec_bitnr__BITNR 16 -#define R_SERIAL0_CTRL__rec_bitnr__WIDTH 1 -#define R_SERIAL0_CTRL__rec_bitnr__rec_8bit 0 -#define R_SERIAL0_CTRL__rec_bitnr__rec_7bit 1 -#define R_SERIAL0_CTRL__txd__BITNR 15 -#define R_SERIAL0_CTRL__txd__WIDTH 1 -#define R_SERIAL0_CTRL__tr_enable__BITNR 14 -#define R_SERIAL0_CTRL__tr_enable__WIDTH 1 -#define R_SERIAL0_CTRL__tr_enable__disable 0 -#define R_SERIAL0_CTRL__tr_enable__enable 1 -#define R_SERIAL0_CTRL__auto_cts__BITNR 13 -#define R_SERIAL0_CTRL__auto_cts__WIDTH 1 -#define R_SERIAL0_CTRL__auto_cts__disabled 0 -#define R_SERIAL0_CTRL__auto_cts__active 1 -#define R_SERIAL0_CTRL__stop_bits__BITNR 12 -#define R_SERIAL0_CTRL__stop_bits__WIDTH 1 -#define R_SERIAL0_CTRL__stop_bits__one_bit 0 -#define R_SERIAL0_CTRL__stop_bits__two_bits 1 -#define R_SERIAL0_CTRL__tr_stick_par__BITNR 11 -#define R_SERIAL0_CTRL__tr_stick_par__WIDTH 1 -#define R_SERIAL0_CTRL__tr_stick_par__normal 0 -#define R_SERIAL0_CTRL__tr_stick_par__stick 1 -#define R_SERIAL0_CTRL__tr_par__BITNR 10 -#define R_SERIAL0_CTRL__tr_par__WIDTH 1 -#define R_SERIAL0_CTRL__tr_par__even 0 -#define R_SERIAL0_CTRL__tr_par__odd 1 -#define R_SERIAL0_CTRL__tr_par_en__BITNR 9 -#define R_SERIAL0_CTRL__tr_par_en__WIDTH 1 -#define R_SERIAL0_CTRL__tr_par_en__disable 0 -#define R_SERIAL0_CTRL__tr_par_en__enable 1 -#define R_SERIAL0_CTRL__tr_bitnr__BITNR 8 -#define R_SERIAL0_CTRL__tr_bitnr__WIDTH 1 -#define R_SERIAL0_CTRL__tr_bitnr__tr_8bit 0 -#define R_SERIAL0_CTRL__tr_bitnr__tr_7bit 1 -#define R_SERIAL0_CTRL__data_out__BITNR 0 -#define R_SERIAL0_CTRL__data_out__WIDTH 8 - -#define R_SERIAL0_BAUD (IO_TYPECAST_BYTE 0xb0000063) -#define R_SERIAL0_BAUD__tr_baud__BITNR 4 -#define R_SERIAL0_BAUD__tr_baud__WIDTH 4 -#define R_SERIAL0_BAUD__tr_baud__c300Hz 0 -#define R_SERIAL0_BAUD__tr_baud__c600Hz 1 -#define R_SERIAL0_BAUD__tr_baud__c1200Hz 2 -#define R_SERIAL0_BAUD__tr_baud__c2400Hz 3 -#define R_SERIAL0_BAUD__tr_baud__c4800Hz 4 -#define R_SERIAL0_BAUD__tr_baud__c9600Hz 5 -#define R_SERIAL0_BAUD__tr_baud__c19k2Hz 6 -#define R_SERIAL0_BAUD__tr_baud__c38k4Hz 7 -#define R_SERIAL0_BAUD__tr_baud__c57k6Hz 8 -#define R_SERIAL0_BAUD__tr_baud__c115k2Hz 9 -#define R_SERIAL0_BAUD__tr_baud__c230k4Hz 10 -#define R_SERIAL0_BAUD__tr_baud__c460k8Hz 11 -#define R_SERIAL0_BAUD__tr_baud__c921k6Hz 12 -#define R_SERIAL0_BAUD__tr_baud__c1843k2Hz 13 -#define R_SERIAL0_BAUD__tr_baud__c6250kHz 14 -#define R_SERIAL0_BAUD__tr_baud__reserved 15 -#define R_SERIAL0_BAUD__rec_baud__BITNR 0 -#define R_SERIAL0_BAUD__rec_baud__WIDTH 4 -#define R_SERIAL0_BAUD__rec_baud__c300Hz 0 -#define R_SERIAL0_BAUD__rec_baud__c600Hz 1 -#define R_SERIAL0_BAUD__rec_baud__c1200Hz 2 -#define R_SERIAL0_BAUD__rec_baud__c2400Hz 3 -#define R_SERIAL0_BAUD__rec_baud__c4800Hz 4 -#define R_SERIAL0_BAUD__rec_baud__c9600Hz 5 -#define R_SERIAL0_BAUD__rec_baud__c19k2Hz 6 -#define R_SERIAL0_BAUD__rec_baud__c38k4Hz 7 -#define R_SERIAL0_BAUD__rec_baud__c57k6Hz 8 -#define R_SERIAL0_BAUD__rec_baud__c115k2Hz 9 -#define R_SERIAL0_BAUD__rec_baud__c230k4Hz 10 -#define R_SERIAL0_BAUD__rec_baud__c460k8Hz 11 -#define R_SERIAL0_BAUD__rec_baud__c921k6Hz 12 -#define R_SERIAL0_BAUD__rec_baud__c1843k2Hz 13 -#define R_SERIAL0_BAUD__rec_baud__c6250kHz 14 -#define R_SERIAL0_BAUD__rec_baud__reserved 15 - -#define R_SERIAL0_REC_CTRL (IO_TYPECAST_BYTE 0xb0000062) -#define R_SERIAL0_REC_CTRL__dma_err__BITNR 7 -#define R_SERIAL0_REC_CTRL__dma_err__WIDTH 1 -#define R_SERIAL0_REC_CTRL__dma_err__stop 0 -#define R_SERIAL0_REC_CTRL__dma_err__ignore 1 -#define R_SERIAL0_REC_CTRL__rec_enable__BITNR 6 -#define R_SERIAL0_REC_CTRL__rec_enable__WIDTH 1 -#define R_SERIAL0_REC_CTRL__rec_enable__disable 0 -#define R_SERIAL0_REC_CTRL__rec_enable__enable 1 -#define R_SERIAL0_REC_CTRL__rts___BITNR 5 -#define R_SERIAL0_REC_CTRL__rts___WIDTH 1 -#define R_SERIAL0_REC_CTRL__rts___active 0 -#define R_SERIAL0_REC_CTRL__rts___inactive 1 -#define R_SERIAL0_REC_CTRL__sampling__BITNR 4 -#define R_SERIAL0_REC_CTRL__sampling__WIDTH 1 -#define R_SERIAL0_REC_CTRL__sampling__middle 0 -#define R_SERIAL0_REC_CTRL__sampling__majority 1 -#define R_SERIAL0_REC_CTRL__rec_stick_par__BITNR 3 -#define R_SERIAL0_REC_CTRL__rec_stick_par__WIDTH 1 -#define R_SERIAL0_REC_CTRL__rec_stick_par__normal 0 -#define R_SERIAL0_REC_CTRL__rec_stick_par__stick 1 -#define R_SERIAL0_REC_CTRL__rec_par__BITNR 2 -#define R_SERIAL0_REC_CTRL__rec_par__WIDTH 1 -#define R_SERIAL0_REC_CTRL__rec_par__even 0 -#define R_SERIAL0_REC_CTRL__rec_par__odd 1 -#define R_SERIAL0_REC_CTRL__rec_par_en__BITNR 1 -#define R_SERIAL0_REC_CTRL__rec_par_en__WIDTH 1 -#define R_SERIAL0_REC_CTRL__rec_par_en__disable 0 -#define R_SERIAL0_REC_CTRL__rec_par_en__enable 1 -#define R_SERIAL0_REC_CTRL__rec_bitnr__BITNR 0 -#define R_SERIAL0_REC_CTRL__rec_bitnr__WIDTH 1 -#define R_SERIAL0_REC_CTRL__rec_bitnr__rec_8bit 0 -#define R_SERIAL0_REC_CTRL__rec_bitnr__rec_7bit 1 - -#define R_SERIAL0_TR_CTRL (IO_TYPECAST_BYTE 0xb0000061) -#define R_SERIAL0_TR_CTRL__txd__BITNR 7 -#define R_SERIAL0_TR_CTRL__txd__WIDTH 1 -#define R_SERIAL0_TR_CTRL__tr_enable__BITNR 6 -#define R_SERIAL0_TR_CTRL__tr_enable__WIDTH 1 -#define R_SERIAL0_TR_CTRL__tr_enable__disable 0 -#define R_SERIAL0_TR_CTRL__tr_enable__enable 1 -#define R_SERIAL0_TR_CTRL__auto_cts__BITNR 5 -#define R_SERIAL0_TR_CTRL__auto_cts__WIDTH 1 -#define R_SERIAL0_TR_CTRL__auto_cts__disabled 0 -#define R_SERIAL0_TR_CTRL__auto_cts__active 1 -#define R_SERIAL0_TR_CTRL__stop_bits__BITNR 4 -#define R_SERIAL0_TR_CTRL__stop_bits__WIDTH 1 -#define R_SERIAL0_TR_CTRL__stop_bits__one_bit 0 -#define R_SERIAL0_TR_CTRL__stop_bits__two_bits 1 -#define R_SERIAL0_TR_CTRL__tr_stick_par__BITNR 3 -#define R_SERIAL0_TR_CTRL__tr_stick_par__WIDTH 1 -#define R_SERIAL0_TR_CTRL__tr_stick_par__normal 0 -#define R_SERIAL0_TR_CTRL__tr_stick_par__stick 1 -#define R_SERIAL0_TR_CTRL__tr_par__BITNR 2 -#define R_SERIAL0_TR_CTRL__tr_par__WIDTH 1 -#define R_SERIAL0_TR_CTRL__tr_par__even 0 -#define R_SERIAL0_TR_CTRL__tr_par__odd 1 -#define R_SERIAL0_TR_CTRL__tr_par_en__BITNR 1 -#define R_SERIAL0_TR_CTRL__tr_par_en__WIDTH 1 -#define R_SERIAL0_TR_CTRL__tr_par_en__disable 0 -#define R_SERIAL0_TR_CTRL__tr_par_en__enable 1 -#define R_SERIAL0_TR_CTRL__tr_bitnr__BITNR 0 -#define R_SERIAL0_TR_CTRL__tr_bitnr__WIDTH 1 -#define R_SERIAL0_TR_CTRL__tr_bitnr__tr_8bit 0 -#define R_SERIAL0_TR_CTRL__tr_bitnr__tr_7bit 1 - -#define R_SERIAL0_TR_DATA (IO_TYPECAST_BYTE 0xb0000060) -#define R_SERIAL0_TR_DATA__data_out__BITNR 0 -#define R_SERIAL0_TR_DATA__data_out__WIDTH 8 - -#define R_SERIAL0_READ (IO_TYPECAST_RO_UDWORD 0xb0000060) -#define R_SERIAL0_READ__xoff_detect__BITNR 15 -#define R_SERIAL0_READ__xoff_detect__WIDTH 1 -#define R_SERIAL0_READ__xoff_detect__no_xoff 0 -#define R_SERIAL0_READ__xoff_detect__xoff 1 -#define R_SERIAL0_READ__cts___BITNR 14 -#define R_SERIAL0_READ__cts___WIDTH 1 -#define R_SERIAL0_READ__cts___active 0 -#define R_SERIAL0_READ__cts___inactive 1 -#define R_SERIAL0_READ__tr_ready__BITNR 13 -#define R_SERIAL0_READ__tr_ready__WIDTH 1 -#define R_SERIAL0_READ__tr_ready__full 0 -#define R_SERIAL0_READ__tr_ready__ready 1 -#define R_SERIAL0_READ__rxd__BITNR 12 -#define R_SERIAL0_READ__rxd__WIDTH 1 -#define R_SERIAL0_READ__overrun__BITNR 11 -#define R_SERIAL0_READ__overrun__WIDTH 1 -#define R_SERIAL0_READ__overrun__no 0 -#define R_SERIAL0_READ__overrun__yes 1 -#define R_SERIAL0_READ__par_err__BITNR 10 -#define R_SERIAL0_READ__par_err__WIDTH 1 -#define R_SERIAL0_READ__par_err__no 0 -#define R_SERIAL0_READ__par_err__yes 1 -#define R_SERIAL0_READ__framing_err__BITNR 9 -#define R_SERIAL0_READ__framing_err__WIDTH 1 -#define R_SERIAL0_READ__framing_err__no 0 -#define R_SERIAL0_READ__framing_err__yes 1 -#define R_SERIAL0_READ__data_avail__BITNR 8 -#define R_SERIAL0_READ__data_avail__WIDTH 1 -#define R_SERIAL0_READ__data_avail__no 0 -#define R_SERIAL0_READ__data_avail__yes 1 -#define R_SERIAL0_READ__data_in__BITNR 0 -#define R_SERIAL0_READ__data_in__WIDTH 8 - -#define R_SERIAL0_STATUS (IO_TYPECAST_RO_BYTE 0xb0000061) -#define R_SERIAL0_STATUS__xoff_detect__BITNR 7 -#define R_SERIAL0_STATUS__xoff_detect__WIDTH 1 -#define R_SERIAL0_STATUS__xoff_detect__no_xoff 0 -#define R_SERIAL0_STATUS__xoff_detect__xoff 1 -#define R_SERIAL0_STATUS__cts___BITNR 6 -#define R_SERIAL0_STATUS__cts___WIDTH 1 -#define R_SERIAL0_STATUS__cts___active 0 -#define R_SERIAL0_STATUS__cts___inactive 1 -#define R_SERIAL0_STATUS__tr_ready__BITNR 5 -#define R_SERIAL0_STATUS__tr_ready__WIDTH 1 -#define R_SERIAL0_STATUS__tr_ready__full 0 -#define R_SERIAL0_STATUS__tr_ready__ready 1 -#define R_SERIAL0_STATUS__rxd__BITNR 4 -#define R_SERIAL0_STATUS__rxd__WIDTH 1 -#define R_SERIAL0_STATUS__overrun__BITNR 3 -#define R_SERIAL0_STATUS__overrun__WIDTH 1 -#define R_SERIAL0_STATUS__overrun__no 0 -#define R_SERIAL0_STATUS__overrun__yes 1 -#define R_SERIAL0_STATUS__par_err__BITNR 2 -#define R_SERIAL0_STATUS__par_err__WIDTH 1 -#define R_SERIAL0_STATUS__par_err__no 0 -#define R_SERIAL0_STATUS__par_err__yes 1 -#define R_SERIAL0_STATUS__framing_err__BITNR 1 -#define R_SERIAL0_STATUS__framing_err__WIDTH 1 -#define R_SERIAL0_STATUS__framing_err__no 0 -#define R_SERIAL0_STATUS__framing_err__yes 1 -#define R_SERIAL0_STATUS__data_avail__BITNR 0 -#define R_SERIAL0_STATUS__data_avail__WIDTH 1 -#define R_SERIAL0_STATUS__data_avail__no 0 -#define R_SERIAL0_STATUS__data_avail__yes 1 - -#define R_SERIAL0_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000060) -#define R_SERIAL0_REC_DATA__data_in__BITNR 0 -#define R_SERIAL0_REC_DATA__data_in__WIDTH 8 - -#define R_SERIAL0_XOFF (IO_TYPECAST_UDWORD 0xb0000064) -#define R_SERIAL0_XOFF__tx_stop__BITNR 9 -#define R_SERIAL0_XOFF__tx_stop__WIDTH 1 -#define R_SERIAL0_XOFF__tx_stop__enable 0 -#define R_SERIAL0_XOFF__tx_stop__stop 1 -#define R_SERIAL0_XOFF__auto_xoff__BITNR 8 -#define R_SERIAL0_XOFF__auto_xoff__WIDTH 1 -#define R_SERIAL0_XOFF__auto_xoff__disable 0 -#define R_SERIAL0_XOFF__auto_xoff__enable 1 -#define R_SERIAL0_XOFF__xoff_char__BITNR 0 -#define R_SERIAL0_XOFF__xoff_char__WIDTH 8 - -#define R_SERIAL1_CTRL (IO_TYPECAST_UDWORD 0xb0000068) -#define R_SERIAL1_CTRL__tr_baud__BITNR 28 -#define R_SERIAL1_CTRL__tr_baud__WIDTH 4 -#define R_SERIAL1_CTRL__tr_baud__c300Hz 0 -#define R_SERIAL1_CTRL__tr_baud__c600Hz 1 -#define R_SERIAL1_CTRL__tr_baud__c1200Hz 2 -#define R_SERIAL1_CTRL__tr_baud__c2400Hz 3 -#define R_SERIAL1_CTRL__tr_baud__c4800Hz 4 -#define R_SERIAL1_CTRL__tr_baud__c9600Hz 5 -#define R_SERIAL1_CTRL__tr_baud__c19k2Hz 6 -#define R_SERIAL1_CTRL__tr_baud__c38k4Hz 7 -#define R_SERIAL1_CTRL__tr_baud__c57k6Hz 8 -#define R_SERIAL1_CTRL__tr_baud__c115k2Hz 9 -#define R_SERIAL1_CTRL__tr_baud__c230k4Hz 10 -#define R_SERIAL1_CTRL__tr_baud__c460k8Hz 11 -#define R_SERIAL1_CTRL__tr_baud__c921k6Hz 12 -#define R_SERIAL1_CTRL__tr_baud__c1843k2Hz 13 -#define R_SERIAL1_CTRL__tr_baud__c6250kHz 14 -#define R_SERIAL1_CTRL__tr_baud__reserved 15 -#define R_SERIAL1_CTRL__rec_baud__BITNR 24 -#define R_SERIAL1_CTRL__rec_baud__WIDTH 4 -#define R_SERIAL1_CTRL__rec_baud__c300Hz 0 -#define R_SERIAL1_CTRL__rec_baud__c600Hz 1 -#define R_SERIAL1_CTRL__rec_baud__c1200Hz 2 -#define R_SERIAL1_CTRL__rec_baud__c2400Hz 3 -#define R_SERIAL1_CTRL__rec_baud__c4800Hz 4 -#define R_SERIAL1_CTRL__rec_baud__c9600Hz 5 -#define R_SERIAL1_CTRL__rec_baud__c19k2Hz 6 -#define R_SERIAL1_CTRL__rec_baud__c38k4Hz 7 -#define R_SERIAL1_CTRL__rec_baud__c57k6Hz 8 -#define R_SERIAL1_CTRL__rec_baud__c115k2Hz 9 -#define R_SERIAL1_CTRL__rec_baud__c230k4Hz 10 -#define R_SERIAL1_CTRL__rec_baud__c460k8Hz 11 -#define R_SERIAL1_CTRL__rec_baud__c921k6Hz 12 -#define R_SERIAL1_CTRL__rec_baud__c1843k2Hz 13 -#define R_SERIAL1_CTRL__rec_baud__c6250kHz 14 -#define R_SERIAL1_CTRL__rec_baud__reserved 15 -#define R_SERIAL1_CTRL__dma_err__BITNR 23 -#define R_SERIAL1_CTRL__dma_err__WIDTH 1 -#define R_SERIAL1_CTRL__dma_err__stop 0 -#define R_SERIAL1_CTRL__dma_err__ignore 1 -#define R_SERIAL1_CTRL__rec_enable__BITNR 22 -#define R_SERIAL1_CTRL__rec_enable__WIDTH 1 -#define R_SERIAL1_CTRL__rec_enable__disable 0 -#define R_SERIAL1_CTRL__rec_enable__enable 1 -#define R_SERIAL1_CTRL__rts___BITNR 21 -#define R_SERIAL1_CTRL__rts___WIDTH 1 -#define R_SERIAL1_CTRL__rts___active 0 -#define R_SERIAL1_CTRL__rts___inactive 1 -#define R_SERIAL1_CTRL__sampling__BITNR 20 -#define R_SERIAL1_CTRL__sampling__WIDTH 1 -#define R_SERIAL1_CTRL__sampling__middle 0 -#define R_SERIAL1_CTRL__sampling__majority 1 -#define R_SERIAL1_CTRL__rec_stick_par__BITNR 19 -#define R_SERIAL1_CTRL__rec_stick_par__WIDTH 1 -#define R_SERIAL1_CTRL__rec_stick_par__normal 0 -#define R_SERIAL1_CTRL__rec_stick_par__stick 1 -#define R_SERIAL1_CTRL__rec_par__BITNR 18 -#define R_SERIAL1_CTRL__rec_par__WIDTH 1 -#define R_SERIAL1_CTRL__rec_par__even 0 -#define R_SERIAL1_CTRL__rec_par__odd 1 -#define R_SERIAL1_CTRL__rec_par_en__BITNR 17 -#define R_SERIAL1_CTRL__rec_par_en__WIDTH 1 -#define R_SERIAL1_CTRL__rec_par_en__disable 0 -#define R_SERIAL1_CTRL__rec_par_en__enable 1 -#define R_SERIAL1_CTRL__rec_bitnr__BITNR 16 -#define R_SERIAL1_CTRL__rec_bitnr__WIDTH 1 -#define R_SERIAL1_CTRL__rec_bitnr__rec_8bit 0 -#define R_SERIAL1_CTRL__rec_bitnr__rec_7bit 1 -#define R_SERIAL1_CTRL__txd__BITNR 15 -#define R_SERIAL1_CTRL__txd__WIDTH 1 -#define R_SERIAL1_CTRL__tr_enable__BITNR 14 -#define R_SERIAL1_CTRL__tr_enable__WIDTH 1 -#define R_SERIAL1_CTRL__tr_enable__disable 0 -#define R_SERIAL1_CTRL__tr_enable__enable 1 -#define R_SERIAL1_CTRL__auto_cts__BITNR 13 -#define R_SERIAL1_CTRL__auto_cts__WIDTH 1 -#define R_SERIAL1_CTRL__auto_cts__disabled 0 -#define R_SERIAL1_CTRL__auto_cts__active 1 -#define R_SERIAL1_CTRL__stop_bits__BITNR 12 -#define R_SERIAL1_CTRL__stop_bits__WIDTH 1 -#define R_SERIAL1_CTRL__stop_bits__one_bit 0 -#define R_SERIAL1_CTRL__stop_bits__two_bits 1 -#define R_SERIAL1_CTRL__tr_stick_par__BITNR 11 -#define R_SERIAL1_CTRL__tr_stick_par__WIDTH 1 -#define R_SERIAL1_CTRL__tr_stick_par__normal 0 -#define R_SERIAL1_CTRL__tr_stick_par__stick 1 -#define R_SERIAL1_CTRL__tr_par__BITNR 10 -#define R_SERIAL1_CTRL__tr_par__WIDTH 1 -#define R_SERIAL1_CTRL__tr_par__even 0 -#define R_SERIAL1_CTRL__tr_par__odd 1 -#define R_SERIAL1_CTRL__tr_par_en__BITNR 9 -#define R_SERIAL1_CTRL__tr_par_en__WIDTH 1 -#define R_SERIAL1_CTRL__tr_par_en__disable 0 -#define R_SERIAL1_CTRL__tr_par_en__enable 1 -#define R_SERIAL1_CTRL__tr_bitnr__BITNR 8 -#define R_SERIAL1_CTRL__tr_bitnr__WIDTH 1 -#define R_SERIAL1_CTRL__tr_bitnr__tr_8bit 0 -#define R_SERIAL1_CTRL__tr_bitnr__tr_7bit 1 -#define R_SERIAL1_CTRL__data_out__BITNR 0 -#define R_SERIAL1_CTRL__data_out__WIDTH 8 - -#define R_SERIAL1_BAUD (IO_TYPECAST_BYTE 0xb000006b) -#define R_SERIAL1_BAUD__tr_baud__BITNR 4 -#define R_SERIAL1_BAUD__tr_baud__WIDTH 4 -#define R_SERIAL1_BAUD__tr_baud__c300Hz 0 -#define R_SERIAL1_BAUD__tr_baud__c600Hz 1 -#define R_SERIAL1_BAUD__tr_baud__c1200Hz 2 -#define R_SERIAL1_BAUD__tr_baud__c2400Hz 3 -#define R_SERIAL1_BAUD__tr_baud__c4800Hz 4 -#define R_SERIAL1_BAUD__tr_baud__c9600Hz 5 -#define R_SERIAL1_BAUD__tr_baud__c19k2Hz 6 -#define R_SERIAL1_BAUD__tr_baud__c38k4Hz 7 -#define R_SERIAL1_BAUD__tr_baud__c57k6Hz 8 -#define R_SERIAL1_BAUD__tr_baud__c115k2Hz 9 -#define R_SERIAL1_BAUD__tr_baud__c230k4Hz 10 -#define R_SERIAL1_BAUD__tr_baud__c460k8Hz 11 -#define R_SERIAL1_BAUD__tr_baud__c921k6Hz 12 -#define R_SERIAL1_BAUD__tr_baud__c1843k2Hz 13 -#define R_SERIAL1_BAUD__tr_baud__c6250kHz 14 -#define R_SERIAL1_BAUD__tr_baud__reserved 15 -#define R_SERIAL1_BAUD__rec_baud__BITNR 0 -#define R_SERIAL1_BAUD__rec_baud__WIDTH 4 -#define R_SERIAL1_BAUD__rec_baud__c300Hz 0 -#define R_SERIAL1_BAUD__rec_baud__c600Hz 1 -#define R_SERIAL1_BAUD__rec_baud__c1200Hz 2 -#define R_SERIAL1_BAUD__rec_baud__c2400Hz 3 -#define R_SERIAL1_BAUD__rec_baud__c4800Hz 4 -#define R_SERIAL1_BAUD__rec_baud__c9600Hz 5 -#define R_SERIAL1_BAUD__rec_baud__c19k2Hz 6 -#define R_SERIAL1_BAUD__rec_baud__c38k4Hz 7 -#define R_SERIAL1_BAUD__rec_baud__c57k6Hz 8 -#define R_SERIAL1_BAUD__rec_baud__c115k2Hz 9 -#define R_SERIAL1_BAUD__rec_baud__c230k4Hz 10 -#define R_SERIAL1_BAUD__rec_baud__c460k8Hz 11 -#define R_SERIAL1_BAUD__rec_baud__c921k6Hz 12 -#define R_SERIAL1_BAUD__rec_baud__c1843k2Hz 13 -#define R_SERIAL1_BAUD__rec_baud__c6250kHz 14 -#define R_SERIAL1_BAUD__rec_baud__reserved 15 - -#define R_SERIAL1_REC_CTRL (IO_TYPECAST_BYTE 0xb000006a) -#define R_SERIAL1_REC_CTRL__dma_err__BITNR 7 -#define R_SERIAL1_REC_CTRL__dma_err__WIDTH 1 -#define R_SERIAL1_REC_CTRL__dma_err__stop 0 -#define R_SERIAL1_REC_CTRL__dma_err__ignore 1 -#define R_SERIAL1_REC_CTRL__rec_enable__BITNR 6 -#define R_SERIAL1_REC_CTRL__rec_enable__WIDTH 1 -#define R_SERIAL1_REC_CTRL__rec_enable__disable 0 -#define R_SERIAL1_REC_CTRL__rec_enable__enable 1 -#define R_SERIAL1_REC_CTRL__rts___BITNR 5 -#define R_SERIAL1_REC_CTRL__rts___WIDTH 1 -#define R_SERIAL1_REC_CTRL__rts___active 0 -#define R_SERIAL1_REC_CTRL__rts___inactive 1 -#define R_SERIAL1_REC_CTRL__sampling__BITNR 4 -#define R_SERIAL1_REC_CTRL__sampling__WIDTH 1 -#define R_SERIAL1_REC_CTRL__sampling__middle 0 -#define R_SERIAL1_REC_CTRL__sampling__majority 1 -#define R_SERIAL1_REC_CTRL__rec_stick_par__BITNR 3 -#define R_SERIAL1_REC_CTRL__rec_stick_par__WIDTH 1 -#define R_SERIAL1_REC_CTRL__rec_stick_par__normal 0 -#define R_SERIAL1_REC_CTRL__rec_stick_par__stick 1 -#define R_SERIAL1_REC_CTRL__rec_par__BITNR 2 -#define R_SERIAL1_REC_CTRL__rec_par__WIDTH 1 -#define R_SERIAL1_REC_CTRL__rec_par__even 0 -#define R_SERIAL1_REC_CTRL__rec_par__odd 1 -#define R_SERIAL1_REC_CTRL__rec_par_en__BITNR 1 -#define R_SERIAL1_REC_CTRL__rec_par_en__WIDTH 1 -#define R_SERIAL1_REC_CTRL__rec_par_en__disable 0 -#define R_SERIAL1_REC_CTRL__rec_par_en__enable 1 -#define R_SERIAL1_REC_CTRL__rec_bitnr__BITNR 0 -#define R_SERIAL1_REC_CTRL__rec_bitnr__WIDTH 1 -#define R_SERIAL1_REC_CTRL__rec_bitnr__rec_8bit 0 -#define R_SERIAL1_REC_CTRL__rec_bitnr__rec_7bit 1 - -#define R_SERIAL1_TR_CTRL (IO_TYPECAST_BYTE 0xb0000069) -#define R_SERIAL1_TR_CTRL__txd__BITNR 7 -#define R_SERIAL1_TR_CTRL__txd__WIDTH 1 -#define R_SERIAL1_TR_CTRL__tr_enable__BITNR 6 -#define R_SERIAL1_TR_CTRL__tr_enable__WIDTH 1 -#define R_SERIAL1_TR_CTRL__tr_enable__disable 0 -#define R_SERIAL1_TR_CTRL__tr_enable__enable 1 -#define R_SERIAL1_TR_CTRL__auto_cts__BITNR 5 -#define R_SERIAL1_TR_CTRL__auto_cts__WIDTH 1 -#define R_SERIAL1_TR_CTRL__auto_cts__disabled 0 -#define R_SERIAL1_TR_CTRL__auto_cts__active 1 -#define R_SERIAL1_TR_CTRL__stop_bits__BITNR 4 -#define R_SERIAL1_TR_CTRL__stop_bits__WIDTH 1 -#define R_SERIAL1_TR_CTRL__stop_bits__one_bit 0 -#define R_SERIAL1_TR_CTRL__stop_bits__two_bits 1 -#define R_SERIAL1_TR_CTRL__tr_stick_par__BITNR 3 -#define R_SERIAL1_TR_CTRL__tr_stick_par__WIDTH 1 -#define R_SERIAL1_TR_CTRL__tr_stick_par__normal 0 -#define R_SERIAL1_TR_CTRL__tr_stick_par__stick 1 -#define R_SERIAL1_TR_CTRL__tr_par__BITNR 2 -#define R_SERIAL1_TR_CTRL__tr_par__WIDTH 1 -#define R_SERIAL1_TR_CTRL__tr_par__even 0 -#define R_SERIAL1_TR_CTRL__tr_par__odd 1 -#define R_SERIAL1_TR_CTRL__tr_par_en__BITNR 1 -#define R_SERIAL1_TR_CTRL__tr_par_en__WIDTH 1 -#define R_SERIAL1_TR_CTRL__tr_par_en__disable 0 -#define R_SERIAL1_TR_CTRL__tr_par_en__enable 1 -#define R_SERIAL1_TR_CTRL__tr_bitnr__BITNR 0 -#define R_SERIAL1_TR_CTRL__tr_bitnr__WIDTH 1 -#define R_SERIAL1_TR_CTRL__tr_bitnr__tr_8bit 0 -#define R_SERIAL1_TR_CTRL__tr_bitnr__tr_7bit 1 - -#define R_SERIAL1_TR_DATA (IO_TYPECAST_BYTE 0xb0000068) -#define R_SERIAL1_TR_DATA__data_out__BITNR 0 -#define R_SERIAL1_TR_DATA__data_out__WIDTH 8 - -#define R_SERIAL1_READ (IO_TYPECAST_RO_UDWORD 0xb0000068) -#define R_SERIAL1_READ__xoff_detect__BITNR 15 -#define R_SERIAL1_READ__xoff_detect__WIDTH 1 -#define R_SERIAL1_READ__xoff_detect__no_xoff 0 -#define R_SERIAL1_READ__xoff_detect__xoff 1 -#define R_SERIAL1_READ__cts___BITNR 14 -#define R_SERIAL1_READ__cts___WIDTH 1 -#define R_SERIAL1_READ__cts___active 0 -#define R_SERIAL1_READ__cts___inactive 1 -#define R_SERIAL1_READ__tr_ready__BITNR 13 -#define R_SERIAL1_READ__tr_ready__WIDTH 1 -#define R_SERIAL1_READ__tr_ready__full 0 -#define R_SERIAL1_READ__tr_ready__ready 1 -#define R_SERIAL1_READ__rxd__BITNR 12 -#define R_SERIAL1_READ__rxd__WIDTH 1 -#define R_SERIAL1_READ__overrun__BITNR 11 -#define R_SERIAL1_READ__overrun__WIDTH 1 -#define R_SERIAL1_READ__overrun__no 0 -#define R_SERIAL1_READ__overrun__yes 1 -#define R_SERIAL1_READ__par_err__BITNR 10 -#define R_SERIAL1_READ__par_err__WIDTH 1 -#define R_SERIAL1_READ__par_err__no 0 -#define R_SERIAL1_READ__par_err__yes 1 -#define R_SERIAL1_READ__framing_err__BITNR 9 -#define R_SERIAL1_READ__framing_err__WIDTH 1 -#define R_SERIAL1_READ__framing_err__no 0 -#define R_SERIAL1_READ__framing_err__yes 1 -#define R_SERIAL1_READ__data_avail__BITNR 8 -#define R_SERIAL1_READ__data_avail__WIDTH 1 -#define R_SERIAL1_READ__data_avail__no 0 -#define R_SERIAL1_READ__data_avail__yes 1 -#define R_SERIAL1_READ__data_in__BITNR 0 -#define R_SERIAL1_READ__data_in__WIDTH 8 - -#define R_SERIAL1_STATUS (IO_TYPECAST_RO_BYTE 0xb0000069) -#define R_SERIAL1_STATUS__xoff_detect__BITNR 7 -#define R_SERIAL1_STATUS__xoff_detect__WIDTH 1 -#define R_SERIAL1_STATUS__xoff_detect__no_xoff 0 -#define R_SERIAL1_STATUS__xoff_detect__xoff 1 -#define R_SERIAL1_STATUS__cts___BITNR 6 -#define R_SERIAL1_STATUS__cts___WIDTH 1 -#define R_SERIAL1_STATUS__cts___active 0 -#define R_SERIAL1_STATUS__cts___inactive 1 -#define R_SERIAL1_STATUS__tr_ready__BITNR 5 -#define R_SERIAL1_STATUS__tr_ready__WIDTH 1 -#define R_SERIAL1_STATUS__tr_ready__full 0 -#define R_SERIAL1_STATUS__tr_ready__ready 1 -#define R_SERIAL1_STATUS__rxd__BITNR 4 -#define R_SERIAL1_STATUS__rxd__WIDTH 1 -#define R_SERIAL1_STATUS__overrun__BITNR 3 -#define R_SERIAL1_STATUS__overrun__WIDTH 1 -#define R_SERIAL1_STATUS__overrun__no 0 -#define R_SERIAL1_STATUS__overrun__yes 1 -#define R_SERIAL1_STATUS__par_err__BITNR 2 -#define R_SERIAL1_STATUS__par_err__WIDTH 1 -#define R_SERIAL1_STATUS__par_err__no 0 -#define R_SERIAL1_STATUS__par_err__yes 1 -#define R_SERIAL1_STATUS__framing_err__BITNR 1 -#define R_SERIAL1_STATUS__framing_err__WIDTH 1 -#define R_SERIAL1_STATUS__framing_err__no 0 -#define R_SERIAL1_STATUS__framing_err__yes 1 -#define R_SERIAL1_STATUS__data_avail__BITNR 0 -#define R_SERIAL1_STATUS__data_avail__WIDTH 1 -#define R_SERIAL1_STATUS__data_avail__no 0 -#define R_SERIAL1_STATUS__data_avail__yes 1 - -#define R_SERIAL1_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000068) -#define R_SERIAL1_REC_DATA__data_in__BITNR 0 -#define R_SERIAL1_REC_DATA__data_in__WIDTH 8 - -#define R_SERIAL1_XOFF (IO_TYPECAST_UDWORD 0xb000006c) -#define R_SERIAL1_XOFF__tx_stop__BITNR 9 -#define R_SERIAL1_XOFF__tx_stop__WIDTH 1 -#define R_SERIAL1_XOFF__tx_stop__enable 0 -#define R_SERIAL1_XOFF__tx_stop__stop 1 -#define R_SERIAL1_XOFF__auto_xoff__BITNR 8 -#define R_SERIAL1_XOFF__auto_xoff__WIDTH 1 -#define R_SERIAL1_XOFF__auto_xoff__disable 0 -#define R_SERIAL1_XOFF__auto_xoff__enable 1 -#define R_SERIAL1_XOFF__xoff_char__BITNR 0 -#define R_SERIAL1_XOFF__xoff_char__WIDTH 8 - -#define R_SERIAL2_CTRL (IO_TYPECAST_UDWORD 0xb0000070) -#define R_SERIAL2_CTRL__tr_baud__BITNR 28 -#define R_SERIAL2_CTRL__tr_baud__WIDTH 4 -#define R_SERIAL2_CTRL__tr_baud__c300Hz 0 -#define R_SERIAL2_CTRL__tr_baud__c600Hz 1 -#define R_SERIAL2_CTRL__tr_baud__c1200Hz 2 -#define R_SERIAL2_CTRL__tr_baud__c2400Hz 3 -#define R_SERIAL2_CTRL__tr_baud__c4800Hz 4 -#define R_SERIAL2_CTRL__tr_baud__c9600Hz 5 -#define R_SERIAL2_CTRL__tr_baud__c19k2Hz 6 -#define R_SERIAL2_CTRL__tr_baud__c38k4Hz 7 -#define R_SERIAL2_CTRL__tr_baud__c57k6Hz 8 -#define R_SERIAL2_CTRL__tr_baud__c115k2Hz 9 -#define R_SERIAL2_CTRL__tr_baud__c230k4Hz 10 -#define R_SERIAL2_CTRL__tr_baud__c460k8Hz 11 -#define R_SERIAL2_CTRL__tr_baud__c921k6Hz 12 -#define R_SERIAL2_CTRL__tr_baud__c1843k2Hz 13 -#define R_SERIAL2_CTRL__tr_baud__c6250kHz 14 -#define R_SERIAL2_CTRL__tr_baud__reserved 15 -#define R_SERIAL2_CTRL__rec_baud__BITNR 24 -#define R_SERIAL2_CTRL__rec_baud__WIDTH 4 -#define R_SERIAL2_CTRL__rec_baud__c300Hz 0 -#define R_SERIAL2_CTRL__rec_baud__c600Hz 1 -#define R_SERIAL2_CTRL__rec_baud__c1200Hz 2 -#define R_SERIAL2_CTRL__rec_baud__c2400Hz 3 -#define R_SERIAL2_CTRL__rec_baud__c4800Hz 4 -#define R_SERIAL2_CTRL__rec_baud__c9600Hz 5 -#define R_SERIAL2_CTRL__rec_baud__c19k2Hz 6 -#define R_SERIAL2_CTRL__rec_baud__c38k4Hz 7 -#define R_SERIAL2_CTRL__rec_baud__c57k6Hz 8 -#define R_SERIAL2_CTRL__rec_baud__c115k2Hz 9 -#define R_SERIAL2_CTRL__rec_baud__c230k4Hz 10 -#define R_SERIAL2_CTRL__rec_baud__c460k8Hz 11 -#define R_SERIAL2_CTRL__rec_baud__c921k6Hz 12 -#define R_SERIAL2_CTRL__rec_baud__c1843k2Hz 13 -#define R_SERIAL2_CTRL__rec_baud__c6250kHz 14 -#define R_SERIAL2_CTRL__rec_baud__reserved 15 -#define R_SERIAL2_CTRL__dma_err__BITNR 23 -#define R_SERIAL2_CTRL__dma_err__WIDTH 1 -#define R_SERIAL2_CTRL__dma_err__stop 0 -#define R_SERIAL2_CTRL__dma_err__ignore 1 -#define R_SERIAL2_CTRL__rec_enable__BITNR 22 -#define R_SERIAL2_CTRL__rec_enable__WIDTH 1 -#define R_SERIAL2_CTRL__rec_enable__disable 0 -#define R_SERIAL2_CTRL__rec_enable__enable 1 -#define R_SERIAL2_CTRL__rts___BITNR 21 -#define R_SERIAL2_CTRL__rts___WIDTH 1 -#define R_SERIAL2_CTRL__rts___active 0 -#define R_SERIAL2_CTRL__rts___inactive 1 -#define R_SERIAL2_CTRL__sampling__BITNR 20 -#define R_SERIAL2_CTRL__sampling__WIDTH 1 -#define R_SERIAL2_CTRL__sampling__middle 0 -#define R_SERIAL2_CTRL__sampling__majority 1 -#define R_SERIAL2_CTRL__rec_stick_par__BITNR 19 -#define R_SERIAL2_CTRL__rec_stick_par__WIDTH 1 -#define R_SERIAL2_CTRL__rec_stick_par__normal 0 -#define R_SERIAL2_CTRL__rec_stick_par__stick 1 -#define R_SERIAL2_CTRL__rec_par__BITNR 18 -#define R_SERIAL2_CTRL__rec_par__WIDTH 1 -#define R_SERIAL2_CTRL__rec_par__even 0 -#define R_SERIAL2_CTRL__rec_par__odd 1 -#define R_SERIAL2_CTRL__rec_par_en__BITNR 17 -#define R_SERIAL2_CTRL__rec_par_en__WIDTH 1 -#define R_SERIAL2_CTRL__rec_par_en__disable 0 -#define R_SERIAL2_CTRL__rec_par_en__enable 1 -#define R_SERIAL2_CTRL__rec_bitnr__BITNR 16 -#define R_SERIAL2_CTRL__rec_bitnr__WIDTH 1 -#define R_SERIAL2_CTRL__rec_bitnr__rec_8bit 0 -#define R_SERIAL2_CTRL__rec_bitnr__rec_7bit 1 -#define R_SERIAL2_CTRL__txd__BITNR 15 -#define R_SERIAL2_CTRL__txd__WIDTH 1 -#define R_SERIAL2_CTRL__tr_enable__BITNR 14 -#define R_SERIAL2_CTRL__tr_enable__WIDTH 1 -#define R_SERIAL2_CTRL__tr_enable__disable 0 -#define R_SERIAL2_CTRL__tr_enable__enable 1 -#define R_SERIAL2_CTRL__auto_cts__BITNR 13 -#define R_SERIAL2_CTRL__auto_cts__WIDTH 1 -#define R_SERIAL2_CTRL__auto_cts__disabled 0 -#define R_SERIAL2_CTRL__auto_cts__active 1 -#define R_SERIAL2_CTRL__stop_bits__BITNR 12 -#define R_SERIAL2_CTRL__stop_bits__WIDTH 1 -#define R_SERIAL2_CTRL__stop_bits__one_bit 0 -#define R_SERIAL2_CTRL__stop_bits__two_bits 1 -#define R_SERIAL2_CTRL__tr_stick_par__BITNR 11 -#define R_SERIAL2_CTRL__tr_stick_par__WIDTH 1 -#define R_SERIAL2_CTRL__tr_stick_par__normal 0 -#define R_SERIAL2_CTRL__tr_stick_par__stick 1 -#define R_SERIAL2_CTRL__tr_par__BITNR 10 -#define R_SERIAL2_CTRL__tr_par__WIDTH 1 -#define R_SERIAL2_CTRL__tr_par__even 0 -#define R_SERIAL2_CTRL__tr_par__odd 1 -#define R_SERIAL2_CTRL__tr_par_en__BITNR 9 -#define R_SERIAL2_CTRL__tr_par_en__WIDTH 1 -#define R_SERIAL2_CTRL__tr_par_en__disable 0 -#define R_SERIAL2_CTRL__tr_par_en__enable 1 -#define R_SERIAL2_CTRL__tr_bitnr__BITNR 8 -#define R_SERIAL2_CTRL__tr_bitnr__WIDTH 1 -#define R_SERIAL2_CTRL__tr_bitnr__tr_8bit 0 -#define R_SERIAL2_CTRL__tr_bitnr__tr_7bit 1 -#define R_SERIAL2_CTRL__data_out__BITNR 0 -#define R_SERIAL2_CTRL__data_out__WIDTH 8 - -#define R_SERIAL2_BAUD (IO_TYPECAST_BYTE 0xb0000073) -#define R_SERIAL2_BAUD__tr_baud__BITNR 4 -#define R_SERIAL2_BAUD__tr_baud__WIDTH 4 -#define R_SERIAL2_BAUD__tr_baud__c300Hz 0 -#define R_SERIAL2_BAUD__tr_baud__c600Hz 1 -#define R_SERIAL2_BAUD__tr_baud__c1200Hz 2 -#define R_SERIAL2_BAUD__tr_baud__c2400Hz 3 -#define R_SERIAL2_BAUD__tr_baud__c4800Hz 4 -#define R_SERIAL2_BAUD__tr_baud__c9600Hz 5 -#define R_SERIAL2_BAUD__tr_baud__c19k2Hz 6 -#define R_SERIAL2_BAUD__tr_baud__c38k4Hz 7 -#define R_SERIAL2_BAUD__tr_baud__c57k6Hz 8 -#define R_SERIAL2_BAUD__tr_baud__c115k2Hz 9 -#define R_SERIAL2_BAUD__tr_baud__c230k4Hz 10 -#define R_SERIAL2_BAUD__tr_baud__c460k8Hz 11 -#define R_SERIAL2_BAUD__tr_baud__c921k6Hz 12 -#define R_SERIAL2_BAUD__tr_baud__c1843k2Hz 13 -#define R_SERIAL2_BAUD__tr_baud__c6250kHz 14 -#define R_SERIAL2_BAUD__tr_baud__reserved 15 -#define R_SERIAL2_BAUD__rec_baud__BITNR 0 -#define R_SERIAL2_BAUD__rec_baud__WIDTH 4 -#define R_SERIAL2_BAUD__rec_baud__c300Hz 0 -#define R_SERIAL2_BAUD__rec_baud__c600Hz 1 -#define R_SERIAL2_BAUD__rec_baud__c1200Hz 2 -#define R_SERIAL2_BAUD__rec_baud__c2400Hz 3 -#define R_SERIAL2_BAUD__rec_baud__c4800Hz 4 -#define R_SERIAL2_BAUD__rec_baud__c9600Hz 5 -#define R_SERIAL2_BAUD__rec_baud__c19k2Hz 6 -#define R_SERIAL2_BAUD__rec_baud__c38k4Hz 7 -#define R_SERIAL2_BAUD__rec_baud__c57k6Hz 8 -#define R_SERIAL2_BAUD__rec_baud__c115k2Hz 9 -#define R_SERIAL2_BAUD__rec_baud__c230k4Hz 10 -#define R_SERIAL2_BAUD__rec_baud__c460k8Hz 11 -#define R_SERIAL2_BAUD__rec_baud__c921k6Hz 12 -#define R_SERIAL2_BAUD__rec_baud__c1843k2Hz 13 -#define R_SERIAL2_BAUD__rec_baud__c6250kHz 14 -#define R_SERIAL2_BAUD__rec_baud__reserved 15 - -#define R_SERIAL2_REC_CTRL (IO_TYPECAST_BYTE 0xb0000072) -#define R_SERIAL2_REC_CTRL__dma_err__BITNR 7 -#define R_SERIAL2_REC_CTRL__dma_err__WIDTH 1 -#define R_SERIAL2_REC_CTRL__dma_err__stop 0 -#define R_SERIAL2_REC_CTRL__dma_err__ignore 1 -#define R_SERIAL2_REC_CTRL__rec_enable__BITNR 6 -#define R_SERIAL2_REC_CTRL__rec_enable__WIDTH 1 -#define R_SERIAL2_REC_CTRL__rec_enable__disable 0 -#define R_SERIAL2_REC_CTRL__rec_enable__enable 1 -#define R_SERIAL2_REC_CTRL__rts___BITNR 5 -#define R_SERIAL2_REC_CTRL__rts___WIDTH 1 -#define R_SERIAL2_REC_CTRL__rts___active 0 -#define R_SERIAL2_REC_CTRL__rts___inactive 1 -#define R_SERIAL2_REC_CTRL__sampling__BITNR 4 -#define R_SERIAL2_REC_CTRL__sampling__WIDTH 1 -#define R_SERIAL2_REC_CTRL__sampling__middle 0 -#define R_SERIAL2_REC_CTRL__sampling__majority 1 -#define R_SERIAL2_REC_CTRL__rec_stick_par__BITNR 3 -#define R_SERIAL2_REC_CTRL__rec_stick_par__WIDTH 1 -#define R_SERIAL2_REC_CTRL__rec_stick_par__normal 0 -#define R_SERIAL2_REC_CTRL__rec_stick_par__stick 1 -#define R_SERIAL2_REC_CTRL__rec_par__BITNR 2 -#define R_SERIAL2_REC_CTRL__rec_par__WIDTH 1 -#define R_SERIAL2_REC_CTRL__rec_par__even 0 -#define R_SERIAL2_REC_CTRL__rec_par__odd 1 -#define R_SERIAL2_REC_CTRL__rec_par_en__BITNR 1 -#define R_SERIAL2_REC_CTRL__rec_par_en__WIDTH 1 -#define R_SERIAL2_REC_CTRL__rec_par_en__disable 0 -#define R_SERIAL2_REC_CTRL__rec_par_en__enable 1 -#define R_SERIAL2_REC_CTRL__rec_bitnr__BITNR 0 -#define R_SERIAL2_REC_CTRL__rec_bitnr__WIDTH 1 -#define R_SERIAL2_REC_CTRL__rec_bitnr__rec_8bit 0 -#define R_SERIAL2_REC_CTRL__rec_bitnr__rec_7bit 1 - -#define R_SERIAL2_TR_CTRL (IO_TYPECAST_BYTE 0xb0000071) -#define R_SERIAL2_TR_CTRL__txd__BITNR 7 -#define R_SERIAL2_TR_CTRL__txd__WIDTH 1 -#define R_SERIAL2_TR_CTRL__tr_enable__BITNR 6 -#define R_SERIAL2_TR_CTRL__tr_enable__WIDTH 1 -#define R_SERIAL2_TR_CTRL__tr_enable__disable 0 -#define R_SERIAL2_TR_CTRL__tr_enable__enable 1 -#define R_SERIAL2_TR_CTRL__auto_cts__BITNR 5 -#define R_SERIAL2_TR_CTRL__auto_cts__WIDTH 1 -#define R_SERIAL2_TR_CTRL__auto_cts__disabled 0 -#define R_SERIAL2_TR_CTRL__auto_cts__active 1 -#define R_SERIAL2_TR_CTRL__stop_bits__BITNR 4 -#define R_SERIAL2_TR_CTRL__stop_bits__WIDTH 1 -#define R_SERIAL2_TR_CTRL__stop_bits__one_bit 0 -#define R_SERIAL2_TR_CTRL__stop_bits__two_bits 1 -#define R_SERIAL2_TR_CTRL__tr_stick_par__BITNR 3 -#define R_SERIAL2_TR_CTRL__tr_stick_par__WIDTH 1 -#define R_SERIAL2_TR_CTRL__tr_stick_par__normal 0 -#define R_SERIAL2_TR_CTRL__tr_stick_par__stick 1 -#define R_SERIAL2_TR_CTRL__tr_par__BITNR 2 -#define R_SERIAL2_TR_CTRL__tr_par__WIDTH 1 -#define R_SERIAL2_TR_CTRL__tr_par__even 0 -#define R_SERIAL2_TR_CTRL__tr_par__odd 1 -#define R_SERIAL2_TR_CTRL__tr_par_en__BITNR 1 -#define R_SERIAL2_TR_CTRL__tr_par_en__WIDTH 1 -#define R_SERIAL2_TR_CTRL__tr_par_en__disable 0 -#define R_SERIAL2_TR_CTRL__tr_par_en__enable 1 -#define R_SERIAL2_TR_CTRL__tr_bitnr__BITNR 0 -#define R_SERIAL2_TR_CTRL__tr_bitnr__WIDTH 1 -#define R_SERIAL2_TR_CTRL__tr_bitnr__tr_8bit 0 -#define R_SERIAL2_TR_CTRL__tr_bitnr__tr_7bit 1 - -#define R_SERIAL2_TR_DATA (IO_TYPECAST_BYTE 0xb0000070) -#define R_SERIAL2_TR_DATA__data_out__BITNR 0 -#define R_SERIAL2_TR_DATA__data_out__WIDTH 8 - -#define R_SERIAL2_READ (IO_TYPECAST_RO_UDWORD 0xb0000070) -#define R_SERIAL2_READ__xoff_detect__BITNR 15 -#define R_SERIAL2_READ__xoff_detect__WIDTH 1 -#define R_SERIAL2_READ__xoff_detect__no_xoff 0 -#define R_SERIAL2_READ__xoff_detect__xoff 1 -#define R_SERIAL2_READ__cts___BITNR 14 -#define R_SERIAL2_READ__cts___WIDTH 1 -#define R_SERIAL2_READ__cts___active 0 -#define R_SERIAL2_READ__cts___inactive 1 -#define R_SERIAL2_READ__tr_ready__BITNR 13 -#define R_SERIAL2_READ__tr_ready__WIDTH 1 -#define R_SERIAL2_READ__tr_ready__full 0 -#define R_SERIAL2_READ__tr_ready__ready 1 -#define R_SERIAL2_READ__rxd__BITNR 12 -#define R_SERIAL2_READ__rxd__WIDTH 1 -#define R_SERIAL2_READ__overrun__BITNR 11 -#define R_SERIAL2_READ__overrun__WIDTH 1 -#define R_SERIAL2_READ__overrun__no 0 -#define R_SERIAL2_READ__overrun__yes 1 -#define R_SERIAL2_READ__par_err__BITNR 10 -#define R_SERIAL2_READ__par_err__WIDTH 1 -#define R_SERIAL2_READ__par_err__no 0 -#define R_SERIAL2_READ__par_err__yes 1 -#define R_SERIAL2_READ__framing_err__BITNR 9 -#define R_SERIAL2_READ__framing_err__WIDTH 1 -#define R_SERIAL2_READ__framing_err__no 0 -#define R_SERIAL2_READ__framing_err__yes 1 -#define R_SERIAL2_READ__data_avail__BITNR 8 -#define R_SERIAL2_READ__data_avail__WIDTH 1 -#define R_SERIAL2_READ__data_avail__no 0 -#define R_SERIAL2_READ__data_avail__yes 1 -#define R_SERIAL2_READ__data_in__BITNR 0 -#define R_SERIAL2_READ__data_in__WIDTH 8 - -#define R_SERIAL2_STATUS (IO_TYPECAST_RO_BYTE 0xb0000071) -#define R_SERIAL2_STATUS__xoff_detect__BITNR 7 -#define R_SERIAL2_STATUS__xoff_detect__WIDTH 1 -#define R_SERIAL2_STATUS__xoff_detect__no_xoff 0 -#define R_SERIAL2_STATUS__xoff_detect__xoff 1 -#define R_SERIAL2_STATUS__cts___BITNR 6 -#define R_SERIAL2_STATUS__cts___WIDTH 1 -#define R_SERIAL2_STATUS__cts___active 0 -#define R_SERIAL2_STATUS__cts___inactive 1 -#define R_SERIAL2_STATUS__tr_ready__BITNR 5 -#define R_SERIAL2_STATUS__tr_ready__WIDTH 1 -#define R_SERIAL2_STATUS__tr_ready__full 0 -#define R_SERIAL2_STATUS__tr_ready__ready 1 -#define R_SERIAL2_STATUS__rxd__BITNR 4 -#define R_SERIAL2_STATUS__rxd__WIDTH 1 -#define R_SERIAL2_STATUS__overrun__BITNR 3 -#define R_SERIAL2_STATUS__overrun__WIDTH 1 -#define R_SERIAL2_STATUS__overrun__no 0 -#define R_SERIAL2_STATUS__overrun__yes 1 -#define R_SERIAL2_STATUS__par_err__BITNR 2 -#define R_SERIAL2_STATUS__par_err__WIDTH 1 -#define R_SERIAL2_STATUS__par_err__no 0 -#define R_SERIAL2_STATUS__par_err__yes 1 -#define R_SERIAL2_STATUS__framing_err__BITNR 1 -#define R_SERIAL2_STATUS__framing_err__WIDTH 1 -#define R_SERIAL2_STATUS__framing_err__no 0 -#define R_SERIAL2_STATUS__framing_err__yes 1 -#define R_SERIAL2_STATUS__data_avail__BITNR 0 -#define R_SERIAL2_STATUS__data_avail__WIDTH 1 -#define R_SERIAL2_STATUS__data_avail__no 0 -#define R_SERIAL2_STATUS__data_avail__yes 1 - -#define R_SERIAL2_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000070) -#define R_SERIAL2_REC_DATA__data_in__BITNR 0 -#define R_SERIAL2_REC_DATA__data_in__WIDTH 8 - -#define R_SERIAL2_XOFF (IO_TYPECAST_UDWORD 0xb0000074) -#define R_SERIAL2_XOFF__tx_stop__BITNR 9 -#define R_SERIAL2_XOFF__tx_stop__WIDTH 1 -#define R_SERIAL2_XOFF__tx_stop__enable 0 -#define R_SERIAL2_XOFF__tx_stop__stop 1 -#define R_SERIAL2_XOFF__auto_xoff__BITNR 8 -#define R_SERIAL2_XOFF__auto_xoff__WIDTH 1 -#define R_SERIAL2_XOFF__auto_xoff__disable 0 -#define R_SERIAL2_XOFF__auto_xoff__enable 1 -#define R_SERIAL2_XOFF__xoff_char__BITNR 0 -#define R_SERIAL2_XOFF__xoff_char__WIDTH 8 - -#define R_SERIAL3_CTRL (IO_TYPECAST_UDWORD 0xb0000078) -#define R_SERIAL3_CTRL__tr_baud__BITNR 28 -#define R_SERIAL3_CTRL__tr_baud__WIDTH 4 -#define R_SERIAL3_CTRL__tr_baud__c300Hz 0 -#define R_SERIAL3_CTRL__tr_baud__c600Hz 1 -#define R_SERIAL3_CTRL__tr_baud__c1200Hz 2 -#define R_SERIAL3_CTRL__tr_baud__c2400Hz 3 -#define R_SERIAL3_CTRL__tr_baud__c4800Hz 4 -#define R_SERIAL3_CTRL__tr_baud__c9600Hz 5 -#define R_SERIAL3_CTRL__tr_baud__c19k2Hz 6 -#define R_SERIAL3_CTRL__tr_baud__c38k4Hz 7 -#define R_SERIAL3_CTRL__tr_baud__c57k6Hz 8 -#define R_SERIAL3_CTRL__tr_baud__c115k2Hz 9 -#define R_SERIAL3_CTRL__tr_baud__c230k4Hz 10 -#define R_SERIAL3_CTRL__tr_baud__c460k8Hz 11 -#define R_SERIAL3_CTRL__tr_baud__c921k6Hz 12 -#define R_SERIAL3_CTRL__tr_baud__c1843k2Hz 13 -#define R_SERIAL3_CTRL__tr_baud__c6250kHz 14 -#define R_SERIAL3_CTRL__tr_baud__reserved 15 -#define R_SERIAL3_CTRL__rec_baud__BITNR 24 -#define R_SERIAL3_CTRL__rec_baud__WIDTH 4 -#define R_SERIAL3_CTRL__rec_baud__c300Hz 0 -#define R_SERIAL3_CTRL__rec_baud__c600Hz 1 -#define R_SERIAL3_CTRL__rec_baud__c1200Hz 2 -#define R_SERIAL3_CTRL__rec_baud__c2400Hz 3 -#define R_SERIAL3_CTRL__rec_baud__c4800Hz 4 -#define R_SERIAL3_CTRL__rec_baud__c9600Hz 5 -#define R_SERIAL3_CTRL__rec_baud__c19k2Hz 6 -#define R_SERIAL3_CTRL__rec_baud__c38k4Hz 7 -#define R_SERIAL3_CTRL__rec_baud__c57k6Hz 8 -#define R_SERIAL3_CTRL__rec_baud__c115k2Hz 9 -#define R_SERIAL3_CTRL__rec_baud__c230k4Hz 10 -#define R_SERIAL3_CTRL__rec_baud__c460k8Hz 11 -#define R_SERIAL3_CTRL__rec_baud__c921k6Hz 12 -#define R_SERIAL3_CTRL__rec_baud__c1843k2Hz 13 -#define R_SERIAL3_CTRL__rec_baud__c6250kHz 14 -#define R_SERIAL3_CTRL__rec_baud__reserved 15 -#define R_SERIAL3_CTRL__dma_err__BITNR 23 -#define R_SERIAL3_CTRL__dma_err__WIDTH 1 -#define R_SERIAL3_CTRL__dma_err__stop 0 -#define R_SERIAL3_CTRL__dma_err__ignore 1 -#define R_SERIAL3_CTRL__rec_enable__BITNR 22 -#define R_SERIAL3_CTRL__rec_enable__WIDTH 1 -#define R_SERIAL3_CTRL__rec_enable__disable 0 -#define R_SERIAL3_CTRL__rec_enable__enable 1 -#define R_SERIAL3_CTRL__rts___BITNR 21 -#define R_SERIAL3_CTRL__rts___WIDTH 1 -#define R_SERIAL3_CTRL__rts___active 0 -#define R_SERIAL3_CTRL__rts___inactive 1 -#define R_SERIAL3_CTRL__sampling__BITNR 20 -#define R_SERIAL3_CTRL__sampling__WIDTH 1 -#define R_SERIAL3_CTRL__sampling__middle 0 -#define R_SERIAL3_CTRL__sampling__majority 1 -#define R_SERIAL3_CTRL__rec_stick_par__BITNR 19 -#define R_SERIAL3_CTRL__rec_stick_par__WIDTH 1 -#define R_SERIAL3_CTRL__rec_stick_par__normal 0 -#define R_SERIAL3_CTRL__rec_stick_par__stick 1 -#define R_SERIAL3_CTRL__rec_par__BITNR 18 -#define R_SERIAL3_CTRL__rec_par__WIDTH 1 -#define R_SERIAL3_CTRL__rec_par__even 0 -#define R_SERIAL3_CTRL__rec_par__odd 1 -#define R_SERIAL3_CTRL__rec_par_en__BITNR 17 -#define R_SERIAL3_CTRL__rec_par_en__WIDTH 1 -#define R_SERIAL3_CTRL__rec_par_en__disable 0 -#define R_SERIAL3_CTRL__rec_par_en__enable 1 -#define R_SERIAL3_CTRL__rec_bitnr__BITNR 16 -#define R_SERIAL3_CTRL__rec_bitnr__WIDTH 1 -#define R_SERIAL3_CTRL__rec_bitnr__rec_8bit 0 -#define R_SERIAL3_CTRL__rec_bitnr__rec_7bit 1 -#define R_SERIAL3_CTRL__txd__BITNR 15 -#define R_SERIAL3_CTRL__txd__WIDTH 1 -#define R_SERIAL3_CTRL__tr_enable__BITNR 14 -#define R_SERIAL3_CTRL__tr_enable__WIDTH 1 -#define R_SERIAL3_CTRL__tr_enable__disable 0 -#define R_SERIAL3_CTRL__tr_enable__enable 1 -#define R_SERIAL3_CTRL__auto_cts__BITNR 13 -#define R_SERIAL3_CTRL__auto_cts__WIDTH 1 -#define R_SERIAL3_CTRL__auto_cts__disabled 0 -#define R_SERIAL3_CTRL__auto_cts__active 1 -#define R_SERIAL3_CTRL__stop_bits__BITNR 12 -#define R_SERIAL3_CTRL__stop_bits__WIDTH 1 -#define R_SERIAL3_CTRL__stop_bits__one_bit 0 -#define R_SERIAL3_CTRL__stop_bits__two_bits 1 -#define R_SERIAL3_CTRL__tr_stick_par__BITNR 11 -#define R_SERIAL3_CTRL__tr_stick_par__WIDTH 1 -#define R_SERIAL3_CTRL__tr_stick_par__normal 0 -#define R_SERIAL3_CTRL__tr_stick_par__stick 1 -#define R_SERIAL3_CTRL__tr_par__BITNR 10 -#define R_SERIAL3_CTRL__tr_par__WIDTH 1 -#define R_SERIAL3_CTRL__tr_par__even 0 -#define R_SERIAL3_CTRL__tr_par__odd 1 -#define R_SERIAL3_CTRL__tr_par_en__BITNR 9 -#define R_SERIAL3_CTRL__tr_par_en__WIDTH 1 -#define R_SERIAL3_CTRL__tr_par_en__disable 0 -#define R_SERIAL3_CTRL__tr_par_en__enable 1 -#define R_SERIAL3_CTRL__tr_bitnr__BITNR 8 -#define R_SERIAL3_CTRL__tr_bitnr__WIDTH 1 -#define R_SERIAL3_CTRL__tr_bitnr__tr_8bit 0 -#define R_SERIAL3_CTRL__tr_bitnr__tr_7bit 1 -#define R_SERIAL3_CTRL__data_out__BITNR 0 -#define R_SERIAL3_CTRL__data_out__WIDTH 8 - -#define R_SERIAL3_BAUD (IO_TYPECAST_BYTE 0xb000007b) -#define R_SERIAL3_BAUD__tr_baud__BITNR 4 -#define R_SERIAL3_BAUD__tr_baud__WIDTH 4 -#define R_SERIAL3_BAUD__tr_baud__c300Hz 0 -#define R_SERIAL3_BAUD__tr_baud__c600Hz 1 -#define R_SERIAL3_BAUD__tr_baud__c1200Hz 2 -#define R_SERIAL3_BAUD__tr_baud__c2400Hz 3 -#define R_SERIAL3_BAUD__tr_baud__c4800Hz 4 -#define R_SERIAL3_BAUD__tr_baud__c9600Hz 5 -#define R_SERIAL3_BAUD__tr_baud__c19k2Hz 6 -#define R_SERIAL3_BAUD__tr_baud__c38k4Hz 7 -#define R_SERIAL3_BAUD__tr_baud__c57k6Hz 8 -#define R_SERIAL3_BAUD__tr_baud__c115k2Hz 9 -#define R_SERIAL3_BAUD__tr_baud__c230k4Hz 10 -#define R_SERIAL3_BAUD__tr_baud__c460k8Hz 11 -#define R_SERIAL3_BAUD__tr_baud__c921k6Hz 12 -#define R_SERIAL3_BAUD__tr_baud__c1843k2Hz 13 -#define R_SERIAL3_BAUD__tr_baud__c6250kHz 14 -#define R_SERIAL3_BAUD__tr_baud__reserved 15 -#define R_SERIAL3_BAUD__rec_baud__BITNR 0 -#define R_SERIAL3_BAUD__rec_baud__WIDTH 4 -#define R_SERIAL3_BAUD__rec_baud__c300Hz 0 -#define R_SERIAL3_BAUD__rec_baud__c600Hz 1 -#define R_SERIAL3_BAUD__rec_baud__c1200Hz 2 -#define R_SERIAL3_BAUD__rec_baud__c2400Hz 3 -#define R_SERIAL3_BAUD__rec_baud__c4800Hz 4 -#define R_SERIAL3_BAUD__rec_baud__c9600Hz 5 -#define R_SERIAL3_BAUD__rec_baud__c19k2Hz 6 -#define R_SERIAL3_BAUD__rec_baud__c38k4Hz 7 -#define R_SERIAL3_BAUD__rec_baud__c57k6Hz 8 -#define R_SERIAL3_BAUD__rec_baud__c115k2Hz 9 -#define R_SERIAL3_BAUD__rec_baud__c230k4Hz 10 -#define R_SERIAL3_BAUD__rec_baud__c460k8Hz 11 -#define R_SERIAL3_BAUD__rec_baud__c921k6Hz 12 -#define R_SERIAL3_BAUD__rec_baud__c1843k2Hz 13 -#define R_SERIAL3_BAUD__rec_baud__c6250kHz 14 -#define R_SERIAL3_BAUD__rec_baud__reserved 15 - -#define R_SERIAL3_REC_CTRL (IO_TYPECAST_BYTE 0xb000007a) -#define R_SERIAL3_REC_CTRL__dma_err__BITNR 7 -#define R_SERIAL3_REC_CTRL__dma_err__WIDTH 1 -#define R_SERIAL3_REC_CTRL__dma_err__stop 0 -#define R_SERIAL3_REC_CTRL__dma_err__ignore 1 -#define R_SERIAL3_REC_CTRL__rec_enable__BITNR 6 -#define R_SERIAL3_REC_CTRL__rec_enable__WIDTH 1 -#define R_SERIAL3_REC_CTRL__rec_enable__disable 0 -#define R_SERIAL3_REC_CTRL__rec_enable__enable 1 -#define R_SERIAL3_REC_CTRL__rts___BITNR 5 -#define R_SERIAL3_REC_CTRL__rts___WIDTH 1 -#define R_SERIAL3_REC_CTRL__rts___active 0 -#define R_SERIAL3_REC_CTRL__rts___inactive 1 -#define R_SERIAL3_REC_CTRL__sampling__BITNR 4 -#define R_SERIAL3_REC_CTRL__sampling__WIDTH 1 -#define R_SERIAL3_REC_CTRL__sampling__middle 0 -#define R_SERIAL3_REC_CTRL__sampling__majority 1 -#define R_SERIAL3_REC_CTRL__rec_stick_par__BITNR 3 -#define R_SERIAL3_REC_CTRL__rec_stick_par__WIDTH 1 -#define R_SERIAL3_REC_CTRL__rec_stick_par__normal 0 -#define R_SERIAL3_REC_CTRL__rec_stick_par__stick 1 -#define R_SERIAL3_REC_CTRL__rec_par__BITNR 2 -#define R_SERIAL3_REC_CTRL__rec_par__WIDTH 1 -#define R_SERIAL3_REC_CTRL__rec_par__even 0 -#define R_SERIAL3_REC_CTRL__rec_par__odd 1 -#define R_SERIAL3_REC_CTRL__rec_par_en__BITNR 1 -#define R_SERIAL3_REC_CTRL__rec_par_en__WIDTH 1 -#define R_SERIAL3_REC_CTRL__rec_par_en__disable 0 -#define R_SERIAL3_REC_CTRL__rec_par_en__enable 1 -#define R_SERIAL3_REC_CTRL__rec_bitnr__BITNR 0 -#define R_SERIAL3_REC_CTRL__rec_bitnr__WIDTH 1 -#define R_SERIAL3_REC_CTRL__rec_bitnr__rec_8bit 0 -#define R_SERIAL3_REC_CTRL__rec_bitnr__rec_7bit 1 - -#define R_SERIAL3_TR_CTRL (IO_TYPECAST_BYTE 0xb0000079) -#define R_SERIAL3_TR_CTRL__txd__BITNR 7 -#define R_SERIAL3_TR_CTRL__txd__WIDTH 1 -#define R_SERIAL3_TR_CTRL__tr_enable__BITNR 6 -#define R_SERIAL3_TR_CTRL__tr_enable__WIDTH 1 -#define R_SERIAL3_TR_CTRL__tr_enable__disable 0 -#define R_SERIAL3_TR_CTRL__tr_enable__enable 1 -#define R_SERIAL3_TR_CTRL__auto_cts__BITNR 5 -#define R_SERIAL3_TR_CTRL__auto_cts__WIDTH 1 -#define R_SERIAL3_TR_CTRL__auto_cts__disabled 0 -#define R_SERIAL3_TR_CTRL__auto_cts__active 1 -#define R_SERIAL3_TR_CTRL__stop_bits__BITNR 4 -#define R_SERIAL3_TR_CTRL__stop_bits__WIDTH 1 -#define R_SERIAL3_TR_CTRL__stop_bits__one_bit 0 -#define R_SERIAL3_TR_CTRL__stop_bits__two_bits 1 -#define R_SERIAL3_TR_CTRL__tr_stick_par__BITNR 3 -#define R_SERIAL3_TR_CTRL__tr_stick_par__WIDTH 1 -#define R_SERIAL3_TR_CTRL__tr_stick_par__normal 0 -#define R_SERIAL3_TR_CTRL__tr_stick_par__stick 1 -#define R_SERIAL3_TR_CTRL__tr_par__BITNR 2 -#define R_SERIAL3_TR_CTRL__tr_par__WIDTH 1 -#define R_SERIAL3_TR_CTRL__tr_par__even 0 -#define R_SERIAL3_TR_CTRL__tr_par__odd 1 -#define R_SERIAL3_TR_CTRL__tr_par_en__BITNR 1 -#define R_SERIAL3_TR_CTRL__tr_par_en__WIDTH 1 -#define R_SERIAL3_TR_CTRL__tr_par_en__disable 0 -#define R_SERIAL3_TR_CTRL__tr_par_en__enable 1 -#define R_SERIAL3_TR_CTRL__tr_bitnr__BITNR 0 -#define R_SERIAL3_TR_CTRL__tr_bitnr__WIDTH 1 -#define R_SERIAL3_TR_CTRL__tr_bitnr__tr_8bit 0 -#define R_SERIAL3_TR_CTRL__tr_bitnr__tr_7bit 1 - -#define R_SERIAL3_TR_DATA (IO_TYPECAST_BYTE 0xb0000078) -#define R_SERIAL3_TR_DATA__data_out__BITNR 0 -#define R_SERIAL3_TR_DATA__data_out__WIDTH 8 - -#define R_SERIAL3_READ (IO_TYPECAST_RO_UDWORD 0xb0000078) -#define R_SERIAL3_READ__xoff_detect__BITNR 15 -#define R_SERIAL3_READ__xoff_detect__WIDTH 1 -#define R_SERIAL3_READ__xoff_detect__no_xoff 0 -#define R_SERIAL3_READ__xoff_detect__xoff 1 -#define R_SERIAL3_READ__cts___BITNR 14 -#define R_SERIAL3_READ__cts___WIDTH 1 -#define R_SERIAL3_READ__cts___active 0 -#define R_SERIAL3_READ__cts___inactive 1 -#define R_SERIAL3_READ__tr_ready__BITNR 13 -#define R_SERIAL3_READ__tr_ready__WIDTH 1 -#define R_SERIAL3_READ__tr_ready__full 0 -#define R_SERIAL3_READ__tr_ready__ready 1 -#define R_SERIAL3_READ__rxd__BITNR 12 -#define R_SERIAL3_READ__rxd__WIDTH 1 -#define R_SERIAL3_READ__overrun__BITNR 11 -#define R_SERIAL3_READ__overrun__WIDTH 1 -#define R_SERIAL3_READ__overrun__no 0 -#define R_SERIAL3_READ__overrun__yes 1 -#define R_SERIAL3_READ__par_err__BITNR 10 -#define R_SERIAL3_READ__par_err__WIDTH 1 -#define R_SERIAL3_READ__par_err__no 0 -#define R_SERIAL3_READ__par_err__yes 1 -#define R_SERIAL3_READ__framing_err__BITNR 9 -#define R_SERIAL3_READ__framing_err__WIDTH 1 -#define R_SERIAL3_READ__framing_err__no 0 -#define R_SERIAL3_READ__framing_err__yes 1 -#define R_SERIAL3_READ__data_avail__BITNR 8 -#define R_SERIAL3_READ__data_avail__WIDTH 1 -#define R_SERIAL3_READ__data_avail__no 0 -#define R_SERIAL3_READ__data_avail__yes 1 -#define R_SERIAL3_READ__data_in__BITNR 0 -#define R_SERIAL3_READ__data_in__WIDTH 8 - -#define R_SERIAL3_STATUS (IO_TYPECAST_RO_BYTE 0xb0000079) -#define R_SERIAL3_STATUS__xoff_detect__BITNR 7 -#define R_SERIAL3_STATUS__xoff_detect__WIDTH 1 -#define R_SERIAL3_STATUS__xoff_detect__no_xoff 0 -#define R_SERIAL3_STATUS__xoff_detect__xoff 1 -#define R_SERIAL3_STATUS__cts___BITNR 6 -#define R_SERIAL3_STATUS__cts___WIDTH 1 -#define R_SERIAL3_STATUS__cts___active 0 -#define R_SERIAL3_STATUS__cts___inactive 1 -#define R_SERIAL3_STATUS__tr_ready__BITNR 5 -#define R_SERIAL3_STATUS__tr_ready__WIDTH 1 -#define R_SERIAL3_STATUS__tr_ready__full 0 -#define R_SERIAL3_STATUS__tr_ready__ready 1 -#define R_SERIAL3_STATUS__rxd__BITNR 4 -#define R_SERIAL3_STATUS__rxd__WIDTH 1 -#define R_SERIAL3_STATUS__overrun__BITNR 3 -#define R_SERIAL3_STATUS__overrun__WIDTH 1 -#define R_SERIAL3_STATUS__overrun__no 0 -#define R_SERIAL3_STATUS__overrun__yes 1 -#define R_SERIAL3_STATUS__par_err__BITNR 2 -#define R_SERIAL3_STATUS__par_err__WIDTH 1 -#define R_SERIAL3_STATUS__par_err__no 0 -#define R_SERIAL3_STATUS__par_err__yes 1 -#define R_SERIAL3_STATUS__framing_err__BITNR 1 -#define R_SERIAL3_STATUS__framing_err__WIDTH 1 -#define R_SERIAL3_STATUS__framing_err__no 0 -#define R_SERIAL3_STATUS__framing_err__yes 1 -#define R_SERIAL3_STATUS__data_avail__BITNR 0 -#define R_SERIAL3_STATUS__data_avail__WIDTH 1 -#define R_SERIAL3_STATUS__data_avail__no 0 -#define R_SERIAL3_STATUS__data_avail__yes 1 - -#define R_SERIAL3_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000078) -#define R_SERIAL3_REC_DATA__data_in__BITNR 0 -#define R_SERIAL3_REC_DATA__data_in__WIDTH 8 - -#define R_SERIAL3_XOFF (IO_TYPECAST_UDWORD 0xb000007c) -#define R_SERIAL3_XOFF__tx_stop__BITNR 9 -#define R_SERIAL3_XOFF__tx_stop__WIDTH 1 -#define R_SERIAL3_XOFF__tx_stop__enable 0 -#define R_SERIAL3_XOFF__tx_stop__stop 1 -#define R_SERIAL3_XOFF__auto_xoff__BITNR 8 -#define R_SERIAL3_XOFF__auto_xoff__WIDTH 1 -#define R_SERIAL3_XOFF__auto_xoff__disable 0 -#define R_SERIAL3_XOFF__auto_xoff__enable 1 -#define R_SERIAL3_XOFF__xoff_char__BITNR 0 -#define R_SERIAL3_XOFF__xoff_char__WIDTH 8 - -#define R_ALT_SER_BAUDRATE (IO_TYPECAST_UDWORD 0xb000005c) -#define R_ALT_SER_BAUDRATE__ser3_tr__BITNR 28 -#define R_ALT_SER_BAUDRATE__ser3_tr__WIDTH 2 -#define R_ALT_SER_BAUDRATE__ser3_tr__normal 0 -#define R_ALT_SER_BAUDRATE__ser3_tr__prescale 1 -#define R_ALT_SER_BAUDRATE__ser3_tr__extern 2 -#define R_ALT_SER_BAUDRATE__ser3_tr__timer 3 -#define R_ALT_SER_BAUDRATE__ser3_rec__BITNR 24 -#define R_ALT_SER_BAUDRATE__ser3_rec__WIDTH 2 -#define R_ALT_SER_BAUDRATE__ser3_rec__normal 0 -#define R_ALT_SER_BAUDRATE__ser3_rec__prescale 1 -#define R_ALT_SER_BAUDRATE__ser3_rec__extern 2 -#define R_ALT_SER_BAUDRATE__ser3_rec__timer 3 -#define R_ALT_SER_BAUDRATE__ser2_tr__BITNR 20 -#define R_ALT_SER_BAUDRATE__ser2_tr__WIDTH 2 -#define R_ALT_SER_BAUDRATE__ser2_tr__normal 0 -#define R_ALT_SER_BAUDRATE__ser2_tr__prescale 1 -#define R_ALT_SER_BAUDRATE__ser2_tr__extern 2 -#define R_ALT_SER_BAUDRATE__ser2_tr__timer 3 -#define R_ALT_SER_BAUDRATE__ser2_rec__BITNR 16 -#define R_ALT_SER_BAUDRATE__ser2_rec__WIDTH 2 -#define R_ALT_SER_BAUDRATE__ser2_rec__normal 0 -#define R_ALT_SER_BAUDRATE__ser2_rec__prescale 1 -#define R_ALT_SER_BAUDRATE__ser2_rec__extern 2 -#define R_ALT_SER_BAUDRATE__ser2_rec__timer 3 -#define R_ALT_SER_BAUDRATE__ser1_tr__BITNR 12 -#define R_ALT_SER_BAUDRATE__ser1_tr__WIDTH 2 -#define R_ALT_SER_BAUDRATE__ser1_tr__normal 0 -#define R_ALT_SER_BAUDRATE__ser1_tr__prescale 1 -#define R_ALT_SER_BAUDRATE__ser1_tr__extern 2 -#define R_ALT_SER_BAUDRATE__ser1_tr__timer 3 -#define R_ALT_SER_BAUDRATE__ser1_rec__BITNR 8 -#define R_ALT_SER_BAUDRATE__ser1_rec__WIDTH 2 -#define R_ALT_SER_BAUDRATE__ser1_rec__normal 0 -#define R_ALT_SER_BAUDRATE__ser1_rec__prescale 1 -#define R_ALT_SER_BAUDRATE__ser1_rec__extern 2 -#define R_ALT_SER_BAUDRATE__ser1_rec__timer 3 -#define R_ALT_SER_BAUDRATE__ser0_tr__BITNR 4 -#define R_ALT_SER_BAUDRATE__ser0_tr__WIDTH 2 -#define R_ALT_SER_BAUDRATE__ser0_tr__normal 0 -#define R_ALT_SER_BAUDRATE__ser0_tr__prescale 1 -#define R_ALT_SER_BAUDRATE__ser0_tr__extern 2 -#define R_ALT_SER_BAUDRATE__ser0_tr__timer 3 -#define R_ALT_SER_BAUDRATE__ser0_rec__BITNR 0 -#define R_ALT_SER_BAUDRATE__ser0_rec__WIDTH 2 -#define R_ALT_SER_BAUDRATE__ser0_rec__normal 0 -#define R_ALT_SER_BAUDRATE__ser0_rec__prescale 1 -#define R_ALT_SER_BAUDRATE__ser0_rec__extern 2 -#define R_ALT_SER_BAUDRATE__ser0_rec__timer 3 - -/* -!* Network interface registers -!*/ - -#define R_NETWORK_SA_0 (IO_TYPECAST_UDWORD 0xb0000080) -#define R_NETWORK_SA_0__ma0_low__BITNR 0 -#define R_NETWORK_SA_0__ma0_low__WIDTH 32 - -#define R_NETWORK_SA_1 (IO_TYPECAST_UDWORD 0xb0000084) -#define R_NETWORK_SA_1__ma1_low__BITNR 16 -#define R_NETWORK_SA_1__ma1_low__WIDTH 16 -#define R_NETWORK_SA_1__ma0_high__BITNR 0 -#define R_NETWORK_SA_1__ma0_high__WIDTH 16 - -#define R_NETWORK_SA_2 (IO_TYPECAST_UDWORD 0xb0000088) -#define R_NETWORK_SA_2__ma1_high__BITNR 0 -#define R_NETWORK_SA_2__ma1_high__WIDTH 32 - -#define R_NETWORK_GA_0 (IO_TYPECAST_UDWORD 0xb000008c) -#define R_NETWORK_GA_0__ga_low__BITNR 0 -#define R_NETWORK_GA_0__ga_low__WIDTH 32 - -#define R_NETWORK_GA_1 (IO_TYPECAST_UDWORD 0xb0000090) -#define R_NETWORK_GA_1__ga_high__BITNR 0 -#define R_NETWORK_GA_1__ga_high__WIDTH 32 - -#define R_NETWORK_REC_CONFIG (IO_TYPECAST_UDWORD 0xb0000094) -#define R_NETWORK_REC_CONFIG__max_size__BITNR 10 -#define R_NETWORK_REC_CONFIG__max_size__WIDTH 1 -#define R_NETWORK_REC_CONFIG__max_size__size1518 0 -#define R_NETWORK_REC_CONFIG__max_size__size1522 1 -#define R_NETWORK_REC_CONFIG__duplex__BITNR 9 -#define R_NETWORK_REC_CONFIG__duplex__WIDTH 1 -#define R_NETWORK_REC_CONFIG__duplex__full 1 -#define R_NETWORK_REC_CONFIG__duplex__half 0 -#define R_NETWORK_REC_CONFIG__bad_crc__BITNR 8 -#define R_NETWORK_REC_CONFIG__bad_crc__WIDTH 1 -#define R_NETWORK_REC_CONFIG__bad_crc__receive 1 -#define R_NETWORK_REC_CONFIG__bad_crc__discard 0 -#define R_NETWORK_REC_CONFIG__oversize__BITNR 7 -#define R_NETWORK_REC_CONFIG__oversize__WIDTH 1 -#define R_NETWORK_REC_CONFIG__oversize__receive 1 -#define R_NETWORK_REC_CONFIG__oversize__discard 0 -#define R_NETWORK_REC_CONFIG__undersize__BITNR 6 -#define R_NETWORK_REC_CONFIG__undersize__WIDTH 1 -#define R_NETWORK_REC_CONFIG__undersize__receive 1 -#define R_NETWORK_REC_CONFIG__undersize__discard 0 -#define R_NETWORK_REC_CONFIG__all_roots__BITNR 5 -#define R_NETWORK_REC_CONFIG__all_roots__WIDTH 1 -#define R_NETWORK_REC_CONFIG__all_roots__receive 1 -#define R_NETWORK_REC_CONFIG__all_roots__discard 0 -#define R_NETWORK_REC_CONFIG__tr_broadcast__BITNR 4 -#define R_NETWORK_REC_CONFIG__tr_broadcast__WIDTH 1 -#define R_NETWORK_REC_CONFIG__tr_broadcast__receive 1 -#define R_NETWORK_REC_CONFIG__tr_broadcast__discard 0 -#define R_NETWORK_REC_CONFIG__broadcast__BITNR 3 -#define R_NETWORK_REC_CONFIG__broadcast__WIDTH 1 -#define R_NETWORK_REC_CONFIG__broadcast__receive 1 -#define R_NETWORK_REC_CONFIG__broadcast__discard 0 -#define R_NETWORK_REC_CONFIG__individual__BITNR 2 -#define R_NETWORK_REC_CONFIG__individual__WIDTH 1 -#define R_NETWORK_REC_CONFIG__individual__receive 1 -#define R_NETWORK_REC_CONFIG__individual__discard 0 -#define R_NETWORK_REC_CONFIG__ma1__BITNR 1 -#define R_NETWORK_REC_CONFIG__ma1__WIDTH 1 -#define R_NETWORK_REC_CONFIG__ma1__enable 1 -#define R_NETWORK_REC_CONFIG__ma1__disable 0 -#define R_NETWORK_REC_CONFIG__ma0__BITNR 0 -#define R_NETWORK_REC_CONFIG__ma0__WIDTH 1 -#define R_NETWORK_REC_CONFIG__ma0__enable 1 -#define R_NETWORK_REC_CONFIG__ma0__disable 0 - -#define R_NETWORK_GEN_CONFIG (IO_TYPECAST_UDWORD 0xb0000098) -#define R_NETWORK_GEN_CONFIG__loopback__BITNR 5 -#define R_NETWORK_GEN_CONFIG__loopback__WIDTH 1 -#define R_NETWORK_GEN_CONFIG__loopback__on 1 -#define R_NETWORK_GEN_CONFIG__loopback__off 0 -#define R_NETWORK_GEN_CONFIG__frame__BITNR 4 -#define R_NETWORK_GEN_CONFIG__frame__WIDTH 1 -#define R_NETWORK_GEN_CONFIG__frame__tokenr 1 -#define R_NETWORK_GEN_CONFIG__frame__ether 0 -#define R_NETWORK_GEN_CONFIG__vg__BITNR 3 -#define R_NETWORK_GEN_CONFIG__vg__WIDTH 1 -#define R_NETWORK_GEN_CONFIG__vg__on 1 -#define R_NETWORK_GEN_CONFIG__vg__off 0 -#define R_NETWORK_GEN_CONFIG__phy__BITNR 1 -#define R_NETWORK_GEN_CONFIG__phy__WIDTH 2 -#define R_NETWORK_GEN_CONFIG__phy__sni 0 -#define R_NETWORK_GEN_CONFIG__phy__mii_clk 1 -#define R_NETWORK_GEN_CONFIG__phy__mii_err 2 -#define R_NETWORK_GEN_CONFIG__phy__mii_req 3 -#define R_NETWORK_GEN_CONFIG__enable__BITNR 0 -#define R_NETWORK_GEN_CONFIG__enable__WIDTH 1 -#define R_NETWORK_GEN_CONFIG__enable__on 1 -#define R_NETWORK_GEN_CONFIG__enable__off 0 - -#define R_NETWORK_TR_CTRL (IO_TYPECAST_UDWORD 0xb000009c) -#define R_NETWORK_TR_CTRL__clr_error__BITNR 8 -#define R_NETWORK_TR_CTRL__clr_error__WIDTH 1 -#define R_NETWORK_TR_CTRL__clr_error__clr 1 -#define R_NETWORK_TR_CTRL__clr_error__nop 0 -#define R_NETWORK_TR_CTRL__delay__BITNR 5 -#define R_NETWORK_TR_CTRL__delay__WIDTH 1 -#define R_NETWORK_TR_CTRL__delay__d2us 1 -#define R_NETWORK_TR_CTRL__delay__none 0 -#define R_NETWORK_TR_CTRL__cancel__BITNR 4 -#define R_NETWORK_TR_CTRL__cancel__WIDTH 1 -#define R_NETWORK_TR_CTRL__cancel__do 1 -#define R_NETWORK_TR_CTRL__cancel__dont 0 -#define R_NETWORK_TR_CTRL__cd__BITNR 3 -#define R_NETWORK_TR_CTRL__cd__WIDTH 1 -#define R_NETWORK_TR_CTRL__cd__enable 0 -#define R_NETWORK_TR_CTRL__cd__disable 1 -#define R_NETWORK_TR_CTRL__cd__ack_col 0 -#define R_NETWORK_TR_CTRL__cd__ack_crs 1 -#define R_NETWORK_TR_CTRL__retry__BITNR 2 -#define R_NETWORK_TR_CTRL__retry__WIDTH 1 -#define R_NETWORK_TR_CTRL__retry__enable 0 -#define R_NETWORK_TR_CTRL__retry__disable 1 -#define R_NETWORK_TR_CTRL__pad__BITNR 1 -#define R_NETWORK_TR_CTRL__pad__WIDTH 1 -#define R_NETWORK_TR_CTRL__pad__enable 1 -#define R_NETWORK_TR_CTRL__pad__disable 0 -#define R_NETWORK_TR_CTRL__crc__BITNR 0 -#define R_NETWORK_TR_CTRL__crc__WIDTH 1 -#define R_NETWORK_TR_CTRL__crc__enable 0 -#define R_NETWORK_TR_CTRL__crc__disable 1 - -#define R_NETWORK_MGM_CTRL (IO_TYPECAST_UDWORD 0xb00000a0) -#define R_NETWORK_MGM_CTRL__txd_pins__BITNR 4 -#define R_NETWORK_MGM_CTRL__txd_pins__WIDTH 4 -#define R_NETWORK_MGM_CTRL__txer_pin__BITNR 3 -#define R_NETWORK_MGM_CTRL__txer_pin__WIDTH 1 -#define R_NETWORK_MGM_CTRL__mdck__BITNR 2 -#define R_NETWORK_MGM_CTRL__mdck__WIDTH 1 -#define R_NETWORK_MGM_CTRL__mdoe__BITNR 1 -#define R_NETWORK_MGM_CTRL__mdoe__WIDTH 1 -#define R_NETWORK_MGM_CTRL__mdoe__enable 1 -#define R_NETWORK_MGM_CTRL__mdoe__disable 0 -#define R_NETWORK_MGM_CTRL__mdio__BITNR 0 -#define R_NETWORK_MGM_CTRL__mdio__WIDTH 1 - -#define R_NETWORK_STAT (IO_TYPECAST_RO_UDWORD 0xb00000a0) -#define R_NETWORK_STAT__rxd_pins__BITNR 4 -#define R_NETWORK_STAT__rxd_pins__WIDTH 4 -#define R_NETWORK_STAT__rxer__BITNR 3 -#define R_NETWORK_STAT__rxer__WIDTH 1 -#define R_NETWORK_STAT__underrun__BITNR 2 -#define R_NETWORK_STAT__underrun__WIDTH 1 -#define R_NETWORK_STAT__underrun__yes 1 -#define R_NETWORK_STAT__underrun__no 0 -#define R_NETWORK_STAT__exc_col__BITNR 1 -#define R_NETWORK_STAT__exc_col__WIDTH 1 -#define R_NETWORK_STAT__exc_col__yes 1 -#define R_NETWORK_STAT__exc_col__no 0 -#define R_NETWORK_STAT__mdio__BITNR 0 -#define R_NETWORK_STAT__mdio__WIDTH 1 - -#define R_REC_COUNTERS (IO_TYPECAST_RO_UDWORD 0xb00000a4) -#define R_REC_COUNTERS__congestion__BITNR 24 -#define R_REC_COUNTERS__congestion__WIDTH 8 -#define R_REC_COUNTERS__oversize__BITNR 16 -#define R_REC_COUNTERS__oversize__WIDTH 8 -#define R_REC_COUNTERS__alignment_error__BITNR 8 -#define R_REC_COUNTERS__alignment_error__WIDTH 8 -#define R_REC_COUNTERS__crc_error__BITNR 0 -#define R_REC_COUNTERS__crc_error__WIDTH 8 - -#define R_TR_COUNTERS (IO_TYPECAST_RO_UDWORD 0xb00000a8) -#define R_TR_COUNTERS__deferred__BITNR 24 -#define R_TR_COUNTERS__deferred__WIDTH 8 -#define R_TR_COUNTERS__late_col__BITNR 16 -#define R_TR_COUNTERS__late_col__WIDTH 8 -#define R_TR_COUNTERS__multiple_col__BITNR 8 -#define R_TR_COUNTERS__multiple_col__WIDTH 8 -#define R_TR_COUNTERS__single_col__BITNR 0 -#define R_TR_COUNTERS__single_col__WIDTH 8 - -#define R_PHY_COUNTERS (IO_TYPECAST_RO_UDWORD 0xb00000ac) -#define R_PHY_COUNTERS__sqe_test_error__BITNR 8 -#define R_PHY_COUNTERS__sqe_test_error__WIDTH 8 -#define R_PHY_COUNTERS__carrier_loss__BITNR 0 -#define R_PHY_COUNTERS__carrier_loss__WIDTH 8 - -/* -!* Parallel printer port registers -!*/ - -#define R_PAR0_CTRL_DATA (IO_TYPECAST_UDWORD 0xb0000040) -#define R_PAR0_CTRL_DATA__peri_int__BITNR 24 -#define R_PAR0_CTRL_DATA__peri_int__WIDTH 1 -#define R_PAR0_CTRL_DATA__peri_int__ack 1 -#define R_PAR0_CTRL_DATA__peri_int__nop 0 -#define R_PAR0_CTRL_DATA__oe__BITNR 20 -#define R_PAR0_CTRL_DATA__oe__WIDTH 1 -#define R_PAR0_CTRL_DATA__oe__enable 1 -#define R_PAR0_CTRL_DATA__oe__disable 0 -#define R_PAR0_CTRL_DATA__seli__BITNR 19 -#define R_PAR0_CTRL_DATA__seli__WIDTH 1 -#define R_PAR0_CTRL_DATA__seli__active 1 -#define R_PAR0_CTRL_DATA__seli__inactive 0 -#define R_PAR0_CTRL_DATA__autofd__BITNR 18 -#define R_PAR0_CTRL_DATA__autofd__WIDTH 1 -#define R_PAR0_CTRL_DATA__autofd__active 1 -#define R_PAR0_CTRL_DATA__autofd__inactive 0 -#define R_PAR0_CTRL_DATA__strb__BITNR 17 -#define R_PAR0_CTRL_DATA__strb__WIDTH 1 -#define R_PAR0_CTRL_DATA__strb__active 1 -#define R_PAR0_CTRL_DATA__strb__inactive 0 -#define R_PAR0_CTRL_DATA__init__BITNR 16 -#define R_PAR0_CTRL_DATA__init__WIDTH 1 -#define R_PAR0_CTRL_DATA__init__active 1 -#define R_PAR0_CTRL_DATA__init__inactive 0 -#define R_PAR0_CTRL_DATA__ecp_cmd__BITNR 8 -#define R_PAR0_CTRL_DATA__ecp_cmd__WIDTH 1 -#define R_PAR0_CTRL_DATA__ecp_cmd__command 1 -#define R_PAR0_CTRL_DATA__ecp_cmd__data 0 -#define R_PAR0_CTRL_DATA__data__BITNR 0 -#define R_PAR0_CTRL_DATA__data__WIDTH 8 - -#define R_PAR0_CTRL (IO_TYPECAST_BYTE 0xb0000042) -#define R_PAR0_CTRL__ctrl__BITNR 0 -#define R_PAR0_CTRL__ctrl__WIDTH 5 - -#define R_PAR0_STATUS_DATA (IO_TYPECAST_RO_UDWORD 0xb0000040) -#define R_PAR0_STATUS_DATA__mode__BITNR 29 -#define R_PAR0_STATUS_DATA__mode__WIDTH 3 -#define R_PAR0_STATUS_DATA__mode__manual 0 -#define R_PAR0_STATUS_DATA__mode__centronics 1 -#define R_PAR0_STATUS_DATA__mode__fastbyte 2 -#define R_PAR0_STATUS_DATA__mode__nibble 3 -#define R_PAR0_STATUS_DATA__mode__byte 4 -#define R_PAR0_STATUS_DATA__mode__ecp_fwd 5 -#define R_PAR0_STATUS_DATA__mode__ecp_rev 6 -#define R_PAR0_STATUS_DATA__mode__off 7 -#define R_PAR0_STATUS_DATA__mode__epp_wr1 5 -#define R_PAR0_STATUS_DATA__mode__epp_wr2 6 -#define R_PAR0_STATUS_DATA__mode__epp_wr3 7 -#define R_PAR0_STATUS_DATA__mode__epp_rd 0 -#define R_PAR0_STATUS_DATA__perr__BITNR 28 -#define R_PAR0_STATUS_DATA__perr__WIDTH 1 -#define R_PAR0_STATUS_DATA__perr__active 1 -#define R_PAR0_STATUS_DATA__perr__inactive 0 -#define R_PAR0_STATUS_DATA__ack__BITNR 27 -#define R_PAR0_STATUS_DATA__ack__WIDTH 1 -#define R_PAR0_STATUS_DATA__ack__active 0 -#define R_PAR0_STATUS_DATA__ack__inactive 1 -#define R_PAR0_STATUS_DATA__busy__BITNR 26 -#define R_PAR0_STATUS_DATA__busy__WIDTH 1 -#define R_PAR0_STATUS_DATA__busy__active 1 -#define R_PAR0_STATUS_DATA__busy__inactive 0 -#define R_PAR0_STATUS_DATA__fault__BITNR 25 -#define R_PAR0_STATUS_DATA__fault__WIDTH 1 -#define R_PAR0_STATUS_DATA__fault__active 0 -#define R_PAR0_STATUS_DATA__fault__inactive 1 -#define R_PAR0_STATUS_DATA__sel__BITNR 24 -#define R_PAR0_STATUS_DATA__sel__WIDTH 1 -#define R_PAR0_STATUS_DATA__sel__active 1 -#define R_PAR0_STATUS_DATA__sel__inactive 0 -#define R_PAR0_STATUS_DATA__ext_mode__BITNR 23 -#define R_PAR0_STATUS_DATA__ext_mode__WIDTH 1 -#define R_PAR0_STATUS_DATA__ext_mode__enable 1 -#define R_PAR0_STATUS_DATA__ext_mode__disable 0 -#define R_PAR0_STATUS_DATA__ecp_16__BITNR 22 -#define R_PAR0_STATUS_DATA__ecp_16__WIDTH 1 -#define R_PAR0_STATUS_DATA__ecp_16__active 1 -#define R_PAR0_STATUS_DATA__ecp_16__inactive 0 -#define R_PAR0_STATUS_DATA__tr_rdy__BITNR 17 -#define R_PAR0_STATUS_DATA__tr_rdy__WIDTH 1 -#define R_PAR0_STATUS_DATA__tr_rdy__ready 1 -#define R_PAR0_STATUS_DATA__tr_rdy__busy 0 -#define R_PAR0_STATUS_DATA__dav__BITNR 16 -#define R_PAR0_STATUS_DATA__dav__WIDTH 1 -#define R_PAR0_STATUS_DATA__dav__data 1 -#define R_PAR0_STATUS_DATA__dav__nodata 0 -#define R_PAR0_STATUS_DATA__ecp_cmd__BITNR 8 -#define R_PAR0_STATUS_DATA__ecp_cmd__WIDTH 1 -#define R_PAR0_STATUS_DATA__ecp_cmd__command 1 -#define R_PAR0_STATUS_DATA__ecp_cmd__data 0 -#define R_PAR0_STATUS_DATA__data__BITNR 0 -#define R_PAR0_STATUS_DATA__data__WIDTH 8 - -#define R_PAR0_STATUS (IO_TYPECAST_RO_UWORD 0xb0000042) -#define R_PAR0_STATUS__mode__BITNR 13 -#define R_PAR0_STATUS__mode__WIDTH 3 -#define R_PAR0_STATUS__mode__manual 0 -#define R_PAR0_STATUS__mode__centronics 1 -#define R_PAR0_STATUS__mode__fastbyte 2 -#define R_PAR0_STATUS__mode__nibble 3 -#define R_PAR0_STATUS__mode__byte 4 -#define R_PAR0_STATUS__mode__ecp_fwd 5 -#define R_PAR0_STATUS__mode__ecp_rev 6 -#define R_PAR0_STATUS__mode__off 7 -#define R_PAR0_STATUS__mode__epp_wr1 5 -#define R_PAR0_STATUS__mode__epp_wr2 6 -#define R_PAR0_STATUS__mode__epp_wr3 7 -#define R_PAR0_STATUS__mode__epp_rd 0 -#define R_PAR0_STATUS__perr__BITNR 12 -#define R_PAR0_STATUS__perr__WIDTH 1 -#define R_PAR0_STATUS__perr__active 1 -#define R_PAR0_STATUS__perr__inactive 0 -#define R_PAR0_STATUS__ack__BITNR 11 -#define R_PAR0_STATUS__ack__WIDTH 1 -#define R_PAR0_STATUS__ack__active 0 -#define R_PAR0_STATUS__ack__inactive 1 -#define R_PAR0_STATUS__busy__BITNR 10 -#define R_PAR0_STATUS__busy__WIDTH 1 -#define R_PAR0_STATUS__busy__active 1 -#define R_PAR0_STATUS__busy__inactive 0 -#define R_PAR0_STATUS__fault__BITNR 9 -#define R_PAR0_STATUS__fault__WIDTH 1 -#define R_PAR0_STATUS__fault__active 0 -#define R_PAR0_STATUS__fault__inactive 1 -#define R_PAR0_STATUS__sel__BITNR 8 -#define R_PAR0_STATUS__sel__WIDTH 1 -#define R_PAR0_STATUS__sel__active 1 -#define R_PAR0_STATUS__sel__inactive 0 -#define R_PAR0_STATUS__ext_mode__BITNR 7 -#define R_PAR0_STATUS__ext_mode__WIDTH 1 -#define R_PAR0_STATUS__ext_mode__enable 1 -#define R_PAR0_STATUS__ext_mode__disable 0 -#define R_PAR0_STATUS__ecp_16__BITNR 6 -#define R_PAR0_STATUS__ecp_16__WIDTH 1 -#define R_PAR0_STATUS__ecp_16__active 1 -#define R_PAR0_STATUS__ecp_16__inactive 0 -#define R_PAR0_STATUS__tr_rdy__BITNR 1 -#define R_PAR0_STATUS__tr_rdy__WIDTH 1 -#define R_PAR0_STATUS__tr_rdy__ready 1 -#define R_PAR0_STATUS__tr_rdy__busy 0 -#define R_PAR0_STATUS__dav__BITNR 0 -#define R_PAR0_STATUS__dav__WIDTH 1 -#define R_PAR0_STATUS__dav__data 1 -#define R_PAR0_STATUS__dav__nodata 0 - -#define R_PAR_ECP16_DATA (IO_TYPECAST_UWORD 0xb0000040) -#define R_PAR_ECP16_DATA__data__BITNR 0 -#define R_PAR_ECP16_DATA__data__WIDTH 16 - -#define R_PAR0_CONFIG (IO_TYPECAST_UDWORD 0xb0000044) -#define R_PAR0_CONFIG__ioe__BITNR 25 -#define R_PAR0_CONFIG__ioe__WIDTH 1 -#define R_PAR0_CONFIG__ioe__inv 1 -#define R_PAR0_CONFIG__ioe__noninv 0 -#define R_PAR0_CONFIG__iseli__BITNR 24 -#define R_PAR0_CONFIG__iseli__WIDTH 1 -#define R_PAR0_CONFIG__iseli__inv 1 -#define R_PAR0_CONFIG__iseli__noninv 0 -#define R_PAR0_CONFIG__iautofd__BITNR 23 -#define R_PAR0_CONFIG__iautofd__WIDTH 1 -#define R_PAR0_CONFIG__iautofd__inv 1 -#define R_PAR0_CONFIG__iautofd__noninv 0 -#define R_PAR0_CONFIG__istrb__BITNR 22 -#define R_PAR0_CONFIG__istrb__WIDTH 1 -#define R_PAR0_CONFIG__istrb__inv 1 -#define R_PAR0_CONFIG__istrb__noninv 0 -#define R_PAR0_CONFIG__iinit__BITNR 21 -#define R_PAR0_CONFIG__iinit__WIDTH 1 -#define R_PAR0_CONFIG__iinit__inv 1 -#define R_PAR0_CONFIG__iinit__noninv 0 -#define R_PAR0_CONFIG__iperr__BITNR 20 -#define R_PAR0_CONFIG__iperr__WIDTH 1 -#define R_PAR0_CONFIG__iperr__inv 1 -#define R_PAR0_CONFIG__iperr__noninv 0 -#define R_PAR0_CONFIG__iack__BITNR 19 -#define R_PAR0_CONFIG__iack__WIDTH 1 -#define R_PAR0_CONFIG__iack__inv 1 -#define R_PAR0_CONFIG__iack__noninv 0 -#define R_PAR0_CONFIG__ibusy__BITNR 18 -#define R_PAR0_CONFIG__ibusy__WIDTH 1 -#define R_PAR0_CONFIG__ibusy__inv 1 -#define R_PAR0_CONFIG__ibusy__noninv 0 -#define R_PAR0_CONFIG__ifault__BITNR 17 -#define R_PAR0_CONFIG__ifault__WIDTH 1 -#define R_PAR0_CONFIG__ifault__inv 1 -#define R_PAR0_CONFIG__ifault__noninv 0 -#define R_PAR0_CONFIG__isel__BITNR 16 -#define R_PAR0_CONFIG__isel__WIDTH 1 -#define R_PAR0_CONFIG__isel__inv 1 -#define R_PAR0_CONFIG__isel__noninv 0 -#define R_PAR0_CONFIG__ext_mode__BITNR 11 -#define R_PAR0_CONFIG__ext_mode__WIDTH 1 -#define R_PAR0_CONFIG__ext_mode__enable 1 -#define R_PAR0_CONFIG__ext_mode__disable 0 -#define R_PAR0_CONFIG__wide__BITNR 10 -#define R_PAR0_CONFIG__wide__WIDTH 1 -#define R_PAR0_CONFIG__wide__enable 1 -#define R_PAR0_CONFIG__wide__disable 0 -#define R_PAR0_CONFIG__dma__BITNR 9 -#define R_PAR0_CONFIG__dma__WIDTH 1 -#define R_PAR0_CONFIG__dma__enable 1 -#define R_PAR0_CONFIG__dma__disable 0 -#define R_PAR0_CONFIG__rle_in__BITNR 8 -#define R_PAR0_CONFIG__rle_in__WIDTH 1 -#define R_PAR0_CONFIG__rle_in__enable 1 -#define R_PAR0_CONFIG__rle_in__disable 0 -#define R_PAR0_CONFIG__rle_out__BITNR 7 -#define R_PAR0_CONFIG__rle_out__WIDTH 1 -#define R_PAR0_CONFIG__rle_out__enable 1 -#define R_PAR0_CONFIG__rle_out__disable 0 -#define R_PAR0_CONFIG__enable__BITNR 6 -#define R_PAR0_CONFIG__enable__WIDTH 1 -#define R_PAR0_CONFIG__enable__on 1 -#define R_PAR0_CONFIG__enable__reset 0 -#define R_PAR0_CONFIG__force__BITNR 5 -#define R_PAR0_CONFIG__force__WIDTH 1 -#define R_PAR0_CONFIG__force__on 1 -#define R_PAR0_CONFIG__force__off 0 -#define R_PAR0_CONFIG__ign_ack__BITNR 4 -#define R_PAR0_CONFIG__ign_ack__WIDTH 1 -#define R_PAR0_CONFIG__ign_ack__ignore 1 -#define R_PAR0_CONFIG__ign_ack__wait 0 -#define R_PAR0_CONFIG__oe_ack__BITNR 3 -#define R_PAR0_CONFIG__oe_ack__WIDTH 1 -#define R_PAR0_CONFIG__oe_ack__wait_oe 1 -#define R_PAR0_CONFIG__oe_ack__dont_wait 0 -#define R_PAR0_CONFIG__oe_ack__epp_addr 1 -#define R_PAR0_CONFIG__oe_ack__epp_data 0 -#define R_PAR0_CONFIG__epp_addr_data__BITNR 3 -#define R_PAR0_CONFIG__epp_addr_data__WIDTH 1 -#define R_PAR0_CONFIG__epp_addr_data__wait_oe 1 -#define R_PAR0_CONFIG__epp_addr_data__dont_wait 0 -#define R_PAR0_CONFIG__epp_addr_data__epp_addr 1 -#define R_PAR0_CONFIG__epp_addr_data__epp_data 0 -#define R_PAR0_CONFIG__mode__BITNR 0 -#define R_PAR0_CONFIG__mode__WIDTH 3 -#define R_PAR0_CONFIG__mode__manual 0 -#define R_PAR0_CONFIG__mode__centronics 1 -#define R_PAR0_CONFIG__mode__fastbyte 2 -#define R_PAR0_CONFIG__mode__nibble 3 -#define R_PAR0_CONFIG__mode__byte 4 -#define R_PAR0_CONFIG__mode__ecp_fwd 5 -#define R_PAR0_CONFIG__mode__ecp_rev 6 -#define R_PAR0_CONFIG__mode__off 7 -#define R_PAR0_CONFIG__mode__epp_wr1 5 -#define R_PAR0_CONFIG__mode__epp_wr2 6 -#define R_PAR0_CONFIG__mode__epp_wr3 7 -#define R_PAR0_CONFIG__mode__epp_rd 0 - -#define R_PAR0_DELAY (IO_TYPECAST_UDWORD 0xb0000048) -#define R_PAR0_DELAY__fine_hold__BITNR 21 -#define R_PAR0_DELAY__fine_hold__WIDTH 3 -#define R_PAR0_DELAY__hold__BITNR 16 -#define R_PAR0_DELAY__hold__WIDTH 5 -#define R_PAR0_DELAY__fine_strb__BITNR 13 -#define R_PAR0_DELAY__fine_strb__WIDTH 3 -#define R_PAR0_DELAY__strobe__BITNR 8 -#define R_PAR0_DELAY__strobe__WIDTH 5 -#define R_PAR0_DELAY__fine_setup__BITNR 5 -#define R_PAR0_DELAY__fine_setup__WIDTH 3 -#define R_PAR0_DELAY__setup__BITNR 0 -#define R_PAR0_DELAY__setup__WIDTH 5 - -#define R_PAR1_CTRL_DATA (IO_TYPECAST_UDWORD 0xb0000050) -#define R_PAR1_CTRL_DATA__peri_int__BITNR 24 -#define R_PAR1_CTRL_DATA__peri_int__WIDTH 1 -#define R_PAR1_CTRL_DATA__peri_int__ack 1 -#define R_PAR1_CTRL_DATA__peri_int__nop 0 -#define R_PAR1_CTRL_DATA__oe__BITNR 20 -#define R_PAR1_CTRL_DATA__oe__WIDTH 1 -#define R_PAR1_CTRL_DATA__oe__enable 1 -#define R_PAR1_CTRL_DATA__oe__disable 0 -#define R_PAR1_CTRL_DATA__seli__BITNR 19 -#define R_PAR1_CTRL_DATA__seli__WIDTH 1 -#define R_PAR1_CTRL_DATA__seli__active 1 -#define R_PAR1_CTRL_DATA__seli__inactive 0 -#define R_PAR1_CTRL_DATA__autofd__BITNR 18 -#define R_PAR1_CTRL_DATA__autofd__WIDTH 1 -#define R_PAR1_CTRL_DATA__autofd__active 1 -#define R_PAR1_CTRL_DATA__autofd__inactive 0 -#define R_PAR1_CTRL_DATA__strb__BITNR 17 -#define R_PAR1_CTRL_DATA__strb__WIDTH 1 -#define R_PAR1_CTRL_DATA__strb__active 1 -#define R_PAR1_CTRL_DATA__strb__inactive 0 -#define R_PAR1_CTRL_DATA__init__BITNR 16 -#define R_PAR1_CTRL_DATA__init__WIDTH 1 -#define R_PAR1_CTRL_DATA__init__active 1 -#define R_PAR1_CTRL_DATA__init__inactive 0 -#define R_PAR1_CTRL_DATA__ecp_cmd__BITNR 8 -#define R_PAR1_CTRL_DATA__ecp_cmd__WIDTH 1 -#define R_PAR1_CTRL_DATA__ecp_cmd__command 1 -#define R_PAR1_CTRL_DATA__ecp_cmd__data 0 -#define R_PAR1_CTRL_DATA__data__BITNR 0 -#define R_PAR1_CTRL_DATA__data__WIDTH 8 - -#define R_PAR1_CTRL (IO_TYPECAST_BYTE 0xb0000052) -#define R_PAR1_CTRL__ctrl__BITNR 0 -#define R_PAR1_CTRL__ctrl__WIDTH 5 - -#define R_PAR1_STATUS_DATA (IO_TYPECAST_RO_UDWORD 0xb0000050) -#define R_PAR1_STATUS_DATA__mode__BITNR 29 -#define R_PAR1_STATUS_DATA__mode__WIDTH 3 -#define R_PAR1_STATUS_DATA__mode__manual 0 -#define R_PAR1_STATUS_DATA__mode__centronics 1 -#define R_PAR1_STATUS_DATA__mode__fastbyte 2 -#define R_PAR1_STATUS_DATA__mode__nibble 3 -#define R_PAR1_STATUS_DATA__mode__byte 4 -#define R_PAR1_STATUS_DATA__mode__ecp_fwd 5 -#define R_PAR1_STATUS_DATA__mode__ecp_rev 6 -#define R_PAR1_STATUS_DATA__mode__off 7 -#define R_PAR1_STATUS_DATA__mode__epp_wr1 5 -#define R_PAR1_STATUS_DATA__mode__epp_wr2 6 -#define R_PAR1_STATUS_DATA__mode__epp_wr3 7 -#define R_PAR1_STATUS_DATA__mode__epp_rd 0 -#define R_PAR1_STATUS_DATA__perr__BITNR 28 -#define R_PAR1_STATUS_DATA__perr__WIDTH 1 -#define R_PAR1_STATUS_DATA__perr__active 1 -#define R_PAR1_STATUS_DATA__perr__inactive 0 -#define R_PAR1_STATUS_DATA__ack__BITNR 27 -#define R_PAR1_STATUS_DATA__ack__WIDTH 1 -#define R_PAR1_STATUS_DATA__ack__active 0 -#define R_PAR1_STATUS_DATA__ack__inactive 1 -#define R_PAR1_STATUS_DATA__busy__BITNR 26 -#define R_PAR1_STATUS_DATA__busy__WIDTH 1 -#define R_PAR1_STATUS_DATA__busy__active 1 -#define R_PAR1_STATUS_DATA__busy__inactive 0 -#define R_PAR1_STATUS_DATA__fault__BITNR 25 -#define R_PAR1_STATUS_DATA__fault__WIDTH 1 -#define R_PAR1_STATUS_DATA__fault__active 0 -#define R_PAR1_STATUS_DATA__fault__inactive 1 -#define R_PAR1_STATUS_DATA__sel__BITNR 24 -#define R_PAR1_STATUS_DATA__sel__WIDTH 1 -#define R_PAR1_STATUS_DATA__sel__active 1 -#define R_PAR1_STATUS_DATA__sel__inactive 0 -#define R_PAR1_STATUS_DATA__ext_mode__BITNR 23 -#define R_PAR1_STATUS_DATA__ext_mode__WIDTH 1 -#define R_PAR1_STATUS_DATA__ext_mode__enable 1 -#define R_PAR1_STATUS_DATA__ext_mode__disable 0 -#define R_PAR1_STATUS_DATA__tr_rdy__BITNR 17 -#define R_PAR1_STATUS_DATA__tr_rdy__WIDTH 1 -#define R_PAR1_STATUS_DATA__tr_rdy__ready 1 -#define R_PAR1_STATUS_DATA__tr_rdy__busy 0 -#define R_PAR1_STATUS_DATA__dav__BITNR 16 -#define R_PAR1_STATUS_DATA__dav__WIDTH 1 -#define R_PAR1_STATUS_DATA__dav__data 1 -#define R_PAR1_STATUS_DATA__dav__nodata 0 -#define R_PAR1_STATUS_DATA__ecp_cmd__BITNR 8 -#define R_PAR1_STATUS_DATA__ecp_cmd__WIDTH 1 -#define R_PAR1_STATUS_DATA__ecp_cmd__command 1 -#define R_PAR1_STATUS_DATA__ecp_cmd__data 0 -#define R_PAR1_STATUS_DATA__data__BITNR 0 -#define R_PAR1_STATUS_DATA__data__WIDTH 8 - -#define R_PAR1_STATUS (IO_TYPECAST_RO_UWORD 0xb0000052) -#define R_PAR1_STATUS__mode__BITNR 13 -#define R_PAR1_STATUS__mode__WIDTH 3 -#define R_PAR1_STATUS__mode__manual 0 -#define R_PAR1_STATUS__mode__centronics 1 -#define R_PAR1_STATUS__mode__fastbyte 2 -#define R_PAR1_STATUS__mode__nibble 3 -#define R_PAR1_STATUS__mode__byte 4 -#define R_PAR1_STATUS__mode__ecp_fwd 5 -#define R_PAR1_STATUS__mode__ecp_rev 6 -#define R_PAR1_STATUS__mode__off 7 -#define R_PAR1_STATUS__mode__epp_wr1 5 -#define R_PAR1_STATUS__mode__epp_wr2 6 -#define R_PAR1_STATUS__mode__epp_wr3 7 -#define R_PAR1_STATUS__mode__epp_rd 0 -#define R_PAR1_STATUS__perr__BITNR 12 -#define R_PAR1_STATUS__perr__WIDTH 1 -#define R_PAR1_STATUS__perr__active 1 -#define R_PAR1_STATUS__perr__inactive 0 -#define R_PAR1_STATUS__ack__BITNR 11 -#define R_PAR1_STATUS__ack__WIDTH 1 -#define R_PAR1_STATUS__ack__active 0 -#define R_PAR1_STATUS__ack__inactive 1 -#define R_PAR1_STATUS__busy__BITNR 10 -#define R_PAR1_STATUS__busy__WIDTH 1 -#define R_PAR1_STATUS__busy__active 1 -#define R_PAR1_STATUS__busy__inactive 0 -#define R_PAR1_STATUS__fault__BITNR 9 -#define R_PAR1_STATUS__fault__WIDTH 1 -#define R_PAR1_STATUS__fault__active 0 -#define R_PAR1_STATUS__fault__inactive 1 -#define R_PAR1_STATUS__sel__BITNR 8 -#define R_PAR1_STATUS__sel__WIDTH 1 -#define R_PAR1_STATUS__sel__active 1 -#define R_PAR1_STATUS__sel__inactive 0 -#define R_PAR1_STATUS__ext_mode__BITNR 7 -#define R_PAR1_STATUS__ext_mode__WIDTH 1 -#define R_PAR1_STATUS__ext_mode__enable 1 -#define R_PAR1_STATUS__ext_mode__disable 0 -#define R_PAR1_STATUS__tr_rdy__BITNR 1 -#define R_PAR1_STATUS__tr_rdy__WIDTH 1 -#define R_PAR1_STATUS__tr_rdy__ready 1 -#define R_PAR1_STATUS__tr_rdy__busy 0 -#define R_PAR1_STATUS__dav__BITNR 0 -#define R_PAR1_STATUS__dav__WIDTH 1 -#define R_PAR1_STATUS__dav__data 1 -#define R_PAR1_STATUS__dav__nodata 0 - -#define R_PAR1_CONFIG (IO_TYPECAST_UDWORD 0xb0000054) -#define R_PAR1_CONFIG__ioe__BITNR 25 -#define R_PAR1_CONFIG__ioe__WIDTH 1 -#define R_PAR1_CONFIG__ioe__inv 1 -#define R_PAR1_CONFIG__ioe__noninv 0 -#define R_PAR1_CONFIG__iseli__BITNR 24 -#define R_PAR1_CONFIG__iseli__WIDTH 1 -#define R_PAR1_CONFIG__iseli__inv 1 -#define R_PAR1_CONFIG__iseli__noninv 0 -#define R_PAR1_CONFIG__iautofd__BITNR 23 -#define R_PAR1_CONFIG__iautofd__WIDTH 1 -#define R_PAR1_CONFIG__iautofd__inv 1 -#define R_PAR1_CONFIG__iautofd__noninv 0 -#define R_PAR1_CONFIG__istrb__BITNR 22 -#define R_PAR1_CONFIG__istrb__WIDTH 1 -#define R_PAR1_CONFIG__istrb__inv 1 -#define R_PAR1_CONFIG__istrb__noninv 0 -#define R_PAR1_CONFIG__iinit__BITNR 21 -#define R_PAR1_CONFIG__iinit__WIDTH 1 -#define R_PAR1_CONFIG__iinit__inv 1 -#define R_PAR1_CONFIG__iinit__noninv 0 -#define R_PAR1_CONFIG__iperr__BITNR 20 -#define R_PAR1_CONFIG__iperr__WIDTH 1 -#define R_PAR1_CONFIG__iperr__inv 1 -#define R_PAR1_CONFIG__iperr__noninv 0 -#define R_PAR1_CONFIG__iack__BITNR 19 -#define R_PAR1_CONFIG__iack__WIDTH 1 -#define R_PAR1_CONFIG__iack__inv 1 -#define R_PAR1_CONFIG__iack__noninv 0 -#define R_PAR1_CONFIG__ibusy__BITNR 18 -#define R_PAR1_CONFIG__ibusy__WIDTH 1 -#define R_PAR1_CONFIG__ibusy__inv 1 -#define R_PAR1_CONFIG__ibusy__noninv 0 -#define R_PAR1_CONFIG__ifault__BITNR 17 -#define R_PAR1_CONFIG__ifault__WIDTH 1 -#define R_PAR1_CONFIG__ifault__inv 1 -#define R_PAR1_CONFIG__ifault__noninv 0 -#define R_PAR1_CONFIG__isel__BITNR 16 -#define R_PAR1_CONFIG__isel__WIDTH 1 -#define R_PAR1_CONFIG__isel__inv 1 -#define R_PAR1_CONFIG__isel__noninv 0 -#define R_PAR1_CONFIG__ext_mode__BITNR 11 -#define R_PAR1_CONFIG__ext_mode__WIDTH 1 -#define R_PAR1_CONFIG__ext_mode__enable 1 -#define R_PAR1_CONFIG__ext_mode__disable 0 -#define R_PAR1_CONFIG__dma__BITNR 9 -#define R_PAR1_CONFIG__dma__WIDTH 1 -#define R_PAR1_CONFIG__dma__enable 1 -#define R_PAR1_CONFIG__dma__disable 0 -#define R_PAR1_CONFIG__rle_in__BITNR 8 -#define R_PAR1_CONFIG__rle_in__WIDTH 1 -#define R_PAR1_CONFIG__rle_in__enable 1 -#define R_PAR1_CONFIG__rle_in__disable 0 -#define R_PAR1_CONFIG__rle_out__BITNR 7 -#define R_PAR1_CONFIG__rle_out__WIDTH 1 -#define R_PAR1_CONFIG__rle_out__enable 1 -#define R_PAR1_CONFIG__rle_out__disable 0 -#define R_PAR1_CONFIG__enable__BITNR 6 -#define R_PAR1_CONFIG__enable__WIDTH 1 -#define R_PAR1_CONFIG__enable__on 1 -#define R_PAR1_CONFIG__enable__reset 0 -#define R_PAR1_CONFIG__force__BITNR 5 -#define R_PAR1_CONFIG__force__WIDTH 1 -#define R_PAR1_CONFIG__force__on 1 -#define R_PAR1_CONFIG__force__off 0 -#define R_PAR1_CONFIG__ign_ack__BITNR 4 -#define R_PAR1_CONFIG__ign_ack__WIDTH 1 -#define R_PAR1_CONFIG__ign_ack__ignore 1 -#define R_PAR1_CONFIG__ign_ack__wait 0 -#define R_PAR1_CONFIG__oe_ack__BITNR 3 -#define R_PAR1_CONFIG__oe_ack__WIDTH 1 -#define R_PAR1_CONFIG__oe_ack__wait_oe 1 -#define R_PAR1_CONFIG__oe_ack__dont_wait 0 -#define R_PAR1_CONFIG__oe_ack__epp_addr 1 -#define R_PAR1_CONFIG__oe_ack__epp_data 0 -#define R_PAR1_CONFIG__epp_addr_data__BITNR 3 -#define R_PAR1_CONFIG__epp_addr_data__WIDTH 1 -#define R_PAR1_CONFIG__epp_addr_data__wait_oe 1 -#define R_PAR1_CONFIG__epp_addr_data__dont_wait 0 -#define R_PAR1_CONFIG__epp_addr_data__epp_addr 1 -#define R_PAR1_CONFIG__epp_addr_data__epp_data 0 -#define R_PAR1_CONFIG__mode__BITNR 0 -#define R_PAR1_CONFIG__mode__WIDTH 3 -#define R_PAR1_CONFIG__mode__manual 0 -#define R_PAR1_CONFIG__mode__centronics 1 -#define R_PAR1_CONFIG__mode__fastbyte 2 -#define R_PAR1_CONFIG__mode__nibble 3 -#define R_PAR1_CONFIG__mode__byte 4 -#define R_PAR1_CONFIG__mode__ecp_fwd 5 -#define R_PAR1_CONFIG__mode__ecp_rev 6 -#define R_PAR1_CONFIG__mode__off 7 -#define R_PAR1_CONFIG__mode__epp_wr1 5 -#define R_PAR1_CONFIG__mode__epp_wr2 6 -#define R_PAR1_CONFIG__mode__epp_wr3 7 -#define R_PAR1_CONFIG__mode__epp_rd 0 - -#define R_PAR1_DELAY (IO_TYPECAST_UDWORD 0xb0000058) -#define R_PAR1_DELAY__fine_hold__BITNR 21 -#define R_PAR1_DELAY__fine_hold__WIDTH 3 -#define R_PAR1_DELAY__hold__BITNR 16 -#define R_PAR1_DELAY__hold__WIDTH 5 -#define R_PAR1_DELAY__fine_strb__BITNR 13 -#define R_PAR1_DELAY__fine_strb__WIDTH 3 -#define R_PAR1_DELAY__strobe__BITNR 8 -#define R_PAR1_DELAY__strobe__WIDTH 5 -#define R_PAR1_DELAY__fine_setup__BITNR 5 -#define R_PAR1_DELAY__fine_setup__WIDTH 3 -#define R_PAR1_DELAY__setup__BITNR 0 -#define R_PAR1_DELAY__setup__WIDTH 5 - -/* -!* ATA interface registers -!*/ - -#define R_ATA_CTRL_DATA (IO_TYPECAST_UDWORD 0xb0000040) -#define R_ATA_CTRL_DATA__sel__BITNR 30 -#define R_ATA_CTRL_DATA__sel__WIDTH 2 -#define R_ATA_CTRL_DATA__cs1__BITNR 29 -#define R_ATA_CTRL_DATA__cs1__WIDTH 1 -#define R_ATA_CTRL_DATA__cs1__active 1 -#define R_ATA_CTRL_DATA__cs1__inactive 0 -#define R_ATA_CTRL_DATA__cs0__BITNR 28 -#define R_ATA_CTRL_DATA__cs0__WIDTH 1 -#define R_ATA_CTRL_DATA__cs0__active 1 -#define R_ATA_CTRL_DATA__cs0__inactive 0 -#define R_ATA_CTRL_DATA__addr__BITNR 25 -#define R_ATA_CTRL_DATA__addr__WIDTH 3 -#define R_ATA_CTRL_DATA__rw__BITNR 24 -#define R_ATA_CTRL_DATA__rw__WIDTH 1 -#define R_ATA_CTRL_DATA__rw__read 1 -#define R_ATA_CTRL_DATA__rw__write 0 -#define R_ATA_CTRL_DATA__src_dst__BITNR 23 -#define R_ATA_CTRL_DATA__src_dst__WIDTH 1 -#define R_ATA_CTRL_DATA__src_dst__dma 1 -#define R_ATA_CTRL_DATA__src_dst__register 0 -#define R_ATA_CTRL_DATA__handsh__BITNR 22 -#define R_ATA_CTRL_DATA__handsh__WIDTH 1 -#define R_ATA_CTRL_DATA__handsh__dma 1 -#define R_ATA_CTRL_DATA__handsh__pio 0 -#define R_ATA_CTRL_DATA__multi__BITNR 21 -#define R_ATA_CTRL_DATA__multi__WIDTH 1 -#define R_ATA_CTRL_DATA__multi__on 1 -#define R_ATA_CTRL_DATA__multi__off 0 -#define R_ATA_CTRL_DATA__dma_size__BITNR 20 -#define R_ATA_CTRL_DATA__dma_size__WIDTH 1 -#define R_ATA_CTRL_DATA__dma_size__byte 1 -#define R_ATA_CTRL_DATA__dma_size__word 0 -#define R_ATA_CTRL_DATA__data__BITNR 0 -#define R_ATA_CTRL_DATA__data__WIDTH 16 - -#define R_ATA_STATUS_DATA (IO_TYPECAST_RO_UDWORD 0xb0000040) -#define R_ATA_STATUS_DATA__busy__BITNR 18 -#define R_ATA_STATUS_DATA__busy__WIDTH 1 -#define R_ATA_STATUS_DATA__busy__yes 1 -#define R_ATA_STATUS_DATA__busy__no 0 -#define R_ATA_STATUS_DATA__tr_rdy__BITNR 17 -#define R_ATA_STATUS_DATA__tr_rdy__WIDTH 1 -#define R_ATA_STATUS_DATA__tr_rdy__ready 1 -#define R_ATA_STATUS_DATA__tr_rdy__busy 0 -#define R_ATA_STATUS_DATA__dav__BITNR 16 -#define R_ATA_STATUS_DATA__dav__WIDTH 1 -#define R_ATA_STATUS_DATA__dav__data 1 -#define R_ATA_STATUS_DATA__dav__nodata 0 -#define R_ATA_STATUS_DATA__data__BITNR 0 -#define R_ATA_STATUS_DATA__data__WIDTH 16 - -#define R_ATA_CONFIG (IO_TYPECAST_UDWORD 0xb0000044) -#define R_ATA_CONFIG__enable__BITNR 25 -#define R_ATA_CONFIG__enable__WIDTH 1 -#define R_ATA_CONFIG__enable__on 1 -#define R_ATA_CONFIG__enable__off 0 -#define R_ATA_CONFIG__dma_strobe__BITNR 20 -#define R_ATA_CONFIG__dma_strobe__WIDTH 5 -#define R_ATA_CONFIG__dma_hold__BITNR 15 -#define R_ATA_CONFIG__dma_hold__WIDTH 5 -#define R_ATA_CONFIG__pio_setup__BITNR 10 -#define R_ATA_CONFIG__pio_setup__WIDTH 5 -#define R_ATA_CONFIG__pio_strobe__BITNR 5 -#define R_ATA_CONFIG__pio_strobe__WIDTH 5 -#define R_ATA_CONFIG__pio_hold__BITNR 0 -#define R_ATA_CONFIG__pio_hold__WIDTH 5 - -#define R_ATA_TRANSFER_CNT (IO_TYPECAST_UDWORD 0xb0000048) -#define R_ATA_TRANSFER_CNT__count__BITNR 0 -#define R_ATA_TRANSFER_CNT__count__WIDTH 17 - -/* -!* SCSI registers -!*/ - -#define R_SCSI0_CTRL (IO_TYPECAST_UDWORD 0xb0000044) -#define R_SCSI0_CTRL__id_type__BITNR 31 -#define R_SCSI0_CTRL__id_type__WIDTH 1 -#define R_SCSI0_CTRL__id_type__software 1 -#define R_SCSI0_CTRL__id_type__hardware 0 -#define R_SCSI0_CTRL__sel_timeout__BITNR 24 -#define R_SCSI0_CTRL__sel_timeout__WIDTH 7 -#define R_SCSI0_CTRL__synch_per__BITNR 16 -#define R_SCSI0_CTRL__synch_per__WIDTH 8 -#define R_SCSI0_CTRL__rst__BITNR 15 -#define R_SCSI0_CTRL__rst__WIDTH 1 -#define R_SCSI0_CTRL__rst__yes 1 -#define R_SCSI0_CTRL__rst__no 0 -#define R_SCSI0_CTRL__atn__BITNR 14 -#define R_SCSI0_CTRL__atn__WIDTH 1 -#define R_SCSI0_CTRL__atn__yes 1 -#define R_SCSI0_CTRL__atn__no 0 -#define R_SCSI0_CTRL__my_id__BITNR 9 -#define R_SCSI0_CTRL__my_id__WIDTH 4 -#define R_SCSI0_CTRL__target_id__BITNR 4 -#define R_SCSI0_CTRL__target_id__WIDTH 4 -#define R_SCSI0_CTRL__fast_20__BITNR 3 -#define R_SCSI0_CTRL__fast_20__WIDTH 1 -#define R_SCSI0_CTRL__fast_20__yes 1 -#define R_SCSI0_CTRL__fast_20__no 0 -#define R_SCSI0_CTRL__bus_width__BITNR 2 -#define R_SCSI0_CTRL__bus_width__WIDTH 1 -#define R_SCSI0_CTRL__bus_width__wide 1 -#define R_SCSI0_CTRL__bus_width__narrow 0 -#define R_SCSI0_CTRL__synch__BITNR 1 -#define R_SCSI0_CTRL__synch__WIDTH 1 -#define R_SCSI0_CTRL__synch__synch 1 -#define R_SCSI0_CTRL__synch__asynch 0 -#define R_SCSI0_CTRL__enable__BITNR 0 -#define R_SCSI0_CTRL__enable__WIDTH 1 -#define R_SCSI0_CTRL__enable__on 1 -#define R_SCSI0_CTRL__enable__off 0 - -#define R_SCSI0_CMD_DATA (IO_TYPECAST_UDWORD 0xb0000040) -#define R_SCSI0_CMD_DATA__parity_in__BITNR 26 -#define R_SCSI0_CMD_DATA__parity_in__WIDTH 1 -#define R_SCSI0_CMD_DATA__parity_in__on 0 -#define R_SCSI0_CMD_DATA__parity_in__off 1 -#define R_SCSI0_CMD_DATA__skip__BITNR 25 -#define R_SCSI0_CMD_DATA__skip__WIDTH 1 -#define R_SCSI0_CMD_DATA__skip__on 1 -#define R_SCSI0_CMD_DATA__skip__off 0 -#define R_SCSI0_CMD_DATA__clr_status__BITNR 24 -#define R_SCSI0_CMD_DATA__clr_status__WIDTH 1 -#define R_SCSI0_CMD_DATA__clr_status__yes 1 -#define R_SCSI0_CMD_DATA__clr_status__nop 0 -#define R_SCSI0_CMD_DATA__asynch_setup__BITNR 20 -#define R_SCSI0_CMD_DATA__asynch_setup__WIDTH 4 -#define R_SCSI0_CMD_DATA__command__BITNR 16 -#define R_SCSI0_CMD_DATA__command__WIDTH 4 -#define R_SCSI0_CMD_DATA__command__full_din_1 0 -#define R_SCSI0_CMD_DATA__command__full_dout_1 1 -#define R_SCSI0_CMD_DATA__command__full_stat_1 2 -#define R_SCSI0_CMD_DATA__command__resel_din 3 -#define R_SCSI0_CMD_DATA__command__resel_dout 4 -#define R_SCSI0_CMD_DATA__command__resel_stat 5 -#define R_SCSI0_CMD_DATA__command__arb_only 6 -#define R_SCSI0_CMD_DATA__command__full_din_3 8 -#define R_SCSI0_CMD_DATA__command__full_dout_3 9 -#define R_SCSI0_CMD_DATA__command__full_stat_3 10 -#define R_SCSI0_CMD_DATA__command__man_data_in 11 -#define R_SCSI0_CMD_DATA__command__man_data_out 12 -#define R_SCSI0_CMD_DATA__command__man_rat 13 -#define R_SCSI0_CMD_DATA__data_out__BITNR 0 -#define R_SCSI0_CMD_DATA__data_out__WIDTH 16 - -#define R_SCSI0_DATA (IO_TYPECAST_UWORD 0xb0000040) -#define R_SCSI0_DATA__data_out__BITNR 0 -#define R_SCSI0_DATA__data_out__WIDTH 16 - -#define R_SCSI0_CMD (IO_TYPECAST_BYTE 0xb0000042) -#define R_SCSI0_CMD__asynch_setup__BITNR 4 -#define R_SCSI0_CMD__asynch_setup__WIDTH 4 -#define R_SCSI0_CMD__command__BITNR 0 -#define R_SCSI0_CMD__command__WIDTH 4 -#define R_SCSI0_CMD__command__full_din_1 0 -#define R_SCSI0_CMD__command__full_dout_1 1 -#define R_SCSI0_CMD__command__full_stat_1 2 -#define R_SCSI0_CMD__command__resel_din 3 -#define R_SCSI0_CMD__command__resel_dout 4 -#define R_SCSI0_CMD__command__resel_stat 5 -#define R_SCSI0_CMD__command__arb_only 6 -#define R_SCSI0_CMD__command__full_din_3 8 -#define R_SCSI0_CMD__command__full_dout_3 9 -#define R_SCSI0_CMD__command__full_stat_3 10 -#define R_SCSI0_CMD__command__man_data_in 11 -#define R_SCSI0_CMD__command__man_data_out 12 -#define R_SCSI0_CMD__command__man_rat 13 - -#define R_SCSI0_STATUS_CTRL (IO_TYPECAST_BYTE 0xb0000043) -#define R_SCSI0_STATUS_CTRL__parity_in__BITNR 2 -#define R_SCSI0_STATUS_CTRL__parity_in__WIDTH 1 -#define R_SCSI0_STATUS_CTRL__parity_in__on 0 -#define R_SCSI0_STATUS_CTRL__parity_in__off 1 -#define R_SCSI0_STATUS_CTRL__skip__BITNR 1 -#define R_SCSI0_STATUS_CTRL__skip__WIDTH 1 -#define R_SCSI0_STATUS_CTRL__skip__on 1 -#define R_SCSI0_STATUS_CTRL__skip__off 0 -#define R_SCSI0_STATUS_CTRL__clr_status__BITNR 0 -#define R_SCSI0_STATUS_CTRL__clr_status__WIDTH 1 -#define R_SCSI0_STATUS_CTRL__clr_status__yes 1 -#define R_SCSI0_STATUS_CTRL__clr_status__nop 0 - -#define R_SCSI0_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000048) -#define R_SCSI0_STATUS__tst_arb_won__BITNR 23 -#define R_SCSI0_STATUS__tst_arb_won__WIDTH 1 -#define R_SCSI0_STATUS__tst_resel__BITNR 22 -#define R_SCSI0_STATUS__tst_resel__WIDTH 1 -#define R_SCSI0_STATUS__parity_error__BITNR 21 -#define R_SCSI0_STATUS__parity_error__WIDTH 1 -#define R_SCSI0_STATUS__bus_reset__BITNR 20 -#define R_SCSI0_STATUS__bus_reset__WIDTH 1 -#define R_SCSI0_STATUS__bus_reset__yes 1 -#define R_SCSI0_STATUS__bus_reset__no 0 -#define R_SCSI0_STATUS__resel_target__BITNR 15 -#define R_SCSI0_STATUS__resel_target__WIDTH 4 -#define R_SCSI0_STATUS__resel__BITNR 14 -#define R_SCSI0_STATUS__resel__WIDTH 1 -#define R_SCSI0_STATUS__resel__yes 1 -#define R_SCSI0_STATUS__resel__no 0 -#define R_SCSI0_STATUS__curr_phase__BITNR 11 -#define R_SCSI0_STATUS__curr_phase__WIDTH 3 -#define R_SCSI0_STATUS__curr_phase__ph_undef 0 -#define R_SCSI0_STATUS__curr_phase__ph_msg_in 7 -#define R_SCSI0_STATUS__curr_phase__ph_msg_out 6 -#define R_SCSI0_STATUS__curr_phase__ph_status 3 -#define R_SCSI0_STATUS__curr_phase__ph_command 2 -#define R_SCSI0_STATUS__curr_phase__ph_data_in 5 -#define R_SCSI0_STATUS__curr_phase__ph_data_out 4 -#define R_SCSI0_STATUS__curr_phase__ph_resel 1 -#define R_SCSI0_STATUS__last_seq_step__BITNR 6 -#define R_SCSI0_STATUS__last_seq_step__WIDTH 5 -#define R_SCSI0_STATUS__last_seq_step__st_bus_free 24 -#define R_SCSI0_STATUS__last_seq_step__st_arbitrate 8 -#define R_SCSI0_STATUS__last_seq_step__st_resel_req 29 -#define R_SCSI0_STATUS__last_seq_step__st_msg_1 2 -#define R_SCSI0_STATUS__last_seq_step__st_manual 28 -#define R_SCSI0_STATUS__last_seq_step__st_transf_cmd 30 -#define R_SCSI0_STATUS__last_seq_step__st_msg_2 6 -#define R_SCSI0_STATUS__last_seq_step__st_msg_3 22 -#define R_SCSI0_STATUS__last_seq_step__st_answer 3 -#define R_SCSI0_STATUS__last_seq_step__st_synch_din_perr 1 -#define R_SCSI0_STATUS__last_seq_step__st_transfer_done 15 -#define R_SCSI0_STATUS__last_seq_step__st_synch_dout 0 -#define R_SCSI0_STATUS__last_seq_step__st_asynch_dout 25 -#define R_SCSI0_STATUS__last_seq_step__st_synch_din 13 -#define R_SCSI0_STATUS__last_seq_step__st_asynch_din 9 -#define R_SCSI0_STATUS__last_seq_step__st_synch_dout_ack 4 -#define R_SCSI0_STATUS__last_seq_step__st_synch_din_ack 12 -#define R_SCSI0_STATUS__last_seq_step__st_synch_din_ack_perr 5 -#define R_SCSI0_STATUS__last_seq_step__st_asynch_dout_end 11 -#define R_SCSI0_STATUS__last_seq_step__st_iwr 27 -#define R_SCSI0_STATUS__last_seq_step__st_wait_free_disc 21 -#define R_SCSI0_STATUS__last_seq_step__st_sdp_disc 7 -#define R_SCSI0_STATUS__last_seq_step__st_cc 31 -#define R_SCSI0_STATUS__last_seq_step__st_iwr_good 14 -#define R_SCSI0_STATUS__last_seq_step__st_iwr_cc 23 -#define R_SCSI0_STATUS__last_seq_step__st_wait_free_iwr_cc 17 -#define R_SCSI0_STATUS__last_seq_step__st_wait_free_cc 20 -#define R_SCSI0_STATUS__last_seq_step__st_wait_free_sdp_disc 16 -#define R_SCSI0_STATUS__last_seq_step__st_manual_req 10 -#define R_SCSI0_STATUS__last_seq_step__st_manual_din_prot 18 -#define R_SCSI0_STATUS__valid_status__BITNR 5 -#define R_SCSI0_STATUS__valid_status__WIDTH 1 -#define R_SCSI0_STATUS__valid_status__yes 1 -#define R_SCSI0_STATUS__valid_status__no 0 -#define R_SCSI0_STATUS__seq_status__BITNR 0 -#define R_SCSI0_STATUS__seq_status__WIDTH 5 -#define R_SCSI0_STATUS__seq_status__info_seq_complete 0 -#define R_SCSI0_STATUS__seq_status__info_parity_error 1 -#define R_SCSI0_STATUS__seq_status__info_unhandled_msg_in 2 -#define R_SCSI0_STATUS__seq_status__info_unexp_ph_change 3 -#define R_SCSI0_STATUS__seq_status__info_arb_lost 4 -#define R_SCSI0_STATUS__seq_status__info_sel_timeout 5 -#define R_SCSI0_STATUS__seq_status__info_unexp_bf 6 -#define R_SCSI0_STATUS__seq_status__info_illegal_op 7 -#define R_SCSI0_STATUS__seq_status__info_rec_recvd 8 -#define R_SCSI0_STATUS__seq_status__info_reselected 9 -#define R_SCSI0_STATUS__seq_status__info_unhandled_status 10 -#define R_SCSI0_STATUS__seq_status__info_bus_reset 11 -#define R_SCSI0_STATUS__seq_status__info_illegal_bf 12 -#define R_SCSI0_STATUS__seq_status__info_bus_free 13 - -#define R_SCSI0_DATA_IN (IO_TYPECAST_RO_UWORD 0xb0000040) -#define R_SCSI0_DATA_IN__data_in__BITNR 0 -#define R_SCSI0_DATA_IN__data_in__WIDTH 16 - -#define R_SCSI1_CTRL (IO_TYPECAST_UDWORD 0xb0000054) -#define R_SCSI1_CTRL__id_type__BITNR 31 -#define R_SCSI1_CTRL__id_type__WIDTH 1 -#define R_SCSI1_CTRL__id_type__software 1 -#define R_SCSI1_CTRL__id_type__hardware 0 -#define R_SCSI1_CTRL__sel_timeout__BITNR 24 -#define R_SCSI1_CTRL__sel_timeout__WIDTH 7 -#define R_SCSI1_CTRL__synch_per__BITNR 16 -#define R_SCSI1_CTRL__synch_per__WIDTH 8 -#define R_SCSI1_CTRL__rst__BITNR 15 -#define R_SCSI1_CTRL__rst__WIDTH 1 -#define R_SCSI1_CTRL__rst__yes 1 -#define R_SCSI1_CTRL__rst__no 0 -#define R_SCSI1_CTRL__atn__BITNR 14 -#define R_SCSI1_CTRL__atn__WIDTH 1 -#define R_SCSI1_CTRL__atn__yes 1 -#define R_SCSI1_CTRL__atn__no 0 -#define R_SCSI1_CTRL__my_id__BITNR 9 -#define R_SCSI1_CTRL__my_id__WIDTH 4 -#define R_SCSI1_CTRL__target_id__BITNR 4 -#define R_SCSI1_CTRL__target_id__WIDTH 4 -#define R_SCSI1_CTRL__fast_20__BITNR 3 -#define R_SCSI1_CTRL__fast_20__WIDTH 1 -#define R_SCSI1_CTRL__fast_20__yes 1 -#define R_SCSI1_CTRL__fast_20__no 0 -#define R_SCSI1_CTRL__bus_width__BITNR 2 -#define R_SCSI1_CTRL__bus_width__WIDTH 1 -#define R_SCSI1_CTRL__bus_width__wide 1 -#define R_SCSI1_CTRL__bus_width__narrow 0 -#define R_SCSI1_CTRL__synch__BITNR 1 -#define R_SCSI1_CTRL__synch__WIDTH 1 -#define R_SCSI1_CTRL__synch__synch 1 -#define R_SCSI1_CTRL__synch__asynch 0 -#define R_SCSI1_CTRL__enable__BITNR 0 -#define R_SCSI1_CTRL__enable__WIDTH 1 -#define R_SCSI1_CTRL__enable__on 1 -#define R_SCSI1_CTRL__enable__off 0 - -#define R_SCSI1_CMD_DATA (IO_TYPECAST_UDWORD 0xb0000050) -#define R_SCSI1_CMD_DATA__parity_in__BITNR 26 -#define R_SCSI1_CMD_DATA__parity_in__WIDTH 1 -#define R_SCSI1_CMD_DATA__parity_in__on 0 -#define R_SCSI1_CMD_DATA__parity_in__off 1 -#define R_SCSI1_CMD_DATA__skip__BITNR 25 -#define R_SCSI1_CMD_DATA__skip__WIDTH 1 -#define R_SCSI1_CMD_DATA__skip__on 1 -#define R_SCSI1_CMD_DATA__skip__off 0 -#define R_SCSI1_CMD_DATA__clr_status__BITNR 24 -#define R_SCSI1_CMD_DATA__clr_status__WIDTH 1 -#define R_SCSI1_CMD_DATA__clr_status__yes 1 -#define R_SCSI1_CMD_DATA__clr_status__nop 0 -#define R_SCSI1_CMD_DATA__asynch_setup__BITNR 20 -#define R_SCSI1_CMD_DATA__asynch_setup__WIDTH 4 -#define R_SCSI1_CMD_DATA__command__BITNR 16 -#define R_SCSI1_CMD_DATA__command__WIDTH 4 -#define R_SCSI1_CMD_DATA__command__full_din_1 0 -#define R_SCSI1_CMD_DATA__command__full_dout_1 1 -#define R_SCSI1_CMD_DATA__command__full_stat_1 2 -#define R_SCSI1_CMD_DATA__command__resel_din 3 -#define R_SCSI1_CMD_DATA__command__resel_dout 4 -#define R_SCSI1_CMD_DATA__command__resel_stat 5 -#define R_SCSI1_CMD_DATA__command__arb_only 6 -#define R_SCSI1_CMD_DATA__command__full_din_3 8 -#define R_SCSI1_CMD_DATA__command__full_dout_3 9 -#define R_SCSI1_CMD_DATA__command__full_stat_3 10 -#define R_SCSI1_CMD_DATA__command__man_data_in 11 -#define R_SCSI1_CMD_DATA__command__man_data_out 12 -#define R_SCSI1_CMD_DATA__command__man_rat 13 -#define R_SCSI1_CMD_DATA__data_out__BITNR 0 -#define R_SCSI1_CMD_DATA__data_out__WIDTH 16 - -#define R_SCSI1_DATA (IO_TYPECAST_UWORD 0xb0000050) -#define R_SCSI1_DATA__data_out__BITNR 0 -#define R_SCSI1_DATA__data_out__WIDTH 16 - -#define R_SCSI1_CMD (IO_TYPECAST_BYTE 0xb0000052) -#define R_SCSI1_CMD__asynch_setup__BITNR 4 -#define R_SCSI1_CMD__asynch_setup__WIDTH 4 -#define R_SCSI1_CMD__command__BITNR 0 -#define R_SCSI1_CMD__command__WIDTH 4 -#define R_SCSI1_CMD__command__full_din_1 0 -#define R_SCSI1_CMD__command__full_dout_1 1 -#define R_SCSI1_CMD__command__full_stat_1 2 -#define R_SCSI1_CMD__command__resel_din 3 -#define R_SCSI1_CMD__command__resel_dout 4 -#define R_SCSI1_CMD__command__resel_stat 5 -#define R_SCSI1_CMD__command__arb_only 6 -#define R_SCSI1_CMD__command__full_din_3 8 -#define R_SCSI1_CMD__command__full_dout_3 9 -#define R_SCSI1_CMD__command__full_stat_3 10 -#define R_SCSI1_CMD__command__man_data_in 11 -#define R_SCSI1_CMD__command__man_data_out 12 -#define R_SCSI1_CMD__command__man_rat 13 - -#define R_SCSI1_STATUS_CTRL (IO_TYPECAST_BYTE 0xb0000053) -#define R_SCSI1_STATUS_CTRL__parity_in__BITNR 2 -#define R_SCSI1_STATUS_CTRL__parity_in__WIDTH 1 -#define R_SCSI1_STATUS_CTRL__parity_in__on 0 -#define R_SCSI1_STATUS_CTRL__parity_in__off 1 -#define R_SCSI1_STATUS_CTRL__skip__BITNR 1 -#define R_SCSI1_STATUS_CTRL__skip__WIDTH 1 -#define R_SCSI1_STATUS_CTRL__skip__on 1 -#define R_SCSI1_STATUS_CTRL__skip__off 0 -#define R_SCSI1_STATUS_CTRL__clr_status__BITNR 0 -#define R_SCSI1_STATUS_CTRL__clr_status__WIDTH 1 -#define R_SCSI1_STATUS_CTRL__clr_status__yes 1 -#define R_SCSI1_STATUS_CTRL__clr_status__nop 0 - -#define R_SCSI1_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000058) -#define R_SCSI1_STATUS__tst_arb_won__BITNR 23 -#define R_SCSI1_STATUS__tst_arb_won__WIDTH 1 -#define R_SCSI1_STATUS__tst_resel__BITNR 22 -#define R_SCSI1_STATUS__tst_resel__WIDTH 1 -#define R_SCSI1_STATUS__parity_error__BITNR 21 -#define R_SCSI1_STATUS__parity_error__WIDTH 1 -#define R_SCSI1_STATUS__bus_reset__BITNR 20 -#define R_SCSI1_STATUS__bus_reset__WIDTH 1 -#define R_SCSI1_STATUS__bus_reset__yes 1 -#define R_SCSI1_STATUS__bus_reset__no 0 -#define R_SCSI1_STATUS__resel_target__BITNR 15 -#define R_SCSI1_STATUS__resel_target__WIDTH 4 -#define R_SCSI1_STATUS__resel__BITNR 14 -#define R_SCSI1_STATUS__resel__WIDTH 1 -#define R_SCSI1_STATUS__resel__yes 1 -#define R_SCSI1_STATUS__resel__no 0 -#define R_SCSI1_STATUS__curr_phase__BITNR 11 -#define R_SCSI1_STATUS__curr_phase__WIDTH 3 -#define R_SCSI1_STATUS__curr_phase__ph_undef 0 -#define R_SCSI1_STATUS__curr_phase__ph_msg_in 7 -#define R_SCSI1_STATUS__curr_phase__ph_msg_out 6 -#define R_SCSI1_STATUS__curr_phase__ph_status 3 -#define R_SCSI1_STATUS__curr_phase__ph_command 2 -#define R_SCSI1_STATUS__curr_phase__ph_data_in 5 -#define R_SCSI1_STATUS__curr_phase__ph_data_out 4 -#define R_SCSI1_STATUS__curr_phase__ph_resel 1 -#define R_SCSI1_STATUS__last_seq_step__BITNR 6 -#define R_SCSI1_STATUS__last_seq_step__WIDTH 5 -#define R_SCSI1_STATUS__last_seq_step__st_bus_free 24 -#define R_SCSI1_STATUS__last_seq_step__st_arbitrate 8 -#define R_SCSI1_STATUS__last_seq_step__st_resel_req 29 -#define R_SCSI1_STATUS__last_seq_step__st_msg_1 2 -#define R_SCSI1_STATUS__last_seq_step__st_manual 28 -#define R_SCSI1_STATUS__last_seq_step__st_transf_cmd 30 -#define R_SCSI1_STATUS__last_seq_step__st_msg_2 6 -#define R_SCSI1_STATUS__last_seq_step__st_msg_3 22 -#define R_SCSI1_STATUS__last_seq_step__st_answer 3 -#define R_SCSI1_STATUS__last_seq_step__st_synch_din_perr 1 -#define R_SCSI1_STATUS__last_seq_step__st_transfer_done 15 -#define R_SCSI1_STATUS__last_seq_step__st_synch_dout 0 -#define R_SCSI1_STATUS__last_seq_step__st_asynch_dout 25 -#define R_SCSI1_STATUS__last_seq_step__st_synch_din 13 -#define R_SCSI1_STATUS__last_seq_step__st_asynch_din 9 -#define R_SCSI1_STATUS__last_seq_step__st_synch_dout_ack 4 -#define R_SCSI1_STATUS__last_seq_step__st_synch_din_ack 12 -#define R_SCSI1_STATUS__last_seq_step__st_synch_din_ack_perr 5 -#define R_SCSI1_STATUS__last_seq_step__st_asynch_dout_end 11 -#define R_SCSI1_STATUS__last_seq_step__st_iwr 27 -#define R_SCSI1_STATUS__last_seq_step__st_wait_free_disc 21 -#define R_SCSI1_STATUS__last_seq_step__st_sdp_disc 7 -#define R_SCSI1_STATUS__last_seq_step__st_cc 31 -#define R_SCSI1_STATUS__last_seq_step__st_iwr_good 14 -#define R_SCSI1_STATUS__last_seq_step__st_iwr_cc 23 -#define R_SCSI1_STATUS__last_seq_step__st_wait_free_iwr_cc 17 -#define R_SCSI1_STATUS__last_seq_step__st_wait_free_cc 20 -#define R_SCSI1_STATUS__last_seq_step__st_wait_free_sdp_disc 16 -#define R_SCSI1_STATUS__last_seq_step__st_manual_req 10 -#define R_SCSI1_STATUS__last_seq_step__st_manual_din_prot 18 -#define R_SCSI1_STATUS__valid_status__BITNR 5 -#define R_SCSI1_STATUS__valid_status__WIDTH 1 -#define R_SCSI1_STATUS__valid_status__yes 1 -#define R_SCSI1_STATUS__valid_status__no 0 -#define R_SCSI1_STATUS__seq_status__BITNR 0 -#define R_SCSI1_STATUS__seq_status__WIDTH 5 -#define R_SCSI1_STATUS__seq_status__info_seq_complete 0 -#define R_SCSI1_STATUS__seq_status__info_parity_error 1 -#define R_SCSI1_STATUS__seq_status__info_unhandled_msg_in 2 -#define R_SCSI1_STATUS__seq_status__info_unexp_ph_change 3 -#define R_SCSI1_STATUS__seq_status__info_arb_lost 4 -#define R_SCSI1_STATUS__seq_status__info_sel_timeout 5 -#define R_SCSI1_STATUS__seq_status__info_unexp_bf 6 -#define R_SCSI1_STATUS__seq_status__info_illegal_op 7 -#define R_SCSI1_STATUS__seq_status__info_rec_recvd 8 -#define R_SCSI1_STATUS__seq_status__info_reselected 9 -#define R_SCSI1_STATUS__seq_status__info_unhandled_status 10 -#define R_SCSI1_STATUS__seq_status__info_bus_reset 11 -#define R_SCSI1_STATUS__seq_status__info_illegal_bf 12 -#define R_SCSI1_STATUS__seq_status__info_bus_free 13 - -#define R_SCSI1_DATA_IN (IO_TYPECAST_RO_UWORD 0xb0000050) -#define R_SCSI1_DATA_IN__data_in__BITNR 0 -#define R_SCSI1_DATA_IN__data_in__WIDTH 16 - -/* -!* Interrupt mask and status registers -!*/ - -#define R_IRQ_MASK0_RD (IO_TYPECAST_RO_UDWORD 0xb00000c0) -#define R_IRQ_MASK0_RD__nmi_pin__BITNR 31 -#define R_IRQ_MASK0_RD__nmi_pin__WIDTH 1 -#define R_IRQ_MASK0_RD__nmi_pin__active 1 -#define R_IRQ_MASK0_RD__nmi_pin__inactive 0 -#define R_IRQ_MASK0_RD__watchdog_nmi__BITNR 30 -#define R_IRQ_MASK0_RD__watchdog_nmi__WIDTH 1 -#define R_IRQ_MASK0_RD__watchdog_nmi__active 1 -#define R_IRQ_MASK0_RD__watchdog_nmi__inactive 0 -#define R_IRQ_MASK0_RD__sqe_test_error__BITNR 29 -#define R_IRQ_MASK0_RD__sqe_test_error__WIDTH 1 -#define R_IRQ_MASK0_RD__sqe_test_error__active 1 -#define R_IRQ_MASK0_RD__sqe_test_error__inactive 0 -#define R_IRQ_MASK0_RD__carrier_loss__BITNR 28 -#define R_IRQ_MASK0_RD__carrier_loss__WIDTH 1 -#define R_IRQ_MASK0_RD__carrier_loss__active 1 -#define R_IRQ_MASK0_RD__carrier_loss__inactive 0 -#define R_IRQ_MASK0_RD__deferred__BITNR 27 -#define R_IRQ_MASK0_RD__deferred__WIDTH 1 -#define R_IRQ_MASK0_RD__deferred__active 1 -#define R_IRQ_MASK0_RD__deferred__inactive 0 -#define R_IRQ_MASK0_RD__late_col__BITNR 26 -#define R_IRQ_MASK0_RD__late_col__WIDTH 1 -#define R_IRQ_MASK0_RD__late_col__active 1 -#define R_IRQ_MASK0_RD__late_col__inactive 0 -#define R_IRQ_MASK0_RD__multiple_col__BITNR 25 -#define R_IRQ_MASK0_RD__multiple_col__WIDTH 1 -#define R_IRQ_MASK0_RD__multiple_col__active 1 -#define R_IRQ_MASK0_RD__multiple_col__inactive 0 -#define R_IRQ_MASK0_RD__single_col__BITNR 24 -#define R_IRQ_MASK0_RD__single_col__WIDTH 1 -#define R_IRQ_MASK0_RD__single_col__active 1 -#define R_IRQ_MASK0_RD__single_col__inactive 0 -#define R_IRQ_MASK0_RD__congestion__BITNR 23 -#define R_IRQ_MASK0_RD__congestion__WIDTH 1 -#define R_IRQ_MASK0_RD__congestion__active 1 -#define R_IRQ_MASK0_RD__congestion__inactive 0 -#define R_IRQ_MASK0_RD__oversize__BITNR 22 -#define R_IRQ_MASK0_RD__oversize__WIDTH 1 -#define R_IRQ_MASK0_RD__oversize__active 1 -#define R_IRQ_MASK0_RD__oversize__inactive 0 -#define R_IRQ_MASK0_RD__alignment_error__BITNR 21 -#define R_IRQ_MASK0_RD__alignment_error__WIDTH 1 -#define R_IRQ_MASK0_RD__alignment_error__active 1 -#define R_IRQ_MASK0_RD__alignment_error__inactive 0 -#define R_IRQ_MASK0_RD__crc_error__BITNR 20 -#define R_IRQ_MASK0_RD__crc_error__WIDTH 1 -#define R_IRQ_MASK0_RD__crc_error__active 1 -#define R_IRQ_MASK0_RD__crc_error__inactive 0 -#define R_IRQ_MASK0_RD__overrun__BITNR 19 -#define R_IRQ_MASK0_RD__overrun__WIDTH 1 -#define R_IRQ_MASK0_RD__overrun__active 1 -#define R_IRQ_MASK0_RD__overrun__inactive 0 -#define R_IRQ_MASK0_RD__underrun__BITNR 18 -#define R_IRQ_MASK0_RD__underrun__WIDTH 1 -#define R_IRQ_MASK0_RD__underrun__active 1 -#define R_IRQ_MASK0_RD__underrun__inactive 0 -#define R_IRQ_MASK0_RD__excessive_col__BITNR 17 -#define R_IRQ_MASK0_RD__excessive_col__WIDTH 1 -#define R_IRQ_MASK0_RD__excessive_col__active 1 -#define R_IRQ_MASK0_RD__excessive_col__inactive 0 -#define R_IRQ_MASK0_RD__mdio__BITNR 16 -#define R_IRQ_MASK0_RD__mdio__WIDTH 1 -#define R_IRQ_MASK0_RD__mdio__active 1 -#define R_IRQ_MASK0_RD__mdio__inactive 0 -#define R_IRQ_MASK0_RD__ata_drq3__BITNR 15 -#define R_IRQ_MASK0_RD__ata_drq3__WIDTH 1 -#define R_IRQ_MASK0_RD__ata_drq3__active 1 -#define R_IRQ_MASK0_RD__ata_drq3__inactive 0 -#define R_IRQ_MASK0_RD__ata_drq2__BITNR 14 -#define R_IRQ_MASK0_RD__ata_drq2__WIDTH 1 -#define R_IRQ_MASK0_RD__ata_drq2__active 1 -#define R_IRQ_MASK0_RD__ata_drq2__inactive 0 -#define R_IRQ_MASK0_RD__ata_drq1__BITNR 13 -#define R_IRQ_MASK0_RD__ata_drq1__WIDTH 1 -#define R_IRQ_MASK0_RD__ata_drq1__active 1 -#define R_IRQ_MASK0_RD__ata_drq1__inactive 0 -#define R_IRQ_MASK0_RD__ata_drq0__BITNR 12 -#define R_IRQ_MASK0_RD__ata_drq0__WIDTH 1 -#define R_IRQ_MASK0_RD__ata_drq0__active 1 -#define R_IRQ_MASK0_RD__ata_drq0__inactive 0 -#define R_IRQ_MASK0_RD__par0_ecp_cmd__BITNR 11 -#define R_IRQ_MASK0_RD__par0_ecp_cmd__WIDTH 1 -#define R_IRQ_MASK0_RD__par0_ecp_cmd__active 1 -#define R_IRQ_MASK0_RD__par0_ecp_cmd__inactive 0 -#define R_IRQ_MASK0_RD__ata_irq3__BITNR 11 -#define R_IRQ_MASK0_RD__ata_irq3__WIDTH 1 -#define R_IRQ_MASK0_RD__ata_irq3__active 1 -#define R_IRQ_MASK0_RD__ata_irq3__inactive 0 -#define R_IRQ_MASK0_RD__par0_peri__BITNR 10 -#define R_IRQ_MASK0_RD__par0_peri__WIDTH 1 -#define R_IRQ_MASK0_RD__par0_peri__active 1 -#define R_IRQ_MASK0_RD__par0_peri__inactive 0 -#define R_IRQ_MASK0_RD__ata_irq2__BITNR 10 -#define R_IRQ_MASK0_RD__ata_irq2__WIDTH 1 -#define R_IRQ_MASK0_RD__ata_irq2__active 1 -#define R_IRQ_MASK0_RD__ata_irq2__inactive 0 -#define R_IRQ_MASK0_RD__par0_data__BITNR 9 -#define R_IRQ_MASK0_RD__par0_data__WIDTH 1 -#define R_IRQ_MASK0_RD__par0_data__active 1 -#define R_IRQ_MASK0_RD__par0_data__inactive 0 -#define R_IRQ_MASK0_RD__ata_irq1__BITNR 9 -#define R_IRQ_MASK0_RD__ata_irq1__WIDTH 1 -#define R_IRQ_MASK0_RD__ata_irq1__active 1 -#define R_IRQ_MASK0_RD__ata_irq1__inactive 0 -#define R_IRQ_MASK0_RD__par0_ready__BITNR 8 -#define R_IRQ_MASK0_RD__par0_ready__WIDTH 1 -#define R_IRQ_MASK0_RD__par0_ready__active 1 -#define R_IRQ_MASK0_RD__par0_ready__inactive 0 -#define R_IRQ_MASK0_RD__ata_irq0__BITNR 8 -#define R_IRQ_MASK0_RD__ata_irq0__WIDTH 1 -#define R_IRQ_MASK0_RD__ata_irq0__active 1 -#define R_IRQ_MASK0_RD__ata_irq0__inactive 0 -#define R_IRQ_MASK0_RD__mio__BITNR 8 -#define R_IRQ_MASK0_RD__mio__WIDTH 1 -#define R_IRQ_MASK0_RD__mio__active 1 -#define R_IRQ_MASK0_RD__mio__inactive 0 -#define R_IRQ_MASK0_RD__scsi0__BITNR 8 -#define R_IRQ_MASK0_RD__scsi0__WIDTH 1 -#define R_IRQ_MASK0_RD__scsi0__active 1 -#define R_IRQ_MASK0_RD__scsi0__inactive 0 -#define R_IRQ_MASK0_RD__ata_dmaend__BITNR 7 -#define R_IRQ_MASK0_RD__ata_dmaend__WIDTH 1 -#define R_IRQ_MASK0_RD__ata_dmaend__active 1 -#define R_IRQ_MASK0_RD__ata_dmaend__inactive 0 -#define R_IRQ_MASK0_RD__irq_ext_vector_nr__BITNR 5 -#define R_IRQ_MASK0_RD__irq_ext_vector_nr__WIDTH 1 -#define R_IRQ_MASK0_RD__irq_ext_vector_nr__active 1 -#define R_IRQ_MASK0_RD__irq_ext_vector_nr__inactive 0 -#define R_IRQ_MASK0_RD__irq_int_vector_nr__BITNR 4 -#define R_IRQ_MASK0_RD__irq_int_vector_nr__WIDTH 1 -#define R_IRQ_MASK0_RD__irq_int_vector_nr__active 1 -#define R_IRQ_MASK0_RD__irq_int_vector_nr__inactive 0 -#define R_IRQ_MASK0_RD__ext_dma1__BITNR 3 -#define R_IRQ_MASK0_RD__ext_dma1__WIDTH 1 -#define R_IRQ_MASK0_RD__ext_dma1__active 1 -#define R_IRQ_MASK0_RD__ext_dma1__inactive 0 -#define R_IRQ_MASK0_RD__ext_dma0__BITNR 2 -#define R_IRQ_MASK0_RD__ext_dma0__WIDTH 1 -#define R_IRQ_MASK0_RD__ext_dma0__active 1 -#define R_IRQ_MASK0_RD__ext_dma0__inactive 0 -#define R_IRQ_MASK0_RD__timer1__BITNR 1 -#define R_IRQ_MASK0_RD__timer1__WIDTH 1 -#define R_IRQ_MASK0_RD__timer1__active 1 -#define R_IRQ_MASK0_RD__timer1__inactive 0 -#define R_IRQ_MASK0_RD__timer0__BITNR 0 -#define R_IRQ_MASK0_RD__timer0__WIDTH 1 -#define R_IRQ_MASK0_RD__timer0__active 1 -#define R_IRQ_MASK0_RD__timer0__inactive 0 - -#define R_IRQ_MASK0_CLR (IO_TYPECAST_UDWORD 0xb00000c0) -#define R_IRQ_MASK0_CLR__nmi_pin__BITNR 31 -#define R_IRQ_MASK0_CLR__nmi_pin__WIDTH 1 -#define R_IRQ_MASK0_CLR__nmi_pin__clr 1 -#define R_IRQ_MASK0_CLR__nmi_pin__nop 0 -#define R_IRQ_MASK0_CLR__watchdog_nmi__BITNR 30 -#define R_IRQ_MASK0_CLR__watchdog_nmi__WIDTH 1 -#define R_IRQ_MASK0_CLR__watchdog_nmi__clr 1 -#define R_IRQ_MASK0_CLR__watchdog_nmi__nop 0 -#define R_IRQ_MASK0_CLR__sqe_test_error__BITNR 29 -#define R_IRQ_MASK0_CLR__sqe_test_error__WIDTH 1 -#define R_IRQ_MASK0_CLR__sqe_test_error__clr 1 -#define R_IRQ_MASK0_CLR__sqe_test_error__nop 0 -#define R_IRQ_MASK0_CLR__carrier_loss__BITNR 28 -#define R_IRQ_MASK0_CLR__carrier_loss__WIDTH 1 -#define R_IRQ_MASK0_CLR__carrier_loss__clr 1 -#define R_IRQ_MASK0_CLR__carrier_loss__nop 0 -#define R_IRQ_MASK0_CLR__deferred__BITNR 27 -#define R_IRQ_MASK0_CLR__deferred__WIDTH 1 -#define R_IRQ_MASK0_CLR__deferred__clr 1 -#define R_IRQ_MASK0_CLR__deferred__nop 0 -#define R_IRQ_MASK0_CLR__late_col__BITNR 26 -#define R_IRQ_MASK0_CLR__late_col__WIDTH 1 -#define R_IRQ_MASK0_CLR__late_col__clr 1 -#define R_IRQ_MASK0_CLR__late_col__nop 0 -#define R_IRQ_MASK0_CLR__multiple_col__BITNR 25 -#define R_IRQ_MASK0_CLR__multiple_col__WIDTH 1 -#define R_IRQ_MASK0_CLR__multiple_col__clr 1 -#define R_IRQ_MASK0_CLR__multiple_col__nop 0 -#define R_IRQ_MASK0_CLR__single_col__BITNR 24 -#define R_IRQ_MASK0_CLR__single_col__WIDTH 1 -#define R_IRQ_MASK0_CLR__single_col__clr 1 -#define R_IRQ_MASK0_CLR__single_col__nop 0 -#define R_IRQ_MASK0_CLR__congestion__BITNR 23 -#define R_IRQ_MASK0_CLR__congestion__WIDTH 1 -#define R_IRQ_MASK0_CLR__congestion__clr 1 -#define R_IRQ_MASK0_CLR__congestion__nop 0 -#define R_IRQ_MASK0_CLR__oversize__BITNR 22 -#define R_IRQ_MASK0_CLR__oversize__WIDTH 1 -#define R_IRQ_MASK0_CLR__oversize__clr 1 -#define R_IRQ_MASK0_CLR__oversize__nop 0 -#define R_IRQ_MASK0_CLR__alignment_error__BITNR 21 -#define R_IRQ_MASK0_CLR__alignment_error__WIDTH 1 -#define R_IRQ_MASK0_CLR__alignment_error__clr 1 -#define R_IRQ_MASK0_CLR__alignment_error__nop 0 -#define R_IRQ_MASK0_CLR__crc_error__BITNR 20 -#define R_IRQ_MASK0_CLR__crc_error__WIDTH 1 -#define R_IRQ_MASK0_CLR__crc_error__clr 1 -#define R_IRQ_MASK0_CLR__crc_error__nop 0 -#define R_IRQ_MASK0_CLR__overrun__BITNR 19 -#define R_IRQ_MASK0_CLR__overrun__WIDTH 1 -#define R_IRQ_MASK0_CLR__overrun__clr 1 -#define R_IRQ_MASK0_CLR__overrun__nop 0 -#define R_IRQ_MASK0_CLR__underrun__BITNR 18 -#define R_IRQ_MASK0_CLR__underrun__WIDTH 1 -#define R_IRQ_MASK0_CLR__underrun__clr 1 -#define R_IRQ_MASK0_CLR__underrun__nop 0 -#define R_IRQ_MASK0_CLR__excessive_col__BITNR 17 -#define R_IRQ_MASK0_CLR__excessive_col__WIDTH 1 -#define R_IRQ_MASK0_CLR__excessive_col__clr 1 -#define R_IRQ_MASK0_CLR__excessive_col__nop 0 -#define R_IRQ_MASK0_CLR__mdio__BITNR 16 -#define R_IRQ_MASK0_CLR__mdio__WIDTH 1 -#define R_IRQ_MASK0_CLR__mdio__clr 1 -#define R_IRQ_MASK0_CLR__mdio__nop 0 -#define R_IRQ_MASK0_CLR__ata_drq3__BITNR 15 -#define R_IRQ_MASK0_CLR__ata_drq3__WIDTH 1 -#define R_IRQ_MASK0_CLR__ata_drq3__clr 1 -#define R_IRQ_MASK0_CLR__ata_drq3__nop 0 -#define R_IRQ_MASK0_CLR__ata_drq2__BITNR 14 -#define R_IRQ_MASK0_CLR__ata_drq2__WIDTH 1 -#define R_IRQ_MASK0_CLR__ata_drq2__clr 1 -#define R_IRQ_MASK0_CLR__ata_drq2__nop 0 -#define R_IRQ_MASK0_CLR__ata_drq1__BITNR 13 -#define R_IRQ_MASK0_CLR__ata_drq1__WIDTH 1 -#define R_IRQ_MASK0_CLR__ata_drq1__clr 1 -#define R_IRQ_MASK0_CLR__ata_drq1__nop 0 -#define R_IRQ_MASK0_CLR__ata_drq0__BITNR 12 -#define R_IRQ_MASK0_CLR__ata_drq0__WIDTH 1 -#define R_IRQ_MASK0_CLR__ata_drq0__clr 1 -#define R_IRQ_MASK0_CLR__ata_drq0__nop 0 -#define R_IRQ_MASK0_CLR__par0_ecp_cmd__BITNR 11 -#define R_IRQ_MASK0_CLR__par0_ecp_cmd__WIDTH 1 -#define R_IRQ_MASK0_CLR__par0_ecp_cmd__clr 1 -#define R_IRQ_MASK0_CLR__par0_ecp_cmd__nop 0 -#define R_IRQ_MASK0_CLR__ata_irq3__BITNR 11 -#define R_IRQ_MASK0_CLR__ata_irq3__WIDTH 1 -#define R_IRQ_MASK0_CLR__ata_irq3__clr 1 -#define R_IRQ_MASK0_CLR__ata_irq3__nop 0 -#define R_IRQ_MASK0_CLR__par0_peri__BITNR 10 -#define R_IRQ_MASK0_CLR__par0_peri__WIDTH 1 -#define R_IRQ_MASK0_CLR__par0_peri__clr 1 -#define R_IRQ_MASK0_CLR__par0_peri__nop 0 -#define R_IRQ_MASK0_CLR__ata_irq2__BITNR 10 -#define R_IRQ_MASK0_CLR__ata_irq2__WIDTH 1 -#define R_IRQ_MASK0_CLR__ata_irq2__clr 1 -#define R_IRQ_MASK0_CLR__ata_irq2__nop 0 -#define R_IRQ_MASK0_CLR__par0_data__BITNR 9 -#define R_IRQ_MASK0_CLR__par0_data__WIDTH 1 -#define R_IRQ_MASK0_CLR__par0_data__clr 1 -#define R_IRQ_MASK0_CLR__par0_data__nop 0 -#define R_IRQ_MASK0_CLR__ata_irq1__BITNR 9 -#define R_IRQ_MASK0_CLR__ata_irq1__WIDTH 1 -#define R_IRQ_MASK0_CLR__ata_irq1__clr 1 -#define R_IRQ_MASK0_CLR__ata_irq1__nop 0 -#define R_IRQ_MASK0_CLR__par0_ready__BITNR 8 -#define R_IRQ_MASK0_CLR__par0_ready__WIDTH 1 -#define R_IRQ_MASK0_CLR__par0_ready__clr 1 -#define R_IRQ_MASK0_CLR__par0_ready__nop 0 -#define R_IRQ_MASK0_CLR__ata_irq0__BITNR 8 -#define R_IRQ_MASK0_CLR__ata_irq0__WIDTH 1 -#define R_IRQ_MASK0_CLR__ata_irq0__clr 1 -#define R_IRQ_MASK0_CLR__ata_irq0__nop 0 -#define R_IRQ_MASK0_CLR__mio__BITNR 8 -#define R_IRQ_MASK0_CLR__mio__WIDTH 1 -#define R_IRQ_MASK0_CLR__mio__clr 1 -#define R_IRQ_MASK0_CLR__mio__nop 0 -#define R_IRQ_MASK0_CLR__scsi0__BITNR 8 -#define R_IRQ_MASK0_CLR__scsi0__WIDTH 1 -#define R_IRQ_MASK0_CLR__scsi0__clr 1 -#define R_IRQ_MASK0_CLR__scsi0__nop 0 -#define R_IRQ_MASK0_CLR__ata_dmaend__BITNR 7 -#define R_IRQ_MASK0_CLR__ata_dmaend__WIDTH 1 -#define R_IRQ_MASK0_CLR__ata_dmaend__clr 1 -#define R_IRQ_MASK0_CLR__ata_dmaend__nop 0 -#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__BITNR 5 -#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__WIDTH 1 -#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__clr 1 -#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__nop 0 -#define R_IRQ_MASK0_CLR__irq_int_vector_nr__BITNR 4 -#define R_IRQ_MASK0_CLR__irq_int_vector_nr__WIDTH 1 -#define R_IRQ_MASK0_CLR__irq_int_vector_nr__clr 1 -#define R_IRQ_MASK0_CLR__irq_int_vector_nr__nop 0 -#define R_IRQ_MASK0_CLR__ext_dma1__BITNR 3 -#define R_IRQ_MASK0_CLR__ext_dma1__WIDTH 1 -#define R_IRQ_MASK0_CLR__ext_dma1__clr 1 -#define R_IRQ_MASK0_CLR__ext_dma1__nop 0 -#define R_IRQ_MASK0_CLR__ext_dma0__BITNR 2 -#define R_IRQ_MASK0_CLR__ext_dma0__WIDTH 1 -#define R_IRQ_MASK0_CLR__ext_dma0__clr 1 -#define R_IRQ_MASK0_CLR__ext_dma0__nop 0 -#define R_IRQ_MASK0_CLR__timer1__BITNR 1 -#define R_IRQ_MASK0_CLR__timer1__WIDTH 1 -#define R_IRQ_MASK0_CLR__timer1__clr 1 -#define R_IRQ_MASK0_CLR__timer1__nop 0 -#define R_IRQ_MASK0_CLR__timer0__BITNR 0 -#define R_IRQ_MASK0_CLR__timer0__WIDTH 1 -#define R_IRQ_MASK0_CLR__timer0__clr 1 -#define R_IRQ_MASK0_CLR__timer0__nop 0 - -#define R_IRQ_READ0 (IO_TYPECAST_RO_UDWORD 0xb00000c4) -#define R_IRQ_READ0__nmi_pin__BITNR 31 -#define R_IRQ_READ0__nmi_pin__WIDTH 1 -#define R_IRQ_READ0__nmi_pin__active 1 -#define R_IRQ_READ0__nmi_pin__inactive 0 -#define R_IRQ_READ0__watchdog_nmi__BITNR 30 -#define R_IRQ_READ0__watchdog_nmi__WIDTH 1 -#define R_IRQ_READ0__watchdog_nmi__active 1 -#define R_IRQ_READ0__watchdog_nmi__inactive 0 -#define R_IRQ_READ0__sqe_test_error__BITNR 29 -#define R_IRQ_READ0__sqe_test_error__WIDTH 1 -#define R_IRQ_READ0__sqe_test_error__active 1 -#define R_IRQ_READ0__sqe_test_error__inactive 0 -#define R_IRQ_READ0__carrier_loss__BITNR 28 -#define R_IRQ_READ0__carrier_loss__WIDTH 1 -#define R_IRQ_READ0__carrier_loss__active 1 -#define R_IRQ_READ0__carrier_loss__inactive 0 -#define R_IRQ_READ0__deferred__BITNR 27 -#define R_IRQ_READ0__deferred__WIDTH 1 -#define R_IRQ_READ0__deferred__active 1 -#define R_IRQ_READ0__deferred__inactive 0 -#define R_IRQ_READ0__late_col__BITNR 26 -#define R_IRQ_READ0__late_col__WIDTH 1 -#define R_IRQ_READ0__late_col__active 1 -#define R_IRQ_READ0__late_col__inactive 0 -#define R_IRQ_READ0__multiple_col__BITNR 25 -#define R_IRQ_READ0__multiple_col__WIDTH 1 -#define R_IRQ_READ0__multiple_col__active 1 -#define R_IRQ_READ0__multiple_col__inactive 0 -#define R_IRQ_READ0__single_col__BITNR 24 -#define R_IRQ_READ0__single_col__WIDTH 1 -#define R_IRQ_READ0__single_col__active 1 -#define R_IRQ_READ0__single_col__inactive 0 -#define R_IRQ_READ0__congestion__BITNR 23 -#define R_IRQ_READ0__congestion__WIDTH 1 -#define R_IRQ_READ0__congestion__active 1 -#define R_IRQ_READ0__congestion__inactive 0 -#define R_IRQ_READ0__oversize__BITNR 22 -#define R_IRQ_READ0__oversize__WIDTH 1 -#define R_IRQ_READ0__oversize__active 1 -#define R_IRQ_READ0__oversize__inactive 0 -#define R_IRQ_READ0__alignment_error__BITNR 21 -#define R_IRQ_READ0__alignment_error__WIDTH 1 -#define R_IRQ_READ0__alignment_error__active 1 -#define R_IRQ_READ0__alignment_error__inactive 0 -#define R_IRQ_READ0__crc_error__BITNR 20 -#define R_IRQ_READ0__crc_error__WIDTH 1 -#define R_IRQ_READ0__crc_error__active 1 -#define R_IRQ_READ0__crc_error__inactive 0 -#define R_IRQ_READ0__overrun__BITNR 19 -#define R_IRQ_READ0__overrun__WIDTH 1 -#define R_IRQ_READ0__overrun__active 1 -#define R_IRQ_READ0__overrun__inactive 0 -#define R_IRQ_READ0__underrun__BITNR 18 -#define R_IRQ_READ0__underrun__WIDTH 1 -#define R_IRQ_READ0__underrun__active 1 -#define R_IRQ_READ0__underrun__inactive 0 -#define R_IRQ_READ0__excessive_col__BITNR 17 -#define R_IRQ_READ0__excessive_col__WIDTH 1 -#define R_IRQ_READ0__excessive_col__active 1 -#define R_IRQ_READ0__excessive_col__inactive 0 -#define R_IRQ_READ0__mdio__BITNR 16 -#define R_IRQ_READ0__mdio__WIDTH 1 -#define R_IRQ_READ0__mdio__active 1 -#define R_IRQ_READ0__mdio__inactive 0 -#define R_IRQ_READ0__ata_drq3__BITNR 15 -#define R_IRQ_READ0__ata_drq3__WIDTH 1 -#define R_IRQ_READ0__ata_drq3__active 1 -#define R_IRQ_READ0__ata_drq3__inactive 0 -#define R_IRQ_READ0__ata_drq2__BITNR 14 -#define R_IRQ_READ0__ata_drq2__WIDTH 1 -#define R_IRQ_READ0__ata_drq2__active 1 -#define R_IRQ_READ0__ata_drq2__inactive 0 -#define R_IRQ_READ0__ata_drq1__BITNR 13 -#define R_IRQ_READ0__ata_drq1__WIDTH 1 -#define R_IRQ_READ0__ata_drq1__active 1 -#define R_IRQ_READ0__ata_drq1__inactive 0 -#define R_IRQ_READ0__ata_drq0__BITNR 12 -#define R_IRQ_READ0__ata_drq0__WIDTH 1 -#define R_IRQ_READ0__ata_drq0__active 1 -#define R_IRQ_READ0__ata_drq0__inactive 0 -#define R_IRQ_READ0__par0_ecp_cmd__BITNR 11 -#define R_IRQ_READ0__par0_ecp_cmd__WIDTH 1 -#define R_IRQ_READ0__par0_ecp_cmd__active 1 -#define R_IRQ_READ0__par0_ecp_cmd__inactive 0 -#define R_IRQ_READ0__ata_irq3__BITNR 11 -#define R_IRQ_READ0__ata_irq3__WIDTH 1 -#define R_IRQ_READ0__ata_irq3__active 1 -#define R_IRQ_READ0__ata_irq3__inactive 0 -#define R_IRQ_READ0__par0_peri__BITNR 10 -#define R_IRQ_READ0__par0_peri__WIDTH 1 -#define R_IRQ_READ0__par0_peri__active 1 -#define R_IRQ_READ0__par0_peri__inactive 0 -#define R_IRQ_READ0__ata_irq2__BITNR 10 -#define R_IRQ_READ0__ata_irq2__WIDTH 1 -#define R_IRQ_READ0__ata_irq2__active 1 -#define R_IRQ_READ0__ata_irq2__inactive 0 -#define R_IRQ_READ0__par0_data__BITNR 9 -#define R_IRQ_READ0__par0_data__WIDTH 1 -#define R_IRQ_READ0__par0_data__active 1 -#define R_IRQ_READ0__par0_data__inactive 0 -#define R_IRQ_READ0__ata_irq1__BITNR 9 -#define R_IRQ_READ0__ata_irq1__WIDTH 1 -#define R_IRQ_READ0__ata_irq1__active 1 -#define R_IRQ_READ0__ata_irq1__inactive 0 -#define R_IRQ_READ0__par0_ready__BITNR 8 -#define R_IRQ_READ0__par0_ready__WIDTH 1 -#define R_IRQ_READ0__par0_ready__active 1 -#define R_IRQ_READ0__par0_ready__inactive 0 -#define R_IRQ_READ0__ata_irq0__BITNR 8 -#define R_IRQ_READ0__ata_irq0__WIDTH 1 -#define R_IRQ_READ0__ata_irq0__active 1 -#define R_IRQ_READ0__ata_irq0__inactive 0 -#define R_IRQ_READ0__mio__BITNR 8 -#define R_IRQ_READ0__mio__WIDTH 1 -#define R_IRQ_READ0__mio__active 1 -#define R_IRQ_READ0__mio__inactive 0 -#define R_IRQ_READ0__scsi0__BITNR 8 -#define R_IRQ_READ0__scsi0__WIDTH 1 -#define R_IRQ_READ0__scsi0__active 1 -#define R_IRQ_READ0__scsi0__inactive 0 -#define R_IRQ_READ0__ata_dmaend__BITNR 7 -#define R_IRQ_READ0__ata_dmaend__WIDTH 1 -#define R_IRQ_READ0__ata_dmaend__active 1 -#define R_IRQ_READ0__ata_dmaend__inactive 0 -#define R_IRQ_READ0__irq_ext_vector_nr__BITNR 5 -#define R_IRQ_READ0__irq_ext_vector_nr__WIDTH 1 -#define R_IRQ_READ0__irq_ext_vector_nr__active 1 -#define R_IRQ_READ0__irq_ext_vector_nr__inactive 0 -#define R_IRQ_READ0__irq_int_vector_nr__BITNR 4 -#define R_IRQ_READ0__irq_int_vector_nr__WIDTH 1 -#define R_IRQ_READ0__irq_int_vector_nr__active 1 -#define R_IRQ_READ0__irq_int_vector_nr__inactive 0 -#define R_IRQ_READ0__ext_dma1__BITNR 3 -#define R_IRQ_READ0__ext_dma1__WIDTH 1 -#define R_IRQ_READ0__ext_dma1__active 1 -#define R_IRQ_READ0__ext_dma1__inactive 0 -#define R_IRQ_READ0__ext_dma0__BITNR 2 -#define R_IRQ_READ0__ext_dma0__WIDTH 1 -#define R_IRQ_READ0__ext_dma0__active 1 -#define R_IRQ_READ0__ext_dma0__inactive 0 -#define R_IRQ_READ0__timer1__BITNR 1 -#define R_IRQ_READ0__timer1__WIDTH 1 -#define R_IRQ_READ0__timer1__active 1 -#define R_IRQ_READ0__timer1__inactive 0 -#define R_IRQ_READ0__timer0__BITNR 0 -#define R_IRQ_READ0__timer0__WIDTH 1 -#define R_IRQ_READ0__timer0__active 1 -#define R_IRQ_READ0__timer0__inactive 0 - -#define R_IRQ_MASK0_SET (IO_TYPECAST_UDWORD 0xb00000c4) -#define R_IRQ_MASK0_SET__nmi_pin__BITNR 31 -#define R_IRQ_MASK0_SET__nmi_pin__WIDTH 1 -#define R_IRQ_MASK0_SET__nmi_pin__set 1 -#define R_IRQ_MASK0_SET__nmi_pin__nop 0 -#define R_IRQ_MASK0_SET__watchdog_nmi__BITNR 30 -#define R_IRQ_MASK0_SET__watchdog_nmi__WIDTH 1 -#define R_IRQ_MASK0_SET__watchdog_nmi__set 1 -#define R_IRQ_MASK0_SET__watchdog_nmi__nop 0 -#define R_IRQ_MASK0_SET__sqe_test_error__BITNR 29 -#define R_IRQ_MASK0_SET__sqe_test_error__WIDTH 1 -#define R_IRQ_MASK0_SET__sqe_test_error__set 1 -#define R_IRQ_MASK0_SET__sqe_test_error__nop 0 -#define R_IRQ_MASK0_SET__carrier_loss__BITNR 28 -#define R_IRQ_MASK0_SET__carrier_loss__WIDTH 1 -#define R_IRQ_MASK0_SET__carrier_loss__set 1 -#define R_IRQ_MASK0_SET__carrier_loss__nop 0 -#define R_IRQ_MASK0_SET__deferred__BITNR 27 -#define R_IRQ_MASK0_SET__deferred__WIDTH 1 -#define R_IRQ_MASK0_SET__deferred__set 1 -#define R_IRQ_MASK0_SET__deferred__nop 0 -#define R_IRQ_MASK0_SET__late_col__BITNR 26 -#define R_IRQ_MASK0_SET__late_col__WIDTH 1 -#define R_IRQ_MASK0_SET__late_col__set 1 -#define R_IRQ_MASK0_SET__late_col__nop 0 -#define R_IRQ_MASK0_SET__multiple_col__BITNR 25 -#define R_IRQ_MASK0_SET__multiple_col__WIDTH 1 -#define R_IRQ_MASK0_SET__multiple_col__set 1 -#define R_IRQ_MASK0_SET__multiple_col__nop 0 -#define R_IRQ_MASK0_SET__single_col__BITNR 24 -#define R_IRQ_MASK0_SET__single_col__WIDTH 1 -#define R_IRQ_MASK0_SET__single_col__set 1 -#define R_IRQ_MASK0_SET__single_col__nop 0 -#define R_IRQ_MASK0_SET__congestion__BITNR 23 -#define R_IRQ_MASK0_SET__congestion__WIDTH 1 -#define R_IRQ_MASK0_SET__congestion__set 1 -#define R_IRQ_MASK0_SET__congestion__nop 0 -#define R_IRQ_MASK0_SET__oversize__BITNR 22 -#define R_IRQ_MASK0_SET__oversize__WIDTH 1 -#define R_IRQ_MASK0_SET__oversize__set 1 -#define R_IRQ_MASK0_SET__oversize__nop 0 -#define R_IRQ_MASK0_SET__alignment_error__BITNR 21 -#define R_IRQ_MASK0_SET__alignment_error__WIDTH 1 -#define R_IRQ_MASK0_SET__alignment_error__set 1 -#define R_IRQ_MASK0_SET__alignment_error__nop 0 -#define R_IRQ_MASK0_SET__crc_error__BITNR 20 -#define R_IRQ_MASK0_SET__crc_error__WIDTH 1 -#define R_IRQ_MASK0_SET__crc_error__set 1 -#define R_IRQ_MASK0_SET__crc_error__nop 0 -#define R_IRQ_MASK0_SET__overrun__BITNR 19 -#define R_IRQ_MASK0_SET__overrun__WIDTH 1 -#define R_IRQ_MASK0_SET__overrun__set 1 -#define R_IRQ_MASK0_SET__overrun__nop 0 -#define R_IRQ_MASK0_SET__underrun__BITNR 18 -#define R_IRQ_MASK0_SET__underrun__WIDTH 1 -#define R_IRQ_MASK0_SET__underrun__set 1 -#define R_IRQ_MASK0_SET__underrun__nop 0 -#define R_IRQ_MASK0_SET__excessive_col__BITNR 17 -#define R_IRQ_MASK0_SET__excessive_col__WIDTH 1 -#define R_IRQ_MASK0_SET__excessive_col__set 1 -#define R_IRQ_MASK0_SET__excessive_col__nop 0 -#define R_IRQ_MASK0_SET__mdio__BITNR 16 -#define R_IRQ_MASK0_SET__mdio__WIDTH 1 -#define R_IRQ_MASK0_SET__mdio__set 1 -#define R_IRQ_MASK0_SET__mdio__nop 0 -#define R_IRQ_MASK0_SET__ata_drq3__BITNR 15 -#define R_IRQ_MASK0_SET__ata_drq3__WIDTH 1 -#define R_IRQ_MASK0_SET__ata_drq3__set 1 -#define R_IRQ_MASK0_SET__ata_drq3__nop 0 -#define R_IRQ_MASK0_SET__ata_drq2__BITNR 14 -#define R_IRQ_MASK0_SET__ata_drq2__WIDTH 1 -#define R_IRQ_MASK0_SET__ata_drq2__set 1 -#define R_IRQ_MASK0_SET__ata_drq2__nop 0 -#define R_IRQ_MASK0_SET__ata_drq1__BITNR 13 -#define R_IRQ_MASK0_SET__ata_drq1__WIDTH 1 -#define R_IRQ_MASK0_SET__ata_drq1__set 1 -#define R_IRQ_MASK0_SET__ata_drq1__nop 0 -#define R_IRQ_MASK0_SET__ata_drq0__BITNR 12 -#define R_IRQ_MASK0_SET__ata_drq0__WIDTH 1 -#define R_IRQ_MASK0_SET__ata_drq0__set 1 -#define R_IRQ_MASK0_SET__ata_drq0__nop 0 -#define R_IRQ_MASK0_SET__par0_ecp_cmd__BITNR 11 -#define R_IRQ_MASK0_SET__par0_ecp_cmd__WIDTH 1 -#define R_IRQ_MASK0_SET__par0_ecp_cmd__set 1 -#define R_IRQ_MASK0_SET__par0_ecp_cmd__nop 0 -#define R_IRQ_MASK0_SET__ata_irq3__BITNR 11 -#define R_IRQ_MASK0_SET__ata_irq3__WIDTH 1 -#define R_IRQ_MASK0_SET__ata_irq3__set 1 -#define R_IRQ_MASK0_SET__ata_irq3__nop 0 -#define R_IRQ_MASK0_SET__par0_peri__BITNR 10 -#define R_IRQ_MASK0_SET__par0_peri__WIDTH 1 -#define R_IRQ_MASK0_SET__par0_peri__set 1 -#define R_IRQ_MASK0_SET__par0_peri__nop 0 -#define R_IRQ_MASK0_SET__ata_irq2__BITNR 10 -#define R_IRQ_MASK0_SET__ata_irq2__WIDTH 1 -#define R_IRQ_MASK0_SET__ata_irq2__set 1 -#define R_IRQ_MASK0_SET__ata_irq2__nop 0 -#define R_IRQ_MASK0_SET__par0_data__BITNR 9 -#define R_IRQ_MASK0_SET__par0_data__WIDTH 1 -#define R_IRQ_MASK0_SET__par0_data__set 1 -#define R_IRQ_MASK0_SET__par0_data__nop 0 -#define R_IRQ_MASK0_SET__ata_irq1__BITNR 9 -#define R_IRQ_MASK0_SET__ata_irq1__WIDTH 1 -#define R_IRQ_MASK0_SET__ata_irq1__set 1 -#define R_IRQ_MASK0_SET__ata_irq1__nop 0 -#define R_IRQ_MASK0_SET__par0_ready__BITNR 8 -#define R_IRQ_MASK0_SET__par0_ready__WIDTH 1 -#define R_IRQ_MASK0_SET__par0_ready__set 1 -#define R_IRQ_MASK0_SET__par0_ready__nop 0 -#define R_IRQ_MASK0_SET__ata_irq0__BITNR 8 -#define R_IRQ_MASK0_SET__ata_irq0__WIDTH 1 -#define R_IRQ_MASK0_SET__ata_irq0__set 1 -#define R_IRQ_MASK0_SET__ata_irq0__nop 0 -#define R_IRQ_MASK0_SET__mio__BITNR 8 -#define R_IRQ_MASK0_SET__mio__WIDTH 1 -#define R_IRQ_MASK0_SET__mio__set 1 -#define R_IRQ_MASK0_SET__mio__nop 0 -#define R_IRQ_MASK0_SET__scsi0__BITNR 8 -#define R_IRQ_MASK0_SET__scsi0__WIDTH 1 -#define R_IRQ_MASK0_SET__scsi0__set 1 -#define R_IRQ_MASK0_SET__scsi0__nop 0 -#define R_IRQ_MASK0_SET__ata_dmaend__BITNR 7 -#define R_IRQ_MASK0_SET__ata_dmaend__WIDTH 1 -#define R_IRQ_MASK0_SET__ata_dmaend__set 1 -#define R_IRQ_MASK0_SET__ata_dmaend__nop 0 -#define R_IRQ_MASK0_SET__irq_ext_vector_nr__BITNR 5 -#define R_IRQ_MASK0_SET__irq_ext_vector_nr__WIDTH 1 -#define R_IRQ_MASK0_SET__irq_ext_vector_nr__set 1 -#define R_IRQ_MASK0_SET__irq_ext_vector_nr__nop 0 -#define R_IRQ_MASK0_SET__irq_int_vector_nr__BITNR 4 -#define R_IRQ_MASK0_SET__irq_int_vector_nr__WIDTH 1 -#define R_IRQ_MASK0_SET__irq_int_vector_nr__set 1 -#define R_IRQ_MASK0_SET__irq_int_vector_nr__nop 0 -#define R_IRQ_MASK0_SET__ext_dma1__BITNR 3 -#define R_IRQ_MASK0_SET__ext_dma1__WIDTH 1 -#define R_IRQ_MASK0_SET__ext_dma1__set 1 -#define R_IRQ_MASK0_SET__ext_dma1__nop 0 -#define R_IRQ_MASK0_SET__ext_dma0__BITNR 2 -#define R_IRQ_MASK0_SET__ext_dma0__WIDTH 1 -#define R_IRQ_MASK0_SET__ext_dma0__set 1 -#define R_IRQ_MASK0_SET__ext_dma0__nop 0 -#define R_IRQ_MASK0_SET__timer1__BITNR 1 -#define R_IRQ_MASK0_SET__timer1__WIDTH 1 -#define R_IRQ_MASK0_SET__timer1__set 1 -#define R_IRQ_MASK0_SET__timer1__nop 0 -#define R_IRQ_MASK0_SET__timer0__BITNR 0 -#define R_IRQ_MASK0_SET__timer0__WIDTH 1 -#define R_IRQ_MASK0_SET__timer0__set 1 -#define R_IRQ_MASK0_SET__timer0__nop 0 - -#define R_IRQ_MASK1_RD (IO_TYPECAST_RO_UDWORD 0xb00000c8) -#define R_IRQ_MASK1_RD__sw_int7__BITNR 31 -#define R_IRQ_MASK1_RD__sw_int7__WIDTH 1 -#define R_IRQ_MASK1_RD__sw_int7__active 1 -#define R_IRQ_MASK1_RD__sw_int7__inactive 0 -#define R_IRQ_MASK1_RD__sw_int6__BITNR 30 -#define R_IRQ_MASK1_RD__sw_int6__WIDTH 1 -#define R_IRQ_MASK1_RD__sw_int6__active 1 -#define R_IRQ_MASK1_RD__sw_int6__inactive 0 -#define R_IRQ_MASK1_RD__sw_int5__BITNR 29 -#define R_IRQ_MASK1_RD__sw_int5__WIDTH 1 -#define R_IRQ_MASK1_RD__sw_int5__active 1 -#define R_IRQ_MASK1_RD__sw_int5__inactive 0 -#define R_IRQ_MASK1_RD__sw_int4__BITNR 28 -#define R_IRQ_MASK1_RD__sw_int4__WIDTH 1 -#define R_IRQ_MASK1_RD__sw_int4__active 1 -#define R_IRQ_MASK1_RD__sw_int4__inactive 0 -#define R_IRQ_MASK1_RD__sw_int3__BITNR 27 -#define R_IRQ_MASK1_RD__sw_int3__WIDTH 1 -#define R_IRQ_MASK1_RD__sw_int3__active 1 -#define R_IRQ_MASK1_RD__sw_int3__inactive 0 -#define R_IRQ_MASK1_RD__sw_int2__BITNR 26 -#define R_IRQ_MASK1_RD__sw_int2__WIDTH 1 -#define R_IRQ_MASK1_RD__sw_int2__active 1 -#define R_IRQ_MASK1_RD__sw_int2__inactive 0 -#define R_IRQ_MASK1_RD__sw_int1__BITNR 25 -#define R_IRQ_MASK1_RD__sw_int1__WIDTH 1 -#define R_IRQ_MASK1_RD__sw_int1__active 1 -#define R_IRQ_MASK1_RD__sw_int1__inactive 0 -#define R_IRQ_MASK1_RD__sw_int0__BITNR 24 -#define R_IRQ_MASK1_RD__sw_int0__WIDTH 1 -#define R_IRQ_MASK1_RD__sw_int0__active 1 -#define R_IRQ_MASK1_RD__sw_int0__inactive 0 -#define R_IRQ_MASK1_RD__par1_ecp_cmd__BITNR 19 -#define R_IRQ_MASK1_RD__par1_ecp_cmd__WIDTH 1 -#define R_IRQ_MASK1_RD__par1_ecp_cmd__active 1 -#define R_IRQ_MASK1_RD__par1_ecp_cmd__inactive 0 -#define R_IRQ_MASK1_RD__par1_peri__BITNR 18 -#define R_IRQ_MASK1_RD__par1_peri__WIDTH 1 -#define R_IRQ_MASK1_RD__par1_peri__active 1 -#define R_IRQ_MASK1_RD__par1_peri__inactive 0 -#define R_IRQ_MASK1_RD__par1_data__BITNR 17 -#define R_IRQ_MASK1_RD__par1_data__WIDTH 1 -#define R_IRQ_MASK1_RD__par1_data__active 1 -#define R_IRQ_MASK1_RD__par1_data__inactive 0 -#define R_IRQ_MASK1_RD__par1_ready__BITNR 16 -#define R_IRQ_MASK1_RD__par1_ready__WIDTH 1 -#define R_IRQ_MASK1_RD__par1_ready__active 1 -#define R_IRQ_MASK1_RD__par1_ready__inactive 0 -#define R_IRQ_MASK1_RD__scsi1__BITNR 16 -#define R_IRQ_MASK1_RD__scsi1__WIDTH 1 -#define R_IRQ_MASK1_RD__scsi1__active 1 -#define R_IRQ_MASK1_RD__scsi1__inactive 0 -#define R_IRQ_MASK1_RD__ser3_ready__BITNR 15 -#define R_IRQ_MASK1_RD__ser3_ready__WIDTH 1 -#define R_IRQ_MASK1_RD__ser3_ready__active 1 -#define R_IRQ_MASK1_RD__ser3_ready__inactive 0 -#define R_IRQ_MASK1_RD__ser3_data__BITNR 14 -#define R_IRQ_MASK1_RD__ser3_data__WIDTH 1 -#define R_IRQ_MASK1_RD__ser3_data__active 1 -#define R_IRQ_MASK1_RD__ser3_data__inactive 0 -#define R_IRQ_MASK1_RD__ser2_ready__BITNR 13 -#define R_IRQ_MASK1_RD__ser2_ready__WIDTH 1 -#define R_IRQ_MASK1_RD__ser2_ready__active 1 -#define R_IRQ_MASK1_RD__ser2_ready__inactive 0 -#define R_IRQ_MASK1_RD__ser2_data__BITNR 12 -#define R_IRQ_MASK1_RD__ser2_data__WIDTH 1 -#define R_IRQ_MASK1_RD__ser2_data__active 1 -#define R_IRQ_MASK1_RD__ser2_data__inactive 0 -#define R_IRQ_MASK1_RD__ser1_ready__BITNR 11 -#define R_IRQ_MASK1_RD__ser1_ready__WIDTH 1 -#define R_IRQ_MASK1_RD__ser1_ready__active 1 -#define R_IRQ_MASK1_RD__ser1_ready__inactive 0 -#define R_IRQ_MASK1_RD__ser1_data__BITNR 10 -#define R_IRQ_MASK1_RD__ser1_data__WIDTH 1 -#define R_IRQ_MASK1_RD__ser1_data__active 1 -#define R_IRQ_MASK1_RD__ser1_data__inactive 0 -#define R_IRQ_MASK1_RD__ser0_ready__BITNR 9 -#define R_IRQ_MASK1_RD__ser0_ready__WIDTH 1 -#define R_IRQ_MASK1_RD__ser0_ready__active 1 -#define R_IRQ_MASK1_RD__ser0_ready__inactive 0 -#define R_IRQ_MASK1_RD__ser0_data__BITNR 8 -#define R_IRQ_MASK1_RD__ser0_data__WIDTH 1 -#define R_IRQ_MASK1_RD__ser0_data__active 1 -#define R_IRQ_MASK1_RD__ser0_data__inactive 0 -#define R_IRQ_MASK1_RD__pa7__BITNR 7 -#define R_IRQ_MASK1_RD__pa7__WIDTH 1 -#define R_IRQ_MASK1_RD__pa7__active 1 -#define R_IRQ_MASK1_RD__pa7__inactive 0 -#define R_IRQ_MASK1_RD__pa6__BITNR 6 -#define R_IRQ_MASK1_RD__pa6__WIDTH 1 -#define R_IRQ_MASK1_RD__pa6__active 1 -#define R_IRQ_MASK1_RD__pa6__inactive 0 -#define R_IRQ_MASK1_RD__pa5__BITNR 5 -#define R_IRQ_MASK1_RD__pa5__WIDTH 1 -#define R_IRQ_MASK1_RD__pa5__active 1 -#define R_IRQ_MASK1_RD__pa5__inactive 0 -#define R_IRQ_MASK1_RD__pa4__BITNR 4 -#define R_IRQ_MASK1_RD__pa4__WIDTH 1 -#define R_IRQ_MASK1_RD__pa4__active 1 -#define R_IRQ_MASK1_RD__pa4__inactive 0 -#define R_IRQ_MASK1_RD__pa3__BITNR 3 -#define R_IRQ_MASK1_RD__pa3__WIDTH 1 -#define R_IRQ_MASK1_RD__pa3__active 1 -#define R_IRQ_MASK1_RD__pa3__inactive 0 -#define R_IRQ_MASK1_RD__pa2__BITNR 2 -#define R_IRQ_MASK1_RD__pa2__WIDTH 1 -#define R_IRQ_MASK1_RD__pa2__active 1 -#define R_IRQ_MASK1_RD__pa2__inactive 0 -#define R_IRQ_MASK1_RD__pa1__BITNR 1 -#define R_IRQ_MASK1_RD__pa1__WIDTH 1 -#define R_IRQ_MASK1_RD__pa1__active 1 -#define R_IRQ_MASK1_RD__pa1__inactive 0 -#define R_IRQ_MASK1_RD__pa0__BITNR 0 -#define R_IRQ_MASK1_RD__pa0__WIDTH 1 -#define R_IRQ_MASK1_RD__pa0__active 1 -#define R_IRQ_MASK1_RD__pa0__inactive 0 - -#define R_IRQ_MASK1_CLR (IO_TYPECAST_UDWORD 0xb00000c8) -#define R_IRQ_MASK1_CLR__sw_int7__BITNR 31 -#define R_IRQ_MASK1_CLR__sw_int7__WIDTH 1 -#define R_IRQ_MASK1_CLR__sw_int7__clr 1 -#define R_IRQ_MASK1_CLR__sw_int7__nop 0 -#define R_IRQ_MASK1_CLR__sw_int6__BITNR 30 -#define R_IRQ_MASK1_CLR__sw_int6__WIDTH 1 -#define R_IRQ_MASK1_CLR__sw_int6__clr 1 -#define R_IRQ_MASK1_CLR__sw_int6__nop 0 -#define R_IRQ_MASK1_CLR__sw_int5__BITNR 29 -#define R_IRQ_MASK1_CLR__sw_int5__WIDTH 1 -#define R_IRQ_MASK1_CLR__sw_int5__clr 1 -#define R_IRQ_MASK1_CLR__sw_int5__nop 0 -#define R_IRQ_MASK1_CLR__sw_int4__BITNR 28 -#define R_IRQ_MASK1_CLR__sw_int4__WIDTH 1 -#define R_IRQ_MASK1_CLR__sw_int4__clr 1 -#define R_IRQ_MASK1_CLR__sw_int4__nop 0 -#define R_IRQ_MASK1_CLR__sw_int3__BITNR 27 -#define R_IRQ_MASK1_CLR__sw_int3__WIDTH 1 -#define R_IRQ_MASK1_CLR__sw_int3__clr 1 -#define R_IRQ_MASK1_CLR__sw_int3__nop 0 -#define R_IRQ_MASK1_CLR__sw_int2__BITNR 26 -#define R_IRQ_MASK1_CLR__sw_int2__WIDTH 1 -#define R_IRQ_MASK1_CLR__sw_int2__clr 1 -#define R_IRQ_MASK1_CLR__sw_int2__nop 0 -#define R_IRQ_MASK1_CLR__sw_int1__BITNR 25 -#define R_IRQ_MASK1_CLR__sw_int1__WIDTH 1 -#define R_IRQ_MASK1_CLR__sw_int1__clr 1 -#define R_IRQ_MASK1_CLR__sw_int1__nop 0 -#define R_IRQ_MASK1_CLR__sw_int0__BITNR 24 -#define R_IRQ_MASK1_CLR__sw_int0__WIDTH 1 -#define R_IRQ_MASK1_CLR__sw_int0__clr 1 -#define R_IRQ_MASK1_CLR__sw_int0__nop 0 -#define R_IRQ_MASK1_CLR__par1_ecp_cmd__BITNR 19 -#define R_IRQ_MASK1_CLR__par1_ecp_cmd__WIDTH 1 -#define R_IRQ_MASK1_CLR__par1_ecp_cmd__clr 1 -#define R_IRQ_MASK1_CLR__par1_ecp_cmd__nop 0 -#define R_IRQ_MASK1_CLR__par1_peri__BITNR 18 -#define R_IRQ_MASK1_CLR__par1_peri__WIDTH 1 -#define R_IRQ_MASK1_CLR__par1_peri__clr 1 -#define R_IRQ_MASK1_CLR__par1_peri__nop 0 -#define R_IRQ_MASK1_CLR__par1_data__BITNR 17 -#define R_IRQ_MASK1_CLR__par1_data__WIDTH 1 -#define R_IRQ_MASK1_CLR__par1_data__clr 1 -#define R_IRQ_MASK1_CLR__par1_data__nop 0 -#define R_IRQ_MASK1_CLR__par1_ready__BITNR 16 -#define R_IRQ_MASK1_CLR__par1_ready__WIDTH 1 -#define R_IRQ_MASK1_CLR__par1_ready__clr 1 -#define R_IRQ_MASK1_CLR__par1_ready__nop 0 -#define R_IRQ_MASK1_CLR__scsi1__BITNR 16 -#define R_IRQ_MASK1_CLR__scsi1__WIDTH 1 -#define R_IRQ_MASK1_CLR__scsi1__clr 1 -#define R_IRQ_MASK1_CLR__scsi1__nop 0 -#define R_IRQ_MASK1_CLR__ser3_ready__BITNR 15 -#define R_IRQ_MASK1_CLR__ser3_ready__WIDTH 1 -#define R_IRQ_MASK1_CLR__ser3_ready__clr 1 -#define R_IRQ_MASK1_CLR__ser3_ready__nop 0 -#define R_IRQ_MASK1_CLR__ser3_data__BITNR 14 -#define R_IRQ_MASK1_CLR__ser3_data__WIDTH 1 -#define R_IRQ_MASK1_CLR__ser3_data__clr 1 -#define R_IRQ_MASK1_CLR__ser3_data__nop 0 -#define R_IRQ_MASK1_CLR__ser2_ready__BITNR 13 -#define R_IRQ_MASK1_CLR__ser2_ready__WIDTH 1 -#define R_IRQ_MASK1_CLR__ser2_ready__clr 1 -#define R_IRQ_MASK1_CLR__ser2_ready__nop 0 -#define R_IRQ_MASK1_CLR__ser2_data__BITNR 12 -#define R_IRQ_MASK1_CLR__ser2_data__WIDTH 1 -#define R_IRQ_MASK1_CLR__ser2_data__clr 1 -#define R_IRQ_MASK1_CLR__ser2_data__nop 0 -#define R_IRQ_MASK1_CLR__ser1_ready__BITNR 11 -#define R_IRQ_MASK1_CLR__ser1_ready__WIDTH 1 -#define R_IRQ_MASK1_CLR__ser1_ready__clr 1 -#define R_IRQ_MASK1_CLR__ser1_ready__nop 0 -#define R_IRQ_MASK1_CLR__ser1_data__BITNR 10 -#define R_IRQ_MASK1_CLR__ser1_data__WIDTH 1 -#define R_IRQ_MASK1_CLR__ser1_data__clr 1 -#define R_IRQ_MASK1_CLR__ser1_data__nop 0 -#define R_IRQ_MASK1_CLR__ser0_ready__BITNR 9 -#define R_IRQ_MASK1_CLR__ser0_ready__WIDTH 1 -#define R_IRQ_MASK1_CLR__ser0_ready__clr 1 -#define R_IRQ_MASK1_CLR__ser0_ready__nop 0 -#define R_IRQ_MASK1_CLR__ser0_data__BITNR 8 -#define R_IRQ_MASK1_CLR__ser0_data__WIDTH 1 -#define R_IRQ_MASK1_CLR__ser0_data__clr 1 -#define R_IRQ_MASK1_CLR__ser0_data__nop 0 -#define R_IRQ_MASK1_CLR__pa7__BITNR 7 -#define R_IRQ_MASK1_CLR__pa7__WIDTH 1 -#define R_IRQ_MASK1_CLR__pa7__clr 1 -#define R_IRQ_MASK1_CLR__pa7__nop 0 -#define R_IRQ_MASK1_CLR__pa6__BITNR 6 -#define R_IRQ_MASK1_CLR__pa6__WIDTH 1 -#define R_IRQ_MASK1_CLR__pa6__clr 1 -#define R_IRQ_MASK1_CLR__pa6__nop 0 -#define R_IRQ_MASK1_CLR__pa5__BITNR 5 -#define R_IRQ_MASK1_CLR__pa5__WIDTH 1 -#define R_IRQ_MASK1_CLR__pa5__clr 1 -#define R_IRQ_MASK1_CLR__pa5__nop 0 -#define R_IRQ_MASK1_CLR__pa4__BITNR 4 -#define R_IRQ_MASK1_CLR__pa4__WIDTH 1 -#define R_IRQ_MASK1_CLR__pa4__clr 1 -#define R_IRQ_MASK1_CLR__pa4__nop 0 -#define R_IRQ_MASK1_CLR__pa3__BITNR 3 -#define R_IRQ_MASK1_CLR__pa3__WIDTH 1 -#define R_IRQ_MASK1_CLR__pa3__clr 1 -#define R_IRQ_MASK1_CLR__pa3__nop 0 -#define R_IRQ_MASK1_CLR__pa2__BITNR 2 -#define R_IRQ_MASK1_CLR__pa2__WIDTH 1 -#define R_IRQ_MASK1_CLR__pa2__clr 1 -#define R_IRQ_MASK1_CLR__pa2__nop 0 -#define R_IRQ_MASK1_CLR__pa1__BITNR 1 -#define R_IRQ_MASK1_CLR__pa1__WIDTH 1 -#define R_IRQ_MASK1_CLR__pa1__clr 1 -#define R_IRQ_MASK1_CLR__pa1__nop 0 -#define R_IRQ_MASK1_CLR__pa0__BITNR 0 -#define R_IRQ_MASK1_CLR__pa0__WIDTH 1 -#define R_IRQ_MASK1_CLR__pa0__clr 1 -#define R_IRQ_MASK1_CLR__pa0__nop 0 - -#define R_IRQ_READ1 (IO_TYPECAST_RO_UDWORD 0xb00000cc) -#define R_IRQ_READ1__sw_int7__BITNR 31 -#define R_IRQ_READ1__sw_int7__WIDTH 1 -#define R_IRQ_READ1__sw_int7__active 1 -#define R_IRQ_READ1__sw_int7__inactive 0 -#define R_IRQ_READ1__sw_int6__BITNR 30 -#define R_IRQ_READ1__sw_int6__WIDTH 1 -#define R_IRQ_READ1__sw_int6__active 1 -#define R_IRQ_READ1__sw_int6__inactive 0 -#define R_IRQ_READ1__sw_int5__BITNR 29 -#define R_IRQ_READ1__sw_int5__WIDTH 1 -#define R_IRQ_READ1__sw_int5__active 1 -#define R_IRQ_READ1__sw_int5__inactive 0 -#define R_IRQ_READ1__sw_int4__BITNR 28 -#define R_IRQ_READ1__sw_int4__WIDTH 1 -#define R_IRQ_READ1__sw_int4__active 1 -#define R_IRQ_READ1__sw_int4__inactive 0 -#define R_IRQ_READ1__sw_int3__BITNR 27 -#define R_IRQ_READ1__sw_int3__WIDTH 1 -#define R_IRQ_READ1__sw_int3__active 1 -#define R_IRQ_READ1__sw_int3__inactive 0 -#define R_IRQ_READ1__sw_int2__BITNR 26 -#define R_IRQ_READ1__sw_int2__WIDTH 1 -#define R_IRQ_READ1__sw_int2__active 1 -#define R_IRQ_READ1__sw_int2__inactive 0 -#define R_IRQ_READ1__sw_int1__BITNR 25 -#define R_IRQ_READ1__sw_int1__WIDTH 1 -#define R_IRQ_READ1__sw_int1__active 1 -#define R_IRQ_READ1__sw_int1__inactive 0 -#define R_IRQ_READ1__sw_int0__BITNR 24 -#define R_IRQ_READ1__sw_int0__WIDTH 1 -#define R_IRQ_READ1__sw_int0__active 1 -#define R_IRQ_READ1__sw_int0__inactive 0 -#define R_IRQ_READ1__par1_ecp_cmd__BITNR 19 -#define R_IRQ_READ1__par1_ecp_cmd__WIDTH 1 -#define R_IRQ_READ1__par1_ecp_cmd__active 1 -#define R_IRQ_READ1__par1_ecp_cmd__inactive 0 -#define R_IRQ_READ1__par1_peri__BITNR 18 -#define R_IRQ_READ1__par1_peri__WIDTH 1 -#define R_IRQ_READ1__par1_peri__active 1 -#define R_IRQ_READ1__par1_peri__inactive 0 -#define R_IRQ_READ1__par1_data__BITNR 17 -#define R_IRQ_READ1__par1_data__WIDTH 1 -#define R_IRQ_READ1__par1_data__active 1 -#define R_IRQ_READ1__par1_data__inactive 0 -#define R_IRQ_READ1__par1_ready__BITNR 16 -#define R_IRQ_READ1__par1_ready__WIDTH 1 -#define R_IRQ_READ1__par1_ready__active 1 -#define R_IRQ_READ1__par1_ready__inactive 0 -#define R_IRQ_READ1__scsi1__BITNR 16 -#define R_IRQ_READ1__scsi1__WIDTH 1 -#define R_IRQ_READ1__scsi1__active 1 -#define R_IRQ_READ1__scsi1__inactive 0 -#define R_IRQ_READ1__ser3_ready__BITNR 15 -#define R_IRQ_READ1__ser3_ready__WIDTH 1 -#define R_IRQ_READ1__ser3_ready__active 1 -#define R_IRQ_READ1__ser3_ready__inactive 0 -#define R_IRQ_READ1__ser3_data__BITNR 14 -#define R_IRQ_READ1__ser3_data__WIDTH 1 -#define R_IRQ_READ1__ser3_data__active 1 -#define R_IRQ_READ1__ser3_data__inactive 0 -#define R_IRQ_READ1__ser2_ready__BITNR 13 -#define R_IRQ_READ1__ser2_ready__WIDTH 1 -#define R_IRQ_READ1__ser2_ready__active 1 -#define R_IRQ_READ1__ser2_ready__inactive 0 -#define R_IRQ_READ1__ser2_data__BITNR 12 -#define R_IRQ_READ1__ser2_data__WIDTH 1 -#define R_IRQ_READ1__ser2_data__active 1 -#define R_IRQ_READ1__ser2_data__inactive 0 -#define R_IRQ_READ1__ser1_ready__BITNR 11 -#define R_IRQ_READ1__ser1_ready__WIDTH 1 -#define R_IRQ_READ1__ser1_ready__active 1 -#define R_IRQ_READ1__ser1_ready__inactive 0 -#define R_IRQ_READ1__ser1_data__BITNR 10 -#define R_IRQ_READ1__ser1_data__WIDTH 1 -#define R_IRQ_READ1__ser1_data__active 1 -#define R_IRQ_READ1__ser1_data__inactive 0 -#define R_IRQ_READ1__ser0_ready__BITNR 9 -#define R_IRQ_READ1__ser0_ready__WIDTH 1 -#define R_IRQ_READ1__ser0_ready__active 1 -#define R_IRQ_READ1__ser0_ready__inactive 0 -#define R_IRQ_READ1__ser0_data__BITNR 8 -#define R_IRQ_READ1__ser0_data__WIDTH 1 -#define R_IRQ_READ1__ser0_data__active 1 -#define R_IRQ_READ1__ser0_data__inactive 0 -#define R_IRQ_READ1__pa7__BITNR 7 -#define R_IRQ_READ1__pa7__WIDTH 1 -#define R_IRQ_READ1__pa7__active 1 -#define R_IRQ_READ1__pa7__inactive 0 -#define R_IRQ_READ1__pa6__BITNR 6 -#define R_IRQ_READ1__pa6__WIDTH 1 -#define R_IRQ_READ1__pa6__active 1 -#define R_IRQ_READ1__pa6__inactive 0 -#define R_IRQ_READ1__pa5__BITNR 5 -#define R_IRQ_READ1__pa5__WIDTH 1 -#define R_IRQ_READ1__pa5__active 1 -#define R_IRQ_READ1__pa5__inactive 0 -#define R_IRQ_READ1__pa4__BITNR 4 -#define R_IRQ_READ1__pa4__WIDTH 1 -#define R_IRQ_READ1__pa4__active 1 -#define R_IRQ_READ1__pa4__inactive 0 -#define R_IRQ_READ1__pa3__BITNR 3 -#define R_IRQ_READ1__pa3__WIDTH 1 -#define R_IRQ_READ1__pa3__active 1 -#define R_IRQ_READ1__pa3__inactive 0 -#define R_IRQ_READ1__pa2__BITNR 2 -#define R_IRQ_READ1__pa2__WIDTH 1 -#define R_IRQ_READ1__pa2__active 1 -#define R_IRQ_READ1__pa2__inactive 0 -#define R_IRQ_READ1__pa1__BITNR 1 -#define R_IRQ_READ1__pa1__WIDTH 1 -#define R_IRQ_READ1__pa1__active 1 -#define R_IRQ_READ1__pa1__inactive 0 -#define R_IRQ_READ1__pa0__BITNR 0 -#define R_IRQ_READ1__pa0__WIDTH 1 -#define R_IRQ_READ1__pa0__active 1 -#define R_IRQ_READ1__pa0__inactive 0 - -#define R_IRQ_MASK1_SET (IO_TYPECAST_UDWORD 0xb00000cc) -#define R_IRQ_MASK1_SET__sw_int7__BITNR 31 -#define R_IRQ_MASK1_SET__sw_int7__WIDTH 1 -#define R_IRQ_MASK1_SET__sw_int7__set 1 -#define R_IRQ_MASK1_SET__sw_int7__nop 0 -#define R_IRQ_MASK1_SET__sw_int6__BITNR 30 -#define R_IRQ_MASK1_SET__sw_int6__WIDTH 1 -#define R_IRQ_MASK1_SET__sw_int6__set 1 -#define R_IRQ_MASK1_SET__sw_int6__nop 0 -#define R_IRQ_MASK1_SET__sw_int5__BITNR 29 -#define R_IRQ_MASK1_SET__sw_int5__WIDTH 1 -#define R_IRQ_MASK1_SET__sw_int5__set 1 -#define R_IRQ_MASK1_SET__sw_int5__nop 0 -#define R_IRQ_MASK1_SET__sw_int4__BITNR 28 -#define R_IRQ_MASK1_SET__sw_int4__WIDTH 1 -#define R_IRQ_MASK1_SET__sw_int4__set 1 -#define R_IRQ_MASK1_SET__sw_int4__nop 0 -#define R_IRQ_MASK1_SET__sw_int3__BITNR 27 -#define R_IRQ_MASK1_SET__sw_int3__WIDTH 1 -#define R_IRQ_MASK1_SET__sw_int3__set 1 -#define R_IRQ_MASK1_SET__sw_int3__nop 0 -#define R_IRQ_MASK1_SET__sw_int2__BITNR 26 -#define R_IRQ_MASK1_SET__sw_int2__WIDTH 1 -#define R_IRQ_MASK1_SET__sw_int2__set 1 -#define R_IRQ_MASK1_SET__sw_int2__nop 0 -#define R_IRQ_MASK1_SET__sw_int1__BITNR 25 -#define R_IRQ_MASK1_SET__sw_int1__WIDTH 1 -#define R_IRQ_MASK1_SET__sw_int1__set 1 -#define R_IRQ_MASK1_SET__sw_int1__nop 0 -#define R_IRQ_MASK1_SET__sw_int0__BITNR 24 -#define R_IRQ_MASK1_SET__sw_int0__WIDTH 1 -#define R_IRQ_MASK1_SET__sw_int0__set 1 -#define R_IRQ_MASK1_SET__sw_int0__nop 0 -#define R_IRQ_MASK1_SET__par1_ecp_cmd__BITNR 19 -#define R_IRQ_MASK1_SET__par1_ecp_cmd__WIDTH 1 -#define R_IRQ_MASK1_SET__par1_ecp_cmd__set 1 -#define R_IRQ_MASK1_SET__par1_ecp_cmd__nop 0 -#define R_IRQ_MASK1_SET__par1_peri__BITNR 18 -#define R_IRQ_MASK1_SET__par1_peri__WIDTH 1 -#define R_IRQ_MASK1_SET__par1_peri__set 1 -#define R_IRQ_MASK1_SET__par1_peri__nop 0 -#define R_IRQ_MASK1_SET__par1_data__BITNR 17 -#define R_IRQ_MASK1_SET__par1_data__WIDTH 1 -#define R_IRQ_MASK1_SET__par1_data__set 1 -#define R_IRQ_MASK1_SET__par1_data__nop 0 -#define R_IRQ_MASK1_SET__par1_ready__BITNR 16 -#define R_IRQ_MASK1_SET__par1_ready__WIDTH 1 -#define R_IRQ_MASK1_SET__par1_ready__set 1 -#define R_IRQ_MASK1_SET__par1_ready__nop 0 -#define R_IRQ_MASK1_SET__scsi1__BITNR 16 -#define R_IRQ_MASK1_SET__scsi1__WIDTH 1 -#define R_IRQ_MASK1_SET__scsi1__set 1 -#define R_IRQ_MASK1_SET__scsi1__nop 0 -#define R_IRQ_MASK1_SET__ser3_ready__BITNR 15 -#define R_IRQ_MASK1_SET__ser3_ready__WIDTH 1 -#define R_IRQ_MASK1_SET__ser3_ready__set 1 -#define R_IRQ_MASK1_SET__ser3_ready__nop 0 -#define R_IRQ_MASK1_SET__ser3_data__BITNR 14 -#define R_IRQ_MASK1_SET__ser3_data__WIDTH 1 -#define R_IRQ_MASK1_SET__ser3_data__set 1 -#define R_IRQ_MASK1_SET__ser3_data__nop 0 -#define R_IRQ_MASK1_SET__ser2_ready__BITNR 13 -#define R_IRQ_MASK1_SET__ser2_ready__WIDTH 1 -#define R_IRQ_MASK1_SET__ser2_ready__set 1 -#define R_IRQ_MASK1_SET__ser2_ready__nop 0 -#define R_IRQ_MASK1_SET__ser2_data__BITNR 12 -#define R_IRQ_MASK1_SET__ser2_data__WIDTH 1 -#define R_IRQ_MASK1_SET__ser2_data__set 1 -#define R_IRQ_MASK1_SET__ser2_data__nop 0 -#define R_IRQ_MASK1_SET__ser1_ready__BITNR 11 -#define R_IRQ_MASK1_SET__ser1_ready__WIDTH 1 -#define R_IRQ_MASK1_SET__ser1_ready__set 1 -#define R_IRQ_MASK1_SET__ser1_ready__nop 0 -#define R_IRQ_MASK1_SET__ser1_data__BITNR 10 -#define R_IRQ_MASK1_SET__ser1_data__WIDTH 1 -#define R_IRQ_MASK1_SET__ser1_data__set 1 -#define R_IRQ_MASK1_SET__ser1_data__nop 0 -#define R_IRQ_MASK1_SET__ser0_ready__BITNR 9 -#define R_IRQ_MASK1_SET__ser0_ready__WIDTH 1 -#define R_IRQ_MASK1_SET__ser0_ready__set 1 -#define R_IRQ_MASK1_SET__ser0_ready__nop 0 -#define R_IRQ_MASK1_SET__ser0_data__BITNR 8 -#define R_IRQ_MASK1_SET__ser0_data__WIDTH 1 -#define R_IRQ_MASK1_SET__ser0_data__set 1 -#define R_IRQ_MASK1_SET__ser0_data__nop 0 -#define R_IRQ_MASK1_SET__pa7__BITNR 7 -#define R_IRQ_MASK1_SET__pa7__WIDTH 1 -#define R_IRQ_MASK1_SET__pa7__set 1 -#define R_IRQ_MASK1_SET__pa7__nop 0 -#define R_IRQ_MASK1_SET__pa6__BITNR 6 -#define R_IRQ_MASK1_SET__pa6__WIDTH 1 -#define R_IRQ_MASK1_SET__pa6__set 1 -#define R_IRQ_MASK1_SET__pa6__nop 0 -#define R_IRQ_MASK1_SET__pa5__BITNR 5 -#define R_IRQ_MASK1_SET__pa5__WIDTH 1 -#define R_IRQ_MASK1_SET__pa5__set 1 -#define R_IRQ_MASK1_SET__pa5__nop 0 -#define R_IRQ_MASK1_SET__pa4__BITNR 4 -#define R_IRQ_MASK1_SET__pa4__WIDTH 1 -#define R_IRQ_MASK1_SET__pa4__set 1 -#define R_IRQ_MASK1_SET__pa4__nop 0 -#define R_IRQ_MASK1_SET__pa3__BITNR 3 -#define R_IRQ_MASK1_SET__pa3__WIDTH 1 -#define R_IRQ_MASK1_SET__pa3__set 1 -#define R_IRQ_MASK1_SET__pa3__nop 0 -#define R_IRQ_MASK1_SET__pa2__BITNR 2 -#define R_IRQ_MASK1_SET__pa2__WIDTH 1 -#define R_IRQ_MASK1_SET__pa2__set 1 -#define R_IRQ_MASK1_SET__pa2__nop 0 -#define R_IRQ_MASK1_SET__pa1__BITNR 1 -#define R_IRQ_MASK1_SET__pa1__WIDTH 1 -#define R_IRQ_MASK1_SET__pa1__set 1 -#define R_IRQ_MASK1_SET__pa1__nop 0 -#define R_IRQ_MASK1_SET__pa0__BITNR 0 -#define R_IRQ_MASK1_SET__pa0__WIDTH 1 -#define R_IRQ_MASK1_SET__pa0__set 1 -#define R_IRQ_MASK1_SET__pa0__nop 0 - -#define R_IRQ_MASK2_RD (IO_TYPECAST_RO_UDWORD 0xb00000d0) -#define R_IRQ_MASK2_RD__dma8_sub3_descr__BITNR 23 -#define R_IRQ_MASK2_RD__dma8_sub3_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma8_sub3_descr__active 1 -#define R_IRQ_MASK2_RD__dma8_sub3_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma8_sub2_descr__BITNR 22 -#define R_IRQ_MASK2_RD__dma8_sub2_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma8_sub2_descr__active 1 -#define R_IRQ_MASK2_RD__dma8_sub2_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma8_sub1_descr__BITNR 21 -#define R_IRQ_MASK2_RD__dma8_sub1_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma8_sub1_descr__active 1 -#define R_IRQ_MASK2_RD__dma8_sub1_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma8_sub0_descr__BITNR 20 -#define R_IRQ_MASK2_RD__dma8_sub0_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma8_sub0_descr__active 1 -#define R_IRQ_MASK2_RD__dma8_sub0_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma9_eop__BITNR 19 -#define R_IRQ_MASK2_RD__dma9_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma9_eop__active 1 -#define R_IRQ_MASK2_RD__dma9_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma9_descr__BITNR 18 -#define R_IRQ_MASK2_RD__dma9_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma9_descr__active 1 -#define R_IRQ_MASK2_RD__dma9_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma8_eop__BITNR 17 -#define R_IRQ_MASK2_RD__dma8_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma8_eop__active 1 -#define R_IRQ_MASK2_RD__dma8_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma8_descr__BITNR 16 -#define R_IRQ_MASK2_RD__dma8_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma8_descr__active 1 -#define R_IRQ_MASK2_RD__dma8_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma7_eop__BITNR 15 -#define R_IRQ_MASK2_RD__dma7_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma7_eop__active 1 -#define R_IRQ_MASK2_RD__dma7_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma7_descr__BITNR 14 -#define R_IRQ_MASK2_RD__dma7_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma7_descr__active 1 -#define R_IRQ_MASK2_RD__dma7_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma6_eop__BITNR 13 -#define R_IRQ_MASK2_RD__dma6_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma6_eop__active 1 -#define R_IRQ_MASK2_RD__dma6_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma6_descr__BITNR 12 -#define R_IRQ_MASK2_RD__dma6_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma6_descr__active 1 -#define R_IRQ_MASK2_RD__dma6_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma5_eop__BITNR 11 -#define R_IRQ_MASK2_RD__dma5_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma5_eop__active 1 -#define R_IRQ_MASK2_RD__dma5_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma5_descr__BITNR 10 -#define R_IRQ_MASK2_RD__dma5_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma5_descr__active 1 -#define R_IRQ_MASK2_RD__dma5_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma4_eop__BITNR 9 -#define R_IRQ_MASK2_RD__dma4_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma4_eop__active 1 -#define R_IRQ_MASK2_RD__dma4_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma4_descr__BITNR 8 -#define R_IRQ_MASK2_RD__dma4_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma4_descr__active 1 -#define R_IRQ_MASK2_RD__dma4_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma3_eop__BITNR 7 -#define R_IRQ_MASK2_RD__dma3_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma3_eop__active 1 -#define R_IRQ_MASK2_RD__dma3_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma3_descr__BITNR 6 -#define R_IRQ_MASK2_RD__dma3_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma3_descr__active 1 -#define R_IRQ_MASK2_RD__dma3_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma2_eop__BITNR 5 -#define R_IRQ_MASK2_RD__dma2_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma2_eop__active 1 -#define R_IRQ_MASK2_RD__dma2_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma2_descr__BITNR 4 -#define R_IRQ_MASK2_RD__dma2_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma2_descr__active 1 -#define R_IRQ_MASK2_RD__dma2_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma1_eop__BITNR 3 -#define R_IRQ_MASK2_RD__dma1_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma1_eop__active 1 -#define R_IRQ_MASK2_RD__dma1_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma1_descr__BITNR 2 -#define R_IRQ_MASK2_RD__dma1_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma1_descr__active 1 -#define R_IRQ_MASK2_RD__dma1_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma0_eop__BITNR 1 -#define R_IRQ_MASK2_RD__dma0_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma0_eop__active 1 -#define R_IRQ_MASK2_RD__dma0_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma0_descr__BITNR 0 -#define R_IRQ_MASK2_RD__dma0_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma0_descr__active 1 -#define R_IRQ_MASK2_RD__dma0_descr__inactive 0 - -#define R_IRQ_MASK2_CLR (IO_TYPECAST_UDWORD 0xb00000d0) -#define R_IRQ_MASK2_CLR__dma8_sub3_descr__BITNR 23 -#define R_IRQ_MASK2_CLR__dma8_sub3_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma8_sub3_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma8_sub3_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma8_sub2_descr__BITNR 22 -#define R_IRQ_MASK2_CLR__dma8_sub2_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma8_sub2_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma8_sub2_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma8_sub1_descr__BITNR 21 -#define R_IRQ_MASK2_CLR__dma8_sub1_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma8_sub1_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma8_sub1_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma8_sub0_descr__BITNR 20 -#define R_IRQ_MASK2_CLR__dma8_sub0_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma8_sub0_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma8_sub0_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma9_eop__BITNR 19 -#define R_IRQ_MASK2_CLR__dma9_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma9_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma9_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma9_descr__BITNR 18 -#define R_IRQ_MASK2_CLR__dma9_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma9_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma9_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma8_eop__BITNR 17 -#define R_IRQ_MASK2_CLR__dma8_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma8_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma8_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma8_descr__BITNR 16 -#define R_IRQ_MASK2_CLR__dma8_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma8_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma8_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma7_eop__BITNR 15 -#define R_IRQ_MASK2_CLR__dma7_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma7_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma7_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma7_descr__BITNR 14 -#define R_IRQ_MASK2_CLR__dma7_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma7_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma7_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma6_eop__BITNR 13 -#define R_IRQ_MASK2_CLR__dma6_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma6_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma6_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma6_descr__BITNR 12 -#define R_IRQ_MASK2_CLR__dma6_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma6_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma6_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma5_eop__BITNR 11 -#define R_IRQ_MASK2_CLR__dma5_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma5_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma5_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma5_descr__BITNR 10 -#define R_IRQ_MASK2_CLR__dma5_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma5_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma5_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma4_eop__BITNR 9 -#define R_IRQ_MASK2_CLR__dma4_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma4_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma4_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma4_descr__BITNR 8 -#define R_IRQ_MASK2_CLR__dma4_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma4_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma4_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma3_eop__BITNR 7 -#define R_IRQ_MASK2_CLR__dma3_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma3_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma3_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma3_descr__BITNR 6 -#define R_IRQ_MASK2_CLR__dma3_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma3_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma3_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma2_eop__BITNR 5 -#define R_IRQ_MASK2_CLR__dma2_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma2_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma2_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma2_descr__BITNR 4 -#define R_IRQ_MASK2_CLR__dma2_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma2_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma2_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma1_eop__BITNR 3 -#define R_IRQ_MASK2_CLR__dma1_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma1_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma1_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma1_descr__BITNR 2 -#define R_IRQ_MASK2_CLR__dma1_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma1_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma1_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma0_eop__BITNR 1 -#define R_IRQ_MASK2_CLR__dma0_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma0_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma0_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma0_descr__BITNR 0 -#define R_IRQ_MASK2_CLR__dma0_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma0_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma0_descr__nop 0 - -#define R_IRQ_READ2 (IO_TYPECAST_RO_UDWORD 0xb00000d4) -#define R_IRQ_READ2__dma8_sub3_descr__BITNR 23 -#define R_IRQ_READ2__dma8_sub3_descr__WIDTH 1 -#define R_IRQ_READ2__dma8_sub3_descr__active 1 -#define R_IRQ_READ2__dma8_sub3_descr__inactive 0 -#define R_IRQ_READ2__dma8_sub2_descr__BITNR 22 -#define R_IRQ_READ2__dma8_sub2_descr__WIDTH 1 -#define R_IRQ_READ2__dma8_sub2_descr__active 1 -#define R_IRQ_READ2__dma8_sub2_descr__inactive 0 -#define R_IRQ_READ2__dma8_sub1_descr__BITNR 21 -#define R_IRQ_READ2__dma8_sub1_descr__WIDTH 1 -#define R_IRQ_READ2__dma8_sub1_descr__active 1 -#define R_IRQ_READ2__dma8_sub1_descr__inactive 0 -#define R_IRQ_READ2__dma8_sub0_descr__BITNR 20 -#define R_IRQ_READ2__dma8_sub0_descr__WIDTH 1 -#define R_IRQ_READ2__dma8_sub0_descr__active 1 -#define R_IRQ_READ2__dma8_sub0_descr__inactive 0 -#define R_IRQ_READ2__dma9_eop__BITNR 19 -#define R_IRQ_READ2__dma9_eop__WIDTH 1 -#define R_IRQ_READ2__dma9_eop__active 1 -#define R_IRQ_READ2__dma9_eop__inactive 0 -#define R_IRQ_READ2__dma9_descr__BITNR 18 -#define R_IRQ_READ2__dma9_descr__WIDTH 1 -#define R_IRQ_READ2__dma9_descr__active 1 -#define R_IRQ_READ2__dma9_descr__inactive 0 -#define R_IRQ_READ2__dma8_eop__BITNR 17 -#define R_IRQ_READ2__dma8_eop__WIDTH 1 -#define R_IRQ_READ2__dma8_eop__active 1 -#define R_IRQ_READ2__dma8_eop__inactive 0 -#define R_IRQ_READ2__dma8_descr__BITNR 16 -#define R_IRQ_READ2__dma8_descr__WIDTH 1 -#define R_IRQ_READ2__dma8_descr__active 1 -#define R_IRQ_READ2__dma8_descr__inactive 0 -#define R_IRQ_READ2__dma7_eop__BITNR 15 -#define R_IRQ_READ2__dma7_eop__WIDTH 1 -#define R_IRQ_READ2__dma7_eop__active 1 -#define R_IRQ_READ2__dma7_eop__inactive 0 -#define R_IRQ_READ2__dma7_descr__BITNR 14 -#define R_IRQ_READ2__dma7_descr__WIDTH 1 -#define R_IRQ_READ2__dma7_descr__active 1 -#define R_IRQ_READ2__dma7_descr__inactive 0 -#define R_IRQ_READ2__dma6_eop__BITNR 13 -#define R_IRQ_READ2__dma6_eop__WIDTH 1 -#define R_IRQ_READ2__dma6_eop__active 1 -#define R_IRQ_READ2__dma6_eop__inactive 0 -#define R_IRQ_READ2__dma6_descr__BITNR 12 -#define R_IRQ_READ2__dma6_descr__WIDTH 1 -#define R_IRQ_READ2__dma6_descr__active 1 -#define R_IRQ_READ2__dma6_descr__inactive 0 -#define R_IRQ_READ2__dma5_eop__BITNR 11 -#define R_IRQ_READ2__dma5_eop__WIDTH 1 -#define R_IRQ_READ2__dma5_eop__active 1 -#define R_IRQ_READ2__dma5_eop__inactive 0 -#define R_IRQ_READ2__dma5_descr__BITNR 10 -#define R_IRQ_READ2__dma5_descr__WIDTH 1 -#define R_IRQ_READ2__dma5_descr__active 1 -#define R_IRQ_READ2__dma5_descr__inactive 0 -#define R_IRQ_READ2__dma4_eop__BITNR 9 -#define R_IRQ_READ2__dma4_eop__WIDTH 1 -#define R_IRQ_READ2__dma4_eop__active 1 -#define R_IRQ_READ2__dma4_eop__inactive 0 -#define R_IRQ_READ2__dma4_descr__BITNR 8 -#define R_IRQ_READ2__dma4_descr__WIDTH 1 -#define R_IRQ_READ2__dma4_descr__active 1 -#define R_IRQ_READ2__dma4_descr__inactive 0 -#define R_IRQ_READ2__dma3_eop__BITNR 7 -#define R_IRQ_READ2__dma3_eop__WIDTH 1 -#define R_IRQ_READ2__dma3_eop__active 1 -#define R_IRQ_READ2__dma3_eop__inactive 0 -#define R_IRQ_READ2__dma3_descr__BITNR 6 -#define R_IRQ_READ2__dma3_descr__WIDTH 1 -#define R_IRQ_READ2__dma3_descr__active 1 -#define R_IRQ_READ2__dma3_descr__inactive 0 -#define R_IRQ_READ2__dma2_eop__BITNR 5 -#define R_IRQ_READ2__dma2_eop__WIDTH 1 -#define R_IRQ_READ2__dma2_eop__active 1 -#define R_IRQ_READ2__dma2_eop__inactive 0 -#define R_IRQ_READ2__dma2_descr__BITNR 4 -#define R_IRQ_READ2__dma2_descr__WIDTH 1 -#define R_IRQ_READ2__dma2_descr__active 1 -#define R_IRQ_READ2__dma2_descr__inactive 0 -#define R_IRQ_READ2__dma1_eop__BITNR 3 -#define R_IRQ_READ2__dma1_eop__WIDTH 1 -#define R_IRQ_READ2__dma1_eop__active 1 -#define R_IRQ_READ2__dma1_eop__inactive 0 -#define R_IRQ_READ2__dma1_descr__BITNR 2 -#define R_IRQ_READ2__dma1_descr__WIDTH 1 -#define R_IRQ_READ2__dma1_descr__active 1 -#define R_IRQ_READ2__dma1_descr__inactive 0 -#define R_IRQ_READ2__dma0_eop__BITNR 1 -#define R_IRQ_READ2__dma0_eop__WIDTH 1 -#define R_IRQ_READ2__dma0_eop__active 1 -#define R_IRQ_READ2__dma0_eop__inactive 0 -#define R_IRQ_READ2__dma0_descr__BITNR 0 -#define R_IRQ_READ2__dma0_descr__WIDTH 1 -#define R_IRQ_READ2__dma0_descr__active 1 -#define R_IRQ_READ2__dma0_descr__inactive 0 - -#define R_IRQ_MASK2_SET (IO_TYPECAST_UDWORD 0xb00000d4) -#define R_IRQ_MASK2_SET__dma8_sub3_descr__BITNR 23 -#define R_IRQ_MASK2_SET__dma8_sub3_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma8_sub3_descr__set 1 -#define R_IRQ_MASK2_SET__dma8_sub3_descr__nop 0 -#define R_IRQ_MASK2_SET__dma8_sub2_descr__BITNR 22 -#define R_IRQ_MASK2_SET__dma8_sub2_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma8_sub2_descr__set 1 -#define R_IRQ_MASK2_SET__dma8_sub2_descr__nop 0 -#define R_IRQ_MASK2_SET__dma8_sub1_descr__BITNR 21 -#define R_IRQ_MASK2_SET__dma8_sub1_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma8_sub1_descr__set 1 -#define R_IRQ_MASK2_SET__dma8_sub1_descr__nop 0 -#define R_IRQ_MASK2_SET__dma8_sub0_descr__BITNR 20 -#define R_IRQ_MASK2_SET__dma8_sub0_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma8_sub0_descr__set 1 -#define R_IRQ_MASK2_SET__dma8_sub0_descr__nop 0 -#define R_IRQ_MASK2_SET__dma9_eop__BITNR 19 -#define R_IRQ_MASK2_SET__dma9_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma9_eop__set 1 -#define R_IRQ_MASK2_SET__dma9_eop__nop 0 -#define R_IRQ_MASK2_SET__dma9_descr__BITNR 18 -#define R_IRQ_MASK2_SET__dma9_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma9_descr__set 1 -#define R_IRQ_MASK2_SET__dma9_descr__nop 0 -#define R_IRQ_MASK2_SET__dma8_eop__BITNR 17 -#define R_IRQ_MASK2_SET__dma8_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma8_eop__set 1 -#define R_IRQ_MASK2_SET__dma8_eop__nop 0 -#define R_IRQ_MASK2_SET__dma8_descr__BITNR 16 -#define R_IRQ_MASK2_SET__dma8_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma8_descr__set 1 -#define R_IRQ_MASK2_SET__dma8_descr__nop 0 -#define R_IRQ_MASK2_SET__dma7_eop__BITNR 15 -#define R_IRQ_MASK2_SET__dma7_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma7_eop__set 1 -#define R_IRQ_MASK2_SET__dma7_eop__nop 0 -#define R_IRQ_MASK2_SET__dma7_descr__BITNR 14 -#define R_IRQ_MASK2_SET__dma7_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma7_descr__set 1 -#define R_IRQ_MASK2_SET__dma7_descr__nop 0 -#define R_IRQ_MASK2_SET__dma6_eop__BITNR 13 -#define R_IRQ_MASK2_SET__dma6_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma6_eop__set 1 -#define R_IRQ_MASK2_SET__dma6_eop__nop 0 -#define R_IRQ_MASK2_SET__dma6_descr__BITNR 12 -#define R_IRQ_MASK2_SET__dma6_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma6_descr__set 1 -#define R_IRQ_MASK2_SET__dma6_descr__nop 0 -#define R_IRQ_MASK2_SET__dma5_eop__BITNR 11 -#define R_IRQ_MASK2_SET__dma5_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma5_eop__set 1 -#define R_IRQ_MASK2_SET__dma5_eop__nop 0 -#define R_IRQ_MASK2_SET__dma5_descr__BITNR 10 -#define R_IRQ_MASK2_SET__dma5_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma5_descr__set 1 -#define R_IRQ_MASK2_SET__dma5_descr__nop 0 -#define R_IRQ_MASK2_SET__dma4_eop__BITNR 9 -#define R_IRQ_MASK2_SET__dma4_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma4_eop__set 1 -#define R_IRQ_MASK2_SET__dma4_eop__nop 0 -#define R_IRQ_MASK2_SET__dma4_descr__BITNR 8 -#define R_IRQ_MASK2_SET__dma4_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma4_descr__set 1 -#define R_IRQ_MASK2_SET__dma4_descr__nop 0 -#define R_IRQ_MASK2_SET__dma3_eop__BITNR 7 -#define R_IRQ_MASK2_SET__dma3_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma3_eop__set 1 -#define R_IRQ_MASK2_SET__dma3_eop__nop 0 -#define R_IRQ_MASK2_SET__dma3_descr__BITNR 6 -#define R_IRQ_MASK2_SET__dma3_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma3_descr__set 1 -#define R_IRQ_MASK2_SET__dma3_descr__nop 0 -#define R_IRQ_MASK2_SET__dma2_eop__BITNR 5 -#define R_IRQ_MASK2_SET__dma2_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma2_eop__set 1 -#define R_IRQ_MASK2_SET__dma2_eop__nop 0 -#define R_IRQ_MASK2_SET__dma2_descr__BITNR 4 -#define R_IRQ_MASK2_SET__dma2_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma2_descr__set 1 -#define R_IRQ_MASK2_SET__dma2_descr__nop 0 -#define R_IRQ_MASK2_SET__dma1_eop__BITNR 3 -#define R_IRQ_MASK2_SET__dma1_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma1_eop__set 1 -#define R_IRQ_MASK2_SET__dma1_eop__nop 0 -#define R_IRQ_MASK2_SET__dma1_descr__BITNR 2 -#define R_IRQ_MASK2_SET__dma1_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma1_descr__set 1 -#define R_IRQ_MASK2_SET__dma1_descr__nop 0 -#define R_IRQ_MASK2_SET__dma0_eop__BITNR 1 -#define R_IRQ_MASK2_SET__dma0_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma0_eop__set 1 -#define R_IRQ_MASK2_SET__dma0_eop__nop 0 -#define R_IRQ_MASK2_SET__dma0_descr__BITNR 0 -#define R_IRQ_MASK2_SET__dma0_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma0_descr__set 1 -#define R_IRQ_MASK2_SET__dma0_descr__nop 0 - -#define R_VECT_MASK_RD (IO_TYPECAST_RO_UDWORD 0xb00000d8) -#define R_VECT_MASK_RD__usb__BITNR 31 -#define R_VECT_MASK_RD__usb__WIDTH 1 -#define R_VECT_MASK_RD__usb__active 1 -#define R_VECT_MASK_RD__usb__inactive 0 -#define R_VECT_MASK_RD__dma9__BITNR 25 -#define R_VECT_MASK_RD__dma9__WIDTH 1 -#define R_VECT_MASK_RD__dma9__active 1 -#define R_VECT_MASK_RD__dma9__inactive 0 -#define R_VECT_MASK_RD__dma8__BITNR 24 -#define R_VECT_MASK_RD__dma8__WIDTH 1 -#define R_VECT_MASK_RD__dma8__active 1 -#define R_VECT_MASK_RD__dma8__inactive 0 -#define R_VECT_MASK_RD__dma7__BITNR 23 -#define R_VECT_MASK_RD__dma7__WIDTH 1 -#define R_VECT_MASK_RD__dma7__active 1 -#define R_VECT_MASK_RD__dma7__inactive 0 -#define R_VECT_MASK_RD__dma6__BITNR 22 -#define R_VECT_MASK_RD__dma6__WIDTH 1 -#define R_VECT_MASK_RD__dma6__active 1 -#define R_VECT_MASK_RD__dma6__inactive 0 -#define R_VECT_MASK_RD__dma5__BITNR 21 -#define R_VECT_MASK_RD__dma5__WIDTH 1 -#define R_VECT_MASK_RD__dma5__active 1 -#define R_VECT_MASK_RD__dma5__inactive 0 -#define R_VECT_MASK_RD__dma4__BITNR 20 -#define R_VECT_MASK_RD__dma4__WIDTH 1 -#define R_VECT_MASK_RD__dma4__active 1 -#define R_VECT_MASK_RD__dma4__inactive 0 -#define R_VECT_MASK_RD__dma3__BITNR 19 -#define R_VECT_MASK_RD__dma3__WIDTH 1 -#define R_VECT_MASK_RD__dma3__active 1 -#define R_VECT_MASK_RD__dma3__inactive 0 -#define R_VECT_MASK_RD__dma2__BITNR 18 -#define R_VECT_MASK_RD__dma2__WIDTH 1 -#define R_VECT_MASK_RD__dma2__active 1 -#define R_VECT_MASK_RD__dma2__inactive 0 -#define R_VECT_MASK_RD__dma1__BITNR 17 -#define R_VECT_MASK_RD__dma1__WIDTH 1 -#define R_VECT_MASK_RD__dma1__active 1 -#define R_VECT_MASK_RD__dma1__inactive 0 -#define R_VECT_MASK_RD__dma0__BITNR 16 -#define R_VECT_MASK_RD__dma0__WIDTH 1 -#define R_VECT_MASK_RD__dma0__active 1 -#define R_VECT_MASK_RD__dma0__inactive 0 -#define R_VECT_MASK_RD__ext_dma1__BITNR 13 -#define R_VECT_MASK_RD__ext_dma1__WIDTH 1 -#define R_VECT_MASK_RD__ext_dma1__active 1 -#define R_VECT_MASK_RD__ext_dma1__inactive 0 -#define R_VECT_MASK_RD__ext_dma0__BITNR 12 -#define R_VECT_MASK_RD__ext_dma0__WIDTH 1 -#define R_VECT_MASK_RD__ext_dma0__active 1 -#define R_VECT_MASK_RD__ext_dma0__inactive 0 -#define R_VECT_MASK_RD__pa__BITNR 11 -#define R_VECT_MASK_RD__pa__WIDTH 1 -#define R_VECT_MASK_RD__pa__active 1 -#define R_VECT_MASK_RD__pa__inactive 0 -#define R_VECT_MASK_RD__irq_intnr__BITNR 10 -#define R_VECT_MASK_RD__irq_intnr__WIDTH 1 -#define R_VECT_MASK_RD__irq_intnr__active 1 -#define R_VECT_MASK_RD__irq_intnr__inactive 0 -#define R_VECT_MASK_RD__sw__BITNR 9 -#define R_VECT_MASK_RD__sw__WIDTH 1 -#define R_VECT_MASK_RD__sw__active 1 -#define R_VECT_MASK_RD__sw__inactive 0 -#define R_VECT_MASK_RD__serial__BITNR 8 -#define R_VECT_MASK_RD__serial__WIDTH 1 -#define R_VECT_MASK_RD__serial__active 1 -#define R_VECT_MASK_RD__serial__inactive 0 -#define R_VECT_MASK_RD__snmp__BITNR 7 -#define R_VECT_MASK_RD__snmp__WIDTH 1 -#define R_VECT_MASK_RD__snmp__active 1 -#define R_VECT_MASK_RD__snmp__inactive 0 -#define R_VECT_MASK_RD__network__BITNR 6 -#define R_VECT_MASK_RD__network__WIDTH 1 -#define R_VECT_MASK_RD__network__active 1 -#define R_VECT_MASK_RD__network__inactive 0 -#define R_VECT_MASK_RD__scsi1__BITNR 5 -#define R_VECT_MASK_RD__scsi1__WIDTH 1 -#define R_VECT_MASK_RD__scsi1__active 1 -#define R_VECT_MASK_RD__scsi1__inactive 0 -#define R_VECT_MASK_RD__par1__BITNR 5 -#define R_VECT_MASK_RD__par1__WIDTH 1 -#define R_VECT_MASK_RD__par1__active 1 -#define R_VECT_MASK_RD__par1__inactive 0 -#define R_VECT_MASK_RD__scsi0__BITNR 4 -#define R_VECT_MASK_RD__scsi0__WIDTH 1 -#define R_VECT_MASK_RD__scsi0__active 1 -#define R_VECT_MASK_RD__scsi0__inactive 0 -#define R_VECT_MASK_RD__par0__BITNR 4 -#define R_VECT_MASK_RD__par0__WIDTH 1 -#define R_VECT_MASK_RD__par0__active 1 -#define R_VECT_MASK_RD__par0__inactive 0 -#define R_VECT_MASK_RD__ata__BITNR 4 -#define R_VECT_MASK_RD__ata__WIDTH 1 -#define R_VECT_MASK_RD__ata__active 1 -#define R_VECT_MASK_RD__ata__inactive 0 -#define R_VECT_MASK_RD__mio__BITNR 4 -#define R_VECT_MASK_RD__mio__WIDTH 1 -#define R_VECT_MASK_RD__mio__active 1 -#define R_VECT_MASK_RD__mio__inactive 0 -#define R_VECT_MASK_RD__timer1__BITNR 3 -#define R_VECT_MASK_RD__timer1__WIDTH 1 -#define R_VECT_MASK_RD__timer1__active 1 -#define R_VECT_MASK_RD__timer1__inactive 0 -#define R_VECT_MASK_RD__timer0__BITNR 2 -#define R_VECT_MASK_RD__timer0__WIDTH 1 -#define R_VECT_MASK_RD__timer0__active 1 -#define R_VECT_MASK_RD__timer0__inactive 0 -#define R_VECT_MASK_RD__nmi__BITNR 1 -#define R_VECT_MASK_RD__nmi__WIDTH 1 -#define R_VECT_MASK_RD__nmi__active 1 -#define R_VECT_MASK_RD__nmi__inactive 0 -#define R_VECT_MASK_RD__some__BITNR 0 -#define R_VECT_MASK_RD__some__WIDTH 1 -#define R_VECT_MASK_RD__some__active 1 -#define R_VECT_MASK_RD__some__inactive 0 - -#define R_VECT_MASK_CLR (IO_TYPECAST_UDWORD 0xb00000d8) -#define R_VECT_MASK_CLR__usb__BITNR 31 -#define R_VECT_MASK_CLR__usb__WIDTH 1 -#define R_VECT_MASK_CLR__usb__clr 1 -#define R_VECT_MASK_CLR__usb__nop 0 -#define R_VECT_MASK_CLR__dma9__BITNR 25 -#define R_VECT_MASK_CLR__dma9__WIDTH 1 -#define R_VECT_MASK_CLR__dma9__clr 1 -#define R_VECT_MASK_CLR__dma9__nop 0 -#define R_VECT_MASK_CLR__dma8__BITNR 24 -#define R_VECT_MASK_CLR__dma8__WIDTH 1 -#define R_VECT_MASK_CLR__dma8__clr 1 -#define R_VECT_MASK_CLR__dma8__nop 0 -#define R_VECT_MASK_CLR__dma7__BITNR 23 -#define R_VECT_MASK_CLR__dma7__WIDTH 1 -#define R_VECT_MASK_CLR__dma7__clr 1 -#define R_VECT_MASK_CLR__dma7__nop 0 -#define R_VECT_MASK_CLR__dma6__BITNR 22 -#define R_VECT_MASK_CLR__dma6__WIDTH 1 -#define R_VECT_MASK_CLR__dma6__clr 1 -#define R_VECT_MASK_CLR__dma6__nop 0 -#define R_VECT_MASK_CLR__dma5__BITNR 21 -#define R_VECT_MASK_CLR__dma5__WIDTH 1 -#define R_VECT_MASK_CLR__dma5__clr 1 -#define R_VECT_MASK_CLR__dma5__nop 0 -#define R_VECT_MASK_CLR__dma4__BITNR 20 -#define R_VECT_MASK_CLR__dma4__WIDTH 1 -#define R_VECT_MASK_CLR__dma4__clr 1 -#define R_VECT_MASK_CLR__dma4__nop 0 -#define R_VECT_MASK_CLR__dma3__BITNR 19 -#define R_VECT_MASK_CLR__dma3__WIDTH 1 -#define R_VECT_MASK_CLR__dma3__clr 1 -#define R_VECT_MASK_CLR__dma3__nop 0 -#define R_VECT_MASK_CLR__dma2__BITNR 18 -#define R_VECT_MASK_CLR__dma2__WIDTH 1 -#define R_VECT_MASK_CLR__dma2__clr 1 -#define R_VECT_MASK_CLR__dma2__nop 0 -#define R_VECT_MASK_CLR__dma1__BITNR 17 -#define R_VECT_MASK_CLR__dma1__WIDTH 1 -#define R_VECT_MASK_CLR__dma1__clr 1 -#define R_VECT_MASK_CLR__dma1__nop 0 -#define R_VECT_MASK_CLR__dma0__BITNR 16 -#define R_VECT_MASK_CLR__dma0__WIDTH 1 -#define R_VECT_MASK_CLR__dma0__clr 1 -#define R_VECT_MASK_CLR__dma0__nop 0 -#define R_VECT_MASK_CLR__ext_dma1__BITNR 13 -#define R_VECT_MASK_CLR__ext_dma1__WIDTH 1 -#define R_VECT_MASK_CLR__ext_dma1__clr 1 -#define R_VECT_MASK_CLR__ext_dma1__nop 0 -#define R_VECT_MASK_CLR__ext_dma0__BITNR 12 -#define R_VECT_MASK_CLR__ext_dma0__WIDTH 1 -#define R_VECT_MASK_CLR__ext_dma0__clr 1 -#define R_VECT_MASK_CLR__ext_dma0__nop 0 -#define R_VECT_MASK_CLR__pa__BITNR 11 -#define R_VECT_MASK_CLR__pa__WIDTH 1 -#define R_VECT_MASK_CLR__pa__clr 1 -#define R_VECT_MASK_CLR__pa__nop 0 -#define R_VECT_MASK_CLR__irq_intnr__BITNR 10 -#define R_VECT_MASK_CLR__irq_intnr__WIDTH 1 -#define R_VECT_MASK_CLR__irq_intnr__clr 1 -#define R_VECT_MASK_CLR__irq_intnr__nop 0 -#define R_VECT_MASK_CLR__sw__BITNR 9 -#define R_VECT_MASK_CLR__sw__WIDTH 1 -#define R_VECT_MASK_CLR__sw__clr 1 -#define R_VECT_MASK_CLR__sw__nop 0 -#define R_VECT_MASK_CLR__serial__BITNR 8 -#define R_VECT_MASK_CLR__serial__WIDTH 1 -#define R_VECT_MASK_CLR__serial__clr 1 -#define R_VECT_MASK_CLR__serial__nop 0 -#define R_VECT_MASK_CLR__snmp__BITNR 7 -#define R_VECT_MASK_CLR__snmp__WIDTH 1 -#define R_VECT_MASK_CLR__snmp__clr 1 -#define R_VECT_MASK_CLR__snmp__nop 0 -#define R_VECT_MASK_CLR__network__BITNR 6 -#define R_VECT_MASK_CLR__network__WIDTH 1 -#define R_VECT_MASK_CLR__network__clr 1 -#define R_VECT_MASK_CLR__network__nop 0 -#define R_VECT_MASK_CLR__scsi1__BITNR 5 -#define R_VECT_MASK_CLR__scsi1__WIDTH 1 -#define R_VECT_MASK_CLR__scsi1__clr 1 -#define R_VECT_MASK_CLR__scsi1__nop 0 -#define R_VECT_MASK_CLR__par1__BITNR 5 -#define R_VECT_MASK_CLR__par1__WIDTH 1 -#define R_VECT_MASK_CLR__par1__clr 1 -#define R_VECT_MASK_CLR__par1__nop 0 -#define R_VECT_MASK_CLR__scsi0__BITNR 4 -#define R_VECT_MASK_CLR__scsi0__WIDTH 1 -#define R_VECT_MASK_CLR__scsi0__clr 1 -#define R_VECT_MASK_CLR__scsi0__nop 0 -#define R_VECT_MASK_CLR__par0__BITNR 4 -#define R_VECT_MASK_CLR__par0__WIDTH 1 -#define R_VECT_MASK_CLR__par0__clr 1 -#define R_VECT_MASK_CLR__par0__nop 0 -#define R_VECT_MASK_CLR__ata__BITNR 4 -#define R_VECT_MASK_CLR__ata__WIDTH 1 -#define R_VECT_MASK_CLR__ata__clr 1 -#define R_VECT_MASK_CLR__ata__nop 0 -#define R_VECT_MASK_CLR__mio__BITNR 4 -#define R_VECT_MASK_CLR__mio__WIDTH 1 -#define R_VECT_MASK_CLR__mio__clr 1 -#define R_VECT_MASK_CLR__mio__nop 0 -#define R_VECT_MASK_CLR__timer1__BITNR 3 -#define R_VECT_MASK_CLR__timer1__WIDTH 1 -#define R_VECT_MASK_CLR__timer1__clr 1 -#define R_VECT_MASK_CLR__timer1__nop 0 -#define R_VECT_MASK_CLR__timer0__BITNR 2 -#define R_VECT_MASK_CLR__timer0__WIDTH 1 -#define R_VECT_MASK_CLR__timer0__clr 1 -#define R_VECT_MASK_CLR__timer0__nop 0 -#define R_VECT_MASK_CLR__nmi__BITNR 1 -#define R_VECT_MASK_CLR__nmi__WIDTH 1 -#define R_VECT_MASK_CLR__nmi__clr 1 -#define R_VECT_MASK_CLR__nmi__nop 0 -#define R_VECT_MASK_CLR__some__BITNR 0 -#define R_VECT_MASK_CLR__some__WIDTH 1 -#define R_VECT_MASK_CLR__some__clr 1 -#define R_VECT_MASK_CLR__some__nop 0 - -#define R_VECT_READ (IO_TYPECAST_RO_UDWORD 0xb00000dc) -#define R_VECT_READ__usb__BITNR 31 -#define R_VECT_READ__usb__WIDTH 1 -#define R_VECT_READ__usb__active 1 -#define R_VECT_READ__usb__inactive 0 -#define R_VECT_READ__dma9__BITNR 25 -#define R_VECT_READ__dma9__WIDTH 1 -#define R_VECT_READ__dma9__active 1 -#define R_VECT_READ__dma9__inactive 0 -#define R_VECT_READ__dma8__BITNR 24 -#define R_VECT_READ__dma8__WIDTH 1 -#define R_VECT_READ__dma8__active 1 -#define R_VECT_READ__dma8__inactive 0 -#define R_VECT_READ__dma7__BITNR 23 -#define R_VECT_READ__dma7__WIDTH 1 -#define R_VECT_READ__dma7__active 1 -#define R_VECT_READ__dma7__inactive 0 -#define R_VECT_READ__dma6__BITNR 22 -#define R_VECT_READ__dma6__WIDTH 1 -#define R_VECT_READ__dma6__active 1 -#define R_VECT_READ__dma6__inactive 0 -#define R_VECT_READ__dma5__BITNR 21 -#define R_VECT_READ__dma5__WIDTH 1 -#define R_VECT_READ__dma5__active 1 -#define R_VECT_READ__dma5__inactive 0 -#define R_VECT_READ__dma4__BITNR 20 -#define R_VECT_READ__dma4__WIDTH 1 -#define R_VECT_READ__dma4__active 1 -#define R_VECT_READ__dma4__inactive 0 -#define R_VECT_READ__dma3__BITNR 19 -#define R_VECT_READ__dma3__WIDTH 1 -#define R_VECT_READ__dma3__active 1 -#define R_VECT_READ__dma3__inactive 0 -#define R_VECT_READ__dma2__BITNR 18 -#define R_VECT_READ__dma2__WIDTH 1 -#define R_VECT_READ__dma2__active 1 -#define R_VECT_READ__dma2__inactive 0 -#define R_VECT_READ__dma1__BITNR 17 -#define R_VECT_READ__dma1__WIDTH 1 -#define R_VECT_READ__dma1__active 1 -#define R_VECT_READ__dma1__inactive 0 -#define R_VECT_READ__dma0__BITNR 16 -#define R_VECT_READ__dma0__WIDTH 1 -#define R_VECT_READ__dma0__active 1 -#define R_VECT_READ__dma0__inactive 0 -#define R_VECT_READ__ext_dma1__BITNR 13 -#define R_VECT_READ__ext_dma1__WIDTH 1 -#define R_VECT_READ__ext_dma1__active 1 -#define R_VECT_READ__ext_dma1__inactive 0 -#define R_VECT_READ__ext_dma0__BITNR 12 -#define R_VECT_READ__ext_dma0__WIDTH 1 -#define R_VECT_READ__ext_dma0__active 1 -#define R_VECT_READ__ext_dma0__inactive 0 -#define R_VECT_READ__pa__BITNR 11 -#define R_VECT_READ__pa__WIDTH 1 -#define R_VECT_READ__pa__active 1 -#define R_VECT_READ__pa__inactive 0 -#define R_VECT_READ__irq_intnr__BITNR 10 -#define R_VECT_READ__irq_intnr__WIDTH 1 -#define R_VECT_READ__irq_intnr__active 1 -#define R_VECT_READ__irq_intnr__inactive 0 -#define R_VECT_READ__sw__BITNR 9 -#define R_VECT_READ__sw__WIDTH 1 -#define R_VECT_READ__sw__active 1 -#define R_VECT_READ__sw__inactive 0 -#define R_VECT_READ__serial__BITNR 8 -#define R_VECT_READ__serial__WIDTH 1 -#define R_VECT_READ__serial__active 1 -#define R_VECT_READ__serial__inactive 0 -#define R_VECT_READ__snmp__BITNR 7 -#define R_VECT_READ__snmp__WIDTH 1 -#define R_VECT_READ__snmp__active 1 -#define R_VECT_READ__snmp__inactive 0 -#define R_VECT_READ__network__BITNR 6 -#define R_VECT_READ__network__WIDTH 1 -#define R_VECT_READ__network__active 1 -#define R_VECT_READ__network__inactive 0 -#define R_VECT_READ__scsi1__BITNR 5 -#define R_VECT_READ__scsi1__WIDTH 1 -#define R_VECT_READ__scsi1__active 1 -#define R_VECT_READ__scsi1__inactive 0 -#define R_VECT_READ__par1__BITNR 5 -#define R_VECT_READ__par1__WIDTH 1 -#define R_VECT_READ__par1__active 1 -#define R_VECT_READ__par1__inactive 0 -#define R_VECT_READ__scsi0__BITNR 4 -#define R_VECT_READ__scsi0__WIDTH 1 -#define R_VECT_READ__scsi0__active 1 -#define R_VECT_READ__scsi0__inactive 0 -#define R_VECT_READ__par0__BITNR 4 -#define R_VECT_READ__par0__WIDTH 1 -#define R_VECT_READ__par0__active 1 -#define R_VECT_READ__par0__inactive 0 -#define R_VECT_READ__ata__BITNR 4 -#define R_VECT_READ__ata__WIDTH 1 -#define R_VECT_READ__ata__active 1 -#define R_VECT_READ__ata__inactive 0 -#define R_VECT_READ__mio__BITNR 4 -#define R_VECT_READ__mio__WIDTH 1 -#define R_VECT_READ__mio__active 1 -#define R_VECT_READ__mio__inactive 0 -#define R_VECT_READ__timer1__BITNR 3 -#define R_VECT_READ__timer1__WIDTH 1 -#define R_VECT_READ__timer1__active 1 -#define R_VECT_READ__timer1__inactive 0 -#define R_VECT_READ__timer0__BITNR 2 -#define R_VECT_READ__timer0__WIDTH 1 -#define R_VECT_READ__timer0__active 1 -#define R_VECT_READ__timer0__inactive 0 -#define R_VECT_READ__nmi__BITNR 1 -#define R_VECT_READ__nmi__WIDTH 1 -#define R_VECT_READ__nmi__active 1 -#define R_VECT_READ__nmi__inactive 0 -#define R_VECT_READ__some__BITNR 0 -#define R_VECT_READ__some__WIDTH 1 -#define R_VECT_READ__some__active 1 -#define R_VECT_READ__some__inactive 0 - -#define R_VECT_MASK_SET (IO_TYPECAST_UDWORD 0xb00000dc) -#define R_VECT_MASK_SET__usb__BITNR 31 -#define R_VECT_MASK_SET__usb__WIDTH 1 -#define R_VECT_MASK_SET__usb__set 1 -#define R_VECT_MASK_SET__usb__nop 0 -#define R_VECT_MASK_SET__dma9__BITNR 25 -#define R_VECT_MASK_SET__dma9__WIDTH 1 -#define R_VECT_MASK_SET__dma9__set 1 -#define R_VECT_MASK_SET__dma9__nop 0 -#define R_VECT_MASK_SET__dma8__BITNR 24 -#define R_VECT_MASK_SET__dma8__WIDTH 1 -#define R_VECT_MASK_SET__dma8__set 1 -#define R_VECT_MASK_SET__dma8__nop 0 -#define R_VECT_MASK_SET__dma7__BITNR 23 -#define R_VECT_MASK_SET__dma7__WIDTH 1 -#define R_VECT_MASK_SET__dma7__set 1 -#define R_VECT_MASK_SET__dma7__nop 0 -#define R_VECT_MASK_SET__dma6__BITNR 22 -#define R_VECT_MASK_SET__dma6__WIDTH 1 -#define R_VECT_MASK_SET__dma6__set 1 -#define R_VECT_MASK_SET__dma6__nop 0 -#define R_VECT_MASK_SET__dma5__BITNR 21 -#define R_VECT_MASK_SET__dma5__WIDTH 1 -#define R_VECT_MASK_SET__dma5__set 1 -#define R_VECT_MASK_SET__dma5__nop 0 -#define R_VECT_MASK_SET__dma4__BITNR 20 -#define R_VECT_MASK_SET__dma4__WIDTH 1 -#define R_VECT_MASK_SET__dma4__set 1 -#define R_VECT_MASK_SET__dma4__nop 0 -#define R_VECT_MASK_SET__dma3__BITNR 19 -#define R_VECT_MASK_SET__dma3__WIDTH 1 -#define R_VECT_MASK_SET__dma3__set 1 -#define R_VECT_MASK_SET__dma3__nop 0 -#define R_VECT_MASK_SET__dma2__BITNR 18 -#define R_VECT_MASK_SET__dma2__WIDTH 1 -#define R_VECT_MASK_SET__dma2__set 1 -#define R_VECT_MASK_SET__dma2__nop 0 -#define R_VECT_MASK_SET__dma1__BITNR 17 -#define R_VECT_MASK_SET__dma1__WIDTH 1 -#define R_VECT_MASK_SET__dma1__set 1 -#define R_VECT_MASK_SET__dma1__nop 0 -#define R_VECT_MASK_SET__dma0__BITNR 16 -#define R_VECT_MASK_SET__dma0__WIDTH 1 -#define R_VECT_MASK_SET__dma0__set 1 -#define R_VECT_MASK_SET__dma0__nop 0 -#define R_VECT_MASK_SET__ext_dma1__BITNR 13 -#define R_VECT_MASK_SET__ext_dma1__WIDTH 1 -#define R_VECT_MASK_SET__ext_dma1__set 1 -#define R_VECT_MASK_SET__ext_dma1__nop 0 -#define R_VECT_MASK_SET__ext_dma0__BITNR 12 -#define R_VECT_MASK_SET__ext_dma0__WIDTH 1 -#define R_VECT_MASK_SET__ext_dma0__set 1 -#define R_VECT_MASK_SET__ext_dma0__nop 0 -#define R_VECT_MASK_SET__pa__BITNR 11 -#define R_VECT_MASK_SET__pa__WIDTH 1 -#define R_VECT_MASK_SET__pa__set 1 -#define R_VECT_MASK_SET__pa__nop 0 -#define R_VECT_MASK_SET__irq_intnr__BITNR 10 -#define R_VECT_MASK_SET__irq_intnr__WIDTH 1 -#define R_VECT_MASK_SET__irq_intnr__set 1 -#define R_VECT_MASK_SET__irq_intnr__nop 0 -#define R_VECT_MASK_SET__sw__BITNR 9 -#define R_VECT_MASK_SET__sw__WIDTH 1 -#define R_VECT_MASK_SET__sw__set 1 -#define R_VECT_MASK_SET__sw__nop 0 -#define R_VECT_MASK_SET__serial__BITNR 8 -#define R_VECT_MASK_SET__serial__WIDTH 1 -#define R_VECT_MASK_SET__serial__set 1 -#define R_VECT_MASK_SET__serial__nop 0 -#define R_VECT_MASK_SET__snmp__BITNR 7 -#define R_VECT_MASK_SET__snmp__WIDTH 1 -#define R_VECT_MASK_SET__snmp__set 1 -#define R_VECT_MASK_SET__snmp__nop 0 -#define R_VECT_MASK_SET__network__BITNR 6 -#define R_VECT_MASK_SET__network__WIDTH 1 -#define R_VECT_MASK_SET__network__set 1 -#define R_VECT_MASK_SET__network__nop 0 -#define R_VECT_MASK_SET__scsi1__BITNR 5 -#define R_VECT_MASK_SET__scsi1__WIDTH 1 -#define R_VECT_MASK_SET__scsi1__set 1 -#define R_VECT_MASK_SET__scsi1__nop 0 -#define R_VECT_MASK_SET__par1__BITNR 5 -#define R_VECT_MASK_SET__par1__WIDTH 1 -#define R_VECT_MASK_SET__par1__set 1 -#define R_VECT_MASK_SET__par1__nop 0 -#define R_VECT_MASK_SET__scsi0__BITNR 4 -#define R_VECT_MASK_SET__scsi0__WIDTH 1 -#define R_VECT_MASK_SET__scsi0__set 1 -#define R_VECT_MASK_SET__scsi0__nop 0 -#define R_VECT_MASK_SET__par0__BITNR 4 -#define R_VECT_MASK_SET__par0__WIDTH 1 -#define R_VECT_MASK_SET__par0__set 1 -#define R_VECT_MASK_SET__par0__nop 0 -#define R_VECT_MASK_SET__ata__BITNR 4 -#define R_VECT_MASK_SET__ata__WIDTH 1 -#define R_VECT_MASK_SET__ata__set 1 -#define R_VECT_MASK_SET__ata__nop 0 -#define R_VECT_MASK_SET__mio__BITNR 4 -#define R_VECT_MASK_SET__mio__WIDTH 1 -#define R_VECT_MASK_SET__mio__set 1 -#define R_VECT_MASK_SET__mio__nop 0 -#define R_VECT_MASK_SET__timer1__BITNR 3 -#define R_VECT_MASK_SET__timer1__WIDTH 1 -#define R_VECT_MASK_SET__timer1__set 1 -#define R_VECT_MASK_SET__timer1__nop 0 -#define R_VECT_MASK_SET__timer0__BITNR 2 -#define R_VECT_MASK_SET__timer0__WIDTH 1 -#define R_VECT_MASK_SET__timer0__set 1 -#define R_VECT_MASK_SET__timer0__nop 0 -#define R_VECT_MASK_SET__nmi__BITNR 1 -#define R_VECT_MASK_SET__nmi__WIDTH 1 -#define R_VECT_MASK_SET__nmi__set 1 -#define R_VECT_MASK_SET__nmi__nop 0 -#define R_VECT_MASK_SET__some__BITNR 0 -#define R_VECT_MASK_SET__some__WIDTH 1 -#define R_VECT_MASK_SET__some__set 1 -#define R_VECT_MASK_SET__some__nop 0 - -/* -!* DMA registers -!*/ - -#define R_SET_EOP (IO_TYPECAST_UDWORD 0xb000003c) -#define R_SET_EOP__ch9_eop__BITNR 3 -#define R_SET_EOP__ch9_eop__WIDTH 1 -#define R_SET_EOP__ch9_eop__set 1 -#define R_SET_EOP__ch9_eop__nop 0 -#define R_SET_EOP__ch7_eop__BITNR 2 -#define R_SET_EOP__ch7_eop__WIDTH 1 -#define R_SET_EOP__ch7_eop__set 1 -#define R_SET_EOP__ch7_eop__nop 0 -#define R_SET_EOP__ch5_eop__BITNR 1 -#define R_SET_EOP__ch5_eop__WIDTH 1 -#define R_SET_EOP__ch5_eop__set 1 -#define R_SET_EOP__ch5_eop__nop 0 -#define R_SET_EOP__ch3_eop__BITNR 0 -#define R_SET_EOP__ch3_eop__WIDTH 1 -#define R_SET_EOP__ch3_eop__set 1 -#define R_SET_EOP__ch3_eop__nop 0 - -#define R_DMA_CH0_HWSW (IO_TYPECAST_UDWORD 0xb0000100) -#define R_DMA_CH0_HWSW__hw__BITNR 16 -#define R_DMA_CH0_HWSW__hw__WIDTH 16 -#define R_DMA_CH0_HWSW__sw__BITNR 0 -#define R_DMA_CH0_HWSW__sw__WIDTH 16 - -#define R_DMA_CH0_DESCR (IO_TYPECAST_UDWORD 0xb000010c) -#define R_DMA_CH0_DESCR__descr__BITNR 0 -#define R_DMA_CH0_DESCR__descr__WIDTH 32 - -#define R_DMA_CH0_NEXT (IO_TYPECAST_UDWORD 0xb0000104) -#define R_DMA_CH0_NEXT__next__BITNR 0 -#define R_DMA_CH0_NEXT__next__WIDTH 32 - -#define R_DMA_CH0_BUF (IO_TYPECAST_UDWORD 0xb0000108) -#define R_DMA_CH0_BUF__buf__BITNR 0 -#define R_DMA_CH0_BUF__buf__WIDTH 32 - -#define R_DMA_CH0_FIRST (IO_TYPECAST_UDWORD 0xb00001a0) -#define R_DMA_CH0_FIRST__first__BITNR 0 -#define R_DMA_CH0_FIRST__first__WIDTH 32 - -#define R_DMA_CH0_CMD (IO_TYPECAST_BYTE 0xb00001d0) -#define R_DMA_CH0_CMD__cmd__BITNR 0 -#define R_DMA_CH0_CMD__cmd__WIDTH 3 -#define R_DMA_CH0_CMD__cmd__hold 0 -#define R_DMA_CH0_CMD__cmd__start 1 -#define R_DMA_CH0_CMD__cmd__restart 3 -#define R_DMA_CH0_CMD__cmd__continue 3 -#define R_DMA_CH0_CMD__cmd__reset 4 - -#define R_DMA_CH0_CLR_INTR (IO_TYPECAST_BYTE 0xb00001d1) -#define R_DMA_CH0_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH0_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH0_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH0_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH0_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH0_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH0_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH0_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH0_STATUS (IO_TYPECAST_RO_BYTE 0xb00001d2) -#define R_DMA_CH0_STATUS__avail__BITNR 0 -#define R_DMA_CH0_STATUS__avail__WIDTH 7 - -#define R_DMA_CH1_HWSW (IO_TYPECAST_UDWORD 0xb0000110) -#define R_DMA_CH1_HWSW__hw__BITNR 16 -#define R_DMA_CH1_HWSW__hw__WIDTH 16 -#define R_DMA_CH1_HWSW__sw__BITNR 0 -#define R_DMA_CH1_HWSW__sw__WIDTH 16 - -#define R_DMA_CH1_DESCR (IO_TYPECAST_UDWORD 0xb000011c) -#define R_DMA_CH1_DESCR__descr__BITNR 0 -#define R_DMA_CH1_DESCR__descr__WIDTH 32 - -#define R_DMA_CH1_NEXT (IO_TYPECAST_UDWORD 0xb0000114) -#define R_DMA_CH1_NEXT__next__BITNR 0 -#define R_DMA_CH1_NEXT__next__WIDTH 32 - -#define R_DMA_CH1_BUF (IO_TYPECAST_UDWORD 0xb0000118) -#define R_DMA_CH1_BUF__buf__BITNR 0 -#define R_DMA_CH1_BUF__buf__WIDTH 32 - -#define R_DMA_CH1_FIRST (IO_TYPECAST_UDWORD 0xb00001a4) -#define R_DMA_CH1_FIRST__first__BITNR 0 -#define R_DMA_CH1_FIRST__first__WIDTH 32 - -#define R_DMA_CH1_CMD (IO_TYPECAST_BYTE 0xb00001d4) -#define R_DMA_CH1_CMD__cmd__BITNR 0 -#define R_DMA_CH1_CMD__cmd__WIDTH 3 -#define R_DMA_CH1_CMD__cmd__hold 0 -#define R_DMA_CH1_CMD__cmd__start 1 -#define R_DMA_CH1_CMD__cmd__restart 3 -#define R_DMA_CH1_CMD__cmd__continue 3 -#define R_DMA_CH1_CMD__cmd__reset 4 - -#define R_DMA_CH1_CLR_INTR (IO_TYPECAST_BYTE 0xb00001d5) -#define R_DMA_CH1_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH1_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH1_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH1_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH1_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH1_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH1_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH1_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH1_STATUS (IO_TYPECAST_RO_BYTE 0xb00001d6) -#define R_DMA_CH1_STATUS__avail__BITNR 0 -#define R_DMA_CH1_STATUS__avail__WIDTH 7 - -#define R_DMA_CH2_HWSW (IO_TYPECAST_UDWORD 0xb0000120) -#define R_DMA_CH2_HWSW__hw__BITNR 16 -#define R_DMA_CH2_HWSW__hw__WIDTH 16 -#define R_DMA_CH2_HWSW__sw__BITNR 0 -#define R_DMA_CH2_HWSW__sw__WIDTH 16 - -#define R_DMA_CH2_DESCR (IO_TYPECAST_UDWORD 0xb000012c) -#define R_DMA_CH2_DESCR__descr__BITNR 0 -#define R_DMA_CH2_DESCR__descr__WIDTH 32 - -#define R_DMA_CH2_NEXT (IO_TYPECAST_UDWORD 0xb0000124) -#define R_DMA_CH2_NEXT__next__BITNR 0 -#define R_DMA_CH2_NEXT__next__WIDTH 32 - -#define R_DMA_CH2_BUF (IO_TYPECAST_UDWORD 0xb0000128) -#define R_DMA_CH2_BUF__buf__BITNR 0 -#define R_DMA_CH2_BUF__buf__WIDTH 32 - -#define R_DMA_CH2_FIRST (IO_TYPECAST_UDWORD 0xb00001a8) -#define R_DMA_CH2_FIRST__first__BITNR 0 -#define R_DMA_CH2_FIRST__first__WIDTH 32 - -#define R_DMA_CH2_CMD (IO_TYPECAST_BYTE 0xb00001d8) -#define R_DMA_CH2_CMD__cmd__BITNR 0 -#define R_DMA_CH2_CMD__cmd__WIDTH 3 -#define R_DMA_CH2_CMD__cmd__hold 0 -#define R_DMA_CH2_CMD__cmd__start 1 -#define R_DMA_CH2_CMD__cmd__restart 3 -#define R_DMA_CH2_CMD__cmd__continue 3 -#define R_DMA_CH2_CMD__cmd__reset 4 - -#define R_DMA_CH2_CLR_INTR (IO_TYPECAST_BYTE 0xb00001d9) -#define R_DMA_CH2_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH2_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH2_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH2_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH2_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH2_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH2_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH2_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH2_STATUS (IO_TYPECAST_RO_BYTE 0xb00001da) -#define R_DMA_CH2_STATUS__avail__BITNR 0 -#define R_DMA_CH2_STATUS__avail__WIDTH 7 - -#define R_DMA_CH3_HWSW (IO_TYPECAST_UDWORD 0xb0000130) -#define R_DMA_CH3_HWSW__hw__BITNR 16 -#define R_DMA_CH3_HWSW__hw__WIDTH 16 -#define R_DMA_CH3_HWSW__sw__BITNR 0 -#define R_DMA_CH3_HWSW__sw__WIDTH 16 - -#define R_DMA_CH3_DESCR (IO_TYPECAST_UDWORD 0xb000013c) -#define R_DMA_CH3_DESCR__descr__BITNR 0 -#define R_DMA_CH3_DESCR__descr__WIDTH 32 - -#define R_DMA_CH3_NEXT (IO_TYPECAST_UDWORD 0xb0000134) -#define R_DMA_CH3_NEXT__next__BITNR 0 -#define R_DMA_CH3_NEXT__next__WIDTH 32 - -#define R_DMA_CH3_BUF (IO_TYPECAST_UDWORD 0xb0000138) -#define R_DMA_CH3_BUF__buf__BITNR 0 -#define R_DMA_CH3_BUF__buf__WIDTH 32 - -#define R_DMA_CH3_FIRST (IO_TYPECAST_UDWORD 0xb00001ac) -#define R_DMA_CH3_FIRST__first__BITNR 0 -#define R_DMA_CH3_FIRST__first__WIDTH 32 - -#define R_DMA_CH3_CMD (IO_TYPECAST_BYTE 0xb00001dc) -#define R_DMA_CH3_CMD__cmd__BITNR 0 -#define R_DMA_CH3_CMD__cmd__WIDTH 3 -#define R_DMA_CH3_CMD__cmd__hold 0 -#define R_DMA_CH3_CMD__cmd__start 1 -#define R_DMA_CH3_CMD__cmd__restart 3 -#define R_DMA_CH3_CMD__cmd__continue 3 -#define R_DMA_CH3_CMD__cmd__reset 4 - -#define R_DMA_CH3_CLR_INTR (IO_TYPECAST_BYTE 0xb00001dd) -#define R_DMA_CH3_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH3_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH3_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH3_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH3_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH3_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH3_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH3_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH3_STATUS (IO_TYPECAST_RO_BYTE 0xb00001de) -#define R_DMA_CH3_STATUS__avail__BITNR 0 -#define R_DMA_CH3_STATUS__avail__WIDTH 7 - -#define R_DMA_CH4_HWSW (IO_TYPECAST_UDWORD 0xb0000140) -#define R_DMA_CH4_HWSW__hw__BITNR 16 -#define R_DMA_CH4_HWSW__hw__WIDTH 16 -#define R_DMA_CH4_HWSW__sw__BITNR 0 -#define R_DMA_CH4_HWSW__sw__WIDTH 16 - -#define R_DMA_CH4_DESCR (IO_TYPECAST_UDWORD 0xb000014c) -#define R_DMA_CH4_DESCR__descr__BITNR 0 -#define R_DMA_CH4_DESCR__descr__WIDTH 32 - -#define R_DMA_CH4_NEXT (IO_TYPECAST_UDWORD 0xb0000144) -#define R_DMA_CH4_NEXT__next__BITNR 0 -#define R_DMA_CH4_NEXT__next__WIDTH 32 - -#define R_DMA_CH4_BUF (IO_TYPECAST_UDWORD 0xb0000148) -#define R_DMA_CH4_BUF__buf__BITNR 0 -#define R_DMA_CH4_BUF__buf__WIDTH 32 - -#define R_DMA_CH4_FIRST (IO_TYPECAST_UDWORD 0xb00001b0) -#define R_DMA_CH4_FIRST__first__BITNR 0 -#define R_DMA_CH4_FIRST__first__WIDTH 32 - -#define R_DMA_CH4_CMD (IO_TYPECAST_BYTE 0xb00001e0) -#define R_DMA_CH4_CMD__cmd__BITNR 0 -#define R_DMA_CH4_CMD__cmd__WIDTH 3 -#define R_DMA_CH4_CMD__cmd__hold 0 -#define R_DMA_CH4_CMD__cmd__start 1 -#define R_DMA_CH4_CMD__cmd__restart 3 -#define R_DMA_CH4_CMD__cmd__continue 3 -#define R_DMA_CH4_CMD__cmd__reset 4 - -#define R_DMA_CH4_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e1) -#define R_DMA_CH4_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH4_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH4_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH4_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH4_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH4_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH4_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH4_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH4_STATUS (IO_TYPECAST_RO_BYTE 0xb00001e2) -#define R_DMA_CH4_STATUS__avail__BITNR 0 -#define R_DMA_CH4_STATUS__avail__WIDTH 7 - -#define R_DMA_CH5_HWSW (IO_TYPECAST_UDWORD 0xb0000150) -#define R_DMA_CH5_HWSW__hw__BITNR 16 -#define R_DMA_CH5_HWSW__hw__WIDTH 16 -#define R_DMA_CH5_HWSW__sw__BITNR 0 -#define R_DMA_CH5_HWSW__sw__WIDTH 16 - -#define R_DMA_CH5_DESCR (IO_TYPECAST_UDWORD 0xb000015c) -#define R_DMA_CH5_DESCR__descr__BITNR 0 -#define R_DMA_CH5_DESCR__descr__WIDTH 32 - -#define R_DMA_CH5_NEXT (IO_TYPECAST_UDWORD 0xb0000154) -#define R_DMA_CH5_NEXT__next__BITNR 0 -#define R_DMA_CH5_NEXT__next__WIDTH 32 - -#define R_DMA_CH5_BUF (IO_TYPECAST_UDWORD 0xb0000158) -#define R_DMA_CH5_BUF__buf__BITNR 0 -#define R_DMA_CH5_BUF__buf__WIDTH 32 - -#define R_DMA_CH5_FIRST (IO_TYPECAST_UDWORD 0xb00001b4) -#define R_DMA_CH5_FIRST__first__BITNR 0 -#define R_DMA_CH5_FIRST__first__WIDTH 32 - -#define R_DMA_CH5_CMD (IO_TYPECAST_BYTE 0xb00001e4) -#define R_DMA_CH5_CMD__cmd__BITNR 0 -#define R_DMA_CH5_CMD__cmd__WIDTH 3 -#define R_DMA_CH5_CMD__cmd__hold 0 -#define R_DMA_CH5_CMD__cmd__start 1 -#define R_DMA_CH5_CMD__cmd__restart 3 -#define R_DMA_CH5_CMD__cmd__continue 3 -#define R_DMA_CH5_CMD__cmd__reset 4 - -#define R_DMA_CH5_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e5) -#define R_DMA_CH5_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH5_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH5_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH5_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH5_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH5_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH5_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH5_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH5_STATUS (IO_TYPECAST_RO_BYTE 0xb00001e6) -#define R_DMA_CH5_STATUS__avail__BITNR 0 -#define R_DMA_CH5_STATUS__avail__WIDTH 7 - -#define R_DMA_CH6_HWSW (IO_TYPECAST_UDWORD 0xb0000160) -#define R_DMA_CH6_HWSW__hw__BITNR 16 -#define R_DMA_CH6_HWSW__hw__WIDTH 16 -#define R_DMA_CH6_HWSW__sw__BITNR 0 -#define R_DMA_CH6_HWSW__sw__WIDTH 16 - -#define R_DMA_CH6_DESCR (IO_TYPECAST_UDWORD 0xb000016c) -#define R_DMA_CH6_DESCR__descr__BITNR 0 -#define R_DMA_CH6_DESCR__descr__WIDTH 32 - -#define R_DMA_CH6_NEXT (IO_TYPECAST_UDWORD 0xb0000164) -#define R_DMA_CH6_NEXT__next__BITNR 0 -#define R_DMA_CH6_NEXT__next__WIDTH 32 - -#define R_DMA_CH6_BUF (IO_TYPECAST_UDWORD 0xb0000168) -#define R_DMA_CH6_BUF__buf__BITNR 0 -#define R_DMA_CH6_BUF__buf__WIDTH 32 - -#define R_DMA_CH6_FIRST (IO_TYPECAST_UDWORD 0xb00001b8) -#define R_DMA_CH6_FIRST__first__BITNR 0 -#define R_DMA_CH6_FIRST__first__WIDTH 32 - -#define R_DMA_CH6_CMD (IO_TYPECAST_BYTE 0xb00001e8) -#define R_DMA_CH6_CMD__cmd__BITNR 0 -#define R_DMA_CH6_CMD__cmd__WIDTH 3 -#define R_DMA_CH6_CMD__cmd__hold 0 -#define R_DMA_CH6_CMD__cmd__start 1 -#define R_DMA_CH6_CMD__cmd__restart 3 -#define R_DMA_CH6_CMD__cmd__continue 3 -#define R_DMA_CH6_CMD__cmd__reset 4 - -#define R_DMA_CH6_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e9) -#define R_DMA_CH6_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH6_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH6_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH6_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH6_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH6_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH6_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH6_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH6_STATUS (IO_TYPECAST_RO_BYTE 0xb00001ea) -#define R_DMA_CH6_STATUS__avail__BITNR 0 -#define R_DMA_CH6_STATUS__avail__WIDTH 7 - -#define R_DMA_CH7_HWSW (IO_TYPECAST_UDWORD 0xb0000170) -#define R_DMA_CH7_HWSW__hw__BITNR 16 -#define R_DMA_CH7_HWSW__hw__WIDTH 16 -#define R_DMA_CH7_HWSW__sw__BITNR 0 -#define R_DMA_CH7_HWSW__sw__WIDTH 16 - -#define R_DMA_CH7_DESCR (IO_TYPECAST_UDWORD 0xb000017c) -#define R_DMA_CH7_DESCR__descr__BITNR 0 -#define R_DMA_CH7_DESCR__descr__WIDTH 32 - -#define R_DMA_CH7_NEXT (IO_TYPECAST_UDWORD 0xb0000174) -#define R_DMA_CH7_NEXT__next__BITNR 0 -#define R_DMA_CH7_NEXT__next__WIDTH 32 - -#define R_DMA_CH7_BUF (IO_TYPECAST_UDWORD 0xb0000178) -#define R_DMA_CH7_BUF__buf__BITNR 0 -#define R_DMA_CH7_BUF__buf__WIDTH 32 - -#define R_DMA_CH7_FIRST (IO_TYPECAST_UDWORD 0xb00001bc) -#define R_DMA_CH7_FIRST__first__BITNR 0 -#define R_DMA_CH7_FIRST__first__WIDTH 32 - -#define R_DMA_CH7_CMD (IO_TYPECAST_BYTE 0xb00001ec) -#define R_DMA_CH7_CMD__cmd__BITNR 0 -#define R_DMA_CH7_CMD__cmd__WIDTH 3 -#define R_DMA_CH7_CMD__cmd__hold 0 -#define R_DMA_CH7_CMD__cmd__start 1 -#define R_DMA_CH7_CMD__cmd__restart 3 -#define R_DMA_CH7_CMD__cmd__continue 3 -#define R_DMA_CH7_CMD__cmd__reset 4 - -#define R_DMA_CH7_CLR_INTR (IO_TYPECAST_BYTE 0xb00001ed) -#define R_DMA_CH7_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH7_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH7_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH7_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH7_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH7_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH7_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH7_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH7_STATUS (IO_TYPECAST_RO_BYTE 0xb00001ee) -#define R_DMA_CH7_STATUS__avail__BITNR 0 -#define R_DMA_CH7_STATUS__avail__WIDTH 7 - -#define R_DMA_CH8_HWSW (IO_TYPECAST_UDWORD 0xb0000180) -#define R_DMA_CH8_HWSW__hw__BITNR 16 -#define R_DMA_CH8_HWSW__hw__WIDTH 16 -#define R_DMA_CH8_HWSW__sw__BITNR 0 -#define R_DMA_CH8_HWSW__sw__WIDTH 16 - -#define R_DMA_CH8_DESCR (IO_TYPECAST_UDWORD 0xb000018c) -#define R_DMA_CH8_DESCR__descr__BITNR 0 -#define R_DMA_CH8_DESCR__descr__WIDTH 32 - -#define R_DMA_CH8_NEXT (IO_TYPECAST_UDWORD 0xb0000184) -#define R_DMA_CH8_NEXT__next__BITNR 0 -#define R_DMA_CH8_NEXT__next__WIDTH 32 - -#define R_DMA_CH8_BUF (IO_TYPECAST_UDWORD 0xb0000188) -#define R_DMA_CH8_BUF__buf__BITNR 0 -#define R_DMA_CH8_BUF__buf__WIDTH 32 - -#define R_DMA_CH8_FIRST (IO_TYPECAST_UDWORD 0xb00001c0) -#define R_DMA_CH8_FIRST__first__BITNR 0 -#define R_DMA_CH8_FIRST__first__WIDTH 32 - -#define R_DMA_CH8_CMD (IO_TYPECAST_BYTE 0xb00001f0) -#define R_DMA_CH8_CMD__cmd__BITNR 0 -#define R_DMA_CH8_CMD__cmd__WIDTH 3 -#define R_DMA_CH8_CMD__cmd__hold 0 -#define R_DMA_CH8_CMD__cmd__start 1 -#define R_DMA_CH8_CMD__cmd__restart 3 -#define R_DMA_CH8_CMD__cmd__continue 3 -#define R_DMA_CH8_CMD__cmd__reset 4 - -#define R_DMA_CH8_CLR_INTR (IO_TYPECAST_BYTE 0xb00001f1) -#define R_DMA_CH8_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH8_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH8_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH8_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH8_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH8_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH8_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH8_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH8_STATUS (IO_TYPECAST_RO_BYTE 0xb00001f2) -#define R_DMA_CH8_STATUS__avail__BITNR 0 -#define R_DMA_CH8_STATUS__avail__WIDTH 7 - -#define R_DMA_CH8_SUB (IO_TYPECAST_UDWORD 0xb000018c) -#define R_DMA_CH8_SUB__sub__BITNR 0 -#define R_DMA_CH8_SUB__sub__WIDTH 32 - -#define R_DMA_CH8_NEP (IO_TYPECAST_UDWORD 0xb00001c0) -#define R_DMA_CH8_NEP__nep__BITNR 0 -#define R_DMA_CH8_NEP__nep__WIDTH 32 - -#define R_DMA_CH8_SUB0_EP (IO_TYPECAST_UDWORD 0xb00001c8) -#define R_DMA_CH8_SUB0_EP__ep__BITNR 0 -#define R_DMA_CH8_SUB0_EP__ep__WIDTH 32 - -#define R_DMA_CH8_SUB0_CMD (IO_TYPECAST_BYTE 0xb00001d3) -#define R_DMA_CH8_SUB0_CMD__cmd__BITNR 0 -#define R_DMA_CH8_SUB0_CMD__cmd__WIDTH 1 -#define R_DMA_CH8_SUB0_CMD__cmd__stop 0 -#define R_DMA_CH8_SUB0_CMD__cmd__start 1 - -#define R_DMA_CH8_SUB0_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e3) -#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__dont 0 -#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__do 1 - -#define R_DMA_CH8_SUB1_EP (IO_TYPECAST_UDWORD 0xb00001cc) -#define R_DMA_CH8_SUB1_EP__ep__BITNR 0 -#define R_DMA_CH8_SUB1_EP__ep__WIDTH 32 - -#define R_DMA_CH8_SUB1_CMD (IO_TYPECAST_BYTE 0xb00001d7) -#define R_DMA_CH8_SUB1_CMD__cmd__BITNR 0 -#define R_DMA_CH8_SUB1_CMD__cmd__WIDTH 1 -#define R_DMA_CH8_SUB1_CMD__cmd__stop 0 -#define R_DMA_CH8_SUB1_CMD__cmd__start 1 - -#define R_DMA_CH8_SUB1_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e7) -#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__dont 0 -#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__do 1 - -#define R_DMA_CH8_SUB2_EP (IO_TYPECAST_UDWORD 0xb00001f8) -#define R_DMA_CH8_SUB2_EP__ep__BITNR 0 -#define R_DMA_CH8_SUB2_EP__ep__WIDTH 32 - -#define R_DMA_CH8_SUB2_CMD (IO_TYPECAST_BYTE 0xb00001db) -#define R_DMA_CH8_SUB2_CMD__cmd__BITNR 0 -#define R_DMA_CH8_SUB2_CMD__cmd__WIDTH 1 -#define R_DMA_CH8_SUB2_CMD__cmd__stop 0 -#define R_DMA_CH8_SUB2_CMD__cmd__start 1 - -#define R_DMA_CH8_SUB2_CLR_INTR (IO_TYPECAST_BYTE 0xb00001eb) -#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__dont 0 -#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__do 1 - -#define R_DMA_CH8_SUB3_EP (IO_TYPECAST_UDWORD 0xb00001fc) -#define R_DMA_CH8_SUB3_EP__ep__BITNR 0 -#define R_DMA_CH8_SUB3_EP__ep__WIDTH 32 - -#define R_DMA_CH8_SUB3_CMD (IO_TYPECAST_BYTE 0xb00001df) -#define R_DMA_CH8_SUB3_CMD__cmd__BITNR 0 -#define R_DMA_CH8_SUB3_CMD__cmd__WIDTH 1 -#define R_DMA_CH8_SUB3_CMD__cmd__stop 0 -#define R_DMA_CH8_SUB3_CMD__cmd__start 1 - -#define R_DMA_CH8_SUB3_CLR_INTR (IO_TYPECAST_BYTE 0xb00001ef) -#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__dont 0 -#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__do 1 - -#define R_DMA_CH9_HWSW (IO_TYPECAST_UDWORD 0xb0000190) -#define R_DMA_CH9_HWSW__hw__BITNR 16 -#define R_DMA_CH9_HWSW__hw__WIDTH 16 -#define R_DMA_CH9_HWSW__sw__BITNR 0 -#define R_DMA_CH9_HWSW__sw__WIDTH 16 - -#define R_DMA_CH9_DESCR (IO_TYPECAST_UDWORD 0xb000019c) -#define R_DMA_CH9_DESCR__descr__BITNR 0 -#define R_DMA_CH9_DESCR__descr__WIDTH 32 - -#define R_DMA_CH9_NEXT (IO_TYPECAST_UDWORD 0xb0000194) -#define R_DMA_CH9_NEXT__next__BITNR 0 -#define R_DMA_CH9_NEXT__next__WIDTH 32 - -#define R_DMA_CH9_BUF (IO_TYPECAST_UDWORD 0xb0000198) -#define R_DMA_CH9_BUF__buf__BITNR 0 -#define R_DMA_CH9_BUF__buf__WIDTH 32 - -#define R_DMA_CH9_FIRST (IO_TYPECAST_UDWORD 0xb00001c4) -#define R_DMA_CH9_FIRST__first__BITNR 0 -#define R_DMA_CH9_FIRST__first__WIDTH 32 - -#define R_DMA_CH9_CMD (IO_TYPECAST_BYTE 0xb00001f4) -#define R_DMA_CH9_CMD__cmd__BITNR 0 -#define R_DMA_CH9_CMD__cmd__WIDTH 3 -#define R_DMA_CH9_CMD__cmd__hold 0 -#define R_DMA_CH9_CMD__cmd__start 1 -#define R_DMA_CH9_CMD__cmd__restart 3 -#define R_DMA_CH9_CMD__cmd__continue 3 -#define R_DMA_CH9_CMD__cmd__reset 4 - -#define R_DMA_CH9_CLR_INTR (IO_TYPECAST_BYTE 0xb00001f5) -#define R_DMA_CH9_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH9_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH9_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH9_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH9_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH9_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH9_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH9_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH9_STATUS (IO_TYPECAST_RO_BYTE 0xb00001f6) -#define R_DMA_CH9_STATUS__avail__BITNR 0 -#define R_DMA_CH9_STATUS__avail__WIDTH 7 - -/* -!* Test mode registers -!*/ - -#define R_TEST_MODE (IO_TYPECAST_UDWORD 0xb00000fc) -#define R_TEST_MODE__single_step__BITNR 19 -#define R_TEST_MODE__single_step__WIDTH 1 -#define R_TEST_MODE__single_step__on 1 -#define R_TEST_MODE__single_step__off 0 -#define R_TEST_MODE__step_wr__BITNR 18 -#define R_TEST_MODE__step_wr__WIDTH 1 -#define R_TEST_MODE__step_wr__on 1 -#define R_TEST_MODE__step_wr__off 0 -#define R_TEST_MODE__step_rd__BITNR 17 -#define R_TEST_MODE__step_rd__WIDTH 1 -#define R_TEST_MODE__step_rd__on 1 -#define R_TEST_MODE__step_rd__off 0 -#define R_TEST_MODE__step_fetch__BITNR 16 -#define R_TEST_MODE__step_fetch__WIDTH 1 -#define R_TEST_MODE__step_fetch__on 1 -#define R_TEST_MODE__step_fetch__off 0 -#define R_TEST_MODE__mmu_test__BITNR 12 -#define R_TEST_MODE__mmu_test__WIDTH 1 -#define R_TEST_MODE__mmu_test__on 1 -#define R_TEST_MODE__mmu_test__off 0 -#define R_TEST_MODE__usb_test__BITNR 11 -#define R_TEST_MODE__usb_test__WIDTH 1 -#define R_TEST_MODE__usb_test__on 1 -#define R_TEST_MODE__usb_test__off 0 -#define R_TEST_MODE__scsi_timer_test__BITNR 10 -#define R_TEST_MODE__scsi_timer_test__WIDTH 1 -#define R_TEST_MODE__scsi_timer_test__on 1 -#define R_TEST_MODE__scsi_timer_test__off 0 -#define R_TEST_MODE__backoff__BITNR 9 -#define R_TEST_MODE__backoff__WIDTH 1 -#define R_TEST_MODE__backoff__on 1 -#define R_TEST_MODE__backoff__off 0 -#define R_TEST_MODE__snmp_test__BITNR 8 -#define R_TEST_MODE__snmp_test__WIDTH 1 -#define R_TEST_MODE__snmp_test__on 1 -#define R_TEST_MODE__snmp_test__off 0 -#define R_TEST_MODE__snmp_inc__BITNR 7 -#define R_TEST_MODE__snmp_inc__WIDTH 1 -#define R_TEST_MODE__snmp_inc__do 1 -#define R_TEST_MODE__snmp_inc__dont 0 -#define R_TEST_MODE__ser_loop__BITNR 6 -#define R_TEST_MODE__ser_loop__WIDTH 1 -#define R_TEST_MODE__ser_loop__on 1 -#define R_TEST_MODE__ser_loop__off 0 -#define R_TEST_MODE__baudrate__BITNR 5 -#define R_TEST_MODE__baudrate__WIDTH 1 -#define R_TEST_MODE__baudrate__on 1 -#define R_TEST_MODE__baudrate__off 0 -#define R_TEST_MODE__timer__BITNR 3 -#define R_TEST_MODE__timer__WIDTH 2 -#define R_TEST_MODE__timer__off 0 -#define R_TEST_MODE__timer__even 1 -#define R_TEST_MODE__timer__odd 2 -#define R_TEST_MODE__timer__all 3 -#define R_TEST_MODE__cache_test__BITNR 2 -#define R_TEST_MODE__cache_test__WIDTH 1 -#define R_TEST_MODE__cache_test__normal 0 -#define R_TEST_MODE__cache_test__test 1 -#define R_TEST_MODE__tag_test__BITNR 1 -#define R_TEST_MODE__tag_test__WIDTH 1 -#define R_TEST_MODE__tag_test__normal 0 -#define R_TEST_MODE__tag_test__test 1 -#define R_TEST_MODE__cache_enable__BITNR 0 -#define R_TEST_MODE__cache_enable__WIDTH 1 -#define R_TEST_MODE__cache_enable__enable 1 -#define R_TEST_MODE__cache_enable__disable 0 - -#define R_SINGLE_STEP (IO_TYPECAST_BYTE 0xb00000fe) -#define R_SINGLE_STEP__single_step__BITNR 3 -#define R_SINGLE_STEP__single_step__WIDTH 1 -#define R_SINGLE_STEP__single_step__on 1 -#define R_SINGLE_STEP__single_step__off 0 -#define R_SINGLE_STEP__step_wr__BITNR 2 -#define R_SINGLE_STEP__step_wr__WIDTH 1 -#define R_SINGLE_STEP__step_wr__on 1 -#define R_SINGLE_STEP__step_wr__off 0 -#define R_SINGLE_STEP__step_rd__BITNR 1 -#define R_SINGLE_STEP__step_rd__WIDTH 1 -#define R_SINGLE_STEP__step_rd__on 1 -#define R_SINGLE_STEP__step_rd__off 0 -#define R_SINGLE_STEP__step_fetch__BITNR 0 -#define R_SINGLE_STEP__step_fetch__WIDTH 1 -#define R_SINGLE_STEP__step_fetch__on 1 -#define R_SINGLE_STEP__step_fetch__off 0 - -/* -!* USB interface control registers -!*/ - -#define R_USB_REVISION (IO_TYPECAST_RO_BYTE 0xb0000200) -#define R_USB_REVISION__major__BITNR 4 -#define R_USB_REVISION__major__WIDTH 4 -#define R_USB_REVISION__minor__BITNR 0 -#define R_USB_REVISION__minor__WIDTH 4 -#define R_USB_REVISION__minor__v1_v2 1 -#define R_USB_REVISION__minor__v3 0 - -#define R_USB_COMMAND (IO_TYPECAST_BYTE 0xb0000201) -#define R_USB_COMMAND__port_sel__BITNR 6 -#define R_USB_COMMAND__port_sel__WIDTH 2 -#define R_USB_COMMAND__port_sel__nop 0 -#define R_USB_COMMAND__port_sel__port1 1 -#define R_USB_COMMAND__port_sel__port2 2 -#define R_USB_COMMAND__port_sel__both 3 -#define R_USB_COMMAND__port_cmd__BITNR 4 -#define R_USB_COMMAND__port_cmd__WIDTH 2 -#define R_USB_COMMAND__port_cmd__reset 0 -#define R_USB_COMMAND__port_cmd__disable 1 -#define R_USB_COMMAND__port_cmd__suspend 2 -#define R_USB_COMMAND__port_cmd__resume 3 -#define R_USB_COMMAND__busy__BITNR 3 -#define R_USB_COMMAND__busy__WIDTH 1 -#define R_USB_COMMAND__busy__no 0 -#define R_USB_COMMAND__busy__yes 1 -#define R_USB_COMMAND__ctrl_cmd__BITNR 0 -#define R_USB_COMMAND__ctrl_cmd__WIDTH 3 -#define R_USB_COMMAND__ctrl_cmd__nop 0 -#define R_USB_COMMAND__ctrl_cmd__reset 1 -#define R_USB_COMMAND__ctrl_cmd__deconfig 2 -#define R_USB_COMMAND__ctrl_cmd__host_config 3 -#define R_USB_COMMAND__ctrl_cmd__dev_config 4 -#define R_USB_COMMAND__ctrl_cmd__host_nop 5 -#define R_USB_COMMAND__ctrl_cmd__host_run 6 -#define R_USB_COMMAND__ctrl_cmd__host_stop 7 - -#define R_USB_COMMAND_DEV (IO_TYPECAST_BYTE 0xb0000201) -#define R_USB_COMMAND_DEV__port_sel__BITNR 6 -#define R_USB_COMMAND_DEV__port_sel__WIDTH 2 -#define R_USB_COMMAND_DEV__port_sel__nop 0 -#define R_USB_COMMAND_DEV__port_sel__dummy1 1 -#define R_USB_COMMAND_DEV__port_sel__dummy2 2 -#define R_USB_COMMAND_DEV__port_sel__any 3 -#define R_USB_COMMAND_DEV__port_cmd__BITNR 4 -#define R_USB_COMMAND_DEV__port_cmd__WIDTH 2 -#define R_USB_COMMAND_DEV__port_cmd__active 0 -#define R_USB_COMMAND_DEV__port_cmd__passive 1 -#define R_USB_COMMAND_DEV__port_cmd__nop 2 -#define R_USB_COMMAND_DEV__port_cmd__wakeup 3 -#define R_USB_COMMAND_DEV__busy__BITNR 3 -#define R_USB_COMMAND_DEV__busy__WIDTH 1 -#define R_USB_COMMAND_DEV__busy__no 0 -#define R_USB_COMMAND_DEV__busy__yes 1 -#define R_USB_COMMAND_DEV__ctrl_cmd__BITNR 0 -#define R_USB_COMMAND_DEV__ctrl_cmd__WIDTH 3 -#define R_USB_COMMAND_DEV__ctrl_cmd__nop 0 -#define R_USB_COMMAND_DEV__ctrl_cmd__dev_nop 1 -#define R_USB_COMMAND_DEV__ctrl_cmd__deconfig 2 -#define R_USB_COMMAND_DEV__ctrl_cmd__host_config 3 -#define R_USB_COMMAND_DEV__ctrl_cmd__dev_config 4 -#define R_USB_COMMAND_DEV__ctrl_cmd__dev_nop2 5 -#define R_USB_COMMAND_DEV__ctrl_cmd__dev_nop3 6 -#define R_USB_COMMAND_DEV__ctrl_cmd__dev_nop4 7 - -#define R_USB_STATUS (IO_TYPECAST_RO_BYTE 0xb0000202) -#define R_USB_STATUS__ourun__BITNR 5 -#define R_USB_STATUS__ourun__WIDTH 1 -#define R_USB_STATUS__ourun__no 0 -#define R_USB_STATUS__ourun__yes 1 -#define R_USB_STATUS__perror__BITNR 4 -#define R_USB_STATUS__perror__WIDTH 1 -#define R_USB_STATUS__perror__no 0 -#define R_USB_STATUS__perror__yes 1 -#define R_USB_STATUS__device_mode__BITNR 3 -#define R_USB_STATUS__device_mode__WIDTH 1 -#define R_USB_STATUS__device_mode__no 0 -#define R_USB_STATUS__device_mode__yes 1 -#define R_USB_STATUS__host_mode__BITNR 2 -#define R_USB_STATUS__host_mode__WIDTH 1 -#define R_USB_STATUS__host_mode__no 0 -#define R_USB_STATUS__host_mode__yes 1 -#define R_USB_STATUS__started__BITNR 1 -#define R_USB_STATUS__started__WIDTH 1 -#define R_USB_STATUS__started__no 0 -#define R_USB_STATUS__started__yes 1 -#define R_USB_STATUS__running__BITNR 0 -#define R_USB_STATUS__running__WIDTH 1 -#define R_USB_STATUS__running__no 0 -#define R_USB_STATUS__running__yes 1 - -#define R_USB_IRQ_MASK_SET (IO_TYPECAST_UWORD 0xb0000204) -#define R_USB_IRQ_MASK_SET__iso_eof__BITNR 13 -#define R_USB_IRQ_MASK_SET__iso_eof__WIDTH 1 -#define R_USB_IRQ_MASK_SET__iso_eof__nop 0 -#define R_USB_IRQ_MASK_SET__iso_eof__set 1 -#define R_USB_IRQ_MASK_SET__intr_eof__BITNR 12 -#define R_USB_IRQ_MASK_SET__intr_eof__WIDTH 1 -#define R_USB_IRQ_MASK_SET__intr_eof__nop 0 -#define R_USB_IRQ_MASK_SET__intr_eof__set 1 -#define R_USB_IRQ_MASK_SET__iso_eot__BITNR 11 -#define R_USB_IRQ_MASK_SET__iso_eot__WIDTH 1 -#define R_USB_IRQ_MASK_SET__iso_eot__nop 0 -#define R_USB_IRQ_MASK_SET__iso_eot__set 1 -#define R_USB_IRQ_MASK_SET__intr_eot__BITNR 10 -#define R_USB_IRQ_MASK_SET__intr_eot__WIDTH 1 -#define R_USB_IRQ_MASK_SET__intr_eot__nop 0 -#define R_USB_IRQ_MASK_SET__intr_eot__set 1 -#define R_USB_IRQ_MASK_SET__ctl_eot__BITNR 9 -#define R_USB_IRQ_MASK_SET__ctl_eot__WIDTH 1 -#define R_USB_IRQ_MASK_SET__ctl_eot__nop 0 -#define R_USB_IRQ_MASK_SET__ctl_eot__set 1 -#define R_USB_IRQ_MASK_SET__bulk_eot__BITNR 8 -#define R_USB_IRQ_MASK_SET__bulk_eot__WIDTH 1 -#define R_USB_IRQ_MASK_SET__bulk_eot__nop 0 -#define R_USB_IRQ_MASK_SET__bulk_eot__set 1 -#define R_USB_IRQ_MASK_SET__epid_attn__BITNR 3 -#define R_USB_IRQ_MASK_SET__epid_attn__WIDTH 1 -#define R_USB_IRQ_MASK_SET__epid_attn__nop 0 -#define R_USB_IRQ_MASK_SET__epid_attn__set 1 -#define R_USB_IRQ_MASK_SET__sof__BITNR 2 -#define R_USB_IRQ_MASK_SET__sof__WIDTH 1 -#define R_USB_IRQ_MASK_SET__sof__nop 0 -#define R_USB_IRQ_MASK_SET__sof__set 1 -#define R_USB_IRQ_MASK_SET__port_status__BITNR 1 -#define R_USB_IRQ_MASK_SET__port_status__WIDTH 1 -#define R_USB_IRQ_MASK_SET__port_status__nop 0 -#define R_USB_IRQ_MASK_SET__port_status__set 1 -#define R_USB_IRQ_MASK_SET__ctl_status__BITNR 0 -#define R_USB_IRQ_MASK_SET__ctl_status__WIDTH 1 -#define R_USB_IRQ_MASK_SET__ctl_status__nop 0 -#define R_USB_IRQ_MASK_SET__ctl_status__set 1 - -#define R_USB_IRQ_MASK_READ (IO_TYPECAST_RO_UWORD 0xb0000204) -#define R_USB_IRQ_MASK_READ__iso_eof__BITNR 13 -#define R_USB_IRQ_MASK_READ__iso_eof__WIDTH 1 -#define R_USB_IRQ_MASK_READ__iso_eof__no_pend 0 -#define R_USB_IRQ_MASK_READ__iso_eof__pend 1 -#define R_USB_IRQ_MASK_READ__intr_eof__BITNR 12 -#define R_USB_IRQ_MASK_READ__intr_eof__WIDTH 1 -#define R_USB_IRQ_MASK_READ__intr_eof__no_pend 0 -#define R_USB_IRQ_MASK_READ__intr_eof__pend 1 -#define R_USB_IRQ_MASK_READ__iso_eot__BITNR 11 -#define R_USB_IRQ_MASK_READ__iso_eot__WIDTH 1 -#define R_USB_IRQ_MASK_READ__iso_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ__iso_eot__pend 1 -#define R_USB_IRQ_MASK_READ__intr_eot__BITNR 10 -#define R_USB_IRQ_MASK_READ__intr_eot__WIDTH 1 -#define R_USB_IRQ_MASK_READ__intr_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ__intr_eot__pend 1 -#define R_USB_IRQ_MASK_READ__ctl_eot__BITNR 9 -#define R_USB_IRQ_MASK_READ__ctl_eot__WIDTH 1 -#define R_USB_IRQ_MASK_READ__ctl_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ__ctl_eot__pend 1 -#define R_USB_IRQ_MASK_READ__bulk_eot__BITNR 8 -#define R_USB_IRQ_MASK_READ__bulk_eot__WIDTH 1 -#define R_USB_IRQ_MASK_READ__bulk_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ__bulk_eot__pend 1 -#define R_USB_IRQ_MASK_READ__epid_attn__BITNR 3 -#define R_USB_IRQ_MASK_READ__epid_attn__WIDTH 1 -#define R_USB_IRQ_MASK_READ__epid_attn__no_pend 0 -#define R_USB_IRQ_MASK_READ__epid_attn__pend 1 -#define R_USB_IRQ_MASK_READ__sof__BITNR 2 -#define R_USB_IRQ_MASK_READ__sof__WIDTH 1 -#define R_USB_IRQ_MASK_READ__sof__no_pend 0 -#define R_USB_IRQ_MASK_READ__sof__pend 1 -#define R_USB_IRQ_MASK_READ__port_status__BITNR 1 -#define R_USB_IRQ_MASK_READ__port_status__WIDTH 1 -#define R_USB_IRQ_MASK_READ__port_status__no_pend 0 -#define R_USB_IRQ_MASK_READ__port_status__pend 1 -#define R_USB_IRQ_MASK_READ__ctl_status__BITNR 0 -#define R_USB_IRQ_MASK_READ__ctl_status__WIDTH 1 -#define R_USB_IRQ_MASK_READ__ctl_status__no_pend 0 -#define R_USB_IRQ_MASK_READ__ctl_status__pend 1 - -#define R_USB_IRQ_MASK_CLR (IO_TYPECAST_UWORD 0xb0000206) -#define R_USB_IRQ_MASK_CLR__iso_eof__BITNR 13 -#define R_USB_IRQ_MASK_CLR__iso_eof__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__iso_eof__nop 0 -#define R_USB_IRQ_MASK_CLR__iso_eof__clr 1 -#define R_USB_IRQ_MASK_CLR__intr_eof__BITNR 12 -#define R_USB_IRQ_MASK_CLR__intr_eof__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__intr_eof__nop 0 -#define R_USB_IRQ_MASK_CLR__intr_eof__clr 1 -#define R_USB_IRQ_MASK_CLR__iso_eot__BITNR 11 -#define R_USB_IRQ_MASK_CLR__iso_eot__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__iso_eot__nop 0 -#define R_USB_IRQ_MASK_CLR__iso_eot__clr 1 -#define R_USB_IRQ_MASK_CLR__intr_eot__BITNR 10 -#define R_USB_IRQ_MASK_CLR__intr_eot__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__intr_eot__nop 0 -#define R_USB_IRQ_MASK_CLR__intr_eot__clr 1 -#define R_USB_IRQ_MASK_CLR__ctl_eot__BITNR 9 -#define R_USB_IRQ_MASK_CLR__ctl_eot__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__ctl_eot__nop 0 -#define R_USB_IRQ_MASK_CLR__ctl_eot__clr 1 -#define R_USB_IRQ_MASK_CLR__bulk_eot__BITNR 8 -#define R_USB_IRQ_MASK_CLR__bulk_eot__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__bulk_eot__nop 0 -#define R_USB_IRQ_MASK_CLR__bulk_eot__clr 1 -#define R_USB_IRQ_MASK_CLR__epid_attn__BITNR 3 -#define R_USB_IRQ_MASK_CLR__epid_attn__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__epid_attn__nop 0 -#define R_USB_IRQ_MASK_CLR__epid_attn__clr 1 -#define R_USB_IRQ_MASK_CLR__sof__BITNR 2 -#define R_USB_IRQ_MASK_CLR__sof__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__sof__nop 0 -#define R_USB_IRQ_MASK_CLR__sof__clr 1 -#define R_USB_IRQ_MASK_CLR__port_status__BITNR 1 -#define R_USB_IRQ_MASK_CLR__port_status__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__port_status__nop 0 -#define R_USB_IRQ_MASK_CLR__port_status__clr 1 -#define R_USB_IRQ_MASK_CLR__ctl_status__BITNR 0 -#define R_USB_IRQ_MASK_CLR__ctl_status__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__ctl_status__nop 0 -#define R_USB_IRQ_MASK_CLR__ctl_status__clr 1 - -#define R_USB_IRQ_READ (IO_TYPECAST_RO_UWORD 0xb0000206) -#define R_USB_IRQ_READ__iso_eof__BITNR 13 -#define R_USB_IRQ_READ__iso_eof__WIDTH 1 -#define R_USB_IRQ_READ__iso_eof__no_pend 0 -#define R_USB_IRQ_READ__iso_eof__pend 1 -#define R_USB_IRQ_READ__intr_eof__BITNR 12 -#define R_USB_IRQ_READ__intr_eof__WIDTH 1 -#define R_USB_IRQ_READ__intr_eof__no_pend 0 -#define R_USB_IRQ_READ__intr_eof__pend 1 -#define R_USB_IRQ_READ__iso_eot__BITNR 11 -#define R_USB_IRQ_READ__iso_eot__WIDTH 1 -#define R_USB_IRQ_READ__iso_eot__no_pend 0 -#define R_USB_IRQ_READ__iso_eot__pend 1 -#define R_USB_IRQ_READ__intr_eot__BITNR 10 -#define R_USB_IRQ_READ__intr_eot__WIDTH 1 -#define R_USB_IRQ_READ__intr_eot__no_pend 0 -#define R_USB_IRQ_READ__intr_eot__pend 1 -#define R_USB_IRQ_READ__ctl_eot__BITNR 9 -#define R_USB_IRQ_READ__ctl_eot__WIDTH 1 -#define R_USB_IRQ_READ__ctl_eot__no_pend 0 -#define R_USB_IRQ_READ__ctl_eot__pend 1 -#define R_USB_IRQ_READ__bulk_eot__BITNR 8 -#define R_USB_IRQ_READ__bulk_eot__WIDTH 1 -#define R_USB_IRQ_READ__bulk_eot__no_pend 0 -#define R_USB_IRQ_READ__bulk_eot__pend 1 -#define R_USB_IRQ_READ__epid_attn__BITNR 3 -#define R_USB_IRQ_READ__epid_attn__WIDTH 1 -#define R_USB_IRQ_READ__epid_attn__no_pend 0 -#define R_USB_IRQ_READ__epid_attn__pend 1 -#define R_USB_IRQ_READ__sof__BITNR 2 -#define R_USB_IRQ_READ__sof__WIDTH 1 -#define R_USB_IRQ_READ__sof__no_pend 0 -#define R_USB_IRQ_READ__sof__pend 1 -#define R_USB_IRQ_READ__port_status__BITNR 1 -#define R_USB_IRQ_READ__port_status__WIDTH 1 -#define R_USB_IRQ_READ__port_status__no_pend 0 -#define R_USB_IRQ_READ__port_status__pend 1 -#define R_USB_IRQ_READ__ctl_status__BITNR 0 -#define R_USB_IRQ_READ__ctl_status__WIDTH 1 -#define R_USB_IRQ_READ__ctl_status__no_pend 0 -#define R_USB_IRQ_READ__ctl_status__pend 1 - -#define R_USB_IRQ_MASK_SET_DEV (IO_TYPECAST_UWORD 0xb0000204) -#define R_USB_IRQ_MASK_SET_DEV__out_eot__BITNR 12 -#define R_USB_IRQ_MASK_SET_DEV__out_eot__WIDTH 1 -#define R_USB_IRQ_MASK_SET_DEV__out_eot__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__out_eot__set 1 -#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__BITNR 11 -#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__set 1 -#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__BITNR 10 -#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__set 1 -#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__BITNR 9 -#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__set 1 -#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__BITNR 8 -#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__set 1 -#define R_USB_IRQ_MASK_SET_DEV__epid_attn__BITNR 3 -#define R_USB_IRQ_MASK_SET_DEV__epid_attn__WIDTH 1 -#define R_USB_IRQ_MASK_SET_DEV__epid_attn__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__epid_attn__set 1 -#define R_USB_IRQ_MASK_SET_DEV__sof__BITNR 2 -#define R_USB_IRQ_MASK_SET_DEV__sof__WIDTH 1 -#define R_USB_IRQ_MASK_SET_DEV__sof__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__sof__set 1 -#define R_USB_IRQ_MASK_SET_DEV__port_status__BITNR 1 -#define R_USB_IRQ_MASK_SET_DEV__port_status__WIDTH 1 -#define R_USB_IRQ_MASK_SET_DEV__port_status__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__port_status__set 1 -#define R_USB_IRQ_MASK_SET_DEV__ctl_status__BITNR 0 -#define R_USB_IRQ_MASK_SET_DEV__ctl_status__WIDTH 1 -#define R_USB_IRQ_MASK_SET_DEV__ctl_status__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__ctl_status__set 1 - -#define R_USB_IRQ_MASK_READ_DEV (IO_TYPECAST_RO_UWORD 0xb0000204) -#define R_USB_IRQ_MASK_READ_DEV__out_eot__BITNR 12 -#define R_USB_IRQ_MASK_READ_DEV__out_eot__WIDTH 1 -#define R_USB_IRQ_MASK_READ_DEV__out_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__out_eot__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__BITNR 11 -#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__BITNR 10 -#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__BITNR 9 -#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__BITNR 8 -#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__epid_attn__BITNR 3 -#define R_USB_IRQ_MASK_READ_DEV__epid_attn__WIDTH 1 -#define R_USB_IRQ_MASK_READ_DEV__epid_attn__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__epid_attn__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__sof__BITNR 2 -#define R_USB_IRQ_MASK_READ_DEV__sof__WIDTH 1 -#define R_USB_IRQ_MASK_READ_DEV__sof__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__sof__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__port_status__BITNR 1 -#define R_USB_IRQ_MASK_READ_DEV__port_status__WIDTH 1 -#define R_USB_IRQ_MASK_READ_DEV__port_status__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__port_status__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__ctl_status__BITNR 0 -#define R_USB_IRQ_MASK_READ_DEV__ctl_status__WIDTH 1 -#define R_USB_IRQ_MASK_READ_DEV__ctl_status__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__ctl_status__pend 1 - -#define R_USB_IRQ_MASK_CLR_DEV (IO_TYPECAST_UWORD 0xb0000206) -#define R_USB_IRQ_MASK_CLR_DEV__out_eot__BITNR 12 -#define R_USB_IRQ_MASK_CLR_DEV__out_eot__WIDTH 1 -#define R_USB_IRQ_MASK_CLR_DEV__out_eot__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__out_eot__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__BITNR 11 -#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__BITNR 10 -#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__BITNR 9 -#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__BITNR 8 -#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__BITNR 3 -#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__WIDTH 1 -#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__sof__BITNR 2 -#define R_USB_IRQ_MASK_CLR_DEV__sof__WIDTH 1 -#define R_USB_IRQ_MASK_CLR_DEV__sof__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__sof__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__port_status__BITNR 1 -#define R_USB_IRQ_MASK_CLR_DEV__port_status__WIDTH 1 -#define R_USB_IRQ_MASK_CLR_DEV__port_status__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__port_status__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__BITNR 0 -#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__WIDTH 1 -#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__clr 1 - -#define R_USB_IRQ_READ_DEV (IO_TYPECAST_RO_UWORD 0xb0000206) -#define R_USB_IRQ_READ_DEV__out_eot__BITNR 12 -#define R_USB_IRQ_READ_DEV__out_eot__WIDTH 1 -#define R_USB_IRQ_READ_DEV__out_eot__no_pend 0 -#define R_USB_IRQ_READ_DEV__out_eot__pend 1 -#define R_USB_IRQ_READ_DEV__ep3_in_eot__BITNR 11 -#define R_USB_IRQ_READ_DEV__ep3_in_eot__WIDTH 1 -#define R_USB_IRQ_READ_DEV__ep3_in_eot__no_pend 0 -#define R_USB_IRQ_READ_DEV__ep3_in_eot__pend 1 -#define R_USB_IRQ_READ_DEV__ep2_in_eot__BITNR 10 -#define R_USB_IRQ_READ_DEV__ep2_in_eot__WIDTH 1 -#define R_USB_IRQ_READ_DEV__ep2_in_eot__no_pend 0 -#define R_USB_IRQ_READ_DEV__ep2_in_eot__pend 1 -#define R_USB_IRQ_READ_DEV__ep1_in_eot__BITNR 9 -#define R_USB_IRQ_READ_DEV__ep1_in_eot__WIDTH 1 -#define R_USB_IRQ_READ_DEV__ep1_in_eot__no_pend 0 -#define R_USB_IRQ_READ_DEV__ep1_in_eot__pend 1 -#define R_USB_IRQ_READ_DEV__ep0_in_eot__BITNR 8 -#define R_USB_IRQ_READ_DEV__ep0_in_eot__WIDTH 1 -#define R_USB_IRQ_READ_DEV__ep0_in_eot__no_pend 0 -#define R_USB_IRQ_READ_DEV__ep0_in_eot__pend 1 -#define R_USB_IRQ_READ_DEV__epid_attn__BITNR 3 -#define R_USB_IRQ_READ_DEV__epid_attn__WIDTH 1 -#define R_USB_IRQ_READ_DEV__epid_attn__no_pend 0 -#define R_USB_IRQ_READ_DEV__epid_attn__pend 1 -#define R_USB_IRQ_READ_DEV__sof__BITNR 2 -#define R_USB_IRQ_READ_DEV__sof__WIDTH 1 -#define R_USB_IRQ_READ_DEV__sof__no_pend 0 -#define R_USB_IRQ_READ_DEV__sof__pend 1 -#define R_USB_IRQ_READ_DEV__port_status__BITNR 1 -#define R_USB_IRQ_READ_DEV__port_status__WIDTH 1 -#define R_USB_IRQ_READ_DEV__port_status__no_pend 0 -#define R_USB_IRQ_READ_DEV__port_status__pend 1 -#define R_USB_IRQ_READ_DEV__ctl_status__BITNR 0 -#define R_USB_IRQ_READ_DEV__ctl_status__WIDTH 1 -#define R_USB_IRQ_READ_DEV__ctl_status__no_pend 0 -#define R_USB_IRQ_READ_DEV__ctl_status__pend 1 - -#define R_USB_FM_NUMBER (IO_TYPECAST_UDWORD 0xb000020c) -#define R_USB_FM_NUMBER__value__BITNR 0 -#define R_USB_FM_NUMBER__value__WIDTH 32 - -#define R_USB_FM_NUMBER_DEV (IO_TYPECAST_UDWORD 0xb000020c) -#define R_USB_FM_NUMBER_DEV__sign__BITNR 31 -#define R_USB_FM_NUMBER_DEV__sign__WIDTH 1 -#define R_USB_FM_NUMBER_DEV__sign__early 0 -#define R_USB_FM_NUMBER_DEV__sign__late 1 -#define R_USB_FM_NUMBER_DEV__deviation__BITNR 24 -#define R_USB_FM_NUMBER_DEV__deviation__WIDTH 7 -#define R_USB_FM_NUMBER_DEV__fm_number__BITNR 0 -#define R_USB_FM_NUMBER_DEV__fm_number__WIDTH 11 - -#define R_USB_FM_INTERVAL (IO_TYPECAST_UWORD 0xb0000210) -#define R_USB_FM_INTERVAL__fixed__BITNR 6 -#define R_USB_FM_INTERVAL__fixed__WIDTH 8 -#define R_USB_FM_INTERVAL__adj__BITNR 0 -#define R_USB_FM_INTERVAL__adj__WIDTH 6 - -#define R_USB_FM_REMAINING (IO_TYPECAST_RO_UWORD 0xb0000212) -#define R_USB_FM_REMAINING__value__BITNR 0 -#define R_USB_FM_REMAINING__value__WIDTH 14 - -#define R_USB_FM_PSTART (IO_TYPECAST_UWORD 0xb0000214) -#define R_USB_FM_PSTART__value__BITNR 0 -#define R_USB_FM_PSTART__value__WIDTH 14 - -#define R_USB_RH_STATUS (IO_TYPECAST_RO_BYTE 0xb0000203) -#define R_USB_RH_STATUS__babble2__BITNR 7 -#define R_USB_RH_STATUS__babble2__WIDTH 1 -#define R_USB_RH_STATUS__babble2__no 0 -#define R_USB_RH_STATUS__babble2__yes 1 -#define R_USB_RH_STATUS__babble1__BITNR 6 -#define R_USB_RH_STATUS__babble1__WIDTH 1 -#define R_USB_RH_STATUS__babble1__no 0 -#define R_USB_RH_STATUS__babble1__yes 1 -#define R_USB_RH_STATUS__bus1__BITNR 4 -#define R_USB_RH_STATUS__bus1__WIDTH 2 -#define R_USB_RH_STATUS__bus1__SE0 0 -#define R_USB_RH_STATUS__bus1__Diff0 1 -#define R_USB_RH_STATUS__bus1__Diff1 2 -#define R_USB_RH_STATUS__bus1__SE1 3 -#define R_USB_RH_STATUS__bus2__BITNR 2 -#define R_USB_RH_STATUS__bus2__WIDTH 2 -#define R_USB_RH_STATUS__bus2__SE0 0 -#define R_USB_RH_STATUS__bus2__Diff0 1 -#define R_USB_RH_STATUS__bus2__Diff1 2 -#define R_USB_RH_STATUS__bus2__SE1 3 -#define R_USB_RH_STATUS__nports__BITNR 0 -#define R_USB_RH_STATUS__nports__WIDTH 2 - -#define R_USB_RH_PORT_STATUS_1 (IO_TYPECAST_RO_UWORD 0xb0000218) -#define R_USB_RH_PORT_STATUS_1__speed__BITNR 9 -#define R_USB_RH_PORT_STATUS_1__speed__WIDTH 1 -#define R_USB_RH_PORT_STATUS_1__speed__full 0 -#define R_USB_RH_PORT_STATUS_1__speed__low 1 -#define R_USB_RH_PORT_STATUS_1__power__BITNR 8 -#define R_USB_RH_PORT_STATUS_1__power__WIDTH 1 -#define R_USB_RH_PORT_STATUS_1__reset__BITNR 4 -#define R_USB_RH_PORT_STATUS_1__reset__WIDTH 1 -#define R_USB_RH_PORT_STATUS_1__reset__no 0 -#define R_USB_RH_PORT_STATUS_1__reset__yes 1 -#define R_USB_RH_PORT_STATUS_1__overcurrent__BITNR 3 -#define R_USB_RH_PORT_STATUS_1__overcurrent__WIDTH 1 -#define R_USB_RH_PORT_STATUS_1__overcurrent__no 0 -#define R_USB_RH_PORT_STATUS_1__overcurrent__yes 1 -#define R_USB_RH_PORT_STATUS_1__suspended__BITNR 2 -#define R_USB_RH_PORT_STATUS_1__suspended__WIDTH 1 -#define R_USB_RH_PORT_STATUS_1__suspended__no 0 -#define R_USB_RH_PORT_STATUS_1__suspended__yes 1 -#define R_USB_RH_PORT_STATUS_1__enabled__BITNR 1 -#define R_USB_RH_PORT_STATUS_1__enabled__WIDTH 1 -#define R_USB_RH_PORT_STATUS_1__enabled__no 0 -#define R_USB_RH_PORT_STATUS_1__enabled__yes 1 -#define R_USB_RH_PORT_STATUS_1__connected__BITNR 0 -#define R_USB_RH_PORT_STATUS_1__connected__WIDTH 1 -#define R_USB_RH_PORT_STATUS_1__connected__no 0 -#define R_USB_RH_PORT_STATUS_1__connected__yes 1 - -#define R_USB_RH_PORT_STATUS_2 (IO_TYPECAST_RO_UWORD 0xb000021a) -#define R_USB_RH_PORT_STATUS_2__speed__BITNR 9 -#define R_USB_RH_PORT_STATUS_2__speed__WIDTH 1 -#define R_USB_RH_PORT_STATUS_2__speed__full 0 -#define R_USB_RH_PORT_STATUS_2__speed__low 1 -#define R_USB_RH_PORT_STATUS_2__power__BITNR 8 -#define R_USB_RH_PORT_STATUS_2__power__WIDTH 1 -#define R_USB_RH_PORT_STATUS_2__reset__BITNR 4 -#define R_USB_RH_PORT_STATUS_2__reset__WIDTH 1 -#define R_USB_RH_PORT_STATUS_2__reset__no 0 -#define R_USB_RH_PORT_STATUS_2__reset__yes 1 -#define R_USB_RH_PORT_STATUS_2__overcurrent__BITNR 3 -#define R_USB_RH_PORT_STATUS_2__overcurrent__WIDTH 1 -#define R_USB_RH_PORT_STATUS_2__overcurrent__no 0 -#define R_USB_RH_PORT_STATUS_2__overcurrent__yes 1 -#define R_USB_RH_PORT_STATUS_2__suspended__BITNR 2 -#define R_USB_RH_PORT_STATUS_2__suspended__WIDTH 1 -#define R_USB_RH_PORT_STATUS_2__suspended__no 0 -#define R_USB_RH_PORT_STATUS_2__suspended__yes 1 -#define R_USB_RH_PORT_STATUS_2__enabled__BITNR 1 -#define R_USB_RH_PORT_STATUS_2__enabled__WIDTH 1 -#define R_USB_RH_PORT_STATUS_2__enabled__no 0 -#define R_USB_RH_PORT_STATUS_2__enabled__yes 1 -#define R_USB_RH_PORT_STATUS_2__connected__BITNR 0 -#define R_USB_RH_PORT_STATUS_2__connected__WIDTH 1 -#define R_USB_RH_PORT_STATUS_2__connected__no 0 -#define R_USB_RH_PORT_STATUS_2__connected__yes 1 - -#define R_USB_EPT_INDEX (IO_TYPECAST_BYTE 0xb0000208) -#define R_USB_EPT_INDEX__value__BITNR 0 -#define R_USB_EPT_INDEX__value__WIDTH 5 - -#define R_USB_EPT_DATA (IO_TYPECAST_UDWORD 0xb000021c) -#define R_USB_EPT_DATA__valid__BITNR 31 -#define R_USB_EPT_DATA__valid__WIDTH 1 -#define R_USB_EPT_DATA__valid__no 0 -#define R_USB_EPT_DATA__valid__yes 1 -#define R_USB_EPT_DATA__hold__BITNR 30 -#define R_USB_EPT_DATA__hold__WIDTH 1 -#define R_USB_EPT_DATA__hold__no 0 -#define R_USB_EPT_DATA__hold__yes 1 -#define R_USB_EPT_DATA__error_count_in__BITNR 28 -#define R_USB_EPT_DATA__error_count_in__WIDTH 2 -#define R_USB_EPT_DATA__t_in__BITNR 27 -#define R_USB_EPT_DATA__t_in__WIDTH 1 -#define R_USB_EPT_DATA__low_speed__BITNR 26 -#define R_USB_EPT_DATA__low_speed__WIDTH 1 -#define R_USB_EPT_DATA__low_speed__no 0 -#define R_USB_EPT_DATA__low_speed__yes 1 -#define R_USB_EPT_DATA__port__BITNR 24 -#define R_USB_EPT_DATA__port__WIDTH 2 -#define R_USB_EPT_DATA__port__any 0 -#define R_USB_EPT_DATA__port__p1 1 -#define R_USB_EPT_DATA__port__p2 2 -#define R_USB_EPT_DATA__port__undef 3 -#define R_USB_EPT_DATA__error_code__BITNR 22 -#define R_USB_EPT_DATA__error_code__WIDTH 2 -#define R_USB_EPT_DATA__error_code__no_error 0 -#define R_USB_EPT_DATA__error_code__stall 1 -#define R_USB_EPT_DATA__error_code__bus_error 2 -#define R_USB_EPT_DATA__error_code__buffer_error 3 -#define R_USB_EPT_DATA__t_out__BITNR 21 -#define R_USB_EPT_DATA__t_out__WIDTH 1 -#define R_USB_EPT_DATA__error_count_out__BITNR 19 -#define R_USB_EPT_DATA__error_count_out__WIDTH 2 -#define R_USB_EPT_DATA__max_len__BITNR 11 -#define R_USB_EPT_DATA__max_len__WIDTH 7 -#define R_USB_EPT_DATA__ep__BITNR 7 -#define R_USB_EPT_DATA__ep__WIDTH 4 -#define R_USB_EPT_DATA__dev__BITNR 0 -#define R_USB_EPT_DATA__dev__WIDTH 7 - -#define R_USB_EPT_DATA_ISO (IO_TYPECAST_UDWORD 0xb000021c) -#define R_USB_EPT_DATA_ISO__valid__BITNR 31 -#define R_USB_EPT_DATA_ISO__valid__WIDTH 1 -#define R_USB_EPT_DATA_ISO__valid__no 0 -#define R_USB_EPT_DATA_ISO__valid__yes 1 -#define R_USB_EPT_DATA_ISO__port__BITNR 24 -#define R_USB_EPT_DATA_ISO__port__WIDTH 2 -#define R_USB_EPT_DATA_ISO__port__any 0 -#define R_USB_EPT_DATA_ISO__port__p1 1 -#define R_USB_EPT_DATA_ISO__port__p2 2 -#define R_USB_EPT_DATA_ISO__port__undef 3 -#define R_USB_EPT_DATA_ISO__error_code__BITNR 22 -#define R_USB_EPT_DATA_ISO__error_code__WIDTH 2 -#define R_USB_EPT_DATA_ISO__error_code__no_error 0 -#define R_USB_EPT_DATA_ISO__error_code__stall 1 -#define R_USB_EPT_DATA_ISO__error_code__bus_error 2 -#define R_USB_EPT_DATA_ISO__error_code__TBD3 3 -#define R_USB_EPT_DATA_ISO__max_len__BITNR 11 -#define R_USB_EPT_DATA_ISO__max_len__WIDTH 10 -#define R_USB_EPT_DATA_ISO__ep__BITNR 7 -#define R_USB_EPT_DATA_ISO__ep__WIDTH 4 -#define R_USB_EPT_DATA_ISO__dev__BITNR 0 -#define R_USB_EPT_DATA_ISO__dev__WIDTH 7 - -#define R_USB_EPT_DATA_DEV (IO_TYPECAST_UDWORD 0xb000021c) -#define R_USB_EPT_DATA_DEV__valid__BITNR 31 -#define R_USB_EPT_DATA_DEV__valid__WIDTH 1 -#define R_USB_EPT_DATA_DEV__valid__no 0 -#define R_USB_EPT_DATA_DEV__valid__yes 1 -#define R_USB_EPT_DATA_DEV__hold__BITNR 30 -#define R_USB_EPT_DATA_DEV__hold__WIDTH 1 -#define R_USB_EPT_DATA_DEV__hold__no 0 -#define R_USB_EPT_DATA_DEV__hold__yes 1 -#define R_USB_EPT_DATA_DEV__stall__BITNR 29 -#define R_USB_EPT_DATA_DEV__stall__WIDTH 1 -#define R_USB_EPT_DATA_DEV__stall__no 0 -#define R_USB_EPT_DATA_DEV__stall__yes 1 -#define R_USB_EPT_DATA_DEV__iso_resp__BITNR 28 -#define R_USB_EPT_DATA_DEV__iso_resp__WIDTH 1 -#define R_USB_EPT_DATA_DEV__iso_resp__quiet 0 -#define R_USB_EPT_DATA_DEV__iso_resp__yes 1 -#define R_USB_EPT_DATA_DEV__ctrl__BITNR 27 -#define R_USB_EPT_DATA_DEV__ctrl__WIDTH 1 -#define R_USB_EPT_DATA_DEV__ctrl__no 0 -#define R_USB_EPT_DATA_DEV__ctrl__yes 1 -#define R_USB_EPT_DATA_DEV__iso__BITNR 26 -#define R_USB_EPT_DATA_DEV__iso__WIDTH 1 -#define R_USB_EPT_DATA_DEV__iso__no 0 -#define R_USB_EPT_DATA_DEV__iso__yes 1 -#define R_USB_EPT_DATA_DEV__port__BITNR 24 -#define R_USB_EPT_DATA_DEV__port__WIDTH 2 -#define R_USB_EPT_DATA_DEV__control_phase__BITNR 22 -#define R_USB_EPT_DATA_DEV__control_phase__WIDTH 1 -#define R_USB_EPT_DATA_DEV__t__BITNR 21 -#define R_USB_EPT_DATA_DEV__t__WIDTH 1 -#define R_USB_EPT_DATA_DEV__max_len__BITNR 11 -#define R_USB_EPT_DATA_DEV__max_len__WIDTH 10 -#define R_USB_EPT_DATA_DEV__ep__BITNR 7 -#define R_USB_EPT_DATA_DEV__ep__WIDTH 4 -#define R_USB_EPT_DATA_DEV__dev__BITNR 0 -#define R_USB_EPT_DATA_DEV__dev__WIDTH 7 - -#define R_USB_SNMP_TERROR (IO_TYPECAST_UDWORD 0xb0000220) -#define R_USB_SNMP_TERROR__value__BITNR 0 -#define R_USB_SNMP_TERROR__value__WIDTH 32 - -#define R_USB_EPID_ATTN (IO_TYPECAST_RO_UDWORD 0xb0000224) -#define R_USB_EPID_ATTN__value__BITNR 0 -#define R_USB_EPID_ATTN__value__WIDTH 32 - -#define R_USB_PORT1_DISABLE (IO_TYPECAST_BYTE 0xb000006a) -#define R_USB_PORT1_DISABLE__disable__BITNR 0 -#define R_USB_PORT1_DISABLE__disable__WIDTH 1 -#define R_USB_PORT1_DISABLE__disable__yes 0 -#define R_USB_PORT1_DISABLE__disable__no 1 - -#define R_USB_PORT2_DISABLE (IO_TYPECAST_BYTE 0xb0000052) -#define R_USB_PORT2_DISABLE__disable__BITNR 0 -#define R_USB_PORT2_DISABLE__disable__WIDTH 1 -#define R_USB_PORT2_DISABLE__disable__yes 0 -#define R_USB_PORT2_DISABLE__disable__no 1 - -/* -!* MMU registers -!*/ - -#define R_MMU_CONFIG (IO_TYPECAST_UDWORD 0xb0000240) -#define R_MMU_CONFIG__mmu_enable__BITNR 31 -#define R_MMU_CONFIG__mmu_enable__WIDTH 1 -#define R_MMU_CONFIG__mmu_enable__enable 1 -#define R_MMU_CONFIG__mmu_enable__disable 0 -#define R_MMU_CONFIG__inv_excp__BITNR 18 -#define R_MMU_CONFIG__inv_excp__WIDTH 1 -#define R_MMU_CONFIG__inv_excp__enable 1 -#define R_MMU_CONFIG__inv_excp__disable 0 -#define R_MMU_CONFIG__acc_excp__BITNR 17 -#define R_MMU_CONFIG__acc_excp__WIDTH 1 -#define R_MMU_CONFIG__acc_excp__enable 1 -#define R_MMU_CONFIG__acc_excp__disable 0 -#define R_MMU_CONFIG__we_excp__BITNR 16 -#define R_MMU_CONFIG__we_excp__WIDTH 1 -#define R_MMU_CONFIG__we_excp__enable 1 -#define R_MMU_CONFIG__we_excp__disable 0 -#define R_MMU_CONFIG__seg_f__BITNR 15 -#define R_MMU_CONFIG__seg_f__WIDTH 1 -#define R_MMU_CONFIG__seg_f__seg 1 -#define R_MMU_CONFIG__seg_f__page 0 -#define R_MMU_CONFIG__seg_e__BITNR 14 -#define R_MMU_CONFIG__seg_e__WIDTH 1 -#define R_MMU_CONFIG__seg_e__seg 1 -#define R_MMU_CONFIG__seg_e__page 0 -#define R_MMU_CONFIG__seg_d__BITNR 13 -#define R_MMU_CONFIG__seg_d__WIDTH 1 -#define R_MMU_CONFIG__seg_d__seg 1 -#define R_MMU_CONFIG__seg_d__page 0 -#define R_MMU_CONFIG__seg_c__BITNR 12 -#define R_MMU_CONFIG__seg_c__WIDTH 1 -#define R_MMU_CONFIG__seg_c__seg 1 -#define R_MMU_CONFIG__seg_c__page 0 -#define R_MMU_CONFIG__seg_b__BITNR 11 -#define R_MMU_CONFIG__seg_b__WIDTH 1 -#define R_MMU_CONFIG__seg_b__seg 1 -#define R_MMU_CONFIG__seg_b__page 0 -#define R_MMU_CONFIG__seg_a__BITNR 10 -#define R_MMU_CONFIG__seg_a__WIDTH 1 -#define R_MMU_CONFIG__seg_a__seg 1 -#define R_MMU_CONFIG__seg_a__page 0 -#define R_MMU_CONFIG__seg_9__BITNR 9 -#define R_MMU_CONFIG__seg_9__WIDTH 1 -#define R_MMU_CONFIG__seg_9__seg 1 -#define R_MMU_CONFIG__seg_9__page 0 -#define R_MMU_CONFIG__seg_8__BITNR 8 -#define R_MMU_CONFIG__seg_8__WIDTH 1 -#define R_MMU_CONFIG__seg_8__seg 1 -#define R_MMU_CONFIG__seg_8__page 0 -#define R_MMU_CONFIG__seg_7__BITNR 7 -#define R_MMU_CONFIG__seg_7__WIDTH 1 -#define R_MMU_CONFIG__seg_7__seg 1 -#define R_MMU_CONFIG__seg_7__page 0 -#define R_MMU_CONFIG__seg_6__BITNR 6 -#define R_MMU_CONFIG__seg_6__WIDTH 1 -#define R_MMU_CONFIG__seg_6__seg 1 -#define R_MMU_CONFIG__seg_6__page 0 -#define R_MMU_CONFIG__seg_5__BITNR 5 -#define R_MMU_CONFIG__seg_5__WIDTH 1 -#define R_MMU_CONFIG__seg_5__seg 1 -#define R_MMU_CONFIG__seg_5__page 0 -#define R_MMU_CONFIG__seg_4__BITNR 4 -#define R_MMU_CONFIG__seg_4__WIDTH 1 -#define R_MMU_CONFIG__seg_4__seg 1 -#define R_MMU_CONFIG__seg_4__page 0 -#define R_MMU_CONFIG__seg_3__BITNR 3 -#define R_MMU_CONFIG__seg_3__WIDTH 1 -#define R_MMU_CONFIG__seg_3__seg 1 -#define R_MMU_CONFIG__seg_3__page 0 -#define R_MMU_CONFIG__seg_2__BITNR 2 -#define R_MMU_CONFIG__seg_2__WIDTH 1 -#define R_MMU_CONFIG__seg_2__seg 1 -#define R_MMU_CONFIG__seg_2__page 0 -#define R_MMU_CONFIG__seg_1__BITNR 1 -#define R_MMU_CONFIG__seg_1__WIDTH 1 -#define R_MMU_CONFIG__seg_1__seg 1 -#define R_MMU_CONFIG__seg_1__page 0 -#define R_MMU_CONFIG__seg_0__BITNR 0 -#define R_MMU_CONFIG__seg_0__WIDTH 1 -#define R_MMU_CONFIG__seg_0__seg 1 -#define R_MMU_CONFIG__seg_0__page 0 - -#define R_MMU_KSEG (IO_TYPECAST_UWORD 0xb0000240) -#define R_MMU_KSEG__seg_f__BITNR 15 -#define R_MMU_KSEG__seg_f__WIDTH 1 -#define R_MMU_KSEG__seg_f__seg 1 -#define R_MMU_KSEG__seg_f__page 0 -#define R_MMU_KSEG__seg_e__BITNR 14 -#define R_MMU_KSEG__seg_e__WIDTH 1 -#define R_MMU_KSEG__seg_e__seg 1 -#define R_MMU_KSEG__seg_e__page 0 -#define R_MMU_KSEG__seg_d__BITNR 13 -#define R_MMU_KSEG__seg_d__WIDTH 1 -#define R_MMU_KSEG__seg_d__seg 1 -#define R_MMU_KSEG__seg_d__page 0 -#define R_MMU_KSEG__seg_c__BITNR 12 -#define R_MMU_KSEG__seg_c__WIDTH 1 -#define R_MMU_KSEG__seg_c__seg 1 -#define R_MMU_KSEG__seg_c__page 0 -#define R_MMU_KSEG__seg_b__BITNR 11 -#define R_MMU_KSEG__seg_b__WIDTH 1 -#define R_MMU_KSEG__seg_b__seg 1 -#define R_MMU_KSEG__seg_b__page 0 -#define R_MMU_KSEG__seg_a__BITNR 10 -#define R_MMU_KSEG__seg_a__WIDTH 1 -#define R_MMU_KSEG__seg_a__seg 1 -#define R_MMU_KSEG__seg_a__page 0 -#define R_MMU_KSEG__seg_9__BITNR 9 -#define R_MMU_KSEG__seg_9__WIDTH 1 -#define R_MMU_KSEG__seg_9__seg 1 -#define R_MMU_KSEG__seg_9__page 0 -#define R_MMU_KSEG__seg_8__BITNR 8 -#define R_MMU_KSEG__seg_8__WIDTH 1 -#define R_MMU_KSEG__seg_8__seg 1 -#define R_MMU_KSEG__seg_8__page 0 -#define R_MMU_KSEG__seg_7__BITNR 7 -#define R_MMU_KSEG__seg_7__WIDTH 1 -#define R_MMU_KSEG__seg_7__seg 1 -#define R_MMU_KSEG__seg_7__page 0 -#define R_MMU_KSEG__seg_6__BITNR 6 -#define R_MMU_KSEG__seg_6__WIDTH 1 -#define R_MMU_KSEG__seg_6__seg 1 -#define R_MMU_KSEG__seg_6__page 0 -#define R_MMU_KSEG__seg_5__BITNR 5 -#define R_MMU_KSEG__seg_5__WIDTH 1 -#define R_MMU_KSEG__seg_5__seg 1 -#define R_MMU_KSEG__seg_5__page 0 -#define R_MMU_KSEG__seg_4__BITNR 4 -#define R_MMU_KSEG__seg_4__WIDTH 1 -#define R_MMU_KSEG__seg_4__seg 1 -#define R_MMU_KSEG__seg_4__page 0 -#define R_MMU_KSEG__seg_3__BITNR 3 -#define R_MMU_KSEG__seg_3__WIDTH 1 -#define R_MMU_KSEG__seg_3__seg 1 -#define R_MMU_KSEG__seg_3__page 0 -#define R_MMU_KSEG__seg_2__BITNR 2 -#define R_MMU_KSEG__seg_2__WIDTH 1 -#define R_MMU_KSEG__seg_2__seg 1 -#define R_MMU_KSEG__seg_2__page 0 -#define R_MMU_KSEG__seg_1__BITNR 1 -#define R_MMU_KSEG__seg_1__WIDTH 1 -#define R_MMU_KSEG__seg_1__seg 1 -#define R_MMU_KSEG__seg_1__page 0 -#define R_MMU_KSEG__seg_0__BITNR 0 -#define R_MMU_KSEG__seg_0__WIDTH 1 -#define R_MMU_KSEG__seg_0__seg 1 -#define R_MMU_KSEG__seg_0__page 0 - -#define R_MMU_CTRL (IO_TYPECAST_BYTE 0xb0000242) -#define R_MMU_CTRL__inv_excp__BITNR 2 -#define R_MMU_CTRL__inv_excp__WIDTH 1 -#define R_MMU_CTRL__inv_excp__enable 1 -#define R_MMU_CTRL__inv_excp__disable 0 -#define R_MMU_CTRL__acc_excp__BITNR 1 -#define R_MMU_CTRL__acc_excp__WIDTH 1 -#define R_MMU_CTRL__acc_excp__enable 1 -#define R_MMU_CTRL__acc_excp__disable 0 -#define R_MMU_CTRL__we_excp__BITNR 0 -#define R_MMU_CTRL__we_excp__WIDTH 1 -#define R_MMU_CTRL__we_excp__enable 1 -#define R_MMU_CTRL__we_excp__disable 0 - -#define R_MMU_ENABLE (IO_TYPECAST_BYTE 0xb0000243) -#define R_MMU_ENABLE__mmu_enable__BITNR 7 -#define R_MMU_ENABLE__mmu_enable__WIDTH 1 -#define R_MMU_ENABLE__mmu_enable__enable 1 -#define R_MMU_ENABLE__mmu_enable__disable 0 - -#define R_MMU_KBASE_LO (IO_TYPECAST_UDWORD 0xb0000244) -#define R_MMU_KBASE_LO__base_7__BITNR 28 -#define R_MMU_KBASE_LO__base_7__WIDTH 4 -#define R_MMU_KBASE_LO__base_6__BITNR 24 -#define R_MMU_KBASE_LO__base_6__WIDTH 4 -#define R_MMU_KBASE_LO__base_5__BITNR 20 -#define R_MMU_KBASE_LO__base_5__WIDTH 4 -#define R_MMU_KBASE_LO__base_4__BITNR 16 -#define R_MMU_KBASE_LO__base_4__WIDTH 4 -#define R_MMU_KBASE_LO__base_3__BITNR 12 -#define R_MMU_KBASE_LO__base_3__WIDTH 4 -#define R_MMU_KBASE_LO__base_2__BITNR 8 -#define R_MMU_KBASE_LO__base_2__WIDTH 4 -#define R_MMU_KBASE_LO__base_1__BITNR 4 -#define R_MMU_KBASE_LO__base_1__WIDTH 4 -#define R_MMU_KBASE_LO__base_0__BITNR 0 -#define R_MMU_KBASE_LO__base_0__WIDTH 4 - -#define R_MMU_KBASE_HI (IO_TYPECAST_UDWORD 0xb0000248) -#define R_MMU_KBASE_HI__base_f__BITNR 28 -#define R_MMU_KBASE_HI__base_f__WIDTH 4 -#define R_MMU_KBASE_HI__base_e__BITNR 24 -#define R_MMU_KBASE_HI__base_e__WIDTH 4 -#define R_MMU_KBASE_HI__base_d__BITNR 20 -#define R_MMU_KBASE_HI__base_d__WIDTH 4 -#define R_MMU_KBASE_HI__base_c__BITNR 16 -#define R_MMU_KBASE_HI__base_c__WIDTH 4 -#define R_MMU_KBASE_HI__base_b__BITNR 12 -#define R_MMU_KBASE_HI__base_b__WIDTH 4 -#define R_MMU_KBASE_HI__base_a__BITNR 8 -#define R_MMU_KBASE_HI__base_a__WIDTH 4 -#define R_MMU_KBASE_HI__base_9__BITNR 4 -#define R_MMU_KBASE_HI__base_9__WIDTH 4 -#define R_MMU_KBASE_HI__base_8__BITNR 0 -#define R_MMU_KBASE_HI__base_8__WIDTH 4 - -#define R_MMU_CONTEXT (IO_TYPECAST_BYTE 0xb000024c) -#define R_MMU_CONTEXT__page_id__BITNR 0 -#define R_MMU_CONTEXT__page_id__WIDTH 6 - -#define R_MMU_CAUSE (IO_TYPECAST_RO_UDWORD 0xb0000250) -#define R_MMU_CAUSE__vpn__BITNR 13 -#define R_MMU_CAUSE__vpn__WIDTH 19 -#define R_MMU_CAUSE__miss_excp__BITNR 12 -#define R_MMU_CAUSE__miss_excp__WIDTH 1 -#define R_MMU_CAUSE__miss_excp__yes 1 -#define R_MMU_CAUSE__miss_excp__no 0 -#define R_MMU_CAUSE__inv_excp__BITNR 11 -#define R_MMU_CAUSE__inv_excp__WIDTH 1 -#define R_MMU_CAUSE__inv_excp__yes 1 -#define R_MMU_CAUSE__inv_excp__no 0 -#define R_MMU_CAUSE__acc_excp__BITNR 10 -#define R_MMU_CAUSE__acc_excp__WIDTH 1 -#define R_MMU_CAUSE__acc_excp__yes 1 -#define R_MMU_CAUSE__acc_excp__no 0 -#define R_MMU_CAUSE__we_excp__BITNR 9 -#define R_MMU_CAUSE__we_excp__WIDTH 1 -#define R_MMU_CAUSE__we_excp__yes 1 -#define R_MMU_CAUSE__we_excp__no 0 -#define R_MMU_CAUSE__wr_rd__BITNR 8 -#define R_MMU_CAUSE__wr_rd__WIDTH 1 -#define R_MMU_CAUSE__wr_rd__write 1 -#define R_MMU_CAUSE__wr_rd__read 0 -#define R_MMU_CAUSE__page_id__BITNR 0 -#define R_MMU_CAUSE__page_id__WIDTH 6 - -#define R_TLB_SELECT (IO_TYPECAST_BYTE 0xb0000254) -#define R_TLB_SELECT__index__BITNR 0 -#define R_TLB_SELECT__index__WIDTH 6 - -#define R_TLB_LO (IO_TYPECAST_UDWORD 0xb0000258) -#define R_TLB_LO__pfn__BITNR 13 -#define R_TLB_LO__pfn__WIDTH 19 -#define R_TLB_LO__global__BITNR 3 -#define R_TLB_LO__global__WIDTH 1 -#define R_TLB_LO__global__yes 1 -#define R_TLB_LO__global__no 0 -#define R_TLB_LO__valid__BITNR 2 -#define R_TLB_LO__valid__WIDTH 1 -#define R_TLB_LO__valid__yes 1 -#define R_TLB_LO__valid__no 0 -#define R_TLB_LO__kernel__BITNR 1 -#define R_TLB_LO__kernel__WIDTH 1 -#define R_TLB_LO__kernel__yes 1 -#define R_TLB_LO__kernel__no 0 -#define R_TLB_LO__we__BITNR 0 -#define R_TLB_LO__we__WIDTH 1 -#define R_TLB_LO__we__yes 1 -#define R_TLB_LO__we__no 0 - -#define R_TLB_HI (IO_TYPECAST_UDWORD 0xb000025c) -#define R_TLB_HI__vpn__BITNR 13 -#define R_TLB_HI__vpn__WIDTH 19 -#define R_TLB_HI__page_id__BITNR 0 -#define R_TLB_HI__page_id__WIDTH 6 - -/* -!* Syncrounous serial port registers -!*/ - -#define R_SYNC_SERIAL1_REC_DATA (IO_TYPECAST_RO_UDWORD 0xb000006c) -#define R_SYNC_SERIAL1_REC_DATA__data_in__BITNR 0 -#define R_SYNC_SERIAL1_REC_DATA__data_in__WIDTH 32 - -#define R_SYNC_SERIAL1_REC_WORD (IO_TYPECAST_RO_UWORD 0xb000006c) -#define R_SYNC_SERIAL1_REC_WORD__data_in__BITNR 0 -#define R_SYNC_SERIAL1_REC_WORD__data_in__WIDTH 16 - -#define R_SYNC_SERIAL1_REC_BYTE (IO_TYPECAST_RO_BYTE 0xb000006c) -#define R_SYNC_SERIAL1_REC_BYTE__data_in__BITNR 0 -#define R_SYNC_SERIAL1_REC_BYTE__data_in__WIDTH 8 - -#define R_SYNC_SERIAL1_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000068) -#define R_SYNC_SERIAL1_STATUS__rec_status__BITNR 15 -#define R_SYNC_SERIAL1_STATUS__rec_status__WIDTH 1 -#define R_SYNC_SERIAL1_STATUS__rec_status__running 0 -#define R_SYNC_SERIAL1_STATUS__rec_status__idle 1 -#define R_SYNC_SERIAL1_STATUS__tr_empty__BITNR 14 -#define R_SYNC_SERIAL1_STATUS__tr_empty__WIDTH 1 -#define R_SYNC_SERIAL1_STATUS__tr_empty__empty 1 -#define R_SYNC_SERIAL1_STATUS__tr_empty__not_empty 0 -#define R_SYNC_SERIAL1_STATUS__tr_ready__BITNR 13 -#define R_SYNC_SERIAL1_STATUS__tr_ready__WIDTH 1 -#define R_SYNC_SERIAL1_STATUS__tr_ready__full 0 -#define R_SYNC_SERIAL1_STATUS__tr_ready__ready 1 -#define R_SYNC_SERIAL1_STATUS__pin_1__BITNR 12 -#define R_SYNC_SERIAL1_STATUS__pin_1__WIDTH 1 -#define R_SYNC_SERIAL1_STATUS__pin_1__low 0 -#define R_SYNC_SERIAL1_STATUS__pin_1__high 1 -#define R_SYNC_SERIAL1_STATUS__pin_0__BITNR 11 -#define R_SYNC_SERIAL1_STATUS__pin_0__WIDTH 1 -#define R_SYNC_SERIAL1_STATUS__pin_0__low 0 -#define R_SYNC_SERIAL1_STATUS__pin_0__high 1 -#define R_SYNC_SERIAL1_STATUS__underflow__BITNR 10 -#define R_SYNC_SERIAL1_STATUS__underflow__WIDTH 1 -#define R_SYNC_SERIAL1_STATUS__underflow__no 0 -#define R_SYNC_SERIAL1_STATUS__underflow__yes 1 -#define R_SYNC_SERIAL1_STATUS__overrun__BITNR 9 -#define R_SYNC_SERIAL1_STATUS__overrun__WIDTH 1 -#define R_SYNC_SERIAL1_STATUS__overrun__no 0 -#define R_SYNC_SERIAL1_STATUS__overrun__yes 1 -#define R_SYNC_SERIAL1_STATUS__data_avail__BITNR 8 -#define R_SYNC_SERIAL1_STATUS__data_avail__WIDTH 1 -#define R_SYNC_SERIAL1_STATUS__data_avail__no 0 -#define R_SYNC_SERIAL1_STATUS__data_avail__yes 1 -#define R_SYNC_SERIAL1_STATUS__data__BITNR 0 -#define R_SYNC_SERIAL1_STATUS__data__WIDTH 8 - -#define R_SYNC_SERIAL1_TR_DATA (IO_TYPECAST_UDWORD 0xb000006c) -#define R_SYNC_SERIAL1_TR_DATA__data_out__BITNR 0 -#define R_SYNC_SERIAL1_TR_DATA__data_out__WIDTH 32 - -#define R_SYNC_SERIAL1_TR_WORD (IO_TYPECAST_UWORD 0xb000006c) -#define R_SYNC_SERIAL1_TR_WORD__data_out__BITNR 0 -#define R_SYNC_SERIAL1_TR_WORD__data_out__WIDTH 16 - -#define R_SYNC_SERIAL1_TR_BYTE (IO_TYPECAST_BYTE 0xb000006c) -#define R_SYNC_SERIAL1_TR_BYTE__data_out__BITNR 0 -#define R_SYNC_SERIAL1_TR_BYTE__data_out__WIDTH 8 - -#define R_SYNC_SERIAL1_CTRL (IO_TYPECAST_UDWORD 0xb0000068) -#define R_SYNC_SERIAL1_CTRL__tr_baud__BITNR 28 -#define R_SYNC_SERIAL1_CTRL__tr_baud__WIDTH 4 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c150Hz 0 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c300Hz 1 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c600Hz 2 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c1200Hz 3 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c2400Hz 4 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c4800Hz 5 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c9600Hz 6 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c19k2Hz 7 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c28k8Hz 8 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c57k6Hz 9 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c115k2Hz 10 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c230k4Hz 11 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c460k8Hz 12 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c921k6Hz 13 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c3125kHz 14 -#define R_SYNC_SERIAL1_CTRL__tr_baud__reserved 15 -#define R_SYNC_SERIAL1_CTRL__dma_enable__BITNR 27 -#define R_SYNC_SERIAL1_CTRL__dma_enable__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__dma_enable__on 1 -#define R_SYNC_SERIAL1_CTRL__dma_enable__off 0 -#define R_SYNC_SERIAL1_CTRL__mode__BITNR 24 -#define R_SYNC_SERIAL1_CTRL__mode__WIDTH 3 -#define R_SYNC_SERIAL1_CTRL__mode__master_output 0 -#define R_SYNC_SERIAL1_CTRL__mode__slave_output 1 -#define R_SYNC_SERIAL1_CTRL__mode__master_input 2 -#define R_SYNC_SERIAL1_CTRL__mode__slave_input 3 -#define R_SYNC_SERIAL1_CTRL__mode__master_bidir 4 -#define R_SYNC_SERIAL1_CTRL__mode__slave_bidir 5 -#define R_SYNC_SERIAL1_CTRL__error__BITNR 23 -#define R_SYNC_SERIAL1_CTRL__error__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__error__normal 0 -#define R_SYNC_SERIAL1_CTRL__error__ignore 1 -#define R_SYNC_SERIAL1_CTRL__rec_enable__BITNR 22 -#define R_SYNC_SERIAL1_CTRL__rec_enable__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__rec_enable__disable 0 -#define R_SYNC_SERIAL1_CTRL__rec_enable__enable 1 -#define R_SYNC_SERIAL1_CTRL__f_synctype__BITNR 21 -#define R_SYNC_SERIAL1_CTRL__f_synctype__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__f_synctype__normal 0 -#define R_SYNC_SERIAL1_CTRL__f_synctype__early 1 -#define R_SYNC_SERIAL1_CTRL__f_syncsize__BITNR 19 -#define R_SYNC_SERIAL1_CTRL__f_syncsize__WIDTH 2 -#define R_SYNC_SERIAL1_CTRL__f_syncsize__bit 0 -#define R_SYNC_SERIAL1_CTRL__f_syncsize__word 1 -#define R_SYNC_SERIAL1_CTRL__f_syncsize__extended 2 -#define R_SYNC_SERIAL1_CTRL__f_syncsize__reserved 3 -#define R_SYNC_SERIAL1_CTRL__f_sync__BITNR 18 -#define R_SYNC_SERIAL1_CTRL__f_sync__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__f_sync__on 0 -#define R_SYNC_SERIAL1_CTRL__f_sync__off 1 -#define R_SYNC_SERIAL1_CTRL__clk_mode__BITNR 17 -#define R_SYNC_SERIAL1_CTRL__clk_mode__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__clk_mode__normal 0 -#define R_SYNC_SERIAL1_CTRL__clk_mode__gated 1 -#define R_SYNC_SERIAL1_CTRL__clk_halt__BITNR 16 -#define R_SYNC_SERIAL1_CTRL__clk_halt__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__clk_halt__running 0 -#define R_SYNC_SERIAL1_CTRL__clk_halt__stopped 1 -#define R_SYNC_SERIAL1_CTRL__bitorder__BITNR 15 -#define R_SYNC_SERIAL1_CTRL__bitorder__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__bitorder__lsb 0 -#define R_SYNC_SERIAL1_CTRL__bitorder__msb 1 -#define R_SYNC_SERIAL1_CTRL__tr_enable__BITNR 14 -#define R_SYNC_SERIAL1_CTRL__tr_enable__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__tr_enable__disable 0 -#define R_SYNC_SERIAL1_CTRL__tr_enable__enable 1 -#define R_SYNC_SERIAL1_CTRL__wordsize__BITNR 11 -#define R_SYNC_SERIAL1_CTRL__wordsize__WIDTH 3 -#define R_SYNC_SERIAL1_CTRL__wordsize__size8bit 0 -#define R_SYNC_SERIAL1_CTRL__wordsize__size12bit 1 -#define R_SYNC_SERIAL1_CTRL__wordsize__size16bit 2 -#define R_SYNC_SERIAL1_CTRL__wordsize__size24bit 3 -#define R_SYNC_SERIAL1_CTRL__wordsize__size32bit 4 -#define R_SYNC_SERIAL1_CTRL__buf_empty__BITNR 10 -#define R_SYNC_SERIAL1_CTRL__buf_empty__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__buf_empty__lmt_8 0 -#define R_SYNC_SERIAL1_CTRL__buf_empty__lmt_0 1 -#define R_SYNC_SERIAL1_CTRL__buf_full__BITNR 9 -#define R_SYNC_SERIAL1_CTRL__buf_full__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__buf_full__lmt_32 0 -#define R_SYNC_SERIAL1_CTRL__buf_full__lmt_8 1 -#define R_SYNC_SERIAL1_CTRL__flow_ctrl__BITNR 8 -#define R_SYNC_SERIAL1_CTRL__flow_ctrl__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__flow_ctrl__disabled 0 -#define R_SYNC_SERIAL1_CTRL__flow_ctrl__enabled 1 -#define R_SYNC_SERIAL1_CTRL__clk_polarity__BITNR 6 -#define R_SYNC_SERIAL1_CTRL__clk_polarity__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__clk_polarity__pos 0 -#define R_SYNC_SERIAL1_CTRL__clk_polarity__neg 1 -#define R_SYNC_SERIAL1_CTRL__frame_polarity__BITNR 5 -#define R_SYNC_SERIAL1_CTRL__frame_polarity__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__frame_polarity__normal 0 -#define R_SYNC_SERIAL1_CTRL__frame_polarity__inverted 1 -#define R_SYNC_SERIAL1_CTRL__status_polarity__BITNR 4 -#define R_SYNC_SERIAL1_CTRL__status_polarity__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__status_polarity__normal 0 -#define R_SYNC_SERIAL1_CTRL__status_polarity__inverted 1 -#define R_SYNC_SERIAL1_CTRL__clk_driver__BITNR 3 -#define R_SYNC_SERIAL1_CTRL__clk_driver__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__clk_driver__normal 0 -#define R_SYNC_SERIAL1_CTRL__clk_driver__inverted 1 -#define R_SYNC_SERIAL1_CTRL__frame_driver__BITNR 2 -#define R_SYNC_SERIAL1_CTRL__frame_driver__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__frame_driver__normal 0 -#define R_SYNC_SERIAL1_CTRL__frame_driver__inverted 1 -#define R_SYNC_SERIAL1_CTRL__status_driver__BITNR 1 -#define R_SYNC_SERIAL1_CTRL__status_driver__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__status_driver__normal 0 -#define R_SYNC_SERIAL1_CTRL__status_driver__inverted 1 -#define R_SYNC_SERIAL1_CTRL__def_out0__BITNR 0 -#define R_SYNC_SERIAL1_CTRL__def_out0__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__def_out0__high 1 -#define R_SYNC_SERIAL1_CTRL__def_out0__low 0 - -#define R_SYNC_SERIAL3_REC_DATA (IO_TYPECAST_RO_UDWORD 0xb000007c) -#define R_SYNC_SERIAL3_REC_DATA__data_in__BITNR 0 -#define R_SYNC_SERIAL3_REC_DATA__data_in__WIDTH 32 - -#define R_SYNC_SERIAL3_REC_WORD (IO_TYPECAST_RO_UWORD 0xb000007c) -#define R_SYNC_SERIAL3_REC_WORD__data_in__BITNR 0 -#define R_SYNC_SERIAL3_REC_WORD__data_in__WIDTH 16 - -#define R_SYNC_SERIAL3_REC_BYTE (IO_TYPECAST_RO_BYTE 0xb000007c) -#define R_SYNC_SERIAL3_REC_BYTE__data_in__BITNR 0 -#define R_SYNC_SERIAL3_REC_BYTE__data_in__WIDTH 8 - -#define R_SYNC_SERIAL3_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000078) -#define R_SYNC_SERIAL3_STATUS__rec_status__BITNR 15 -#define R_SYNC_SERIAL3_STATUS__rec_status__WIDTH 1 -#define R_SYNC_SERIAL3_STATUS__rec_status__running 0 -#define R_SYNC_SERIAL3_STATUS__rec_status__idle 1 -#define R_SYNC_SERIAL3_STATUS__tr_empty__BITNR 14 -#define R_SYNC_SERIAL3_STATUS__tr_empty__WIDTH 1 -#define R_SYNC_SERIAL3_STATUS__tr_empty__empty 1 -#define R_SYNC_SERIAL3_STATUS__tr_empty__not_empty 0 -#define R_SYNC_SERIAL3_STATUS__tr_ready__BITNR 13 -#define R_SYNC_SERIAL3_STATUS__tr_ready__WIDTH 1 -#define R_SYNC_SERIAL3_STATUS__tr_ready__full 0 -#define R_SYNC_SERIAL3_STATUS__tr_ready__ready 1 -#define R_SYNC_SERIAL3_STATUS__pin_1__BITNR 12 -#define R_SYNC_SERIAL3_STATUS__pin_1__WIDTH 1 -#define R_SYNC_SERIAL3_STATUS__pin_1__low 0 -#define R_SYNC_SERIAL3_STATUS__pin_1__high 1 -#define R_SYNC_SERIAL3_STATUS__pin_0__BITNR 11 -#define R_SYNC_SERIAL3_STATUS__pin_0__WIDTH 1 -#define R_SYNC_SERIAL3_STATUS__pin_0__low 0 -#define R_SYNC_SERIAL3_STATUS__pin_0__high 1 -#define R_SYNC_SERIAL3_STATUS__underflow__BITNR 10 -#define R_SYNC_SERIAL3_STATUS__underflow__WIDTH 1 -#define R_SYNC_SERIAL3_STATUS__underflow__no 0 -#define R_SYNC_SERIAL3_STATUS__underflow__yes 1 -#define R_SYNC_SERIAL3_STATUS__overrun__BITNR 9 -#define R_SYNC_SERIAL3_STATUS__overrun__WIDTH 1 -#define R_SYNC_SERIAL3_STATUS__overrun__no 0 -#define R_SYNC_SERIAL3_STATUS__overrun__yes 1 -#define R_SYNC_SERIAL3_STATUS__data_avail__BITNR 8 -#define R_SYNC_SERIAL3_STATUS__data_avail__WIDTH 1 -#define R_SYNC_SERIAL3_STATUS__data_avail__no 0 -#define R_SYNC_SERIAL3_STATUS__data_avail__yes 1 -#define R_SYNC_SERIAL3_STATUS__data__BITNR 0 -#define R_SYNC_SERIAL3_STATUS__data__WIDTH 8 - -#define R_SYNC_SERIAL3_TR_DATA (IO_TYPECAST_UDWORD 0xb000007c) -#define R_SYNC_SERIAL3_TR_DATA__data_out__BITNR 0 -#define R_SYNC_SERIAL3_TR_DATA__data_out__WIDTH 32 - -#define R_SYNC_SERIAL3_TR_WORD (IO_TYPECAST_UWORD 0xb000007c) -#define R_SYNC_SERIAL3_TR_WORD__data_out__BITNR 0 -#define R_SYNC_SERIAL3_TR_WORD__data_out__WIDTH 16 - -#define R_SYNC_SERIAL3_TR_BYTE (IO_TYPECAST_BYTE 0xb000007c) -#define R_SYNC_SERIAL3_TR_BYTE__data_out__BITNR 0 -#define R_SYNC_SERIAL3_TR_BYTE__data_out__WIDTH 8 - -#define R_SYNC_SERIAL3_CTRL (IO_TYPECAST_UDWORD 0xb0000078) -#define R_SYNC_SERIAL3_CTRL__tr_baud__BITNR 28 -#define R_SYNC_SERIAL3_CTRL__tr_baud__WIDTH 4 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c150Hz 0 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c300Hz 1 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c600Hz 2 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c1200Hz 3 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c2400Hz 4 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c4800Hz 5 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c9600Hz 6 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c19k2Hz 7 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c28k8Hz 8 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c57k6Hz 9 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c115k2Hz 10 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c230k4Hz 11 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c460k8Hz 12 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c921k6Hz 13 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c3125kHz 14 -#define R_SYNC_SERIAL3_CTRL__tr_baud__reserved 15 -#define R_SYNC_SERIAL3_CTRL__dma_enable__BITNR 27 -#define R_SYNC_SERIAL3_CTRL__dma_enable__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__dma_enable__on 1 -#define R_SYNC_SERIAL3_CTRL__dma_enable__off 0 -#define R_SYNC_SERIAL3_CTRL__mode__BITNR 24 -#define R_SYNC_SERIAL3_CTRL__mode__WIDTH 3 -#define R_SYNC_SERIAL3_CTRL__mode__master_output 0 -#define R_SYNC_SERIAL3_CTRL__mode__slave_output 1 -#define R_SYNC_SERIAL3_CTRL__mode__master_input 2 -#define R_SYNC_SERIAL3_CTRL__mode__slave_input 3 -#define R_SYNC_SERIAL3_CTRL__mode__master_bidir 4 -#define R_SYNC_SERIAL3_CTRL__mode__slave_bidir 5 -#define R_SYNC_SERIAL3_CTRL__error__BITNR 23 -#define R_SYNC_SERIAL3_CTRL__error__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__error__normal 0 -#define R_SYNC_SERIAL3_CTRL__error__ignore 1 -#define R_SYNC_SERIAL3_CTRL__rec_enable__BITNR 22 -#define R_SYNC_SERIAL3_CTRL__rec_enable__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__rec_enable__disable 0 -#define R_SYNC_SERIAL3_CTRL__rec_enable__enable 1 -#define R_SYNC_SERIAL3_CTRL__f_synctype__BITNR 21 -#define R_SYNC_SERIAL3_CTRL__f_synctype__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__f_synctype__normal 0 -#define R_SYNC_SERIAL3_CTRL__f_synctype__early 1 -#define R_SYNC_SERIAL3_CTRL__f_syncsize__BITNR 19 -#define R_SYNC_SERIAL3_CTRL__f_syncsize__WIDTH 2 -#define R_SYNC_SERIAL3_CTRL__f_syncsize__bit 0 -#define R_SYNC_SERIAL3_CTRL__f_syncsize__word 1 -#define R_SYNC_SERIAL3_CTRL__f_syncsize__extended 2 -#define R_SYNC_SERIAL3_CTRL__f_syncsize__reserved 3 -#define R_SYNC_SERIAL3_CTRL__f_sync__BITNR 18 -#define R_SYNC_SERIAL3_CTRL__f_sync__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__f_sync__on 0 -#define R_SYNC_SERIAL3_CTRL__f_sync__off 1 -#define R_SYNC_SERIAL3_CTRL__clk_mode__BITNR 17 -#define R_SYNC_SERIAL3_CTRL__clk_mode__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__clk_mode__normal 0 -#define R_SYNC_SERIAL3_CTRL__clk_mode__gated 1 -#define R_SYNC_SERIAL3_CTRL__clk_halt__BITNR 16 -#define R_SYNC_SERIAL3_CTRL__clk_halt__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__clk_halt__running 0 -#define R_SYNC_SERIAL3_CTRL__clk_halt__stopped 1 -#define R_SYNC_SERIAL3_CTRL__bitorder__BITNR 15 -#define R_SYNC_SERIAL3_CTRL__bitorder__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__bitorder__lsb 0 -#define R_SYNC_SERIAL3_CTRL__bitorder__msb 1 -#define R_SYNC_SERIAL3_CTRL__tr_enable__BITNR 14 -#define R_SYNC_SERIAL3_CTRL__tr_enable__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__tr_enable__disable 0 -#define R_SYNC_SERIAL3_CTRL__tr_enable__enable 1 -#define R_SYNC_SERIAL3_CTRL__wordsize__BITNR 11 -#define R_SYNC_SERIAL3_CTRL__wordsize__WIDTH 3 -#define R_SYNC_SERIAL3_CTRL__wordsize__size8bit 0 -#define R_SYNC_SERIAL3_CTRL__wordsize__size12bit 1 -#define R_SYNC_SERIAL3_CTRL__wordsize__size16bit 2 -#define R_SYNC_SERIAL3_CTRL__wordsize__size24bit 3 -#define R_SYNC_SERIAL3_CTRL__wordsize__size32bit 4 -#define R_SYNC_SERIAL3_CTRL__buf_empty__BITNR 10 -#define R_SYNC_SERIAL3_CTRL__buf_empty__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__buf_empty__lmt_8 0 -#define R_SYNC_SERIAL3_CTRL__buf_empty__lmt_0 1 -#define R_SYNC_SERIAL3_CTRL__buf_full__BITNR 9 -#define R_SYNC_SERIAL3_CTRL__buf_full__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__buf_full__lmt_32 0 -#define R_SYNC_SERIAL3_CTRL__buf_full__lmt_8 1 -#define R_SYNC_SERIAL3_CTRL__flow_ctrl__BITNR 8 -#define R_SYNC_SERIAL3_CTRL__flow_ctrl__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__flow_ctrl__disabled 0 -#define R_SYNC_SERIAL3_CTRL__flow_ctrl__enabled 1 -#define R_SYNC_SERIAL3_CTRL__clk_polarity__BITNR 6 -#define R_SYNC_SERIAL3_CTRL__clk_polarity__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__clk_polarity__pos 0 -#define R_SYNC_SERIAL3_CTRL__clk_polarity__neg 1 -#define R_SYNC_SERIAL3_CTRL__frame_polarity__BITNR 5 -#define R_SYNC_SERIAL3_CTRL__frame_polarity__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__frame_polarity__normal 0 -#define R_SYNC_SERIAL3_CTRL__frame_polarity__inverted 1 -#define R_SYNC_SERIAL3_CTRL__status_polarity__BITNR 4 -#define R_SYNC_SERIAL3_CTRL__status_polarity__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__status_polarity__normal 0 -#define R_SYNC_SERIAL3_CTRL__status_polarity__inverted 1 -#define R_SYNC_SERIAL3_CTRL__clk_driver__BITNR 3 -#define R_SYNC_SERIAL3_CTRL__clk_driver__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__clk_driver__normal 0 -#define R_SYNC_SERIAL3_CTRL__clk_driver__inverted 1 -#define R_SYNC_SERIAL3_CTRL__frame_driver__BITNR 2 -#define R_SYNC_SERIAL3_CTRL__frame_driver__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__frame_driver__normal 0 -#define R_SYNC_SERIAL3_CTRL__frame_driver__inverted 1 -#define R_SYNC_SERIAL3_CTRL__status_driver__BITNR 1 -#define R_SYNC_SERIAL3_CTRL__status_driver__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__status_driver__normal 0 -#define R_SYNC_SERIAL3_CTRL__status_driver__inverted 1 -#define R_SYNC_SERIAL3_CTRL__def_out0__BITNR 0 -#define R_SYNC_SERIAL3_CTRL__def_out0__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__def_out0__high 1 -#define R_SYNC_SERIAL3_CTRL__def_out0__low 0 - diff --git a/target/linux/etrax-2.6/image/e100boot/src/cbl/src/sv_addr_ag.h b/target/linux/etrax-2.6/image/e100boot/src/cbl/src/sv_addr_ag.h deleted file mode 100644 index 140f73875e..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/cbl/src/sv_addr_ag.h +++ /dev/null @@ -1,137 +0,0 @@ -/*!************************************************************************** -*! -*! MACROS: -*! IO_MASK(reg,field) -*! IO_STATE(reg,field,state) -*! IO_EXTRACT(reg,field,val) -*! IO_STATE_VALUE(reg,field,state) -*! IO_BITNR(reg,field) -*! IO_WIDTH(reg,field) -*! IO_FIELD(reg,field,val) -*! IO_RD(reg) -*! All moderegister addresses and fields of these. -*! -*!**************************************************************************/ - -#ifndef __sv_addr_ag_h__ -#define __sv_addr_ag_h__ - - -#define __test_sv_addr__ 0 - -/*------------------------------------------------------------ -!* General macros to manipulate moderegisters. -!*-----------------------------------------------------------*/ - -/* IO_MASK returns a mask for a specified bitfield in a register. - Note that this macro doesn't work when field width is 32 bits. */ -#define IO_MASK(reg, field) IO_MASK_ (reg##_, field##_) -#define IO_MASK_(reg_, field_) \ - ( ( ( 1 << reg_##_##field_##_WIDTH ) - 1 ) << reg_##_##field_##_BITNR ) - -/* IO_STATE returns a constant corresponding to a one of the symbolic - states that the bitfield can have. (Shifted to correct position) */ -#define IO_STATE(reg, field, state) IO_STATE_ (reg##_, field##_, _##state) -#define IO_STATE_(reg_, field_, _state) \ - ( reg_##_##field_##_state << reg_##_##field_##_BITNR ) - -/* IO_EXTRACT returns the masked and shifted value corresponding to the - bitfield can have. */ -#define IO_EXTRACT(reg, field, val) IO_EXTRACT_ (reg##_, field##_, val) -#define IO_EXTRACT_(reg_, field_, val) ( (( ( ( 1 << reg_##_##field_##_WIDTH ) \ - - 1 ) << reg_##_##field_##_BITNR ) & (val)) >> reg_##_##field_##_BITNR ) - -/* IO_STATE_VALUE returns a constant corresponding to a one of the symbolic - states that the bitfield can have. (Not shifted) */ -#define IO_STATE_VALUE(reg, field, state) \ - IO_STATE_VALUE_ (reg##_, field##_, _##state) -#define IO_STATE_VALUE_(reg_, field_, _state) ( reg_##_##field_##_state ) - -/* IO_FIELD shifts the val parameter to be aligned with the bitfield - specified. */ -#define IO_FIELD(reg, field, val) IO_FIELD_ (reg##_, field##_, val) -#define IO_FIELD_(reg_, field_, val) ((val) << reg_##_##field_##_BITNR) - -/* IO_BITNR returns the starting bitnumber of a bitfield. Bit 0 is - LSB and the returned bitnumber is LSB of the field. */ -#define IO_BITNR(reg, field) IO_BITNR_ (reg##_, field##_) -#define IO_BITNR_(reg_, field_) (reg_##_##field_##_BITNR) - -/* IO_WIDTH returns the width, in bits, of a bitfield. */ -#define IO_WIDTH(reg, field) IO_WIDTH_ (reg##_, field##_) -#define IO_WIDTH_(reg_, field_) (reg_##_##field_##_WIDTH) - -/*--- Obsolete. Kept for backw compatibility. ---*/ -/* Reads (or writes) a byte/uword/udword from the specified mode - register. */ -#define IO_RD(reg) (*(volatile udword*)(reg)) -#define IO_RD_B(reg) (*(volatile byte*)(reg)) -#define IO_RD_W(reg) (*(volatile uword*)(reg)) -#define IO_RD_D(reg) (*(volatile udword*)(reg)) - -/*------------------------------------------------------------ -!* Start addresses of the different memory areas. -!*-----------------------------------------------------------*/ - -#define MEM_CSE0_START (0x00000000) -#define MEM_CSE1_START (0x04000000) -#define MEM_CSR0_START (0x08000000) -#define MEM_CSR1_START (0x0c000000) -#define MEM_CSP0_START (0x10000000) -#define MEM_CSP1_START (0x14000000) -#define MEM_CSP2_START (0x18000000) -#define MEM_CSP3_START (0x1c000000) -#define MEM_CSP4_START (0x20000000) -#define MEM_CSP5_START (0x24000000) -#define MEM_CSP6_START (0x28000000) -#define MEM_CSP7_START (0x2c000000) -#define MEM_DRAM_START (0x40000000) - -#define MEM_NON_CACHEABLE (0x80000000) - -/*------------------------------------------------------------ -!* Type casts used in mode register macros, making pointer -!* dereferencing possible. Empty in assembler. -!*-----------------------------------------------------------*/ - -#ifndef __ASSEMBLER__ -# define IO_TYPECAST_UDWORD (volatile udword*) -# define IO_TYPECAST_RO_UDWORD (const volatile udword*) -# define IO_TYPECAST_UWORD (volatile uword*) -# define IO_TYPECAST_RO_UWORD (const volatile uword*) -# define IO_TYPECAST_BYTE (volatile byte*) -# define IO_TYPECAST_RO_BYTE (const volatile byte*) -#else -# define IO_TYPECAST_UDWORD -# define IO_TYPECAST_RO_UDWORD -# define IO_TYPECAST_UWORD -# define IO_TYPECAST_RO_UWORD -# define IO_TYPECAST_BYTE -# define IO_TYPECAST_RO_BYTE -#endif - -/*------------------------------------------------------------*/ - -#include "sv_addr.agh" - -#if __test_sv_addr__ -/* IO_MASK( R_BUS_CONFIG , CE ) */ -IO_MASK( R_WAITSTATES , SRAM_WS ) -IO_MASK( R_TEST , W32 ) - -IO_STATE( R_BUS_CONFIG, CE, DISABLE ) -IO_STATE( R_BUS_CONFIG, CE, ENABLE ) - -IO_STATE( R_DRAM_TIMING, REF, IVAL2 ) - -IO_MASK( R_DRAM_TIMING, REF ) - -IO_MASK( R_EXT_DMA_0_STAT, TFR_COUNT ) >> IO_BITNR( R_EXT_DMA_0_STAT, TFR_COUNT ) - -IO_RD(R_EXT_DMA_0_STAT) & IO_MASK( R_EXT_DMA_0_STAT, S ) - == IO_STATE( R_EXT_DMA_0_STAT, S, STARTED ) -#endif - - -#endif /* ifndef __sv_addr_ag_h__ */ - diff --git a/target/linux/etrax-2.6/image/e100boot/src/doc/Makefile b/target/linux/etrax-2.6/image/e100boot/src/doc/Makefile deleted file mode 100644 index df6076b8e2..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/doc/Makefile +++ /dev/null @@ -1,17 +0,0 @@ -OBJS=e100boot.1 e100boot.html - -all: $(OBJS) - -%.1: %.pod - pod2man $< > $@ - -%.html: %.pod - pod2html $< > $@ - @rm -f pod2htmd.x~~ pod2htmi.x~~ - -clean: - rm -f *cache *~ - -# The 'clean' doesn't remove the generated documentation as we want -# them in the distribution. - diff --git a/target/linux/etrax-2.6/image/e100boot/src/doc/e100boot.1 b/target/linux/etrax-2.6/image/e100boot/src/doc/e100boot.1 deleted file mode 100644 index 116b9e577f..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/doc/e100boot.1 +++ /dev/null @@ -1,401 +0,0 @@ -.\" Automatically generated by Pod::Man v1.37, Pod::Parser v1.32 -.\" -.\" Standard preamble: -.\" ======================================================================== -.de Sh \" Subsection heading -.br -.if t .Sp -.ne 5 -.PP -\fB\\$1\fR -.PP -.. -.de Sp \" Vertical space (when we can't use .PP) -.if t .sp .5v -.if n .sp -.. -.de Vb \" Begin verbatim text -.ft CW -.nf -.ne \\$1 -.. -.de Ve \" End verbatim text -.ft R -.fi -.. -.\" Set up some character translations and predefined strings. \*(-- will -.\" give an unbreakable dash, \*(PI will give pi, \*(L" will give a left -.\" double quote, and \*(R" will give a right double quote. \*(C+ will -.\" give a nicer C++. Capital omega is used to do unbreakable dashes and -.\" therefore won't be available. \*(C` and \*(C' expand to `' in nroff, -.\" nothing in troff, for use with C<>. -.tr \(*W- -.ds C+ C\v'-.1v'\h'-1p'\s-2+\h'-1p'+\s0\v'.1v'\h'-1p' -.ie n \{\ -. ds -- \(*W- -. ds PI pi -. if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch -. if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch -. ds L" "" -. ds R" "" -. ds C` "" -. ds C' "" -'br\} -.el\{\ -. ds -- \|\(em\| -. ds PI \(*p -. ds L" `` -. ds R" '' -'br\} -.\" -.\" If the F register is turned on, we'll generate index entries on stderr for -.\" titles (.TH), headers (.SH), subsections (.Sh), items (.Ip), and index -.\" entries marked with X<> in POD. Of course, you'll have to process the -.\" output yourself in some meaningful fashion. -.if \nF \{\ -. de IX -. tm Index:\\$1\t\\n%\t"\\$2" -.. -. nr % 0 -. rr F -.\} -.\" -.\" For nroff, turn off justification. Always turn off hyphenation; it makes -.\" way too many mistakes in technical documents. -.hy 0 -.if n .na -.\" -.\" Accent mark definitions (@(#)ms.acc 1.5 88/02/08 SMI; from UCB 4.2). -.\" Fear. Run. Save yourself. No user-serviceable parts. -. \" fudge factors for nroff and troff -.if n \{\ -. ds #H 0 -. ds #V .8m -. ds #F .3m -. ds #[ \f1 -. ds #] \fP -.\} -.if t \{\ -. ds #H ((1u-(\\\\n(.fu%2u))*.13m) -. ds #V .6m -. ds #F 0 -. ds #[ \& -. ds #] \& -.\} -. \" simple accents for nroff and troff -.if n \{\ -. ds ' \& -. ds ` \& -. ds ^ \& -. ds , \& -. ds ~ ~ -. ds / -.\} -.if t \{\ -. ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u" -. ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u' -. ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'^\h'|\\n:u' -. ds , \\k:\h'-(\\n(.wu*8/10)',\h'|\\n:u' -. ds ~ \\k:\h'-(\\n(.wu-\*(#H-.1m)'~\h'|\\n:u' -. ds / \\k:\h'-(\\n(.wu*8/10-\*(#H)'\z\(sl\h'|\\n:u' -.\} -. \" troff and (daisy-wheel) nroff accents -.ds : \\k:\h'-(\\n(.wu*8/10-\*(#H+.1m+\*(#F)'\v'-\*(#V'\z.\h'.2m+\*(#F'.\h'|\\n:u'\v'\*(#V' -.ds 8 \h'\*(#H'\(*b\h'-\*(#H' -.ds o \\k:\h'-(\\n(.wu+\w'\(de'u-\*(#H)/2u'\v'-.3n'\*(#[\z\(de\v'.3n'\h'|\\n:u'\*(#] -.ds d- \h'\*(#H'\(pd\h'-\w'~'u'\v'-.25m'\f2\(hy\fP\v'.25m'\h'-\*(#H' -.ds D- D\\k:\h'-\w'D'u'\v'-.11m'\z\(hy\v'.11m'\h'|\\n:u' -.ds th \*(#[\v'.3m'\s+1I\s-1\v'-.3m'\h'-(\w'I'u*2/3)'\s-1o\s+1\*(#] -.ds Th \*(#[\s+2I\s-2\h'-\w'I'u*3/5'\v'-.3m'o\v'.3m'\*(#] -.ds ae a\h'-(\w'a'u*4/10)'e -.ds Ae A\h'-(\w'A'u*4/10)'E -. \" corrections for vroff -.if v .ds ~ \\k:\h'-(\\n(.wu*9/10-\*(#H)'\s-2\u~\d\s+2\h'|\\n:u' -.if v .ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'\v'-.4m'^\v'.4m'\h'|\\n:u' -. \" for low resolution devices (crt and lpr) -.if \n(.H>23 .if \n(.V>19 \ -\{\ -. ds : e -. ds 8 ss -. ds o a -. ds d- d\h'-1'\(ga -. ds D- D\h'-1'\(hy -. ds th \o'bp' -. ds Th \o'LP' -. ds ae ae -. ds Ae AE -.\} -.rm #[ #] #H #V #F C -.\" ======================================================================== -.\" -.IX Title "E100BOOT 1" -.TH E100BOOT 1 "2003-12-16" "perl v5.8.8" "User Contributed Perl Documentation" -.SH "NAME" -e100boot \- Network and serial port bootloader for the ETRAX100 CPU. -.SH "SYNOPSIS" -.IX Header "SYNOPSIS" -\&\fBe100boot\fR [\fB\-\-device\fR \fIdevicename\fR] -[\fB\-\-file\fR \fIfilename\fR|\- \fIaddr\fR [\fIsize\fR]] -[\fB\-\-flash\fR \fIram-source\fR \fIflash-offset\fR \fIsize\fR] [\fB\-\-pause\fR \fIiter\fR] -[\fB\-\-memtest\fR \fIaddr\fR \fIaddr\fR] [\fB\-\-memclear\fR \fIaddr\fR \fIaddr\fR] -[\fB\-\-memdump\fR \fIaddr\fR \fIaddr\fR] [\fB\-\-setreg\fR \fIaddr\fR|\fIregname\fR \fIval\fR] -[\fB\-\-getreg\fR \fIaddr\fR|\fIregname\fR] [\fB\-\-verify\fR \fIaddr\fR \fIval\fR] -[\fB\-\-label\fR \fIlabel\fR] [\fB\-\-loop\fR \fIaddr\fR \fIlabel\fR] [\fB\-\-5400\fR] [\fB\-\-5600\fR] -[\fB\-\-testcard\fR] [\fB\-\-devboard\fR] [\fB\-\-testcardlx\fR] [\fB\-\-network\fR] [\fB\-\-serial\fR] -[\fB\-\-baudrate\fR \fIbaudrate\fR] [\fB\-\-bootfile\fR \fIfile\fR] [\fB\-\-jump\fR \fIaddr\fR] -[\fB\-\-tofiles\fR] [\fB\-\-cmdsonly\fR] [\fB\-\-images\fR] [\fB\-\-noleds\fR] [\fB\-\-help\fR] -.SH "DESCRIPTION" -.IX Header "DESCRIPTION" -This boot loader facilitates loading of files over the network or a -serial port to an \s-1ETRAX100\s0. It can also be used for fairly extensive -hardware debugging as you can read and write to any memory addresses, -including the \s-1ETRAX100\s0 registers. You can also perform memory checks -and dumps and copy data to flash memories. -.PP -The first packet (or the first 784 bytes in the case of serial boot) -sent to Etrax100 is loaded into the cache. The code in this packet is -executed and loads the rest of the boot loader into the cache. The -cache is the only thing we can be sure of exists on all \s-1ETRAX100\s0 -products, so the boot loader is limited to the size of the cache, -8KB. If further boot loading code is needed you have to set up -external memory and load another boot loader into it, but this is -rarely needed. -.PP -Two programs are involved in this boot loading, one is the program on -your workstation that sends the packets to \s-1ETRAX100\s0, this is called -the server boot loader or \s-1SBL\s0. The other program is the one in -\&\s-1ETRAX100\s0 that receives packets from the \s-1SBL\s0 and acts upon the data -therein, this is called the client boot loader or \s-1CBL\s0. -.PP -We don't want to edit and recompile the \s-1CBL\s0 each time we want to load -level two to different parts of memory, like we do on different -products. We also want to change things like the setup of external -memory before we load data into it. To make the boot loading as -flexible as possible and separate the \s-1CBL\s0 from level two we send a -configuration packet to it. After this packet we load other files, if -we want to. -.PP -The configuration packet can contain information to the \s-1CBL\s0 which lets -you: initialize external memory, read and write to all \s-1ETRAX100\s0 -registers, read and write to any part of memory, load as many other -files as you like to any part of memory you like, etc. The -configuration packet is generated on the fly by the \s-1SBL\s0. -.PP -Since the \s-1CBL\s0 is unaware of which product it will be loaded on, it -doesn't do product specific initialization like setting up the -memory. This must be done with the configuration packet. -.Sh "Debugging printout" -.IX Subsection "Debugging printout" -When doing network boot the debugging printout from the \s-1CBL\s0 in \s-1ETRAX\s0 -is transmitted back over the network and printed by e100boot. When -doing serial boot that interface will be used. So in either case you -will not need any other software or hardware to receive the debugging -printout. -.Sh "Creating binaries" -.IX Subsection "Creating binaries" -The files containing code to be loaded on the \s-1ETRAX100\s0 must be -stripped using the standard \s-1GCC\s0 binutils. -.Sh "How it works, things you don't want to know." -.IX Subsection "How it works, things you don't want to know." -ack, timeout bla, bla... \s-1RTFS\s0. -.Sh "Compilation and code" -.IX Subsection "Compilation and code" -Noteworthy is that two separate \s-1ETRAX100\s0 binaries are created, one for -network boot and one for serial boot. They actually contain exactly -the same code, but linked in different order. This is because the code -to load the rest of the bootloader over a specific interface must be -contained in the first data sent to the \s-1ETRAX100\s0 and it is too -difficult to cram the code for both interfaces in the beginning of the -same binary. Hence two files. -.PP -Other stuff you don't want to know is that the cache is mapped from -0x380000f0 to 0x380020f0. Code starts at the first address followed by -data up to the symbol \fIEbss\fR. At the other end is the buffer for boot -commands (addresses defined by \fI\s-1IO_BUF_START\s0\fR and \fI\s-1IO_BUF_END\s0\fR below -which the stack lies and hopefully the stack and \fIEbss\fR will never -meet... -.PP -The serial data is loaded from 0x380000f0 to 0x380003ff before -execution starts. -.SH "OPTIONS" -.IX Header "OPTIONS" -The options are done in the order specified on the command line, so -you probably want to do any memory setup before loading a file to the -memory, and you probably do not want to perform a memory test after -you have loaded a file to that memory. -.PP -All addresses and sizes must be in hex with optional '0x' prefix, or a -\&\s-1ETRAX100\s0 register name. Since the \fB\-\-setreg\fR and \fB\-\-getreg\fR options -only can be performed on dword aligned dwords only the registers that -conform to this can be named. -.PP -Note also that all addresses must be in uncached memory (bit 31 set), -as the bootloader lies in the cache. If you access any uncached -address during boot, the bootloader will be destroyed without warning. -.PP -It is also possible to specify an address as \fI+address\fR, in which -case it is considered to be relative to \fI\s-1IO_BUF_START\s0\fR. This is -especially useful in combination with the \fB\-\-loop\fR option below. -.IP "\fB\-\-baudrate\fR \fIbaudrate\fR" 4 -.IX Item "--baudrate baudrate" -Set baudrate for files loaded after the boot loader. -.IP "\fB\-\-bootfile\fR \fIfilename\fR" 4 -.IX Item "--bootfile filename" -Which boot image to send to \s-1ETRAX\s0 instead of the default ones. -.IP "\fB\-\-cmdsonly\fR" 4 -.IX Item "--cmdsonly" -Write the commands to file e100boot.cmds. -.IP "\fB\-\-devboard\fR" 4 -.IX Item "--devboard" -Sets registers for the developer board. -.IP "\fB\-\-device\fR \fIdevicename\fR" 4 -.IX Item "--device devicename" -Which device to send packets on. For network boot the default is -eth0. For serial boot it is ttyS0. -.IP "\fB\-\-file\fR \fIfilename\fR|\- \fIaddress\fR [\fIsize\fR]" 4 -.IX Item "--file filename|- address [size]" -The file to load and the address to load it to. If file is loaded on -stdin, specify filename '\-' followed by a size. Size need only be -given in this case. You can load as many files as you want, each -specified with a \fB\-\-file\fR. -.IP "\fB\-\-flash\fR \fIram-source flash-offset size\fR" 4 -.IX Item "--flash ram-source flash-offset size" -Copies the specified \s-1RAM\s0 area to the flash. -.IP "\fB\-\-getreg\fR \fIaddress\fR|\fIregname\fR" 4 -.IX Item "--getreg address|regname" -Print value of memory location. Must be uncached address. -.IP "\fB\-\-help\fR" 4 -.IX Item "--help" -Print the help information. -.IP "\fB\-\-images\fR" 4 -.IX Item "--images" -Print information about the internal boot images, then exit. -.IP "\fB\-\-jump\fR \fIaddress\fR" 4 -.IX Item "--jump address" -Jump to specified address. -.IP "\fB\-\-label\fR \fIlabel\fR" 4 -.IX Item "--label label" -Define a label to be used as target by the \fB\-\-loop\fR command. This -command is only used by the \s-1SBL\s0 to calculate the address for the -\&\fB\-\-loop\fR and does not take up any space in the configuration packet. -.IP "\fB\-\-loop\fR \fIcheck-address label\fR" 4 -.IX Item "--loop check-address label" -If the contents of check-address is nonzero it is decremented and the -command parser continues parsing at the label. -.Sp -If no external memory is initialized yet it can be convenient to use -an address in the area occupied by the configuration packet. Run -e100boot with \fB\-\-help\fR to see which addresses the commands are stored -at. The size of the commands are four bytes for each command plus four -bytes per argument to the command. -.IP "\fB\-\-memclear\fR \fIstart-address end-address\fR" 4 -.IX Item "--memclear start-address end-address" -Clears the specified memory area. -.IP "\fB\-\-memdump\fR \fIstart-address end-address\fR" 4 -.IX Item "--memdump start-address end-address" -Prints the contents of the specified memory area. -.IP "\fB\-\-memtest\fR \fIstart-address end-address\fR" 4 -.IX Item "--memtest start-address end-address" -Does a fairly extensive test of the specified memory area. Not only -catches defect memories but also catches things like wrong memory -setups where memory addresses are mirrored onto each other. -.IP "\fB\-\-network\fR" 4 -.IX Item "--network" -Perform a network boot. -.IP "\fB\-\-noleds\fR" 4 -.IX Item "--noleds" -When using the internal images use a version that does not toggle -general port \s-1PA\s0 or \s-1PB\s0 in \s-1ETRAX\s0 during the boot procedure. -.IP "\fB\-\-pause\fR \fIiterations\fR" 4 -.IX Item "--pause iterations" -How many \fIiterations\fR to do of an empty loop. -.IP "\fB\-\-serial\fR" 4 -.IX Item "--serial" -Do a serial boot. -.IP "\fB\-\-setreg\fR \fIaddress\fR|\fIregname\fR \fIvalue\fR" 4 -.IX Item "--setreg address|regname value" -Load dword to dword aligned memory location. -.IP "\fB\-\-testcard\fR" 4 -.IX Item "--testcard" -Configures the memories for the \s-1ETRAX\s0 100 testcard. -.IP "\fB\-\-testcardlx\fR" 4 -.IX Item "--testcardlx" -Configures the memories for the \s-1ETRAX100\s0 \s-1LX\s0 testcard. -.IP "\fB\-\-tofiles\fR" 4 -.IX Item "--tofiles" -Write packets to files e100boot.seq[0..]. Does not transmit the data. -.IP "\fB\-\-verify\fR \fIaddress value\fR" 4 -.IX Item "--verify address value" -Verify that memory contains dword. If not loader will stop. This is to -avoid booting the wrong unit. If you have the units ethernet address -in the flash memory you can check for that. -.IP "\fB\-\-5400\fR" 4 -.IX Item "--5400" -Sets R_WAITSTATES, R_DRAM_TIMING and R_DRAM_CONFIG for the 5400 -printserver. -.IP "\fB\-\-5600\fR" 4 -.IX Item "--5600" -Sets R_WAITSTATES, R_DRAM_TIMING and R_DRAM_CONFIG for the 5600 -printserver. -.SH "EXAMPLES" -.IX Header "EXAMPLES" -If you have a stripped binary (file.ima) linked to 0x08000000 that you want -to boot via the network, do this: -.PP -\&\fBe100boot \-\-file file.ima 88000000 \-\-jump 08000000\fR -.PP -Or something like this. Sets waitstates to zero and loads two files, -the first from stdin: -.PP -\&\fBcat file.ima | e100boot \-\-memtest 88000000 8801ffff \-\-memclear -88000000 8801ffff \-\-setreg b0000000 0 \-\-getreg b0000000 \-\-file \- -88000000 a000 \-\-file file2.ima 88010000 \-\-memdump 88000000 880000ff -\&\-\-jump 08000000\fR -.PP -Or this, enables 16 bit parallel port and flashes the led on \s-1PA0:\s0 -.PP -\&\fBe100boot \-\-testcardlx \-\-setreg R_PORT_PA_SET 0x00000000 \-\-setreg -R_GEN_CONFIG 0x80000004 \-\-setreg R_PAR0_CONFIG 0x00000200 \-\-setreg -R_PORT_G_DATA 0x00000000 \-\-pause 0x02000000 \-\-setreg R_PORT_G_DATA -0xffffffff \-\-pause 0x02000000 \-\-setreg R_PORT_G_DATA 0x00000000 \-\-loop -0x38001e0b 0x38001e60\fR -.PP -Setup the memory, test the \s-1SRAM\s0, print the contents of the first 256 -bytes of \s-1SRAM\s0, clear \s-1SRAM\s0, test the \s-1DRAM\s0, print R_DMA_CH0_CMD, load a -file to \s-1SRAM\s0, load another file to \s-1SRAM\s0, load file to \s-1DRAM\s0, jump to -code in \s-1SRAM\s0. -.PP -\&\fBe100boot \-\-setreg b0000000 1000 \-\-setreg b0000008 00006543 \-\-setreg -b000000c 12966060 \-\-memtest 88000000 80000 \-\-memdump 88000000 880000ff -\&\-\-memclear 88000000 80000 \-\-memtest c0000000 400000 \-\-getreg b00001d0 -\&\-\-file file1.ima 88000000 \-\-file file2.ima 88010000 \-\-file file3.ima -c0000000 \-\-jump 88000000\fR -.PP -Boot Linux on the testcard. -.PP -\&\fBe100boot \-\-setreg b0000000 1000 \-\-setreg b0000008 6557 \-\-setreg -b000000c 1b988080 \-\-file timage c0000500 \-\-jump 40000500\fR -.PP -Booting over serial port and using labels to flash the leds on port -\&\s-1PA\s0. -.PP -\&\fBe100boot \-\-serial \-\-device /dev/ttyS1 \-\-baudrate 9600 \-\-label first -\&\-\-setreg 0x380020e0 00000001 \-\-setreg R_PORT_PA_SET 0x0000ff00 \-\-pause -0x02000000 \-\-setreg R_PORT_PA_SET 0x0000ffff \-\-pause 0x02000000 \-\-loop -0x380020e0 first\fR -.SH "BUGS" -.IX Header "BUGS" -You're kidding, right? Check \s-1AUTHOR\s0 below. The only thing -would be the hubris of the author, but that I consider a feature. If -you find any other 'features' report them to -technology@axis.com. Don't bother the author directly, he is busy -playing PlayStation2. -.SH "COPYING" -.IX Header "COPYING" -Copyright © 1996\-2002 Axis Communications \s-1AB\s0. -.SH "AUTHOR" -.IX Header "AUTHOR" -Written by Ronny Ranerup. -.SH "SEE ALSO" -.IX Header "SEE ALSO" -The fine source, which you can get at http://developer.axis.com. diff --git a/target/linux/etrax-2.6/image/e100boot/src/doc/e100boot.html b/target/linux/etrax-2.6/image/e100boot/src/doc/e100boot.html deleted file mode 100644 index 15e23966d0..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/doc/e100boot.html +++ /dev/null @@ -1,395 +0,0 @@ - - - - -e100boot - Network and serial port bootloader for the ETRAX100 CPU. - - - - - - -

- - - - - -
-

-

-

NAME

-

e100boot - Network and serial port bootloader for the ETRAX100 CPU.

-

-

-
-

SYNOPSIS

-

e100boot [--device devicename] -[--file filename|- addr [size]] -[--flash ram-source flash-offset size] [--pause iter] -[--memtest addr addr] [--memclear addr addr] -[--memdump addr addr] [--setreg addr|regname val] -[--getreg addr|regname] [--verify addr val] -[--label label] [--loop addr label] [--5400] [--5600] -[--testcard] [--devboard] [--testcardlx] [--network] [--serial] -[--baudrate baudrate] [--bootfile file] [--jump addr] -[--tofiles] [--cmdsonly] [--images] [--noleds] [--help]

-

-

-
-

DESCRIPTION

-

This boot loader facilitates loading of files over the network or a -serial port to an ETRAX100. It can also be used for fairly extensive -hardware debugging as you can read and write to any memory addresses, -including the ETRAX100 registers. You can also perform memory checks -and dumps and copy data to flash memories.

-

The first packet (or the first 784 bytes in the case of serial boot) -sent to Etrax100 is loaded into the cache. The code in this packet is -executed and loads the rest of the boot loader into the cache. The -cache is the only thing we can be sure of exists on all ETRAX100 -products, so the boot loader is limited to the size of the cache, -8KB. If further boot loading code is needed you have to set up -external memory and load another boot loader into it, but this is -rarely needed.

-

Two programs are involved in this boot loading, one is the program on -your workstation that sends the packets to ETRAX100, this is called -the server boot loader or SBL. The other program is the one in -ETRAX100 that receives packets from the SBL and acts upon the data -therein, this is called the client boot loader or CBL.

-

We don't want to edit and recompile the CBL each time we want to load -level two to different parts of memory, like we do on different -products. We also want to change things like the setup of external -memory before we load data into it. To make the boot loading as -flexible as possible and separate the CBL from level two we send a -configuration packet to it. After this packet we load other files, if -we want to.

-

The configuration packet can contain information to the CBL which lets -you: initialize external memory, read and write to all ETRAX100 -registers, read and write to any part of memory, load as many other -files as you like to any part of memory you like, etc. The -configuration packet is generated on the fly by the SBL.

-

Since the CBL is unaware of which product it will be loaded on, it -doesn't do product specific initialization like setting up the -memory. This must be done with the configuration packet.

-

-

-

Debugging printout

-

When doing network boot the debugging printout from the CBL in ETRAX -is transmitted back over the network and printed by e100boot. When -doing serial boot that interface will be used. So in either case you -will not need any other software or hardware to receive the debugging -printout.

-

-

-

Creating binaries

-

The files containing code to be loaded on the ETRAX100 must be -stripped using the standard GCC binutils.

-

-

-

How it works, things you don't want to know.

-

ack, timeout bla, bla... RTFS.

-

-

-

Compilation and code

-

Noteworthy is that two separate ETRAX100 binaries are created, one for -network boot and one for serial boot. They actually contain exactly -the same code, but linked in different order. This is because the code -to load the rest of the bootloader over a specific interface must be -contained in the first data sent to the ETRAX100 and it is too -difficult to cram the code for both interfaces in the beginning of the -same binary. Hence two files.

-

Other stuff you don't want to know is that the cache is mapped from -0x380000f0 to 0x380020f0. Code starts at the first address followed by -data up to the symbol Ebss. At the other end is the buffer for boot -commands (addresses defined by IO_BUF_START and IO_BUF_END below -which the stack lies and hopefully the stack and Ebss will never -meet...

-

The serial data is loaded from 0x380000f0 to 0x380003ff before -execution starts.

-

-

-
-

OPTIONS

-

The options are done in the order specified on the command line, so -you probably want to do any memory setup before loading a file to the -memory, and you probably do not want to perform a memory test after -you have loaded a file to that memory.

-

All addresses and sizes must be in hex with optional '0x' prefix, or a -ETRAX100 register name. Since the --setreg and --getreg options -only can be performed on dword aligned dwords only the registers that -conform to this can be named.

-

Note also that all addresses must be in uncached memory (bit 31 set), -as the bootloader lies in the cache. If you access any uncached -address during boot, the bootloader will be destroyed without warning.

-

It is also possible to specify an address as +address, in which -case it is considered to be relative to IO_BUF_START. This is -especially useful in combination with the --loop option below.

-
-
--baudrate baudrate - -
-

Set baudrate for files loaded after the boot loader.

-
- -
--bootfile filename - -
-

Which boot image to send to ETRAX instead of the default ones.

-
- -
--cmdsonly - -
-

Write the commands to file e100boot.cmds.

-
- -
--devboard - -
-

Sets registers for the developer board.

-
- -
--device devicename - -
-

Which device to send packets on. For network boot the default is -eth0. For serial boot it is ttyS0.

-
- -
--file filename|- address [size] - -
-

The file to load and the address to load it to. If file is loaded on -stdin, specify filename '-' followed by a size. Size need only be -given in this case. You can load as many files as you want, each -specified with a --file.

-
- -
--flash ram-source flash-offset size - -
-

Copies the specified RAM area to the flash.

-
- -
--getreg address|regname - -
-

Print value of memory location. Must be uncached address.

-
- -
--help - -
-

Print the help information.

-
- -
--images - -
-

Print information about the internal boot images, then exit.

-
- -
--jump address - -
-

Jump to specified address.

-
- -
--label label - -
-

Define a label to be used as target by the --loop command. This -command is only used by the SBL to calculate the address for the ---loop and does not take up any space in the configuration packet.

-
- -
--loop check-address label - -
-

If the contents of check-address is nonzero it is decremented and the -command parser continues parsing at the label.

-
-
-

If no external memory is initialized yet it can be convenient to use -an address in the area occupied by the configuration packet. Run -e100boot with --help to see which addresses the commands are stored -at. The size of the commands are four bytes for each command plus four -bytes per argument to the command.

-
- -
--memclear start-address end-address - -
-

Clears the specified memory area.

-
- -
--memdump start-address end-address - -
-

Prints the contents of the specified memory area.

-
- -
--memtest start-address end-address - -
-

Does a fairly extensive test of the specified memory area. Not only -catches defect memories but also catches things like wrong memory -setups where memory addresses are mirrored onto each other.

-
- -
--network - -
-

Perform a network boot.

-
- -
--noleds - -
-

When using the internal images use a version that does not toggle -general port PA or PB in ETRAX during the boot procedure.

-
- -
--pause iterations - -
-

How many iterations to do of an empty loop.

-
- -
--serial - -
-

Do a serial boot.

-
- -
--setreg address|regname value - -
-

Load dword to dword aligned memory location.

-
- -
--testcard - -
-

Configures the memories for the ETRAX 100 testcard.

-
- -
--testcardlx - -
-

Configures the memories for the ETRAX100 LX testcard.

-
- -
--tofiles - -
-

Write packets to files e100boot.seq[0..]. Does not transmit the data.

-
- -
--verify address value - -
-

Verify that memory contains dword. If not loader will stop. This is to -avoid booting the wrong unit. If you have the units ethernet address -in the flash memory you can check for that.

-
- -
--5400 - -
-

Sets R_WAITSTATES, R_DRAM_TIMING and R_DRAM_CONFIG for the 5400 -printserver.

-
- -
--5600 - -
-

Sets R_WAITSTATES, R_DRAM_TIMING and R_DRAM_CONFIG for the 5600 -printserver.

-
- -
-

-

-
-

EXAMPLES

-

If you have a stripped binary (file.ima) linked to 0x08000000 that you want -to boot via the network, do this:

-

e100boot --file file.ima 88000000 --jump 08000000

-

Or something like this. Sets waitstates to zero and loads two files, -the first from stdin:

-

cat file.ima | e100boot --memtest 88000000 8801ffff --memclear -88000000 8801ffff --setreg b0000000 0 --getreg b0000000 --file - -88000000 a000 --file file2.ima 88010000 --memdump 88000000 880000ff ---jump 08000000

-

Or this, enables 16 bit parallel port and flashes the led on PA0:

-

e100boot --testcardlx --setreg R_PORT_PA_SET 0x00000000 --setreg -R_GEN_CONFIG 0x80000004 --setreg R_PAR0_CONFIG 0x00000200 --setreg -R_PORT_G_DATA 0x00000000 --pause 0x02000000 --setreg R_PORT_G_DATA -0xffffffff --pause 0x02000000 --setreg R_PORT_G_DATA 0x00000000 --loop -0x38001e0b 0x38001e60

-

Setup the memory, test the SRAM, print the contents of the first 256 -bytes of SRAM, clear SRAM, test the DRAM, print R_DMA_CH0_CMD, load a -file to SRAM, load another file to SRAM, load file to DRAM, jump to -code in SRAM.

-

e100boot --setreg b0000000 1000 --setreg b0000008 00006543 --setreg -b000000c 12966060 --memtest 88000000 80000 --memdump 88000000 880000ff ---memclear 88000000 80000 --memtest c0000000 400000 --getreg b00001d0 ---file file1.ima 88000000 --file file2.ima 88010000 --file file3.ima -c0000000 --jump 88000000

-

Boot Linux on the testcard.

-

e100boot --setreg b0000000 1000 --setreg b0000008 6557 --setreg -b000000c 1b988080 --file timage c0000500 --jump 40000500

-

Booting over serial port and using labels to flash the leds on port -PA.

-

e100boot --serial --device /dev/ttyS1 --baudrate 9600 --label first ---setreg 0x380020e0 00000001 --setreg R_PORT_PA_SET 0x0000ff00 --pause -0x02000000 --setreg R_PORT_PA_SET 0x0000ffff --pause 0x02000000 --loop -0x380020e0 first

-

-

-
-

BUGS

-

You're kidding, right? Check AUTHOR below. The only thing -would be the hubris of the author, but that I consider a feature. If -you find any other 'features' report them to -technology@axis.com. Don't bother the author directly, he is busy -playing PlayStation2.

-

-

-
-

COPYING

-

Copyright © 1996-2002 Axis Communications AB.

-

-

-
-

AUTHOR

-

Written by Ronny Ranerup.

-

-

-
-

SEE ALSO

-

The fine source, which you can get at http://developer.axis.com.

- - - - diff --git a/target/linux/etrax-2.6/image/e100boot/src/doc/e100boot.pod b/target/linux/etrax-2.6/image/e100boot/src/doc/e100boot.pod deleted file mode 100644 index 8ff514c6b7..0000000000 --- a/target/linux/etrax-2.6/image/e100boot/src/doc/e100boot.pod +++ /dev/null @@ -1,314 +0,0 @@ -=head1 NAME - -e100boot - Network and serial port bootloader for the ETRAX100 CPU. - -=head1 SYNOPSIS - -B [B<--device> I] -[B<--file> I|- I [I]] -[B<--flash> I I I] [B<--pause> I] -[B<--memtest> I I] [B<--memclear> I I] -[B<--memdump> I I] [B<--setreg> I|I I] -[B<--getreg> I|I] [B<--verify> I I] -[B<--label> I