From df8e6be59a1fbce3f8c6878fe7440a129b1245d6 Mon Sep 17 00:00:00 2001 From: Birger Koblitz Date: Sun, 13 Sep 2020 09:06:13 +0200 Subject: rtl838x: add new architecture This adds support for the RTL838x Architecture. SoCs of this type are used in managed and un-managed Switches and Routers with 8-28 ports. Drivers are provided for SoC initialization, GPIOs, Flash, Ethernet including a DSA switch driver and internal and external PHYs used with these switches. Supported SoCs: RTL8380M RTL8381M RTL8382M The kernel will also boot on the following RTL839x SoCs, however driver support apart from spi-nor is missing: RTL8390 RTL8391 RTL8393 The following PHYs are supported: RTL8214FC (Quad QSGMII multiplexing GMAC and SFP port) RTL8218B internal: internal PHY of the RTL838x chips RTL8318b external (QSGMII 8-port GMAC phy) RTL8382M SerDes for 2 SFP ports Initialization sequences for the PHYs are provided in the form of firmware files. Flash driver supports 3 / 4 byte access DSA switch driver supports VLANs, port isolation, STP and port mirroring. The ALLNET ALL-SG8208M is supported as Proof of Concept: RTL8382M SoC 1 MIPS 4KEc core @ 500MHz 8 Internal PHYs (RTL8218B) 128MB DRAM (Nanya NT5TU128MB) 16MB NOR Flash (MXIC 25L128) 8 GBEthernet ports with one green status LED each (SoC controlled) 1 Power LED (not configurable) 1 SYS LED (configurable) 1 On-Off switch (not configurable) 1 Reset button at the right behind right air-vent (not configurable) 1 Reset button on front panel (configurable) 12V 1A barrel connector 1 serial header with populated standard pin connector and with markings GND TX RX Vcc(3.3V), connection properties: 115200 8N1 To install, upload the sysupgrade image to the OEM webpage. Signed-off-by: Birger Koblitz --- target/linux/rtl838x/Makefile | 22 + .../linux/rtl838x/base-files/etc/board.d/01_leds | 15 + .../rtl838x/base-files/etc/board.d/02_network | 87 + target/linux/rtl838x/base-files/etc/inittab | 3 + .../lib/firmware/rtl838x_phy/rtl838x_8214fc.fw | Bin 0 -> 1676 bytes .../lib/firmware/rtl838x_phy/rtl838x_8218b.fw | Bin 0 -> 1168 bytes .../lib/firmware/rtl838x_phy/rtl838x_8380.fw | Bin 0 -> 1184 bytes .../rtl838x/base-files/lib/upgrade/platform.sh | 19 + target/linux/rtl838x/config-5.4 | 226 ++ .../rtl838x/dts/rtl8382_allnet_all-sg8208m.dts | 221 ++ target/linux/rtl838x/dts/rtl838x.dtsi | 110 + .../arch/mips/include/asm/mach-rtl838x/ioremap.h | 34 + .../arch/mips/include/asm/mach-rtl838x/irq.h | 10 + .../mips/include/asm/mach-rtl838x/mach-rtl838x.h | 428 ++++ .../rtl838x/files-5.4/arch/mips/rtl838x/Makefile | 5 + .../rtl838x/files-5.4/arch/mips/rtl838x/Platform | 6 + .../rtl838x/files-5.4/arch/mips/rtl838x/irq.c | 263 +++ .../rtl838x/files-5.4/arch/mips/rtl838x/prom.c | 174 ++ .../rtl838x/files-5.4/arch/mips/rtl838x/serial.c | 100 + .../rtl838x/files-5.4/arch/mips/rtl838x/setup.c | 187 ++ .../rtl838x/files-5.4/drivers/gpio/gpio-rtl838x.c | 807 ++++++++ .../files-5.4/drivers/mtd/spi-nor/rtl838x-nor.c | 607 ++++++ .../files-5.4/drivers/mtd/spi-nor/rtl838x-spi.h | 111 + .../rtl838x/files-5.4/drivers/net/dsa/rtl838x.h | 188 ++ .../files-5.4/drivers/net/dsa/rtl838x_phy.c | 1286 ++++++++++++ .../rtl838x/files-5.4/drivers/net/dsa/rtl838x_sw.c | 2150 ++++++++++++++++++++ .../files-5.4/drivers/net/ethernet/rtl838x_eth.c | 1205 +++++++++++ .../files-5.4/drivers/net/ethernet/rtl838x_eth.h | 261 +++ target/linux/rtl838x/image/Makefile | 44 + .../300-mips-add-rtl838x-platform.patch | 42 + .../patches-5.4/301-gpio-add-rtl838x-driver.patch | 25 + .../400-mtd-add-rtl838x-spi-flash-driver.patch | 23 + ...00-net-dsa-add-support-for-rtl838x-switch.patch | 26 + ...t-dsa-add-rtl838x-support-for-tag-trailer.patch | 37 + ...et-dsa-increase-dsa-max-ports-for-rtl838x.patch | 13 + ...ethernet-add-support-for-rtl838x-ethernet.patch | 26 + ...703-include-linux-add-phy-ops-for-rtl838x.patch | 13 + ...4-drivers-net-phy-eee-support-for-rtl838x.patch | 41 + target/linux/rtl838x/profiles/00-default.mk | 13 + 39 files changed, 8828 insertions(+) create mode 100644 target/linux/rtl838x/Makefile create mode 100755 target/linux/rtl838x/base-files/etc/board.d/01_leds create mode 100755 target/linux/rtl838x/base-files/etc/board.d/02_network create mode 100644 target/linux/rtl838x/base-files/etc/inittab create mode 100644 target/linux/rtl838x/base-files/lib/firmware/rtl838x_phy/rtl838x_8214fc.fw create mode 100644 target/linux/rtl838x/base-files/lib/firmware/rtl838x_phy/rtl838x_8218b.fw create mode 100644 target/linux/rtl838x/base-files/lib/firmware/rtl838x_phy/rtl838x_8380.fw create mode 100644 target/linux/rtl838x/base-files/lib/upgrade/platform.sh create mode 100644 target/linux/rtl838x/config-5.4 create mode 100644 target/linux/rtl838x/dts/rtl8382_allnet_all-sg8208m.dts create mode 100644 target/linux/rtl838x/dts/rtl838x.dtsi create mode 100644 target/linux/rtl838x/files-5.4/arch/mips/include/asm/mach-rtl838x/ioremap.h create mode 100644 target/linux/rtl838x/files-5.4/arch/mips/include/asm/mach-rtl838x/irq.h create mode 100644 target/linux/rtl838x/files-5.4/arch/mips/include/asm/mach-rtl838x/mach-rtl838x.h create mode 100644 target/linux/rtl838x/files-5.4/arch/mips/rtl838x/Makefile create mode 100644 target/linux/rtl838x/files-5.4/arch/mips/rtl838x/Platform create mode 100644 target/linux/rtl838x/files-5.4/arch/mips/rtl838x/irq.c create mode 100644 target/linux/rtl838x/files-5.4/arch/mips/rtl838x/prom.c create mode 100644 target/linux/rtl838x/files-5.4/arch/mips/rtl838x/serial.c create mode 100644 target/linux/rtl838x/files-5.4/arch/mips/rtl838x/setup.c create mode 100644 target/linux/rtl838x/files-5.4/drivers/gpio/gpio-rtl838x.c create mode 100644 target/linux/rtl838x/files-5.4/drivers/mtd/spi-nor/rtl838x-nor.c create mode 100644 target/linux/rtl838x/files-5.4/drivers/mtd/spi-nor/rtl838x-spi.h create mode 100644 target/linux/rtl838x/files-5.4/drivers/net/dsa/rtl838x.h create mode 100644 target/linux/rtl838x/files-5.4/drivers/net/dsa/rtl838x_phy.c create mode 100644 target/linux/rtl838x/files-5.4/drivers/net/dsa/rtl838x_sw.c create mode 100644 target/linux/rtl838x/files-5.4/drivers/net/ethernet/rtl838x_eth.c create mode 100644 target/linux/rtl838x/files-5.4/drivers/net/ethernet/rtl838x_eth.h create mode 100644 target/linux/rtl838x/image/Makefile create mode 100644 target/linux/rtl838x/patches-5.4/300-mips-add-rtl838x-platform.patch create mode 100644 target/linux/rtl838x/patches-5.4/301-gpio-add-rtl838x-driver.patch create mode 100644 target/linux/rtl838x/patches-5.4/400-mtd-add-rtl838x-spi-flash-driver.patch create mode 100644 target/linux/rtl838x/patches-5.4/700-net-dsa-add-support-for-rtl838x-switch.patch create mode 100644 target/linux/rtl838x/patches-5.4/701-net-dsa-add-rtl838x-support-for-tag-trailer.patch create mode 100644 target/linux/rtl838x/patches-5.4/702-net-dsa-increase-dsa-max-ports-for-rtl838x.patch create mode 100644 target/linux/rtl838x/patches-5.4/702-net-ethernet-add-support-for-rtl838x-ethernet.patch create mode 100644 target/linux/rtl838x/patches-5.4/703-include-linux-add-phy-ops-for-rtl838x.patch create mode 100644 target/linux/rtl838x/patches-5.4/704-drivers-net-phy-eee-support-for-rtl838x.patch create mode 100644 target/linux/rtl838x/profiles/00-default.mk diff --git a/target/linux/rtl838x/Makefile b/target/linux/rtl838x/Makefile new file mode 100644 index 0000000000..764b94ae38 --- /dev/null +++ b/target/linux/rtl838x/Makefile @@ -0,0 +1,22 @@ +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk + +ARCH:=mips +CPU_TYPE:=4kec +BOARD:=rtl838x +BOARDNAME:=Realtek MIPS +FEATURES:=ramdisk squashfs + +KERNEL_PATCHVER:=5.4 + +define Target/Description + Build firmware images for Realtek RTL838x based boards. +endef + +include $(INCLUDE_DIR)/target.mk + +DEFAULT_PACKAGES += swconfig uboot-envtools ethtool kmod-gpio-button-hotplug + +$(eval $(call BuildTarget)) diff --git a/target/linux/rtl838x/base-files/etc/board.d/01_leds b/target/linux/rtl838x/base-files/etc/board.d/01_leds new file mode 100755 index 0000000000..7991b832f6 --- /dev/null +++ b/target/linux/rtl838x/base-files/etc/board.d/01_leds @@ -0,0 +1,15 @@ +#!/bin/sh + +. /lib/functions/uci-defaults.sh + +board=$(board_name) +boardname="${board##*,}" + +board_config_update + +case $board in +esac + +board_config_flush + +exit 0 diff --git a/target/linux/rtl838x/base-files/etc/board.d/02_network b/target/linux/rtl838x/base-files/etc/board.d/02_network new file mode 100755 index 0000000000..a79869d8c3 --- /dev/null +++ b/target/linux/rtl838x/base-files/etc/board.d/02_network @@ -0,0 +1,87 @@ +#!/bin/sh + +. /lib/functions.sh +. /lib/functions/uci-defaults.sh +. /lib/functions/system.sh + +rtl838x_setup_switch() +{ + local switchid net portid master device lan_role lan_list + + json_select_object switch + # Find slave ports + for net in $(ls -d /sys/class/net/*); do + switchid=$(cat $net/phys_switch_id 2>/dev/null) + [ -z "$switchid" ] && continue + device=$(basename $net) + portid=$(cat $net/phys_port_name) + lan_role="$lan_role ${portid##p}" + lan_list="$lan_list $device" + json_select_object "switch$((switchid))" + json_add_boolean enable 1 + json_add_boolean reset 0 + json_add_boolean dsa 1 + json_select_array ports + json_add_object + json_add_int num "${portid##p}" + json_add_string role "lan" + json_add_string device "$device" + json_close_object + json_select .. + json_select .. + done + # Add switch master device + for net in $(ls -d /sys/class/net/*/dsa); do + master=$(dirname $net) + device=$(basename $master) + portid=$(cat $master/phys_port_name) + lan_role="$lan_role ${portid##p}" + json_select_object "switch$((switchid))" + json_select_array ports + json_add_object + json_add_int num "${portid##p}" + json_add_string device "$device" + json_add_boolean need_tag 0 + json_add_boolean want_untag 0 + json_add_boolean master 1 + json_close_object + json_select .. + json_select_array roles + json_add_object + json_add_string role "lan" + lan_role=$(echo $lan_role | xargs -n1 | sort -n | xargs) + json_add_string ports "$lan_role" + json_close_object + json_select .. + json_select .. + done + json_select .. + lan_list=$(echo $lan_list | xargs -n1 | sort -V | xargs) + ucidef_set_interface_lan "$lan_list" +} + +rtl838x_setup_macs() +{ + local board="$1" + local lan_mac + local wan_mac + local label_mac + + case $board in + allnet,all-sg8208m) + lan_mac=$(mtd_get_mac_ascii u-boot-env ethaddr) + label_mac=$lan_mac + esac + + [ -n "$lan_mac" ] && ucidef_set_interface_macaddr "lan" $lan_mac + [ -n "$wan_mac" ] && ucidef_set_interface_macaddr "wan" $wan_mac + [ -n "$label_mac" ] && ucidef_set_label_macaddr $label_mac +} + +board_config_update +board=$(board_name) +rtl838x_setup_switch +rtl838x_setup_macs $board +board_config_flush + +exit 0 diff --git a/target/linux/rtl838x/base-files/etc/inittab b/target/linux/rtl838x/base-files/etc/inittab new file mode 100644 index 0000000000..9820e7144b --- /dev/null +++ b/target/linux/rtl838x/base-files/etc/inittab @@ -0,0 +1,3 @@ +::sysinit:/etc/init.d/rcS S boot +::shutdown:/etc/init.d/rcS K shutdown +::askconsole:/usr/libexec/login.sh diff --git a/target/linux/rtl838x/base-files/lib/firmware/rtl838x_phy/rtl838x_8214fc.fw b/target/linux/rtl838x/base-files/lib/firmware/rtl838x_phy/rtl838x_8214fc.fw new file mode 100644 index 0000000000..035c02d804 Binary files /dev/null and b/target/linux/rtl838x/base-files/lib/firmware/rtl838x_phy/rtl838x_8214fc.fw differ diff --git a/target/linux/rtl838x/base-files/lib/firmware/rtl838x_phy/rtl838x_8218b.fw b/target/linux/rtl838x/base-files/lib/firmware/rtl838x_phy/rtl838x_8218b.fw new file mode 100644 index 0000000000..a907849fb9 Binary files /dev/null and b/target/linux/rtl838x/base-files/lib/firmware/rtl838x_phy/rtl838x_8218b.fw differ diff --git a/target/linux/rtl838x/base-files/lib/firmware/rtl838x_phy/rtl838x_8380.fw b/target/linux/rtl838x/base-files/lib/firmware/rtl838x_phy/rtl838x_8380.fw new file mode 100644 index 0000000000..ef84c71753 Binary files /dev/null and b/target/linux/rtl838x/base-files/lib/firmware/rtl838x_phy/rtl838x_8380.fw differ diff --git a/target/linux/rtl838x/base-files/lib/upgrade/platform.sh b/target/linux/rtl838x/base-files/lib/upgrade/platform.sh new file mode 100644 index 0000000000..927aadbe31 --- /dev/null +++ b/target/linux/rtl838x/base-files/lib/upgrade/platform.sh @@ -0,0 +1,19 @@ +PART_NAME=firmware +REQUIRE_IMAGE_METADATA=1 + +RAMFS_COPY_BIN='fw_printenv fw_setenv' +RAMFS_COPY_DATA='/etc/fw_env.config /var/lock/fw_printenv.lock' + +platform_check_image() { + return 0 +} + +platform_do_upgrade() { + local board=$(board_name) + + case "$board" in + *) + default_do_upgrade "$1" + ;; + esac +} diff --git a/target/linux/rtl838x/config-5.4 b/target/linux/rtl838x/config-5.4 new file mode 100644 index 0000000000..4cd2fddba3 --- /dev/null +++ b/target/linux/rtl838x/config-5.4 @@ -0,0 +1,226 @@ +CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_ARCH_CLOCKSOURCE_DATA=y +CONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN=y +CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y +CONFIG_ARCH_HAS_DMA_WRITE_COMBINE=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_ARCH_HAS_RESET_CONTROLLER=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y +CONFIG_ARCH_HAS_UNCACHED_SEGMENT=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_MMAP_RND_BITS_MAX=15 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_ARCH_USE_MEMREMAP_PROT=y +CONFIG_ARCH_USE_QUEUED_RWLOCKS=y +CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y +CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +CONFIG_CEVT_R4K=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_COMMON_CLK=y +# CONFIG_COMMON_CLK_BOSTON is not set +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15 +CONFIG_CPU_BIG_ENDIAN=y +CONFIG_CPU_GENERIC_DUMP_TLB=y +CONFIG_CPU_HAS_LOAD_STORE_LR=y +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_CPU_HAS_RIXI=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_MIPS32=y +# CONFIG_CPU_MIPS32_R1 is not set +CONFIG_CPU_MIPS32_R2=y +CONFIG_CPU_MIPSR2=y +CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y +CONFIG_CPU_R4K_CACHE_TLB=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_CPU_SUPPORTS_MSA=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CSRC_R4K=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_SECTION_MISMATCH=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NONCOHERENT_CACHE_SYNC=y +CONFIG_DTC=y +CONFIG_EARLY_PRINTK=y +CONFIG_EFI_EARLYCON=y +CONFIG_ETHERNET_PACKET_MANGLE=y +# CONFIG_FIXED_PHY is not set +# CONFIG_FONT_SUPPORT is not set +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IOMAP=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_IPI=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_LIB_ASHLDI3=y +CONFIG_GENERIC_LIB_ASHRDI3=y +CONFIG_GENERIC_LIB_CMPDI2=y +CONFIG_GENERIC_LIB_LSHRDI3=y +CONFIG_GENERIC_LIB_UCMPDI2=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDWARE_WATCHPOINTS=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAVE_ARCH_COMPILER_H=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_ASM_MODVERSIONS=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_COPY_THREAD_TLS=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DEBUG_STACKOVERFLOW=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FAST_GUP=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_GENERIC_VDSO=y +CONFIG_HAVE_IDE=y +CONFIG_HAVE_IOREMAP_PROT=y +CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_KVM=y +CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y +CONFIG_HAVE_MEMBLOCK_NODE_MAP=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_RSEQ=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_HZ_PERIODIC=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_MIPS_CPU=y +CONFIG_IRQ_WORK=y +CONFIG_LEDS_GPIO=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +CONFIG_LIBFDT=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MEMFD_CREATE=y +CONFIG_MFD_SYSCON=y +CONFIG_MIGRATION=y +CONFIG_MIPS=y +CONFIG_MIPS_ASID_BITS=8 +CONFIG_MIPS_ASID_SHIFT=0 +CONFIG_MIPS_CLOCK_VSYSCALL=y +# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set +# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set +CONFIG_MIPS_CMDLINE_FROM_DTB=y +# CONFIG_MIPS_ELF_APPENDED_DTB is not set +CONFIG_MIPS_L1_CACHE_SHIFT=5 +# CONFIG_MIPS_MT_SMP is not set +# CONFIG_MIPS_NO_APPENDED_DTB is not set +CONFIG_MIPS_RAW_APPENDED_DTB=y +CONFIG_MIPS_SPRAM=y +# CONFIG_MIPS_VPE_LOADER is not set +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_GEOMETRY=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPLIT_BRNIMAGE_FW=y +CONFIG_MTD_SPLIT_EVA_FW=y +CONFIG_MTD_SPLIT_FIRMWARE=y +CONFIG_MTD_SPLIT_TPLINK_FW=y +CONFIG_MTD_SPLIT_UIMAGE_FW=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_PER_CPU_KM=y +CONFIG_NET_DEVLINK=y +CONFIG_NET_DSA=y +CONFIG_NET_DSA_RTL838X=y +CONFIG_NET_DSA_TAG_TRAILER=y +CONFIG_NET_RTL838X=y +CONFIG_NET_SWITCHDEV=y +CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y +CONFIG_NVMEM=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OF_NET=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_PCI_DRIVERS_LEGACY=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +# CONFIG_PHYLIB is not set +CONFIG_PHYLINK=y +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_SINGLE is not set +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_PSB6970_PHY=y +CONFIG_REGMAP=y +CONFIG_REGMAP_MMIO=y +CONFIG_RESET_CONTROLLER=y +CONFIG_RTL838X=y +CONFIG_GPIO_RTL838X=y +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +CONFIG_SERIAL_8250_NR_UARTS=2 +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SPI=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +CONFIG_SPI_RTL838X=y +CONFIG_SRCU=y +CONFIG_SWAP_IO_SPACE=y +CONFIG_SWCONFIG=y +CONFIG_SWPHY=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_SYS_HAS_CPU_MIPS32_R2=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_MIPS16=y +CONFIG_SYS_SUPPORTS_MULTITHREADING=y +CONFIG_SYS_SUPPORTS_VPE_LOADER=y +CONFIG_TARGET_ISA_REV=2 +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TINY_SRCU=y +CONFIG_USE_OF=y +CONFIG_JFFS2_ZLIB=y diff --git a/target/linux/rtl838x/dts/rtl8382_allnet_all-sg8208m.dts b/target/linux/rtl838x/dts/rtl8382_allnet_all-sg8208m.dts new file mode 100644 index 0000000000..09d5aff0fe --- /dev/null +++ b/target/linux/rtl838x/dts/rtl8382_allnet_all-sg8208m.dts @@ -0,0 +1,221 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/dts-v1/; + +#include "rtl838x.dtsi" + +#include +#include + +/ { + compatible = "allnet,all-sg8208m", "realtek,rtl838x-soc"; + model = "ALLNET ALL-SG8208M"; + + aliases { + led-boot = &led_sys; + led-failsafe = &led_sys; + led-running = &led_sys; + led-upgrade = &led_sys; + }; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + keys { + compatible = "gpio-keys-polled"; + poll-interval = <20>; + + reset { + label = "reset"; + gpios = <&gpio0 67 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_sys: sys { + label = "all-sg8208m:green:sys"; + gpios = <&gpio0 47 GPIO_ACTIVE_HIGH>; + }; + // GPIO 25: power on/off all port leds + }; +}; + +&gpio0 { + indirect-access-bus-id = <0>; +}; + +&spi0 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <10000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x80000>; + read-only; + }; + + partition@80000 { + label = "u-boot-env"; + reg = <0x80000 0x10000>; + read-only; + }; + + partition@90000 { + label = "u-boot-env2"; + reg = <0x90000 0x10000>; + read-only; + }; + + partition@a0000 { + label = "jffs"; + reg = <0xa0000 0x100000>; + }; + + partition@1a0000 { + label = "jffs2"; + reg = <0x1a0000 0x100000>; + }; + + partition@2a0000 { + label = "firmware"; + reg = <0x2a0000 0xd60000>; + compatible = "allnet,uimage"; + }; + }; + }; +}; + +ðernet0 { + mdio: mdio-bus { + compatible = "realtek,rtl838x-mdio"; + regmap = <ðernet0>; + #address-cells = <1>; + #size-cells = <0>; + + /* Internal phy */ + phy8: ethernet-phy@8 { + reg = <8>; + compatible = "ethernet-phy-ieee802.3-c22"; + }; + + phy9: ethernet-phy@9 { + reg = <9>; + compatible = "ethernet-phy-ieee802.3-c22"; + }; + + phy10: ethernet-phy@10 { + reg = <10>; + compatible = "ethernet-phy-ieee802.3-c22"; + }; + + phy11: ethernet-phy@11 { + reg = <11>; + compatible = "ethernet-phy-ieee802.3-c22"; + }; + + phy12: ethernet-phy@12 { + reg = <12>; + compatible = "ethernet-phy-ieee802.3-c22"; + }; + + phy13: ethernet-phy@13 { + reg = <13>; + compatible = "ethernet-phy-ieee802.3-c22"; + }; + + phy14: ethernet-phy@14 { + reg = <14>; + compatible = "ethernet-phy-ieee802.3-c22"; + }; + + phy15: ethernet-phy@15 { + reg = <15>; + compatible = "ethernet-phy-ieee802.3-c22"; + }; + }; +}; + +&switch0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <8>; + label = "lan1"; + phy-handle = <&phy8>; + phy-mode = "internal"; + }; + + port@1 { + reg = <9>; + label = "lan2"; + phy-handle = <&phy9>; + phy-mode = "internal"; + }; + + port@2 { + reg = <10>; + label = "lan3"; + phy-handle = <&phy10>; + phy-mode = "internal"; + }; + + port@3 { + reg = <11>; + label = "lan4"; + phy-handle = <&phy11>; + phy-mode = "internal"; + }; + + port@4 { + reg = <12>; + label = "lan5"; + phy-handle = <&phy12>; + phy-mode = "internal"; + }; + + port@5 { + reg = <13>; + label = "lan6"; + phy-handle = <&phy13>; + phy-mode = "internal"; + }; + + port@6 { + reg = <14>; + label = "lan7"; + phy-handle = <&phy14>; + phy-mode = "internal"; + }; + + port@7 { + reg = <15>; + label = "lan8"; + phy-handle = <&phy15>; + phy-mode = "internal"; + }; + + port@28 { + ethernet = <ðernet0>; + reg = <28>; + phy-mode = "internal"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; +}; diff --git a/target/linux/rtl838x/dts/rtl838x.dtsi b/target/linux/rtl838x/dts/rtl838x.dtsi new file mode 100644 index 0000000000..63dc9bf1ba --- /dev/null +++ b/target/linux/rtl838x/dts/rtl838x.dtsi @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +/ { + #address-cells = <1>; + #size-cells = <1>; + + compatible = "realtek,rtl838x-soc"; + reg = <0xbb000000 0xa000>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + frequency = <500000000>; + + cpu@0 { + compatible = "mips,mips4KEc"; + reg = <0>; + }; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x8000000>; + }; + + chosen { + bootargs = "console=ttyS0,38400"; + }; + + cpuintc: cpuintc { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + compatible = "rtl838x,icu"; + reg = <0xb8003000 0x20>; + }; + + spi0: spi@b8001200 { + status = "okay"; + + compatible = "realtek,rtl838x-nor"; + reg = <0xb8001200 0x100>; + + #address-cells = <1>; + #size-cells = <0>; + }; + + uart0: uart@b8002000 { + status = "disabled"; + + compatible = "ns16550a"; + reg = <0xb8002000 0x100>; + + clock-frequency = <200000000>; + interrupts = <31>; + + reg-io-width = <1>; + reg-shift = <2>; + fifo-size = <1>; + no-loopback-test; + }; + + uart1: uart@b8002100 { + status = "okay"; + + compatible = "ns16550a"; + reg = <0xb8002100 0x100>; + + clock-frequency = <200000000>; + + interrupt-parent = <&cpuintc>; + interrupts = <30>; + + reg-io-width = <1>; + reg-shift = <2>; + fifo-size = <1>; + no-loopback-test; + }; + + gpio0: gpio-controller@b8003500 { + compatible = "realtek,rtl838x-gpio"; + reg = <0xb8003500 0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&cpuintc>; + interrupts = <23>; + }; + + ethernet0: ethernet@bb00a300 { + status = "okay"; + + compatible = "realtek,rtl838x-eth"; + reg = <0xbb00a300 0x100>; + interrupt-parent = <&cpuintc>; + interrupts = <24>; + #interrupt-cells = <1>; + phy-mode = "internal"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + switch0: switch@bb000000 { + status = "okay"; + + compatible = "realtek,rtl838x-switch"; + }; +}; diff --git a/target/linux/rtl838x/files-5.4/arch/mips/include/asm/mach-rtl838x/ioremap.h b/target/linux/rtl838x/files-5.4/arch/mips/include/asm/mach-rtl838x/ioremap.h new file mode 100644 index 0000000000..e7a5bfaffc --- /dev/null +++ b/target/linux/rtl838x/files-5.4/arch/mips/include/asm/mach-rtl838x/ioremap.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef RTL838X_IOREMAP_H_ +#define RTL838X_IOREMAP_H_ + +static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size) +{ + return phys_addr; +} + +static inline int is_rtl838x_internal_registers(phys_addr_t offset) +{ + /* IO-Block */ + if (offset >= 0xb8000000 && offset < 0xb9000000) + return 1; + /* Switch block */ + if (offset >= 0xbb000000 && offset < 0xbc000000) + return 1; + return 0; +} + +static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size, + unsigned long flags) +{ + if (is_rtl838x_internal_registers(offset)) + return (void __iomem *)offset; + return NULL; +} + +static inline int plat_iounmap(const volatile void __iomem *addr) +{ + return is_rtl838x_internal_registers((unsigned long)addr); +} + +#endif diff --git a/target/linux/rtl838x/files-5.4/arch/mips/include/asm/mach-rtl838x/irq.h b/target/linux/rtl838x/files-5.4/arch/mips/include/asm/mach-rtl838x/irq.h new file mode 100644 index 0000000000..e821111c5d --- /dev/null +++ b/target/linux/rtl838x/files-5.4/arch/mips/include/asm/mach-rtl838x/irq.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef __ASM_MACH_RTL838X_IRQ_H +#define __ASM_MACH_RTL838X_IRQ_H + +#define MIPS_CPU_IRQ_BASE 0 +#define NR_IRQS 64 + +#include_next + +#endif /* __ASM_MACH_ATH79_IRQ_H */ diff --git a/target/linux/rtl838x/files-5.4/arch/mips/include/asm/mach-rtl838x/mach-rtl838x.h b/target/linux/rtl838x/files-5.4/arch/mips/include/asm/mach-rtl838x/mach-rtl838x.h new file mode 100644 index 0000000000..cece36635c --- /dev/null +++ b/target/linux/rtl838x/files-5.4/arch/mips/include/asm/mach-rtl838x/mach-rtl838x.h @@ -0,0 +1,428 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com) + * Copyright (C) 2020 B. Koblitz + */ +#ifndef _MACH_RTL838X_H_ +#define _MACH_RTL838X_H_ + +/* + * Register access macros + */ + +#define RTL838X_SW_BASE ((volatile void *) 0xBB000000) + +#define rtl838x_r32(reg) __raw_readl(reg) +#define rtl838x_w32(val, reg) __raw_writel(val, reg) +#define rtl838x_w32_mask(clear, set, reg) rtl838x_w32((rtl838x_r32(reg) & ~(clear)) | (set), reg) + +#define sw_r32(reg) __raw_readl(RTL838X_SW_BASE + reg) +#define sw_w32(val, reg) __raw_writel(val, RTL838X_SW_BASE + reg) +#define sw_w32_mask(clear, set, reg) \ + sw_w32((sw_r32(reg) & ~(clear)) | (set), reg) + +#define sw_r64(reg) ((((u64)__raw_readl(RTL838X_SW_BASE + reg)) << 32) | \ + __raw_readl(RTL838X_SW_BASE + reg + 4)) + +#define sw_w64(val, reg) do { \ + __raw_writel((u32)((val) >> 32), RTL838X_SW_BASE + reg); \ + __raw_writel((u32)((val) & 0xffffffff), \ + RTL838X_SW_BASE + reg + 4); \ + } while (0) + +/* + * SPRAM + */ +#define RTL838X_ISPRAM_BASE 0x0 +#define RTL838X_DSPRAM_BASE 0x0 + +/* + * IRQ Controller + */ +#define RTL838X_IRQ_CPU_BASE 0 +#define RTL838X_IRQ_CPU_NUM 8 +#define RTL838X_IRQ_ICTL_BASE (RTL838X_IRQ_CPU_BASE + RTL838X_IRQ_CPU_NUM) +#define RTL838X_IRQ_ICTL_NUM 32 + +/* + * MIPS32R2 counter + */ +#define RTL838X_COMPARE_IRQ (RTL838X_IRQ_CPU_BASE + 7) + +/* + * ICTL + * Base address 0xb8003000UL + */ +#define RTL838X_ICTL1_IRQ (RTL838X_IRQ_CPU_BASE + 2) +#define RTL838X_ICTL2_IRQ (RTL838X_IRQ_CPU_BASE + 3) +#define RTL838X_ICTL3_IRQ (RTL838X_IRQ_CPU_BASE + 4) +#define RTL838X_ICTL4_IRQ (RTL838X_IRQ_CPU_BASE + 5) +#define RTL838X_ICTL5_IRQ (RTL838X_IRQ_CPU_BASE + 6) + +#define GIMR (0x00) +#define UART0_IE (1 << 31) +#define UART1_IE (1 << 30) +#define TC0_IE (1 << 29) +#define TC1_IE (1 << 28) +#define OCPTO_IE (1 << 27) +#define HLXTO_IE (1 << 26) +#define SLXTO_IE (1 << 25) +#define NIC_IE (1 << 24) +#define GPIO_ABCD_IE (1 << 23) +#define GPIO_EFGH_IE (1 << 22) +#define RTC_IE (1 << 21) +#define WDT_IP1_IE (1 << 19) +#define WDT_IP2_IE (1 << 18) + +#define GISR (0x04) +#define UART0_IP (1 << 31) +#define UART1_IP (1 << 30) +#define TC0_IP (1 << 29) +#define TC1_IP (1 << 28) +#define OCPTO_IP (1 << 27) +#define HLXTO_IP (1 << 26) +#define SLXTO_IP (1 << 25) +#define NIC_IP (1 << 24) +#define GPIO_ABCD_IP (1 << 23) +#define GPIO_EFGH_IP (1 << 22) +#define RTC_IP (1 << 21) +#define WDT_IP1_IP (1 << 19) +#define WDT_IP2_IP (1 << 18) + +#define IRR0 (0x08) +#define IRR0_SETTING ((UART0_RS << 28) | \ + (UART1_RS << 24) | \ + (TC0_RS << 20) | \ + (TC1_RS << 16) | \ + (OCPTO_RS << 12) | \ + (HLXTO_RS << 8) | \ + (SLXTO_RS << 4) | \ + (NIC_RS << 0) \ + ) + +#define IRR1 (0x0c) + +#define IRR1_SETTING ((GPIO_ABCD_RS << 28) | \ + (GPIO_EFGH_RS << 24) | \ + (RTC_RS << 20) | \ + (SWCORE_RS << 16) \ + ) + +#define IRR2 (0x10) +#define IRR2_SETTING 0 + +#define IRR3 (0x14) +#define IRR3_SETTING 0 + +/* Interrupt Routing Selection */ +#define UART0_RS 2 +#define UART1_RS 1 +#define TC0_RS 5 +#define TC1_RS 1 +#define OCPTO_RS 1 +#define HLXTO_RS 1 +#define SLXTO_RS 1 +#define NIC_RS 4 +#define GPIO_ABCD_RS 4 +#define GPIO_EFGH_RS 4 +#define RTC_RS 4 +#define SWCORE_RS 3 +#define WDT_IP1_RS 4 +#define WDT_IP2_RS 5 + +/* Interrupt IRQ Assignments */ +#define UART0_IRQ 31 +#define UART1_IRQ 30 +#define TC0_IRQ 29 +#define TC1_IRQ 28 +#define OCPTO_IRQ 27 +#define HLXTO_IRQ 26 +#define SLXTO_IRQ 25 +#define NIC_IRQ 24 +#define GPIO_ABCD_IRQ 23 +#define GPIO_EFGH_IRQ 22 +#define RTC_IRQ 21 +#define SWCORE_IRQ 20 +#define WDT_IP1_IRQ 19 +#define WDT_IP2_IRQ 18 + +#define SYSTEM_FREQ 200000000 +#define RTL838X_UART0_BASE ((volatile void *)(0xb8002000UL)) +#define RTL838X_UART0_BAUD 38400 /* ex. 19200 or 38400 or 57600 or 115200 */ +#define RTL838X_UART0_FREQ (SYSTEM_FREQ - RTL838X_UART0_BAUD * 24) +#define RTL838X_UART0_MAPBASE 0x18002000UL +#define RTL838X_UART0_MAPSIZE 0x100 +#define RTL838X_UART0_IRQ UART0_IRQ + +#define RTL838X_UART1_BASE ((volatile void *)(0xb8002100UL)) +#define RTL838X_UART1_BAUD 38400 /* ex. 19200 or 38400 or 57600 or 115200 */ +#define RTL838X_UART1_FREQ (SYSTEM_FREQ - RTL838X_UART1_BAUD * 24) +#define RTL838X_UART1_MAPBASE 0x18002100UL +#define RTL838X_UART1_MAPSIZE 0x100 +#define RTL838X_UART1_IRQ UART1_IRQ + +#define UART0_RBR (RTL838X_UART0_BASE + 0x000) +#define UART0_THR (RTL838X_UART0_BASE + 0x000) +#define UART0_DLL (RTL838X_UART0_BASE + 0x000) +#define UART0_IER (RTL838X_UART0_BASE + 0x004) +#define UART0_DLM (RTL838X_UART0_BASE + 0x004) +#define UART0_IIR (RTL838X_UART0_BASE + 0x008) +#define UART0_FCR (RTL838X_UART0_BASE + 0x008) +#define UART0_LCR (RTL838X_UART0_BASE + 0x00C) +#define UART0_MCR (RTL838X_UART0_BASE + 0x010) +#define UART0_LSR (RTL838X_UART0_BASE + 0x014) + +#define UART1_RBR (RTL838X_UART1_BASE + 0x000) +#define UART1_THR (RTL838X_UART1_BASE + 0x000) +#define UART1_DLL (RTL838X_UART1_BASE + 0x000) +#define UART1_IER (RTL838X_UART1_BASE + 0x004) +#define UART1_DLM (RTL838X_UART1_BASE + 0x004) +#define UART1_IIR (RTL838X_UART1_BASE + 0x008) +#define UART1_FCR (RTL838X_UART1_BASE + 0x008) + #define FCR_EN 0x01 + #define FCR_RXRST 0x02 + #define XRST 0x02 + #define FCR_TXRST 0x04 + #define TXRST 0x04 + #define FCR_DMA 0x08 + #define FCR_RTRG 0xC0 + #define CHAR_TRIGGER_01 0x00 + #define CHAR_TRIGGER_04 0x40 + #define CHAR_TRIGGER_08 0x80 + #define CHAR_TRIGGER_14 0xC0 +#define UART1_LCR (RTL838X_UART1_BASE + 0x00C) + #define LCR_WLN 0x03 + #define CHAR_LEN_5 0x00 + #define CHAR_LEN_6 0x01 + #define CHAR_LEN_7 0x02 + #define CHAR_LEN_8 0x03 + #define LCR_STB 0x04 + #define ONE_STOP 0x00 + #define TWO_STOP 0x04 + #define LCR_PEN 0x08 + #define PARITY_ENABLE 0x01 + #define PARITY_DISABLE 0x00 + #define LCR_EPS 0x30 + #define PARITY_ODD 0x00 + #define PARITY_EVEN 0x10 + #define PARITY_MARK 0x20 + #define PARITY_SPACE 0x30 + #define LCR_BRK 0x40 + #define LCR_DLAB 0x80 + #define DLAB 0x80 +#define UART1_MCR (RTL838X_UART1_BASE + 0x010) +#define UART1_LSR (RTL838X_UART1_BASE + 0x014) + #define LSR_DR 0x01 + #define RxCHAR_AVAIL 0x01 + #define LSR_OE 0x02 + #define LSR_PE 0x04 + #define LSR_FE 0x08 + #define LSR_BI 0x10 + #define LSR_THRE 0x20 + #define TxCHAR_AVAIL 0x00 + #define TxCHAR_EMPTY 0x20 + #define LSR_TEMT 0x40 + #define LSR_RFE 0x80 + +/* + * Timer/counter for 8390/80/28 TC & MP chip + */ +#define RTL838X_TIMER0_BASE ((volatile void *)(0xb8003100UL)) +#define RTL838X_TIMER0_IRQ RTL838X_TC0_EXT_IRQ + +#define RTL8390TC_TC1DATA (RTL838X_TIMER0_BASE + 0x04) +#define RTL8390TC_TCD_OFFSET 8 +#define RTL8390TC_TC0CNT (RTL838X_TIMER0_BASE + 0x08) +#define RTL8390TC_TC1CNT (RTL838X_TIMER0_BASE + 0x0C) +#define RTL8390TC_TCCNR (RTL838X_TIMER0_BASE + 0x10) +#define RTL8390TC_TC0EN (1 << 31) +#define RTL8390TC_TC0MODE_TIMER (1 << 30) +#define RTL8390TC_TC1EN (1 << 29) +#define RTL8390TC_TC1MODE_TIMER (1 << 28) +#define RTL8390TC_TCIR (RTL838X_TIMER0_BASE + 0x14) +#define RTL8390TC_TC0IE (1 << 31) +#define RTL8390TC_TC1IE (1 << 30) +#define RTL8390TC_TC0IP (1 << 29) +#define RTL8390TC_TC1IP (1 << 28) +#define RTL8390TC_CDBR (RTL838X_TIMER0_BASE + 0x18) +#define RTL8390TC_DIVF_OFFSET 16 +#define RTL8390TC_WDTCNR (RTL838X_TIMER0_BASE + 0x1C) + +#define RTL8390MP_TC1DATA (RTL838X_TIMER0_BASE + 0x10) +#define RTL8390MP_TC0CNT (RTL838X_TIMER0_BASE + 0x04) +#define RTL8390MP_TC1CNT (RTL838X_TIMER0_BASE + 0x14) +#define RTL8390MP_TC0CTL (RTL838X_TIMER0_BASE + 0x08) +#define RTL8390MP_TC1CTL (RTL838X_TIMER0_BASE + 0x18) +#define RTL8390MP_TCEN (1 << 28) +#define RTL8390MP_TCMODE_TIMER (1 << 24) +#define RTL8390MP_TCDIV_FACTOR (0xFFFF << 0) +#define RTL8390MP_TC0INT (RTL838X_TIMER0_BASE + 0xC) +#define RTL8390MP_TC1INT (RTL838X_TIMER0_BASE + 0x1C) +#define RTL8390MP_TCIE (1 << 20) +#define RTL8390MP_TCIP (1 << 16) +#define RTL8390MP_WDTCNR (RTL838X_TIMER0_BASE + 0x50) + +#define RTL8380MP_TC0DATA (RTL838X_TIMER0_BASE + 0x00) +#define RTL8380MP_TC1DATA (RTL838X_TIMER0_BASE + 0x10) +#define RTL8380MP_TC0CNT (RTL838X_TIMER0_BASE + 0x04) +#define RTL8380MP_TC1CNT (RTL838X_TIMER0_BASE + 0x14) +#define RTL8380MP_TC0CTL (RTL838X_TIMER0_BASE + 0x08) +#define RTL8380MP_TC1CTL (RTL838X_TIMER0_BASE + 0x18) +#define RTL8380MP_TCEN (1 << 28) +#define RTL8380MP_TCMODE_TIMER (1 << 24) +#define RTL8380MP_TCDIV_FACTOR (0xFFFF << 0) +#define RTL8380MP_TC0INT (RTL838X_TIMER0_BASE + 0xC) +#define RTL8380MP_TC1INT (RTL838X_TIMER0_BASE + 0x1C) +#define RTL8380MP_TCIE (1 << 20) +#define RTL8380MP_TCIP (1 << 16) +#define RTL8380MP_WDTCNR (RTL838X_TIMER0_BASE + 0x50) + +#define DIVISOR_RTL8390 55 +#define DIVISOR_RTL8380 2500 +#define DIVISOR_MAX 16834 + +/* + * Memory Controller + */ +#define MC_MCR 0xB8001000 +#define MC_MCR_VAL 0x00000000 + +#define MC_DCR 0xB8001004 +#define MC_DCR0_VAL 0x54480000 + +#define MC_DTCR 0xB8001008 +#define MC_DTCR_VAL 0xFFFF05C0 + +/* + * GPIO + */ +#define GPIO_CTRL_REG_BASE ((volatile void *) 0xb8003500) +#define RTL838X_GPIO_PABC_CNR (GPIO_CTRL_REG_BASE + 0x0) +#define RTL838X_GPIO_PABC_TYPE (GPIO_CTRL_REG_BASE + 0x04) +#define RTL838X_GPIO_PABC_DIR (GPIO_CTRL_REG_BASE + 0x8) +#define RTL838X_GPIO_PABC_DATA (GPIO_CTRL_REG_BASE + 0xc) +#define RTL838X_GPIO_PABC_ISR (GPIO_CTRL_REG_BASE + 0x10) +#define RTL838X_GPIO_PAB_IMR (GPIO_CTRL_REG_BASE + 0x14) +#define RTL838X_GPIO_PC_IMR (GPIO_CTRL_REG_BASE + 0x18) + +#define RTL838X_MODEL_NAME_INFO (0x00D4) +#define RTL839X_MODEL_NAME_INFO (0x0FF0) +#define RTL838X_LED_GLB_CTRL (0xA000) +#define RTL839X_LED_GLB_CTRL (0x00E4) +#define RTL838X_EXT_GPIO_DIR_0 (0xA08C) +#define RTL838X_EXT_GPIO_DIR_1 (0xA090) +#define RTL838X_EXT_GPIO_DATA_0 (0xA094) +#define RTL838X_EXT_GPIO_DATA_1 (0xA098) +#define RTL838X_EXT_GPIO_INDRT_ACCESS (0xA09C) +#define RTL838X_EXTRA_GPIO_CTRL (0xA0E0) +#define RTL838X_EXTRA_GPIO_DIR_0 (0xA0E4) +#define RTL838X_EXTRA_GPIO_DIR_1 (0xA0E8) +#define RTL838X_EXTRA_GPIO_DATA_0 (0xA0EC) +#define RTL838X_EXTRA_GPIO_DATA_1 (0xA0F0) +#define RTL838X_DMY_REG5 (0x0144) +#define RTL838X_EXTRA_GPIO_CTRL (0xA0E0) + +#define RTL838X_GMII_INTF_SEL (0x1000) +#define RTL838X_IO_DRIVING_ABILITY_CTRL (0x1010) + +#define RTL838X_GPIO_A7 31 +#define RTL838X_GPIO_A6 30 +#define RTL838X_GPIO_A5 29 +#define RTL838X_GPIO_A4 28 +#define RTL838X_GPIO_A3 27 +#define RTL838X_GPIO_A2 26 +#define RTL838X_GPIO_A1 25 +#define RTL838X_GPIO_A0 24 +#define RTL838X_GPIO_B7 23 +#define RTL838X_GPIO_B6 22 +#define RTL838X_GPIO_B5 21 +#define RTL838X_GPIO_B4 20 +#define RTL838X_GPIO_B3 19 +#define RTL838X_GPIO_B2 18 +#define RTL838X_GPIO_B1 17 +#define RTL838X_GPIO_B0 16 +#define RTL838X_GPIO_C7 15 +#define RTL838X_GPIO_C6 14 +#define RTL838X_GPIO_C5 13 +#define RTL838X_GPIO_C4 12 +#define RTL838X_GPIO_C3 11 +#define RTL838X_GPIO_C2 10 +#define RTL838X_GPIO_C1 9 +#define RTL838X_GPIO_C0 8 + +#define RTL838X_INT_RW_CTRL (0x0058) +#define RTL838X_EXT_VERSION (0x00D0) +#define RTL838X_PLL_CML_CTRL (0x0FF8) +#define RTL838X_STRAP_DBG (0x100C) + +/* + * Reset + */ +#define RGCR (0x1E70) +#define RTL839X_RST_GLB_CTRL (0x0014) +#define RTL838X_RST_GLB_CTRL_1 (0x0040) + +/* LED control by switch */ +#define RTL838X_LED_MODE_SEL (0x1004) +#define RTL838X_LED_MODE_CTRL (0xA004) +#define RTL838X_LED_P_EN_CTRL (0xA008) + +/* LED control by software */ +#define RTL838X_LED_SW_CTRL (0xA00C) +#define RTL838X_LED0_SW_P_EN_CTRL (0xA010) +#define RTL838X_LED1_SW_P_EN_CTRL (0xA014) +#define RTL838X_LED2_SW_P_EN_CTRL (0xA018) +#define RTL838X_LED_SW_P_CTRL(p) (0xA01C + ((p) << 2)) + +#define RTL839X_MAC_EFUSE_CTRL (0x02ac) + +/* + * MDIO via Realtek's SMI interface + */ +#define RTL838X_SMI_GLB_CTRL (0xa100) +#define RTL838X_SMI_ACCESS_PHY_CTRL_0 (0xa1b8) +#define RTL838X_SMI_ACCESS_PHY_CTRL_1 (0xa1bc) +#define RTL838X_SMI_ACCESS_PHY_CTRL_2 (0xa1c0) +#define RTL838X_SMI_ACCESS_PHY_CTRL_3 (0xa1c4) +#define RTL838X_SMI_PORT0_5_ADDR_CTRL (0xa1c8) +#define RTL838X_SMI_POLL_CTRL (0xa17c) + +#define RTL839X_SMI_GLB_CTRL (0x03f8) +#define RTL839X_SMI_PORT_POLLING_CTRL (0x03fc) +#define RTL839X_PHYREG_ACCESS_CTRL (0x03DC) +#define RTL839X_PHYREG_CTRL (0x03E0) +#define RTL839X_PHYREG_PORT_CTRL(p) (0x03E4 + ((p >> 5) << 2)) +#define RTL839X_PHYREG_DATA_CTRL (0x03F0) + +/* + * Switch interrupts + */ +#define RTL838X_IMR_GLB (0x1100) +#define RTL838X_IMR_PORT_LINK_STS_CHG (0x1104) +#define RTL838X_ISR_GLB_SRC (0x1148) +#define RTL838X_ISR_PORT_LINK_STS_CHG (0x114C) +#define RTL839X_IMR_GLB (0x0064) +#define RTL839X_IMR_PORT_LINK_STS_CHG (0x0068) +#define RTL839X_ISR_GLB_SRC (0x009c) +#define RTL839X_ISR_PORT_LINK_STS_CHG (0x00a0) + +/* Definition of family IDs */ +#define RTL8389_FAMILY_ID (0x8389) +#define RTL8328_FAMILY_ID (0x8328) +#define RTL8390_FAMILY_ID (0x8390) +#define RTL8350_FAMILY_ID (0x8350) +#define RTL8380_FAMILY_ID (0x8380) +#define RTL8330_FAMILY_ID (0x8330) + +struct rtl838x_soc_info { + unsigned char *name; + unsigned int id; + unsigned int family; + unsigned char *compatible; + volatile void *sw_base; + volatile void *icu_base; +}; + +void rtl838x_soc_detect(struct rtl838x_soc_info *i); + +#endif /* _MACH_RTL838X_H_ */ diff --git a/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/Makefile b/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/Makefile new file mode 100644 index 0000000000..fe5e1d96a9 --- /dev/null +++ b/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/Makefile @@ -0,0 +1,5 @@ +# +# Makefile for the rtl838x specific parts of the kernel +# + +obj-y := serial.o setup.o prom.o irq.o diff --git a/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/Platform b/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/Platform new file mode 100644 index 0000000000..4d48932d80 --- /dev/null +++ b/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/Platform @@ -0,0 +1,6 @@ +# +# Realtek RTL838x SoCs +# +platform-$(CONFIG_RTL838X) += rtl838x/ +cflags-$(CONFIG_RTL838X) += -I$(srctree)/arch/mips/include/asm/mach-rtl838x/ +load-$(CONFIG_RTL838X) += 0xffffffff80000000 diff --git a/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/irq.c b/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/irq.c new file mode 100644 index 0000000000..34e90982b2 --- /dev/null +++ b/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/irq.c @@ -0,0 +1,263 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Realtek RTL838X architecture specific IRQ handling + * + * Copyright (C) 2020 B. Koblitz + * based on the original BSP + * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com) + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +extern struct rtl838x_soc_info soc_info; + +#define icu_r32(reg) rtl838x_r32(soc_info.icu_base + reg) +#define icu_w32(val, reg) rtl838x_w32(val, soc_info.icu_base + reg) +#define icu_w32_mask(clear, set, reg) rtl838x_w32_mask(clear, set, soc_info.icu_base + reg) + +static DEFINE_RAW_SPINLOCK(irq_lock); + +extern irqreturn_t c0_compare_interrupt(int irq, void *dev_id); +unsigned int rtl838x_ictl_irq_dispatch1(void); +unsigned int rtl838x_ictl_irq_dispatch2(void); +unsigned int rtl838x_ictl_irq_dispatch3(void); +unsigned int rtl838x_ictl_irq_dispatch4(void); +unsigned int rtl838x_ictl_irq_dispatch5(void); + +static struct irqaction irq_cascade1 = { + .handler = no_action, + .name = "RTL838X IRQ cascade1", +}; + +static struct irqaction irq_cascade2 = { + .handler = no_action, + .name = "RTL838X IRQ cascade2", +}; + +static struct irqaction irq_cascade3 = { + .handler = no_action, + .name = "RTL838X IRQ cascade3", +}; + +static struct irqaction irq_cascade4 = { + .handler = no_action, + .name = "RTL838X IRQ cascade4", +}; + +static struct irqaction irq_cascade5 = { + .handler = no_action, + .name = "RTL838X IRQ cascade5", +}; + +static void rtl838x_ictl_enable_irq(struct irq_data *i) +{ + unsigned long flags; + + raw_spin_lock_irqsave(&irq_lock, flags); + icu_w32_mask(0, 1 << i->irq, GIMR); + raw_spin_unlock_irqrestore(&irq_lock, flags); +} + +static unsigned int rtl838x_ictl_startup_irq(struct irq_data *i) +{ + rtl838x_ictl_enable_irq(i); + return 0; +} + +static void rtl838x_ictl_disable_irq(struct irq_data *i) +{ + unsigned long flags; + + raw_spin_lock_irqsave(&irq_lock, flags); + icu_w32_mask(1 << i->irq, 0, GIMR); + raw_spin_unlock_irqrestore(&irq_lock, flags); +} + +static void rtl838x_ictl_eoi_irq(struct irq_data *i) +{ + unsigned long flags; + + raw_spin_lock_irqsave(&irq_lock, flags); + icu_w32_mask(0, 1 << i->irq, GIMR); + raw_spin_unlock_irqrestore(&irq_lock, flags); +} + +static struct irq_chip rtl838x_ictl_irq = { + .name = "RTL838X", + .irq_startup = rtl838x_ictl_startup_irq, + .irq_shutdown = rtl838x_ictl_disable_irq, + .irq_enable = rtl838x_ictl_enable_irq, + .irq_disable = rtl838x_ictl_disable_irq, + .irq_ack = rtl838x_ictl_disable_irq, + .irq_mask = rtl838x_ictl_disable_irq, + .irq_unmask = rtl838x_ictl_enable_irq, + .irq_eoi = rtl838x_ictl_eoi_irq, +}; + +/* + * RTL8390/80/28 Interrupt Scheme + * + * Source IRQ CPU INT + * -------- ------- ------- + * UART0 31 IP3 + * UART1 30 IP2 + * TIMER0 29 IP6 + * TIMER1 28 IP2 + * OCPTO 27 IP2 + * HLXTO 26 IP2 + * SLXTO 25 IP2 + * NIC 24 IP5 + * GPIO_ABCD 23 IP5 + * SWCORE 20 IP4 + */ + +unsigned int rtl838x_ictl_irq_dispatch1(void) +{ + /* Identify shared IRQ */ + unsigned int extint_ip = icu_r32(GIMR) & icu_r32(GISR); + + if (extint_ip & TC1_IP) + do_IRQ(TC1_IRQ); + else if (extint_ip & UART1_IP) + do_IRQ(UART1_IRQ); + else + spurious_interrupt(); + + return IRQ_HANDLED; +} + +unsigned int rtl838x_ictl_irq_dispatch2(void) +{ + do_IRQ(UART0_IRQ); + return IRQ_HANDLED; +} + +unsigned int rtl838x_ictl_irq_dispatch3(void) +{ + do_IRQ(SWCORE_IRQ); + return IRQ_HANDLED; +} + +unsigned int rtl838x_ictl_irq_dispatch4(void) +{ + /* Identify shared IRQ */ + unsigned int extint_ip = icu_r32(GIMR) & icu_r32(GISR); + + if (extint_ip & NIC_IP) + do_IRQ(NIC_IRQ); + else if (extint_ip & GPIO_ABCD_IP) + do_IRQ(GPIO_ABCD_IRQ); + else if ((extint_ip & GPIO_EFGH_IP) && (soc_info.family == RTL8328_FAMILY_ID)) + do_IRQ(GPIO_EFGH_IRQ); + else + spurious_interrupt(); + + return IRQ_HANDLED; +} + +unsigned int rtl838x_ictl_irq_dispatch5(void) +{ + do_IRQ(TC0_IRQ); + return IRQ_HANDLED; +} + +asmlinkage void plat_irq_dispatch(void) +{ + unsigned int pending; + + pending = read_c0_cause() & read_c0_status() & ST0_IM; + + if (pending & CAUSEF_IP7) + c0_compare_interrupt(7, NULL); + else if (pending & CAUSEF_IP6) + rtl838x_ictl_irq_dispatch5(); + else if (pending & CAUSEF_IP5) + rtl838x_ictl_irq_dispatch4(); + else if (pending & CAUSEF_IP4) + rtl838x_ictl_irq_dispatch3(); + else if (pending & CAUSEF_IP3) + rtl838x_ictl_irq_dispatch2(); + else if (pending & CAUSEF_IP2) + rtl838x_ictl_irq_dispatch1(); + else + spurious_interrupt(); +} + +static void __init rtl838x_ictl_irq_init(unsigned int irq_base) +{ + int i; + + for (i = 0; i < RTL838X_IRQ_ICTL_NUM; i++) + irq_set_chip_and_handler(irq_base + i, &rtl838x_ictl_irq, handle_level_irq); + + setup_irq(RTL838X_ICTL1_IRQ, &irq_cascade1); + setup_irq(RTL838X_ICTL2_IRQ, &irq_cascade2); + setup_irq(RTL838X_ICTL3_IRQ, &irq_cascade3); + setup_irq(RTL838X_ICTL4_IRQ, &irq_cascade4); + setup_irq(RTL838X_ICTL5_IRQ, &irq_cascade5); + + /* Set GIMR, IRR */ + icu_w32(TC0_IE | UART0_IE, GIMR); + icu_w32(IRR0_SETTING, IRR0); + icu_w32(IRR1_SETTING, IRR1); + icu_w32(IRR2_SETTING, IRR2); + icu_w32(IRR3_SETTING, IRR3); +} + +static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) +{ + irq_set_chip_and_handler(hw, &rtl838x_ictl_irq, handle_level_irq); + + return 0; +} + +static const struct irq_domain_ops irq_domain_ops = { + .xlate = irq_domain_xlate_onecell, + .map = intc_map, +}; + +int __init icu_of_init(struct device_node *node, struct device_node *parent) +{ + int i; + struct irq_domain *domain; + struct resource res; + + pr_info("Found Interrupt controller: %s (%s)\n", node->name, node->full_name); + if (of_address_to_resource(node, 0, &res)) { + panic("Failed to get icu memory range"); + } + if (!request_mem_region(res.start, resource_size(&res), res.name)) + pr_err("Failed to request icu memory\n"); + soc_info.icu_base = ioremap(res.start, resource_size(&res)); + pr_info("ICU Memory: %08x\n", (u32)soc_info.icu_base); + + mips_cpu_irq_init(); + + domain = irq_domain_add_simple(node, 32, 0, &irq_domain_ops, NULL); + + /* Setup all external HW irqs */ + for (i = 8; i < 32; i++) + irq_domain_associate(domain, i, i); + + rtl838x_ictl_irq_init(RTL838X_IRQ_ICTL_BASE); + return 0; +} + +void __init arch_init_irq(void) +{ + /* do board-specific irq initialization */ + irqchip_init(); +} + +IRQCHIP_DECLARE(mips_cpu_intc, "rtl838x,icu", icu_of_init); diff --git a/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/prom.c b/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/prom.c new file mode 100644 index 0000000000..604b01806c --- /dev/null +++ b/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/prom.c @@ -0,0 +1,174 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * prom.c + * Early intialization code for the Realtek RTL838X SoC + * + * based on the original BSP by + * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com) + * Copyright (C) 2020 B. Koblitz + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +extern char arcs_cmdline[]; +const void *fdt; +extern const char __appended_dtb; +//extern int __init rtl838x_serial_init(void); + +void prom_console_init(void) +{ + /* UART 16550A is initialized by the bootloader */ +} + +#ifdef CONFIG_EARLY_PRINTK +#define rtl838x_r8(reg) __raw_readb(reg) +#define rtl838x_w8(val, reg) __raw_writeb(val, reg) + +void unregister_prom_console(void) +{ + +} + +void disable_early_printk(void) +{ + +} + +void prom_putchar(char c) +{ + unsigned int retry = 0; + + do { + if (retry++ >= 30000) { + /* Reset Tx FIFO */ + rtl838x_w8(TXRST | CHAR_TRIGGER_14, UART0_FCR); + return; + } + } while ((rtl838x_r8(UART0_LSR) & LSR_THRE) == TxCHAR_AVAIL); + + /* Send Character */ + rtl838x_w8(c, UART0_THR); +} + +char prom_getchar(void) +{ + return '\0'; +} +#endif + +struct rtl838x_soc_info soc_info; + +const char *get_system_type(void) +{ + return soc_info.name; +} + + +void __init prom_free_prom_memory(void) +{ + +} + +void __init device_tree_init(void) +{ + pr_info("%s called\r\n", __func__); + if (!fdt_check_header(&__appended_dtb)) { + fdt = &__appended_dtb; + pr_info("Using appended Device Tree.\n"); + } + initial_boot_params = (void *)fdt; + unflatten_and_copy_device_tree(); +} + +static void __init prom_init_cmdline(void) +{ + int argc = fw_arg0; + char **argv = (char **) KSEG1ADDR(fw_arg1); + int i; + + arcs_cmdline[0] = '\0'; + + for (i = 0; i < argc; i++) { + char *p = (char *) KSEG1ADDR(argv[i]); + + if (CPHYSADDR(p) && *p) { + strlcat(arcs_cmdline, p, sizeof(arcs_cmdline)); + strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline)); + } + } + pr_info("Kernel command line: %s\n", arcs_cmdline); +} + +/* Do basic initialization */ +void __init prom_init(void) +{ + uint32_t model; + + pr_info("%s called\n", __func__); + soc_info.sw_base = RTL838X_SW_BASE; + + model = sw_r32(RTL838X_MODEL_NAME_INFO); + pr_info("RTL838X model is %x\n", model); + model = model >> 16 & 0xFFFF; + + if ((model != 0x8328) && (model != 0x8330) && (model != 0x8332) + && (model != 0x8380) && (model != 0x8382)) { + model = sw_r32(RTL839X_MODEL_NAME_INFO); + pr_info("RTL839X model is %x\n", model); + model = model >> 16 & 0xFFFF; + } + + soc_info.id = model; + + switch (model) { + case 0x8328: + soc_info.name = "RTL8328"; + soc_info.family = RTL8328_FAMILY_ID; + break; + case 0x8332: + soc_info.name = "RTL8332"; + soc_info.family = RTL8380_FAMILY_ID; + break; + case 0x8380: + soc_info.name = "RTL8380"; + soc_info.family = RTL8380_FAMILY_ID; + break; + case 0x8382: + soc_info.name = "RTL8382"; + soc_info.family = RTL8380_FAMILY_ID; + break; + case 0x8390: + soc_info.name = "RTL8390"; + soc_info.family = RTL8390_FAMILY_ID; + break; + case 0x8391: + soc_info.name = "RTL8391"; + soc_info.family = RTL8390_FAMILY_ID; + break; + case 0x8392: + soc_info.name = "RTL8392"; + soc_info.family = RTL8390_FAMILY_ID; + break; + case 0x8393: + soc_info.name = "RTL8393"; + soc_info.family = RTL8390_FAMILY_ID; + break; + default: + soc_info.name = "DEFAULT"; + soc_info.family = 0; + } + pr_info("SoC Type: %s\n", get_system_type()); + prom_init_cmdline(); +} + diff --git a/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/serial.c b/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/serial.c new file mode 100644 index 0000000000..cebab1df8d --- /dev/null +++ b/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/serial.c @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * 8250 serial console setup for the Realtek RTL838X SoC + * + * based on the original BSP by + * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com) + * + * Copyright (C) 2020 B. Koblitz + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +extern char arcs_cmdline[]; +extern struct rtl838x_soc_info soc_info; + +int __init rtl838x_serial_init(void) +{ +#ifdef CONFIG_SERIAL_8250 + int ret; + struct uart_port p; + unsigned long baud = 0; + int err; + char parity = '\0', bits = '\0', flow = '\0'; + char *s; + struct device_node *dn; + + dn = of_find_compatible_node(NULL, NULL, "ns16550a"); + if (dn) { + pr_info("Found NS16550a: %s (%s)\n", dn->name, dn->full_name); + dn = of_find_compatible_node(dn, NULL, "ns16550a"); + if (dn && of_device_is_available(dn) && soc_info.family == RTL8380_FAMILY_ID) { + /* Enable UART1 on RTL838x */ + pr_info("Enabling uart1\n"); + sw_w32(0x10, RTL838X_GMII_INTF_SEL); + } + } else { + pr_err("No NS16550a UART found!"); + return -ENODEV; + } + + s = strstr(arcs_cmdline, "console=ttyS0,"); + if (s) { + s += 14; + baud = kstrtoul(s, 10, &baud); + if (err) + baud = 0; + while (isdigit(*s)) + s++; + if (*s == ',') + s++; + if (*s) + parity = *s++; + if (*s == ',') + s++; + if (*s) + bits = *s++; + if (*s == ',') + s++; + if (*s == 'h') + flow = 'r'; + } + + if (baud == 0) { + baud = 38400; + pr_warn("Using default baud rate: %lu\n", baud); + } + if (parity != 'n' && parity != 'o' && parity != 'e') + parity = 'n'; + if (bits != '7' && bits != '8') + bits = '8'; + + memset(&p, 0, sizeof(p)); + + p.type = PORT_16550A; + p.membase = (unsigned char *) RTL838X_UART0_BASE; + p.irq = RTL838X_UART0_IRQ; + p.uartclk = SYSTEM_FREQ - (24 * baud); + p.flags = UPF_SKIP_TEST | UPF_LOW_LATENCY | UPF_FIXED_TYPE; + p.iotype = UPIO_MEM; + p.regshift = 2; + p.fifosize = 1; + + /* Call early_serial_setup() here, to set up 8250 console driver */ + if (early_serial_setup(&p) != 0) + ret = 1; +#endif + return 0; +} diff --git a/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/setup.c b/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/setup.c new file mode 100644 index 0000000000..6a9485c451 --- /dev/null +++ b/target/linux/rtl838x/files-5.4/arch/mips/rtl838x/setup.c @@ -0,0 +1,187 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Setup for the Realtek RTL838X SoC: + * Memory, Timer and Serial + * + * Copyright (C) 2020 B. Koblitz + * based on the original BSP by + * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com) + * + */ +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include /* for mips_hpt_frequency */ +#include +#include + +#include "mach-rtl838x.h" + +extern int rtl838x_serial_init(void); +extern struct rtl838x_soc_info soc_info; + +struct clk { + struct clk_lookup cl; + unsigned long rate; +}; + +struct clk cpu_clk; + +u32 pll_reset_value; + +static void rtl838x_restart(char *command) +{ + u32 pll = sw_r32(RTL838X_PLL_CML_CTRL); + /* SoC reset vector (in flash memory): on RTL839x platform preferred way to reset */ + void (*f)(void) = (void *) 0xbfc00000; + + pr_info("System restart.\n"); + if (soc_info.family == RTL8390_FAMILY_ID) { + f(); + /* If calling reset vector fails, reset entire chip */ + sw_w32(0xFFFFFFFF, RTL839X_RST_GLB_CTRL); + /* If this fails, halt the CPU */ + while + (1); + } + + pr_info("PLL control register: %x, applying reset value %x\n", + pll, pll_reset_value); + sw_w32(3, RTL838X_INT_RW_CTRL); + sw_w32(pll_reset_value, RTL838X_PLL_CML_CTRL); + sw_w32(0, RTL838X_INT_RW_CTRL); + + pr_info("Resetting RTL838X SoC\n"); + /* Reset Global Control1 Register */ + sw_w32(1, RTL838X_RST_GLB_CTRL_1); +} + +static void rtl838x_halt(void) +{ + pr_info("System halted.\n"); + while + (1); +} + +static void __init rtl838x_setup(void) +{ + unsigned int val; + + pr_info("Registering _machine_restart\n"); + _machine_restart = rtl838x_restart; + _machine_halt = rtl838x_halt; + + val = rtl838x_r32((volatile void *)0xBB0040000); + if (val == 3) + pr_info("PCI device found\n"); + else + pr_info("NO PCI device found\n"); + + /* Setup System LED. Bit 15 (14 for RTL8390) then allows to toggle it */ + if (soc_info.family == RTL8380_FAMILY_ID) + sw_w32_mask(0, 3 << 16, RTL838X_LED_GLB_CTRL); + else + sw_w32_mask(0, 3 << 15, RTL839X_LED_GLB_CTRL); +} + +void __init plat_mem_setup(void) +{ + void *dtb; + + pr_info("%s called\n", __func__); + + set_io_port_base(KSEG1); + + if (fw_passed_dtb) /* UHI interface */ + dtb = (void *)fw_passed_dtb; + else if (__dtb_start != __dtb_end) + dtb = (void *)__dtb_start; + else + panic("no dtb found"); + + /* + * Load the devicetree. This causes the chosen node to be + * parsed resulting in our memory appearing + */ + __dt_setup_arch(dtb); + + rtl838x_setup(); +} + + +/* + * Linux clock API + */ +int clk_enable(struct clk *clk) +{ + return 0; +} +EXPORT_SYMBOL_GPL(clk_enable); + +void clk_disable(struct clk *clk) +{ + +} +EXPORT_SYMBOL_GPL(clk_disable); + +unsigned long clk_get_rate(struct clk *clk) +{ + if (!clk) + return 0; + + return clk->rate; +} +EXPORT_SYMBOL_GPL(clk_get_rate); + +int clk_set_rate(struct clk *clk, unsigned long rate) +{ + return -1; +} +EXPORT_SYMBOL_GPL(clk_set_rate); + +long clk_round_rate(struct clk *clk, unsigned long rate) +{ + return -1; +} +EXPORT_SYMBOL_GPL(clk_round_rate); + +void __init plat_time_init(void) +{ + u32 freq = 500000000; + struct device_node *np; + struct clk *clk = &cpu_clk; + + np = of_find_node_by_name(NULL, "cpus"); + if (!np) { + pr_err("Missing 'cpus' DT node, using default frequency."); + } else { + if (of_property_read_u32(np, "frequency", &freq) < 0) + pr_err("No 'frequency' property in DT, using default."); + else + pr_info("CPU frequency from device tree: %d", freq); + of_node_put(np); + } + + clk->rate = freq; + + if (IS_ERR(clk)) + panic("unable to get CPU clock, err=%ld", PTR_ERR(clk)); + + pr_info("CPU Clock: %ld MHz\n", clk->rate / 1000000); + mips_hpt_frequency = freq / 2; + + pll_reset_value = sw_r32(RTL838X_PLL_CML_CTRL); + pr_info("PLL control register: %x\n", pll_reset_value); + + /* With the info from the command line and cpu-freq we can setup the console */ + rtl838x_serial_init(); +} diff --git a/target/linux/rtl838x/files-5.4/drivers/gpio/gpio-rtl838x.c b/target/linux/rtl838x/files-5.4/drivers/gpio/gpio-rtl838x.c new file mode 100644 index 0000000000..bba3b3f572 --- /dev/null +++ b/target/linux/rtl838x/files-5.4/drivers/gpio/gpio-rtl838x.c @@ -0,0 +1,807 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include +#include +#include +#include +#include + +/* RTL8231 registers for LED control */ +#define RTL8231_LED_FUNC0 0x0000 +#define RTL8231_GPIO_PIN_SEL(gpio) ((0x0002) + ((gpio) >> 4)) +#define RTL8231_GPIO_DIR(gpio) ((0x0005) + ((gpio) >> 4)) +#define RTL8231_GPIO_DATA(gpio) ((0x001C) + ((gpio) >> 4)) +#define RTL8231_GPIO_PIN_SEL0 0x0002 +#define RTL8231_GPIO_PIN_SEL1 0x0003 +#define RTL8231_GPIO_PIN_SEL2 0x0004 +#define RTL8231_GPIO_IO_SEL0 0x0005 +#define RTL8231_GPIO_IO_SEL1 0x0006 +#define RTL8231_GPIO_IO_SEL2 0x0007 + +#define MDC_WAIT { int i; for (i = 0; i < 2; i++); } +#define I2C_WAIT { int i; for (i = 0; i < 5; i++); } + +struct rtl838x_gpios { + struct gpio_chip gc; + u32 id; + struct device *dev; + int irq; + int bus_id; + int num_leds; + int min_led; + int leds_per_port; + u32 led_mode; + u16 rtl8381_phy_id; + int smi_clock; + int smi_data; + int i2c_sda; + int i2c_sdc; +}; + +extern struct mutex smi_lock; + +u32 rtl838x_rtl8231_read(u8 bus_id, u32 reg) +{ + u32 t = 0; + + reg &= 0x1f; + bus_id &= 0x1f; + + /* Calculate read register address */ + t = (bus_id << 2) | (reg << 7); + + mutex_lock(&smi_lock); + /* Set execution bit: cleared when operation completed */ + t |= 1; + sw_w32(t, RTL838X_EXT_GPIO_INDRT_ACCESS); + do { /* TODO: Return 0x80000000 if timeout */ + t = sw_r32(RTL838X_EXT_GPIO_INDRT_ACCESS); + } while (t & 1); + pr_debug("%s: %x, %x, %x\n", __func__, bus_id, reg, (t & 0xffff0000) >> 16); + + mutex_unlock(&smi_lock); + return (t & 0xffff0000) >> 16; +} + +int rtl838x_rtl8231_write(u8 bus_id, u32 reg, u32 data) +{ + u32 t = 0; + + pr_debug("%s: %x, %x, %x\n", __func__, bus_id, reg, data); + data &= 0xffff; + reg &= 0x1f; + bus_id &= 0x1f; + + mutex_lock(&smi_lock); + t = (bus_id << 2) | (reg << 7) | (data << 16); + /* Set write bit */ + t |= 2; + + /* Set execution bit: cleared when operation completed */ + t |= 1; + sw_w32(t, RTL838X_EXT_GPIO_INDRT_ACCESS); + do { /* TODO: Return -1 if timeout */ + t = sw_r32(RTL838X_EXT_GPIO_INDRT_ACCESS); + } while (t & 1); + + mutex_unlock(&smi_lock); + return 0; +} + +static int rtl8231_pin_dir(u8 bus_id, u32 gpio, u32 dir) +{ + /* dir 1: input + * dir 0: output + */ + + u32 v; + int pin_sel_addr = RTL8231_GPIO_PIN_SEL(gpio); + int pin_dir_addr = RTL8231_GPIO_DIR(gpio); + int pin = gpio % 16; + int dpin = pin; + + if (gpio > 31) { + dpin = pin << 5; + pin_dir_addr = pin_sel_addr; + } + + /* Select GPIO function for pin */ + v = rtl838x_rtl8231_read(bus_id, pin_sel_addr); + if (v & 0x80000000) { + pr_err("Error reading RTL8231\n"); + return -1; + } + rtl838x_rtl8231_write(bus_id, pin_sel_addr, v | (1 << pin)); + + v = rtl838x_rtl8231_read(bus_id, pin_dir_addr); + if (v & 0x80000000) { + pr_err("Error reading RTL8231\n"); + return -1; + } + rtl838x_rtl8231_write(bus_id, pin_dir_addr, + (v & ~(1 << dpin)) | (dir << dpin)); + return 0; +} + +static int rtl8231_pin_dir_get(u8 bus_id, u32 gpio, u32 *dir) +{ + /* dir 1: input + * dir 0: output + */ + + u32 v; + int pin_dir_addr = RTL8231_GPIO_DIR(gpio); + int pin = gpio % 16; + + if (gpio > 31) { + pin_dir_addr = RTL8231_GPIO_PIN_SEL(gpio); + pin = pin << 5; + } + + v = rtl838x_rtl8231_read(bus_id, pin_dir_addr); + if (v & (1 << pin)) + *dir = 1; + else + *dir = 0; + return 0; +} + +static int rtl8231_pin_set(u8 bus_id, u32 gpio, u32 data) +{ + u32 v = rtl838x_rtl8231_read(bus_id, RTL8231_GPIO_DATA(gpio)); + + if (v & 0x80000000) { + pr_err("Error reading RTL8231\n"); + return -1; + } + rtl838x_rtl8231_write(bus_id, RTL8231_GPIO_DATA(gpio), + (v & ~(1 << (gpio % 16))) | (data << (gpio % 16))); + return 0; +} + +static int rtl8231_pin_get(u8 bus_id, u32 gpio, u16 *state) +{ + u32 v = rtl838x_rtl8231_read(bus_id, RTL8231_GPIO_DATA(gpio)); + + if (v & 0x80000000) { + pr_err("Error reading RTL8231\n"); + return -1; + } + + *state = v & 0xffff; + return 0; +} + +static int rtl838x_direction_input(struct gpio_chip *gc, unsigned int offset) +{ + struct rtl838x_gpios *gpios = gpiochip_get_data(gc); + + pr_debug("%s: %d\n", __func__, offset); + + if (offset < 32) { + rtl838x_w32_mask(1 << offset, 0, RTL838X_GPIO_PABC_DIR); + return 0; + } + + /* Internal LED driver does not support input */ + if (offset >= 32 && offset < 64) + return -ENOTSUPP; + + if (offset >= 64 && offset < 100 && gpios->bus_id >= 0) + return rtl8231_pin_dir(gpios->bus_id, offset - 64, 1); + + return -ENOTSUPP; +} + +static int rtl838x_direction_output(struct gpio_chip *gc, unsigned int offset, int value) +{ + struct rtl838x_gpios *gpios = gpiochip_get_data(gc); + + pr_debug("%s: %d\n", __func__, offset); + if (offset < 32) + rtl838x_w32_mask(0, 1 << offset, RTL838X_GPIO_PABC_DIR); + + /* LED for PWR and SYS driver is direction output by default */ + if (offset >= 32 && offset < 64) + return 0; + + if (offset >= 64 && offset < 100 && gpios->bus_id >= 0) + return rtl8231_pin_dir(gpios->bus_id, offset - 64, 0); + return 0; +} + +static int rtl838x_get_direction(struct gpio_chip *gc, unsigned int offset) +{ + u32 v = 0; + struct rtl838x_gpios *gpios = gpiochip_get_data(gc); + + pr_debug("%s: %d\n", __func__, offset); + if (offset < 32) { + v = rtl838x_r32(RTL838X_GPIO_PABC_DIR); + if (v & (1 << offset)) + return 0; + return 1; + } + + /* LED driver for PWR and SYS is direction output by default */ + if (offset >= 32 && offset < 64) + return 0; + + if (offset >= 64 && offset < 100 && gpios->bus_id >= 0) { + rtl8231_pin_dir_get(gpios->bus_id, offset - 64, &v); + return v; + } + + return 0; +} + +static int rtl838x_gpio_get(struct gpio_chip *gc, unsigned int offset) +{ + u32 v; + u16 state = 0; + int bit; + struct rtl838x_gpios *gpios = gpiochip_get_data(gc); + + pr_debug("%s: %d\n", __func__, offset); + + /* Internal GPIO of the RTL8380 */ + if (offset < 32) { + v = rtl838x_r32(RTL838X_GPIO_PABC_DATA); + if (v & (1 << offset)) + return 1; + return 0; + } + + /* LED driver for PWR and SYS */ + if (offset >= 32 && offset < 64) { + v = sw_r32(RTL838X_LED_GLB_CTRL); + if (v & (1 << (offset-32))) + return 1; + return 0; + } + + /* Indirect access GPIO with RTL8231 */ + if (offset >= 64 && offset < 100 && gpios->bus_id >= 0) { + rtl8231_pin_get(gpios->bus_id, offset - 64, &state); + if (state & (1 << (offset % 16))) + return 1; + return 0; + } + + bit = (offset - 100) % 32; + if (offset >= 100 && offset < 132) { + if (sw_r32(RTL838X_LED1_SW_P_EN_CTRL) & (1 << bit)) + return 1; + return 0; + } + if (offset >= 132 && offset < 164) { + if (sw_r32(RTL838X_LED1_SW_P_EN_CTRL) & (1 << bit)) + return 1; + return 0; + } + if (offset >= 164 && offset < 196) { + if (sw_r32(RTL838X_LED1_SW_P_EN_CTRL) & (1 << bit)) + return 1; + return 0; + } + return 0; +} + +void rtl838x_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) +{ + int bit; + struct rtl838x_gpios *gpios = gpiochip_get_data(gc); + + pr_debug("rtl838x_set: %d, value: %d\n", offset, value); + /* Internal GPIO of the RTL8380 */ + if (offset < 32) { + if (value) + rtl838x_w32_mask(0, 1 << offset, RTL838X_GPIO_PABC_DATA); + else + rtl838x_w32_mask(1 << offset, 0, RTL838X_GPIO_PABC_DATA); + } + + /* LED driver for PWR and SYS */ + if (offset >= 32 && offset < 64) { + bit = offset - 32; + if (value) + sw_w32_mask(0, 1 << bit, RTL838X_LED_GLB_CTRL); + else + sw_w32_mask(1 << bit, 0, RTL838X_LED_GLB_CTRL); + return; + } + + /* Indirect access GPIO with RTL8231 */ + if (offset >= 64 && offset < 100 && gpios->bus_id >= 0) { + rtl8231_pin_set(gpios->bus_id, offset - 64, value); + return; + } + + bit = (offset - 100) % 32; + /* First Port-LED */ + if (offset >= 100 && offset < 132 + && offset >= (100 + gpios->min_led) + && offset < (100 + gpios->min_led + gpios->num_leds)) { + if (value) + sw_w32_mask(7, 5, RTL838X_LED_SW_P_CTRL(bit)); + else + sw_w32_mask(7, 0, RTL838X_LED_SW_P_CTRL(bit)); + } + if (offset >= 132 && offset < 164 + && offset >= (132 + gpios->min_led) + && offset < (132 + gpios->min_led + gpios->num_leds)) { + if (value) + sw_w32_mask(7 << 3, 5 << 3, RTL838X_LED_SW_P_CTRL(bit)); + else + sw_w32_mask(7 << 3, 0, RTL838X_LED_SW_P_CTRL(bit)); + } + if (offset >= 164 && offset < 196 + && offset >= (164 + gpios->min_led) + && offset < (164 + gpios->min_led + gpios->num_leds)) { + if (value) + sw_w32_mask(7 << 6, 5 << 6, RTL838X_LED_SW_P_CTRL(bit)); + else + sw_w32_mask(7 << 6, 0, RTL838X_LED_SW_P_CTRL(bit)); + } + __asm__ volatile ("sync"); +} + +int rtl8231_init(struct rtl838x_gpios *gpios) +{ + uint32_t v; + u8 bus_id = gpios->bus_id; + + pr_info("%s called\n", __func__); + + /* Enable RTL8231 indirect access mode */ + sw_w32_mask(0, 1, RTL838X_EXTRA_GPIO_CTRL); + sw_w32_mask(3, 1, RTL838X_DMY_REG5); + + /* Enable RTL8231 via GPIO_A1 line */ + rtl838x_w32_mask(0, 1 << RTL838X_GPIO_A1, RTL838X_GPIO_PABC_DIR); + rtl838x_w32_mask(0, 1 << RTL838X_GPIO_A1, RTL838X_GPIO_PABC_DATA); + mdelay(50); /* wait 50ms for reset */ + + /*Select GPIO functionality for pins 0-15, 16-31 and 32-37 */ + rtl838x_rtl8231_write(bus_id, RTL8231_GPIO_PIN_SEL(0), 0xffff); + rtl838x_rtl8231_write(bus_id, RTL8231_GPIO_PIN_SEL(16), 0xffff); + rtl838x_rtl8231_write(bus_id, RTL8231_GPIO_PIN_SEL2, 0x03ff); + + v = rtl838x_rtl8231_read(bus_id, RTL8231_LED_FUNC0); + pr_info("RTL8231 led function now: %x\n", v); + + return 0; +} + +static void smi_write_bit(struct rtl838x_gpios *gpios, u32 bit) +{ + if (bit) + rtl838x_w32_mask(0, 1 << gpios->smi_data, RTL838X_GPIO_PABC_DATA); + else + rtl838x_w32_mask(1 << gpios->smi_data, 0, RTL838X_GPIO_PABC_DATA); + + MDC_WAIT; + rtl838x_w32_mask(1 << gpios->smi_clock, 0, RTL838X_GPIO_PABC_DATA); + MDC_WAIT; + rtl838x_w32_mask(0, 1 << gpios->smi_clock, RTL838X_GPIO_PABC_DATA); +} + +static int smi_read_bit(struct rtl838x_gpios *gpios) +{ + u32 v; + + MDC_WAIT; + rtl838x_w32_mask(1 << gpios->smi_clock, 0, RTL838X_GPIO_PABC_DATA); + MDC_WAIT; + rtl838x_w32_mask(0, 1 << gpios->smi_clock, RTL838X_GPIO_PABC_DATA); + + v = rtl838x_r32(RTL838X_GPIO_PABC_DATA); + if (v & (1 << gpios->smi_data)) + return 1; + return 0; +} + +/* Tri-state of MDIO line */ +static void smi_z(struct rtl838x_gpios *gpios) +{ + /* MDIO pin to input */ + rtl838x_w32_mask(1 << gpios->smi_data, 0, RTL838X_GPIO_PABC_DIR); + MDC_WAIT; + rtl838x_w32_mask(1 << gpios->smi_clock, 0, RTL838X_GPIO_PABC_DATA); + MDC_WAIT; + rtl838x_w32_mask(0, 1 << gpios->smi_clock, RTL838X_GPIO_PABC_DATA); +} + +static void smi_write_bits(struct rtl838x_gpios *gpios, u32 data, int len) +{ + while (len) { + len--; + smi_write_bit(gpios, data & (1 << len)); + } +} + +static void smi_read_bits(struct rtl838x_gpios *gpios, int len, u32 *data) +{ + u32 v = 0; + + while (len) { + len--; + v <<= 1; + v |= smi_read_bit(gpios); + } + *data = v; +} + +/* Bit-banged verson of SMI write access, caller must hold smi_lock */ +int rtl8380_smi_write(struct rtl838x_gpios *gpios, u16 reg, u32 data) +{ + u16 bus_id = gpios->bus_id; + + /* Set clock and data pins on RTL838X to output */ + rtl838x_w32_mask(0, 1 << gpios->smi_clock, RTL838X_GPIO_PABC_DIR); + rtl838x_w32_mask(0, 1 << gpios->smi_data, RTL838X_GPIO_PABC_DIR); + + /* Write start bits */ + smi_write_bits(gpios, 0xffffffff, 32); + + smi_write_bits(gpios, 0x5, 4); /* ST and write OP */ + + smi_write_bits(gpios, bus_id, 5); /* 5 bits: phy address */ + smi_write_bits(gpios, reg, 5); /* 5 bits: register address */ + + smi_write_bits(gpios, 0x2, 2); /* TURNAROUND */ + + smi_write_bits(gpios, data, 16); /* 16 bits: data*/ + + smi_z(gpios); + + return 0; +} + +/* Bit-banged verson of SMI read access, caller must hold smi_lock */ +int rtl8380_smi_read(struct rtl838x_gpios *gpios, u16 reg, u32 *data) +{ + u16 bus_id = gpios->bus_id; + + /* Set clock and data pins on RTL838X to output */ + rtl838x_w32_mask(0, 1 << gpios->smi_clock, RTL838X_GPIO_PABC_DIR); + rtl838x_w32_mask(0, 1 << gpios->smi_data, RTL838X_GPIO_PABC_DIR); + + /* Write start bits */ + smi_write_bits(gpios, 0xffffffff, 32); + + smi_write_bits(gpios, 0x6, 4); /* ST and read OP */ + + smi_write_bits(gpios, bus_id, 5); /* 5 bits: phy address */ + smi_write_bits(gpios, reg, 5); /* 5 bits: register address */ + + smi_z(gpios); /* TURNAROUND */ + + smi_read_bits(gpios, 16, data); + return 0; +} + +static void i2c_pin_set(struct rtl838x_gpios *gpios, int pin, u32 data) +{ + u32 v; + + rtl8380_smi_read(gpios, RTL8231_GPIO_DATA(pin), &v); + if (!data) + v &= ~(1 << (pin % 16)); + else + v |= (1 << (pin % 16)); + rtl8380_smi_write(gpios, RTL8231_GPIO_DATA(pin), v); +} + +static void i2c_pin_get(struct rtl838x_gpios *gpios, int pin, u32 *data) +{ + u32 v; + + rtl8380_smi_read(gpios, RTL8231_GPIO_DATA(pin), &v); + if (v & (1 << (pin % 16))) { + *data = 1; + return; + } + *data = 0; +} + +static void i2c_pin_dir(struct rtl838x_gpios *gpios, int pin, u16 direction) +{ + u32 v; + + rtl8380_smi_read(gpios, RTL8231_GPIO_DIR(pin), &v); + if (direction) // Output + v &= ~(1 << (pin % 16)); + else + v |= (1 << (pin % 16)); + rtl8380_smi_write(gpios, RTL8231_GPIO_DIR(pin), v); +} + +static void i2c_start(struct rtl838x_gpios *gpios) +{ + i2c_pin_dir(gpios, gpios->i2c_sda, 0); /* Output */ + i2c_pin_dir(gpios, gpios->i2c_sdc, 0); /* Output */ + I2C_WAIT; + i2c_pin_set(gpios, gpios->i2c_sdc, 1); + I2C_WAIT; + i2c_pin_set(gpios, gpios->i2c_sda, 1); + I2C_WAIT; + i2c_pin_set(gpios, gpios->i2c_sda, 0); + I2C_WAIT; + i2c_pin_set(gpios, gpios->i2c_sdc, 0); + I2C_WAIT; +} + +static void i2c_stop(struct rtl838x_gpios *gpios) +{ + I2C_WAIT; + i2c_pin_set(gpios, gpios->i2c_sdc, 1); + i2c_pin_set(gpios, gpios->i2c_sda, 0); + I2C_WAIT; + + i2c_pin_set(gpios, gpios->i2c_sda, 1); + I2C_WAIT; + i2c_pin_set(gpios, gpios->i2c_sdc, 0); + + i2c_pin_dir(gpios, gpios->i2c_sda, 1); /* Input */ + i2c_pin_dir(gpios, gpios->i2c_sdc, 1); /* Input */ +} + +static void i2c_read_bits(struct rtl838x_gpios *gpios, int len, u32 *data) +{ + u32 v = 0, t; + + while (len) { + len--; + v <<= 1; + i2c_pin_set(gpios, gpios->i2c_sdc, 1); + I2C_WAIT; + i2c_pin_get(gpios, gpios->i2c_sda, &t); + v |= t; + i2c_pin_set(gpios, gpios->i2c_sdc, 0); + I2C_WAIT; + } + *data = v; +} + +static void i2c_write_bits(struct rtl838x_gpios *gpios, u32 data, int len) +{ + while (len) { + len--; + i2c_pin_set(gpios, gpios->i2c_sda, data & (1 << len)); + I2C_WAIT; + i2c_pin_set(gpios, gpios->i2c_sdc, 1); + I2C_WAIT; + i2c_pin_set(gpios, gpios->i2c_sdc, 0); + I2C_WAIT; + } +} + +/* This initializes direct external GPIOs via the RTL8231 */ +int rtl8380_rtl8321_init(struct rtl838x_gpios *gpios) +{ + u32 v; + int mdc = gpios->smi_clock; + int mdio = gpios->smi_data; + + pr_info("Configuring SMI: Clock %d, Data %d\n", mdc, mdio); + sw_w32_mask(0, 0x2, RTL838X_IO_DRIVING_ABILITY_CTRL); + + /* Enter simulated GPIO mode */ + sw_w32_mask(1, 0, RTL838X_EXTRA_GPIO_CTRL); + + /* MDIO clock to 2.6MHz */ + sw_w32_mask(0x3 << 8, 0, RTL838X_EXTRA_GPIO_CTRL); + + /* Configure SMI clock and data GPIO pins */ + rtl838x_w32_mask((1 << mdc) | (1 << mdio), 0, RTL838X_GPIO_PABC_CNR); + rtl838x_w32_mask(0, (1 << mdc) | (1 << mdio), RTL838X_GPIO_PABC_DIR); + + rtl8380_smi_write(gpios, RTL8231_GPIO_PIN_SEL0, 0xffff); + rtl8380_smi_write(gpios, RTL8231_GPIO_PIN_SEL1, 0xffff); + rtl8380_smi_read(gpios, RTL8231_GPIO_PIN_SEL2, &v); + v |= 0x1f; + rtl8380_smi_write(gpios, RTL8231_GPIO_PIN_SEL2, v); + + rtl8380_smi_write(gpios, RTL8231_GPIO_IO_SEL0, 0xffff); + rtl8380_smi_write(gpios, RTL8231_GPIO_IO_SEL1, 0xffff); + rtl8380_smi_read(gpios, RTL8231_GPIO_IO_SEL2, &v); + v |= 0x1f << 5; + rtl8380_smi_write(gpios, RTL8231_GPIO_PIN_SEL2, v); + + return 0; +} + +void rtl8380_led_test(u32 mask) +{ + int i; + u32 mode_sel = sw_r32(RTL838X_LED_MODE_SEL); + u32 led_gbl = sw_r32(RTL838X_LED_GLB_CTRL); + u32 led_p_en = sw_r32(RTL838X_LED_P_EN_CTRL); + + /* 2 Leds for ports 0-23 and 24-27, 3 would be 0x7 */ + sw_w32_mask(0x3f, 0x3 | (0x3 << 3), RTL838X_LED_GLB_CTRL); + /* Enable all leds */ + sw_w32(0xFFFFFFF, RTL838X_LED_P_EN_CTRL); + + /* Enable software control of all leds */ + sw_w32(0xFFFFFFF, RTL838X_LED_SW_CTRL); + sw_w32(0xFFFFFFF, RTL838X_LED0_SW_P_EN_CTRL); + sw_w32(0xFFFFFFF, RTL838X_LED1_SW_P_EN_CTRL); + sw_w32(0x0000000, RTL838X_LED2_SW_P_EN_CTRL); + + for (i = 0; i < 28; i++) { + if (mask & (1 << i)) + sw_w32(5 | (5 << 3) | (5 << 6), + RTL838X_LED_SW_P_CTRL(i)); + } + msleep(3000); + + sw_w32(led_p_en, RTL838X_LED_P_EN_CTRL); + /* Disable software control of all leds */ + sw_w32(0x0000000, RTL838X_LED_SW_CTRL); + sw_w32(0x0000000, RTL838X_LED0_SW_P_EN_CTRL); + sw_w32(0x0000000, RTL838X_LED1_SW_P_EN_CTRL); + sw_w32(0x0000000, RTL838X_LED2_SW_P_EN_CTRL); + + sw_w32(led_gbl, RTL838X_LED_GLB_CTRL); + sw_w32(mode_sel, RTL838X_LED_MODE_SEL); +} + +void take_port_leds(struct rtl838x_gpios *gpios) +{ + int leds_per_port = gpios->leds_per_port; + int mode = gpios->led_mode; + + pr_info("%s, %d, %x\n", __func__, leds_per_port, mode); + pr_debug("Bootloader settings: %x %x %x\n", + sw_r32(RTL838X_LED0_SW_P_EN_CTRL), + sw_r32(RTL838X_LED1_SW_P_EN_CTRL), + sw_r32(RTL838X_LED2_SW_P_EN_CTRL) + ); + + pr_debug("led glb: %x, sel %x\n", + sw_r32(RTL838X_LED_GLB_CTRL), sw_r32(RTL838X_LED_MODE_SEL)); + pr_debug("RTL838X_LED_P_EN_CTRL: %x", sw_r32(RTL838X_LED_P_EN_CTRL)); + pr_debug("RTL838X_LED_MODE_CTRL: %x", sw_r32(RTL838X_LED_MODE_CTRL)); + + sw_w32_mask(3, 0, RTL838X_LED_MODE_SEL); + sw_w32(mode, RTL838X_LED_MODE_CTRL); + + /* Enable software control of all leds */ + sw_w32(0xFFFFFFF, RTL838X_LED_SW_CTRL); + sw_w32(0xFFFFFFF, RTL838X_LED_P_EN_CTRL); + + sw_w32(0x0000000, RTL838X_LED0_SW_P_EN_CTRL); + sw_w32(0x0000000, RTL838X_LED1_SW_P_EN_CTRL); + sw_w32(0x0000000, RTL838X_LED2_SW_P_EN_CTRL); + + sw_w32_mask(0x3f, 0, RTL838X_LED_GLB_CTRL); + switch (leds_per_port) { + case 3: + sw_w32_mask(0, 0x7 | (0x7 << 3), RTL838X_LED_GLB_CTRL); + sw_w32(0xFFFFFFF, RTL838X_LED2_SW_P_EN_CTRL); + /* FALLTHRU */ + case 2: + sw_w32_mask(0, 0x3 | (0x3 << 3), RTL838X_LED_GLB_CTRL); + sw_w32(0xFFFFFFF, RTL838X_LED1_SW_P_EN_CTRL); + /* FALLTHRU */ + case 1: + sw_w32_mask(0, 0x1 | (0x1 << 3), RTL838X_LED_GLB_CTRL); + sw_w32(0xFFFFFFF, RTL838X_LED0_SW_P_EN_CTRL); + break; + default: + pr_err("No LEDS configured for software control\n"); + } +} + +static const struct of_device_id rtl838x_gpio_of_match[] = { + { .compatible = "realtek,rtl838x-gpio" }, + {}, +}; + +MODULE_DEVICE_TABLE(of, rtl838x_gpio_of_match); + +static int rtl838x_gpio_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct rtl838x_gpios *gpios; + int err; + u8 indirect_bus_id; + + pr_info("Probing RTL838X GPIOs\n"); + + if (!np) { + dev_err(&pdev->dev, "No DT found\n"); + return -EINVAL; + } + + gpios = devm_kzalloc(dev, sizeof(*gpios), GFP_KERNEL); + if (!gpios) + return -ENOMEM; + + gpios->id = sw_r32(RTL838X_MODEL_NAME_INFO) >> 16; + + switch (gpios->id) { + case 0x8332: + pr_debug("Found RTL8332M GPIO\n"); + break; + case 0x8380: + pr_debug("Found RTL8380M GPIO\n"); + break; + case 0x8381: + pr_debug("Found RTL8381M GPIO\n"); + break; + case 0x8382: + pr_debug("Found RTL8382M GPIO\n"); + break; + default: + pr_err("Unknown GPIO chip id (%04x)\n", gpios->id); + return -ENODEV; + } + + gpios->dev = dev; + gpios->gc.base = 0; + /* 0-31: internal + * 32-63, LED control register + * 64-99: external RTL8231 + * 100-131: PORT-LED 0 + * 132-163: PORT-LED 1 + * 164-195: PORT-LED 2 + */ + gpios->gc.ngpio = 196; + gpios->gc.label = "rtl838x"; + gpios->gc.parent = dev; + gpios->gc.owner = THIS_MODULE; + gpios->gc.can_sleep = true; + gpios->bus_id = -1; + gpios->irq = 31; + + gpios->gc.direction_input = rtl838x_direction_input; + gpios->gc.direction_output = rtl838x_direction_output; + gpios->gc.set = rtl838x_gpio_set; + gpios->gc.get = rtl838x_gpio_get; + gpios->gc.get_direction = rtl838x_get_direction; + + if (!of_property_read_u8(np, "indirect-access-bus-id", &indirect_bus_id)) { + gpios->bus_id = indirect_bus_id; + rtl8231_init(gpios); + } + if (!of_property_read_u8(np, "smi-bus-id", &indirect_bus_id)) { + gpios->bus_id = indirect_bus_id; + gpios->smi_clock = RTL838X_GPIO_A2; + gpios->smi_data = RTL838X_GPIO_A3; + gpios->i2c_sda = 1; + gpios->i2c_sdc = 2; + rtl8380_rtl8321_init(gpios); + } + + if (of_property_read_bool(np, "take-port-leds")) { + if (of_property_read_u32(np, "leds-per-port", &gpios->leds_per_port)) + gpios->leds_per_port = 2; + if (of_property_read_u32(np, "led-mode", &gpios->led_mode)) + gpios->led_mode = (0x1ea << 15) | 0x1ea; + if (of_property_read_u32(np, "num-leds", &gpios->num_leds)) + gpios->num_leds = 32; + if (of_property_read_u32(np, "min-led", &gpios->min_led)) + gpios->min_led = 0; + take_port_leds(gpios); + } + + err = devm_gpiochip_add_data(dev, &gpios->gc, gpios); + return err; +} + + +static struct platform_driver rtl838x_gpio_driver = { + .driver = { + .name = "rtl838x-gpio", + .of_match_table = rtl838x_gpio_of_match, + }, + .probe = rtl838x_gpio_probe, +}; + +module_platform_driver(rtl838x_gpio_driver); + +MODULE_DESCRIPTION("Realtek RTL838X GPIO API support"); +MODULE_LICENSE("GPL v2"); diff --git a/target/linux/rtl838x/files-5.4/drivers/mtd/spi-nor/rtl838x-nor.c b/target/linux/rtl838x/files-5.4/drivers/mtd/spi-nor/rtl838x-nor.c new file mode 100644 index 0000000000..0d8f9dbd3e --- /dev/null +++ b/target/linux/rtl838x/files-5.4/drivers/mtd/spi-nor/rtl838x-nor.c @@ -0,0 +1,607 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "rtl838x-spi.h" +#include + +extern struct rtl838x_soc_info soc_info; + +struct rtl838x_nor { + struct spi_nor nor; + struct device *dev; + volatile void __iomem *base; + bool fourByteMode; + u32 chipSize; + uint32_t flags; + uint32_t io_status; +}; + +static uint32_t spi_prep(struct rtl838x_nor *rtl838x_nor) +{ + /* Needed because of MMU constraints */ + SPI_WAIT_READY; + spi_w32w(SPI_CS_INIT, SFCSR); //deactivate CS0, CS1 + spi_w32w(0, SFCSR); //activate CS0,CS1 + spi_w32w(SPI_CS_INIT, SFCSR); //deactivate CS0, CS1 + + return (CS0 & rtl838x_nor->flags) ? (SPI_eCS0 & SPI_LEN_INIT) + : ((SPI_eCS1 & SPI_LEN_INIT) | SFCSR_CHIP_SEL); +} + +static uint32_t rtl838x_nor_get_SR(struct rtl838x_nor *rtl838x_nor) +{ + uint32_t sfcsr, sfdr; + + sfcsr = spi_prep(rtl838x_nor); + sfdr = (SPINOR_OP_RDSR)<<24; + + pr_debug("%s: rdid,sfcsr_val = %.8x,SFDR = %.8x\n", __func__, sfcsr, sfdr); + pr_debug("rdid,sfcsr = %.8x\n", sfcsr | SPI_LEN4); + spi_w32w(sfcsr, SFCSR); + spi_w32w(sfdr, SFDR); + spi_w32_mask(0, SPI_LEN4, SFCSR); + SPI_WAIT_READY; + + return spi_r32(SFDR); +} + +static void spi_write_disable(struct rtl838x_nor *rtl838x_nor) +{ + uint32_t sfcsr, sfdr; + + sfcsr = spi_prep(rtl838x_nor); + sfdr = (SPINOR_OP_WRDI) << 24; + spi_w32w(sfcsr, SFCSR); + spi_w32w(sfdr, SFDR); + pr_debug("%s: sfcsr_val = %.8x,SFDR = %.8x", __func__, sfcsr, sfdr); + + spi_prep(rtl838x_nor); +} + +static void spi_write_enable(struct rtl838x_nor *rtl838x_nor) +{ + uint32_t sfcsr, sfdr; + + sfcsr = spi_prep(rtl838x_nor); + sfdr = (SPINOR_OP_WREN) << 24; + spi_w32w(sfcsr, SFCSR); + spi_w32w(sfdr, SFDR); + pr_debug("%s: sfcsr_val = %.8x,SFDR = %.8x", __func__, sfcsr, sfdr); + + spi_prep(rtl838x_nor); +} + +static void spi_4b_set(struct rtl838x_nor *rtl838x_nor, bool enable) +{ + uint32_t sfcsr, sfdr; + + sfcsr = spi_prep(rtl838x_nor); + if (enable) + sfdr = (SPINOR_OP_EN4B) << 24; + else + sfdr = (SPINOR_OP_EX4B) << 24; + + spi_w32w(sfcsr, SFCSR); + spi_w32w(sfdr, SFDR); + pr_debug("%s: sfcsr_val = %.8x,SFDR = %.8x", __func__, sfcsr, sfdr); + + spi_prep(rtl838x_nor); +} + +static int rtl838x_get_addr_mode(struct rtl838x_nor *rtl838x_nor) +{ + int res = 3; + u32 reg; + + sw_w32(0x3, RTL838X_INT_RW_CTRL); + if (!sw_r32(RTL838X_EXT_VERSION)) { + if (sw_r32(RTL838X_STRAP_DBG) & (1 << 29)) + res = 4; + } else { + reg = sw_r32(RTL838X_PLL_CML_CTRL); + if ((reg & (1 << 30)) && (reg & (1 << 31))) + res = 4; + if ((!(reg & (1 << 30))) + && sw_r32(RTL838X_STRAP_DBG) & (1 << 29)) + res = 4; + } + sw_w32(0x0, RTL838X_INT_RW_CTRL); + return res; +} + +static int rtl8390_get_addr_mode(struct rtl838x_nor *rtl838x_nor) +{ + if (spi_r32(RTL8390_SOC_SPI_MMIO_CONF) & (1 << 9)) + return 4; + return 3; +} + +ssize_t rtl838x_do_read(struct rtl838x_nor *rtl838x_nor, loff_t from, + size_t length, u_char *buffer, uint8_t command) +{ + uint32_t sfcsr, sfdr; + uint32_t len = length; + + sfcsr = spi_prep(rtl838x_nor); + sfdr = command << 24; + + /* Perform SPINOR_OP_READ: 1 byte command & 3 byte addr*/ + sfcsr |= SPI_LEN4; + sfdr |= from; + + spi_w32w(sfcsr, SFCSR); + spi_w32w(sfdr, SFDR); + + /* Read Data, 4 bytes at a time */ + while (length >= 4) { + SPI_WAIT_READY; + *((uint32_t *) buffer) = spi_r32(SFDR); +/* printk("%.8x ", *((uint32_t*) buffer)); */ + buffer += 4; + length -= 4; + } + + /* The rest needs to be read 1 byte a time */ + sfcsr &= SPI_LEN_INIT|SPI_LEN1; + SPI_WAIT_READY; + spi_w32w(sfcsr, SFCSR); + while (length > 0) { + SPI_WAIT_READY; + *(buffer) = spi_r32(SFDR) >> 24; +/* printk("%.2x ", *(buffer)); */ + buffer++; + length--; + } + return len; +} + +/* + * Do fast read in 3 or 4 Byte addressing mode + */ +static ssize_t rtl838x_do_4bf_read(struct rtl838x_nor *rtl838x_nor, loff_t from, + size_t length, u_char *buffer, uint8_t command) +{ + int sfcsr_addr_len = rtl838x_nor->fourByteMode ? 0x3 : 0x2; + int sfdr_addr_shift = rtl838x_nor->fourByteMode ? 0 : 8; + uint32_t sfcsr; + uint32_t len = length; + + pr_debug("Fast read from %llx, len %x, shift %d\n", + from, sfcsr_addr_len, sfdr_addr_shift); + sfcsr = spi_prep(rtl838x_nor); + + /* Send read command */ + spi_w32w(sfcsr | SPI_LEN1, SFCSR); + spi_w32w(command << 24, SFDR); + + /* Send address */ + spi_w32w(sfcsr | (sfcsr_addr_len << 28), SFCSR); + spi_w32w(from << sfdr_addr_shift, SFDR); + + /* Dummy cycles */ + spi_w32w(sfcsr | SPI_LEN1, SFCSR); + spi_w32w(0, SFDR); + + /* Start reading */ + spi_w32w(sfcsr | SPI_LEN4, SFCSR); + + /* Read Data, 4 bytes at a time */ + while (length >= 4) { + SPI_WAIT_READY; + *((uint32_t *) buffer) = spi_r32(SFDR); +/* printk("%.8x ", *((uint32_t*) buffer)); */ + buffer += 4; + length -= 4; + } + + /* The rest needs to be read 1 byte a time */ + sfcsr &= SPI_LEN_INIT|SPI_LEN1; + SPI_WAIT_READY; + spi_w32w(sfcsr, SFCSR); + while (length > 0) { + SPI_WAIT_READY; + *(buffer) = spi_r32(SFDR) >> 24; +/* printk("%.2x ", *(buffer)); */ + buffer++; + length--; + } + return len; + +} + +/* + * Do write (Page Programming) in 3 or 4 Byte addressing mode + */ +static ssize_t rtl838x_do_4b_write(struct rtl838x_nor *rtl838x_nor, loff_t to, + size_t length, const u_char *buffer, + uint8_t command) +{ + int sfcsr_addr_len = rtl838x_nor->fourByteMode ? 0x3 : 0x2; + int sfdr_addr_shift = rtl838x_nor->fourByteMode ? 0 : 8; + uint32_t sfcsr; + uint32_t len = length; + + pr_debug("Write to %llx, len %x, shift %d\n", + to, sfcsr_addr_len, sfdr_addr_shift); + sfcsr = spi_prep(rtl838x_nor); + + /* Send write command, command IO-width is 1 (bit 25/26) */ + spi_w32w(sfcsr | SPI_LEN1 | (0 << 25), SFCSR); + spi_w32w(command << 24, SFDR); + + /* Send address */ + spi_w32w(sfcsr | (sfcsr_addr_len << 28) | (0 << 25), SFCSR); + spi_w32w(to << sfdr_addr_shift, SFDR); + + /* Write Data, 1 byte at a time, if we are not 4-byte aligned */ + if (((long)buffer) % 4) { + spi_w32w(sfcsr | SPI_LEN1, SFCSR); + while (length > 0 && (((long)buffer) % 4)) { + SPI_WAIT_READY; + spi_w32(*(buffer) << 24, SFDR); + buffer += 1; + length -= 1; + } + } + + /* Now we can write 4 bytes at a time */ + SPI_WAIT_READY; + spi_w32w(sfcsr | SPI_LEN4, SFCSR); + while (length >= 4) { + SPI_WAIT_READY; + spi_w32(*((uint32_t *)buffer), SFDR); + buffer += 4; + length -= 4; + } + + /* Final bytes might need to be written 1 byte at a time, again */ + SPI_WAIT_READY; + spi_w32w(sfcsr | SPI_LEN1, SFCSR); + while (length > 0) { + SPI_WAIT_READY; + spi_w32(*(buffer) << 24, SFDR); + buffer++; + length--; + } + return len; +} + +static ssize_t rtl838x_nor_write(struct spi_nor *nor, loff_t to, size_t len, + const u_char *buffer) +{ + int ret = 0; + uint32_t offset = 0; + struct rtl838x_nor *rtl838x_nor = nor->priv; + size_t l = len; + uint8_t cmd = SPINOR_OP_PP; + + /* Do write in 4-byte mode on large Macronix chips */ + if (rtl838x_nor->fourByteMode) { + cmd = SPINOR_OP_PP_4B; + spi_4b_set(rtl838x_nor, true); + } + + pr_debug("In %s %8x to: %llx\n", __func__, + (unsigned int) rtl838x_nor, to); + + while (l >= SPI_MAX_TRANSFER_SIZE) { + while + (rtl838x_nor_get_SR(rtl838x_nor) & SPI_WIP); + do { + spi_write_enable(rtl838x_nor); + } while (!(rtl838x_nor_get_SR(rtl838x_nor) & SPI_WEL)); + ret = rtl838x_do_4b_write(rtl838x_nor, to + offset, + SPI_MAX_TRANSFER_SIZE, buffer+offset, cmd); + l -= SPI_MAX_TRANSFER_SIZE; + offset += SPI_MAX_TRANSFER_SIZE; + } + + if (l > 0) { + while + (rtl838x_nor_get_SR(rtl838x_nor) & SPI_WIP); + do { + spi_write_enable(rtl838x_nor); + } while (!(rtl838x_nor_get_SR(rtl838x_nor) & SPI_WEL)); + ret = rtl838x_do_4b_write(rtl838x_nor, to+offset, + len, buffer+offset, cmd); + } + + return len; +} + +static ssize_t rtl838x_nor_read(struct spi_nor *nor, loff_t from, + size_t length, u_char *buffer) +{ + uint32_t offset = 0; + uint8_t cmd = SPINOR_OP_READ_FAST; + size_t l = length; + struct rtl838x_nor *rtl838x_nor = nor->priv; + + /* Do fast read in 3, or 4-byte mode on large Macronix chips */ + if (rtl838x_nor->fourByteMode) { + cmd = SPINOR_OP_READ_FAST_4B; + spi_4b_set(rtl838x_nor, true); + } + + /* TODO: do timeout and return error */ + pr_debug("Waiting for pending writes\n"); + while + (rtl838x_nor_get_SR(rtl838x_nor) & SPI_WIP); + do { + spi_write_enable(rtl838x_nor); + } while (!(rtl838x_nor_get_SR(rtl838x_nor) & SPI_WEL)); + + pr_debug("cmd is %d\n", cmd); + pr_debug("%s: addr %.8llx to addr %.8x, cmd %.8x, size %d\n", __func__, + from, (u32)buffer, (u32)cmd, length); + + while (l >= SPI_MAX_TRANSFER_SIZE) { + rtl838x_do_4bf_read(rtl838x_nor, from + offset, + SPI_MAX_TRANSFER_SIZE, buffer+offset, cmd); + l -= SPI_MAX_TRANSFER_SIZE; + offset += SPI_MAX_TRANSFER_SIZE; + } + + if (l > 0) + rtl838x_do_4bf_read(rtl838x_nor, from + offset, l, buffer+offset, cmd); + + return length; +} + +static int rtl838x_erase(struct spi_nor *nor, loff_t offs) +{ + struct rtl838x_nor *rtl838x_nor = nor->priv; + int sfcsr_addr_len = rtl838x_nor->fourByteMode ? 0x3 : 0x2; + int sfdr_addr_shift = rtl838x_nor->fourByteMode ? 0 : 8; + uint32_t sfcsr; + uint8_t cmd = SPINOR_OP_SE; + + pr_debug("Erasing sector at %llx\n", offs); + + /* Do erase in 4-byte mode on large Macronix chips */ + if (rtl838x_nor->fourByteMode) { + cmd = SPINOR_OP_SE_4B; + spi_4b_set(rtl838x_nor, true); + } + /* TODO: do timeout and return error */ + while + (rtl838x_nor_get_SR(rtl838x_nor) & SPI_WIP); + do { + spi_write_enable(rtl838x_nor); + } while (!(rtl838x_nor_get_SR(rtl838x_nor) & SPI_WEL)); + + sfcsr = spi_prep(rtl838x_nor); + + /* Send erase command, command IO-width is 1 (bit 25/26) */ + spi_w32w(sfcsr | SPI_LEN1 | (0 << 25), SFCSR); + spi_w32w(cmd << 24, SFDR); + + /* Send address */ + spi_w32w(sfcsr | (sfcsr_addr_len << 28) | (0 << 25), SFCSR); + spi_w32w(offs << sfdr_addr_shift, SFDR); + + return 0; +} + +static int rtl838x_nor_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len) +{ + int length = len; + u8 *buffer = buf; + uint32_t sfcsr, sfdr; + struct rtl838x_nor *rtl838x_nor = nor->priv; + + pr_debug("In %s: opcode %x, len %x\n", __func__, opcode, len); + + sfcsr = spi_prep(rtl838x_nor); + sfdr = opcode << 24; + + sfcsr |= SPI_LEN1; + + spi_w32w(sfcsr, SFCSR); + spi_w32w(sfdr, SFDR); + + while (length > 0) { + SPI_WAIT_READY; + *(buffer) = spi_r32(SFDR) >> 24; + buffer++; + length--; + } + + return len; +} + +static int rtl838x_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len) +{ + uint32_t sfcsr, sfdr; + struct rtl838x_nor *rtl838x_nor = nor->priv; + + pr_debug("In %s, opcode %x, len %x\n", __func__, opcode, len); + sfcsr = spi_prep(rtl838x_nor); + sfdr = opcode << 24; + + if (len == 1) { /* SPINOR_OP_WRSR */ + sfdr |= buf[0]; + sfcsr |= SPI_LEN2; + } + spi_w32w(sfcsr, SFCSR); + spi_w32w(sfdr, SFDR); + return 0; +} + +static int spi_enter_sio(struct spi_nor *nor) +{ + uint32_t sfcsr, sfcr2, sfdr; + uint32_t ret = 0, reg = 0, size_bits; + struct rtl838x_nor *rtl838x_nor = nor->priv; + + pr_debug("In %s\n", __func__); + rtl838x_nor->io_status = 0; + sfdr = SPI_C_RSTQIO << 24; + sfcsr = spi_prep(rtl838x_nor); + + reg = spi_r32(SFCR2); + pr_debug("SFCR2: %x, size %x, rdopt: %x\n", reg, SFCR2_GETSIZE(reg), + (reg & SFCR2_RDOPT)); + size_bits = rtl838x_nor->fourByteMode ? SFCR2_SIZE(0x6) : SFCR2_SIZE(0x7); + + sfcr2 = SFCR2_HOLD_TILL_SFDR2 | size_bits + | (reg & SFCR2_RDOPT) | SFCR2_CMDIO(0) + | SFCR2_ADDRIO(0) | SFCR2_DUMMYCYCLE(4) + | SFCR2_DATAIO(0) | SFCR2_SFCMD(SPINOR_OP_READ_FAST); + pr_debug("SFCR2: %x, size %x\n", reg, SFCR2_GETSIZE(reg)); + + SPI_WAIT_READY; + spi_w32w(sfcr2, SFCR2); + spi_w32w(sfcsr, SFCSR); + spi_w32w(sfdr, SFDR); + + spi_w32_mask(SFCR2_HOLD_TILL_SFDR2, 0, SFCR2); + rtl838x_nor->io_status &= ~IOSTATUS_CIO_MASK; + rtl838x_nor->io_status |= CIO1; + + spi_prep(rtl838x_nor); + + return ret; +} + +int rtl838x_spi_nor_scan(struct spi_nor *nor, const char *name) +{ + static const struct spi_nor_hwcaps hwcaps = { + .mask = SNOR_HWCAPS_READ | SNOR_HWCAPS_PP + | SNOR_HWCAPS_READ_FAST + }; + + struct rtl838x_nor *rtl838x_nor = nor->priv; + + pr_debug("In %s\n", __func__); + + spi_w32_mask(0, SFCR_EnableWBO, SFCR); + spi_w32_mask(0, SFCR_EnableRBO, SFCR); + + rtl838x_nor->flags = CS0 | R_MODE; + + spi_nor_scan(nor, NULL, &hwcaps); + pr_debug("------------- Got size: %llx\n", nor->mtd.size); + + return 0; +} + +int rtl838x_nor_init(struct rtl838x_nor *rtl838x_nor, + struct device_node *flash_node) +{ + int ret; + struct spi_nor *nor; + + pr_info("%s called\n", __func__); + nor = &rtl838x_nor->nor; + nor->dev = rtl838x_nor->dev; + nor->priv = rtl838x_nor; + spi_nor_set_flash_node(nor, flash_node); + + nor->read_reg = rtl838x_nor_read_reg; + nor->write_reg = rtl838x_nor_write_reg; + nor->read = rtl838x_nor_read; + nor->write = rtl838x_nor_write; + nor->erase = rtl838x_erase; + nor->mtd.name = "rtl838x_nor"; + nor->erase_opcode = rtl838x_nor->fourByteMode ? SPINOR_OP_SE_4B + : SPINOR_OP_SE; + /* initialized with NULL */ + ret = rtl838x_spi_nor_scan(nor, NULL); + if (ret) + return ret; + + spi_enter_sio(nor); + spi_write_disable(rtl838x_nor); + + ret = mtd_device_parse_register(&nor->mtd, NULL, NULL, NULL, 0); + return ret; +} + +static int rtl838x_nor_drv_probe(struct platform_device *pdev) +{ + struct device_node *flash_np; + struct resource *res; + int ret; + struct rtl838x_nor *rtl838x_nor; + int addrMode; + + pr_info("Initializing rtl838x_nor_driver\n"); + if (!pdev->dev.of_node) { + dev_err(&pdev->dev, "No DT found\n"); + return -EINVAL; + } + + rtl838x_nor = devm_kzalloc(&pdev->dev, sizeof(*rtl838x_nor), GFP_KERNEL); + if (!rtl838x_nor) + return -ENOMEM; + platform_set_drvdata(pdev, rtl838x_nor); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + rtl838x_nor->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR((void *)rtl838x_nor->base)) + return PTR_ERR((void *)rtl838x_nor->base); + + pr_info("SPI resource base is %08x\n", (u32)rtl838x_nor->base); + rtl838x_nor->dev = &pdev->dev; + + /* only support one attached flash */ + flash_np = of_get_next_available_child(pdev->dev.of_node, NULL); + if (!flash_np) { + dev_err(&pdev->dev, "no SPI flash device to configure\n"); + ret = -ENODEV; + goto nor_free; + } + + /* Get the 3/4 byte address mode as configure by bootloader */ + if (soc_info.family == RTL8390_FAMILY_ID) + addrMode = rtl8390_get_addr_mode(rtl838x_nor); + else + addrMode = rtl838x_get_addr_mode(rtl838x_nor); + pr_info("Address mode is %d bytes\n", addrMode); + if (addrMode == 4) + rtl838x_nor->fourByteMode = true; + + ret = rtl838x_nor_init(rtl838x_nor, flash_np); + +nor_free: + return ret; +} + +static int rtl838x_nor_drv_remove(struct platform_device *pdev) +{ +/* struct rtl8xx_nor *rtl838x_nor = platform_get_drvdata(pdev); */ + return 0; +} + +static const struct of_device_id rtl838x_nor_of_ids[] = { + { .compatible = "realtek,rtl838x-nor"}, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, rtl838x_nor_of_ids); + +static struct platform_driver rtl838x_nor_driver = { + .probe = rtl838x_nor_drv_probe, + .remove = rtl838x_nor_drv_remove, + .driver = { + .name = "rtl838x-nor", + .pm = NULL, + .of_match_table = rtl838x_nor_of_ids, + }, +}; + +module_platform_driver(rtl838x_nor_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("RTL838x SPI NOR Flash Driver"); diff --git a/target/linux/rtl838x/files-5.4/drivers/mtd/spi-nor/rtl838x-spi.h b/target/linux/rtl838x/files-5.4/drivers/mtd/spi-nor/rtl838x-spi.h new file mode 100644 index 0000000000..1209d47b02 --- /dev/null +++ b/target/linux/rtl838x/files-5.4/drivers/mtd/spi-nor/rtl838x-spi.h @@ -0,0 +1,111 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2009 Realtek Semiconductor Corp. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _RTL838X_SPI_H +#define _RTL838X_SPI_H + + +/* + * Register access macros + */ + +#define spi_r32(reg) __raw_readl(rtl838x_nor->base + reg) +#define spi_w32(val, reg) __raw_writel(val, rtl838x_nor->base + reg) +#define spi_w32_mask(clear, set, reg) \ + spi_w32((spi_r32(reg) & ~(clear)) | (set), reg) + +#define SPI_WAIT_READY do { \ + } while (!(spi_r32(SFCSR) & SFCSR_SPI_RDY)) + +#define spi_w32w(val, reg) do { \ + __raw_writel(val, rtl838x_nor->base + reg); \ + SPI_WAIT_READY; \ + } while (0) + +#define SFCR (0x00) /*SPI Flash Configuration Register*/ + #define SFCR_CLK_DIV(val) ((val)<<29) + #define SFCR_EnableRBO (1<<28) + #define SFCR_EnableWBO (1<<27) + #define SFCR_SPI_TCS(val) ((val)<<23) /*4 bit, 1111 */ + +#define SFCR2 (0x04) /*For memory mapped I/O */ + #define SFCR2_SFCMD(val) ((val)<<24) /*8 bit, 1111_1111 */ + #define SFCR2_SIZE(val) ((val)<<21) /*3 bit, 111 */ + #define SFCR2_RDOPT (1<<20) + #define SFCR2_CMDIO(val) ((val)<<18) /*2 bit, 11 */ + #define SFCR2_ADDRIO(val) ((val)<<16) /*2 bit, 11 */ + #define SFCR2_DUMMYCYCLE(val) ((val)<<13) /*3 bit, 111 */ + #define SFCR2_DATAIO(val) ((val)<<11) /*2 bit, 11 */ + #define SFCR2_HOLD_TILL_SFDR2 (1<<10) + #define SFCR2_GETSIZE(x) (((x)&0x00E00000)>>21) + +#define SFCSR (0x08) /*SPI Flash Control&Status Register*/ + #define SFCSR_SPI_CSB0 (1<<31) + #define SFCSR_SPI_CSB1 (1<<30) + #define SFCSR_LEN(val) ((val)<<28) /*2 bits*/ + #define SFCSR_SPI_RDY (1<<27) + #define SFCSR_IO_WIDTH(val) ((val)<<25) /*2 bits*/ + #define SFCSR_CHIP_SEL (1<<24) + #define SFCSR_CMD_BYTE(val) ((val)<<16) /*8 bit, 1111_1111 */ + +#define SFDR (0x0C) /*SPI Flash Data Register*/ +#define SFDR2 (0x10) /*SPI Flash Data Register - for post SPI bootup setting*/ + #define SPI_CS_INIT (SFCSR_SPI_CSB0 | SFCSR_SPI_CSB1 | SPI_LEN1) + #define SPI_CS0 SFCSR_SPI_CSB0 + #define SPI_CS1 SFCSR_SPI_CSB1 + #define SPI_eCS0 ((SFCSR_SPI_CSB1)) /*and SFCSR to active CS0*/ + #define SPI_eCS1 ((SFCSR_SPI_CSB0)) /*and SFCSR to active CS1*/ + + #define SPI_WIP (1) /* Write In Progress */ + #define SPI_WEL (1<<1) /* Write Enable Latch*/ + #define SPI_SST_QIO_WIP (1<<7) /* SST QIO Flash Write In Progress */ + #define SPI_LEN_INIT 0xCFFFFFFF /* and SFCSR to init */ + #define SPI_LEN4 0x30000000 /* or SFCSR to set */ + #define SPI_LEN3 0x20000000 /* or SFCSR to set */ + #define SPI_LEN2 0x10000000 /* or SFCSR to set */ + #define SPI_LEN1 0x00000000 /* or SFCSR to set */ + #define SPI_SETLEN(val) do { \ + SPI_REG(SFCSR) &= 0xCFFFFFFF; \ + SPI_REG(SFCSR) |= (val-1)<<28; \ + } while (0) +/* + * SPI interface control + */ +#define RTL8390_SOC_SPI_MMIO_CONF (0x04) + +#define IOSTATUS_CIO_MASK (0x00000038) + +/* Chip select: bits 4-7*/ +#define CS0 (1<<4) +#define R_MODE 0x04 + +/* io_status */ +#define IO1 (1<<0) +#define IO2 (1<<1) +#define CIO1 (1<<3) +#define CIO2 (1<<4) +#define CMD_IO1 (1<<6) +#define W_ADDR_IO1 ((1)<<12) +#define R_ADDR_IO2 ((2)<<9) +#define R_DATA_IO2 ((2)<<15) +#define W_DATA_IO1 ((1)<<18) + +/* Commands */ +#define SPI_C_RSTQIO 0xFF + +#define SPI_MAX_TRANSFER_SIZE 256 + +#endif /* _RTL838X_SPI_H */ diff --git a/target/linux/rtl838x/files-5.4/drivers/net/dsa/rtl838x.h b/target/linux/rtl838x/files-5.4/drivers/net/dsa/rtl838x.h new file mode 100644 index 0000000000..127a31dca1 --- /dev/null +++ b/target/linux/rtl838x/files-5.4/drivers/net/dsa/rtl838x.h @@ -0,0 +1,188 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _RTL838X_H +#define _RTL838X_H + +#include + +/* + * Register definition + */ +#define RTL838X_CPU_PORT 28 +#define RTL839X_CPU_PORT 52 + +#define RTL838X_MAC_PORT_CTRL(port) (0xd560 + (((port) << 7))) +#define RTL839X_MAC_PORT_CTRL(port) (0x8004 + (((port) << 7))) +#define RTL838X_RST_GLB_CTRL_0 (0x003c) +#define RTL838X_MAC_FORCE_MODE_CTRL (0xa104) +#define RTL839X_MAC_FORCE_MODE_CTRL (0x02bc) + +#define RTL838X_DMY_REG31 (0x3b28) +#define RTL838X_SDS_MODE_SEL (0x0028) +#define RTL838X_SDS_CFG_REG (0x0034) +#define RTL838X_INT_MODE_CTRL (0x005c) +#define RTL838X_CHIP_INFO (0x00d8) +#define RTL839X_CHIP_INFO (0x0ff4) +#define RTL838X_SDS4_REG28 (0xef80) +#define RTL838X_SDS4_DUMMY0 (0xef8c) +#define RTL838X_SDS5_EXT_REG6 (0xf18c) +#define RTL838X_PORT_ISO_CTRL(port) (0x4100 + ((port) << 2)) +#define RTL839X_PORT_ISO_CTRL(port) (0x1400 + ((port) << 3)) +#define RTL8380_SDS4_FIB_REG0 (0xF800) +#define RTL838X_STAT_PORT_STD_MIB (0x1200) +#define RTL839X_STAT_PORT_STD_MIB (0xC000) +#define RTL838X_STAT_RST (0x3100) +#define RTL839X_STAT_RST (0xF504) +#define RTL838X_STAT_PORT_RST (0x3104) +#define RTL839X_STAT_PORT_RST (0xF508) +#define RTL838X_STAT_CTRL (0x3108) +#define RTL839X_STAT_CTRL (0x04cc) + +/* Registers of the internal Serdes of the 8380 */ +#define MAPLE_SDS4_REG0r RTL838X_SDS4_REG28 +#define MAPLE_SDS5_REG0r (RTL838X_SDS4_REG28 + 0x100) +#define MAPLE_SDS4_REG3r RTL838X_SDS4_DUMMY0 +#define MAPLE_SDS5_REG3r (RTL838X_SDS4_REG28 + 0x100) +#define MAPLE_SDS4_FIB_REG0r (RTL838X_SDS4_REG28 + 0x880) +#define MAPLE_SDS5_FIB_REG0r (RTL838X_SDS4_REG28 + 0x980) + +/* VLAN registers */ +#define RTL838X_VLAN_PROFILE(idx) (0x3A88 + ((idx) << 2)) +#define RTL838X_VLAN_PORT_EGR_FLTR (0x3A84) +#define RTL838X_VLAN_PORT_PB_VLAN(port) (0x3C00 + ((port) << 2)) +#define RTL838X_VLAN_PORT_IGR_FLTR_0 (0x3A7C) +#define RTL838X_VLAN_PORT_IGR_FLTR_1 (0x3A7C + 4) + +/* Table 0/1 access registers */ +#define RTL838X_TBL_ACCESS_CTRL_0 (0x6914) +#define RTL838X_TBL_ACCESS_DATA_0(idx) (0x6918 + ((idx) << 2)) +#define RTL838X_TBL_ACCESS_CTRL_1 (0xA4C8) +#define RTL838X_TBL_ACCESS_DATA_1(idx) (0xA4CC + ((idx) << 2)) +#define RTL839X_TBL_ACCESS_CTRL_0 (0x1190) +#define RTL839X_TBL_ACCESS_DATA_0(idx) (0x1194 + ((idx) << 2)) +#define RTL839X_TBL_ACCESS_CTRL_1 (0x6b80) +#define RTL839X_TBL_ACCESS_DATA_1(idx) (0x6b84 + ((idx) << 2)) + +/* MAC handling */ +#define RTL838X_MAC_LINK_STS (0xa188) +#define RTL839X_MAC_LINK_STS (0x0390) +#define RTL838X_MAC_LINK_SPD_STS(port) (0xa190 + (((port >> 4) << 2))) +#define RTL838X_MAC_LINK_DUP_STS (0xa19c) +#define RTL838X_MAC_TX_PAUSE_STS (0xa1a0) +#define RTL838X_MAC_RX_PAUSE_STS (0xa1a4) +#define RTL838X_EEE_TX_TIMER_GIGA_CTRL (0xaa04) +#define RTL838X_EEE_TX_TIMER_GELITE_CTRL (0xaa08) + +/* MAC link state bits */ +#define FORCE_EN (1 << 0) +#define FORCE_LINK_EN (1 << 1) +#define NWAY_EN (1 << 2) +#define DUPLX_MODE (1 << 3) +#define TX_PAUSE_EN (1 << 6) +#define RX_PAUSE_EN (1 << 7) + +/* EEE */ +#define RTL838X_MAC_EEE_ABLTY (0xa1a8) +#define RTL838X_EEE_PORT_TX_EN (0x014c) +#define RTL838X_EEE_PORT_RX_EN (0x0150) +#define RTL838X_EEE_CLK_STOP_CTRL (0x0148) + +/* L2 functionality */ +#define RTL838X_L2_CTRL_0 (0x3200) +#define RTL839X_L2_CTRL_0 (0x3800) +#define RTL838X_L2_CTRL_1 (0x3204) +#define RTL839X_L2_CTRL_1 (0x3804) +#define RTL838X_L2_PORT_AGING_OUT (0x3358) +#define RTL839X_L2_PORT_AGING_OUT (0x3b74) +#define RTL838X_TBL_ACCESS_L2_CTRL (0x6900) +#define RTL839X_TBL_ACCESS_L2_CTRL (0x1180) +#define RTL838X_TBL_ACCESS_L2_DATA(idx) (0x6908 + ((idx) << 2)) +#define RTL838X_TBL_ACCESS_L2_DATA(idx) (0x6908 + ((idx) << 2)) +#define RTL838X_L2_TBL_FLUSH_CTRL (0x3370) +#define RTL839X_L2_TBL_FLUSH_CTRL (0x3ba0) + +/* Port Mirroring */ +#define RTL838X_MIR_CTRL(grp) (0x5D00 + (((grp) << 2))) +#define RTL838X_MIR_DPM_CTRL(grp) (0x5D20 + (((grp) << 2))) +#define RTL838X_MIR_SPM_CTRL(grp) (0x5D10 + (((grp) << 2))) + +enum phy_type { + PHY_NONE = 0, + PHY_RTL838X_SDS = 1, + PHY_RTL8218B_INT = 2, + PHY_RTL8218B_EXT = 3, + PHY_RTL8214FC = 4 +}; + +struct rtl838x_port { + bool enable; + u64 pm; + u16 pvid; + bool eee_enabled; + enum phy_type phy; +}; + +struct rtl838x_vlan_info { + u64 untagged_ports; + u64 tagged_ports; + u32 vlan_conf; +}; + +struct rtl838x_switch_priv; + +struct rtl838x_reg { + void (*mask_port_reg)(u64 clear, u64 set, int reg); + void (*set_port_reg)(u64 set, int reg); + u64 (*get_port_reg)(int reg); + int stat_port_rst; + int stat_rst; + int (*stat_port_std_mib)(int p); + void (*mask_port_iso_ctrl)(u64 clear, u64 set, int port); + void (*set_port_iso_ctrl)(u64 set, int port); + int l2_ctrl_0; + int l2_ctrl_1; + int l2_port_aging_out; + int smi_poll_ctrl; + int l2_tbl_flush_ctrl; + void (*exec_tbl0_cmd)(u32 cmd); + void (*exec_tbl1_cmd)(u32 cmd); + int (*tbl_access_data_0)(int i); + int isr_glb_src; + int isr_port_link_sts_chg; + int imr_port_link_sts_chg; + int imr_glb; + void (*vlan_tables_read)(u32 vlan, struct rtl838x_vlan_info *info); + void (*vlan_set_tagged)(u32 vlan, u64 portmask, u32 conf); + void (*vlan_set_untagged)(u32 vlan, u64 portmask); + int (*mac_force_mode_ctrl)(int port); + int rst_glb_ctrl; +}; + +struct rtl838x_switch_priv { + /* Switch operation */ + struct dsa_switch *ds; + struct device *dev; + u16 id; + u16 family_id; + char version; + struct rtl838x_port ports[54]; /* TODO: correct size! */ + struct mutex reg_mutex; + int link_state_irq; + int mirror_group_ports[4]; + struct mii_bus *mii_bus; + const struct rtl838x_reg *r; + u8 cpu_port; + u8 port_mask; +}; + +extern struct rtl838x_soc_info soc_info; +extern void rtl8380_sds_rst(int mac); + +extern int rtl838x_write_phy(u32 port, u32 page, u32 reg, u32 val); +extern int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val); +extern int rtl838x_read_phy(u32 port, u32 page, u32 reg, u32 *val); +extern int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val); +extern int rtl838x_write_mmd_phy(u32 port, u32 addr, u32 reg, u32 val); +extern int rtl838x_read_mmd_phy(u32 port, u32 addr, u32 reg, u32 *val); + +#endif /* _RTL838X_H */ diff --git a/target/linux/rtl838x/files-5.4/drivers/net/dsa/rtl838x_phy.c b/target/linux/rtl838x/files-5.4/drivers/net/dsa/rtl838x_phy.c new file mode 100644 index 0000000000..4440dc99cd --- /dev/null +++ b/target/linux/rtl838x/files-5.4/drivers/net/dsa/rtl838x_phy.c @@ -0,0 +1,1286 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Realtek RTL838X Ethernet MDIO interface driver + * + * Copyright (C) 2020 B. Koblitz + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include "rtl838x.h" + +/* External RTL8218B and RTL8214FC IDs are identical */ +#define PHY_ID_RTL8214C 0x001cc942 +#define PHY_ID_RTL8214FC 0x001cc981 +#define PHY_ID_RTL8218B_E 0x001cc981 +#define PHY_ID_RTL8218B_I 0x001cca40 +#define PHY_ID_RTL8390_GENERIC 0x001ccab0 + +struct __attribute__ ((__packed__)) part { + uint16_t start; + uint8_t wordsize; + uint8_t words; +}; + +struct __attribute__ ((__packed__)) fw_header { + uint32_t magic; + uint32_t phy; + uint32_t checksum; + uint32_t version; + struct part parts[10]; +}; + +#define FIRMWARE_838X_8380_1 "rtl838x_phy/rtl838x_8380.fw" +#define FIRMWARE_838X_8214FC_1 "rtl838x_phy/rtl838x_8214fc.fw" +#define FIRMWARE_838X_8218b_1 "rtl838x_phy/rtl838x_8218b.fw" + +static const struct firmware rtl838x_8380_fw; +static const struct firmware rtl838x_8214fc_fw; +static const struct firmware rtl838x_8218b_fw; + +struct rtl838x_phy_priv { + char *name; +}; + +static int read_phy(u32 port, u32 page, u32 reg, u32 *val) +{ + if (soc_info.family == RTL8390_FAMILY_ID) + return rtl839x_read_phy(port, page, reg, val); + else + return rtl838x_read_phy(port, page, reg, val); +} + +static int write_phy(u32 port, u32 page, u32 reg, u32 val) +{ + if (soc_info.family == RTL8390_FAMILY_ID) + return rtl839x_write_phy(port, page, reg, val); + else + return rtl838x_write_phy(port, page, reg, val); +} + +static void rtl8380_int_phy_on_off(int mac, bool on) +{ + u32 val; + + read_phy(mac, 0, 0, &val); + if (on) + write_phy(mac, 0, 0, val & ~(1 << 11)); + else + write_phy(mac, 0, 0, val | (1 << 11)); +} + +static void rtl8380_rtl8214fc_on_off(int mac, bool on) +{ + u32 val; + + /* fiber ports */ + write_phy(mac, 4095, 30, 3); + read_phy(mac, 0, 16, &val); + if (on) + write_phy(mac, 0, 16, val & ~(1 << 11)); + else + write_phy(mac, 0, 16, val | (1 << 11)); + + /* copper ports */ + write_phy(mac, 4095, 30, 1); + read_phy(mac, 0, 16, &val); + if (on) + write_phy(mac, 0xa40, 16, val & ~(1 << 11)); + else + write_phy(mac, 0xa40, 16, val | (1 << 11)); +} + +static void rtl8380_phy_reset(int mac) +{ + u32 val; + + read_phy(mac, 0, 0, &val); + write_phy(mac, 0, 0, val | (0x1 << 15)); +} + +void rtl8380_sds_rst(int mac) +{ + u32 offset = (mac == 24) ? 0 : 0x100; + + sw_w32_mask(1 << 11, 0, RTL8380_SDS4_FIB_REG0 + offset); + sw_w32_mask(0x3, 0, RTL838X_SDS4_REG28 + offset); + sw_w32_mask(0x3, 0x3, RTL838X_SDS4_REG28 + offset); + sw_w32_mask(0, 0x1 << 6, RTL838X_SDS4_DUMMY0 + offset); + sw_w32_mask(0x1 << 6, 0, RTL838X_SDS4_DUMMY0 + offset); + pr_info("SERDES reset: %d\n", mac); +} + +static struct fw_header * +rtl838x_request_fw(struct phy_device *phydev, const struct firmware *fw, + const char *name) +{ + struct device *dev = &phydev->mdio.dev; + int err; + struct fw_header *h; + uint32_t checksum, my_checksum; + + err = request_firmware(&fw, name, dev); + if (err < 0) + goto out; + + if (fw->size < sizeof(struct fw_header)) { + pr_err("Firmware size too small.\n"); + err = -EINVAL; + goto out; + } + + h = (struct fw_header *) fw->data; + pr_info("Firmware loaded. Size %d, magic: %08x\n", fw->size, h->magic); + + if (h->phy != 0x83800000) { + pr_err("Wrong firmware file: PHY mismatch.\n"); + goto out; + } + + checksum = h->checksum; + h->checksum = 0; + my_checksum = ~crc32(0xFFFFFFFFU, fw->data, fw->size); + if (checksum != my_checksum) { + pr_err("Firmware checksum mismatch.\n"); + err = -EINVAL; + goto out; + } + h->checksum = checksum; + + return h; +out: + dev_err(dev, "Unable to load firmware %s (%d)\n", name, err); + return NULL; +} + +static int rtl8390_configure_generic(struct phy_device *phydev) +{ + u32 val, phy_id; + int mac = phydev->mdio.addr; + + read_phy(mac, 0, 2, &val); + phy_id = val << 16; + read_phy(mac, 0, 3, &val); + phy_id |= val; + pr_debug("Phy on MAC %d: %x\n", mac, phy_id); + + /* Read internal PHY ID */ + write_phy(mac, 31, 27, 0x0002); + read_phy(mac, 31, 28, &val); + + /* Internal RTL8218B, version 2 */ + phydev_info(phydev, "Detected unknown %x\n", val); + return 0; +} + +static int rtl8380_configure_int_rtl8218b(struct phy_device *phydev) +{ + u32 val, phy_id; + int i, p, ipd_flag; + int mac = phydev->mdio.addr; + struct fw_header *h; + u32 *rtl838x_6275B_intPhy_perport; + u32 *rtl8218b_6276B_hwEsd_perport; + + + read_phy(mac, 0, 2, &val); + phy_id = val << 16; + read_phy(mac, 0, 3, &val); + phy_id |= val; + pr_debug("Phy on MAC %d: %x\n", mac, phy_id); + + /* Read internal PHY ID */ + write_phy(mac, 31, 27, 0x0002); + read_phy(mac, 31, 28, &val); + if (val != 0x6275) { + phydev_err(phydev, "Expected internal RTL8218B, found PHY-ID %x\n", val); + return -1; + } + + /* Internal RTL8218B, version 2 */ + phydev_info(phydev, "Detected internal RTL8218B\n"); + + h = rtl838x_request_fw(phydev, &rtl838x_8380_fw, FIRMWARE_838X_8380_1); + if (!h) + return -1; + + if (h->phy != 0x83800000) { + phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n"); + return -1; + } + + rtl838x_6275B_intPhy_perport = (void *)h + sizeof(struct fw_header) + + h->parts[8].start; + + rtl8218b_6276B_hwEsd_perport = (void *)h + sizeof(struct fw_header) + + h->parts[9].start; + + if (sw_r32(RTL838X_DMY_REG31) == 0x1) + ipd_flag = 1; + + read_phy(mac, 0, 0, &val); + if (val & (1 << 11)) + rtl8380_int_phy_on_off(mac, true); + else + rtl8380_phy_reset(mac); + msleep(100); + + /* Ready PHY for patch */ + for (p = 0; p < 8; p++) { + write_phy(mac + p, 0xfff, 0x1f, 0x0b82); + write_phy(mac + p, 0xfff, 0x10, 0x0010); + } + msleep(500); + for (p = 0; p < 8; p++) { + for (i = 0; i < 100 ; i++) { + read_phy(mac + p, 0x0b80, 0x10, &val); + if (val & 0x40) + break; + } + if (i >= 100) { + phydev_err(phydev, + "ERROR: Port %d not ready for patch.\n", + mac + p); + return -1; + } + } + for (p = 0; p < 8; p++) { + i = 0; + while (rtl838x_6275B_intPhy_perport[i * 2]) { + write_phy(mac + p, 0xfff, + rtl838x_6275B_intPhy_perport[i * 2], + rtl838x_6275B_intPhy_perport[i * 2 + 1]); + i++; + } + i = 0; + while (rtl8218b_6276B_hwEsd_perport[i * 2]) { + write_phy(mac + p, 0xfff, + rtl8218b_6276B_hwEsd_perport[i * 2], + rtl8218b_6276B_hwEsd_perport[i * 2 + 1]); + i++; + } + } + return 0; +} + +static int rtl8380_configure_ext_rtl8218b(struct phy_device *phydev) +{ + u32 val, ipd, phy_id; + int i, l; + int mac = phydev->mdio.addr; + struct fw_header *h; + u32 *rtl8380_rtl8218b_perchip; + u32 *rtl8218B_6276B_rtl8380_perport; + u32 *rtl8380_rtl8218b_perport; + + if (soc_info.family == RTL8380_FAMILY_ID && mac != 0 && mac != 16) { + phydev_err(phydev, "External RTL8218B must have PHY-IDs 0 or 16!\n"); + return -1; + } + read_phy(mac, 0, 2, &val); + phy_id = val << 16; + read_phy(mac, 0, 3, &val); + phy_id |= val; + pr_info("Phy on MAC %d: %x\n", mac, phy_id); + + /* Read internal PHY ID */ + write_phy(mac, 31, 27, 0x0002); + read_phy(mac, 31, 28, &val); + if (val != 0x6276) { + phydev_err(phydev, "Expected external RTL8218B, found PHY-ID %x\n", val); + return -1; + } + phydev_info(phydev, "Detected external RTL8218B\n"); + + h = rtl838x_request_fw(phydev, &rtl838x_8218b_fw, FIRMWARE_838X_8218b_1); + if (!h) + return -1; + + if (h->phy != 0x8218b00) { + phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n"); + return -1; + } + + rtl8380_rtl8218b_perchip = (void *)h + sizeof(struct fw_header) + + h->parts[0].start; + + rtl8218B_6276B_rtl8380_perport = (void *)h + sizeof(struct fw_header) + + h->parts[1].start; + + rtl8380_rtl8218b_perport = (void *)h + sizeof(struct fw_header) + + h->parts[2].start; + + read_phy(mac, 0, 0, &val); + if (val & (1 << 11)) + rtl8380_int_phy_on_off(mac, true); + else + rtl8380_phy_reset(mac); + msleep(100); + + /* Get Chip revision */ + write_phy(mac, 0xfff, 0x1f, 0x0); + write_phy(mac, 0xfff, 0x1b, 0x4); + read_phy(mac, 0xfff, 0x1c, &val); + + i = 0; + while (rtl8380_rtl8218b_perchip[i * 3] + && rtl8380_rtl8218b_perchip[i * 3 + 1]) { + write_phy(mac + rtl8380_rtl8218b_perchip[i * 3], + 0xfff, rtl8380_rtl8218b_perchip[i * 3 + 1], + rtl8380_rtl8218b_perchip[i * 3 + 2]); + i++; + } + + /* Enable PHY */ + for (i = 0; i < 8; i++) { + write_phy(mac + i, 0xfff, 0x1f, 0x0000); + write_phy(mac + i, 0xfff, 0x00, 0x1140); + } + mdelay(100); + + /* Request patch */ + for (i = 0; i < 8; i++) { + write_phy(mac + i, 0xfff, 0x1f, 0x0b82); + write_phy(mac + i, 0xfff, 0x10, 0x0010); + } + mdelay(300); + + /* Verify patch readiness */ + for (i = 0; i < 8; i++) { + for (l = 0; l < 100; l++) { + read_phy(mac + i, 0xb80, 0x10, &val); + if (val & 0x40) + break; + } + if (l >= 100) { + phydev_err(phydev, "Could not patch PHY\n"); + return -1; + } + } + + /* Use Broadcast ID method for patching */ + write_phy(mac, 0xfff, 0x1f, 0x0000); + write_phy(mac, 0xfff, 0x1d, 0x0008); + write_phy(mac, 0xfff, 0x1f, 0x0266); + write_phy(mac, 0xfff, 0x16, 0xff00 + mac); + write_phy(mac, 0xfff, 0x1f, 0x0000); + write_phy(mac, 0xfff, 0x1d, 0x0000); + mdelay(1); + + write_phy(mac, 0xfff, 30, 8); + write_phy(mac, 0x26e, 17, 0xb); + write_phy(mac, 0x26e, 16, 0x2); + mdelay(1); + read_phy(mac, 0x26e, 19, &ipd); + write_phy(mac, 0, 30, 0); + ipd = (ipd >> 4) & 0xf; + + i = 0; + while (rtl8218B_6276B_rtl8380_perport[i * 2]) { + write_phy(mac, 0xfff, rtl8218B_6276B_rtl8380_perport[i * 2], + rtl8218B_6276B_rtl8380_perport[i * 2 + 1]); + i++; + } + + /*Disable broadcast ID*/ + write_phy(mac, 0xfff, 0x1f, 0x0000); + write_phy(mac, 0xfff, 0x1d, 0x0008); + write_phy(mac, 0xfff, 0x1f, 0x0266); + write_phy(mac, 0xfff, 0x16, 0x00 + mac); + write_phy(mac, 0xfff, 0x1f, 0x0000); + write_phy(mac, 0xfff, 0x1d, 0x0000); + mdelay(1); + + return 0; +} + +static int rtl8218b_ext_match_phy_device(struct phy_device *phydev) +{ + int addr = phydev->mdio.addr; + + return phydev->phy_id == PHY_ID_RTL8218B_E && addr < 8; +} + + +static int rtl8380_rtl8218b_write_mmd(struct phy_device *phydev, + int devnum, u16 regnum, u16 val) +{ + int addr = phydev->mdio.addr; + + return rtl838x_write_mmd_phy(addr, devnum, regnum, val); +} + +static int rtl8380_rtl8218b_read_mmd(struct phy_device *phydev, + int devnum, u16 regnum) +{ + int ret; + u32 val; + int addr = phydev->mdio.addr; + + ret = rtl838x_read_mmd_phy(addr, devnum, regnum, &val); + if (ret) + return ret; + return val; +} + +static void rtl8380_rtl8214fc_media_set(int mac, bool set_fibre) +{ + int base = mac - (mac % 4); + static int reg[] = {16, 19, 20, 21}; + int val, media, power; + + pr_info("%s: port %d, set_fibre: %d\n", __func__, mac, set_fibre); + write_phy(base, 0xfff, 29, 8); + read_phy(base, 0x266, reg[mac % 4], &val); + + media = (val >> 10) & 0x3; + pr_info("Current media %x\n", media); + if (media & 0x2) { + pr_info("Powering off COPPER\n"); + write_phy(base, 0xfff, 29, 1); + /* Ensure power is off */ + read_phy(base, 0xa40, 16, &power); + if (!(power & (1 << 11))) + write_phy(base, 0xa40, 16, power | (1 << 11)); + } else { + pr_info("Powering off FIBRE"); + write_phy(base, 0xfff, 29, 3); + /* Ensure power is off */ + read_phy(base, 0xa40, 16, &power); + if (!(power & (1 << 11))) + write_phy(base, 0xa40, 16, power | (1 << 11)); + } + + if (set_fibre) { + val |= 1 << 10; + val &= ~(1 << 11); + } else { + val |= 1 << 10; + val |= 1 << 11; + } + write_phy(base, 0xfff, 29, 8); + write_phy(base, 0x266, reg[mac % 4], val); + write_phy(base, 0xfff, 29, 0); + + if (set_fibre) { + pr_info("Powering on FIBRE"); + write_phy(base, 0xfff, 29, 3); + /* Ensure power is off */ + read_phy(base, 0xa40, 16, &power); + if (power & (1 << 11)) + write_phy(base, 0xa40, 16, power & ~(1 << 11)); + } else { + pr_info("Powering on COPPER\n"); + write_phy(base, 0xfff, 29, 1); + /* Ensure power is off */ + read_phy(base, 0xa40, 16, &power); + if (power & (1 << 11)) + write_phy(base, 0xa40, 16, power & ~(1 << 11)); + } + + write_phy(base, 0xfff, 29, 0); +} + +static bool rtl8380_rtl8214fc_media_is_fibre(int mac) +{ + int base = mac - (mac % 4); + static int reg[] = {16, 19, 20, 21}; + u32 val; + + write_phy(base, 0xfff, 29, 8); + read_phy(base, 0x266, reg[mac % 4], &val); + write_phy(base, 0xfff, 29, 0); + if (val & (1 << 11)) + return false; + return true; +} + +static int rtl8380_rtl8214fc_set_port(struct phy_device *phydev, int port) +{ + bool is_fibre = (port == PORT_FIBRE ? true : false); + int addr = phydev->mdio.addr; + + pr_debug("%s port %d to %d\n", __func__, addr, port); + + rtl8380_rtl8214fc_media_set(addr, is_fibre); + return 0; +} + +static int rtl8380_rtl8214fc_get_port(struct phy_device *phydev) +{ + int addr = phydev->mdio.addr; + + pr_debug("%s: port %d\n", __func__, addr); + if (rtl8380_rtl8214fc_media_is_fibre(addr)) + return PORT_FIBRE; + return PORT_MII; +} + +void rtl8380_rtl8214fc_ldps_set(int mac, struct ethtool_eee *e) +{ + +} + +static void rtl8380_rtl8218b_eee_set_u_boot(int port, bool enable) +{ + u32 val; + bool an_enabled; + + /* Set GPHY page to copper */ + write_phy(port, 0, 30, 0x0001); + read_phy(port, 0, 0, &val); + an_enabled = val & (1 << 12); + + if (enable) { + /* 100/1000M EEE Capability */ + write_phy(port, 0, 13, 0x0007); + write_phy(port, 0, 14, 0x003C); + write_phy(port, 0, 13, 0x4007); + write_phy(port, 0, 14, 0x0006); + + read_phy(port, 0x0A43, 25, &val); + val |= 1 << 4; + write_phy(port, 0x0A43, 25, val); + } else { + /* 100/1000M EEE Capability */ + write_phy(port, 0, 13, 0x0007); + write_phy(port, 0, 14, 0x003C); + write_phy(port, 0, 13, 0x0007); + write_phy(port, 0, 14, 0x0000); + + read_phy(port, 0x0A43, 25, &val); + val &= ~(1 << 4); + write_phy(port, 0x0A43, 25, val); + } + + /* Restart AN if enabled */ + if (an_enabled) { + read_phy(port, 0, 0, &val); + val |= (1 << 12) | (1 << 9); + write_phy(port, 0, 0, val); + } + + /* GPHY page back to auto*/ + write_phy(port, 0xa42, 29, 0); +} + +static int rtl8380_rtl8218b_get_eee_u_boot(struct phy_device *phydev, struct ethtool_eee *e) +{ + u32 val; + int addr = phydev->mdio.addr; + + pr_debug("In %s %d\n", __func__, addr); + + /* Set GPHY page to copper */ + write_phy(addr, 0xa42, 29, 0x0001); + + read_phy(addr, 0xa43, 25, &val); + if (e->eee_enabled && (!!(val & (1 << 4)))) + e->eee_enabled = !!(val & (1 << 4)); + else + e->eee_enabled = 0; + + /* GPHY page to auto */ + write_phy(addr, 0xa42, 29, 0x0000); + + return 0; +} + +void rtl8380_rtl8218b_eee_set(int port, bool enable) +{ + u32 val; + bool an_enabled; + + pr_debug("In %s %d, enable %d\n", __func__, port, enable); + /* Set GPHY page to copper */ + write_phy(port, 0xa42, 29, 0x0001); + + read_phy(port, 0, 0, &val); + an_enabled = val & (1 << 12); + + /* MAC based EEE */ + read_phy(port, 0xa43, 25, &val); + val &= ~(1 << 5); + write_phy(port, 0xa43, 25, val); + + /* 100M / 1000M EEE */ + if (enable) + rtl838x_write_mmd_phy(port, 7, 60, 0x6); + else + rtl838x_write_mmd_phy(port, 7, 60, 0); + + /* 500M EEE ability */ + read_phy(port, 0xa42, 20, &val); + if (enable) + val |= 1 << 7; + else + val &= ~(1 << 7); + write_phy(port, 0xa42, 20, val); + + /* Restart AN if enabled */ + if (an_enabled) { + read_phy(port, 0, 0, &val); + val |= (1 << 12) | (1 << 9); + write_phy(port, 0, 0, val); + } + + /* GPHY page back to auto*/ + write_phy(port, 0xa42, 29, 0); +} + +int rtl8380_rtl8218b_get_eee(struct phy_device *phydev, + struct ethtool_eee *e) +{ + u32 val; + int addr = phydev->mdio.addr; + + pr_debug("In %s, port %d\n", __func__, addr); + + /* Set GPHY page to copper */ + write_phy(addr, 0xa42, 29, 0x0001); + + rtl838x_read_mmd_phy(addr, 7, 60, &val); + if (e->eee_enabled && (!!(val & (1 << 7)))) + e->eee_enabled = !!(val & (1 << 7)); + else + e->eee_enabled = 0; + + /* GPHY page to auto */ + write_phy(addr, 0xa42, 29, 0x0000); + + return 0; +} + +void rtl8380_rtl8218b_green_set(int mac, bool enable) +{ + u32 val; + + /* Set GPHY page to copper */ + write_phy(mac, 0xa42, 29, 0x0001); + + write_phy(mac, 0, 27, 0x8011); + read_phy(mac, 0, 28, &val); + if (enable) { + val |= 1 << 9; + write_phy(mac, 0, 27, 0x8011); + write_phy(mac, 0, 28, val); + } else { + val &= ~(1 << 9); + write_phy(mac, 0, 27, 0x8011); + write_phy(mac, 0, 28, val); + } + + /* GPHY page to auto */ + write_phy(mac, 0xa42, 29, 0x0000); +} + +int rtl8380_rtl8214fc_get_green(struct phy_device *phydev, struct ethtool_eee *e) +{ + u32 val; + int addr = phydev->mdio.addr; + + pr_debug("In %s %d\n", __func__, addr); + /* Set GPHY page to copper */ + write_phy(addr, 0xa42, 29, 0x0001); + + write_phy(addr, 0, 27, 0x8011); + read_phy(addr, 0, 28, &val); + if (e->eee_enabled && (!!(val & (1 << 9)))) + e->eee_enabled = !!(val & (1 << 9)); + else + e->eee_enabled = 0; + + /* GPHY page to auto */ + write_phy(addr, 0xa42, 29, 0x0000); + + return 0; +} + +static int rtl8380_rtl8214fc_set_eee(struct phy_device *phydev, + struct ethtool_eee *e) +{ + u32 pollMask; + int addr = phydev->mdio.addr; + + pr_debug("In %s port %d, enabled %d\n", __func__, addr, e->eee_enabled); + + if (rtl8380_rtl8214fc_media_is_fibre(addr)) { + netdev_err(phydev->attached_dev, "Port %d configured for FIBRE", addr); + return -ENOTSUPP; + } + + pollMask = sw_r32(RTL838X_SMI_POLL_CTRL); + sw_w32(0, RTL838X_SMI_POLL_CTRL); + rtl8380_rtl8218b_eee_set_u_boot(addr, (bool) e->eee_enabled); + sw_w32(pollMask, RTL838X_SMI_POLL_CTRL); + return 0; +} + +static int rtl8380_rtl8214fc_get_eee(struct phy_device *phydev, + struct ethtool_eee *e) +{ + int addr = phydev->mdio.addr; + + pr_debug("In %s port %d, enabled %d\n", __func__, addr, e->eee_enabled); + if (rtl8380_rtl8214fc_media_is_fibre(addr)) { + netdev_err(phydev->attached_dev, "Port %d configured for FIBRE", addr); + return -ENOTSUPP; + } + + return rtl8380_rtl8218b_get_eee_u_boot(phydev, e); +} + +static int rtl8380_rtl8218b_set_eee(struct phy_device *phydev, + struct ethtool_eee *e) +{ + u32 pollMask; + int addr = phydev->mdio.addr; + + pr_debug("In %s, port %d, enabled %d\n", __func__, addr, e->eee_enabled); + + pollMask = sw_r32(RTL838X_SMI_POLL_CTRL); + sw_w32(0, RTL838X_SMI_POLL_CTRL); + rtl8380_rtl8218b_eee_set_u_boot(addr, (bool) e->eee_enabled); + sw_w32(pollMask, RTL838X_SMI_POLL_CTRL); + + return 0; +} + +static int rtl8214c_match_phy_device(struct phy_device *phydev) +{ + return phydev->phy_id == PHY_ID_RTL8214C; +} + +static int rtl8380_configure_rtl8214c(struct phy_device *phydev) +{ + u32 phy_id, val; + int mac = phydev->mdio.addr; + + read_phy(mac, 0, 2, &val); + phy_id = val << 16; + read_phy(mac, 0, 3, &val); + phy_id |= val; + pr_debug("Phy on MAC %d: %x\n", mac, phy_id); + + phydev_info(phydev, "Detected external RTL8214C\n"); + + /* GPHY auto conf */ + write_phy(mac, 0xa42, 29, 0); + return 0; +} + +static int rtl8380_configure_rtl8214fc(struct phy_device *phydev) +{ + u32 phy_id, val, page = 0; + int i, l; + int mac = phydev->mdio.addr; + struct fw_header *h; + u32 *rtl8380_rtl8214fc_perchip; + u32 *rtl8380_rtl8214fc_perport; + + read_phy(mac, 0, 2, &val); + phy_id = val << 16; + read_phy(mac, 0, 3, &val); + phy_id |= val; + pr_debug("Phy on MAC %d: %x\n", mac, phy_id); + + /* Read internal PHY id */ + write_phy(mac, 0, 30, 0x0001); + write_phy(mac, 0, 31, 0x0a42); + write_phy(mac, 31, 27, 0x0002); + read_phy(mac, 31, 28, &val); + if (val != 0x6276) { + phydev_err(phydev, "Expected external RTL8214FC, found PHY-ID %x\n", val); + return -1; + } + phydev_info(phydev, "Detected external RTL8214FC\n"); + + h = rtl838x_request_fw(phydev, &rtl838x_8214fc_fw, FIRMWARE_838X_8214FC_1); + if (!h) + return -1; + + if (h->phy != 0x8214fc00) { + phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n"); + return -1; + } + + rtl8380_rtl8214fc_perchip = (void *)h + sizeof(struct fw_header) + + h->parts[0].start; + + rtl8380_rtl8214fc_perport = (void *)h + sizeof(struct fw_header) + + h->parts[1].start; + + /* detect phy version */ + write_phy(mac, 0xfff, 27, 0x0004); + read_phy(mac, 0xfff, 28, &val); + + read_phy(mac, 0, 16, &val); + if (val & (1 << 11)) + rtl8380_rtl8214fc_on_off(mac, true); + else + rtl8380_phy_reset(mac); + + msleep(100); + write_phy(mac, 0, 30, 0x0001); + + i = 0; + while (rtl8380_rtl8214fc_perchip[i * 3] + && rtl8380_rtl8214fc_perchip[i * 3 + 1]) { + if (rtl8380_rtl8214fc_perchip[i * 3 + 1] == 0x1f) + page = rtl8380_rtl8214fc_perchip[i * 3 + 2]; + if (rtl8380_rtl8214fc_perchip[i * 3 + 1] == 0x13 && page == 0x260) { + read_phy(mac + rtl8380_rtl8214fc_perchip[i * 3], 0x260, 13, &val); + val = (val & 0x1f00) | (rtl8380_rtl8214fc_perchip[i * 3 + 2] + & 0xe0ff); + write_phy(mac + rtl8380_rtl8214fc_perchip[i * 3], + 0xfff, rtl8380_rtl8214fc_perchip[i * 3 + 1], val); + } else { + write_phy(mac + rtl8380_rtl8214fc_perchip[i * 3], + 0xfff, rtl8380_rtl8214fc_perchip[i * 3 + 1], + rtl8380_rtl8214fc_perchip[i * 3 + 2]); + } + i++; + } + + /* Force copper medium */ + for (i = 0; i < 4; i++) { + write_phy(mac + i, 0xfff, 0x1f, 0x0000); + write_phy(mac + i, 0xfff, 0x1e, 0x0001); + } + + /* Enable PHY */ + for (i = 0; i < 4; i++) { + write_phy(mac + i, 0xfff, 0x1f, 0x0000); + write_phy(mac + i, 0xfff, 0x00, 0x1140); + } + mdelay(100); + + /* Disable Autosensing */ + for (i = 0; i < 4; i++) { + for (l = 0; l < 100; l++) { + read_phy(mac + i, 0x0a42, 0x10, &val); + if ((val & 0x7) >= 3) + break; + } + if (l >= 100) { + phydev_err(phydev, "Could not disable autosensing\n"); + return -1; + } + } + + /* Request patch */ + for (i = 0; i < 4; i++) { + write_phy(mac + i, 0xfff, 0x1f, 0x0b82); + write_phy(mac + i, 0xfff, 0x10, 0x0010); + } + mdelay(300); + + /* Verify patch readiness */ + for (i = 0; i < 4; i++) { + for (l = 0; l < 100; l++) { + read_phy(mac + i, 0xb80, 0x10, &val); + if (val & 0x40) + break; + } + if (l >= 100) { + phydev_err(phydev, "Could not patch PHY\n"); + return -1; + } + } + + /* Use Broadcast ID method for patching */ + write_phy(mac, 0xfff, 0x1f, 0x0000); + write_phy(mac, 0xfff, 0x1d, 0x0008); + write_phy(mac, 0xfff, 0x1f, 0x0266); + write_phy(mac, 0xfff, 0x16, 0xff00 + mac); + write_phy(mac, 0xfff, 0x1f, 0x0000); + write_phy(mac, 0xfff, 0x1d, 0x0000); + mdelay(1); + + i = 0; + while (rtl8380_rtl8214fc_perport[i * 2]) { + write_phy(mac, 0xfff, rtl8380_rtl8214fc_perport[i * 2], + rtl8380_rtl8214fc_perport[i * 2 + 1]); + i++; + } + + /*Disable broadcast ID*/ + write_phy(mac, 0xfff, 0x1f, 0x0000); + write_phy(mac, 0xfff, 0x1d, 0x0008); + write_phy(mac, 0xfff, 0x1f, 0x0266); + write_phy(mac, 0xfff, 0x16, 0x00 + mac); + write_phy(mac, 0xfff, 0x1f, 0x0000); + write_phy(mac, 0xfff, 0x1d, 0x0000); + mdelay(1); + + /* Auto medium selection */ + for (i = 0; i < 4; i++) { + write_phy(mac + i, 0xfff, 0x1f, 0x0000); + write_phy(mac + i, 0xfff, 0x1e, 0x0000); + } + + return 0; +} + +static int rtl8214fc_match_phy_device(struct phy_device *phydev) +{ + int addr = phydev->mdio.addr; + + return phydev->phy_id == PHY_ID_RTL8214FC && addr >= 24; +} + +static int rtl8380_configure_serdes(struct phy_device *phydev) +{ + u32 v; + u32 sds_conf_value; + int i; + struct fw_header *h; + u32 *rtl8380_sds_take_reset; + u32 *rtl8380_sds_common; + u32 *rtl8380_sds01_qsgmii_6275b; + u32 *rtl8380_sds23_qsgmii_6275b; + u32 *rtl8380_sds4_fiber_6275b; + u32 *rtl8380_sds5_fiber_6275b; + u32 *rtl8380_sds_reset; + u32 *rtl8380_sds_release_reset; + + phydev_info(phydev, "Detected internal RTL8380 SERDES\n"); + + h = rtl838x_request_fw(phydev, &rtl838x_8218b_fw, FIRMWARE_838X_8380_1); + if (!h) + return -1; + + if (h->magic != 0x83808380) { + phydev_err(phydev, "Wrong firmware file: magic number mismatch.\n"); + return -1; + } + + rtl8380_sds_take_reset = (void *)h + sizeof(struct fw_header) + + h->parts[0].start; + + rtl8380_sds_common = (void *)h + sizeof(struct fw_header) + + h->parts[1].start; + + rtl8380_sds01_qsgmii_6275b = (void *)h + sizeof(struct fw_header) + + h->parts[2].start; + + rtl8380_sds23_qsgmii_6275b = (void *)h + sizeof(struct fw_header) + + h->parts[3].start; + + rtl8380_sds4_fiber_6275b = (void *)h + sizeof(struct fw_header) + + h->parts[4].start; + + rtl8380_sds5_fiber_6275b = (void *)h + sizeof(struct fw_header) + + h->parts[5].start; + + rtl8380_sds_reset = (void *)h + sizeof(struct fw_header) + + h->parts[6].start; + + rtl8380_sds_release_reset = (void *)h + sizeof(struct fw_header) + + h->parts[7].start; + + /* Back up serdes power off value */ + sds_conf_value = sw_r32(RTL838X_SDS_CFG_REG); + pr_info("SDS power down value: %x\n", sds_conf_value); + + /* take serdes into reset */ + i = 0; + while (rtl8380_sds_take_reset[2 * i]) { + sw_w32(rtl8380_sds_take_reset[2 * i + 1], rtl8380_sds_take_reset[2 * i]); + i++; + udelay(1000); + } + + /* apply common serdes patch */ + i = 0; + while (rtl8380_sds_common[2 * i]) { + sw_w32(rtl8380_sds_common[2 * i + 1], rtl8380_sds_common[2 * i]); + i++; + udelay(1000); + } + + /* internal R/W enable */ + sw_w32(3, RTL838X_INT_RW_CTRL); + + /* SerDes ports 4 and 5 are FIBRE ports */ + sw_w32_mask(0x7 | 0x38, 1 | (1 << 3), RTL838X_INT_MODE_CTRL); + + /* SerDes module settings, SerDes 0-3 are QSGMII */ + v = 0x6 << 25 | 0x6 << 20 | 0x6 << 15 | 0x6 << 10; + /* SerDes 4 and 5 are 1000BX FIBRE */ + v |= 0x4 << 5 | 0x4; + sw_w32(v, RTL838X_SDS_MODE_SEL); + + pr_info("PLL control register: %x\n", sw_r32(RTL838X_PLL_CML_CTRL)); + sw_w32_mask(0xfffffff0, 0xaaaaaaaf & 0xf, RTL838X_PLL_CML_CTRL); + i = 0; + while (rtl8380_sds01_qsgmii_6275b[2 * i]) { + sw_w32(rtl8380_sds01_qsgmii_6275b[2 * i + 1], + rtl8380_sds01_qsgmii_6275b[2 * i]); + i++; + } + + i = 0; + while (rtl8380_sds23_qsgmii_6275b[2 * i]) { + sw_w32(rtl8380_sds23_qsgmii_6275b[2 * i + 1], rtl8380_sds23_qsgmii_6275b[2 * i]); + i++; + } + + i = 0; + while (rtl8380_sds4_fiber_6275b[2 * i]) { + sw_w32(rtl8380_sds4_fiber_6275b[2 * i + 1], rtl8380_sds4_fiber_6275b[2 * i]); + i++; + } + + i = 0; + while (rtl8380_sds5_fiber_6275b[2 * i]) { + sw_w32(rtl8380_sds5_fiber_6275b[2 * i + 1], rtl8380_sds5_fiber_6275b[2 * i]); + i++; + } + + i = 0; + while (rtl8380_sds_reset[2 * i]) { + sw_w32(rtl8380_sds_reset[2 * i + 1], rtl8380_sds_reset[2 * i]); + i++; + } + + i = 0; + while (rtl8380_sds_release_reset[2 * i]) { + sw_w32(rtl8380_sds_release_reset[2 * i + 1], rtl8380_sds_release_reset[2 * i]); + i++; + } + + pr_info("SDS power down value now: %x\n", sw_r32(RTL838X_SDS_CFG_REG)); + sw_w32(sds_conf_value, RTL838X_SDS_CFG_REG); + + pr_info("Configuration of SERDES done\n"); + return 0; +} + +static int rtl8214fc_phy_probe(struct phy_device *phydev) +{ + struct device *dev = &phydev->mdio.dev; + struct rtl838x_phy_priv *priv; + int addr = phydev->mdio.addr; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->name = "RTL8214FC"; + + /* All base addresses of the PHYs start at multiples of 8 */ + if (!(addr % 8)) { + /* Configuration must be done whil patching still possible */ + return rtl8380_configure_rtl8214fc(phydev); + } + return 0; +} + +static int rtl8214c_phy_probe(struct phy_device *phydev) +{ + struct device *dev = &phydev->mdio.dev; + struct rtl838x_phy_priv *priv; + int addr = phydev->mdio.addr; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->name = "RTL8214C"; + + /* All base addresses of the PHYs start at multiples of 8 */ + if (!(addr % 8)) { + /* Configuration must be done whil patching still possible */ + return rtl8380_configure_rtl8214c(phydev); + } + return 0; +} + +static int rtl8218b_ext_phy_probe(struct phy_device *phydev) +{ + struct device *dev = &phydev->mdio.dev; + struct rtl838x_phy_priv *priv; + int addr = phydev->mdio.addr; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->name = "RTL8218B (external)"; + + /* All base addresses of the PHYs start at multiples of 8 */ + if (!(addr % 8)) { + /* Configuration must be done while patching still possible */ + return rtl8380_configure_ext_rtl8218b(phydev); + } + return 0; +} + +static int rtl8218b_int_phy_probe(struct phy_device *phydev) +{ + struct device *dev = &phydev->mdio.dev; + struct rtl838x_phy_priv *priv; + int addr = phydev->mdio.addr; + + if (soc_info.family != RTL8380_FAMILY_ID) + return -ENODEV; + if (addr >= 24) + return -ENODEV; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->name = "RTL8218B (internal)"; + + /* All base addresses of the PHYs start at multiples of 8 */ + if (!(addr % 8)) { + /* Configuration must be done while patching still possible */ + return rtl8380_configure_int_rtl8218b(phydev); + } + return 0; +} + +static int rtl838x_serdes_probe(struct phy_device *phydev) +{ + struct device *dev = &phydev->mdio.dev; + struct rtl838x_phy_priv *priv; + int addr = phydev->mdio.addr; + + if (soc_info.family != RTL8380_FAMILY_ID) + return -ENODEV; + if (addr < 24) + return -ENODEV; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->name = "RTL8380 Serdes"; + + /* On the RTL8380M, PHYs 24-27 connect to the internal SerDes */ + if (soc_info.id == 0x8380) { + if (addr == 24) + return rtl8380_configure_serdes(phydev); + return 0; + } + return -ENODEV; +} + +static int rtl8390_serdes_probe(struct phy_device *phydev) +{ + struct device *dev = &phydev->mdio.dev; + struct rtl838x_phy_priv *priv; + int addr = phydev->mdio.addr; + + if (soc_info.family != RTL8390_FAMILY_ID) + return -ENODEV; + + if (addr < 24) + return -ENODEV; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->name = "RTL8390 Serdes"; + return rtl8390_configure_generic(phydev); +} + +static struct phy_driver rtl838x_phy_driver[] = { + { + PHY_ID_MATCH_MODEL(PHY_ID_RTL8214FC), + .name = "REATLTEK RTL8214C", + .features = PHY_GBIT_FEATURES, + .match_phy_device = rtl8214c_match_phy_device, + .probe = rtl8214c_phy_probe, + .suspend = genphy_suspend, + .resume = genphy_resume, + .set_loopback = genphy_loopback, + }, + { + PHY_ID_MATCH_MODEL(PHY_ID_RTL8214FC), + .name = "REATLTEK RTL8214FC", + .features = PHY_GBIT_FIBRE_FEATURES, + .match_phy_device = rtl8214fc_match_phy_device, + .probe = rtl8214fc_phy_probe, + .suspend = genphy_suspend, + .resume = genphy_resume, + .set_loopback = genphy_loopback, + .read_mmd = rtl8380_rtl8218b_read_mmd, + .write_mmd = rtl8380_rtl8218b_write_mmd, + .set_port = rtl8380_rtl8214fc_set_port, + .get_port = rtl8380_rtl8214fc_get_port, + .set_eee = rtl8380_rtl8214fc_set_eee, + .get_eee = rtl8380_rtl8214fc_get_eee, + }, + { + PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_E), + .name = "REATLTEK RTL8218B (external)", + .features = PHY_GBIT_FEATURES, + .match_phy_device = rtl8218b_ext_match_phy_device, + .probe = rtl8218b_ext_phy_probe, + .suspend = genphy_suspend, + .resume = genphy_resume, + .set_loopback = genphy_loopback, + .read_mmd = rtl8380_rtl8218b_read_mmd, + .write_mmd = rtl8380_rtl8218b_write_mmd, + .set_eee = rtl8380_rtl8218b_set_eee, + .get_eee = rtl8380_rtl8218b_get_eee_u_boot, + }, + { + PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_I), + .name = "REATLTEK RTL8218B (internal)", + .features = PHY_GBIT_FEATURES, + .probe = rtl8218b_int_phy_probe, + .suspend = genphy_suspend, + .resume = genphy_resume, + .set_loopback = genphy_loopback, + .read_mmd = rtl8380_rtl8218b_read_mmd, + .write_mmd = rtl8380_rtl8218b_write_mmd, + .set_eee = rtl8380_rtl8218b_set_eee, + .get_eee = rtl8380_rtl8218b_get_eee_u_boot, + }, + { + PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_I), + .name = "REATLTEK RTL8380 SERDES", + .features = PHY_GBIT_FIBRE_FEATURES, + .probe = rtl838x_serdes_probe, + .suspend = genphy_suspend, + .resume = genphy_resume, + .set_loopback = genphy_loopback, + .read_mmd = rtl8380_rtl8218b_read_mmd, + .write_mmd = rtl8380_rtl8218b_write_mmd, + }, + { + PHY_ID_MATCH_MODEL(PHY_ID_RTL8390_GENERIC), + .name = "REATLTEK RTL8390 Generic", + .features = PHY_GBIT_FIBRE_FEATURES, + .probe = rtl8390_serdes_probe, + .suspend = genphy_suspend, + .resume = genphy_resume, + .set_loopback = genphy_loopback, + } +}; + +module_phy_driver(rtl838x_phy_driver); + +static struct mdio_device_id __maybe_unused rtl838x_tbl[] = { + { PHY_ID_MATCH_MODEL(PHY_ID_RTL8214FC) }, + { } +}; + +MODULE_DEVICE_TABLE(mdio, rtl838x_tbl); + +MODULE_AUTHOR("B. Koblitz"); +MODULE_DESCRIPTION("RTL838x PHY driver"); +MODULE_LICENSE("GPL"); diff --git a/target/linux/rtl838x/files-5.4/drivers/net/dsa/rtl838x_sw.c b/target/linux/rtl838x/files-5.4/drivers/net/dsa/rtl838x_sw.c new file mode 100644 index 0000000000..7f6c2d6a29 --- /dev/null +++ b/target/linux/rtl838x/files-5.4/drivers/net/dsa/rtl838x_sw.c @@ -0,0 +1,2150 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include "rtl838x.h" + +#define RTL8380_VERSION_A 'A' +#define RTL8390_VERSION_A 'A' +#define RTL8380_VERSION_B 'B' + +DEFINE_MUTEX(smi_lock); + +#define MIB_DESC(_size, _offset, _name) {.size = _size, .offset = _offset, .name = _name} +struct rtl838x_mib_desc { + unsigned int size; + unsigned int offset; + const char *name; +}; + +inline void rtl838x_mask_port_reg(u64 clear, u64 set, int reg) +{ + sw_w32_mask((u32)clear, (u32)set, reg); +} + +inline void rtl839x_mask_port_reg(u64 clear, u64 set, int reg) +{ + sw_w32_mask((u32) (clear >> 32), (u32) (set >> 32), reg); + sw_w32_mask((u32) (clear & 0xffffffff), (u32) (set & 0xffffffff), reg + 4); +} + +inline void rtl838x_set_port_reg(u64 set, int reg) +{ + sw_w32(set, reg); +} + +inline void rtl839x_set_port_reg(u64 set, int reg) +{ + sw_w32(set >> 32, reg); + sw_w32(set & 0xffffffff, reg + 4); +} + +inline u64 rtl838x_get_port_reg(int reg) +{ + return ((u64) sw_r32(reg)); +} + +inline u64 rtl839x_get_port_reg(int reg) +{ + u64 v = sw_r32(reg); + + v <<= 32; + v |= sw_r32(reg + 4); + return v; +} + +inline int rtl838x_stat_port_std_mib(int p) +{ + return RTL838X_STAT_PORT_STD_MIB + (p << 8); +} + +inline int rtl839x_stat_port_std_mib(int p) +{ + return RTL839X_STAT_PORT_STD_MIB + (p << 8); +} + +inline void rtl838x_mask_port_iso_ctrl(u64 clear, u64 set, int port) +{ + sw_w32_mask(clear, set, RTL838X_PORT_ISO_CTRL(port)); +} + +inline void rtl839x_mask_port_iso_ctrl(u64 clear, u64 set, int port) +{ + sw_w32_mask(clear >> 32, set >> 32, RTL839X_PORT_ISO_CTRL(port)); + sw_w32_mask(clear & 0xffffffff, set & 0xffffffff, + RTL839X_PORT_ISO_CTRL(port) + 4); +} + +inline void rtl838x_set_port_iso_ctrl(u64 set, int port) +{ + sw_w32(set, RTL838X_PORT_ISO_CTRL(port)); +} + +inline void rtl839x_set_port_iso_ctrl(u64 set, int port) +{ + sw_w32(set >> 32, RTL839X_PORT_ISO_CTRL(port)); + sw_w32(set & 0xffffffff, RTL839X_PORT_ISO_CTRL(port) + 4); +} + +inline void rtl838x_exec_tbl0_cmd(u32 cmd) +{ + sw_w32(cmd, RTL838X_TBL_ACCESS_CTRL_0); + do { } while (sw_r32(RTL838X_TBL_ACCESS_CTRL_0) & (1 << 15)); +} + +inline void rtl839x_exec_tbl0_cmd(u32 cmd) +{ + sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_0); + do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_0) & (1 << 16)); +} + +inline void rtl838x_exec_tbl1_cmd(u32 cmd) +{ + sw_w32(cmd, RTL838X_TBL_ACCESS_CTRL_1); + do { } while (sw_r32(RTL838X_TBL_ACCESS_CTRL_1) & (1 << 15)); +} + +inline void rtl839x_exec_tbl1_cmd(u32 cmd) +{ + sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_1); + do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_1) & (1 << 16)); +} + +inline int rtl838x_tbl_access_data_0(int i) +{ + return RTL838X_TBL_ACCESS_DATA_0(i); +} + +inline int rtl839x_tbl_access_data_0(int i) +{ + return RTL839X_TBL_ACCESS_DATA_0(i); +} + +static void rtl839x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info) +{ + u32 cmd; + u64 v; + + cmd = 1 << 16 /* Execute cmd */ + | 0 << 15 /* Read */ + | 0 << 12 /* Table type 0b000 */ + | (vlan & 0xfff); + rtl839x_exec_tbl0_cmd(cmd); + + v = sw_r32(RTL838X_TBL_ACCESS_DATA_0(0)); + v <<= 32; + v |= sw_r32(RTL838X_TBL_ACCESS_DATA_0(1)); + info->tagged_ports = v >> 11; + info->vlan_conf = (v & 0x7ff) << 2; + info->vlan_conf |= sw_r32(RTL838X_TBL_ACCESS_DATA_0(1)) >> 30; + + cmd = 1 << 16 /* Execute cmd */ + | 0 << 15 /* Read */ + | 0 << 12 /* Table type 0b000 */ + | (vlan & 0xfff); + rtl839x_exec_tbl1_cmd(cmd); + v = sw_r32(RTL838X_TBL_ACCESS_DATA_1(0)); + v <<= 32; + v |= sw_r32(RTL838X_TBL_ACCESS_DATA_1(1)); + info->untagged_ports = v >> 11; +} + +static void rtl838x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info) +{ + u32 cmd; + + cmd = 1 << 15 /* Execute cmd */ + | 1 << 14 /* Read */ + | 0 << 12 /* Table type 0b00 */ + | (vlan & 0xfff); + rtl838x_exec_tbl0_cmd(cmd); + info->tagged_ports = sw_r32(RTL838X_TBL_ACCESS_DATA_0(0)); + info->vlan_conf = sw_r32(RTL838X_TBL_ACCESS_DATA_0(1)); + + cmd = 1 << 15 /* Execute cmd */ + | 1 << 14 /* Read */ + | 0 << 12 /* Table type 0b00 */ + | (vlan & 0xfff); + rtl838x_exec_tbl1_cmd(cmd); + info->untagged_ports = sw_r32(RTL838X_TBL_ACCESS_DATA_1(0)); +} + +static void rtl839x_vlan_set_tagged(u32 vlan, u64 portmask, u32 conf) +{ + u32 cmd = 1 << 16 /* Execute cmd */ + | 1 << 15 /* Write */ + | 0 << 12 /* Table type 0b00 */ + | (vlan & 0xfff); + u64 v = portmask << 11; + + v |= (conf >> 2) & 0x7ff; + sw_w64(v, RTL838X_TBL_ACCESS_DATA_0(0)); + sw_w32(conf << 30, RTL838X_TBL_ACCESS_DATA_0(2)); + rtl839x_exec_tbl0_cmd(cmd); +} + +static void rtl838x_vlan_set_tagged(u32 vlan, u64 portmask, u32 conf) +{ + u32 cmd = 1 << 15 /* Execute cmd */ + | 0 << 14 /* Write */ + | 0 << 12 /* Table type 0b00 */ + | (vlan & 0xfff); + + sw_w32(portmask, RTL838X_TBL_ACCESS_DATA_0(0)); + sw_w32(conf, RTL838X_TBL_ACCESS_DATA_0(1)); + rtl838x_exec_tbl0_cmd(cmd); +} + +static void rtl839x_vlan_set_untagged(u32 vlan, u64 portmask) +{ + u32 cmd = 1 << 16 /* Execute cmd */ + | 1 << 15 /* Write */ + | 0 << 12 /* Table type 0b00 */ + | (vlan & 0xfff); + sw_w64(portmask << 11, RTL838X_TBL_ACCESS_DATA_1(0)); + rtl839x_exec_tbl1_cmd(cmd); +} + +static void rtl838x_vlan_set_untagged(u32 vlan, u64 portmask) +{ + u32 cmd = 1 << 15 /* Execute cmd */ + | 0 << 14 /* Write */ + | 0 << 12 /* Table type 0b00 */ + | (vlan & 0xfff); + sw_w32(portmask & 0x1fffffff, RTL838X_TBL_ACCESS_DATA_1(0)); + rtl838x_exec_tbl1_cmd(cmd); +} + +static inline int rtl838x_mac_force_mode_ctrl(int p) +{ + return RTL838X_MAC_FORCE_MODE_CTRL + (p << 2); +} + +static inline int rtl839x_mac_force_mode_ctrl(int p) +{ + return RTL839X_MAC_FORCE_MODE_CTRL + (p << 2); +} + +static const struct rtl838x_reg rtl838x_reg = { + .mask_port_reg = rtl838x_mask_port_reg, + .set_port_reg = rtl838x_set_port_reg, + .get_port_reg = rtl838x_get_port_reg, + .stat_port_rst = RTL838X_STAT_PORT_RST, + .stat_rst = RTL838X_STAT_RST, + .stat_port_std_mib = rtl838x_stat_port_std_mib, + .mask_port_iso_ctrl = rtl838x_mask_port_iso_ctrl, + .set_port_iso_ctrl = rtl838x_set_port_iso_ctrl, + .l2_ctrl_0 = RTL838X_L2_CTRL_0, + .l2_ctrl_1 = RTL838X_L2_CTRL_1, + .l2_port_aging_out = RTL838X_L2_PORT_AGING_OUT, + .smi_poll_ctrl = RTL838X_SMI_POLL_CTRL, + .l2_tbl_flush_ctrl = RTL838X_L2_TBL_FLUSH_CTRL, + .exec_tbl0_cmd = rtl838x_exec_tbl0_cmd, + .exec_tbl1_cmd = rtl838x_exec_tbl1_cmd, + .tbl_access_data_0 = rtl838x_tbl_access_data_0, + .isr_glb_src = RTL838X_ISR_GLB_SRC, + .isr_port_link_sts_chg = RTL838X_ISR_PORT_LINK_STS_CHG, + .imr_port_link_sts_chg = RTL838X_IMR_PORT_LINK_STS_CHG, + .imr_glb = RTL838X_IMR_GLB, + .vlan_tables_read = rtl838x_vlan_tables_read, + .vlan_set_tagged = rtl838x_vlan_set_tagged, + .vlan_set_untagged = rtl838x_vlan_set_untagged, + .mac_force_mode_ctrl = rtl838x_mac_force_mode_ctrl, + .rst_glb_ctrl = RTL838X_RST_GLB_CTRL_0, +}; + +static const struct rtl838x_reg rtl839x_reg = { + .mask_port_reg = rtl839x_mask_port_reg, + .set_port_reg = rtl839x_set_port_reg, + .get_port_reg = rtl839x_get_port_reg, + .stat_port_rst = RTL839X_STAT_PORT_RST, + .stat_rst = RTL839X_STAT_RST, + .stat_port_std_mib = rtl839x_stat_port_std_mib, + .mask_port_iso_ctrl = rtl839x_mask_port_iso_ctrl, + .set_port_iso_ctrl = rtl839x_set_port_iso_ctrl, + .l2_ctrl_0 = RTL839X_L2_CTRL_0, + .l2_ctrl_1 = RTL839X_L2_CTRL_1, + .l2_port_aging_out = RTL839X_L2_PORT_AGING_OUT, + .smi_poll_ctrl = RTL839X_SMI_PORT_POLLING_CTRL, + .l2_tbl_flush_ctrl = RTL839X_L2_TBL_FLUSH_CTRL, + .exec_tbl0_cmd = rtl839x_exec_tbl0_cmd, + .exec_tbl1_cmd = rtl839x_exec_tbl1_cmd, + .tbl_access_data_0 = rtl839x_tbl_access_data_0, + .isr_glb_src = RTL839X_ISR_GLB_SRC, + .isr_port_link_sts_chg = RTL839X_ISR_PORT_LINK_STS_CHG, + .imr_port_link_sts_chg = RTL839X_IMR_PORT_LINK_STS_CHG, + .imr_glb = RTL839X_IMR_GLB, + .vlan_tables_read = rtl839x_vlan_tables_read, + .vlan_set_tagged = rtl839x_vlan_set_tagged, + .vlan_set_untagged = rtl839x_vlan_set_untagged, + .mac_force_mode_ctrl = rtl839x_mac_force_mode_ctrl, + .rst_glb_ctrl = RTL839X_RST_GLB_CTRL, +}; + +static const struct rtl838x_mib_desc rtl838x_mib[] = { + MIB_DESC(2, 0xf8, "ifInOctets"), + MIB_DESC(2, 0xf0, "ifOutOctets"), + MIB_DESC(1, 0xec, "dot1dTpPortInDiscards"), + MIB_DESC(1, 0xe8, "ifInUcastPkts"), + MIB_DESC(1, 0xe4, "ifInMulticastPkts"), + MIB_DESC(1, 0xe0, "ifInBroadcastPkts"), + MIB_DESC(1, 0xdc, "ifOutUcastPkts"), + MIB_DESC(1, 0xd8, "ifOutMulticastPkts"), + MIB_DESC(1, 0xd4, "ifOutBroadcastPkts"), + MIB_DESC(1, 0xd0, "ifOutDiscards"), + MIB_DESC(1, 0xcc, ".3SingleCollisionFrames"), + MIB_DESC(1, 0xc8, ".3MultipleCollisionFrames"), + MIB_DESC(1, 0xc4, ".3DeferredTransmissions"), + MIB_DESC(1, 0xc0, ".3LateCollisions"), + MIB_DESC(1, 0xbc, ".3ExcessiveCollisions"), + MIB_DESC(1, 0xb8, ".3SymbolErrors"), + MIB_DESC(1, 0xb4, ".3ControlInUnknownOpcodes"), + MIB_DESC(1, 0xb0, ".3InPauseFrames"), + MIB_DESC(1, 0xac, ".3OutPauseFrames"), + MIB_DESC(1, 0xa8, "DropEvents"), + MIB_DESC(1, 0xa4, "tx_BroadcastPkts"), + MIB_DESC(1, 0xa0, "tx_MulticastPkts"), + MIB_DESC(1, 0x9c, "CRCAlignErrors"), + MIB_DESC(1, 0x98, "tx_UndersizePkts"), + MIB_DESC(1, 0x94, "rx_UndersizePkts"), + MIB_DESC(1, 0x90, "rx_UndersizedropPkts"), + MIB_DESC(1, 0x8c, "tx_OversizePkts"), + MIB_DESC(1, 0x88, "rx_OversizePkts"), + MIB_DESC(1, 0x84, "Fragments"), + MIB_DESC(1, 0x80, "Jabbers"), + MIB_DESC(1, 0x7c, "Collisions"), + MIB_DESC(1, 0x78, "tx_Pkts64Octets"), + MIB_DESC(1, 0x74, "rx_Pkts64Octets"), + MIB_DESC(1, 0x70, "tx_Pkts65to127Octets"), + MIB_DESC(1, 0x6c, "rx_Pkts65to127Octets"), + MIB_DESC(1, 0x68, "tx_Pkts128to255Octets"), + MIB_DESC(1, 0x64, "rx_Pkts128to255Octets"), + MIB_DESC(1, 0x60, "tx_Pkts256to511Octets"), + MIB_DESC(1, 0x5c, "rx_Pkts256to511Octets"), + MIB_DESC(1, 0x58, "tx_Pkts512to1023Octets"), + MIB_DESC(1, 0x54, "rx_Pkts512to1023Octets"), + MIB_DESC(1, 0x50, "tx_Pkts1024to1518Octets"), + MIB_DESC(1, 0x4c, "rx_StatsPkts1024to1518Octets"), + MIB_DESC(1, 0x48, "tx_Pkts1519toMaxOctets"), + MIB_DESC(1, 0x44, "rx_Pkts1519toMaxOctets"), + MIB_DESC(1, 0x40, "rxMacDiscards") +}; + +static irqreturn_t rtl838x_switch_irq(int irq, void *dev_id) +{ + struct dsa_switch *ds = dev_id; + u32 status = sw_r32(RTL838X_ISR_GLB_SRC); + u32 ports = sw_r32(RTL838X_ISR_PORT_LINK_STS_CHG); + u32 link; + int i; + + /* Clear status */ + sw_w32(ports, RTL838X_ISR_PORT_LINK_STS_CHG); + pr_info("Link change: status: %x, ports %x\n", status, ports); + + for (i = 0; i < 28; i++) { + if (ports & (1 << i)) { + link = sw_r32(RTL838X_MAC_LINK_STS); + if (link & (1 << i)) + dsa_port_phylink_mac_change(ds, i, true); + else + dsa_port_phylink_mac_change(ds, i, false); + } + } + return IRQ_HANDLED; +} + +static irqreturn_t rtl839x_switch_irq(int irq, void *dev_id) +{ + struct dsa_switch *ds = dev_id; + u32 status = sw_r32(RTL839X_ISR_GLB_SRC); + u64 ports = sw_r64(RTL839X_ISR_PORT_LINK_STS_CHG); + u64 link; + int i; + + /* Clear status */ + sw_w64(ports, RTL839X_ISR_PORT_LINK_STS_CHG); + pr_info("Link change: status: %x, ports %llx\n", status, ports); + + for (i = 0; i < 52; i++) { + if (ports & (1 << i)) { + link = sw_r64(RTL839X_MAC_LINK_STS); + if (link & (1 << i)) + dsa_port_phylink_mac_change(ds, i, true); + else + dsa_port_phylink_mac_change(ds, i, false); + } + } + return IRQ_HANDLED; +} + +int rtl8380_sds_power(int mac, int val) +{ + u32 mode = (val == 1) ? 0x4 : 0x9; + u32 offset = (mac == 24) ? 5 : 0; + + if ((mac != 24) && (mac != 26)) { + pr_err("%s: not a fibre port: %d\n", __func__, mac); + return -1; + } + + sw_w32_mask(0x1f << offset, mode << offset, RTL838X_SDS_MODE_SEL); + + rtl8380_sds_rst(mac); + + return 0; +} + +static int rtl838x_smi_wait_op(int timeout) +{ + do { + timeout--; + udelay(10); + } while ((sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1) & 0x1) && (timeout >= 0)); + if (timeout <= 0) + return -1; + return 0; +} + +/* + * Write to a register in a page of the PHY + */ +int rtl838x_write_phy(u32 port, u32 page, u32 reg, u32 val) +{ + u32 v; + u32 park_page; + + val &= 0xffff; + if (port > 31 || page > 4095 || reg > 31) + return -ENOTSUPP; + + mutex_lock(&smi_lock); + if (rtl838x_smi_wait_op(10000)) + goto timeout; + + sw_w32(1 << port, RTL838X_SMI_ACCESS_PHY_CTRL_0); + mdelay(10); + + sw_w32_mask(0xffff0000, val << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2); + + park_page = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1) & ((0x1f << 15) | 0x2); + v = reg << 20 | page << 3 | 0x4; + sw_w32(v | park_page, RTL838X_SMI_ACCESS_PHY_CTRL_1); + sw_w32_mask(0, 1, RTL838X_SMI_ACCESS_PHY_CTRL_1); + + if (rtl838x_smi_wait_op(10000)) + goto timeout; + + mutex_unlock(&smi_lock); + return 0; + +timeout: + mutex_unlock(&smi_lock); + return -ETIMEDOUT; +} + +int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val) +{ + u32 v; + int err = 0; + + val &= 0xffff; + if (port > 63 || page > 4095 || reg > 31) + return -ENOTSUPP; + + mutex_lock(&smi_lock); + /* Clear both port registers */ + sw_w32(0, RTL839X_PHYREG_PORT_CTRL(0)); + sw_w32(0, RTL839X_PHYREG_PORT_CTRL(0) + 4); + sw_w32_mask(0, 1 << port, RTL839X_PHYREG_PORT_CTRL(port)); + + sw_w32_mask(0xffff0000, val << 16, RTL839X_PHYREG_DATA_CTRL); + + v = reg << 5 | page << 10 | ((page == 0x1fff) ? 0x1f : 0) << 23; + sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL); + + sw_w32(0x1ff, RTL839X_PHYREG_CTRL); + + v |= 1 << 3 | 1; /* Write operation and execute */ + sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL); + + do { + } while (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x1); + + if (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x2) + err = -EIO; + + mutex_unlock(&smi_lock); + return err; +} + +/* + * Reads a register in a page from the PHY + */ +int rtl838x_read_phy(u32 port, u32 page, u32 reg, u32 *val) +{ + u32 v; + u32 park_page; + + if (port > 31 || page > 4095 || reg > 31) + return -ENOTSUPP; + + mutex_lock(&smi_lock); + + if (rtl838x_smi_wait_op(10000)) + goto timeout; + + sw_w32_mask(0xffff0000, port << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2); + + park_page = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1) & ((0x1f << 15) | 0x2); + v = reg << 20 | page << 3; + sw_w32(v | park_page, RTL838X_SMI_ACCESS_PHY_CTRL_1); + sw_w32_mask(0, 1, RTL838X_SMI_ACCESS_PHY_CTRL_1); + + if (rtl838x_smi_wait_op(10000)) + goto timeout; + + *val = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_2) & 0xffff; + + mutex_unlock(&smi_lock); + return 0; + +timeout: + mutex_unlock(&smi_lock); + return -ETIMEDOUT; +} + +int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val) +{ + u32 v; + + if (port > 63 || page > 4095 || reg > 31) + return -ENOTSUPP; + + mutex_lock(&smi_lock); + + sw_w32_mask(0xffff0000, port << 16, RTL839X_PHYREG_DATA_CTRL); + v = reg << 5 | page << 10 | ((page == 0x1fff) ? 0x1f : 0) << 23; + sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL); + + sw_w32(0x1ff, RTL839X_PHYREG_CTRL); + + v |= 1; + sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL); + + do { + } while (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x1); + + *val = sw_r32(RTL839X_PHYREG_DATA_CTRL) & 0xffff; + + mutex_unlock(&smi_lock); + return 0; +} + +static int read_phy(u32 port, u32 page, u32 reg, u32 *val) +{ + if (soc_info.family == RTL8390_FAMILY_ID) + return rtl839x_read_phy(port, page, reg, val); + else + return rtl838x_read_phy(port, page, reg, val); +} + +static int write_phy(u32 port, u32 page, u32 reg, u32 val) +{ + if (soc_info.family == RTL8390_FAMILY_ID) + return rtl839x_write_phy(port, page, reg, val); + else + return rtl838x_write_phy(port, page, reg, val); +} + +/* + * Write to an mmd register of the PHY + */ +int rtl838x_write_mmd_phy(u32 port, u32 addr, u32 reg, u32 val) +{ + u32 v; + + pr_debug("MMD write: port %d, dev %d, reg %d, val %x\n", port, addr, reg, val); + val &= 0xffff; + mutex_lock(&smi_lock); + + if (rtl838x_smi_wait_op(10000)) + goto timeout; + + sw_w32(1 << port, RTL838X_SMI_ACCESS_PHY_CTRL_0); + mdelay(10); + + sw_w32_mask(0xffff0000, val << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2); + + sw_w32_mask(0x1f << 16, addr << 16, RTL838X_SMI_ACCESS_PHY_CTRL_3); + sw_w32_mask(0xffff, reg, RTL838X_SMI_ACCESS_PHY_CTRL_3); + /* mmd-access | write | cmd-start */ + v = 1 << 1 | 1 << 2 | 1; + sw_w32(v, RTL838X_SMI_ACCESS_PHY_CTRL_1); + + if (rtl838x_smi_wait_op(10000)) + goto timeout; + + mutex_unlock(&smi_lock); + return 0; + +timeout: + mutex_unlock(&smi_lock); + return -ETIMEDOUT; +} + +/* + * Read to an mmd register of the PHY + */ +int rtl838x_read_mmd_phy(u32 port, u32 addr, u32 reg, u32 *val) +{ + u32 v; + + mutex_lock(&smi_lock); + + if (rtl838x_smi_wait_op(10000)) + goto timeout; + + sw_w32(1 << port, RTL838X_SMI_ACCESS_PHY_CTRL_0); + mdelay(10); + + sw_w32_mask(0xffff0000, port << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2); + + v = addr << 16 | reg; + sw_w32(v, RTL838X_SMI_ACCESS_PHY_CTRL_3); + + /* mmd-access | read | cmd-start */ + v = 1 << 1 | 0 << 2 | 1; + sw_w32(v, RTL838X_SMI_ACCESS_PHY_CTRL_1); + + if (rtl838x_smi_wait_op(10000)) + goto timeout; + + *val = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_2) & 0xffff; + + mutex_unlock(&smi_lock); + return 0; + +timeout: + mutex_unlock(&smi_lock); + return -ETIMEDOUT; +} + +static void rtl8380_get_version(struct rtl838x_switch_priv *priv) +{ + u32 rw_save, info_save; + u32 info; + + if (priv->id) + pr_debug("SoC ID: %4x: %s\n", priv->id, soc_info.name); + else + pr_err("Unknown chip id (%04x)\n", priv->id); + + rw_save = sw_r32(RTL838X_INT_RW_CTRL); + sw_w32(rw_save | 0x3, RTL838X_INT_RW_CTRL); + + info_save = sw_r32(RTL838X_CHIP_INFO); + sw_w32(info_save | 0xA0000000, RTL838X_CHIP_INFO); + + info = sw_r32(RTL838X_CHIP_INFO); + sw_w32(info_save, RTL838X_CHIP_INFO); + sw_w32(rw_save, RTL838X_INT_RW_CTRL); + + if ((info & 0xFFFF) == 0x6275) { + if (((info >> 16) & 0x1F) == 0x1) + priv->version = RTL8380_VERSION_A; + else if (((info >> 16) & 0x1F) == 0x2) + priv->version = RTL8380_VERSION_B; + else + priv->version = RTL8380_VERSION_B; + } else { + priv->version = '-'; + } +} + +static void rtl8390_get_version(struct rtl838x_switch_priv *priv) +{ + u32 info; + + sw_w32_mask(0xf << 28, 0xa << 28, RTL839X_CHIP_INFO); + info = sw_r32(RTL839X_CHIP_INFO); + pr_info("Chip-Info: %x\n", info); + priv->version = RTL8390_VERSION_A; +} + +int dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg) +{ + u32 val; + u32 offset = 0; + struct rtl838x_switch_priv *priv = ds->priv; + + if (phy_addr >= 24 && phy_addr <= 27 + && priv->ports[24].phy == PHY_RTL838X_SDS) { + if (phy_addr == 26) + offset = 0x100; + val = sw_r32(MAPLE_SDS4_FIB_REG0r + offset + (phy_reg << 2)) & 0xffff; + return val; + } + + read_phy(phy_addr, 0, phy_reg, &val); + return val; +} + +int dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_reg, u16 val) +{ + u32 offset = 0; + struct rtl838x_switch_priv *priv = ds->priv; + + if (phy_addr >= 24 && phy_addr <= 27 + && priv->ports[24].phy == PHY_RTL838X_SDS) { + if (phy_addr == 26) + offset = 0x100; + sw_w32(val, MAPLE_SDS4_FIB_REG0r + offset + (phy_reg << 2)); + return 0; + } + return write_phy(phy_addr, 0, phy_reg, val); +} + +static int rtl838x_mdio_read(struct mii_bus *bus, int addr, int regnum) +{ + int ret; + struct rtl838x_switch_priv *priv = bus->priv; + + ret = dsa_phy_read(priv->ds, addr, regnum); + return ret; +} + +static int rtl838x_mdio_write(struct mii_bus *bus, int addr, int regnum, + u16 val) +{ + struct rtl838x_switch_priv *priv = bus->priv; + + return dsa_phy_write(priv->ds, addr, regnum, val); +} + +static void rtl838x_enable_phy_polling(struct rtl838x_switch_priv *priv) +{ + int i; + u64 v = 0; + + msleep(1000); + /* Enable all ports with a PHY, including the SFP-ports */ + for (i = 0; i < priv->cpu_port; i++) { + if (priv->ports[i].phy) + v |= 1 << i; + } + + pr_info("%s: %16llx\n", __func__, v); + priv->r->set_port_reg(v, priv->r->smi_poll_ctrl); + + /* PHY update complete */ + if (priv->family_id == RTL8390_FAMILY_ID) + sw_w32_mask(1 << 7, 0, RTL839X_SMI_GLB_CTRL); + else + sw_w32_mask(0, 0x8000, RTL838X_SMI_GLB_CTRL); +} + +void rtl839x_print_matrix(void) +{ + volatile u64 *ptr = RTL838X_SW_BASE + RTL839X_PORT_ISO_CTRL(0); + int i; + + for (i = 0; i < 52; i += 4) + pr_info("> %16llx %16llx %16llx %16llx\n", + ptr[i + 0], ptr[i + 1], ptr[i + 2], ptr[i + 3]); + pr_info("CPU_PORT> %16llx\n", ptr[52]); +} + +void rtl838x_print_matrix(void) +{ + unsigned volatile int *ptr = RTL838X_SW_BASE + RTL838X_PORT_ISO_CTRL(0); + int i; + + if (soc_info.family == RTL8390_FAMILY_ID) + return rtl839x_print_matrix(); + + for (i = 0; i < 28; i += 8) + pr_info("> %8x %8x %8x %8x %8x %8x %8x %8x\n", + ptr[i + 0], ptr[i + 1], ptr[i + 2], ptr[i + 3], ptr[i + 4], ptr[i + 5], + ptr[i + 6], ptr[i + 7]); + pr_info("CPU_PORT> %8x\n", ptr[28]); +} + +static void rtl838x_init_stats(struct rtl838x_switch_priv *priv) +{ + mutex_lock(&priv->reg_mutex); + + /* Enable statistics module: all counters plus debug. + * On RTL839x all counters are enabled by default + */ + if (priv->family_id == RTL8380_FAMILY_ID) + sw_w32_mask(0, 3, RTL838X_STAT_CTRL); + + /* Reset statistics counters */ + sw_w32_mask(0, 1, priv->r->stat_rst); + + mutex_unlock(&priv->reg_mutex); +} + +static int rtl838x_setup(struct dsa_switch *ds) +{ + int i; + u64 port_bitmap = 0; + struct rtl838x_switch_priv *priv = ds->priv; + + pr_info("%s called\n", __func__); + + /* Disable MAC polling the PHY so that we can start configuration */ + priv->r->set_port_reg(0, priv->r->smi_poll_ctrl); + + for (i = 0; i < ds->num_ports; i++) + priv->ports[i].enable = false; + priv->ports[priv->cpu_port].enable = true; + + /* Isolate ports from each other: traffic only CPU <-> port */ + for (i = 0; i < priv->cpu_port; i++) { + if (priv->ports[i].phy) { + priv->r->set_port_iso_ctrl(1 << priv->cpu_port, i); + priv->r->mask_port_iso_ctrl(0, 1 << i, i); + port_bitmap |= 1 << i; + } + } + priv->r->set_port_iso_ctrl(port_bitmap, priv->cpu_port); + + rtl838x_print_matrix(); + + rtl838x_init_stats(priv); + + /* Enable MAC Polling PHY again */ + rtl838x_enable_phy_polling(priv); + pr_info("Please wait until PHY is settled\n"); + msleep(1000); + return 0; +} + +static void rtl838x_get_strings(struct dsa_switch *ds, + int port, u32 stringset, u8 *data) +{ + int i; + + if (stringset != ETH_SS_STATS) + return; + + for (i = 0; i < ARRAY_SIZE(rtl838x_mib); i++) + strncpy(data + i * ETH_GSTRING_LEN, rtl838x_mib[i].name, + ETH_GSTRING_LEN); +} + +static void rtl838x_get_ethtool_stats(struct dsa_switch *ds, int port, + uint64_t *data) +{ + struct rtl838x_switch_priv *priv = ds->priv; + const struct rtl838x_mib_desc *mib; + int i; + u64 high; + + for (i = 0; i < ARRAY_SIZE(rtl838x_mib); i++) { + mib = &rtl838x_mib[i]; + + data[i] = sw_r32(priv->r->stat_port_std_mib(port) + 252 - mib->offset); + if (mib->size == 2) { + high = sw_r32(priv->r->stat_port_std_mib(port) + 252 - mib->offset - 4); + data[i] |= high << 32; + } + } +} + +static int rtl838x_get_sset_count(struct dsa_switch *ds, int port, int sset) +{ + if (sset != ETH_SS_STATS) + return 0; + + return ARRAY_SIZE(rtl838x_mib); +} + +static enum dsa_tag_protocol +rtl838x_get_tag_protocol(struct dsa_switch *ds, int port) +{ + /* The switch does not tag the frames, instead internally the header + * structure for each packet is tagged accordingly. + */ + return DSA_TAG_PROTO_TRAILER; +} + +static int rtl838x_get_l2aging(struct rtl838x_switch_priv *priv) +{ + int t = sw_r32(priv->r->l2_ctrl_1) & 0x7fffff; + + pr_debug("RTL838X_L2_CTRL_1 %x\n", sw_r32(priv->r->l2_ctrl_1)); + + t = t * 128 / 625; /* Aging time in seconds. 0: L2 aging disabled */ + pr_info("L2 AGING time: %d sec\n", t); + pr_info("Dynamic aging for ports: %x\n", + sw_r32(priv->r->l2_port_aging_out)); + return t; +} + +/* + * Set Switch L2 Aging time, t is time in milliseconds + * t = 0: aging is disabled + */ +static int rtl838x_set_l2aging(struct dsa_switch *ds, u32 t) +{ + struct rtl838x_switch_priv *priv = ds->priv; + /* Convert time in mseconds to internal value */ + if (t > 0x10000000) /* Set to maximum */ + t = 0x7fffff; + else + t = ((t * 625) / 1000 + 127) / 128; + + sw_w32(t, priv->r->l2_ctrl_1); + + return 0; +} + +static void rtl838x_fast_age(struct dsa_switch *ds, int port) +{ + struct rtl838x_switch_priv *priv = ds->priv; + int s = priv->family_id == RTL8390_FAMILY_ID ? 2 : 0; + + pr_info("FAST AGE port %d\n", port); + mutex_lock(&priv->reg_mutex); + /* RTL838X_L2_TBL_FLUSH_CTRL register bits, 839x has 1 bit larger + * port fields: + * 0-4: Replacing port + * 5-9: Flushed/replaced port + * 10-21: FVID + * 22: Entry types: 1: dynamic, 0: also static + * 23: Match flush port + * 24: Match FVID + * 25: Flush (0) or replace (1) L2 entries + * 26: Status of action (1: Start, 0: Done) + */ + sw_w32(1 << (26 + s) | 1 << (23 + s) | port << 5, priv->r->l2_tbl_flush_ctrl); + + do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & (1 << (26 + s))); + + mutex_unlock(&priv->reg_mutex); +} + +/* + * Applies the same hash algorithm as the one used currently by the ASIC + */ +static u32 rtl838x_hash(struct rtl838x_switch_priv *priv, u64 seed) +{ + u32 h1, h2, h3, h; + + if (sw_r32(priv->r->l2_ctrl_0) & 1) { + h1 = (seed >> 11) & 0x7ff; + h1 = ((h1 & 0x1f) << 6) | ((h1 >> 5) & 0x3f); + + h2 = (seed >> 33) & 0x7ff; + h2 = ((h2 & 0x3f) << 5) | ((h2 >> 6) & 0x1f); + + h3 = (seed >> 44) & 0x7ff; + h3 = ((h3 & 0x7f) << 4) | ((h3 >> 7) & 0xf); + + h = h1 ^ h2 ^ h3 ^ ((seed >> 55) & 0x1ff); + h ^= ((seed >> 22) & 0x7ff) ^ (seed & 0x7ff); + } else { + h = ((seed >> 55) & 0x1ff) ^ ((seed >> 44) & 0x7ff) + ^ ((seed >> 33) & 0x7ff) ^ ((seed >> 22) & 0x7ff) + ^ ((seed >> 11) & 0x7ff) ^ (seed & 0x7ff); + } + + return h; +} + +static u64 rtl838x_hash_key(struct rtl838x_switch_priv *priv, u64 mac, u32 vid) +{ + return rtl838x_hash(priv, mac << 12 | vid); +} + +static u64 read_l2_entry_using_hash(u32 hash, u32 position, u32 *r) +{ + u64 entry; + /* Search in SRAM, with hash and at position in hash bucket (0-3) */ + u32 idx = (0 << 14) | (hash << 2) | position; + + u32 cmd = 1 << 16 /* Execute cmd */ + | 1 << 15 /* Read */ + | 0 << 13 /* Table type 0b00 */ + | (idx & 0x1fff); + + sw_w32(cmd, RTL838X_TBL_ACCESS_L2_CTRL); + do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL) & (1 << 16)); + r[0] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(0)); + r[1] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(1)); + r[2] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(2)); + + entry = (((u64) r[1]) << 32) | (r[2] & 0xfffff000) | (r[0] & 0xfff); + return entry; +} + +static u64 rtl838x_read_cam(int idx, u32 *r) +{ + u64 entry; + u32 cmd = 1 << 16 /* Execute cmd */ + | 1 << 15 /* Read */ + | 1 << 13 /* Table type 0b01 */ + | (idx & 0x3f); + sw_w32(cmd, RTL838X_TBL_ACCESS_L2_CTRL); + do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL) & (1 << 16)); + r[0] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(0)); + r[1] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(1)); + r[2] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(2)); + + entry = (((u64) r[1]) << 32) | (r[2] & 0xfffff000) | (r[0] & 0xfff); + return entry; +} + +static void rtl838x_write_cam(int idx, u32 *r) +{ + u32 cmd = 1 << 16 /* Execute cmd */ + | 1 << 15 /* Read */ + | 1 << 13 /* Table type 0b01 */ + | (idx & 0x3f); + + sw_w32(r[0], RTL838X_TBL_ACCESS_L2_DATA(0)); + sw_w32(r[1], RTL838X_TBL_ACCESS_L2_DATA(1)); + sw_w32(r[2], RTL838X_TBL_ACCESS_L2_DATA(2)); + + sw_w32(cmd, RTL838X_TBL_ACCESS_L2_CTRL); + do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL) & (1 << 16)); +} + +static void rtl838x_write_hash(int idx, u32 *r) +{ + u32 cmd = 1 << 16 /* Execute cmd */ + | 0 << 15 /* Write */ + | 0 << 13 /* Table type 0b00 */ + | (idx & 0x1fff); + + sw_w32(0, RTL838X_TBL_ACCESS_L2_DATA(0)); + sw_w32(0, RTL838X_TBL_ACCESS_L2_DATA(1)); + sw_w32(0, RTL838X_TBL_ACCESS_L2_DATA(2)); + sw_w32(cmd, RTL838X_TBL_ACCESS_L2_CTRL); + do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL) & (1 << 16)); +} + +static void dump_fdb(struct rtl838x_switch_priv *priv) +{ + u32 r[3]; + int i; + u8 mac[6]; + u16 vid, rvid; + + mutex_lock(&priv->reg_mutex); + + for (i = 0; i < 8192; i++) { + read_l2_entry_using_hash(i >> 2, i & 0x3, r); + mac[0] = (r[1] >> 20); + mac[1] = (r[1] >> 12); + mac[2] = (r[1] >> 4); + mac[3] = (r[1] & 0xf) << 4 | (r[2] >> 28); + mac[4] = (r[2] >> 20); + mac[5] = (r[2] >> 12); + vid = r[0] & 0xfff; + rvid = r[2] & 0xfff; + + if (!(r[0] >> 17)) /* Check for invalid entry */ + continue; + + pr_info("-> port %02d: %pM, vid: %d, rvid: %d\n", + (r[0] >> 12) & priv->port_mask, &mac[0], vid, rvid); + } + + mutex_unlock(&priv->reg_mutex); +} + +static int rtl838x_port_fdb_dump(struct dsa_switch *ds, int port, + dsa_fdb_dump_cb_t *cb, void *data) +{ + u32 r[3]; + u8 mac[6]; + u16 vid, rvid; + struct rtl838x_switch_priv *priv = ds->priv; + int i; + + mutex_lock(&priv->reg_mutex); + + for (i = 0; i < 8192; i++) { + read_l2_entry_using_hash(i >> 2, i & 0x3, r); + mac[0] = (r[1] >> 20); + mac[1] = (r[1] >> 12); + mac[2] = (r[1] >> 4); + mac[3] = (r[1] & 0xf) << 4 | (r[2] >> 28); + mac[4] = (r[2] >> 20); + mac[5] = (r[2] >> 12); + vid = r[0] & 0xfff; + rvid = r[2] & 0xfff; + + if (!(r[0] >> 17)) /* Check for invalid entry */ + continue; + + if (port == ((r[0] >> 12) & 0x1f)) { + pr_info("-> mac %pM, vid: %d, rvid: %d\n", &mac[0], vid, rvid); + cb(mac, vid, (r[0] >> 19) & 1, data); + } + } + + for (i = 0; i < 64; i++) { + rtl838x_read_cam(i, r); + mac[0] = (r[1] >> 20); + mac[1] = (r[1] >> 12); + mac[2] = (r[1] >> 4); + mac[3] = (r[1] & 0xf) << 4 | (r[2] >> 28); + mac[4] = (r[2] >> 20); + mac[5] = (r[2] >> 12); + vid = r[0] & 0xfff; + + if (!(r[0] >> 17)) + continue; + + pr_info("Found in CAM: R1 %x R2 %x R3 %x\n", r[0], r[1], r[2]); + if (port == ((r[0] >> 12) & priv->port_mask)) + cb(mac, vid, (r[0] >> 19) & 1, data); + } + + mutex_unlock(&priv->reg_mutex); + return 0; +} + +static int rtl838x_port_fdb_del(struct dsa_switch *ds, int port, + const unsigned char *addr, u16 vid) +{ + struct rtl838x_switch_priv *priv = ds->priv; + u64 mac = ether_addr_to_u64(addr); + u32 key = rtl838x_hash_key(priv, mac, vid); + int i; + u32 r[3]; + u64 entry; + int idx = -1; + int err = 0; + + pr_info("In %s, mac %llx, vid: %d, key: %x\n", __func__, mac, vid, key); + mutex_lock(&priv->reg_mutex); + for (i = 0; i < 4; i++) { + entry = read_l2_entry_using_hash(key, i, r); + if (!(r[0] >> 17)) /* Check for invalid entry */ + continue; + if ((entry & 0x0fffffffffffffff) == ((mac << 12) | vid)) { + idx = (key << 2) | i; + break; + } + } + + if (idx >= 0) { + r[0] = r[1] = r[2] = 0; + rtl838x_write_hash(idx, r); + goto out; + } + + /* Check CAM for spillover from hash buckets */ + for (i = 0; i < 64; i++) { + entry = rtl838x_read_cam(i, r); + if ((entry & 0x0fffffffffffffff) == ((mac << 12) | vid)) { + idx = i; + break; + } + } + if (idx >= 0) { + r[0] = r[1] = r[2] = 0; + rtl838x_write_cam(idx, r); + goto out; + } + err = -ENOENT; +out: + mutex_unlock(&priv->reg_mutex); + return err; +} + +static int rtl838x_port_fdb_add(struct dsa_switch *ds, int port, + const unsigned char *addr, u16 vid) +{ + struct rtl838x_switch_priv *priv = ds->priv; + u64 mac = ether_addr_to_u64(addr); + u32 key = rtl838x_hash_key(priv, mac, vid); + int i; + u32 r[3]; + int idx = -1; + u64 entry; + int err = 0; + + mutex_lock(&priv->reg_mutex); + for (i = 0; i < 4; i++) { + entry = read_l2_entry_using_hash(key, i, r); + if (!(r[0] >> 17)) { /* Check for invalid entry */ + idx = (key << 2) | i; + break; + } + if ((entry & 0x0fffffffffffffff) == ((mac << 12) | vid)) { + idx = (key << 2) | i; + break; + } + } + if (idx >= 0) { + // Found for del: R1 60000 R2 901b0e9 R3 12b0e000, 901b0e912b0e000 + r[0] = 3 << 17 | port << 12; // Aging and port + r[0] |= vid; + r[1] = mac >> 16; + r[2] = (mac & 0xffff) << 12; /* rvid = 0 */ + rtl838x_write_hash(idx, r); + goto out; + } + + /* Hash bucket full, try CAM */ + for (i = 0; i < 64; i++) { + entry = rtl838x_read_cam(i, r); + if (!(r[0] >> 17)) { /* Check for invalid entry */ + if (idx < 0) /* First empty entry? */ + idx = i; + break; + } else if ((entry & 0x0fffffffffffffff) == ((mac << 12) | vid)) { + pr_debug("Found entry in CAM\n"); + idx = i; + break; + } + } + if (idx >= 0) { + r[0] = 3 << 17 | port << 12; // Aging + r[0] |= vid; + r[1] = mac >> 16; + r[2] = (mac & 0xffff) << 12; /* rvid = 0 */ + rtl838x_write_cam(idx, r); + goto out; + } + err = -ENOTSUPP; +out: + mutex_unlock(&priv->reg_mutex); + return err; +} + +static void rtl838x_port_stp_state_set(struct dsa_switch *ds, int port, + u8 state) +{ + u32 cmd, msti = 0; + u32 port_state[4]; + int index, bit, i; + + struct rtl838x_switch_priv *priv = ds->priv; + int n = priv->family_id == RTL8380_FAMILY_ID ? 2 : 4; + + pr_info("%s: port %d state %2x\n", __func__, port, state); + if (port >= priv->cpu_port) + return; + + mutex_lock(&priv->reg_mutex); + + index = n - (port >> 4) - 1; + bit = (port << 1) % 32; + + if (priv->family_id == RTL8380_FAMILY_ID) { + cmd = 1 << 15 /* Execute cmd */ + | 1 << 14 /* Read */ + | 2 << 12 /* Table type 0b10 */ + | (msti & 0xfff); + } else { + cmd = 1 << 16 /* Execute cmd */ + | 0 << 15 /* Read */ + | 5 << 12 /* Table type 0b101 */ + | (msti & 0xfff); + } + priv->r->exec_tbl0_cmd(cmd); + + for (i = 0; i < n; i++) + port_state[i] = sw_r32(priv->r->tbl_access_data_0(i)); + + pr_debug("Current state, port %d: %d\n", port, (port_state[index] >> bit) & 3); + port_state[index] &= ~(3 << bit); + + switch (state) { + case BR_STATE_DISABLED: /* 0 */ + port_state[index] |= (0 << bit); + break; + case BR_STATE_BLOCKING: /* 4 */ + case BR_STATE_LISTENING: /* 1 */ + port_state[index] |= (1 << bit); + break; + case BR_STATE_LEARNING: /* 2 */ + port_state[index] |= (2 << bit); + break; + case BR_STATE_FORWARDING: /* 3*/ + port_state[index] |= (3 << bit); + default: + break; + } + + if (priv->family_id == RTL8380_FAMILY_ID) { + cmd = 1 << 15 /* Execute cmd */ + | 0 << 14 /* Write */ + | 2 << 12 /* Table type 0b10 */ + | (msti & 0xfff); + } else { + cmd = 1 << 16 /* Execute cmd */ + | 1 << 15 /* Write */ + | 5 << 12 /* Table type 0b101 */ + | (msti & 0xfff); + } + for (i = 0; i < n; i++) + sw_w32(port_state[i], priv->r->tbl_access_data_0(i)); + priv->r->exec_tbl0_cmd(cmd); + + mutex_unlock(&priv->reg_mutex); +} + +static int rtl838x_port_mirror_add(struct dsa_switch *ds, int port, + struct dsa_mall_mirror_tc_entry *mirror, + bool ingress) +{ + /* We support 4 mirror groups, one destination port per group */ + int group; + struct rtl838x_switch_priv *priv = ds->priv; + + pr_info("In %s\n", __func__); + + for (group = 0; group < 4; group++) { + if (priv->mirror_group_ports[group] == mirror->to_local_port) + break; + } + if (group >= 4) { + for (group = 0; group < 4; group++) { + if (priv->mirror_group_ports[group] < 0) + break; + } + } + + if (group >= 4) + return -ENOSPC; + + pr_debug("Using group %d\n", group); + mutex_lock(&priv->reg_mutex); + /* Enable mirroring to port across VLANs (bit 11) */ + sw_w32(1 << 11 | (mirror->to_local_port << 4) | 1, RTL838X_MIR_CTRL(group)); + + if (ingress && (sw_r32(RTL838X_MIR_SPM_CTRL(group)) & (1 << port))) { + mutex_unlock(&priv->reg_mutex); + return -EEXIST; + } + if ((!ingress) && (sw_r32(RTL838X_MIR_DPM_CTRL(group)) & (1 << port))) { + mutex_unlock(&priv->reg_mutex); + return -EEXIST; + } + if (ingress) + sw_w32_mask(0, 1 << port, RTL838X_MIR_SPM_CTRL(group)); + else + sw_w32_mask(0, 1 << port, RTL838X_MIR_DPM_CTRL(group)); + + priv->mirror_group_ports[group] = mirror->to_local_port; + mutex_unlock(&priv->reg_mutex); + return 0; +} + +static void rtl838x_port_mirror_del(struct dsa_switch *ds, int port, + struct dsa_mall_mirror_tc_entry *mirror) +{ + int group = 0; + struct rtl838x_switch_priv *priv = ds->priv; + + pr_info("In %s\n", __func__); + for (group = 0; group < 4; group++) { + if (priv->mirror_group_ports[group] == mirror->to_local_port) + break; + } + if (group >= 4) + return; + + mutex_lock(&priv->reg_mutex); + if (mirror->ingress) { + /* Ingress, clear source port matrix */ + sw_w32_mask(1 << port, 0, RTL838X_MIR_SPM_CTRL(group)); + } else { + /* Egress, clear destination port matrix */ + sw_w32_mask(1 << port, 0, RTL838X_MIR_DPM_CTRL(group)); + } + + if (!(sw_r32(RTL838X_MIR_DPM_CTRL(group)) || sw_r32(RTL838X_MIR_DPM_CTRL(group)))) { + priv->mirror_group_ports[group] = -1; + sw_w32(0, RTL838X_MIR_CTRL(group)); + } + + mutex_unlock(&priv->reg_mutex); +} + + +void rtl838x_vlan_profile_dump(int index) +{ + u32 profile; + + if (index < 0 || index > 7) + return; + + profile = sw_r32(RTL838X_VLAN_PROFILE(index)); + + pr_info("VLAN %d: L2 learning: %d, L2 Unknown MultiCast Field %x", + index, profile & 1, (profile >> 1) & 0x1ff); + pr_info(" IPv4 Unkn MultiCast Field %x, IPv6 Unkn MultiCast Field: %x", + (profile >> 10) & 0x1ff, (profile >> 19) & 0x1ff); +} + +static int rtl838x_vlan_filtering(struct dsa_switch *ds, int port, + bool vlan_filtering) +{ + struct rtl838x_switch_priv *priv = ds->priv; + + pr_info("%s: port %d\n", __func__, port); + mutex_lock(&priv->reg_mutex); + + if (vlan_filtering) { + /* Enable ingress and egress filtering */ + if (port != priv->cpu_port) { + if (port < 16) { + sw_w32_mask(0b10 << (port << 1), + 0b01 << (port << 1), + RTL838X_VLAN_PORT_IGR_FLTR_0); + } else { + sw_w32_mask(0b10 << ((port - 16) << 1), + 0b01 << ((port - 16) << 1), + RTL838X_VLAN_PORT_IGR_FLTR_1); + } + } + sw_w32_mask(0, 1 << port, RTL838X_VLAN_PORT_EGR_FLTR); + } else { + /* Disable ingress and egress filtering */ + if (port != priv->cpu_port) { + if (port < 16) { + sw_w32_mask(0b11 << (port << 1), + 0, + RTL838X_VLAN_PORT_IGR_FLTR_0); + } else { + sw_w32_mask(0b11 << ((port - 16) << 1), + 0, + RTL838X_VLAN_PORT_IGR_FLTR_1); + } + } + sw_w32_mask(1 << port, 0, RTL838X_VLAN_PORT_EGR_FLTR); + } + + /* We need to do something to the CPU-Port, too */ + mutex_unlock(&priv->reg_mutex); + + return 0; +} + +static int rtl838x_vlan_prepare(struct dsa_switch *ds, int port, + const struct switchdev_obj_port_vlan *vlan) +{ + struct rtl838x_vlan_info info; + struct rtl838x_switch_priv *priv = ds->priv; + + pr_info("%s: port %d\n", __func__, port); + + mutex_lock(&priv->reg_mutex); + + priv->r->vlan_tables_read(1, &info); + + pr_info("Tagged ports %llx, untag %llx, prof %x, MC# %d, UC# %d, MSTI %x\n", + info.tagged_ports, info.untagged_ports, info.vlan_conf & 7, + (info.vlan_conf & 8) >> 3, (info.vlan_conf & 16) >> 4, + (info.vlan_conf & 0x3e0) >> 5); + + mutex_unlock(&priv->reg_mutex); + return 0; +} + +static void rtl838x_vlan_add(struct dsa_switch *ds, int port, + const struct switchdev_obj_port_vlan *vlan) +{ + struct rtl838x_vlan_info info; + struct rtl838x_switch_priv *priv = ds->priv; + int v; + u64 portmask; + + pr_info("%s port %d, vid_end %d, vid_end %d, flags %x\n", __func__, + port, vlan->vid_begin, vlan->vid_end, vlan->flags); + + if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) { + dev_err(priv->dev, "VLAN out of range: %d - %d", + vlan->vid_begin, vlan->vid_end); + return; + } + + mutex_lock(&priv->reg_mutex); + + if (vlan->flags & BRIDGE_VLAN_INFO_PVID) { + for (v = vlan->vid_begin; v <= vlan->vid_end; v++) { + /* Set both inner and outer PVID of the port */ + sw_w32((v << 16) | v, RTL838X_VLAN_PORT_PB_VLAN(port)); + } + } + + if (vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED) { + for (v = vlan->vid_begin; v <= vlan->vid_end; v++) { + /* Get untagged port memberships of this vlan */ + priv->r->vlan_tables_read(v, &info); + portmask = info.untagged_ports | (1 << port); + pr_debug("Untagged ports, VLAN %d: %llx\n", v, portmask); + priv->r->vlan_set_untagged(v, portmask); + } + } else { + for (v = vlan->vid_begin; v <= vlan->vid_end; v++) { + /* Get tagged port memberships of this vlan */ + priv->r->vlan_tables_read(v, &info); + portmask = info.tagged_ports | (1 << port); + pr_debug("Tagged ports, VLAN %d: %llx\n", v, portmask); + priv->r->vlan_set_tagged(v, portmask, info.vlan_conf); + } + } + mutex_unlock(&priv->reg_mutex); +} + +static int rtl838x_vlan_del(struct dsa_switch *ds, int port, + const struct switchdev_obj_port_vlan *vlan) +{ + struct rtl838x_vlan_info info; + struct rtl838x_switch_priv *priv = ds->priv; + int v; + u64 portmask; + + pr_info("%s: port %d, vid_end %d, vid_end %d, flags %x\n", __func__, + port, vlan->vid_begin, vlan->vid_end, vlan->flags); + + if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) { + dev_err(priv->dev, "VLAN out of range: %d - %d", + vlan->vid_begin, vlan->vid_end); + return -ENOTSUPP; + } + + mutex_lock(&priv->reg_mutex); + + for (v = vlan->vid_begin; v <= vlan->vid_end; v++) { + /* Reset both inner and out PVID of the port */ + sw_w32(0, RTL838X_VLAN_PORT_PB_VLAN(port)); + + if (vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED) { + /* Get untagged port memberships of this vlan */ + priv->r->vlan_tables_read(v, &info); + portmask = info.untagged_ports & (~(1 << port)); + pr_info("Untagged ports, VLAN %d: %llx\n", v, portmask); + priv->r->vlan_set_untagged(v, portmask); + } + + /* Get tagged port memberships of this vlan */ + priv->r->vlan_tables_read(v, &info); + portmask = info.tagged_ports & (~(1 << port)); + pr_info("Tagged ports, VLAN %d: %llx\n", v, portmask); + priv->r->vlan_set_tagged(v, portmask, info.vlan_conf); + } + mutex_unlock(&priv->reg_mutex); + + return 0; +} + +static void rtl838x_port_bridge_leave(struct dsa_switch *ds, int port, + struct net_device *bridge) +{ + struct rtl838x_switch_priv *priv = ds->priv; + u64 port_bitmap = 1 << priv->cpu_port; + int i; + + pr_info("%s %x: %d", __func__, (u32)priv, port); + mutex_lock(&priv->reg_mutex); + for (i = 0; i < ds->num_ports; i++) { + /* Remove this port from the port matrix of the other ports + * in the same bridge. If the port is disabled, port matrix + * is kept and not being setup until the port becomes enabled. + * And the other port's port matrix cannot be broken when the + * other port is still a VLAN-aware port. + */ + if (dsa_is_user_port(ds, i) && i != port) { + if (dsa_to_port(ds, i)->bridge_dev != bridge) + continue; + if (priv->ports[i].enable) + priv->r->mask_port_iso_ctrl(1 << port, 0, i); + priv->ports[i].pm |= 1 << port; + + port_bitmap &= ~(1 << i); + } + } + + /* Add all other ports to this port matrix. */ + if (priv->ports[port].enable) + priv->r->mask_port_iso_ctrl(0, port_bitmap, port); + priv->ports[port].pm &= ~port_bitmap; + mutex_unlock(&priv->reg_mutex); + + rtl838x_print_matrix(); +} + +static int rtl838x_port_bridge_join(struct dsa_switch *ds, int port, + struct net_device *bridge) +{ + struct rtl838x_switch_priv *priv = ds->priv; + u64 port_bitmap = 1 << priv->cpu_port; + int i; + + pr_info("%s %x: %d %llx", __func__, (u32)priv, port, port_bitmap); + mutex_lock(&priv->reg_mutex); + for (i = 0; i < ds->num_ports; i++) { + /* Add this port to the port matrix of the other ports in the + * same bridge. If the port is disabled, port matrix is kept + * and not being setup until the port becomes enabled. + */ + if (dsa_is_user_port(ds, i) && i != port) { + if (dsa_to_port(ds, i)->bridge_dev != bridge) + continue; + if (priv->ports[i].enable) + priv->r->mask_port_iso_ctrl(0, 1 << port, i); + priv->ports[i].pm |= 1 << port; + + port_bitmap |= 1 << i; + } + } + + /* Add all other ports to this port matrix. */ + if (priv->ports[port].enable) { + priv->r->mask_port_iso_ctrl(0, 1 << port, priv->cpu_port); + priv->r->mask_port_iso_ctrl(0, port_bitmap, port); + } + priv->ports[port].pm |= port_bitmap; + mutex_unlock(&priv->reg_mutex); + + return 0; +} + +static int rtl838x_port_enable(struct dsa_switch *ds, int port, + struct phy_device *phydev) +{ + struct rtl838x_switch_priv *priv = ds->priv; + + pr_info("%s: %x %d", __func__, (u32) priv, port); + priv->ports[port].enable = true; + + if (dsa_is_cpu_port(ds, port)) + return 0; + + /* add port to switch mask of CPU_PORT */ + priv->r->mask_port_iso_ctrl(0, 1 << port, priv->cpu_port); + + /* add all other ports in the same bridge to switch mask of port */ + priv->r->mask_port_iso_ctrl(0, priv->ports[port].pm, port); + + /* enable PHY polling */ + sw_w32_mask(0, 1 << port, RTL838X_SMI_POLL_CTRL); + + return 0; +} + +static void rtl838x_port_disable(struct dsa_switch *ds, int port) +{ + struct rtl838x_switch_priv *priv = ds->priv; + + pr_info("%s %x: %d", __func__, (u32)priv, port); + + /* you can only disable user ports */ + if (!dsa_is_user_port(ds, port)) + return; + + /* remove port from switch mask of CPU_PORT */ + priv->r->mask_port_iso_ctrl(1 << port, 0, priv->cpu_port); + + /* remove all other ports in the same bridge from switch mask of port */ + priv->r->mask_port_iso_ctrl(priv->ports[port].pm, 0, port); + + priv->ports[port].enable = false; + + /* disable PHY polling */ + sw_w32_mask(1 << port, 0, RTL838X_SMI_POLL_CTRL); +} + +static int rtl838x_get_mac_eee(struct dsa_switch *ds, int port, + struct ethtool_eee *e) +{ + struct rtl838x_switch_priv *priv = ds->priv; + + pr_info("%s: port %d", __func__, port); + e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full; + if (sw_r32(priv->r->mac_force_mode_ctrl(port)) & (1 << 9)) + e->advertised |= ADVERTISED_100baseT_Full; + + if (sw_r32(priv->r->mac_force_mode_ctrl(port)) & (1 << 10)) + e->advertised |= ADVERTISED_1000baseT_Full; + + e->eee_enabled = priv->ports[port].eee_enabled; + pr_info("enabled: %d, active %x\n", e->eee_enabled, e->advertised); + + if (sw_r32(RTL838X_MAC_EEE_ABLTY) & (1 << port)) { + e->lp_advertised = ADVERTISED_100baseT_Full; + e->lp_advertised |= ADVERTISED_1000baseT_Full; + } + + e->eee_active = !!(e->advertised & e->lp_advertised); + pr_info("active: %d, lp %x\n", e->eee_active, e->lp_advertised); + + return 0; +} + +static int rtl838x_set_mac_eee(struct dsa_switch *ds, int port, + struct ethtool_eee *e) +{ + struct rtl838x_switch_priv *priv = ds->priv; + + pr_info("%s: port %d", __func__, port); + if (e->eee_enabled) { + pr_info("Globally enabling EEE\n"); + sw_w32_mask(0x4, 0, RTL838X_SMI_GLB_CTRL); + } + if (e->eee_enabled) { + pr_info("Enabling EEE for MAC %d\n", port); + sw_w32_mask(0, 3 << 9, priv->r->mac_force_mode_ctrl(port)); + sw_w32_mask(0, 1 << port, RTL838X_EEE_PORT_TX_EN); + sw_w32_mask(0, 1 << port, RTL838X_EEE_PORT_RX_EN); + priv->ports[port].eee_enabled = true; + e->eee_enabled = true; + } else { + pr_info("Disabling EEE for MAC %d\n", port); + sw_w32_mask(3 << 9, 0, priv->r->mac_force_mode_ctrl(port)); + sw_w32_mask(1 << port, 0, RTL838X_EEE_PORT_TX_EN); + sw_w32_mask(1 << port, 0, RTL838X_EEE_PORT_RX_EN); + priv->ports[port].eee_enabled = false; + e->eee_enabled = false; + } + return 0; +} + +static void rtl838x_phylink_mac_config(struct dsa_switch *ds, int port, + unsigned int mode, + const struct phylink_link_state *state) +{ + struct rtl838x_switch_priv *priv = ds->priv; + u32 reg; + + pr_info("%s port %d, mode %x\n", __func__, port, mode); + + if (port == priv->cpu_port) { + /* Set Speed, duplex, flow control + * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL + * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN + * | MEDIA_SEL + */ + if (priv->family_id == RTL8380_FAMILY_ID) { + sw_w32(0x6192F, priv->r->mac_force_mode_ctrl(priv->cpu_port)); + /* allow CRC errors on CPU-port */ + sw_w32_mask(0, 0x8, RTL838X_MAC_PORT_CTRL(priv->cpu_port)); + } else { + sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl(priv->cpu_port)); + } + return; + } + + reg = sw_r32(priv->r->mac_force_mode_ctrl(port)); + if (mode == MLO_AN_PHY) { + pr_info("PHY autonegotiates\n"); + reg |= 1 << 2; + sw_w32(reg, priv->r->mac_force_mode_ctrl(port)); + return; + } + + if (mode != MLO_AN_FIXED) + pr_info("Not fixed\n"); + + /* Clear id_mode_dis bit, and the existing port mode, let + * RGMII_MODE_EN bet set by mac_link_{up,down} + */ + reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN); + + if (state->pause & MLO_PAUSE_TXRX_MASK) { + if (state->pause & MLO_PAUSE_TX) + reg |= TX_PAUSE_EN; + reg |= RX_PAUSE_EN; + } + + reg &= ~(3 << 4); + switch (state->speed) { + case SPEED_1000: + reg |= 2 << 4; + break; + case SPEED_100: + reg |= 1 << 4; + break; + } + + reg &= ~(DUPLEX_FULL | FORCE_LINK_EN); + if (state->link) + reg |= FORCE_LINK_EN; + if (state->duplex == DUPLEX_FULL) + reg |= DUPLX_MODE; + + // Disable AN + reg &= ~(1 << 2); + sw_w32(reg, priv->r->mac_force_mode_ctrl(port)); +} + +static void rtl838x_phylink_mac_link_down(struct dsa_switch *ds, int port, + unsigned int mode, + phy_interface_t interface) +{ + /* Stop TX/RX to port */ + sw_w32_mask(0x03, 0, RTL838X_MAC_PORT_CTRL(port)); +} + +static void rtl838x_phylink_mac_link_up(struct dsa_switch *ds, int port, + unsigned int mode, + phy_interface_t interface, + struct phy_device *phydev) +{ + /* Restart TX/RX to port */ + sw_w32_mask(0, 0x03, RTL838X_MAC_PORT_CTRL(port)); +} + +static void rtl838x_phylink_validate(struct dsa_switch *ds, int port, + unsigned long *supported, + struct phylink_link_state *state) +{ + __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; + + pr_info("In %s port %d", __func__, port); + + if (!phy_interface_mode_is_rgmii(state->interface) && + state->interface != PHY_INTERFACE_MODE_1000BASEX && + state->interface != PHY_INTERFACE_MODE_MII && + state->interface != PHY_INTERFACE_MODE_REVMII && + state->interface != PHY_INTERFACE_MODE_GMII && + state->interface != PHY_INTERFACE_MODE_QSGMII && + state->interface != PHY_INTERFACE_MODE_INTERNAL && + state->interface != PHY_INTERFACE_MODE_SGMII) { + bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); + dev_err(ds->dev, + "Unsupported interface: %d for port %d\n", + state->interface, port); + return; + } + + /* switch chip-id? if (priv->id == 0x8382) */ + + /* Allow all the expected bits */ + phylink_set(mask, Autoneg); + phylink_set_port_modes(mask); + phylink_set(mask, Pause); + phylink_set(mask, Asym_Pause); + + /* With the exclusion of MII and Reverse MII, we support Gigabit, + * including Half duplex + */ + if (state->interface != PHY_INTERFACE_MODE_MII && + state->interface != PHY_INTERFACE_MODE_REVMII) { + phylink_set(mask, 1000baseT_Full); + phylink_set(mask, 1000baseT_Half); + } + + /* On both the 8380 and 8382, ports 24-27 are SFP ports */ + if (port >= 24 && port <= 27) + phylink_set(mask, 1000baseX_Full); + + phylink_set(mask, 10baseT_Half); + phylink_set(mask, 10baseT_Full); + phylink_set(mask, 100baseT_Half); + phylink_set(mask, 100baseT_Full); + + bitmap_and(supported, supported, mask, + __ETHTOOL_LINK_MODE_MASK_NBITS); + bitmap_and(state->advertising, state->advertising, mask, + __ETHTOOL_LINK_MODE_MASK_NBITS); +} + +static int rtl838x_phylink_mac_link_state(struct dsa_switch *ds, int port, + struct phylink_link_state *state) +{ + struct rtl838x_switch_priv *priv = ds->priv; + u32 speed; + + if (port < 0 || port > priv->cpu_port) + return -EINVAL; + + state->link = 0; + if (sw_r32(RTL838X_MAC_LINK_STS) & (1 << port)) + state->link = 1; + state->duplex = 0; + if (sw_r32(RTL838X_MAC_LINK_DUP_STS) & (1 << port)) + state->duplex = 1; + + speed = sw_r32(RTL838X_MAC_LINK_SPD_STS(port)); + speed >>= (port % 16) << 1; + switch (speed & 0x3) { + case 0: + state->speed = SPEED_10; + break; + case 1: + state->speed = SPEED_100; + break; + case 2: + state->speed = SPEED_1000; + break; + case 3: + if (port == 24 || port == 26) /* Internal serdes */ + state->speed = SPEED_2500; + else + state->speed = SPEED_100; /* Is in fact 500Mbit */ + } + + state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX); + if (sw_r32(RTL838X_MAC_RX_PAUSE_STS) & (1 << port)) + state->pause |= MLO_PAUSE_RX; + if (sw_r32(RTL838X_MAC_TX_PAUSE_STS) & (1 << port)) + state->pause |= MLO_PAUSE_TX; + return 1; +} + +static int rtl838x_mdio_probe(struct rtl838x_switch_priv *priv) +{ + struct device *dev = priv->dev; + struct device_node *dn, *mii_np = dev->of_node; + struct mii_bus *bus; + int ret; + u32 pn; + + pr_info("In %s\n", __func__); + mii_np = of_find_compatible_node(NULL, NULL, "realtek,rtl838x-mdio"); + if (mii_np) { + pr_info("Found compatible MDIO node!\n"); + } else { + dev_err(priv->dev, "no %s child node found", "mdio-bus"); + return -ENODEV; + } + + priv->mii_bus = of_mdio_find_bus(mii_np); + if (!priv->mii_bus) { + pr_info("Deferring probe of mdio bus\n"); + return -EPROBE_DEFER; + } + if (!of_device_is_available(mii_np)) + ret = -ENODEV; + + bus = devm_mdiobus_alloc(priv->ds->dev); + if (!bus) + return -ENOMEM; + + bus->name = "rtl838x slave mii"; + bus->read = &rtl838x_mdio_read; + bus->write = &rtl838x_mdio_write; + snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d", bus->name, dev->id); + bus->parent = dev; + priv->ds->slave_mii_bus = bus; + priv->ds->slave_mii_bus->priv = priv; + + ret = mdiobus_register(priv->ds->slave_mii_bus); + if (ret && mii_np) { + of_node_put(dn); + return ret; + } + + dn = mii_np; + for_each_node_by_name(dn, "ethernet-phy") { + if (of_property_read_u32(dn, "reg", &pn)) + continue; + + // Check for the integrated SerDes of the RTL8380M first + if (of_property_read_bool(dn, "phy-is-integrated") + && priv->id == 0x8380 && pn >= 24) { + pr_info("----> FÓUND A SERDES\n"); + priv->ports[pn].phy = PHY_RTL838X_SDS; + continue; + } + + if (of_property_read_bool(dn, "phy-is-integrated") + && !of_property_read_bool(dn, "sfp")) { + priv->ports[pn].phy = PHY_RTL8218B_INT; + continue; + } + + if (!of_property_read_bool(dn, "phy-is-integrated") + && of_property_read_bool(dn, "sfp")) { + priv->ports[pn].phy = PHY_RTL8214FC; + continue; + } + + if (!of_property_read_bool(dn, "phy-is-integrated") + && !of_property_read_bool(dn, "sfp")) { + priv->ports[pn].phy = PHY_RTL8218B_EXT; + continue; + } + } + + /* Disable MAC polling the PHY so that we can start configuration */ + sw_w32(0x00000000, RTL838X_SMI_POLL_CTRL); + + /* Enable PHY control via SoC */ + sw_w32_mask(0, 1 << 15, RTL838X_SMI_GLB_CTRL); + /* Power on fibre ports and reset them if necessary */ + if (priv->ports[24].phy == PHY_RTL838X_SDS) { + pr_info("Powering on fibre ports & reset\n"); + rtl8380_sds_power(24, 1); + rtl8380_sds_power(26, 1); + } + + pr_info("%s done\n", __func__); + return 0; +} + +static const struct dsa_switch_ops rtl838x_switch_ops = { + .get_tag_protocol = rtl838x_get_tag_protocol, + .setup = rtl838x_setup, + .port_vlan_filtering = rtl838x_vlan_filtering, + .port_vlan_prepare = rtl838x_vlan_prepare, + .port_vlan_add = rtl838x_vlan_add, + .port_vlan_del = rtl838x_vlan_del, + .port_bridge_join = rtl838x_port_bridge_join, + .port_bridge_leave = rtl838x_port_bridge_leave, + .port_stp_state_set = rtl838x_port_stp_state_set, + .set_ageing_time = rtl838x_set_l2aging, + .port_fast_age = rtl838x_fast_age, + .port_fdb_add = rtl838x_port_fdb_add, + .port_fdb_del = rtl838x_port_fdb_del, + .port_fdb_dump = rtl838x_port_fdb_dump, + .port_enable = rtl838x_port_enable, + .port_disable = rtl838x_port_disable, + .port_mirror_add = rtl838x_port_mirror_add, + .port_mirror_del = rtl838x_port_mirror_del, + .phy_read = dsa_phy_read, + .phy_write = dsa_phy_write, + .get_strings = rtl838x_get_strings, + .get_ethtool_stats = rtl838x_get_ethtool_stats, + .get_sset_count = rtl838x_get_sset_count, + .phylink_validate = rtl838x_phylink_validate, + .phylink_mac_link_state = rtl838x_phylink_mac_link_state, + .phylink_mac_config = rtl838x_phylink_mac_config, + .phylink_mac_link_down = rtl838x_phylink_mac_link_down, + .phylink_mac_link_up = rtl838x_phylink_mac_link_up, + .set_mac_eee = rtl838x_set_mac_eee, + .get_mac_eee = rtl838x_get_mac_eee, + +}; + +static int __init rtl838x_sw_probe(struct platform_device *pdev) +{ + int err = 0, i; + struct rtl838x_switch_priv *priv; + struct device *dev = &pdev->dev; + + pr_info("Probing RTL838X switch device\n"); + if (!pdev->dev.of_node) { + dev_err(dev, "No DT found\n"); + return -EINVAL; + } + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->ds = dsa_switch_alloc(dev, DSA_MAX_PORTS); + + if (!priv->ds) + return -ENOMEM; + priv->ds->dev = dev; + priv->ds->priv = priv; + priv->ds->ops = &rtl838x_switch_ops; + priv->dev = dev; + + priv->family_id = soc_info.family; + priv->id = soc_info.id; + if (soc_info.family == RTL8380_FAMILY_ID) { + priv->cpu_port = RTL838X_CPU_PORT; + priv->port_mask = 0x1f; + priv->r = &rtl838x_reg; + priv->ds->num_ports = 30; + rtl8380_get_version(priv); + } else { + priv->cpu_port = RTL839X_CPU_PORT; + priv->port_mask = 0x3f; + priv->r = &rtl839x_reg; + priv->ds->num_ports = 53; + rtl8390_get_version(priv); + } + pr_info("Chip version %c\n", priv->version); + + err = rtl838x_mdio_probe(priv); + if (err) { + /* Probing fails the 1st time because of missing ethernet driver + * initialization. Use this to disable traffic in case the bootloader left if on + */ + return err; + } + err = dsa_register_switch(priv->ds); + if (err) { + dev_err(dev, "Error registering switch: %d\n", err); + return err; + } + + /* Enable link and media change interrupts. Are the SERDES masks needed? */ + sw_w32_mask(0, 3, priv->r->isr_glb_src); + /* ... for all ports */ + priv->r->set_port_reg(0xffffffffffffffff, priv->r->isr_port_link_sts_chg); + priv->r->set_port_reg(0xffffffffffffffff, priv->r->imr_port_link_sts_chg); + + priv->link_state_irq = 20; + if (priv->family_id == RTL8380_FAMILY_ID) { + err = request_irq(priv->link_state_irq, rtl838x_switch_irq, + IRQF_SHARED, "rtl8838x-link-state", priv->ds); + } else { + err = request_irq(priv->link_state_irq, rtl839x_switch_irq, + IRQF_SHARED, "rtl8838x-link-state", priv->ds); + } + if (err) { + dev_err(dev, "Error setting up switch interrupt.\n"); + /* Need to free allocated switch here */ + } + + /* Enable interrupts for switch */ + sw_w32(0x1, priv->r->imr_glb); + + rtl838x_get_l2aging(priv); + + /* Clear all destination ports for mirror groups */ + for (i = 0; i < 4; i++) + priv->mirror_group_ports[i] = -1; + + return err; +} + +static int rtl838x_sw_remove(struct platform_device *pdev) +{ + pr_info("Removing platform driver for rtl838x-sw\n"); + return 0; +} + +static const struct of_device_id rtl838x_switch_of_ids[] = { + { .compatible = "realtek,rtl838x-switch"}, + { /* sentinel */ } +}; + + +MODULE_DEVICE_TABLE(of, rtl838x_switch_of_ids); + +static struct platform_driver rtl838x_switch_driver = { + .probe = rtl838x_sw_probe, + .remove = rtl838x_sw_remove, + .driver = { + .name = "rtl838x-switch", + .pm = NULL, + .of_match_table = rtl838x_switch_of_ids, + }, +}; + +module_platform_driver(rtl838x_switch_driver); + +MODULE_AUTHOR("B. Koblitz"); +MODULE_DESCRIPTION("RTL838X SoC Switch Driver"); +MODULE_LICENSE("GPL"); diff --git a/target/linux/rtl838x/files-5.4/drivers/net/ethernet/rtl838x_eth.c b/target/linux/rtl838x/files-5.4/drivers/net/ethernet/rtl838x_eth.c new file mode 100644 index 0000000000..9634b6a24f --- /dev/null +++ b/target/linux/rtl838x/files-5.4/drivers/net/ethernet/rtl838x_eth.c @@ -0,0 +1,1205 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * linux/drivers/net/ethernet/rtl838x_eth.c + * Copyright (C) 2020 B. Koblitz + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include "rtl838x_eth.h" + +extern struct rtl838x_soc_info soc_info; + +/* + * Maximum number of RX rings is 8, assigned by switch based on + * packet/port priortity (not implemented) + * Maximum number of TX rings is 2 (only ring 0 used) + * RX ringlength needs to be at least 200, otherwise CPU and Switch + * may gridlock. + */ +#define RXRINGS 2 +#define RXRINGLEN 300 +#define TXRINGS 2 +#define TXRINGLEN 160 +#define TX_EN 0x8 +#define RX_EN 0x4 +#define TX_DO 0x2 +#define WRAP 0x2 + +#define RING_BUFFER 1600 + +struct p_hdr { + uint8_t *buf; + uint16_t reserved; + uint16_t size; /* buffer size */ + uint16_t offset; + uint16_t len; /* pkt len */ + uint16_t reserved2; + uint16_t cpu_tag[5]; +} __packed __aligned(1); + +struct ring_b { + uint32_t rx_r[RXRINGS][RXRINGLEN]; + uint32_t tx_r[TXRINGS][TXRINGLEN]; + struct p_hdr rx_header[RXRINGS][RXRINGLEN]; + struct p_hdr tx_header[TXRINGS][TXRINGLEN]; + uint32_t c_rx[RXRINGS]; + uint32_t c_tx[TXRINGS]; + uint8_t rx_space[RXRINGS*RXRINGLEN*RING_BUFFER]; + uint8_t tx_space[TXRINGLEN*RING_BUFFER]; +}; + +struct rtl838x_eth_priv { + struct net_device *netdev; + struct platform_device *pdev; + void *membase; + spinlock_t lock; + struct mii_bus *mii_bus; + struct napi_struct napi; + struct phylink *phylink; + struct phylink_config phylink_config; + u16 id; + u16 family_id; + const struct rtl838x_reg *r; + u8 cpu_port; +}; + +static const struct rtl838x_reg rtl838x_reg = { + .mac_port_ctrl = rtl838x_mac_port_ctrl, + .dma_if_intr_sts = RTL838X_DMA_IF_INTR_STS, + .dma_if_intr_msk = RTL838X_DMA_IF_INTR_MSK, + .dma_if_ctrl = RTL838X_DMA_IF_CTRL, + .mac_force_mode_ctrl = rtl838x_mac_force_mode_ctrl, + .dma_rx_base = rtl838x_dma_rx_base, + .dma_tx_base = rtl838x_dma_tx_base, + .dma_if_rx_ring_size = rtl838x_dma_if_rx_ring_size, + .dma_if_rx_ring_cntr = rtl838x_dma_if_rx_ring_cntr, + .dma_if_rx_cur = rtl838x_dma_if_rx_cur, + .rst_glb_ctrl = RTL838X_RST_GLB_CTRL_0, + .get_mac_link_sts = rtl838x_get_mac_link_sts, + .get_mac_link_dup_sts = rtl838x_get_mac_link_dup_sts, + .get_mac_link_spd_sts = rtl838x_get_mac_link_spd_sts, + .get_mac_rx_pause_sts = rtl838x_get_mac_rx_pause_sts, + .get_mac_tx_pause_sts = rtl838x_get_mac_tx_pause_sts, + .mac = RTL838X_MAC, + .l2_tbl_flush_ctrl = RTL838X_L2_TBL_FLUSH_CTRL, +}; + +static const struct rtl838x_reg rtl839x_reg = { + .mac_port_ctrl = rtl839x_mac_port_ctrl, + .dma_if_intr_sts = RTL839X_DMA_IF_INTR_STS, + .dma_if_intr_msk = RTL839X_DMA_IF_INTR_MSK, + .dma_if_ctrl = RTL839X_DMA_IF_CTRL, + .mac_force_mode_ctrl = rtl839x_mac_force_mode_ctrl, + .dma_rx_base = rtl839x_dma_rx_base, + .dma_tx_base = rtl839x_dma_tx_base, + .dma_if_rx_ring_size = rtl839x_dma_if_rx_ring_size, + .dma_if_rx_ring_cntr = rtl839x_dma_if_rx_ring_cntr, + .dma_if_rx_cur = rtl839x_dma_if_rx_cur, + .rst_glb_ctrl = RTL839X_RST_GLB_CTRL, + .get_mac_link_sts = rtl839x_get_mac_link_sts, + .get_mac_link_dup_sts = rtl839x_get_mac_link_dup_sts, + .get_mac_link_spd_sts = rtl839x_get_mac_link_spd_sts, + .get_mac_rx_pause_sts = rtl839x_get_mac_rx_pause_sts, + .get_mac_tx_pause_sts = rtl839x_get_mac_tx_pause_sts, + .mac = RTL839X_MAC, + .l2_tbl_flush_ctrl = RTL839X_L2_TBL_FLUSH_CTRL, +}; + +/* + * Discard the RX ring-buffers, called as part of the net-ISR + * when the buffer runs over + * Caller needs to hold priv->lock + */ +static void rtl838x_rb_cleanup(struct rtl838x_eth_priv *priv) +{ + int r; + u32 *last; + struct p_hdr *h; + struct ring_b *ring = priv->membase; + + for (r = 0; r < RXRINGS; r++) { + last = (u32 *)KSEG1ADDR(sw_r32(priv->r->dma_if_rx_cur(r))); + do { + if ((ring->rx_r[r][ring->c_rx[r]] & 0x1)) + break; + h = &ring->rx_header[r][ring->c_rx[r]]; + h->buf = (u8 *)CPHYSADDR(ring->rx_space + + r * ring->c_rx[r] * RING_BUFFER); + h->size = RING_BUFFER; + h->len = 0; + /* make sure the header is visible to the ASIC */ + mb(); + + ring->rx_r[r][ring->c_rx[r]] = CPHYSADDR(h) | 0x1 + | (ring->c_rx[r] == (RXRINGLEN-1) ? WRAP : 0x1); + ring->c_rx[r] = (ring->c_rx[r] + 1) % RXRINGLEN; + } while (&ring->rx_r[r][ring->c_rx[r]] != last); + } +} + +static irqreturn_t rtl838x_net_irq(int irq, void *dev_id) +{ + struct net_device *dev = dev_id; + struct rtl838x_eth_priv *priv = netdev_priv(dev); + u32 status = sw_r32(priv->r->dma_if_intr_sts); + + spin_lock(&priv->lock); + /* Ignore TX interrupt */ + if ((status & 0xf0000)) { + /* Clear ISR */ + sw_w32(0x000f0000, priv->r->dma_if_intr_sts); + } + + /* RX interrupt */ + if (status & 0x0ff00) { + /* Disable RX interrupt */ + sw_w32_mask(0xff00, 0, priv->r->dma_if_intr_msk); + sw_w32(0x0000ff00, priv->r->dma_if_intr_sts); + napi_schedule(&priv->napi); + } + + /* RX buffer overrun */ + if (status & 0x000ff) { + sw_w32(0x000000ff, priv->r->dma_if_intr_sts); + rtl838x_rb_cleanup(priv); + } + + spin_unlock(&priv->lock); + return IRQ_HANDLED; +} + +static void rtl838x_hw_reset(struct rtl838x_eth_priv *priv) +{ + u32 int_saved; + + pr_info("RESETTING %x, CPU_PORT %d\n", priv->family_id, priv->cpu_port); + /* Stop TX/RX */ + sw_w32(0x0, priv->r->mac_port_ctrl(priv->cpu_port)); + mdelay(500); + + int_saved = sw_r32(priv->r->dma_if_intr_msk); + /* Reset NIC */ + sw_w32(0x08, priv->r->rst_glb_ctrl); + do { + udelay(20); + } while (sw_r32(priv->r->rst_glb_ctrl) & 0x08); + mdelay(100); + + /* Restore notification settings: on RTL838x these bits are null */ + sw_w32_mask(7 << 20, int_saved & (7 << 20), priv->r->dma_if_intr_msk); + + /* Restart TX/RX to CPU port */ + sw_w32(0x03, priv->r->mac_port_ctrl(priv->cpu_port)); + + if (priv->family_id == RTL8380_FAMILY_ID) { + /* Set Speed, duplex, flow control + * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL + * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN + * | MEDIA_SEL + */ + sw_w32(0x6192F, priv->r->mac_force_mode_ctrl(priv->cpu_port)); + /* allow CRC errors on CPU-port */ + sw_w32_mask(0, 0x8, priv->r->mac_port_ctrl(priv->cpu_port)); + } else { + /* Force CPU port link up */ + sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl(priv->cpu_port)); + } + + /* Disable and clear interrupts */ + sw_w32(0x00000000, priv->r->dma_if_intr_msk); + sw_w32(0xffffffff, priv->r->dma_if_intr_sts); +} + +static void rtl838x_hw_ring_setup(struct rtl838x_eth_priv *priv) +{ + int i; + struct ring_b *ring = priv->membase; + + for (i = 0; i < RXRINGS; i++) + sw_w32(CPHYSADDR(&ring->rx_r[i]), priv->r->dma_rx_base(i)); + + for (i = 0; i < TXRINGS; i++) + sw_w32(CPHYSADDR(&ring->tx_r[i]), priv->r->dma_tx_base(i)); +} + +static void rtl838x_hw_en_rxtx(struct rtl838x_eth_priv *priv) +{ + u32 v; + + pr_info("%s\n", __func__); + /* Disable Head of Line features for all RX rings */ + sw_w32(0xffffffff, priv->r->dma_if_rx_ring_size(0)); + + /* Truncate RX buffer to 0x640 (1600) bytes, pad TX */ + sw_w32(0x06400020, priv->r->dma_if_ctrl); + + /* Enable RX done, RX overflow and TX done interrupts */ + sw_w32(0xfffff, priv->r->dma_if_intr_msk); + + /* Enable traffic, engine expects empty FCS field */ + sw_w32_mask(0, RX_EN | TX_EN, priv->r->dma_if_ctrl); + + /* Make sure to flood all traffic to CPU_PORT */ + if (priv->family_id == RTL8390_FAMILY_ID) { + /* CPU port joins Lookup Miss Flooding Portmask */ + /* Table access: CMD: read, table = 2 */ + /* Sets MC_PMSK table port bit for port 52 to 1 */ + sw_w32(0x28000, RTL839X_TBL_ACCESS_L2_CTRL); + do { } while (sw_r32(RTL839X_TBL_ACCESS_L2_CTRL) & (1 << 17)); + v = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(0)); + sw_w32(v | 0x80000000, RTL839X_TBL_ACCESS_L2_DATA(0)); + sw_w32(0x38000, RTL839X_TBL_ACCESS_L2_CTRL); + do { } while (sw_r32(RTL839X_TBL_ACCESS_L2_CTRL) & (1 << 17)); + } +} + +static void rtl838x_setup_ring_buffer(struct ring_b *ring) +{ + int i, j; + + struct p_hdr *h; + + for (i = 0; i < RXRINGS; i++) { + for (j = 0; j < RXRINGLEN; j++) { + h = &ring->rx_header[i][j]; + h->buf = (u8 *)CPHYSADDR(ring->rx_space + i * j * RING_BUFFER); + h->reserved = 0; + h->size = RING_BUFFER; + h->offset = 0; + h->len = 0; + /* All rings owned by switch, last one wraps */ + ring->rx_r[i][j] = CPHYSADDR(h) | 1 | (j == (RXRINGLEN - 1) ? WRAP : 0); + } + ring->c_rx[i] = 0; + } + + for (i = 0; i < TXRINGS; i++) { + for (j = 0; j < TXRINGLEN; j++) { + h = &ring->tx_header[i][j]; + h->buf = (u8 *)CPHYSADDR(ring->tx_space + i * j * RING_BUFFER); + h->reserved = 0; + h->size = RING_BUFFER; + h->offset = 0; + h->len = 0; + ring->tx_r[i][j] = CPHYSADDR(&ring->tx_header[i][j]); + } + /* Last header is wrapping around */ + ring->tx_r[i][j-1] |= 2; + ring->c_tx[i] = 0; + } +} + +static int rtl838x_eth_open(struct net_device *ndev) +{ + unsigned long flags; + struct rtl838x_eth_priv *priv = netdev_priv(ndev); + struct ring_b *ring = priv->membase; + int err; + + pr_info("%s called %x, ring %x\n", __func__, (uint32_t)priv, (uint32_t)ring); + spin_lock_irqsave(&priv->lock, flags); + rtl838x_hw_reset(priv); + rtl838x_setup_ring_buffer(ring); + rtl838x_hw_ring_setup(priv); + err = request_irq(ndev->irq, rtl838x_net_irq, IRQF_SHARED, + ndev->name, ndev); + if (err) { + netdev_err(ndev, "%s: could not acquire interrupt: %d\n", + __func__, err); + return err; + } + phylink_start(priv->phylink); + + napi_enable(&priv->napi); + netif_start_queue(ndev); + + rtl838x_hw_en_rxtx(priv); + + spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +} + +static void rtl838x_hw_stop(struct rtl838x_eth_priv *priv) +{ + int i; + + /* Block all ports */ + if (priv->family_id == RTL8380_FAMILY_ID) { + sw_w32(0x03000000, RTL838X_TBL_ACCESS_DATA_0(0)); + sw_w32(0x00000000, RTL838X_TBL_ACCESS_DATA_0(1)); + sw_w32(1 << 15 | 2 << 12, RTL838X_TBL_ACCESS_CTRL_0); + } + + /* Flush L2 address cache */ + if (priv->family_id == RTL8380_FAMILY_ID) { + for (i = 0; i <= priv->cpu_port; i++) { + sw_w32(1 << 26 | 1 << 23 | i << 5, priv->r->l2_tbl_flush_ctrl); + do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & (1 << 26)); + } + } else { + for (i = 0; i <= priv->cpu_port; i++) { + sw_w32(1 << 28 | 1 << 25 | i << 5, priv->r->l2_tbl_flush_ctrl); + do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & (1 << 28)); + } + } + + /* CPU-Port: Link down BUG: Works only for RTL838x */ + sw_w32(0x6192D, priv->r->mac_force_mode_ctrl(priv->cpu_port)); + mdelay(100); + + /* Disable traffic */ + sw_w32_mask(RX_EN | TX_EN, 0, priv->r->dma_if_ctrl); + mdelay(200); + + /* Disable all TX/RX interrupts */ + sw_w32(0x00000000, priv->r->dma_if_intr_msk); + sw_w32(0x000fffff, priv->r->dma_if_intr_sts); + sw_w32(0x00000000, priv->r->dma_if_ctrl); + mdelay(200); +} + +static int rtl838x_eth_stop(struct net_device *ndev) +{ + unsigned long flags; + struct rtl838x_eth_priv *priv = netdev_priv(ndev); + + pr_info("in %s\n", __func__); + + spin_lock_irqsave(&priv->lock, flags); + phylink_stop(priv->phylink); + rtl838x_hw_stop(priv); + free_irq(ndev->irq, ndev); + napi_disable(&priv->napi); + netif_stop_queue(ndev); + spin_unlock_irqrestore(&priv->lock, flags); + return 0; +} + +static void rtl838x_eth_set_multicast_list(struct net_device *dev) +{ + +} + +static void rtl838x_eth_tx_timeout(struct net_device *ndev) +{ + unsigned long flags; + struct rtl838x_eth_priv *priv = netdev_priv(ndev); + + pr_info("in %s\n", __func__); + spin_lock_irqsave(&priv->lock, flags); + rtl838x_hw_stop(priv); + rtl838x_hw_ring_setup(priv); + rtl838x_hw_en_rxtx(priv); + netif_trans_update(ndev); + netif_start_queue(ndev); + spin_unlock_irqrestore(&priv->lock, flags); +} + +static int rtl838x_eth_tx(struct sk_buff *skb, struct net_device *dev) +{ + int len, i; + struct rtl838x_eth_priv *priv = netdev_priv(dev); + struct ring_b *ring = priv->membase; + uint32_t val; + int ret; + unsigned long flags; + struct p_hdr *h; + int dest_port = -1; + + spin_lock_irqsave(&priv->lock, flags); + len = skb->len; + + /* Check for DSA tagging at the end of the buffer */ + if (netdev_uses_dsa(dev) && skb->data[len-4] == 0x80 && skb->data[len-3] > 0 + && skb->data[len-3] < 28 && skb->data[len-2] == 0x10 + && skb->data[len-1] == 0x00) { + /* Reuse tag space for CRC */ + dest_port = skb->data[len-3]; + len -= 4; + } + if (len < ETH_ZLEN) + len = ETH_ZLEN; + + /* ASIC expects that packet includes CRC, so we extend by 4 bytes */ + len += 4; + + if (skb_padto(skb, len)) { + ret = NETDEV_TX_OK; + goto txdone; + } + + /* We can send this packet if CPU owns the descriptor */ + if (!(ring->tx_r[0][ring->c_tx[0]] & 0x1)) { + /* Set descriptor for tx */ + h = &ring->tx_header[0][ring->c_tx[0]]; + + h->buf = (u8 *)CPHYSADDR(ring->tx_space); + h->size = len; + h->len = len; + + /* Create cpu_tag */ + if (dest_port > 0) { + h->cpu_tag[0] = 0x0400; + h->cpu_tag[1] = 0x0200; + h->cpu_tag[2] = 0x0000; + h->cpu_tag[3] = (1 << dest_port) >> 16; + h->cpu_tag[4] = (1 << dest_port) & 0xffff; + } else { + h->cpu_tag[0] = 0; + h->cpu_tag[1] = 0; + h->cpu_tag[2] = 0; + h->cpu_tag[3] = 0; + h->cpu_tag[4] = 0; + } + + /* Copy packet data to tx buffer */ + memcpy((void *)KSEG1ADDR(h->buf), skb->data, len); + /* Make sure packet data is visible to ASIC */ + mb(); + + /* Hand over to switch */ + ring->tx_r[0][ring->c_tx[0]] = ring->tx_r[0][ring->c_tx[0]] | 0x1; + + /* BUG: before tx fetch, need to make sure right data is accessed */ + for (i = 0; i < 10; i++) { + val = sw_r32(priv->r->dma_if_ctrl); + if ((val & 0xc) == 0xc) + break; + } + + /* Tell switch to send data */ + sw_w32_mask(0, TX_DO, priv->r->dma_if_ctrl); + + dev->stats.tx_packets++; + dev->stats.tx_bytes += len; + dev_kfree_skb(skb); + ring->c_tx[0] = (ring->c_tx[0] + 1) % TXRINGLEN; + ret = NETDEV_TX_OK; + } else { + dev_warn(&priv->pdev->dev, "Data is owned by switch\n"); + ret = NETDEV_TX_BUSY; + } +txdone: + spin_unlock_irqrestore(&priv->lock, flags); + return ret; +} + +static int rtl838x_hw_receive(struct net_device *dev, int r, int budget) +{ + struct rtl838x_eth_priv *priv = netdev_priv(dev); + struct ring_b *ring = priv->membase; + struct sk_buff *skb; + unsigned long flags; + int i, len, work_done = 0; + u8 *data, *skb_data; + unsigned int val; + u32 *last; + struct p_hdr *h; + bool dsa = netdev_uses_dsa(dev); + + spin_lock_irqsave(&priv->lock, flags); + last = (u32 *)KSEG1ADDR(sw_r32(priv->r->dma_if_rx_cur(r))); + + if (&ring->rx_r[r][ring->c_rx[r]] == last) { + spin_unlock_irqrestore(&priv->lock, flags); + return 0; + } + do { + if ((ring->rx_r[r][ring->c_rx[r]] & 0x1)) { + netdev_warn(dev, "WARNING Ring contention: ring %x, last %x, current %x, cPTR %x, ISR %x\n", r, (uint32_t)last, + (u32) &ring->rx_r[r][ring->c_rx[r]], + ring->rx_r[r][ring->c_rx[r]], + sw_r32(priv->r->dma_if_intr_sts)); + break; + } + + h = &ring->rx_header[r][ring->c_rx[r]]; + data = (u8 *)KSEG1ADDR(h->buf); + len = h->len; + + if (!len) + break; + h->buf = (u8 *)CPHYSADDR(ring->rx_space + + r * ring->c_rx[r] * RING_BUFFER); + h->size = RING_BUFFER; + h->len = 0; + work_done++; + + len -= 4; /* strip the CRC */ + /* Add 4 bytes for cpu_tag */ + if (dsa) + len += 4; + + skb = alloc_skb(len + 4, GFP_KERNEL); + skb_reserve(skb, NET_IP_ALIGN); + + if (likely(skb)) { + /* BUG: Prevent ASIC bug */ + sw_w32(0xffffffff, priv->r->dma_if_rx_ring_size(0)); + for (i = 0; i < RXRINGS; i++) { + /* Update each ring cnt */ + val = sw_r32(priv->r->dma_if_rx_ring_cntr(i)); + sw_w32(val, priv->r->dma_if_rx_ring_cntr(i)); + } + + skb_data = skb_put(skb, len); + /* Make sure data is visible */ + mb(); + memcpy(skb->data, (u8 *)KSEG1ADDR(data), len); + /* Overwrite CRC with cpu_tag */ + if (dsa) { + skb->data[len-4] = 0x80; + skb->data[len-3] = h->cpu_tag[0] & 0x1f; + skb->data[len-2] = 0x10; + skb->data[len-1] = 0x00; + } + + skb->protocol = eth_type_trans(skb, dev); + dev->stats.rx_packets++; + dev->stats.rx_bytes += len; + + netif_receive_skb(skb); + } else { + if (net_ratelimit()) + dev_warn(&dev->dev, "low on memory - packet dropped\n"); + dev->stats.rx_dropped++; + } + ring->rx_r[r][ring->c_rx[r]] + = CPHYSADDR(h) | 0x1 | (ring->c_rx[r] == (RXRINGLEN-1) ? WRAP : 0x1); + ring->c_rx[r] = (ring->c_rx[r] + 1) % RXRINGLEN; + } while (&ring->rx_r[r][ring->c_rx[r]] != last && work_done < budget); + + spin_unlock_irqrestore(&priv->lock, flags); + return work_done; +} + +static int rtl838x_poll_rx(struct napi_struct *napi, int budget) +{ + struct rtl838x_eth_priv *priv = container_of(napi, struct rtl838x_eth_priv, napi); + int work_done = 0, r = 0; + + while (work_done < budget && r < RXRINGS) { + work_done += rtl838x_hw_receive(priv->netdev, r, budget - work_done); + r++; + } + + if (work_done < budget) { + napi_complete_done(napi, work_done); + /* Enable RX interrupt */ + sw_w32(0xfffff, priv->r->dma_if_intr_msk); + } + return work_done; +} + + +static void rtl838x_validate(struct phylink_config *config, + unsigned long *supported, + struct phylink_link_state *state) +{ + __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; + + pr_info("In %s\n", __func__); + + if (!phy_interface_mode_is_rgmii(state->interface) && + state->interface != PHY_INTERFACE_MODE_1000BASEX && + state->interface != PHY_INTERFACE_MODE_MII && + state->interface != PHY_INTERFACE_MODE_REVMII && + state->interface != PHY_INTERFACE_MODE_GMII && + state->interface != PHY_INTERFACE_MODE_QSGMII && + state->interface != PHY_INTERFACE_MODE_INTERNAL && + state->interface != PHY_INTERFACE_MODE_SGMII) { + bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); + pr_err("Unsupported interface: %d\n", state->interface); + return; + } + + /* Allow all the expected bits */ + phylink_set(mask, Autoneg); + phylink_set_port_modes(mask); + phylink_set(mask, Pause); + phylink_set(mask, Asym_Pause); + + /* With the exclusion of MII and Reverse MII, we support Gigabit, + * including Half duplex + */ + if (state->interface != PHY_INTERFACE_MODE_MII && + state->interface != PHY_INTERFACE_MODE_REVMII) { + phylink_set(mask, 1000baseT_Full); + phylink_set(mask, 1000baseT_Half); + } + + phylink_set(mask, 10baseT_Half); + phylink_set(mask, 10baseT_Full); + phylink_set(mask, 100baseT_Half); + phylink_set(mask, 100baseT_Full); + + bitmap_and(supported, supported, mask, + __ETHTOOL_LINK_MODE_MASK_NBITS); + bitmap_and(state->advertising, state->advertising, mask, + __ETHTOOL_LINK_MODE_MASK_NBITS); +} + + +static void rtl838x_mac_config(struct phylink_config *config, + unsigned int mode, + const struct phylink_link_state *state) +{ + /* This is only being called for the master device, + * i.e. the CPU-Port + */ + + pr_info("In %s, mode %x\n", __func__, mode); +} + +static void rtl838x_mac_an_restart(struct phylink_config *config) +{ + struct net_device *dev = container_of(config->dev, struct net_device, dev); + struct rtl838x_eth_priv *priv = netdev_priv(dev); + + pr_info("In %s\n", __func__); + /* Restart by disabling and re-enabling link */ + sw_w32(0x6192D, priv->r->mac_force_mode_ctrl(priv->cpu_port)); + mdelay(20); + sw_w32(0x6192F, priv->r->mac_force_mode_ctrl(priv->cpu_port)); +} + +static int rtl838x_mac_pcs_get_state(struct phylink_config *config, + struct phylink_link_state *state) +{ + u32 speed; + struct net_device *dev = container_of(config->dev, struct net_device, dev); + struct rtl838x_eth_priv *priv = netdev_priv(dev); + int port = priv->cpu_port; + + pr_info("In %s\n", __func__); + + state->link = priv->r->get_mac_link_sts(port) ? 1 : 0; + state->duplex = priv->r->get_mac_link_dup_sts(port) ? 1 : 0; + + speed = priv->r->get_mac_link_spd_sts(port); + switch (speed) { + case 0: + state->speed = SPEED_10; + break; + case 1: + state->speed = SPEED_100; + break; + state->speed = SPEED_1000; + break; + default: + state->speed = SPEED_UNKNOWN; + break; + } + + state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX); + if (priv->r->get_mac_rx_pause_sts(port)) + state->pause |= MLO_PAUSE_RX; + if (priv->r->get_mac_tx_pause_sts(port)) + state->pause |= MLO_PAUSE_TX; + + return 1; +} + +static void dump_mac_conf(struct rtl838x_eth_priv *priv) +{ + int p; + + for (p = 8; p < 16; p++) { + pr_debug("%d: %x, force %x\n", p, sw_r32(priv->r->mac_port_ctrl(p)), + sw_r32(priv->r->mac_force_mode_ctrl(p)) + ); + } + pr_debug("CPU: %x, force %x\n", sw_r32(priv->r->mac_port_ctrl(priv->cpu_port)), + sw_r32(priv->r->mac_force_mode_ctrl(priv->cpu_port)) + ); +} + +static void rtl838x_mac_link_down(struct phylink_config *config, + unsigned int mode, + phy_interface_t interface) +{ + struct net_device *dev = container_of(config->dev, struct net_device, dev); + struct rtl838x_eth_priv *priv = netdev_priv(dev); + + pr_info("In %s\n", __func__); + /* Stop TX/RX to port */ + sw_w32_mask(0x03, 0, priv->r->mac_port_ctrl(priv->cpu_port)); +} + +static void rtl838x_mac_link_up(struct phylink_config *config, unsigned int mode, + phy_interface_t interface, + struct phy_device *phy) +{ + struct net_device *dev = container_of(config->dev, struct net_device, dev); + struct rtl838x_eth_priv *priv = netdev_priv(dev); + + pr_info("In %s\n", __func__); + /* Restart TX/RX to port */ + sw_w32_mask(0, 0x03, priv->r->mac_port_ctrl(priv->cpu_port)); +} + +static void rtl838x_set_mac_hw(struct net_device *dev, u8 *mac) +{ + struct rtl838x_eth_priv *priv = netdev_priv(dev); + unsigned long flags; + + spin_lock_irqsave(&priv->lock, flags); + pr_info("In %s\n", __func__); + sw_w32((mac[0] << 8) | mac[1], priv->r->mac); + sw_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5], priv->r->mac + 4); + + if (priv->family_id == RTL8380_FAMILY_ID) { + /* 2 more registers, ALE/MAC block */ + sw_w32((mac[0] << 8) | mac[1], RTL838X_MAC_ALE); + sw_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5], + (RTL838X_MAC_ALE + 4)); + + sw_w32((mac[0] << 8) | mac[1], RTL838X_MAC2); + sw_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5], + RTL838X_MAC2 + 4); + } + spin_unlock_irqrestore(&priv->lock, flags); +} + +static int rtl838x_set_mac_address(struct net_device *dev, void *p) +{ + struct rtl838x_eth_priv *priv = netdev_priv(dev); + const struct sockaddr *addr = p; + u8 *mac = (u8 *) (addr->sa_data); + + if (!is_valid_ether_addr(addr->sa_data)) + return -EADDRNOTAVAIL; + + memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); + rtl838x_set_mac_hw(dev, mac); + + pr_info("Using MAC %08x%08x\n", sw_r32(priv->r->mac), sw_r32(priv->r->mac + 4)); + return 0; +} + +static int rtl8390_init_mac(struct rtl838x_eth_priv *priv) +{ + pr_info("Configuring RTL8390 MAC\n"); + // from mac_config_init + sw_w32(0x80, RTL839X_MAC_EFUSE_CTRL); + sw_w32(0x4, RTL839X_RST_GLB_CTRL); + sw_w32(0x3c324f40, RTL839X_MAC_GLB_CTRL); + /* Unlimited egress rate */ + sw_w32(0x1297b961, RTL839X_SCHED_LB_TICK_TKN_CTRL); + + return 0; +} + +static int rtl8380_init_mac(struct rtl838x_eth_priv *priv) +{ + int i; + + if (priv->family_id == 0x8390) + return rtl8390_init_mac(priv); + + if (priv->family_id != 0x8380) + return 0; + + pr_info("%s\n", __func__); + /* fix timer for EEE */ + sw_w32(0x5001411, RTL838X_EEE_TX_TIMER_GIGA_CTRL); + sw_w32(0x5001417, RTL838X_EEE_TX_TIMER_GELITE_CTRL); + + /* Init VLAN */ + if (priv->id == 0x8382) { + for (i = 0; i <= 28; i++) + sw_w32(0, 0xd57c + i * 0x80); + } + if (priv->id == 0x8380) { + for (i = 8; i <= 28; i++) + sw_w32(0, 0xd57c + i * 0x80); + } + return 0; +} + +static int rtl838x_get_link_ksettings(struct net_device *ndev, + struct ethtool_link_ksettings *cmd) +{ + struct rtl838x_eth_priv *priv = netdev_priv(ndev); + + pr_info("%s called\n", __func__); + return phylink_ethtool_ksettings_get(priv->phylink, cmd); +} + +static int rtl838x_set_link_ksettings(struct net_device *ndev, + const struct ethtool_link_ksettings *cmd) +{ + struct rtl838x_eth_priv *priv = netdev_priv(ndev); + + pr_info("%s called\n", __func__); + return phylink_ethtool_ksettings_set(priv->phylink, cmd); +} + + +static int rtl838x_mdio_read(struct mii_bus *bus, int mii_id, int regnum) +{ + u32 val; + u32 offset = 0; + int err; + struct rtl838x_eth_priv *priv = bus->priv; + + if (mii_id >= 24 && mii_id <= 27 && priv->id == 0x8380) { + if (mii_id == 26) + offset = 0x100; + val = sw_r32(MAPLE_SDS4_FIB_REG0r + offset + (regnum << 2)) & 0xffff; + return val; + } + err = rtl838x_read_phy(mii_id, 0, regnum, &val); + if (err) + return err; + return val; +} + +static int rtl839x_mdio_read(struct mii_bus *bus, int mii_id, int regnum) +{ + u32 val; + int err; + + err = rtl839x_read_phy(mii_id, 0, regnum, &val); + if (err) + return err; + return val; +} + +static int rtl838x_mdio_write(struct mii_bus *bus, int mii_id, + int regnum, u16 value) +{ + u32 offset = 0; + struct rtl838x_eth_priv *priv = bus->priv; + + if (mii_id >= 24 && mii_id <= 27 && priv->id == 0x8380) { + if (mii_id == 26) + offset = 0x100; + sw_w32(value, MAPLE_SDS4_FIB_REG0r + offset + (regnum << 2)); + return 0; + } + return rtl838x_write_phy(mii_id, 0, regnum, value); +} + +static int rtl839x_mdio_write(struct mii_bus *bus, int mii_id, + int regnum, u16 value) +{ + return rtl839x_write_phy(mii_id, 0, regnum, value); +} + +static int rtl838x_mdio_reset(struct mii_bus *bus) +{ + pr_info("%s called\n", __func__); + /* Disable MAC polling the PHY so that we can start configuration */ + sw_w32(0x00000000, RTL838X_SMI_POLL_CTRL); + + /* Enable PHY control via SoC */ + sw_w32_mask(0, 1 << 15, RTL838X_SMI_GLB_CTRL); + + return 0; +} + +static int rtl839x_mdio_reset(struct mii_bus *bus) +{ + pr_info("%s called\n", __func__); + /* Disable MAC polling the PHY so that we can start configuration */ + sw_w32(0x00000000, RTL839X_SMI_PORT_POLLING_CTRL); + sw_w32(0x00000000, RTL839X_SMI_PORT_POLLING_CTRL + 4); + /* Disable PHY polling via SoC */ + sw_w32_mask(1 << 7, 0, RTL839X_SMI_GLB_CTRL); + + return 0; +} + + +static int rtl838x_mdio_init(struct rtl838x_eth_priv *priv) +{ + struct device_node *mii_np; + int ret; + + pr_info("%s called\n", __func__); + mii_np = of_get_child_by_name(priv->pdev->dev.of_node, "mdio-bus"); + + if (!mii_np) { + dev_err(&priv->pdev->dev, "no %s child node found", "mdio-bus"); + return -ENODEV; + } + + if (!of_device_is_available(mii_np)) { + ret = -ENODEV; + goto err_put_node; + } + + priv->mii_bus = devm_mdiobus_alloc(&priv->pdev->dev); + if (!priv->mii_bus) { + ret = -ENOMEM; + goto err_put_node; + } + + if (priv->family_id == RTL8380_FAMILY_ID) { + priv->mii_bus->name = "rtl838x-eth-mdio"; + priv->mii_bus->read = rtl838x_mdio_read; + priv->mii_bus->write = rtl838x_mdio_write; + priv->mii_bus->reset = rtl838x_mdio_reset; + } else { + priv->mii_bus->name = "rtl839x-eth-mdio"; + priv->mii_bus->read = rtl839x_mdio_read; + priv->mii_bus->write = rtl839x_mdio_write; + priv->mii_bus->reset = rtl839x_mdio_reset; + } + priv->mii_bus->priv = priv; + priv->mii_bus->parent = &priv->pdev->dev; + + snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np); + ret = of_mdiobus_register(priv->mii_bus, mii_np); + +err_put_node: + of_node_put(mii_np); + return ret; +} + +static int rtl838x_mdio_remove(struct rtl838x_eth_priv *priv) +{ + pr_info("%s called\n", __func__); + if (!priv->mii_bus) + return 0; + + mdiobus_unregister(priv->mii_bus); + mdiobus_free(priv->mii_bus); + + return 0; +} + +static const struct net_device_ops rtl838x_eth_netdev_ops = { + .ndo_open = rtl838x_eth_open, + .ndo_stop = rtl838x_eth_stop, + .ndo_start_xmit = rtl838x_eth_tx, + .ndo_set_mac_address = rtl838x_set_mac_address, + .ndo_validate_addr = eth_validate_addr, + .ndo_set_rx_mode = rtl838x_eth_set_multicast_list, + .ndo_tx_timeout = rtl838x_eth_tx_timeout, +}; + +static const struct phylink_mac_ops rtl838x_phylink_ops = { + .validate = rtl838x_validate, + .mac_link_state = rtl838x_mac_pcs_get_state, + .mac_an_restart = rtl838x_mac_an_restart, + .mac_config = rtl838x_mac_config, + .mac_link_down = rtl838x_mac_link_down, + .mac_link_up = rtl838x_mac_link_up, +}; + +static const struct ethtool_ops rtl838x_ethtool_ops = { + .get_link_ksettings = rtl838x_get_link_ksettings, + .set_link_ksettings = rtl838x_set_link_ksettings, +}; + +static int __init rtl838x_eth_probe(struct platform_device *pdev) +{ + struct net_device *dev; + struct device_node *dn = pdev->dev.of_node; + struct rtl838x_eth_priv *priv; + struct resource *res, *mem; + const void *mac; + phy_interface_t phy_mode; + struct phylink *phylink; + int err = 0; + + pr_info("Probing RTL838X eth device pdev: %x, dev: %x\n", + (u32)pdev, (u32)(&(pdev->dev))); + + if (!dn) { + dev_err(&pdev->dev, "No DT found\n"); + return -EINVAL; + } + + dev = alloc_etherdev(sizeof(struct rtl838x_eth_priv)); + if (!dev) { + err = -ENOMEM; + goto err_free; + } + SET_NETDEV_DEV(dev, &pdev->dev); + priv = netdev_priv(dev); + + /* obtain buffer memory space */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res) { + mem = devm_request_mem_region(&pdev->dev, res->start, + resource_size(res), res->name); + if (!mem) { + dev_err(&pdev->dev, "cannot request memory space\n"); + err = -ENXIO; + goto err_free; + } + + dev->mem_start = mem->start; + dev->mem_end = mem->end; + } else { + dev_err(&pdev->dev, "cannot request IO resource\n"); + err = -ENXIO; + goto err_free; + } + + /* Allocate buffer memory */ + priv->membase = dmam_alloc_coherent(&pdev->dev, + sizeof(struct ring_b), (void *)&dev->mem_start, + GFP_KERNEL); + if (!priv->membase) { + dev_err(&pdev->dev, "cannot allocate DMA buffer\n"); + err = -ENOMEM; + goto err_free; + } + + spin_lock_init(&priv->lock); + + /* obtain device IRQ number */ + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!res) { + dev_err(&pdev->dev, "cannot obtain IRQ, using default 24\n"); + dev->irq = 24; + } else { + dev->irq = res->start; + } + dev->ethtool_ops = &rtl838x_ethtool_ops; + + priv->id = soc_info.id; + priv->family_id = soc_info.family; + if (priv->id) { + pr_info("Found SoC ID: %4x: %s, family %x\n", + priv->id, soc_info.name, priv->family_id); + } else { + pr_err("Unknown chip id (%04x)\n", priv->id); + return -ENODEV; + } + + if (priv->family_id == 0x8390) { + priv->cpu_port = RTL839X_CPU_PORT; + priv->r = &rtl839x_reg; + } else { + priv->cpu_port = RTL838X_CPU_PORT; + priv->r = &rtl838x_reg; + } + + rtl8380_init_mac(priv); + + /* try to get mac address in the following order: + * 1) from device tree data + * 2) from internal registers set by bootloader + */ + mac = of_get_mac_address(pdev->dev.of_node); + if (!IS_ERR(mac)) { + memcpy(dev->dev_addr, mac, ETH_ALEN); + rtl838x_set_mac_hw(dev, (u8 *)mac); + } else { + dev->dev_addr[0] = (sw_r32(priv->r->mac) >> 8) & 0xff; + dev->dev_addr[1] = sw_r32(priv->r->mac) & 0xff; + dev->dev_addr[2] = (sw_r32(priv->r->mac + 4) >> 24) & 0xff; + dev->dev_addr[3] = (sw_r32(priv->r->mac + 4) >> 16) & 0xff; + dev->dev_addr[4] = (sw_r32(priv->r->mac + 4) >> 8) & 0xff; + dev->dev_addr[5] = sw_r32(priv->r->mac + 4) & 0xff; + } + /* if the address is invalid, use a random value */ + if (!is_valid_ether_addr(dev->dev_addr)) { + struct sockaddr sa = { AF_UNSPEC }; + + netdev_warn(dev, "Invalid MAC address, using random\n"); + eth_hw_addr_random(dev); + memcpy(sa.sa_data, dev->dev_addr, ETH_ALEN); + if (rtl838x_set_mac_address(dev, &sa)) + netdev_warn(dev, "Failed to set MAC address.\n"); + } + pr_info("Using MAC %08x%08x\n", sw_r32(priv->r->mac), + sw_r32(priv->r->mac + 4)); + strcpy(dev->name, "eth%d"); + dev->netdev_ops = &rtl838x_eth_netdev_ops; + priv->pdev = pdev; + priv->netdev = dev; + + err = rtl838x_mdio_init(priv); + if (err) + goto err_free; + + err = register_netdev(dev); + if (err) + goto err_free; + + netif_napi_add(dev, &priv->napi, rtl838x_poll_rx, 64); + platform_set_drvdata(pdev, dev); + + phy_mode = of_get_phy_mode(dn); + if (phy_mode < 0) { + dev_err(&pdev->dev, "incorrect phy-mode\n"); + err = -EINVAL; + goto err_free; + } + priv->phylink_config.dev = &dev->dev; + priv->phylink_config.type = PHYLINK_NETDEV; + + phylink = phylink_create(&priv->phylink_config, pdev->dev.fwnode, + phy_mode, &rtl838x_phylink_ops); + if (IS_ERR(phylink)) { + err = PTR_ERR(phylink); + goto err_free; + } + priv->phylink = phylink; + return 0; + +err_free: + pr_err("Error setting up netdev, freeing it again.\n"); + free_netdev(dev); + return err; +} + +static int rtl838x_eth_remove(struct platform_device *pdev) +{ + struct net_device *dev = platform_get_drvdata(pdev); + struct rtl838x_eth_priv *priv = netdev_priv(dev); + + if (dev) { + pr_info("Removing platform driver for rtl838x-eth\n"); + rtl838x_mdio_remove(priv); + rtl838x_hw_stop(priv); + netif_stop_queue(dev); + netif_napi_del(&priv->napi); + unregister_netdev(dev); + free_netdev(dev); + } + return 0; +} + +static const struct of_device_id rtl838x_eth_of_ids[] = { + { .compatible = "realtek,rtl838x-eth"}, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, rtl838x_eth_of_ids); + +static struct platform_driver rtl838x_eth_driver = { + .probe = rtl838x_eth_probe, + .remove = rtl838x_eth_remove, + .driver = { + .name = "rtl838x-eth", + .pm = NULL, + .of_match_table = rtl838x_eth_of_ids, + }, +}; + +module_platform_driver(rtl838x_eth_driver); + +MODULE_AUTHOR("B. Koblitz"); +MODULE_DESCRIPTION("RTL838X SoC Ethernet Driver"); +MODULE_LICENSE("GPL"); diff --git a/target/linux/rtl838x/files-5.4/drivers/net/ethernet/rtl838x_eth.h b/target/linux/rtl838x/files-5.4/drivers/net/ethernet/rtl838x_eth.h new file mode 100644 index 0000000000..53ab7e5eb2 --- /dev/null +++ b/target/linux/rtl838x/files-5.4/drivers/net/ethernet/rtl838x_eth.h @@ -0,0 +1,261 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _RTL838X_ETH_H +#define _RTL838X_ETH_H + +/* + * Register definition + */ + +#define RTL838X_CPU_PORT 28 +#define RTL839X_CPU_PORT 52 + +#define RTL838X_MAC_PORT_CTRL (0xd560) +#define RTL839X_MAC_PORT_CTRL (0x8004) +#define RTL838X_DMA_IF_INTR_STS (0x9f54) +#define RTL839X_DMA_IF_INTR_STS (0x7868) +#define RTL838X_DMA_IF_INTR_MSK (0x9f50) +#define RTL839X_DMA_IF_INTR_MSK (0x7864) +#define RTL838X_DMA_IF_CTRL (0x9f58) +#define RTL839X_DMA_IF_CTRL (0x786c) +#define RTL838X_RST_GLB_CTRL_0 (0x003c) +#define RTL838X_MAC_FORCE_MODE_CTRL (0xa104) +#define RTL839X_MAC_FORCE_MODE_CTRL (0x02bc) + +/* MAC address settings */ +#define RTL838X_MAC (0xa9ec) +#define RTL839X_MAC (0x02b4) +#define RTL838X_MAC_ALE (0x6b04) +#define RTL838X_MAC2 (0xa320) + +#define RTL838X_DMA_RX_BASE (0x9f00) +#define RTL839X_DMA_RX_BASE (0x780c) +#define RTL838X_DMA_TX_BASE (0x9f40) +#define RTL839X_DMA_TX_BASE (0x784c) +#define RTL838X_DMA_IF_RX_RING_SIZE (0xB7E4) +#define RTL839X_DMA_IF_RX_RING_SIZE (0x6038) +#define RTL838X_DMA_IF_RX_RING_CNTR (0xB7E8) +#define RTL839X_DMA_IF_RX_RING_CNTR (0x603c) +#define RTL838X_DMA_IF_RX_CUR (0x9F20) +#define RTL839X_DMA_IF_RX_CUR (0x782c) + +#define RTL838X_DMY_REG31 (0x3b28) +#define RTL838X_SDS_MODE_SEL (0x0028) +#define RTL838X_SDS_CFG_REG (0x0034) +#define RTL838X_INT_MODE_CTRL (0x005c) +#define RTL838X_CHIP_INFO (0x00d8) +#define RTL838X_SDS4_REG28 (0xef80) +#define RTL838X_SDS4_DUMMY0 (0xef8c) +#define RTL838X_SDS5_EXT_REG6 (0xf18c) +#define RTL838X_PORT_ISO_CTRL(port) (0x4100 + ((port) << 2)) +#define RTL838X_STAT_PORT_STD_MIB(port) (0x1200 + (((port) << 8))) +#define RTL838X_STAT_RST (0x3100) +#define RTL838X_STAT_CTRL (0x3108) + +/* Registers of the internal Serdes of the 8380 */ +#define MAPLE_SDS4_REG0r RTL838X_SDS4_REG28 +#define MAPLE_SDS5_REG0r (RTL838X_SDS4_REG28 + 0x100) +#define MAPLE_SDS4_REG3r RTL838X_SDS4_DUMMY0 +#define MAPLE_SDS5_REG3r (RTL838X_SDS4_REG28 + 0x100) +#define MAPLE_SDS4_FIB_REG0r (RTL838X_SDS4_REG28 + 0x880) +#define MAPLE_SDS5_FIB_REG0r (RTL838X_SDS4_REG28 + 0x980) + +/* VLAN registers */ +#define RTL838X_VLAN_PROFILE(idx) (0x3A88 + ((idx) << 2)) +#define RTL838X_VLAN_PORT_EGR_FLTR (0x3A84) +#define RTL838X_VLAN_PORT_PB_VLAN(port) (0x3C00 + ((port) << 2)) +#define RTL838X_VLAN_PORT_IGR_FLTR_0 (0x3A7C) +#define RTL838X_VLAN_PORT_IGR_FLTR_1 (0x3A7C + 4) +#define RTL838X_TBL_ACCESS_CTRL_0 (0x6914) +#define RTL838X_TBL_ACCESS_DATA_0(idx) (0x6918 + ((idx) << 2)) +#define RTL838X_TBL_ACCESS_CTRL_1 (0xA4C8) +#define RTL838X_TBL_ACCESS_DATA_1(idx) (0xA4CC + ((idx) << 2)) +#define RTL839X_TBL_ACCESS_L2_CTRL (0x1180) +#define RTL839X_TBL_ACCESS_L2_DATA(idx) (0x1184 + ((idx) << 2)) +/* MAC handling */ +#define RTL838X_MAC_LINK_STS (0xa188) +#define RTL839X_MAC_LINK_STS (0x0390) +#define RTL838X_MAC_LINK_SPD_STS (0xa190) +#define RTL839X_MAC_LINK_SPD_STS (0x03a0) +#define RTL838X_MAC_LINK_DUP_STS (0xa19c) +#define RTL839X_MAC_LINK_DUP_STS (0x03b0) +// TODO: RTL8390_MAC_LINK_MEDIA_STS_ADDR ??? +#define RTL838X_MAC_TX_PAUSE_STS (0xa1a0) +#define RTL839X_MAC_TX_PAUSE_STS (0x03b8) +#define RTL838X_MAC_RX_PAUSE_STS (0xa1a4) +#define RTL839X_MAC_RX_PAUSE_STS (0x03c0) +#define RTL838X_EEE_TX_TIMER_GIGA_CTRL (0xaa04) +#define RTL838X_EEE_TX_TIMER_GELITE_CTRL (0xaa08) +#define RTL839X_MAC_GLB_CTRL (0x02a8) +#define RTL839X_SCHED_LB_TICK_TKN_CTRL (0x60f8) + +#define RTL838X_L2_TBL_FLUSH_CTRL (0x3370) +#define RTL839X_L2_TBL_FLUSH_CTRL (0x3ba0) + +/* MAC link state bits */ +#define FORCE_EN (1 << 0) +#define FORCE_LINK_EN (1 << 1) +#define NWAY_EN (1 << 2) +#define DUPLX_MODE (1 << 3) +#define TX_PAUSE_EN (1 << 6) +#define RX_PAUSE_EN (1 << 7) + +inline int rtl838x_mac_port_ctrl(int p) +{ + return RTL838X_MAC_PORT_CTRL + (p << 7); +} + +inline int rtl839x_mac_port_ctrl(int p) +{ + return RTL839X_MAC_PORT_CTRL + (p << 7); +} + +static inline int rtl838x_mac_force_mode_ctrl(int p) +{ + return RTL838X_MAC_FORCE_MODE_CTRL + (p << 2); +} + +static inline int rtl839x_mac_force_mode_ctrl(int p) +{ + return RTL839X_MAC_FORCE_MODE_CTRL + (p << 2); +} + +inline int rtl838x_dma_rx_base(int i) +{ + return RTL838X_DMA_RX_BASE + (i << 2); +} + +inline int rtl839x_dma_rx_base(int i) +{ + return RTL839X_DMA_RX_BASE + (i << 2); +} + +inline int rtl838x_dma_tx_base(int i) +{ + return RTL838X_DMA_TX_BASE + (i << 2); +} + +inline int rtl839x_dma_tx_base(int i) +{ + return RTL839X_DMA_TX_BASE + (i << 2); +} + +inline int rtl838x_dma_if_rx_ring_size(int i) +{ + return RTL838X_DMA_IF_RX_RING_SIZE + ((i >> 3) << 2); +} + +inline int rtl839x_dma_if_rx_ring_size(int i) +{ + return RTL839X_DMA_IF_RX_RING_SIZE + ((i >> 3) << 2); +} + +inline int rtl838x_dma_if_rx_ring_cntr(int i) +{ + return RTL838X_DMA_IF_RX_RING_CNTR + ((i >> 3) << 2); +} + +inline int rtl839x_dma_if_rx_ring_cntr(int i) +{ + return RTL839X_DMA_IF_RX_RING_CNTR + ((i >> 3) << 2); +} + + +inline int rtl838x_dma_if_rx_cur(int i) +{ + return RTL838X_DMA_IF_RX_CUR + (i << 2); +} + +inline int rtl839x_dma_if_rx_cur(int i) +{ + return RTL839X_DMA_IF_RX_CUR + (i << 2); +} + +inline u32 rtl838x_get_mac_link_sts(int port) +{ + return (sw_r32(RTL838X_MAC_LINK_STS) & (1 << port)); +} + +inline u32 rtl839x_get_mac_link_sts(int p) +{ + return (sw_r32(RTL839X_MAC_LINK_STS + ((p >> 5) << 2)) & (1 << p)); +} + +inline u32 rtl838x_get_mac_link_dup_sts(int port) +{ + return (sw_r32(RTL838X_MAC_LINK_DUP_STS) & (1 << port)); +} + +inline u32 rtl839x_get_mac_link_dup_sts(int p) +{ + return (sw_r32(RTL839X_MAC_LINK_DUP_STS + ((p >> 5) << 2)) & (1 << p)); +} + +inline u32 rtl838x_get_mac_link_spd_sts(int port) +{ + int r = RTL838X_MAC_LINK_SPD_STS + ((port >> 4) << 2); + u32 speed = sw_r32(r); + + speed >>= (port % 16) << 1; + return (speed & 0x3); +} + +inline u32 rtl839x_get_mac_link_spd_sts(int port) +{ + int r = RTL839X_MAC_LINK_SPD_STS + ((port >> 4) << 2); + u32 speed = sw_r32(r); + + speed >>= (port % 16) << 1; + return (speed & 0x3); +} + +inline u32 rtl838x_get_mac_rx_pause_sts(int port) +{ + return (sw_r32(RTL838X_MAC_RX_PAUSE_STS) & (1 << port)); +} + +inline u32 rtl839x_get_mac_rx_pause_sts(int p) +{ + return (sw_r32(RTL839X_MAC_RX_PAUSE_STS + ((p >> 5) << 2)) & (1 << p)); +} + +inline u32 rtl838x_get_mac_tx_pause_sts(int port) +{ + return (sw_r32(RTL838X_MAC_TX_PAUSE_STS) & (1 << port)); +} + +inline u32 rtl839x_get_mac_tx_pause_sts(int p) +{ + return (sw_r32(RTL839X_MAC_TX_PAUSE_STS + ((p >> 5) << 2)) & (1 << p)); +} + + +struct rtl838x_reg { + int (*mac_port_ctrl)(int port); + int dma_if_intr_sts; + int dma_if_intr_msk; + int dma_if_ctrl; + int (*mac_force_mode_ctrl)(int port); + int (*dma_rx_base)(int ring); + int (*dma_tx_base)(int ring); + int (*dma_if_rx_ring_size)(int ring); + int (*dma_if_rx_ring_cntr)(int ring); + int (*dma_if_rx_cur)(int ring); + int rst_glb_ctrl; + u32 (*get_mac_link_sts)(int port); + u32 (*get_mac_link_dup_sts)(int port); + u32 (*get_mac_link_spd_sts)(int port); + u32 (*get_mac_rx_pause_sts)(int port); + u32 (*get_mac_tx_pause_sts)(int port); + int mac; + int l2_tbl_flush_ctrl; +}; + +int rtl838x_write_phy(u32 port, u32 page, u32 reg, u32 val); +int rtl838x_read_phy(u32 port, u32 page, u32 reg, u32 *val); +int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val); +int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val); + +extern int rtl8380_sds_power(int mac, int val); + +#endif /* _RTL838X_ETH_H */ diff --git a/target/linux/rtl838x/image/Makefile b/target/linux/rtl838x/image/Makefile new file mode 100644 index 0000000000..eef1fe0a33 --- /dev/null +++ b/target/linux/rtl838x/image/Makefile @@ -0,0 +1,44 @@ +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/image.mk + +KERNEL_LOADADDR = 0x80000000 +KERNEL_ENTRY = 0x80000400 + +define Build/custom-uimage + mkimage -A $(LINUX_KARCH) \ + -O linux -T kernel \ + -C gzip -a $(KERNEL_LOADADDR) $(if $(UIMAGE_MAGIC),-M $(UIMAGE_MAGIC),) \ + -e $(if $(KERNEL_ENTRY),$(KERNEL_ENTRY),$(KERNEL_LOADADDR)) \ + -n '$(1)' -d $@ $@.new + mv $@.new $@ +endef + + +define Device/Default + PROFILES = Default + KERNEL := kernel-bin | append-dtb | gzip | uImage gzip + KERNEL_INITRAMFS := kernel-bin | append-dtb | gzip | uImage gzip + DEVICE_DTS_DIR := ../dts + DEVICE_DTS = $$(SOC)_$(1) + SUPPORTED_DEVICES := $(subst _,$(comma),$(1)) + IMAGES := sysupgrade.bin + IMAGE/sysupgrade.bin := append-kernel | pad-to 64k | append-rootfs | pad-rootfs | \ + append-metadata | check-size +endef + +define Device/allnet_all-sg8208m + SOC := rtl8382 + IMAGE_SIZE := 7168k + DEVICE_VENDOR := ALLNET + DEVICE_MODEL := ALL-SG8208M + UIMAGE_MAGIC := 0x00000006 + KERNEL := kernel-bin | append-dtb | gzip | custom-uimage 2.2.2.0 + KERNEL_INITRAMFS := kernel-bin | append-dtb | gzip | custom-uimage 2.2.2.0 + DEVICE_PACKAGES := ip-full ip-bridge kmod-gpio-button-hotplug tc +endef +TARGET_DEVICES += allnet_all-sg8208m + +$(eval $(call BuildImage)) diff --git a/target/linux/rtl838x/patches-5.4/300-mips-add-rtl838x-platform.patch b/target/linux/rtl838x/patches-5.4/300-mips-add-rtl838x-platform.patch new file mode 100644 index 0000000000..34fb959a50 --- /dev/null +++ b/target/linux/rtl838x/patches-5.4/300-mips-add-rtl838x-platform.patch @@ -0,0 +1,42 @@ +--- a/arch/mips/Kbuild.platforms ++++ b/arch/mips/Kbuild.platforms +@@ -27,6 +27,7 @@ platforms += pistachio + platforms += pmcs-msp71xx + platforms += pnx833x + platforms += ralink ++platforms += rtl838x + platforms += rb532 + platforms += sgi-ip22 + platforms += sgi-ip27 +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -629,6 +629,29 @@ config RALINK + select ARCH_HAS_RESET_CONTROLLER + select RESET_CONTROLLER + ++config RTL838X ++ bool "Realtek based platforms" ++ select DMA_NONCOHERENT ++ select IRQ_MIPS_CPU ++ select CSRC_R4K ++ select CEVT_R4K ++ select SYS_HAS_CPU_MIPS32_R1 ++ select SYS_HAS_CPU_MIPS32_R2 ++ select SYS_SUPPORTS_BIG_ENDIAN ++ select SYS_SUPPORTS_32BIT_KERNEL ++ select SYS_SUPPORTS_MIPS16 ++ select SYS_SUPPORTS_MULTITHREADING ++ select SYS_SUPPORTS_VPE_LOADER ++ select SYS_HAS_EARLY_PRINTK ++ select SWAP_IO_SPACE ++ select BOOT_RAW ++ select CLKDEV_LOOKUP ++ select PINCTRL ++ select ARCH_HAS_RESET_CONTROLLER ++ select RESET_CONTROLLER ++ select RTL8380_SERIES ++ select USE_OF ++ + config SGI_IP22 + bool "SGI IP22 (Indy/Indigo2)" + select FW_ARC diff --git a/target/linux/rtl838x/patches-5.4/301-gpio-add-rtl838x-driver.patch b/target/linux/rtl838x/patches-5.4/301-gpio-add-rtl838x-driver.patch new file mode 100644 index 0000000000..5eb8521ccb --- /dev/null +++ b/target/linux/rtl838x/patches-5.4/301-gpio-add-rtl838x-driver.patch @@ -0,0 +1,25 @@ +--- a/drivers/gpio/Kconfig ++++ b/drivers/gpio/Kconfig +@@ -441,6 +441,12 @@ + A 32-bit single register GPIO fixed in/out implementation. This + can be used to represent any register as a set of GPIO signals. + ++config GPIO_RTL838X ++ tristate "RTL838X GPIO" ++ depends on RTL838X ++ help ++ Say yes here to support RTL838X GPIO devices. ++ + config GPIO_SAMA5D2_PIOBU + tristate "SAMA5D2 PIOBU GPIO support" + depends on MFD_SYSCON +--- a/drivers/gpio/Makefile ++++ b/drivers/gpio/Makefile +@@ -117,6 +117,7 @@ + obj-$(CONFIG_GPIO_RCAR) += gpio-rcar.o + obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o + obj-$(CONFIG_GPIO_REG) += gpio-reg.o ++obj-$(CONFIG_GPIO_RTL838X) += gpio-rtl838x.o + obj-$(CONFIG_ARCH_SA1100) += gpio-sa1100.o + obj-$(CONFIG_GPIO_SAMA5D2_PIOBU) += gpio-sama5d2-piobu.o + obj-$(CONFIG_GPIO_SCH311X) += gpio-sch311x.o diff --git a/target/linux/rtl838x/patches-5.4/400-mtd-add-rtl838x-spi-flash-driver.patch b/target/linux/rtl838x/patches-5.4/400-mtd-add-rtl838x-spi-flash-driver.patch new file mode 100644 index 0000000000..16cff75308 --- /dev/null +++ b/target/linux/rtl838x/patches-5.4/400-mtd-add-rtl838x-spi-flash-driver.patch @@ -0,0 +1,23 @@ +--- a/drivers/mtd/spi-nor/Kconfig ++++ b/drivers/mtd/spi-nor/Kconfig +@@ -118,4 +118,13 @@ config SPI_INTEL_SPI_PLATFORM + To compile this driver as a module, choose M here: the module + will be called intel-spi-platform. + ++config SPI_RTL838X ++ tristate "Realtek RTl838X SPI flash platform driver" ++ depends on RTL838X ++ help ++ This driver provides support for accessing SPI flash ++ in the RTL838X SoC. ++ ++ Say N here unless you know what you are doing. ++ + endif # MTD_SPI_NOR +--- a/drivers/mtd/spi-nor/Makefile ++++ b/drivers/mtd/spi-nor/Makefile +@@ -8,3 +8,4 @@ obj-$(CONFIG_SPI_NXP_SPIFI) += nxp-spifi + obj-$(CONFIG_SPI_INTEL_SPI) += intel-spi.o + obj-$(CONFIG_SPI_INTEL_SPI_PCI) += intel-spi-pci.o + obj-$(CONFIG_SPI_INTEL_SPI_PLATFORM) += intel-spi-platform.o ++obj-$(CONFIG_SPI_RTL838X) += rtl838x-nor.o diff --git a/target/linux/rtl838x/patches-5.4/700-net-dsa-add-support-for-rtl838x-switch.patch b/target/linux/rtl838x/patches-5.4/700-net-dsa-add-support-for-rtl838x-switch.patch new file mode 100644 index 0000000000..0082176d83 --- /dev/null +++ b/target/linux/rtl838x/patches-5.4/700-net-dsa-add-support-for-rtl838x-switch.patch @@ -0,0 +1,26 @@ +--- a/drivers/net/dsa/Kconfig ++++ b/drivers/net/dsa/Kconfig +@@ -74,6 +74,13 @@ config NET_DSA_REALTEK_SMI + This enables support for the Realtek SMI-based switch + chips, currently only RTL8366RB. + ++config NET_DSA_RTL838X ++ tristate "Realtek rtl838x switch support" ++ depends on RTL838X ++ select NET_DSA_TAG_TRAILER ++ ---help--- ++ Say Y here if you want to use the Realtek rtl838x switch. ++ + config NET_DSA_SMSC_LAN9303 + tristate + select NET_DSA_TAG_LAN9303 +--- a/drivers/net/dsa/Makefile ++++ b/drivers/net/dsa/Makefile +@@ -11,6 +11,7 @@ obj-$(CONFIG_NET_DSA_MV88E6060) += mv88e + obj-$(CONFIG_NET_DSA_QCA8K) += qca8k.o + obj-$(CONFIG_NET_DSA_REALTEK_SMI) += realtek-smi.o + realtek-smi-objs := realtek-smi-core.o rtl8366.o rtl8366rb.o ++obj-$(CONFIG_NET_DSA_RTL838X) += rtl838x_sw.o rtl838x_phy.o + obj-$(CONFIG_NET_DSA_SMSC_LAN9303) += lan9303-core.o + obj-$(CONFIG_NET_DSA_SMSC_LAN9303_I2C) += lan9303_i2c.o + obj-$(CONFIG_NET_DSA_SMSC_LAN9303_MDIO) += lan9303_mdio.o diff --git a/target/linux/rtl838x/patches-5.4/701-net-dsa-add-rtl838x-support-for-tag-trailer.patch b/target/linux/rtl838x/patches-5.4/701-net-dsa-add-rtl838x-support-for-tag-trailer.patch new file mode 100644 index 0000000000..d45c547803 --- /dev/null +++ b/target/linux/rtl838x/patches-5.4/701-net-dsa-add-rtl838x-support-for-tag-trailer.patch @@ -0,0 +1,37 @@ +--- a/net/dsa/tag_trailer.c ++++ b/net/dsa/tag_trailer.c +@@ -44,7 +44,12 @@ static struct sk_buff *trailer_xmit(stru + + trailer = skb_put(nskb, 4); + trailer[0] = 0x80; ++ ++#ifdef CONFIG_NET_DSA_RTL838X ++ trailer[1] = dp->index; ++#else + trailer[1] = 1 << dp->index; ++#endif /* CONFIG_NET_DSA_RTL838X */ + trailer[2] = 0x10; + trailer[3] = 0x00; + +@@ -61,12 +66,20 @@ static struct sk_buff *trailer_rcv(struc + return NULL; + + trailer = skb_tail_pointer(skb) - 4; ++ ++#ifdef CONFIG_NET_DSA_RTL838X ++ if (trailer[0] != 0x80 || (trailer[1] & 0xe0) != 0x00 || ++ (trailer[2] & 0xef) != 0x00 || trailer[3] != 0x00) ++ return NULL; ++ ++ source_port = trailer[1] & 0x1f; ++#else + if (trailer[0] != 0x80 || (trailer[1] & 0xf8) != 0x00 || + (trailer[2] & 0xef) != 0x00 || trailer[3] != 0x00) + return NULL; + + source_port = trailer[1] & 7; +- ++#endif + skb->dev = dsa_master_find_slave(dev, 0, source_port); + if (!skb->dev) + return NULL; diff --git a/target/linux/rtl838x/patches-5.4/702-net-dsa-increase-dsa-max-ports-for-rtl838x.patch b/target/linux/rtl838x/patches-5.4/702-net-dsa-increase-dsa-max-ports-for-rtl838x.patch new file mode 100644 index 0000000000..5329dcad59 --- /dev/null +++ b/target/linux/rtl838x/patches-5.4/702-net-dsa-increase-dsa-max-ports-for-rtl838x.patch @@ -0,0 +1,13 @@ +Index: linux-5.4.24/include/linux/platform_data/dsa.h +=================================================================== +--- linux-5.4.24.orig/include/linux/platform_data/dsa.h ++++ linux-5.4.24/include/linux/platform_data/dsa.h +@@ -6,7 +6,7 @@ struct device; + struct net_device; + + #define DSA_MAX_SWITCHES 4 +-#define DSA_MAX_PORTS 12 ++#define DSA_MAX_PORTS 54 + #define DSA_RTABLE_NONE -1 + + struct dsa_chip_data { diff --git a/target/linux/rtl838x/patches-5.4/702-net-ethernet-add-support-for-rtl838x-ethernet.patch b/target/linux/rtl838x/patches-5.4/702-net-ethernet-add-support-for-rtl838x-ethernet.patch new file mode 100644 index 0000000000..11e62450d5 --- /dev/null +++ b/target/linux/rtl838x/patches-5.4/702-net-ethernet-add-support-for-rtl838x-ethernet.patch @@ -0,0 +1,26 @@ +--- a/drivers/net/ethernet/Kconfig ++++ b/drivers/net/ethernet/Kconfig +@@ -163,6 +163,13 @@ source "drivers/net/ethernet/rdc/Kconfig + source "drivers/net/ethernet/realtek/Kconfig" + source "drivers/net/ethernet/renesas/Kconfig" + source "drivers/net/ethernet/rocker/Kconfig" ++ ++config NET_RTL838X ++ tristate "Realtek rtl838x Ethernet MAC support" ++ depends on RTL838X ++ ---help--- ++ Say Y here if you want to use the Realtek rtl838x Gbps Ethernet MAC. ++ + source "drivers/net/ethernet/samsung/Kconfig" + source "drivers/net/ethernet/seeq/Kconfig" + source "drivers/net/ethernet/sfc/Kconfig" +--- a/drivers/net/ethernet/Makefile ++++ b/drivers/net/ethernet/Makefile +@@ -76,6 +76,7 @@ obj-$(CONFIG_NET_VENDOR_REALTEK) += real + obj-$(CONFIG_NET_VENDOR_RENESAS) += renesas/ + obj-$(CONFIG_NET_VENDOR_RDC) += rdc/ + obj-$(CONFIG_NET_VENDOR_ROCKER) += rocker/ ++obj-$(CONFIG_NET_RTL838X) += rtl838x_eth.o + obj-$(CONFIG_NET_VENDOR_SAMSUNG) += samsung/ + obj-$(CONFIG_NET_VENDOR_SEEQ) += seeq/ + obj-$(CONFIG_NET_VENDOR_SILAN) += silan/ diff --git a/target/linux/rtl838x/patches-5.4/703-include-linux-add-phy-ops-for-rtl838x.patch b/target/linux/rtl838x/patches-5.4/703-include-linux-add-phy-ops-for-rtl838x.patch new file mode 100644 index 0000000000..db8b0403f7 --- /dev/null +++ b/target/linux/rtl838x/patches-5.4/703-include-linux-add-phy-ops-for-rtl838x.patch @@ -0,0 +1,13 @@ +--- a/include/linux/phy.h ++++ b/include/linux/phy.h +@@ -628,6 +628,10 @@ + struct ethtool_tunable *tuna, + const void *data); + int (*set_loopback)(struct phy_device *dev, bool enable); ++ int (*get_port)(struct phy_device *dev); ++ int (*set_port)(struct phy_device *dev, int port); ++ int (*get_eee)(struct phy_device *dev, struct ethtool_eee *e); ++ int (*set_eee)(struct phy_device *dev, struct ethtool_eee *e); + }; + #define to_phy_driver(d) container_of(to_mdio_common_driver(d), \ + struct phy_driver, mdiodrv) diff --git a/target/linux/rtl838x/patches-5.4/704-drivers-net-phy-eee-support-for-rtl838x.patch b/target/linux/rtl838x/patches-5.4/704-drivers-net-phy-eee-support-for-rtl838x.patch new file mode 100644 index 0000000000..5262be53c6 --- /dev/null +++ b/target/linux/rtl838x/patches-5.4/704-drivers-net-phy-eee-support-for-rtl838x.patch @@ -0,0 +1,41 @@ +--- a/drivers/net/phy/phylink.c ++++ b/drivers/net/phy/phylink.c +@@ -1244,6 +1244,11 @@ + + /* If we have a PHY, configure the phy */ + if (pl->phydev) { ++ if (pl->phydev->drv->get_port && pl->phydev->drv->set_port) { ++ if(pl->phydev->drv->get_port(pl->phydev) != kset->base.port) { ++ pl->phydev->drv->set_port(pl->phydev, kset->base.port); ++ } ++ } + ret = phy_ethtool_ksettings_set(pl->phydev, &our_kset); + if (ret) + return ret; +@@ -1422,8 +1427,11 @@ + + ASSERT_RTNL(); + +- if (pl->phydev) ++ if (pl->phydev) { ++ if (pl->phydev->drv->get_eee) ++ return pl->phydev->drv->get_eee(pl->phydev, eee); + ret = phy_ethtool_get_eee(pl->phydev, eee); ++ } + + return ret; + } +@@ -1440,9 +1448,11 @@ + + ASSERT_RTNL(); + +- if (pl->phydev) ++ if (pl->phydev) { ++ if (pl->phydev->drv->set_eee) ++ return pl->phydev->drv->set_eee(pl->phydev, eee); + ret = phy_ethtool_set_eee(pl->phydev, eee); +- ++ } + return ret; + } + EXPORT_SYMBOL_GPL(phylink_ethtool_set_eee); diff --git a/target/linux/rtl838x/profiles/00-default.mk b/target/linux/rtl838x/profiles/00-default.mk new file mode 100644 index 0000000000..d6890a815a --- /dev/null +++ b/target/linux/rtl838x/profiles/00-default.mk @@ -0,0 +1,13 @@ +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Default + NAME:=Default Profile + PRIORITY:=1 +endef + +define Profile/Default/Description + Default package set compatible with most boards. +endef +$(eval $(call Profile,Default)) -- cgit v1.2.3