From ebddc5f984a240980303aed68524eb615484eef8 Mon Sep 17 00:00:00 2001 From: David Bauer Date: Tue, 19 May 2020 22:49:35 +0200 Subject: ath79: add support for Enterasys WS-AP3705i Hardware -------- SoC: Atheros AR9344 RAM: 128M DDR2 FLASH: 2x Macronix MX25L12845EM 2x 16MiB SPI-NOR WLAN2: Atheros AR9344 2x2 2T2R WLAN5: Atheros AR9580 2x2 2T2R SERIAL: Cisco-RJ45 on the back (115200 8n1) Installation ------------ The U-Boot CLI is password protected (using the same credentials as the OS). Default is admin/new2day. 1. Download the OpenWrt initramfs-image. Place it into a TFTP server root directory and rename it to 1401A8C0.img. Configure the TFTP server to listen at 192.168.1.66/24. 2. Connect the TFTP server to the access point. 3. Connect to the serial console of the access point. Attach power and interrupt the boot procedure when prompted (bootdelay is 1 second). 4. Configure the U-Boot environment for booting OpenWrt from Ram and flash: $ setenv boot_openwrt 'setenv bootargs; bootm 0xbf230000' $ setenv ramboot_openwrt 'setenv serverip 192.168.1.66; tftpboot 0x85000000; bootm' $ setenv bootcmd 'run boot_openwrt' $ saveenv 5. Load OpenWrt into memory: $ run ramboot_openwrt Wait for the image to boot. 6. Transfer the OpenWrt sysupgrade image to the device. Write the image to flash using sysupgrade: $ sysupgrade -n /path/to/openwrt-sysuograde.bin Signed-off-by: David Bauer --- .../ath79/dts/ar9344_enterasys_ws-ap3705i.dts | 236 +++++++++++++++++++++ 1 file changed, 236 insertions(+) create mode 100644 target/linux/ath79/dts/ar9344_enterasys_ws-ap3705i.dts (limited to 'target/linux/ath79/dts') diff --git a/target/linux/ath79/dts/ar9344_enterasys_ws-ap3705i.dts b/target/linux/ath79/dts/ar9344_enterasys_ws-ap3705i.dts new file mode 100644 index 0000000000..0f02881471 --- /dev/null +++ b/target/linux/ath79/dts/ar9344_enterasys_ws-ap3705i.dts @@ -0,0 +1,236 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/dts-v1/; + +#include +#include + +#include "ar9344.dtsi" + +/ { + compatible = "enterasys,ws-ap3705i", "qca,ar9344"; + model = "Enterasys WS-AP3705i"; + + chosen { + bootargs = "console=ttyS0,115200n8"; + }; + + aliases { + led-boot = &led_power_green; + led-failsafe = &led_power_red; + led-running = &led_power_green; + led-upgrade = &led_power_red; + label-mac-device = ð0; + }; + + mtd-concat { + compatible = "mtd-concat"; + devices = <&concat0 &concat1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + compatible = "denx,uimage"; + label = "firmware"; + reg = <0x0 0x1dd0000>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + pinctrl-names = "default"; + pinctrl-0 = <&enable_gpio_11 &enable_gpio_16>; + + led_power_green: power_green { + label = "ws-ap3705i:green:power"; + gpios = <&gpio 13 GPIO_ACTIVE_LOW>; + }; + + led_power_red: power_red { + label = "ws-ap3705i:red:power"; + gpios = <&gpio 16 GPIO_ACTIVE_LOW>; + }; + + lan_blue { + label = "ws-ap3705i:blue:lan"; + gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; + }; + + lan_green { + label = "ws-ap3705i:green:lan"; + gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; + }; + + radio2 { + label = "ws-ap3705i:green:radio2"; + gpios = <&gpio 11 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy0tpt"; + }; + }; + + ath9k-leds { + compatible = "gpio-leds"; + + radio1 { + label = "ws-ap3705i:green:radio1"; + gpios = <&ath9k 0 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy1tpt"; + }; + }; + + keys { + compatible = "gpio-keys"; + + reset { + label = "Reset button"; + linux,code = ; + gpios = <&gpio 17 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&ref { + clock-frequency = <40000000>; +}; + +&uart { + status = "okay"; +}; + +&pinmux { + enable_gpio_16: pinmux_enable_gpio_16 { + pinctrl-single,bits = <0x10 0x0 0x000000ff>; + }; + + enable_gpio_11: pinmux_enable_gpio_11 { + pinctrl-single,bits = <0x8 0x0 0xff000000>; + }; +}; + +&gpio { + status = "okay"; +}; + +&wmac { + status = "okay"; + qca,no-eeprom; +}; + +&spi { + status = "okay"; + + cs-gpios = <0>, <0>; + num-cs = <2>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot-bak"; + reg = <0x0 0x80000>; + read-only; + }; + + partition@80000 { + label = "u-boot-env0"; + reg = <0x80000 0x10000>; + read-only; + }; + + partition@90000 { + label = "u-boot-env1"; + reg = <0x90000 0x10000>; + read-only; + }; + + partition@a0000 { + label = "u-boot"; + reg = <0xa0000 0x80000>; + read-only; + }; + + partition@120000 { + label = "calibrate"; + reg = <0x120000 0x10000>; + read-only; + }; + + partition@130000 { + label = "nvram"; + reg = <0x130000 0x100000>; + read-only; + }; + + concat0: partition@230000 { + label = "concat0"; + reg = <0x230000 0xdd0000>; + }; + }; + }; + + flash@1 { + compatible = "jedec,spi-nor"; + reg = <1>; + spi-max-frequency = <25000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + concat1: partition@0 { + label = "concat1"; + reg = <0x0 0x1000000>; + }; + }; + }; +}; + +&pcie { + status = "okay"; + + ath9k: wifi@0,0 { + compatible = "pci168c,0033"; + reg = <0x0000 0 0 0 0>; + qca,no-eeprom; + #gpio-cells = <2>; + gpio-controller; + }; +}; + +&mdio0 { + status = "okay"; + + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +ð0 { + status = "okay"; + + pll-data = <0x1e000000 0x08000101 0x08001313>; + + phy-mode = "rgmii"; + phy-handle = <&phy0>; + + gmac-config { + device = <&gmac>; + rgmii-gmac0 = <1>; + rxd-delay = <0>; + rxdv-delay = <0>; + txen-delay = <0>; + txd-delay = <0>; + }; +}; -- cgit v1.2.3