From 53c474abbdfef8eb3499e2d10c9ad491788b8a72 Mon Sep 17 00:00:00 2001 From: John Crispin Date: Sun, 6 May 2018 10:20:11 +0200 Subject: ath79: add new OF only target for QCA MIPS silicon This target aims to replace ar71xx mid-term. The big part that is still missing is making the MMIO/AHB wifi work using OF. NAND and mikrotik subtargets will follow. Signed-off-by: John Crispin --- target/linux/ath79/image/lzma-loader/src/cache.c | 43 ++++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 target/linux/ath79/image/lzma-loader/src/cache.c (limited to 'target/linux/ath79/image/lzma-loader/src/cache.c') diff --git a/target/linux/ath79/image/lzma-loader/src/cache.c b/target/linux/ath79/image/lzma-loader/src/cache.c new file mode 100644 index 0000000000..28cc848333 --- /dev/null +++ b/target/linux/ath79/image/lzma-loader/src/cache.c @@ -0,0 +1,43 @@ +/* + * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards + * + * Copyright (C) 2011 Gabor Juhos + * + * The cache manipulation routine has been taken from the U-Boot project. + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include "cache.h" +#include "cacheops.h" +#include "config.h" + +#define cache_op(op,addr) \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noreorder \n" \ + " .set mips3\n\t \n" \ + " cache %0, %1 \n" \ + " .set pop \n" \ + : \ + : "i" (op), "R" (*(unsigned char *)(addr))) + +void flush_cache(unsigned long start_addr, unsigned long size) +{ + unsigned long lsize = CONFIG_CACHELINE_SIZE; + unsigned long addr = start_addr & ~(lsize - 1); + unsigned long aend = (start_addr + size - 1) & ~(lsize - 1); + + while (1) { + cache_op(Hit_Writeback_Inv_D, addr); + cache_op(Hit_Invalidate_I, addr); + if (addr == aend) + break; + addr += lsize; + } +} -- cgit v1.2.3