From 84d555aa74434392b682fd9eb0fa701c89a046d6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Tue, 4 Feb 2020 19:02:53 +0100 Subject: brcm2708: update to latest patches from RPi foundation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Álvaro Fernández Rojas --- ...60-overlays-Add-the-spi-gpio40-45-overlay.patch | 80 ++++++++++++++++++++++ 1 file changed, 80 insertions(+) create mode 100644 target/linux/brcm2708/patches-4.19/950-0560-overlays-Add-the-spi-gpio40-45-overlay.patch (limited to 'target/linux/brcm2708/patches-4.19/950-0560-overlays-Add-the-spi-gpio40-45-overlay.patch') diff --git a/target/linux/brcm2708/patches-4.19/950-0560-overlays-Add-the-spi-gpio40-45-overlay.patch b/target/linux/brcm2708/patches-4.19/950-0560-overlays-Add-the-spi-gpio40-45-overlay.patch new file mode 100644 index 0000000000..26930baadd --- /dev/null +++ b/target/linux/brcm2708/patches-4.19/950-0560-overlays-Add-the-spi-gpio40-45-overlay.patch @@ -0,0 +1,80 @@ +From 726da40b8c272d181a41686195f91b914363167b Mon Sep 17 00:00:00 2001 +From: Tim Gover +Date: Tue, 22 Jan 2019 10:49:41 +0000 +Subject: [PATCH] overlays: Add the spi-gpio40-45 overlay + +The 2711 B0 boot EEPROM is programmed via SPI0 on GPIO +pins 40-43 CS0. Add a device tree overlay to optionally +change the SPI0 pinmux from the external GPIO pins to +the boot EEPROM pins. +--- + arch/arm/boot/dts/overlays/Makefile | 1 + + arch/arm/boot/dts/overlays/README | 6 ++++ + .../dts/overlays/spi-gpio40-45-overlay.dts | 36 +++++++++++++++++++ + 3 files changed, 43 insertions(+) + create mode 100644 arch/arm/boot/dts/overlays/spi-gpio40-45-overlay.dts + +--- a/arch/arm/boot/dts/overlays/Makefile ++++ b/arch/arm/boot/dts/overlays/Makefile +@@ -135,6 +135,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \ + smi-dev.dtbo \ + smi-nand.dtbo \ + spi-gpio35-39.dtbo \ ++ spi-gpio40-45.dtbo \ + spi-rtc.dtbo \ + spi0-cs.dtbo \ + spi0-hw-cs.dtbo \ +--- a/arch/arm/boot/dts/overlays/README ++++ b/arch/arm/boot/dts/overlays/README +@@ -1967,6 +1967,12 @@ Load: dtoverlay=spi-gpio35-39 + Params: + + ++Name: spi-gpio40-45 ++Info: Move SPI function block to GPIOs 40 to 45 ++Load: dtoverlay=spi-gpio40-45 ++Params: ++ ++ + Name: spi-rtc + Info: Adds support for a number of SPI Real Time Clock devices + Load: dtoverlay=spi-rtc,= +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/spi-gpio40-45-overlay.dts +@@ -0,0 +1,36 @@ ++/* ++ * Boot EEPROM overlay ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2835"; ++ ++ fragment@0 { ++ target = <&spi0>; ++ __overlay__ { ++ cs-gpios = <&gpio 43 1>, <&gpio 44 1>, <&gpio 45 1>; ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi0_cs_pins>; ++ __overlay__ { ++ brcm,pins = <45 44 43>; ++ brcm,function = <1>; /* output */ ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi0_pins>; ++ __overlay__ { ++ brcm,pins = <40 41 42>; ++ brcm,function = <3>; /* alt4 */ ++ status = "okay"; ++ }; ++ }; ++}; -- cgit v1.2.3