From 0ace4636dba140db5ecf1cadb985982378be41dc Mon Sep 17 00:00:00 2001
From: Imre Kaloz <kaloz@openwrt.org>
Date: Sat, 11 Feb 2012 15:59:23 +0000
Subject: rename 3.1 patches directory as it will be used for newer kernels as
well
SVN-Revision: 30454
---
target/linux/cns3xxx/patches/054-cns3xxx_pcie_clock.patch | 11 +++++++++++
1 file changed, 11 insertions(+)
create mode 100644 target/linux/cns3xxx/patches/054-cns3xxx_pcie_clock.patch
(limited to 'target/linux/cns3xxx/patches/054-cns3xxx_pcie_clock.patch')
diff --git a/target/linux/cns3xxx/patches/054-cns3xxx_pcie_clock.patch b/target/linux/cns3xxx/patches/054-cns3xxx_pcie_clock.patch
new file mode 100644
index 0000000000..0c6c525039
--- /dev/null
+++ b/target/linux/cns3xxx/patches/054-cns3xxx_pcie_clock.patch
@@ -0,0 +1,11 @@
+--- a/arch/arm/mach-cns3xxx/pcie.c
++++ b/arch/arm/mach-cns3xxx/pcie.c
+@@ -378,8 +378,6 @@ static int __init cns3xxx_pcie_init(void
+ for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
+ iotable_init(cns3xxx_pcie[i].cfg_bases,
+ ARRAY_SIZE(cns3xxx_pcie[i].cfg_bases));
+- cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_PCIE(i));
+- cns3xxx_pwr_soft_rst(0x1 << PM_SOFT_RST_REG_OFFST_PCIE(i));
+ cns3xxx_pcie_check_link(&cns3xxx_pcie[i]);
+ cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]);
+ pci_common_init(&cns3xxx_pcie[i].hw_pci);
--
cgit v1.2.3