From 6b13238a132c6c6e7a12b708e2655002e94c12a8 Mon Sep 17 00:00:00 2001 From: Mathias Kresin Date: Wed, 15 Aug 2018 08:20:33 +0200 Subject: generic: revert workarounds for AR8337 switch The intention of 967b6be118e3 ("ar8327: Add workarounds for AR8337 switch") was to remove the register fixups for AR8337. But instead they were removed for AR8327. The RGMII RX delay is forced even if the port is used as phy instead of mac, which results in no package flow at least for one board. Fixes: FS#1664 Signed-off-by: Mathias Kresin --- .../linux/generic/files/drivers/net/phy/ar8327.c | 42 +--------------------- 1 file changed, 1 insertion(+), 41 deletions(-) (limited to 'target/linux/generic/files/drivers/net/phy/ar8327.c') diff --git a/target/linux/generic/files/drivers/net/phy/ar8327.c b/target/linux/generic/files/drivers/net/phy/ar8327.c index 7bfc187509..74f0a08d76 100644 --- a/target/linux/generic/files/drivers/net/phy/ar8327.c +++ b/target/linux/generic/files/drivers/net/phy/ar8327.c @@ -506,14 +506,6 @@ ar8327_hw_config_pdata(struct ar8xxx_priv *priv, ar8xxx_write(priv, AR8327_REG_PAD0_MODE, t); t = ar8327_get_pad_cfg(pdata->pad5_cfg); - if (chip_is_ar8337(priv)) { - /* - * Workaround: RGMII RX delay setting needs to be - * always specified for AR8337 to avoid port 5 - * RX hang on high traffic / flood conditions - */ - t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN; - } ar8xxx_write(priv, AR8327_REG_PAD5_MODE, t); t = ar8327_get_pad_cfg(pdata->pad6_cfg); ar8xxx_write(priv, AR8327_REG_PAD6_MODE, t); @@ -678,39 +670,6 @@ ar8327_init_globals(struct ar8xxx_priv *priv) /* Disable EEE on all phy's due to stability issues */ for (i = 0; i < AR8XXX_NUM_PHYS; i++) data->eee[i] = false; - - if (chip_is_ar8337(priv)) { - /* Update HOL registers with values suggested by QCA switch team */ - for (i = 0; i < AR8327_NUM_PORTS; i++) { - if (i == AR8216_PORT_CPU || i == 5 || i == 6) { - t = 0x3 << AR8327_PORT_HOL_CTRL0_EG_PRI0_BUF_S; - t |= 0x4 << AR8327_PORT_HOL_CTRL0_EG_PRI1_BUF_S; - t |= 0x4 << AR8327_PORT_HOL_CTRL0_EG_PRI2_BUF_S; - t |= 0x4 << AR8327_PORT_HOL_CTRL0_EG_PRI3_BUF_S; - t |= 0x6 << AR8327_PORT_HOL_CTRL0_EG_PRI4_BUF_S; - t |= 0x8 << AR8327_PORT_HOL_CTRL0_EG_PRI5_BUF_S; - t |= 0x1e << AR8327_PORT_HOL_CTRL0_EG_PORT_BUF_S; - } else { - t = 0x3 << AR8327_PORT_HOL_CTRL0_EG_PRI0_BUF_S; - t |= 0x4 << AR8327_PORT_HOL_CTRL0_EG_PRI1_BUF_S; - t |= 0x6 << AR8327_PORT_HOL_CTRL0_EG_PRI2_BUF_S; - t |= 0x8 << AR8327_PORT_HOL_CTRL0_EG_PRI3_BUF_S; - t |= 0x19 << AR8327_PORT_HOL_CTRL0_EG_PORT_BUF_S; - } - ar8xxx_write(priv, AR8327_REG_PORT_HOL_CTRL0(i), t); - - t = 0x6 << AR8327_PORT_HOL_CTRL1_ING_BUF_S; - t |= AR8327_PORT_HOL_CTRL1_EG_PRI_BUF_EN; - t |= AR8327_PORT_HOL_CTRL1_EG_PORT_BUF_EN; - t |= AR8327_PORT_HOL_CTRL1_WRED_EN; - ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(i), - AR8327_PORT_HOL_CTRL1_ING_BUF | - AR8327_PORT_HOL_CTRL1_EG_PRI_BUF_EN | - AR8327_PORT_HOL_CTRL1_EG_PORT_BUF_EN | - AR8327_PORT_HOL_CTRL1_WRED_EN, - t); - } - } } static void @@ -1498,6 +1457,7 @@ const struct ar8xxx_chip ar8327_chip = { .atu_flush_port = ar8327_atu_flush_port, .vtu_flush = ar8327_vtu_flush, .vtu_load_vlan = ar8327_vtu_load_vlan, + .phy_fixup = ar8327_phy_fixup, .set_mirror_regs = ar8327_set_mirror_regs, .get_arl_entry = ar8327_get_arl_entry, .sw_hw_apply = ar8327_sw_hw_apply, -- cgit v1.2.3