From f2b7d9dc1ca3d33f14961cf2885639f4f9e8965e Mon Sep 17 00:00:00 2001
From: Chris Blake <chrisrblake93@gmail.com>
Date: Sat, 30 Sep 2017 11:14:58 -0500
Subject: mpc85xx: Add Aerohive HiveAP-330 Access Point
The following adds the Aerohive HiveAP-330 Access Point to LEDE under
the mpc85xx/p1020 subtarget.
Hardware:
- SoC: Freescale P1020NSE2DFB
- NAND: Intel JS28F512M29EWH 64MB
- Memory: 2x ProMOS V59C1G01168QBJ3 128MB (Total of 256MB)
- 2.4GHz WiFi: Atheros AR9390-AL1A
- 5.0GHz WiFi: Atheros AR9390-AL1A
- Eth1: Atheros AR8035-A PoE
- Eth2: Atheros AR8035-A
- TPM: Atmel AT97SC3204
- LED Driver: TI LP5521
Flashing:
1. Hook into UART (9600 baud) and enter U-Boot. You may need to enter a
password of administrator or AhNf?d@ta06 if prompted.
2. Once in U-Boot, tftp boot the initramfs image:
dhcp;
tftpboot 0x1000000 192.168.1.101:lede-
mpc85xx-p1020-hiveap-330-initramfs.zImage;
tftpboot 0x6000000 192.168.1.101:lede-mpc85xx-p1020-hiveap-330.fdt;
bootm 0x1000000 - 0x6000000;
3. Once booted, scp over the sysupgrade file and sysupgrade the device
to flash LEDE to the NAND.
sysupgrade /tmp/lede-mpc85xx-p1020-hiveap-330-sysupgrade.img
Signed-off-by: Chris Blake <chrisrblake93@gmail.com>
---
.../files/arch/powerpc/boot/dts/hiveap-330.dts | 227 +++++++++++++++++++++
.../files/arch/powerpc/platforms/85xx/hiveap-330.c | 89 ++++++++
2 files changed, 316 insertions(+)
create mode 100644 target/linux/mpc85xx/files/arch/powerpc/boot/dts/hiveap-330.dts
create mode 100644 target/linux/mpc85xx/files/arch/powerpc/platforms/85xx/hiveap-330.c
(limited to 'target/linux/mpc85xx/files/arch/powerpc')
diff --git a/target/linux/mpc85xx/files/arch/powerpc/boot/dts/hiveap-330.dts b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/hiveap-330.dts
new file mode 100644
index 0000000000..7900c40c7e
--- /dev/null
+++ b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/hiveap-330.dts
@@ -0,0 +1,227 @@
+/*
+ * Aerohive HiveAP-330 Device Tree Source
+ *
+ * Copyright (C) 2017 Chris Blake <chrisrblake93@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/include/ "fsl/p1020si-pre.dtsi"
+/ {
+ model = "Aerohive HiveAP-330";
+ compatible = "aerohive,hiveap-330";
+
+ chosen {
+ bootargs = "console=ttyS0,9600";
+ bootargs-override = "console=ttyS0,9600 noinitrd";
+ };
+
+ memory {
+ device_type = "memory";
+ };
+
+ board_lbc: lbc: localbus@ffe05000 {
+ reg = <0 0xffe05000 0 0x1000>;
+ ranges = <0x0 0x0 0x0 0xec000000 0x4000000>;
+
+ nor@0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x4000000>;
+ bank-width = <2>;
+ device-width = <1>;
+
+ partition@0 {
+ reg = <0x0 0x40000>;
+ label = "dtb";
+ };
+
+ partition@40000 {
+ reg = <0x40000 0x40000>;
+ label = "initramfs";
+ };
+
+ partition@80000 {
+ reg = <0x80000 0x27c0000>;
+ label = "rootfs";
+ };
+
+ partition@2840000 {
+ reg = <0x2840000 0x800000>;
+ label = "kernel";
+ };
+
+ partition@3040000 {
+ reg = <0x3040000 0xec0000>;
+ label = "stock-jffs2";
+ read-only;
+ };
+
+ partition@3f00000 {
+ reg = <0x3f00000 0x20000>;
+ label = "hw-info";
+ read-only;
+ };
+
+ partition@3f20000 {
+ reg = <0x3f20000 0x20000>;
+ label = "boot-info";
+ read-only;
+ };
+
+ partition@3f40000 {
+ reg = <0x3f40000 0x20000>;
+ label = "boot-info-backup";
+ read-only;
+ };
+
+ partition@3f60000 {
+ reg = <0x3f60000 0x20000>;
+ label = "u-boot-env";
+ };
+
+ partition@3f80000 {
+ reg = <0x3f80000 0x80000>;
+ label = "u-boot";
+ read-only;
+ };
+
+ firmware@0 {
+ reg = <0x0 0x3040000>;
+ label = "firmware";
+ };
+ };
+ };
+
+ board_soc: soc: soc@ffe00000 {
+ ranges = <0x0 0x0 0xffe00000 0x100000>;
+
+ i2c@3100 {
+ tpm@29 {
+ compatible = "atmel,at97sc3204t";
+ reg = <0x29>;
+ };
+
+ lp5521@32 {
+ compatible = "national,lp5521";
+ reg = <0x32>;
+ clock-mode = /bits/ 8 <2>;
+ chan0 {
+ chan-name = "hiveap-330:red:tricolor0";
+ led-cur = /bits/ 8 <0x2f>;
+ max-cur = /bits/ 8 <0x5f>;
+ };
+ chan1 {
+ chan-name = "hiveap-330:green:tricolor0";
+ led-cur = /bits/ 8 <0x2f>;
+ max-cur = /bits/ 8 <0x5f>;
+ };
+ chan2 {
+ chan-name = "hiveap-330:blue:tricolor0";
+ led-cur = /bits/ 8 <0x2f>;
+ max-cur = /bits/ 8 <0x5f>;
+ };
+ };
+
+ /* Most likely SoC boot config */
+ eeprom@51 {
+ compatible = "eeprom";
+ reg = <0x51>;
+ };
+ };
+
+ mdio@24000 {
+ phy0: ethernet-phy@0 {
+ interrupts = <3 1 0 0>;
+ reg = <0x1>;
+ };
+
+ phy1: ethernet-phy@1 {
+ interrupts = <2 1 0 0>;
+ reg = <0x2>;
+ };
+ };
+
+ mdio@25000 {
+ status = "disabled";
+ };
+
+ mdio@26000 {
+ status = "disabled";
+ };
+
+ enet0: ethernet@b0000 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-connection-type = "rgmii-id";
+
+ };
+
+ enet1: ethernet@b1000 {
+ status = "disabled";
+ };
+
+ enet2: ethernet@b2000 {
+ status = "okay";
+ phy-handle = <&phy1>;
+ phy-connection-type = "rgmii-id";
+ };
+
+ gpio0: gpio-controller@fc00 {
+ };
+
+ usb@22000 {
+ phy_type = "ulpi";
+ dr_mode = "host";
+ };
+
+ usb@23000 {
+ status = "disabled";
+ };
+ };
+
+ pci0: pcie@ffe09000 {
+ reg = <0x0 0xffe09000 0x0 0x1000>;
+ ranges = <0x2000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000
+ 0x1000000 0x0 0x00000000 0x0 0xffc30000 0x0 0x10000>;
+ pcie@0 {
+ ranges = <0x2000000 0x0 0xa0000000
+ 0x2000000 0x0 0xa0000000
+ 0x0 0x20000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x100000>;
+ };
+ };
+
+ pci1: pcie@ffe0a000 {
+ reg = <0x0 0xffe0a000 0x0 0x1000>;
+ ranges = <0x2000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000
+ 0x1000000 0x0 0x00000000 0x0 0xffc20000 0x0 0x10000>;
+ pcie@0 {
+ ranges = <0x2000000 0x0 0xc0000000
+ 0x2000000 0x0 0xc0000000
+ 0x0 0x20000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x100000>;
+ };
+ };
+
+ buttons {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "Reset button";
+ gpios = <&gpio0 8 1>; /* active low */
+ linux,code = <0x198>; /* KEY_RESTART */
+ };
+ };
+};
+/include/ "fsl/p1020si-post.dtsi"
diff --git a/target/linux/mpc85xx/files/arch/powerpc/platforms/85xx/hiveap-330.c b/target/linux/mpc85xx/files/arch/powerpc/platforms/85xx/hiveap-330.c
new file mode 100644
index 0000000000..f325b32ce6
--- /dev/null
+++ b/target/linux/mpc85xx/files/arch/powerpc/platforms/85xx/hiveap-330.c
@@ -0,0 +1,89 @@
+/*
+ * Aerohive HiveAP-330 Board Setup
+ *
+ * Copyright (C) 2017 Chris Blake <chrisrblake93@gmail.com>
+ *
+ * Based on:
+ * mpc85xx_rdb.c:
+ * MPC85xx RDB Board Setup
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/of_platform.h>
+
+#include <asm/time.h>
+#include <asm/machdep.h>
+#include <asm/pci-bridge.h>
+#include <mm/mmu_decl.h>
+#include <asm/prom.h>
+#include <asm/udbg.h>
+#include <asm/mpic.h>
+
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+#include "smp.h"
+
+#include "mpc85xx.h"
+
+void __init hiveap_330_pic_init(void)
+{
+ struct mpic *mpic;
+
+ mpic = mpic_alloc(NULL, 0,
+ MPIC_BIG_ENDIAN |
+ MPIC_SINGLE_DEST_CPU,
+ 0, 256, " OpenPIC ");
+
+ BUG_ON(mpic == NULL);
+ mpic_init(mpic);
+}
+
+/*
+ * Setup the architecture
+ */
+static void __init hiveap_330_setup_arch(void)
+{
+ if (ppc_md.progress)
+ ppc_md.progress("hiveap_330_setup_arch()", 0);
+
+ mpc85xx_smp_init();
+
+ fsl_pci_assign_primary();
+
+ printk(KERN_INFO "HiveAP-330 board from Aerohive\n");
+}
+
+machine_arch_initcall(hiveap_330, mpc85xx_common_publish_devices);
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init hiveap_330_probe(void)
+{
+ if (of_machine_is_compatible("aerohive,hiveap-330"))
+ return 1;
+ return 0;
+}
+
+define_machine(hiveap_330) {
+ .name = "P1020 RDB",
+ .probe = hiveap_330_probe,
+ .setup_arch = hiveap_330_setup_arch,
+ .init_IRQ = hiveap_330_pic_init,
+#ifdef CONFIG_PCI
+ .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
+ .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
+#endif
+ .get_irq = mpic_get_irq,
+ .calibrate_decr = generic_calibrate_decr,
+ .progress = udbg_progress,
+};
--
cgit v1.2.3