From 26b06940a9bd894c1a21d76b160a3daea0843417 Mon Sep 17 00:00:00 2001 From: Luka Perkov Date: Sun, 29 Jun 2014 23:29:57 +0000 Subject: mvebu: drop 3.10 support Signed-off-by: Luka Perkov SVN-Revision: 41406 --- .../0096-clk-mvebu-Add-Core-Divider-clock.patch | 273 --------------------- 1 file changed, 273 deletions(-) delete mode 100644 target/linux/mvebu/patches-3.10/0096-clk-mvebu-Add-Core-Divider-clock.patch (limited to 'target/linux/mvebu/patches-3.10/0096-clk-mvebu-Add-Core-Divider-clock.patch') diff --git a/target/linux/mvebu/patches-3.10/0096-clk-mvebu-Add-Core-Divider-clock.patch b/target/linux/mvebu/patches-3.10/0096-clk-mvebu-Add-Core-Divider-clock.patch deleted file mode 100644 index 968877cab2..0000000000 --- a/target/linux/mvebu/patches-3.10/0096-clk-mvebu-Add-Core-Divider-clock.patch +++ /dev/null @@ -1,273 +0,0 @@ -From ac8294dfb4085f3193bec27673062e5ad63d770a Mon Sep 17 00:00:00 2001 -From: Ezequiel Garcia -Date: Thu, 26 Sep 2013 16:35:27 -0300 -Subject: [PATCH 096/203] clk: mvebu: Add Core Divider clock - -This commit introduces a new group of clocks present in Armada 370/XP -SoCs (called "Core Divider" clocks) and add a provider for them. -The only clock supported for now is the NAND clock (ndclk), but the -infrastructure to add the rest is already set. - -Reviewed-by: Gregory CLEMENT -Signed-off-by: Ezequiel Garcia -Signed-off-by: Mike Turquette ---- - arch/arm/mach-mvebu/Kconfig | 1 + - drivers/clk/mvebu/Kconfig | 3 + - drivers/clk/mvebu/Makefile | 1 + - drivers/clk/mvebu/clk-corediv.c | 223 ++++++++++++++++++++++++++++++++++++++++ - 4 files changed, 228 insertions(+) - create mode 100644 drivers/clk/mvebu/clk-corediv.c - ---- a/arch/arm/mach-mvebu/Kconfig -+++ b/arch/arm/mach-mvebu/Kconfig -@@ -13,6 +13,7 @@ config ARCH_MVEBU - select MVEBU_CLK_CORE - select MVEBU_CLK_CPU - select MVEBU_CLK_GATING -+ select MVEBU_CLK_COREDIV - select MVEBU_MBUS - select ZONE_DMA if ARM_LPAE - select ARCH_REQUIRE_GPIOLIB ---- a/drivers/clk/mvebu/Kconfig -+++ b/drivers/clk/mvebu/Kconfig -@@ -6,3 +6,6 @@ config MVEBU_CLK_CPU - - config MVEBU_CLK_GATING - bool -+ -+config MVEBU_CLK_COREDIV -+ bool ---- a/drivers/clk/mvebu/Makefile -+++ b/drivers/clk/mvebu/Makefile -@@ -1,3 +1,4 @@ - obj-$(CONFIG_MVEBU_CLK_CORE) += clk.o clk-core.o - obj-$(CONFIG_MVEBU_CLK_CPU) += clk-cpu.o - obj-$(CONFIG_MVEBU_CLK_GATING) += clk-gating-ctrl.o -+obj-$(CONFIG_MVEBU_CLK_COREDIV) += clk-corediv.o ---- /dev/null -+++ b/drivers/clk/mvebu/clk-corediv.c -@@ -0,0 +1,223 @@ -+/* -+ * MVEBU Core divider clock -+ * -+ * Copyright (C) 2013 Marvell -+ * -+ * Ezequiel Garcia -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define CORE_CLK_DIV_RATIO_MASK 0xff -+#define CORE_CLK_DIV_RATIO_RELOAD BIT(8) -+#define CORE_CLK_DIV_ENABLE_OFFSET 24 -+#define CORE_CLK_DIV_RATIO_OFFSET 0x8 -+ -+struct clk_corediv_desc { -+ unsigned int mask; -+ unsigned int offset; -+ unsigned int fieldbit; -+}; -+ -+struct clk_corediv { -+ struct clk_hw hw; -+ void __iomem *reg; -+ struct clk_corediv_desc desc; -+ spinlock_t lock; -+}; -+ -+static struct clk_onecell_data clk_data; -+ -+static const struct clk_corediv_desc mvebu_corediv_desc[] __initconst = { -+ { .mask = 0x3f, .offset = 8, .fieldbit = 1 }, /* NAND clock */ -+}; -+ -+#define to_corediv_clk(p) container_of(p, struct clk_corediv, hw) -+ -+static int clk_corediv_is_enabled(struct clk_hw *hwclk) -+{ -+ struct clk_corediv *corediv = to_corediv_clk(hwclk); -+ struct clk_corediv_desc *desc = &corediv->desc; -+ u32 enable_mask = BIT(desc->fieldbit) << CORE_CLK_DIV_ENABLE_OFFSET; -+ -+ return !!(readl(corediv->reg) & enable_mask); -+} -+ -+static int clk_corediv_enable(struct clk_hw *hwclk) -+{ -+ struct clk_corediv *corediv = to_corediv_clk(hwclk); -+ struct clk_corediv_desc *desc = &corediv->desc; -+ unsigned long flags = 0; -+ u32 reg; -+ -+ spin_lock_irqsave(&corediv->lock, flags); -+ -+ reg = readl(corediv->reg); -+ reg |= (BIT(desc->fieldbit) << CORE_CLK_DIV_ENABLE_OFFSET); -+ writel(reg, corediv->reg); -+ -+ spin_unlock_irqrestore(&corediv->lock, flags); -+ -+ return 0; -+} -+ -+static void clk_corediv_disable(struct clk_hw *hwclk) -+{ -+ struct clk_corediv *corediv = to_corediv_clk(hwclk); -+ struct clk_corediv_desc *desc = &corediv->desc; -+ unsigned long flags = 0; -+ u32 reg; -+ -+ spin_lock_irqsave(&corediv->lock, flags); -+ -+ reg = readl(corediv->reg); -+ reg &= ~(BIT(desc->fieldbit) << CORE_CLK_DIV_ENABLE_OFFSET); -+ writel(reg, corediv->reg); -+ -+ spin_unlock_irqrestore(&corediv->lock, flags); -+} -+ -+static unsigned long clk_corediv_recalc_rate(struct clk_hw *hwclk, -+ unsigned long parent_rate) -+{ -+ struct clk_corediv *corediv = to_corediv_clk(hwclk); -+ struct clk_corediv_desc *desc = &corediv->desc; -+ u32 reg, div; -+ -+ reg = readl(corediv->reg + CORE_CLK_DIV_RATIO_OFFSET); -+ div = (reg >> desc->offset) & desc->mask; -+ return parent_rate / div; -+} -+ -+static long clk_corediv_round_rate(struct clk_hw *hwclk, unsigned long rate, -+ unsigned long *parent_rate) -+{ -+ /* Valid ratio are 1:4, 1:5, 1:6 and 1:8 */ -+ u32 div; -+ -+ div = *parent_rate / rate; -+ if (div < 4) -+ div = 4; -+ else if (div > 6) -+ div = 8; -+ -+ return *parent_rate / div; -+} -+ -+static int clk_corediv_set_rate(struct clk_hw *hwclk, unsigned long rate, -+ unsigned long parent_rate) -+{ -+ struct clk_corediv *corediv = to_corediv_clk(hwclk); -+ struct clk_corediv_desc *desc = &corediv->desc; -+ unsigned long flags = 0; -+ u32 reg, div; -+ -+ div = parent_rate / rate; -+ -+ spin_lock_irqsave(&corediv->lock, flags); -+ -+ /* Write new divider to the divider ratio register */ -+ reg = readl(corediv->reg + CORE_CLK_DIV_RATIO_OFFSET); -+ reg &= ~(desc->mask << desc->offset); -+ reg |= (div & desc->mask) << desc->offset; -+ writel(reg, corediv->reg + CORE_CLK_DIV_RATIO_OFFSET); -+ -+ /* Set reload-force for this clock */ -+ reg = readl(corediv->reg) | BIT(desc->fieldbit); -+ writel(reg, corediv->reg); -+ -+ /* Now trigger the clock update */ -+ reg = readl(corediv->reg) | CORE_CLK_DIV_RATIO_RELOAD; -+ writel(reg, corediv->reg); -+ -+ /* -+ * Wait for clocks to settle down, and then clear all the -+ * ratios request and the reload request. -+ */ -+ udelay(1000); -+ reg &= ~(CORE_CLK_DIV_RATIO_MASK | CORE_CLK_DIV_RATIO_RELOAD); -+ writel(reg, corediv->reg); -+ udelay(1000); -+ -+ spin_unlock_irqrestore(&corediv->lock, flags); -+ -+ return 0; -+} -+ -+static const struct clk_ops corediv_ops = { -+ .enable = clk_corediv_enable, -+ .disable = clk_corediv_disable, -+ .is_enabled = clk_corediv_is_enabled, -+ .recalc_rate = clk_corediv_recalc_rate, -+ .round_rate = clk_corediv_round_rate, -+ .set_rate = clk_corediv_set_rate, -+}; -+ -+static void __init mvebu_corediv_clk_init(struct device_node *node) -+{ -+ struct clk_init_data init; -+ struct clk_corediv *corediv; -+ struct clk **clks; -+ void __iomem *base; -+ const char *parent_name; -+ const char *clk_name; -+ int i; -+ -+ base = of_iomap(node, 0); -+ if (WARN_ON(!base)) -+ return; -+ -+ parent_name = of_clk_get_parent_name(node, 0); -+ -+ clk_data.clk_num = ARRAY_SIZE(mvebu_corediv_desc); -+ -+ /* clks holds the clock array */ -+ clks = kcalloc(clk_data.clk_num, sizeof(struct clk *), -+ GFP_KERNEL); -+ if (WARN_ON(!clks)) -+ goto err_unmap; -+ /* corediv holds the clock specific array */ -+ corediv = kcalloc(clk_data.clk_num, sizeof(struct clk_corediv), -+ GFP_KERNEL); -+ if (WARN_ON(!corediv)) -+ goto err_free_clks; -+ -+ spin_lock_init(&corediv->lock); -+ -+ for (i = 0; i < clk_data.clk_num; i++) { -+ of_property_read_string_index(node, "clock-output-names", -+ i, &clk_name); -+ init.num_parents = 1; -+ init.parent_names = &parent_name; -+ init.name = clk_name; -+ init.ops = &corediv_ops; -+ init.flags = 0; -+ -+ corediv[i].desc = mvebu_corediv_desc[i]; -+ corediv[i].reg = base; -+ corediv[i].hw.init = &init; -+ -+ clks[i] = clk_register(NULL, &corediv[i].hw); -+ WARN_ON(IS_ERR(clks[i])); -+ } -+ -+ clk_data.clks = clks; -+ of_clk_add_provider(node, of_clk_src_onecell_get, &clk_data); -+ return; -+ -+err_free_clks: -+ kfree(clks); -+err_unmap: -+ iounmap(base); -+} -+CLK_OF_DECLARE(mvebu_corediv_clk, "marvell,armada-370-corediv-clock", -+ mvebu_corediv_clk_init); -- cgit v1.2.3