From 98684d99b25033f01eae0c25110e660620253b82 Mon Sep 17 00:00:00 2001 From: Marko Ratkaj Date: Thu, 13 Jun 2019 16:40:46 +0200 Subject: mvebu: add kernel 4.19 support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Marko Ratkaj [added sfp related patches from Russell King] Signed-off-by: Marek Behún [rebase; rework patches; separate and cleanup kernel configs; add espessobin dts; adjust venom dts] Signed-off-by: Tomasz Maciej Nowak --- ...aardvark-allow-to-specify-link-capability.patch | 43 ++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 target/linux/mvebu/patches-4.19/527-PCI-aardvark-allow-to-specify-link-capability.patch (limited to 'target/linux/mvebu/patches-4.19/527-PCI-aardvark-allow-to-specify-link-capability.patch') diff --git a/target/linux/mvebu/patches-4.19/527-PCI-aardvark-allow-to-specify-link-capability.patch b/target/linux/mvebu/patches-4.19/527-PCI-aardvark-allow-to-specify-link-capability.patch new file mode 100644 index 0000000000..0ac3476147 --- /dev/null +++ b/target/linux/mvebu/patches-4.19/527-PCI-aardvark-allow-to-specify-link-capability.patch @@ -0,0 +1,43 @@ +From f70b629e488cc3f2a325ac35476f4f7ae502c5d0 Mon Sep 17 00:00:00 2001 +From: Tomasz Maciej Nowak +Date: Thu, 14 Jun 2018 14:24:40 +0200 +Subject: [PATCH 1/2] PCI: aardvark: allow to specify link capability + +Use DT of_pci_get_max_link_speed() facility to allow specifying link +capability. If none or unspecified value is given it falls back to gen2, +which is default for Armada 3700 SoC. + +Signed-off-by: Tomasz Maciej Nowak +--- + drivers/pci/controller/pci-aardvark.c | 11 +++++++++-- + 1 file changed, 9 insertions(+), 2 deletions(-) + +--- a/drivers/pci/controller/pci-aardvark.c ++++ b/drivers/pci/controller/pci-aardvark.c +@@ -233,6 +233,8 @@ static int advk_pcie_wait_for_link(struc + + static void advk_pcie_setup_hw(struct advk_pcie *pcie) + { ++ struct device *dev = &pcie->pdev->dev; ++ struct device_node *node = dev->of_node; + u32 reg; + + /* Set to Direct mode */ +@@ -267,10 +269,15 @@ static void advk_pcie_setup_hw(struct ad + PCIE_CORE_CTRL2_TD_ENABLE; + advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); + +- /* Set GEN2 */ ++ /* Set GEN */ + reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); + reg &= ~PCIE_GEN_SEL_MSK; +- reg |= SPEED_GEN_2; ++ if (of_pci_get_max_link_speed(node) == 1) ++ reg |= SPEED_GEN_1; ++ else if (of_pci_get_max_link_speed(node) == 3) ++ reg |= SPEED_GEN_3; ++ else ++ reg |= SPEED_GEN_2; + advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); + + /* Set lane X1 */ -- cgit v1.2.3