From bc04cf780e95aa292695f064dfaeea08df8c9b84 Mon Sep 17 00:00:00 2001 From: Mathias Kresin Date: Sun, 13 May 2018 13:02:30 +0200 Subject: ath79: ar724x: fix pll settings Add the syscon compatible, otherwise used functions like syscon_regmap_lookup_by_phandle() will return an error and setting the ethernet pll data wont work at all. Fix the pll register width. Writing to registers out of the range via syscon isn't possible and returns an error. On ar7242 the last pll register - Current Audio Modulation Logic Output - is at 0x1805003c. Signed-off-by: Mathias Kresin --- target/linux/ath79/dts/ar724x.dtsi | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'target') diff --git a/target/linux/ath79/dts/ar724x.dtsi b/target/linux/ath79/dts/ar724x.dtsi index 4108745113..fe1b4eb681 100644 --- a/target/linux/ath79/dts/ar724x.dtsi +++ b/target/linux/ath79/dts/ar724x.dtsi @@ -65,9 +65,8 @@ }; pll: pll-controller@18050000 { - compatible = "qca,ar7240-pll", - "qca,ar7240-pll"; - reg = <0x18050000 0x20>; + compatible = "qca,ar7240-pll", "syscon"; + reg = <0x18050000 0x3c>; clock-names = "ref"; /* The board must provides the ref clock */ -- cgit v1.2.3