From 88c07c655262ea63c342e7c9df67cfe36fe3e5df Mon Sep 17 00:00:00 2001 From: Joseph Benden Date: Wed, 8 May 2019 11:52:56 -0700 Subject: toolchain: Add GCC 9.1.0 release Most of the patches are copied over from GCC 8.3. The following patches are backported from the GCC 9.X development branch: toolchain/gcc/patches/9.1.0/970-recompute-dom-fast-queries-before-vn.patch toolchain/gcc/patches/9.1.0/975-g++-ICE-with-generic-lambda.patch The specs file changed with gcc 9, now it contains "%@{L*}" instead of "%{L*}" in older GCC versions. Signed-off-by: Joseph Benden --- .../gcc/patches/9.1.0/110-Fix-MIPS-PR-84790.patch | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 toolchain/gcc/patches/9.1.0/110-Fix-MIPS-PR-84790.patch (limited to 'toolchain/gcc/patches/9.1.0/110-Fix-MIPS-PR-84790.patch') diff --git a/toolchain/gcc/patches/9.1.0/110-Fix-MIPS-PR-84790.patch b/toolchain/gcc/patches/9.1.0/110-Fix-MIPS-PR-84790.patch new file mode 100644 index 0000000000..c7e60e3157 --- /dev/null +++ b/toolchain/gcc/patches/9.1.0/110-Fix-MIPS-PR-84790.patch @@ -0,0 +1,20 @@ +Fix https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84790. +MIPS16 functions have a static assembler prologue which clobbers +registers v0 and v1. Add these register clobbers to function call +instructions. + +--- a/gcc/config/mips/mips.c ++++ b/gcc/config/mips/mips.c +@@ -3131,6 +3131,12 @@ mips_emit_call_insn (rtx pattern, rtx or + emit_insn (gen_update_got_version ()); + } + ++ if (TARGET_MIPS16 && TARGET_USE_GOT) ++ { ++ clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn), MIPS16_PIC_TEMP); ++ clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn), MIPS_PROLOGUE_TEMP (word_mode)); ++ } ++ + if (TARGET_MIPS16 + && TARGET_EXPLICIT_RELOCS + && TARGET_CALL_CLOBBERED_GP) -- cgit v1.2.3