From 98f63141190ac02c58b78d58f771bd263c61d756 Mon Sep 17 00:00:00 2001 From: Jonas Gorski Date: Sat, 7 Dec 2013 17:14:17 +0100 Subject: [PATCH 48/56] MIPS: BCM63XX: add support for BCM63268 Signed-off-by: Jonas Gorski --- arch/mips/bcm63xx/Kconfig | 5 + arch/mips/bcm63xx/boards/board_bcm963xx.c | 2 +- arch/mips/bcm63xx/clk.c | 25 ++++- arch/mips/bcm63xx/cpu.c | 59 +++++++++- arch/mips/bcm63xx/dev-flash.c | 6 + arch/mips/bcm63xx/dev-spi.c | 4 +- arch/mips/bcm63xx/irq.c | 20 +++- arch/mips/bcm63xx/reset.c | 21 ++++ arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 130 ++++++++++++++++++++++ arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h | 2 + arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 79 +++++++++++++ arch/mips/include/asm/mach-bcm63xx/ioremap.h | 1 + 12 files changed, 342 insertions(+), 12 deletions(-) --- a/arch/mips/bcm63xx/Kconfig +++ b/arch/mips/bcm63xx/Kconfig @@ -61,6 +61,11 @@ config BCM63XX_CPU_6368 select HAVE_PCI select BCM63XX_OHCI select BCM63XX_EHCI + +config BCM63XX_CPU_63268 + bool "support 63268 CPU" + select SYS_HAS_CPU_BMIPS4350 + select HAVE_PCI endmenu source "arch/mips/bcm63xx/boards/Kconfig" --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c @@ -694,7 +694,7 @@ void __init board_prom_init(void) /* read base address of boot chip select (0) * 6328/6362 do not have MPI but boot from a fixed address */ - if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) { + if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) { val = 0x18000000; } else { val = bcm_mpi_readl(MPI_CSBASE_REG(0)); --- a/arch/mips/bcm63xx/clk.c +++ b/arch/mips/bcm63xx/clk.c @@ -169,6 +169,8 @@ static void enetsw_set(struct clk *clk, clk_disable_unlocked(&clk_swpkt_sar); } bcm_hwclock_set(CKCTL_6368_ROBOSW_EN, enable); + } else if (BCMCPU_IS_63268()) { + bcm_hwclock_set(CKCTL_63268_ROBOSW_EN, enable); } else { return; } @@ -214,6 +216,8 @@ static void usbh_set(struct clk *clk, in bcm_hwclock_set(CKCTL_6362_USBH_EN, enable); else if (BCMCPU_IS_6368()) bcm_hwclock_set(CKCTL_6368_USBH_EN, enable); + else if (BCMCPU_IS_63268()) + bcm_hwclock_set(CKCTL_63268_USBH_EN, enable); else return; @@ -236,6 +240,8 @@ static void usbd_set(struct clk *clk, in bcm_hwclock_set(CKCTL_6362_USBD_EN, enable); else if (BCMCPU_IS_6368()) bcm_hwclock_set(CKCTL_6368_USBD_EN, enable); + else if (BCMCPU_IS_63268()) + bcm_hwclock_set(CKCTL_63268_USBD_EN, enable); else return; @@ -262,9 +268,13 @@ static void spi_set(struct clk *clk, int mask = CKCTL_6358_SPI_EN; else if (BCMCPU_IS_6362()) mask = CKCTL_6362_SPI_EN; - else - /* BCMCPU_IS_6368 */ + else if (BCMCPU_IS_6368()) mask = CKCTL_6368_SPI_EN; + else if (BCMCPU_IS_63268()) + mask = CKCTL_63268_SPI_EN; + else + return; + bcm_hwclock_set(mask, enable); } @@ -283,6 +293,8 @@ static void hsspi_set(struct clk *clk, i mask = CKCTL_6328_HSSPI_EN; else if (BCMCPU_IS_6362()) mask = CKCTL_6362_HSSPI_EN; + else if (BCMCPU_IS_63268()) + mask = CKCTL_63268_HSSPI_EN; else return; @@ -352,6 +364,8 @@ static void pcie_set(struct clk *clk, in bcm_hwclock_set(CKCTL_6328_PCIE_EN, enable); else if (BCMCPU_IS_6362()) bcm_hwclock_set(CKCTL_6362_PCIE_EN, enable); + else if (BCMCPU_IS_63268()) + bcm_hwclock_set(CKCTL_63268_PCIE_EN, enable); } static struct clk clk_pcie = { @@ -536,6 +550,21 @@ static struct clk_lookup bcm6368_clks[] CLKDEV_INIT(NULL, "ipsec", &clk_ipsec), }; +static struct clk_lookup bcm63268_clks[] = { + /* fixed rate clocks */ + CLKDEV_INIT(NULL, "periph", &clk_periph), + CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph), + CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph), + CLKDEV_INIT("bcm63xx-hsspi.0", "pll", &clk_hsspi_pll), + /* gated clocks */ + CLKDEV_INIT(NULL, "enetsw", &clk_enetsw), + CLKDEV_INIT(NULL, "usbh", &clk_usbh), + CLKDEV_INIT(NULL, "usbd", &clk_usbd), + CLKDEV_INIT(NULL, "spi", &clk_spi), + CLKDEV_INIT(NULL, "hsspi", &clk_hsspi), + CLKDEV_INIT(NULL, "pcie", &clk_pcie), +}; + #define HSSPI_PLL_HZ_6328 133333333 #define HSSPI_PLL_HZ_6362 400000000 @@ -568,6 +597,10 @@ static int __init bcm63xx_clk_init(void) case BCM6368_CPU_ID: clkdev_add_table(bcm6368_clks, ARRAY_SIZE(bcm6368_clks)); break; + case BCM63268_CPU_ID: + clk_hsspi_pll.rate = HSSPI_PLL_HZ_6362; + clkdev_add_table(bcm63268_clks, ARRAY_SIZE(bcm63268_clks)); + break; } return 0; --- a/arch/mips/bcm63xx/cpu.c +++ b/arch/mips/bcm63xx/cpu.c @@ -101,6 +101,15 @@ static const int bcm6368_irqs[] = { }; +static const unsigned long bcm63268_regs_base[] = { + __GEN_CPU_REGS_TABLE(63268) +}; + +static const int bcm63268_irqs[] = { + __GEN_CPU_IRQ_TABLE(63268) + +}; + u32 bcm63xx_get_cpu_variant(void) { return bcm63xx_cpu_variant; @@ -253,6 +262,27 @@ static unsigned int detect_cpu_clock(voi return (((64 * 1000000) / p1) * p2 * ndiv) / m1; } + case BCM63268_CPU_ID: + { + unsigned int tmp, mips_pll_fcvo; + + tmp = bcm_misc_readl(MISC_STRAPBUS_63268_REG); + mips_pll_fcvo = (tmp & STRAPBUS_63268_FCVO_MASK) >> + STRAPBUS_63268_FCVO_SHIFT; + switch (mips_pll_fcvo) { + case 0x3: + case 0xe: + return 320000000; + case 0xa: + return 333000000; + case 0x2: + case 0xb: + case 0xf: + return 400000000; + default: + return 0; + } + } default: panic("Failed to detect clock for CPU with id=%04X\n", cpu_id); @@ -267,7 +297,7 @@ static unsigned int detect_memory_size(v unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0; u32 val; - if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) + if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) return bcm_ddr_readl(DDR_CSEND_REG) << 24; if (BCMCPU_IS_6345()) { @@ -305,6 +335,7 @@ void __init bcm63xx_cpu_init(void) unsigned int tmp; unsigned int cpu = smp_processor_id(); u32 chipid_reg; + bool long_chipid = false; u8 __maybe_unused varid = 0; /* soc registers location depends on cpu type */ @@ -326,6 +357,9 @@ void __init bcm63xx_cpu_init(void) case 0x10: chipid_reg = BCM_6345_PERF_BASE; break; + case 0x80: + long_chipid = true; + /* fall-through */ default: chipid_reg = BCM_6368_PERF_BASE; break; @@ -333,6 +367,7 @@ void __init bcm63xx_cpu_init(void) break; } + /* * really early to panic, but delaying panic would not help since we * will never get any working console @@ -342,10 +377,17 @@ void __init bcm63xx_cpu_init(void) /* read out CPU type */ tmp = bcm_readl(chipid_reg); - bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT; - bcm63xx_cpu_variant = bcm63xx_cpu_id; + + if (long_chipid) { + bcm63xx_cpu_id = tmp & REV_LONG_CHIPID_MASK; + bcm63xx_cpu_id >>= REV_LONG_CHIPID_SHIFT; + } else { + bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT; + varid = (tmp & REV_VARID_MASK) >> REV_VARID_SHIFT; + } + bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT; - varid = (tmp & REV_VARID_MASK) >> REV_VARID_SHIFT; + bcm63xx_cpu_variant = bcm63xx_cpu_id; switch (bcm63xx_cpu_id) { case BCM3368_CPU_ID: @@ -400,6 +442,16 @@ void __init bcm63xx_cpu_init(void) /* BCM6369 is a BCM6368 without xDSL, so treat it the same */ bcm63xx_cpu_id = BCM6368_CPU_ID; break; + case BCM63167_CPU_ID: + case BCM63168_CPU_ID: + case BCM63169_CPU_ID: + case BCM63268_CPU_ID: + case BCM63269_CPU_ID: + bcm63xx_regs_base = bcm63268_regs_base; + bcm63xx_irqs = bcm63268_irqs; + + bcm63xx_cpu_id = BCM63268_CPU_ID; + break; default: panic("unsupported broadcom CPU %x", bcm63xx_cpu_id); break; --- a/arch/mips/bcm63xx/dev-flash.c +++ b/arch/mips/bcm63xx/dev-flash.c @@ -84,6 +84,12 @@ static int __init bcm63xx_detect_flash_t return BCM63XX_FLASH_TYPE_SERIAL; else return BCM63XX_FLASH_TYPE_NAND; + case BCM63268_CPU_ID: + val = bcm_misc_readl(MISC_STRAPBUS_63268_REG); + if (val & STRAPBUS_63268_BOOT_SEL_SERIAL) + return BCM63XX_FLASH_TYPE_SERIAL; + else + return BCM63XX_FLASH_TYPE_NAND; case BCM6368_CPU_ID: val = bcm_gpio_readl(GPIO_STRAPBUS_REG); switch (val & STRAPBUS_6368_BOOT_SEL_MASK) { --- a/arch/mips/bcm63xx/dev-spi.c +++ b/arch/mips/bcm63xx/dev-spi.c @@ -51,7 +51,7 @@ int __init bcm63xx_spi_register(void) } if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6362() || - BCMCPU_IS_6368()) { + BCMCPU_IS_6368() || BCMCPU_IS_63268()) { bcm63xx_spi_device.name = "bcm6358-spi", spi_resources[0].end += BCM_6358_RSET_SPI_SIZE - 1; } --- a/arch/mips/bcm63xx/irq.c +++ b/arch/mips/bcm63xx/irq.c @@ -149,6 +149,20 @@ void __init arch_init_irq(void) ext_irqs[5] = BCM_6368_EXT_IRQ5; ext_shift = 4; break; + case BCM63268_CPU_ID: + periph_bases[0] += PERF_IRQMASK_63268_REG(0); + periph_bases[1] += PERF_IRQMASK_63268_REG(1); + periph_irq_count = 2; + periph_width = 4; + + ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_63268; + ext_irq_count = 4; + ext_irqs[0] = BCM_63268_EXT_IRQ0; + ext_irqs[1] = BCM_63268_EXT_IRQ1; + ext_irqs[2] = BCM_63268_EXT_IRQ2; + ext_irqs[3] = BCM_63268_EXT_IRQ3; + ext_shift = 4; + break; default: BUG(); } --- a/arch/mips/bcm63xx/reset.c +++ b/arch/mips/bcm63xx/reset.c @@ -126,6 +126,20 @@ #define BCM6368_RESET_PCIE 0 #define BCM6368_RESET_PCIE_EXT 0 +#define BCM63268_RESET_SPI SOFTRESET_63268_SPI_MASK +#define BCM63268_RESET_ENET 0 +#define BCM63268_RESET_USBH SOFTRESET_63268_USBH_MASK +#define BCM63268_RESET_USBD SOFTRESET_63268_USBS_MASK +#define BCM63268_RESET_DSL 0 +#define BCM63268_RESET_SAR SOFTRESET_63268_SAR_MASK +#define BCM63268_RESET_EPHY 0 +#define BCM63268_RESET_ENETSW SOFTRESET_63268_ENETSW_MASK +#define BCM63268_RESET_PCM SOFTRESET_63268_PCM_MASK +#define BCM63268_RESET_MPI 0 +#define BCM63268_RESET_PCIE (SOFTRESET_63268_PCIE_MASK | \ + SOFTRESET_63268_PCIE_CORE_MASK) +#define BCM63268_RESET_PCIE_EXT SOFTRESET_63268_PCIE_EXT_MASK + /* * core reset bits */ @@ -157,6 +171,10 @@ static const u32 bcm6368_reset_bits[] = __GEN_RESET_BITS_TABLE(6368) }; +static const u32 bcm63268_reset_bits[] = { + __GEN_RESET_BITS_TABLE(63268) +}; + const u32 *bcm63xx_reset_bits; static int reset_reg; @@ -183,6 +201,9 @@ static int __init bcm63xx_reset_bits_ini } else if (BCMCPU_IS_6368()) { reset_reg = PERF_SOFTRESET_6368_REG; bcm63xx_reset_bits = bcm6368_reset_bits; + } else if (BCMCPU_IS_63268()) { + reset_reg = PERF_SOFTRESET_63268_REG; + bcm63xx_reset_bits = bcm63268_reset_bits; } return 0; --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h @@ -22,6 +22,11 @@ #define BCM6362_CPU_ID 0x6362 #define BCM6368_CPU_ID 0x6368 #define BCM6369_CPU_ID 0x6369 +#define BCM63167_CPU_ID 0x63167 +#define BCM63168_CPU_ID 0x63168 +#define BCM63169_CPU_ID 0x63169 +#define BCM63268_CPU_ID 0x63268 +#define BCM63269_CPU_ID 0x63269 void __init bcm63xx_cpu_init(void); u32 bcm63xx_get_cpu_variant(void); @@ -62,6 +67,10 @@ static inline u32 __pure __bcm63xx_get_c #ifdef CONFIG_BCM63XX_CPU_6368 case BCM6368_CPU_ID: #endif + +#ifdef CONFIG_BCM63XX_CPU_63268 + case BCM63268_CPU_ID: +#endif break; default: unreachable(); @@ -87,6 +96,7 @@ static inline u32 __pure bcm63xx_get_cpu #define BCMCPU_IS_6358() (bcm63xx_get_cpu_id() == BCM6358_CPU_ID) #define BCMCPU_IS_6362() (bcm63xx_get_cpu_id() == BCM6362_CPU_ID) #define BCMCPU_IS_6368() (bcm63xx_get_cpu_id() == BCM6368_CPU_ID) +#define BCMCPU_IS_63268() (bcm63xx_get_cpu_id() == BCM63268_CPU_ID) #define BCMCPU_VARIANT_IS_3368() \ (bcm63xx_get_cpu_variant() == BCM3368_CPU_ID) @@ -110,6 +120,16 @@ static inline u32 __pure bcm63xx_get_cpu (bcm63xx_get_cpu_variant() == BCM6368_CPU_ID) #define BCMCPU_VARIANT_IS_6369() \ (bcm63xx_get_cpu_variant() == BCM6369_CPU_ID) +#define BCMCPU_VARIANT_IS_63167() \ + (bcm63xx_get_cpu_variant() == BCM63167_CPU_ID) +#define BCMCPU_VARIANT_IS_63168() \ + (bcm63xx_get_cpu_variant() == BCM63168_CPU_ID) +#define BCMCPU_VARIANT_IS_63169() \ + (bcm63xx_get_cpu_variant() == BCM63169_CPU_ID) +#define BCMCPU_VARIANT_IS_63268() \ + (bcm63xx_get_cpu_variant() == BCM63268_CPU_ID) +#define BCMCPU_VARIANT_IS_63269() \ + (bcm63xx_get_cpu_variant() == BCM63269_CPU_ID) /* * While registers sets are (mostly) the same across 63xx CPU, base @@ -574,6 +594,52 @@ enum bcm63xx_regs_set { #define BCM_6368_RNG_BASE (0xb0004180) #define BCM_6368_MISC_BASE (0xdeadbeef) +/* + * 63268 register sets base address + */ +#define BCM_63268_DSL_LMEM_BASE (0xdeadbeef) +#define BCM_63268_PERF_BASE (0xb0000000) +#define BCM_63268_TIMER_BASE (0xb0000080) +#define BCM_63268_WDT_BASE (0xb000009c) +#define BCM_63268_UART0_BASE (0xb0000180) +#define BCM_63268_UART1_BASE (0xb00001a0) +#define BCM_63268_GPIO_BASE (0xb00000c0) +#define BCM_63268_SPI_BASE (0xb0000800) +#define BCM_63268_HSSPI_BASE (0xb0001000) +#define BCM_63268_UDC0_BASE (0xdeadbeef) +#define BCM_63268_USBDMA_BASE (0xb000c800) +#define BCM_63268_OHCI0_BASE (0xb0002600) +#define BCM_63268_OHCI_PRIV_BASE (0xdeadbeef) +#define BCM_63268_USBH_PRIV_BASE (0xb0002700) +#define BCM_63268_USBD_BASE (0xb0002400) +#define BCM_63268_MPI_BASE (0xdeadbeef) +#define BCM_63268_PCMCIA_BASE (0xdeadbeef) +#define BCM_63268_PCIE_BASE (0xb06e0000) +#define BCM_63268_SDRAM_REGS_BASE (0xdeadbeef) +#define BCM_63268_DSL_BASE (0xdeadbeef) +#define BCM_63268_UBUS_BASE (0xdeadbeef) +#define BCM_63268_ENET0_BASE (0xdeadbeef) +#define BCM_63268_ENET1_BASE (0xdeadbeef) +#define BCM_63268_ENETDMA_BASE (0xb000d800) +#define BCM_63268_ENETDMAC_BASE (0xb000da00) +#define BCM_63268_ENETDMAS_BASE (0xb000dc00) +#define BCM_63268_ENETSW_BASE (0xb0700000) +#define BCM_63268_EHCI0_BASE (0xb0002500) +#define BCM_63268_SDRAM_BASE (0xdeadbeef) +#define BCM_63268_MEMC_BASE (0xdeadbeef) +#define BCM_63268_DDR_BASE (0xb0003000) +#define BCM_63268_M2M_BASE (0xdeadbeef) +#define BCM_63268_ATM_BASE (0xdeadbeef) +#define BCM_63268_XTM_BASE (0xb0007000) +#define BCM_63268_XTMDMA_BASE (0xb000b800) +#define BCM_63268_XTMDMAC_BASE (0xdeadbeef) +#define BCM_63268_XTMDMAS_BASE (0xdeadbeef) +#define BCM_63268_PCM_BASE (0xb000b000) +#define BCM_63268_PCMDMA_BASE (0xb000b800) +#define BCM_63268_PCMDMAC_BASE (0xdeadbeef) +#define BCM_63268_PCMDMAS_BASE (0xdeadbeef) +#define BCM_63268_RNG_BASE (0xdeadbeef) +#define BCM_63268_MISC_BASE (0xb0001800) extern const unsigned long *bcm63xx_regs_base; @@ -1042,6 +1108,73 @@ enum bcm63xx_irq { #define BCM_6368_EXT_IRQ4 (IRQ_INTERNAL_BASE + 24) #define BCM_6368_EXT_IRQ5 (IRQ_INTERNAL_BASE + 25) +/* + * 63268 irqs + */ +#define BCM_63268_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32) +#define BCM_63268_VERY_HIGH_IRQ_BASE (BCM_63268_HIGH_IRQ_BASE + 32) + +#define BCM_63268_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) +#define BCM_63268_SPI_IRQ (BCM_63268_VERY_HIGH_IRQ_BASE + 16) +#define BCM_63268_UART0_IRQ (IRQ_INTERNAL_BASE + 5) +#define BCM_63268_UART1_IRQ (BCM_63268_HIGH_IRQ_BASE + 2) +#define BCM_63268_DSL_IRQ (IRQ_INTERNAL_BASE + 23) +#define BCM_63268_UDC0_IRQ 0 +#define BCM_63268_ENET0_IRQ 0 +#define BCM_63268_ENET1_IRQ 0 +#define BCM_63268_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 13) +#define BCM_63268_HSSPI_IRQ (IRQ_INTERNAL_BASE + 6) +#define BCM_63268_OHCI0_IRQ (IRQ_INTERNAL_BASE + 9) +#define BCM_63268_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10) +#define BCM_63268_USBD_IRQ (IRQ_INTERNAL_BASE + 11) +#define BCM_63268_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 19) +#define BCM_63268_USBD_TXDMA0_IRQ (BCM_63268_HIGH_IRQ_BASE + 4) +#define BCM_63268_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 20) +#define BCM_63268_USBD_TXDMA1_IRQ (BCM_63268_HIGH_IRQ_BASE + 5) +#define BCM_63268_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 21) +#define BCM_63268_USBD_TXDMA2_IRQ (BCM_63268_HIGH_IRQ_BASE + 6) +#define BCM_63268_PCMCIA_IRQ 0 +#define BCM_63268_ENET0_RXDMA_IRQ 0 +#define BCM_63268_ENET0_TXDMA_IRQ 0 +#define BCM_63268_ENET1_RXDMA_IRQ 0 +#define BCM_63268_ENET1_TXDMA_IRQ 0 +#define BCM_63268_PCI_IRQ (BCM_63268_HIGH_IRQ_BASE + 8) +#define BCM_63268_ATM_IRQ 0 +#define BCM_63268_ENETSW_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 1) +#define BCM_63268_ENETSW_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 2) +#define BCM_63268_ENETSW_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 3) +#define BCM_63268_ENETSW_RXDMA3_IRQ (IRQ_INTERNAL_BASE + 4) +#define BCM_63268_ENETSW_TXDMA0_IRQ (BCM_63268_VERY_HIGH_IRQ_BASE + 0) +#define BCM_63268_ENETSW_TXDMA1_IRQ (BCM_63268_VERY_HIGH_IRQ_BASE + 1) +#define BCM_63268_ENETSW_TXDMA2_IRQ (BCM_63268_VERY_HIGH_IRQ_BASE + 2) +#define BCM_63268_ENETSW_TXDMA3_IRQ (BCM_63268_VERY_HIGH_IRQ_BASE + 3) +#define BCM_63268_XTM_IRQ (BCM_63268_HIGH_IRQ_BASE + 17) +#define BCM_63268_XTM_DMA0_IRQ (IRQ_INTERNAL_BASE + 26) + +#define BCM_63268_RING_OSC_IRQ (BCM_63268_HIGH_IRQ_BASE + 20) +#define BCM_63268_WLAN_GPIO_IRQ (BCM_63268_HIGH_IRQ_BASE + 3) +#define BCM_63268_WLAN_IRQ (IRQ_INTERNAL_BASE + 7) +#define BCM_63268_IPSEC_IRQ (IRQ_INTERNAL_BASE + 8) +#define BCM_63268_NAND_IRQ (BCM_63268_HIGH_IRQ_BASE + 18) +#define BCM_63268_PCM_IRQ (IRQ_INTERNAL_BASE + 13) +#define BCM_63268_DG_IRQ (IRQ_INTERNAL_BASE + 15) +#define BCM_63268_EPHY_ENERGY0_IRQ (IRQ_INTERNAL_BASE + 16) +#define BCM_63268_EPHY_ENERGY1_IRQ (IRQ_INTERNAL_BASE + 17) +#define BCM_63268_EPHY_ENERGY2_IRQ (IRQ_INTERNAL_BASE + 18) +#define BCM_63268_EPHY_ENERGY3_IRQ (IRQ_INTERNAL_BASE + 19) +#define BCM_63268_IPSEC_DMA0_IRQ (IRQ_INTERNAL_BASE + 22) +#define BCM_63268_IPSEC_DMA1_IRQ (BCM_63268_HIGH_IRQ_BASE + 7) +#define BCM_63268_FAP0_IRQ (IRQ_INTERNAL_BASE + 24) +#define BCM_63268_FAP1_IRQ (IRQ_INTERNAL_BASE + 25) +#define BCM_63268_PCM_DMA0_IRQ (BCM_63268_HIGH_IRQ_BASE + 10) +#define BCM_63268_PCM_DMA1_IRQ (BCM_63268_HIGH_IRQ_BASE + 11) +#define BCM_63268_DECT0_IRQ (BCM_63268_HIGH_IRQ_BASE + 0) +#define BCM_63268_DECT1_IRQ (BCM_63268_HIGH_IRQ_BASE + 1) +#define BCM_63268_EXT_IRQ0 (BCM_63268_HIGH_IRQ_BASE + 12) +#define BCM_63268_EXT_IRQ1 (BCM_63268_HIGH_IRQ_BASE + 13) +#define BCM_63268_EXT_IRQ2 (BCM_63268_HIGH_IRQ_BASE + 14) +#define BCM_63268_EXT_IRQ3 (BCM_63268_HIGH_IRQ_BASE + 15) + extern const int *bcm63xx_irqs; #define __GEN_CPU_IRQ_TABLE(__cpu) \ --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h @@ -23,6 +23,8 @@ static inline unsigned long bcm63xx_gpio return 48; case BCM6368_CPU_ID: return 38; + case BCM63268_CPU_ID: + return 52; case BCM6348_CPU_ID: default: return 37; --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h @@ -10,6 +10,8 @@ #define PERF_REV_REG 0x0 #define REV_CHIPID_SHIFT 16 #define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT) +#define REV_LONG_CHIPID_SHIFT 12 +#define REV_LONG_CHIPID_MASK (0xfffff << REV_LONG_CHIPID_SHIFT) #define REV_VARID_SHIFT 12 #define REV_VARID_MASK (0xf << REV_VARID_SHIFT) #define REV_REVID_SHIFT 0 @@ -212,6 +214,52 @@ CKCTL_6368_NAND_EN | \ CKCTL_6368_IPSEC_EN) +#define CKCTL_63268_DISABLE_GLESS (1 << 0) +#define CKCTL_63268_VDSL_QPROC_EN (1 << 1) +#define CKCTL_63268_VDSL_AFE_EN (1 << 2) +#define CKCTL_63268_VDSL_EN (1 << 3) +#define CKCTL_63268_MIPS_EN (1 << 4) +#define CKCTL_63268_WLAN_OCP_EN (1 << 5) +#define CKCTL_63268_DECT_EN (1 << 6) +#define CKCTL_63268_FAP0_EN (1 << 7) +#define CKCTL_63268_FAP1_EN (1 << 8) +#define CKCTL_63268_SAR_EN (1 << 9) +#define CKCTL_63268_ROBOSW_EN (1 << 10) +#define CKCTL_63268_PCM_EN (1 << 11) +#define CKCTL_63268_USBD_EN (1 << 12) +#define CKCTL_63268_USBH_EN (1 << 13) +#define CKCTL_63268_IPSEC_EN (1 << 14) +#define CKCTL_63268_SPI_EN (1 << 15) +#define CKCTL_63268_HSSPI_EN (1 << 16) +#define CKCTL_63268_PCIE_EN (1 << 17) +#define CKCTL_63268_PHYMIPS_EN (1 << 18) +#define CKCTL_63268_GMAC_EN (1 << 19) +#define CKCTL_63268_NAND_EN (1 << 20) +#define CKCTL_63268_TBUS_EN (1 << 27) +#define CKCTL_63268_ROBOSW250_EN (1 << 31) + +#define CKCTL_63268_ALL_SAFE_EN (CKCTL_63268_VDSL_QPROC_EN | \ + CKCTL_63268_VDSL_AFE_EN | \ + CKCTL_63268_VDSL_EN | \ + CKCTL_63268_WLAN_OCP_EN | \ + CKCTL_63268_DECT_EN | \ + CKCTL_63268_FAP0_EN | \ + CKCTL_63268_FAP1_EN | \ + CKCTL_63268_SAR_EN | \ + CKCTL_63268_ROBOSW_EN | \ + CKCTL_63268_PCM_EN | \ + CKCTL_63268_USBD_EN | \ + CKCTL_63268_USBH_EN | \ + CKCTL_63268_IPSEC_EN | \ + CKCTL_63268_SPI_EN | \ + CKCTL_63268_HSSPI_EN | \ + CKCTL_63268_PCIE_EN | \ + CKCTL_63268_PHYMIPS_EN | \ + CKCTL_63268_GMAC_EN | \ + CKCTL_63268_NAND_EN | \ + CKCTL_63268_TBUS_EN | \ + CKCTL_63268_ROBOSW250_EN) + /* System PLL Control register */ #define PERF_SYS_PLL_CTL_REG 0x8 #define SYS_PLL_SOFT_RESET 0x1 @@ -225,6 +273,7 @@ #define PERF_IRQMASK_6358_REG(x) (0xc + (x) * 0x2c) #define PERF_IRQMASK_6362_REG(x) (0x20 + (x) * 0x10) #define PERF_IRQMASK_6368_REG(x) (0x20 + (x) * 0x10) +#define PERF_IRQMASK_63268_REG(x) (0x20 + (x) * 0x20) /* Interrupt Status register */ #define PERF_IRQSTAT_3368_REG 0x10 @@ -235,6 +284,7 @@ #define PERF_IRQSTAT_6358_REG(x) (0x10 + (x) * 0x2c) #define PERF_IRQSTAT_6362_REG(x) (0x28 + (x) * 0x10) #define PERF_IRQSTAT_6368_REG(x) (0x28 + (x) * 0x10) +#define PERF_IRQSTAT_63268_REG(x) (0x30 + (x) * 0x20) /* External Interrupt Configuration register */ #define PERF_EXTIRQ_CFG_REG_3368 0x14 @@ -245,6 +295,7 @@ #define PERF_EXTIRQ_CFG_REG_6358 0x14 #define PERF_EXTIRQ_CFG_REG_6362 0x18 #define PERF_EXTIRQ_CFG_REG_6368 0x18 +#define PERF_EXTIRQ_CFG_REG_63268 0x18 #define PERF_EXTIRQ_CFG_REG2_6358 0x1c #define PERF_EXTIRQ_CFG_REG2_6368 0x1c @@ -275,6 +326,7 @@ #define PERF_SOFTRESET_6358_REG 0x34 #define PERF_SOFTRESET_6362_REG 0x10 #define PERF_SOFTRESET_6368_REG 0x10 +#define PERF_SOFTRESET_63268_REG 0x10 #define SOFTRESET_3368_SPI_MASK (1 << 0) #define SOFTRESET_3368_ENET_MASK (1 << 2) @@ -368,6 +420,26 @@ #define SOFTRESET_6368_USBH_MASK (1 << 12) #define SOFTRESET_6368_PCM_MASK (1 << 13) +#define SOFTRESET_63268_SPI_MASK (1 << 0) +#define SOFTRESET_63268_IPSEC_MASK (1 << 1) +#define SOFTRESET_63268_EPHY_MASK (1 << 2) +#define SOFTRESET_63268_SAR_MASK (1 << 3) +#define SOFTRESET_63268_ENETSW_MASK (1 << 4) +#define SOFTRESET_63268_USBS_MASK (1 << 5) +#define SOFTRESET_63268_USBH_MASK (1 << 6) +#define SOFTRESET_63268_PCM_MASK (1 << 7) +#define SOFTRESET_63268_PCIE_CORE_MASK (1 << 8) +#define SOFTRESET_63268_PCIE_MASK (1 << 9) +#define SOFTRESET_63268_PCIE_EXT_MASK (1 << 10) +#define SOFTRESET_63268_WLAN_SHIM_MASK (1 << 11) +#define SOFTRESET_63268_DDR_PHY_MASK (1 << 12) +#define SOFTRESET_63268_FAP0_MASK (1 << 13) +#define SOFTRESET_63268_WLAN_UBUS_MASK (1 << 14) +#define SOFTRESET_63268_DECT_MASK (1 << 15) +#define SOFTRESET_63268_FAP1_MASK (1 << 16) +#define SOFTRESET_63268_PCIE_HARD_MASK (1 << 17) +#define SOFTRESET_63268_GPHY_MASK (1 << 18) + /* MIPS PLL control register */ #define PERF_MIPSPLLCTL_REG 0x34 #define MIPSPLLCTL_N1_SHIFT 20 @@ -1367,6 +1439,13 @@ #define STRAPBUS_6362_BOOT_SEL_SERIAL (1 << 15) #define STRAPBUS_6362_BOOT_SEL_NAND (0 << 15) +#define MISC_STRAPBUS_63268_REG 0x14 +#define STRAPBUS_63268_HSSPI_CLK_FAST (1 << 9) +#define STRAPBUS_63268_BOOT_SEL_SERIAL (1 << 11) +#define STRAPBUS_63268_BOOT_SEL_NAND (0 << 11) +#define STRAPBUS_63268_FCVO_SHIFT 21 +#define STRAPBUS_63268_FCVO_MASK (0xf << STRAPBUS_63268_FCVO_SHIFT) + #define MISC_STRAPBUS_6328_REG 0x240 #define STRAPBUS_6328_FCVO_SHIFT 7 #define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT) --- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h +++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h @@ -26,6 +26,7 @@ static inline int is_bcm63xx_internal_re case BCM6328_CPU_ID: case BCM6362_CPU_ID: case BCM6368_CPU_ID: + case BCM63268_CPU_ID: if (offset >= 0xb0000000 && offset < 0xb1000000) return 1; break; --- a/arch/mips/bcm63xx/dev-hsspi.c +++ b/arch/mips/bcm63xx/dev-hsspi.c @@ -35,7 +35,7 @@ static struct platform_device bcm63xx_hs int __init bcm63xx_hsspi_register(void) { - if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362()) + if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_63268()) return -ENODEV; spi_resources[0].start = bcm63xx_regset_address(RSET_HSSPI); --- a/arch/mips/bcm63xx/dev-enet.c +++ b/arch/mips/bcm63xx/dev-enet.c @@ -184,7 +184,8 @@ static int __init register_shared(void) else shared_res[0].end += (RSET_ENETDMA_SIZE) - 1; - if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368()) + if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368() || + BCMCPU_IS_63268()) chan_count = 32; else if (BCMCPU_IS_6345()) chan_count = 8; @@ -292,7 +293,8 @@ bcm63xx_enetsw_register(const struct bcm { int ret; - if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368()) + if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368() && + !BCMCPU_IS_63268()) return -ENODEV; ret = register_shared(); @@ -313,6 +315,8 @@ bcm63xx_enetsw_register(const struct bcm enetsw_pd.num_ports = ENETSW_PORTS_6328; else if (BCMCPU_IS_6362() || BCMCPU_IS_6368()) enetsw_pd.num_ports = ENETSW_PORTS_6368; + else if (BCMCPU_IS_63268()) + enetsw_pd.num_ports = ENETSW_PORTS_63268; enetsw_pd.dma_has_sram = true; enetsw_pd.dma_chan_width = ENETDMA_CHAN_WIDTH; --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h @@ -67,6 +67,7 @@ struct bcm63xx_enet_platform_data { #define ENETSW_MAX_PORT 8 #define ENETSW_PORTS_6328 5 /* 4 FE PHY + 1 RGMII */ #define ENETSW_PORTS_6368 6 /* 4 FE PHY + 2 RGMII */ +#define ENETSW_PORTS_63268 8 /* 3 FE PHY + 1 GE PHY + 4 RGMII */ #define ENETSW_RGMII_PORT0 4