From 060265cd3cec354804c0c944e42de83cec9f2f2a Mon Sep 17 00:00:00 2001 From: Mihai Serban Date: Fri, 21 Apr 2017 15:57:58 +0300 Subject: [PATCH] MLK-14847: Revert "ASoC: fsl-sai: set xCR4/xCR5/xMR for SAI master mode" This reverts commit c768ed336bba ("ASoC: fsl-sai: set xCR4/xCR5/xMR for SAI master mode") This change was already introduced by commit 51659ca069ce ("ASoC: fsl-sai: set xCR4/xCR5/xMR for SAI master mode") from upstream. Manually adjust the code to match the changes introduced by subsequent commit b2936555bb38 ("MLK-13609: ASoC: fsl_sai: fix for synchronize mode") by removing updates to FSL_SAI_TMR/FSL_SAI_RMR registers. Signed-off-by: Mihai Serban --- sound/soc/fsl/fsl_sai.c | 29 ----------------------------- 1 file changed, 29 deletions(-) --- a/sound/soc/fsl/fsl_sai.c +++ b/sound/soc/fsl/fsl_sai.c @@ -507,35 +507,6 @@ static int fsl_sai_hw_params(struct snd_ regmap_update_bits(sai->regmap, FSL_SAI_TCR5, FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | FSL_SAI_CR5_FBT_MASK, val_cr5); - regmap_write(sai->regmap, FSL_SAI_TMR, - ~0UL - ((1 << channels) - 1)); - } else if (!sai->synchronous[RX] && sai->synchronous[TX] && tx) { - regmap_update_bits(sai->regmap, FSL_SAI_RCR4, - FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK, - val_cr4); - regmap_update_bits(sai->regmap, FSL_SAI_RCR5, - FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | - FSL_SAI_CR5_FBT_MASK, val_cr5); - regmap_write(sai->regmap, FSL_SAI_RMR, - ~0UL - ((1 << channels) - 1)); - } - } - - /* - * For SAI master mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will - * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4), - * RCR5(TCR5) and RMR(TMR) for playback(capture), or there will be sync - * error. - */ - - if (!sai->slave_mode[tx]) { - if (!sai->synchronous[TX] && sai->synchronous[RX] && !tx) { - regmap_update_bits(sai->regmap, FSL_SAI_TCR4, - FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK, - val_cr4); - regmap_update_bits(sai->regmap, FSL_SAI_TCR5, - FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | - FSL_SAI_CR5_FBT_MASK, val_cr5); } else if (!sai->synchronous[RX] && sai->synchronous[TX] && tx) { regmap_update_bits(sai->regmap, FSL_SAI_RCR4, FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,