From 7d11e6c1669b9134b11a48cdf47e5b7ab1b2396c Mon Sep 17 00:00:00 2001 From: Bing Song Date: Fri, 5 Jan 2018 08:33:51 +0200 Subject: [PATCH] MLK-17368-1 drm: add fourcc codes for Verisilicon tiled formats These formats will be used by VPU and DCSS. Signed-off-by: Laurentiu Palcu [ Aisheng : VENDOR_VSI changed to 0xf1 ] Signed-off-by: Dong Aisheng --- include/uapi/drm/drm_fourcc.h | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -310,6 +310,7 @@ extern "C" { #define DRM_FORMAT_MOD_VENDOR_ARM 0x08 #define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09 #define DRM_FORMAT_MOD_VENDOR_AMPHION 0xf0 +#define DRM_FORMAT_MOD_VENDOR_VSI 0xf1 /* add more to the end as needed */ @@ -767,6 +768,32 @@ extern "C" { */ #define DRM_FORMAT_MOD_AMPHION_TILED fourcc_mod_code(AMPHION, 1) +/* Verisilicon framebuffer modifiers */ + +/* + * Verisilicon 8x4 tiling layout + * + * This is G1 VPU tiled layout using tiles of 8x4 pixels in a row-major + * layout. + */ +#define DRM_FORMAT_MOD_VSI_G1_TILED fourcc_mod_code(VSI, 1) + +/* + * Verisilicon 4x4 tiling layout + * + * This is G2 VPU tiled layout using tiles of 4x4 pixels in a row-major + * layout. + */ +#define DRM_FORMAT_MOD_VSI_G2_TILED fourcc_mod_code(VSI, 2) + +/* + * Verisilicon 4x4 tiling with compression layout + * + * This is G2 VPU tiled layout using tiles of 4x4 pixels in a row-major + * layout with compression. + */ +#define DRM_FORMAT_MOD_VSI_G2_TILED_COMPRESSED fourcc_mod_code(VSI, 3) + #if defined(__cplusplus) } #endif