/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see .
*/
/**
* @file STM8/serial_lld.c
* @brief STM8 low level serial driver code.
*
* @addtogroup STM8_SERIAL
* @{
*/
#include "ch.h"
#include "hal.h"
#if CH_HAL_USE_SERIAL || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/**
* @brief UART1 serial driver identifier.
*/
#if USE_STM8_UART1 || defined(__DOXYGEN__)
SerialDriver SD1;
#endif
/**
* @brief UART2 serial driver identifier.
*/
#if USE_STM8_UART2 || defined(__DOXYGEN__)
SerialDriver SD2;
#endif
/**
* @brief UART3 serial driver identifier.
*/
#if USE_STM8_UART3 || defined(__DOXYGEN__)
SerialDriver SD3;
#endif
/*===========================================================================*/
/* Driver local variables. */
/*===========================================================================*/
/**
* @brief Driver default configuration.
*/
static ROMCONST SerialConfig default_config = {
BBR(SERIAL_DEFAULT_BITRATE),
SD_MODE_PARITY_NONE | SD_MODE_STOP_1
};
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
static void set_error(SerialDriver *sdp, uint8_t sr) {
sdflags_t sts = 0;
/* Note, SR register bit definitions are equal for all UARTs so using
the UART1 definitions is fine.*/
if (sr & UART1_SR_OR)
sts |= SD_OVERRUN_ERROR;
if (sr & UART1_SR_NF)
sts |= SD_NOISE_ERROR;
if (sr & UART1_SR_FE)
sts |= SD_FRAMING_ERROR;
if (sr & UART1_SR_PE)
sts |= SD_PARITY_ERROR;
chSysLockFromIsr();
sdAddFlagsI(sdp, sts);
chSysUnlockFromIsr();
}
#if USE_STM8_UART1 || defined(__DOXYGEN__)
static void notify1(void) {
UART1->CR2 |= UART1_CR2_TIEN;
}
/**
* @brief UART1 initialization.
*
* @param[in] config architecture-dependent serial driver configuration
*/
static void uart1_init(const SerialConfig *config) {
UART1->BRR2 = (uint8_t)(((uint8_t)(config->sc_brr >> 8) & (uint8_t)0xF0) |
((uint8_t)config->sc_brr & (uint8_t)0x0F));
UART1->BRR1 = (uint8_t)(config->sc_brr >> 4);
UART1->CR1 = (uint8_t)(config->sc_mode &
SD_MODE_PARITY); /* PIEN included. */
UART1->CR2 = UART1_CR2_RIEN | UART1_CR2_TEN | UART1_CR2_REN;
UART1->CR3 = (uint8_t)(config->sc_mode & SD_MODE_STOP);
UART1->CR4 = 0;
UART1->CR5 = 0;
UART1->PSCR = 1;
(void)UART1->SR;
(void)UART1->DR;
}
/**
* @brief UART1 de-initialization.
*/
static void uart1_deinit(void) {
UART1->CR1 = UART1_CR1_UARTD;
UART1->CR2 = 0;
UART1->CR3 = 0;
UART1->CR4 = 0;
UART1->CR5 = 0;
UART1->PSCR = 0;
}
#endif /* USE_STM8_UART1 */
#if USE_STM8_UART2 || defined(__DOXYGEN__)
static void notify2(void) {
UART2->CR2 |= UART2_CR2_TIEN;
}
/**
* @brief UART2 initialization.
*
* @param[in] config architecture-dependent serial driver configuration
*/
static void uart2_init(const SerialConfig *config) {
UART2->BRR2 = (uint8_t)(((uint8_t)(config->sc_brr >> 8) & (uint8_t)0xF0) |
((uint8_t)config->sc_brr & (uint8_t)0x0F));
UART2->BRR1 = (uint8_t)(config->sc_brr >> 4);
UART2->CR1 = (uint8_t)(config->sc_mode &
SD_MODE_PARITY); /* PIEN included. */
UART2->CR2 = UART2_CR2_RIEN | UART2_CR2_TEN | UART2_CR2_REN;
UART2->CR3 = (uint8_t)(config->sc_mode & SD_MODE_STOP);
UART2->CR4 = 0;
UART2->CR5 = 0;
UART2->CR6 = 0;
UART2->PSCR = 1;
(void)UART2->SR;
(void)UART2->DR;
}
/**
* @brief UART1 de-initialization.
*/
static void uart2_deinit(void) {
UART2->CR1 = UART2_CR1_UARTD;
UART2->CR2 = 0;
UART2->CR3 = 0;
UART2->CR4 = 0;
UART2->CR5 = 0;
UART2->CR6 = 0;
UART2->PSCR = 0;
}
#endif /* USE_STM8_UART1 */
#if USE_STM8_UART3 || defined(__DOXYGEN__)
static void notify3(void) {
UART3->CR2 |= UART3_CR2_TIEN;
}
/**
* @brief UART3 initialization.
*
* @param[in] config architecture-dependent serial driver configuration
*/
static void uart3_init(const SerialConfig *config) {
UART3->BRR2 = (uint8_t)(((uint8_t)(config->sc_brr >> 8) & (uint8_t)0xF0) |
((uint8_t)config->sc_brr & (uint8_t)0x0F));
UART3->BRR1 = (uint8_t)(config->sc_brr >> 4);
UART3->CR1 = (uint8_t)(config->sc_mode &
SD_MODE_PARITY); /* PIEN included. */
UART3->CR2 = UART3_CR2_RIEN | UART3_CR2_TEN | UART3_CR2_REN;
UART3->CR3 = (uint8_t)(config->sc_mode & SD_MODE_STOP);
UART3->CR4 = 0;
UART3->CR6 = 0;
(void)UART3->SR;
(void)UART3->DR;
}
/**
* @brief UART3 de-initialization.
*/
static void uart3_deinit(void) {
UART3->CR1 = UART3_CR1_UARTD;
UART3->CR2 = 0;
UART3->CR3 = 0;
UART3->CR4 = 0;
UART3->CR6 = 0;
}
#endif /* USE_STM8_UART3 */
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
#if USE_STM8_UART1 || defined(__DOXYGEN__)
/**
* @brief IRQ 17 service routine.
*
* @isr
*/
CH_IRQ_HANDLER(17) {
msg_t b;
CH_IRQ_PROLOGUE();
chSysLockFromIsr();
b = sdRequestDataI(&SD1);
chSysUnlockFromIsr();
if (b < Q_OK)
UART1->CR2 &= (uint8_t)~UART1_CR2_TIEN;
else
UART1->DR = (uint8_t)b;
CH_IRQ_EPILOGUE();
}
/**
* @brief IRQ 18 service routine.
*
* @isr
*/
CH_IRQ_HANDLER(18) {
uint8_t sr = UART1->SR;
CH_IRQ_PROLOGUE();
if ((sr = UART1->SR) & (UART1_SR_OR | UART1_SR_NF |
UART1_SR_FE | UART1_SR_PE))
set_error(&SD1, sr);
chSysLockFromIsr();
sdIncomingDataI(&SD1, UART1->DR);
chSysUnlockFromIsr();
CH_IRQ_EPILOGUE();
}
#endif /* USE_STM8_UART1 */
#if USE_STM8_UART2 || defined(__DOXYGEN__)
/**
* @brief IRQ 20 service routine.
*
* @isr
*/
CH_IRQ_HANDLER(20) {
msg_t b;
CH_IRQ_PROLOGUE();
chSysLockFromIsr();
b = sdRequestDataI(&SD2);
chSysUnlockFromIsr();
if (b < Q_OK)
UART2->CR2 &= (uint8_t)~UART2_CR2_TIEN;
else
UART2->DR = (uint8_t)b;
CH_IRQ_EPILOGUE();
}
/**
* @brief IRQ 21 service routine.
*
* @isr
*/
CH_IRQ_HANDLER(21) {
uint8_t sr = UART2->SR;
CH_IRQ_PROLOGUE();
if ((sr = UART2->SR) & (UART2_SR_OR | UART2_SR_NF |
UART2_SR_FE | UART2_SR_PE))
set_error(&SD2, sr);
chSysLockFromIsr();
sdIncomingDataI(&SD2, UART2->DR);
chSysUnlockFromIsr();
CH_IRQ_EPILOGUE();
}
#endif /* USE_STM8_UART2 */
#if USE_STM8_UART3 || defined(__DOXYGEN__)
/**
* @brief IRQ 20 service routine.
*
* @isr
*/
CH_IRQ_HANDLER(20) {
msg_t b;
CH_IRQ_PROLOGUE();
chSysLockFromIsr();
b = sdRequestDataI(&SD3);
chSysUnlockFromIsr();
if (b < Q_OK)
UART3->CR2 &= (uint8_t)~UART3_CR2_TIEN;
else
UART3->DR = (uint8_t)b;
CH_IRQ_EPILOGUE();
}
/**
* @brief IRQ 21 service routine.
*
* @isr
*/
CH_IRQ_HANDLER(21) {
uint8_t sr = UART3->SR;
CH_IRQ_PROLOGUE();
if ((sr = UART3->SR) & (UART3_SR_OR | UART3_SR_NF |
UART3_SR_FE | UART3_SR_PE))
set_error(&SD3, sr);
chSysLockFromIsr();
sdIncomingDataI(&SD3, UART3->DR);
chSysUnlockFromIsr();
CH_IRQ_EPILOGUE();
}
#endif /* USE_STM8_UART3 */
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief Low level serial driver initialization.
*
* @notapi
*/
void sd_lld_init(void) {
#if USE_STM8_UART1
sdObjectInit(&SD1, NULL, notify1);
CLK->PCKENR1 |= CLK_PCKENR1_UART1; /* PCKEN12, clock source. */
UART1->CR1 = UART1_CR1_UARTD; /* UARTD (low power). */
#endif
#if USE_STM8_UART2
sdObjectInit(&SD2, NULL, notify2);
CLK->PCKENR1 |= CLK_PCKENR1_UART2; /* PCKEN13, clock source. */
UART2->CR1 = UART2_CR1_UARTD; /* UARTD (low power). */
#endif
#if USE_STM8_UART3
sdObjectInit(&SD3, NULL, notify3);
CLK->PCKENR1 |= CLK_PCKENR1_UART3; /* PCKEN13, clock source. */
UART3->CR1 = UART3_CR1_UARTD; /* UARTD (low power). */
#endif
}
/**
* @brief Low level serial driver configuration and (re)start.
*
* @param[in] sdp pointer to a @p SerialDriver object
* @param[in] config the architecture-dependent serial driver configuration.
* If this parameter is set to @p NULL then a default
* configuration is used.
*
* @notapi
*/
void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
if (config == NULL)
config = &default_config;
#if USE_STM8_UART1
if (&SD1 == sdp) {
uart1_init(config);
return;
}
#endif
#if USE_STM8_UART2
if (&SD2 == sdp) {
uart2_init(config);
return;
}
#endif
#if USE_STM8_UART3
if (&SD3 == sdp) {
uart3_init(config);
return;
}
#endif
}
/**
* @brief Low level serial driver stop.
* @details De-initializes the USART, stops the associated clock, resets the
* interrupt vector.
*
* @param[in] sdp pointer to a @p SerialDriver object
*
* @notapi
*/
void sd_lld_stop(SerialDriver *sdp) {
#if USE_STM8_UART1
if (&SD1 == sdp) {
uart1_deinit();
return;
}
#endif
#if USE_STM8_UART2
if (&SD2 == sdp) {
uart2_deinit();
return;
}
#endif
#if USE_STM8_UART3
if (&SD3 == sdp) {
uart3_deinit();
return;
}
#endif
}
#endif /* CH_HAL_USE_SERIAL */
/** @} */
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################################################################################
## Raspberry Pi Configuration Settings
##
## Revision 14, 2012/10/22
##
## Details taken from the eLinux wiki
## For up-to-date information please refer to wiki page.
##
## Wiki Location : http://elinux.org/RPi_config.txt
##
##
## Description:
## Details of each setting are described with each section that begins with
## a double hashed comment ('##')
## It is up to the user to remove the single hashed comment ('#') from each
## option they want to enable, and to set the specific value of that option.
##
## WARNING: Setting the following combination of parameters will set a
## permanent bit within the SOC and your warranty is void.
## over_voltage>0, and at least one of the following:
## force_turbo=1
## current_limit_override=0x5A000020
## temp_limit>85
##
## Overclock settings will be disabled at runtime if the SoC reaches temp_limit
##
################################################################################
################################################################################
## Standard Definition Video Settings
################################################################################
## sdtv_mode
## defines the TV standard for composite output
##
## Value Description
## -------------------------------------------------------------------------
## 0 Normal NTSC (Default)
## 1 Japanese version of NTSC - no pedestal
## 2 Normal PAL
## 3 Brazilian version of PAL - 525/60 rather than 625/50, different
## subcarrier
##
#sdtv_mode=0
## sdtv_aspect
## defines the aspect ratio for composite output
##
## Value Description
## -------------------------------------------------------------------------
## 1 4:3 (Default)
## 2 14:9
## 3 16:9
##
#sdtv_aspect=1
## sdtv_disable_colourburst
## Disables colour burst on composite output. The picture will be
## monochrome, but possibly sharper
##
## Value Description
## -------------------------------------------------------------------------
## 0 Colour burst is enabled (Default)
## 1 Colour burst is disabled
##
#sdtv_disable_colourburst=1
################################################################################
## High Definition Video Settings
################################################################################
## hdmi_safe
## Use "safe mode" settings to try to boot with maximum hdmi compatibility.
##
## Value Description
## -------------------------------------------------------------------------
## 0 Disabled (Default)
## 1 Enabled (this does: hdmi_force_hotplug=1, config_hdmi_boost=4,
## hdmi_group=1, hdmi_mode=1,
## disable_overscan=0)
##
#hdmi_safe=1
## hdmi_force_hotplug
## Pretends HDMI hotplug signal is asserted so it appears a HDMI display
## is attached
##
## Value Description
## -------------------------------------------------------------------------
## 0 Disabled (Default)
## 1 Use HDMI mode even if no HDMI monitor is detected
##
#hdmi_force_hotplug=1
## hdmi_ignore_hotplug
## Pretends HDMI hotplug signal is not asserted so it appears a HDMI
## display is not attached
##
## Value Description
## -------------------------------------------------------------------------
## 0 Disabled (Default)
## 1 Use composite mode even if HDMI monitor is detected
##
#hdmi_ignore_hotplug=1
## hdmi_drive
## chooses between HDMI and DVI modes
##
## Value Description
## -------------------------------------------------------------------------
## 1 Normal DVI mode (No sound)
## 2 Normal HDMI mode (Sound will be sent if supported and enabled)
##
#hdmi_drive=2
## hdmi_ignore_edid
## Enables the ignoring of EDID/display data
##
#hdmi_ignore_edid=0xa5000080
## hdmi_edid_file
## Read the EDID data from the edid.dat file instead of from the attached
## device
##
## Value Description
## -------------------------------------------------------------------------
## 0 Read EDID data from attached device (Default)
## 1 Read EDID data from edid.txt file
##
#hdmi_edid_file=1
## hdmi_force_edid_audio
## Pretends all audio formats are supported by display, allowing
## passthrough of DTS/AC3 even when not reported as supported.
##
## Value Description
## -------------------------------------------------------------------------
## 0 Use EDID provided values (Default)
## 1 Pretend all audio formats are supported
##
#hdmi_force_edid_audio=1
## avoid_edid_fuzzy_match
## Avoid fuzzy matching of modes described in edid.
##
## Value Description
## -------------------------------------------------------------------------
## 0 Use fuzzy matching (Default)
## 1 Avoid fuzzy matching
##
#avoid_edid_fuzzy_match=1
## hdmi_group
## Defines the HDMI type
##
## Value Description
## -------------------------------------------------------------------------
## 0 Use the preferred group reported by the edid (Default)
## 1 CEA
## 2 DMT
##
#hdmi_group=1
## hdmi_mode
## defines screen resolution in CEA or DMT format
##
## H means 16:9 variant (of a normally 4:3 mode).
## 2x means pixel doubled (i.e. higher clock rate, with each pixel repeated
## twice)
## 4x means pixel quadrupled (i.e. higher clock rate, with each pixel
## repeated four times)
## reduced blanking means fewer bytes are used for blanking within the data
## stream (i.e. lower clock rate, with fewer wasted bytes)
##
## Value hdmi_group=CEA hdmi_group=DMT
## -------------------------------------------------------------------------
## 1 VGA 640x350 85Hz
## 2 480p 60Hz 640x400 85Hz
## 3 480p 60Hz H 720x400 85Hz
## 4 720p 60Hz 640x480 60Hz
## 5 1080i 60Hz 640x480 72Hz
## 6 480i 60Hz 640x480 75Hz
## 7 480i 60Hz H 640x480 85Hz
## 8 240p 60Hz 800x600 56Hz
## 9 240p 60Hz H 800x600 60Hz
## 10 480i 60Hz 4x 800x600 72Hz
## 11 480i 60Hz 4x H 800x600 75Hz
## 12 240p 60Hz 4x 800x600 85Hz
## 13 240p 60Hz 4x H 800x600 120Hz
## 14 480p 60Hz 2x 848x480 60Hz
## 15 480p 60Hz 2x H 1024x768 43Hz DO NOT USE
## 16 1080p 60Hz 1024x768 60Hz
## 17 576p 50Hz 1024x768 70Hz
## 18 576p 50Hz H 1024x768 75Hz
## 19 720p 50Hz 1024x768 85Hz
## 20 1080i 50Hz 1024x768 120Hz
## 21 576i 50Hz 1152x864 75Hz
## 22 576i 50Hz H 1280x768 reduced blanking
## 23 288p 50Hz 1280x768 60Hz
## 24 288p 50Hz H 1280x768 75Hz
## 25 576i 50Hz 4x 1280x768 85Hz
## 26 576i 50Hz 4x H 1280x768 120Hz reduced blanking
## 27 288p 50Hz 4x 1280x800 reduced blanking
## 28 288p 50Hz 4x H 1280x800 60Hz
## 29 576p 50Hz 2x 1280x800 75Hz
## 30 576p 50Hz 2x H 1280x800 85Hz
## 31 1080p 50Hz 1280x800 120Hz reduced blanking
## 32 1080p 24Hz 1280x960 60Hz
## 33 1080p 25Hz 1280x960 85Hz
## 34 1080p 30Hz 1280x960 120Hz reduced blanking
## 35 480p 60Hz 4x 1280x1024 60Hz
## 36 480p 60Hz 4x H 1280x1024 75Hz
## 37 576p 50Hz 4x 1280x1024 85Hz
## 38 576p 50Hz 4x H 1280x1024 120Hz reduced blanking
## 39 1080i 50Hz reduced blanking 1360x768 60Hz
## 40 1080i 100Hz 1360x768 120Hz reduced blanking
## 41 720p 100Hz 1400x1050 reduced blanking
## 42 576p 100Hz 1400x1050 60Hz
## 43 576p 100Hz H 1400x1050 75Hz
## 44 576i 100Hz 1400x1050 85Hz
## 45 576i 100Hz H 1400x1050 120Hz reduced blanking
## 46 1080i 120Hz 1440x900 reduced blanking
## 47 720p 120Hz 1440x900 60Hz
## 48 480p 120Hz 1440x900 75Hz
## 49 480p 120Hz H 1440x900 85Hz
## 50 480i 120Hz 1440x900 120Hz reduced blanking
## 51 480i 120Hz H 1600x1200 60Hz
## 52 576p 200Hz 1600x1200 65Hz
## 53 576p 200Hz H 1600x1200 70Hz
## 54 576i 200Hz 1600x1200 75Hz
## 55 576i 200Hz H 1600x1200 85Hz
## 56 480p 240Hz 1600x1200 120Hz reduced blanking
## 57 480p 240Hz H 1680x1050 reduced blanking
## 58 480i 240Hz 1680x1050 60Hz
## 59 480i 240Hz H 1680x1050 75Hz
## 60 1680x1050 85Hz
## 61 1680x1050 120Hz reduced blanking
## 62 1792x1344 60Hz
## 63 1792x1344 75Hz
## 64 1792x1344 120Hz reduced blanking
## 65 1856x1392 60Hz
## 66 1856x1392 75Hz
## 67 1856x1392 120Hz reduced blanking
## 68 1920x1200 reduced blanking
## 69 1920x1200 60Hz
## 70 1920x1200 75Hz
## 71 1920x1200 85Hz
## 72 1920x1200 120Hz reduced blanking
## 73 1920x1440 60Hz
## 74 1920x1440 75Hz
## 75 1920x1440 120Hz reduced blanking
## 76 2560x1600 reduced blanking
## 77 2560x1600 60Hz
## 78 2560x1600 75Hz
## 79 2560x1600 85Hz
## 80 2560x1600 120Hz reduced blanking
## 81 1366x768 60Hz
## 82 1080p 60Hz
## 83 1600x900 reduced blanking
## 84 2048x1152 reduced blanking
## 85 720p 60Hz
## 86 1366x768 reduced blanking
##
#hdmi_mode=1
## config_hdmi_boost
## configure the signal strength of the HDMI interface.
##
## Value Description
## -------------------------------------------------------------------------
## 0 (Default)
## 1
## 2
## 3
## 4 Try if you have interference issues with HDMI
## 5
## 6
## 7 Maximum
##
#config_hdmi_boost=0
## hdmi_ignore_cec_init
## Doesn't sent initial active source message. Avoids bringing
## (CEC enabled) TV out of standby and channel switch when rebooting.
##
## Value Description
## -------------------------------------------------------------------------
## 0 Normal behaviour (Default)
## 1 Doesn't sent initial active source message
##
#hdmi_ignore_cec_init=1
## hdmi_ignore_cec
## Pretends CEC is not supported at all by TV.
## No CEC functions will be supported.
##
## Value Description
## -------------------------------------------------------------------------
## 0 Normal behaviour (Default)
## 1 Pretend CEC is not supported by TV
##
#hdmi_ignore_cec=1
################################################################################
## Overscan Video Settings
################################################################################
## overscan_left
## Number of pixels to skip on left
##
#overscan_left=0
## overscan_right
## Number of pixels to skip on right
##
#overscan_right=0
## overscan_top
## Number of pixels to skip on top
##
#overscan_top=0
## overscan_bottom
## Number of pixels to skip on bottom
##
#overscan_bottom=0
## disable_overscan
## Set to 1 to disable overscan
##
## Value Description
## -------------------------------------------------------------------------
## 0 Overscan Enabled (Default)
## 1 Overscan Disabled
##
#disable_overscan=1
################################################################################
## Framebuffer Video Settings
################################################################################
## framebuffer_width
## Console framebuffer width in pixels. Default is display width minus
## overscan.
##
#framebuffer_width=0
## framebuffer_height
## Console framebuffer height in pixels. Default is display height minus
## overscan.
##
#framebuffer_height=0
## framebuffer_depth
## Console framebuffer depth in bits per pixel.
##
## Value Description
## -------------------------------------------------------------------------
## 8 Valid, but default RGB palette makes an unreadable screen
## 16 (Default)
## 24 Looks better but has corruption issues as of 2012/06/15
## 32 Has no corruption issues but needs framebuffer_ignore_alpha=1
## and shows the wrong colors as of 2012/06/15
##
#framebuffer_depth=16
## framebuffer_ignore_alpha
## Set to 1 to disable alpha channel. Helps with 32bit.
##
## Value Description
## -------------------------------------------------------------------------
## 0 Enable Alpha Channel (Default)
## 1 Disable Alpha Channel
##
#framebuffer_ignore_alpha=0
################################################################################
## General Video Settings
################################################################################
## display_rotate
## Rotate the display clockwise or flip the display.
## The 90 and 270 degrees rotation options require additional memory on GPU,
## so won't work with the 16M GPU split.
##
## Value Description
## -------------------------------------------------------------------------
## 0 0 degrees (Default)
## 1 90 degrees
## 2 180 degrees
## 3 270 degrees
## 0x10000 Horizontal flip
## 0x20000 Vertical flip
##
#display_rotate=0
################################################################################
## Licensed Codecs
##
## Hardware decoding of additional codecs can be enabled by purchasing a
## license that is locked to the CPU serial number of your Raspberry Pi.
##
## Up to 8 licenses per CODEC can be specified as a comma seperated list.
##
################################################################################
## decode_MPG2
## License key to allow hardware MPEG-2 decoding.
##
#decode_MPG2=0x12345678
## decode_WVC1
## License key to allow hardware VC-1 decoding.
##
#decode_WVC1=0x12345678
################################################################################
## Test Settings
################################################################################
## test_mode
## Enable test sound/image during boot for manufacturing test.
##
## Value Description
## -------------------------------------------------------------------------
## 0 Disable Test Mod (Default)
## 1 Enable Test Mode
##
#test_mode=0
################################################################################
## Memory Settings
################################################################################
## disable_l2cache
## Disable arm access to GPU's L2 cache. Needs corresponding L2 disabled
## kernel.
##
## Value Description
## -------------------------------------------------------------------------
## 0 Enable L2 Cache (Default)
## 1 Disable L2 cache
##
#disable_l2cache=0
## gpu_mem
## GPU memory allocation in MB for all board revisions.
##
## Default 64
##
#gpu_mem=128
## gpu_mem_256
## GPU memory allocation in MB for 256MB board revision.
## This option overrides gpu_mem.
##
#gpu_mem_256=128
## gpu_mem_512
## GPU memory allocation in MB for 512MB board revision.
## This option overrides gpu_mem.
##
#gpu_mem_512=128
## gpu_mem_1024
## GPU memory allocation in MB for 1024MB board revision.
## This option overrides gpu_mem.
##
#gpu_mem_1024=128
################################################################################
## Boot Option Settings
################################################################################
## disable_commandline_tags
## Stop start.elf from filling in ATAGS (memory from 0x100) before
## launching kernel
##
disable_commandline_tags=2
## cmdline (string)
## Command line parameters. Can be used instead of cmdline.txt file
##
#cmdline=""
## kernel (string)
## Alternative name to use when loading kernel.
##
#kernel=""
## kernel_address
## Address to load kernel.img file at
##
kernel_address=0x8000
## ramfsfile (string)
## ramfs file to load
##
#ramfsfile=""
## ramfsaddr
## Address to load ramfs file at
##
#ramfsaddr=0x00000000
## initramfs (string address)
## ramfs file and address to load it at (it's like ramfsfile+ramfsaddr in
## one option).
##
## NOTE: this option uses different syntax than all other options - you
## should not use "=" character here.
##
#initramfs initramf.gz 0x00800000
## device_tree_address
## Address to load device_tree at
##
device_tree_address=0x100
## init_uart_baud
## Initial uart baud rate.
##
## Default 115200
##
init_uart_baud=115200
## init_uart_clock
## Initial uart clock.
##
## Default 3000000 (3MHz)
##
init_uart_clock=3000000
## init_emmc_clock
## Initial emmc clock, increasing this can speedup your SD-card.
##
## Default 100000000 (100mhz)
##
#init_emmc_clock=100000000
## boot_delay
## Wait for a given number of seconds in start.elf before loading
## kernel.img.
##
## delay = (1000 * boot_delay) + boot_delay_ms
##
## Default 1
##
#boot_delay=0
## boot_delay_ms
## Wait for a given number of milliseconds in start.elf before loading
## kernel.img.
##
## delay = (1000 * boot_delay) + boot_delay_ms
##
## Default 0
##
#boot_delay_ms=0
## avoid_safe_mode
## Adding a jumper between pins 5 & 6 of P1 enables a recovery Safe Mode.
## If pins 5 & 6 are used for connecting to external devices (e.g. GPIO),
## then this setting can be used to ensure Safe Mode is not triggered.
##
## Value Description
## -------------------------------------------------------------------------
## 0 Respect Safe Mode input (Default)
## 1 Ignore Safe Mode input
##
#avoid_safe_mode=1
################################################################################
## Overclocking Settings
##
## ARM, SDRAM and GPU each have their own PLLs and can have unrelated
## frequencies.
##
## The GPU core, h264, v3d and isp share a PLL, so need to have related
## frequencies.
## pll_freq = floor(2400 / (2 * core_freq)) * (2 * core_freq)
## gpu_freq = pll_freq / [even number]
##
## The effective gpu_freq is automatically rounded to nearest even integer, so
## asking for core_freq = 500 and gpu_freq = 300 will result in divisor of
## 2000/300 = 6.666 => 6 and so 333.33MHz.
##
##
## Standard Profiles:
## arm_freq core_freq sdram_freq over_voltage
## -------------------------------------------------------------------------
## None 700 250 400 0
## Modest 800 300 400 0
## Medium 900 333 450 2
## High 950 450 450 6
## Turbo 1000 500 500 6
##
################################################################################
## force_turbo
## Control the kernel "ondemand" governor. It has no effect if no overclock
## settings are specified.
##
## Value Description
## -------------------------------------------------------------------------
## 0 Enable dynamic clocks and voltage for the ARM core, GPU core and
## SDRAM (Default).
## Overclocking of h264_freq, v3d_freq and isp_freq is ignored.
## 1 Disable dynamic clocks and voltage for the ARM core, GPU core
## and SDRAM.
## Overclocking of h264_freq, v3d_freq and isp_freq is allowed.
##
#force_turbo=0
## initial_turbo
## Enables turbo mode from boot for the given value in seconds (up to 60)
## or until cpufreq sets a frequency. Can help with sdcard corruption if
## overclocked.
##
## Default 0
##
#initial_turbo=0
## temp_limit
## Overheat protection. Sets clocks and voltages to default when the SoC
## reaches this Celsius value.
## Setting this higher than default voids warranty.
##
## Default 85
##
#temp_limit=85
## arm_freq
## Frequency of ARM in MHz.
##
## Default 700.
##
#arm_freq=700
## arm_freq_min
## Minimum frequency of ARM in MHz (used for dynamic clocking).
##
## Default 700.
##
#arm_freq_min=700
## gpu_freq
## Sets core_freq, h264_freq, isp_freq, v3d_freq together.
##
## Default 250.
##
#gpu_freq=250
## core_freq
## Frequency of GPU processor core in MHz. It has an impact on ARM
## performance since it drives L2 cache.
##
## Default 250.
##
#core_freq=250
## core_freq_min
## Minimum frequency of GPU processor core in MHz (used for dynamic
## clocking). It has an impact on ARM performance since it drives L2 cache.
##
## Default 250.
##
#core_freq_min=250
## h264_freq
## Frequency of hardware video block in MHz.
##
## Default 250.
##
#h264_freq=250
## isp_freq
## Frequency of image sensor pipeline block in MHz.
##
## Default 250.
##
#isp_freq=250
## v3d_freq
## Frequency of 3D block in MHz.
##
## Default 250.
##
#v3d_freq=250
## sdram_freq
## Frequency of SDRAM in MHz.
##
## Default 400.
##
#sdram_freq=400
## sdram_freq_min
## Minimum frequency of SDRAM in MHz (used for dynamic clocking).
##
## Default 400.
##
#sdram_freq_min=400
## avoid_pwm_pll
## Unlink core_freq from the rest of the gpu. Analog audio should still
## work, but from a fractional divider, so lower quality.
##
## Value Description
## -------------------------------------------------------------------------
## 0 Linked core_freq (Default)
## 1 Unlinked core_freq
##
#avoid_pwm_pll=1
################################################################################
## Voltage Settings
################################################################################
## current_limit_override
## Disables SMPS current limit protection. Can help if you are currently
## hitting a reboot failure when overclocking too high.
##
#current_limit_override=0x5A000020
## over_voltage
## ARM/GPU core voltage adjust.
##
## Value Description
## -------------------------------------------------------------------------
## -16 0.8 V
## -15 0.825 V
## -14 0.85 V
## -13 0.875 V
## -12 0.9 V
## -11 0.925 V
## -10 0.95 V
## -9 0.975 V
## -8 1.0 V
## -7 1.025 V
## -6 1.05 V
## -5 1.075 V
## -4 1.1 V
## -3 1.125 V
## -2 1.15 V
## -1 1.175 V
## 0 1.2 V (Default)
## 1 1.225 V
## 2 1.25 V
## 3 1.275 V
## 4 1.3 V
## 5 1.325 V
## 6 1.35 V
## 7 1.375 V (requires force_turbo=1)
## 8 1.4 V (requires force_turbo=1)
##
#over_voltage=0
## over_voltage_min
## Minimum ARM/GPU core voltage adjust (used for dynamic clocking).
##
## Value Description
## -------------------------------------------------------------------------
## -16 0.8 V
## -15 0.825 V
## -14 0.85 V
## -13 0.875 V
## -12 0.9 V
## -11 0.925 V
## -10 0.95 V
## -9 0.975 V
## -8 1.0 V
## -7 1.025 V
## -6 1.05 V
## -5 1.075 V
## -4 1.1 V
## -3 1.125 V
## -2 1.15 V
## -1 1.175 V
## 0 1.2 V (Default)
## 1 1.225 V
## 2 1.25 V
## 3 1.275 V
## 4 1.3 V
## 5 1.325 V
## 6 1.35 V
## 7 1.375 V (requires force_turbo=1)
## 8 1.4 V (requires force_turbo=1)
##
#over_voltage_min=0
## over_voltage_sdram
## Sets over_voltage_sdram_c, over_voltage_sdram_i, over_voltage_sdram_p
## together
##
## Value Description
## -------------------------------------------------------------------------
## -16 0.8 V
## -15 0.825 V
## -14 0.85 V
## -13 0.875 V
## -12 0.9 V
## -11 0.925 V
## -10 0.95 V
## -9 0.975 V
## -8 1.0 V
## -7 1.025 V
## -6 1.05 V
## -5 1.075 V
## -4 1.1 V
## -3 1.125 V
## -2 1.15 V
## -1 1.175 V
## 0 1.2 V (Default)
## 1 1.225 V
## 2 1.25 V
## 3 1.275 V
## 4 1.3 V
## 5 1.325 V
## 6 1.35 V
## 7 1.375 V
## 8 1.4 V
##
#over_voltage_sdram=0
## over_voltage_sdram_c
## SDRAM controller voltage adjust.
##
## Value Description
## -------------------------------------------------------------------------
## -16 0.8 V
## -15 0.825 V
## -14 0.85 V
## -13 0.875 V
## -12 0.9 V
## -11 0.925 V
## -10 0.95 V
## -9 0.975 V
## -8 1.0 V
## -7 1.025 V
## -6 1.05 V
## -5 1.075 V
## -4 1.1 V
## -3 1.125 V
## -2 1.15 V
## -1 1.175 V
## 0 1.2 V (Default)
## 1 1.225 V
## 2 1.25 V
## 3 1.275 V
## 4 1.3 V
## 5 1.325 V
## 6 1.35 V
## 7 1.375 V
## 8 1.4 V
##
#over_voltage_sdram_c=0
## over_voltage_sdram_i
## SDRAM I/O voltage adjust.
##
## Value Description
## -------------------------------------------------------------------------
## -16 0.8 V
## -15 0.825 V
## -14 0.85 V
## -13 0.875 V
## -12 0.9 V
## -11 0.925 V
## -10 0.95 V
## -9 0.975 V
## -8 1.0 V
## -7 1.025 V
## -6 1.05 V
## -5 1.075 V
## -4 1.1 V
## -3 1.125 V
## -2 1.15 V
## -1 1.175 V
## 0 1.2 V (Default)
## 1 1.225 V
## 2 1.25 V
## 3 1.275 V
## 4 1.3 V
## 5 1.325 V
## 6 1.35 V
## 7 1.375 V
## 8 1.4 V
##
#over_voltage_sdram_i=0
## over_voltage_sdram_p
## SDRAM phy voltage adjust.
##
## Value Description
## -------------------------------------------------------------------------
## -16 0.8 V
## -15 0.825 V
## -14 0.85 V
## -13 0.875 V
## -12 0.9 V
## -11 0.925 V
## -10 0.95 V
## -9 0.975 V
## -8 1.0 V
## -7 1.025 V
## -6 1.05 V
## -5 1.075 V
## -4 1.1 V
## -3 1.125 V
## -2 1.15 V
## -1 1.175 V
## 0 1.2 V (Default)
## 1 1.225 V
## 2 1.25 V
## 3 1.275 V
## 4 1.3 V
## 5 1.325 V
## 6 1.35 V
## 7 1.375 V
## 8 1.4 V
##
#over_voltage_sdram_p=0
################################################################################
## Device Tree Settings
################################################################################
dtparam=random=on,watchdog=on,audio=on,i2c0=on,i2c1=on,spi=on
#dtoverlay=hifiberry-amp-overlay
#dtoverlay=hifiberry-dac-overlay
#dtoverlay=hifiberry-dacplus-overlay
#dtoverlay=hifiberry-digi-overlay
#dtoverlay=iqaudio-dac-overlay
#dtoverlay=iqaudio-dacplus-overlay
#dtoverlay=raspidac3-overlay
#dtoverlay=rpi-proto-overlay
|