#ifndef B43_PHY_H_ #define B43_PHY_H_ #include struct b43_wldev; struct b43_phy; /*** PHY Registers ***/ /* Routing */ #define B43_PHYROUTE 0x0C00 /* PHY register routing bits mask */ #define B43_PHYROUTE_BASE 0x0000 /* Base registers */ #define B43_PHYROUTE_OFDM_GPHY 0x0400 /* OFDM register routing for G-PHYs */ #define B43_PHYROUTE_EXT_GPHY 0x0800 /* Extended G-PHY registers */ #define B43_PHYROUTE_N_BMODE 0x0C00 /* N-PHY BMODE registers */ /* CCK (B-PHY) registers. */ #define B43_PHY_CCK(reg) ((reg) | B43_PHYROUTE_BASE) /* N-PHY registers. */ #define B43_PHY_N(reg) ((reg) | B43_PHYROUTE_BASE) /* N-PHY BMODE registers. */ #define B43_PHY_N_BMODE(reg) ((reg) | B43_PHYROUTE_N_BMODE) /* OFDM (A-PHY) registers. */ #define B43_PHY_OFDM(reg) ((reg) | B43_PHYROUTE_OFDM_GPHY) /* Extended G-PHY registers. */ #define B43_PHY_EXTG(reg) ((reg) | B43_PHYROUTE_EXT_GPHY) /* OFDM (A) PHY Registers */ #define B43_PHY_VERSION_OFDM B43_PHY_OFDM(0x00) /* Versioning register for A-PHY */ #define B43_PHY_BBANDCFG B43_PHY_OFDM(0x01) /* Baseband config */ #define B43_PHY_BBANDCFG_RXANT 0x180 /* RX Antenna selection */ #define B43_PHY_BBANDCFG_RXANT_SHIFT 7 #define B43_PHY_PWRDOWN B43_PHY_OFDM(0x03) /* Powerdown */ #define B43_PHY_CRSTHRES1_R1 B43_PHY_OFDM(0x06) /* CRS Threshold 1 (phy.rev 1 only) */ #define B43_PHY_LNAHPFCTL B43_PHY_OFDM(0x1C) /* LNA/HPF control */ #define B43_PHY_LPFGAINCTL B43_PHY_OFDM(0x20) /* LPF Gain control */ #define B43_PHY_ADIVRELATED B43_PHY_OFDM(0x27) /* FIXME rename */ #define B43_PHY_CRS0 B43_PHY_OFDM(0x29) #define B43_PHY_CRS0_EN 0x4000 #define B43_PHY_PEAK_COUNT B43_PHY_OFDM(0x30) #define B43_PHY_ANTDWELL B43_PHY_OFDM(0x2B) /* Antenna dwell */ #define B43_PHY_ANTDWELL_AUTODIV1 0x0100 /* Automatic RX diversity start antenna */ #define B43_PHY_ENCORE B43_PHY_OFDM(0x49) /* "Encore" (RangeMax / BroadRange) */ #define B43_PHY_ENCORE_EN 0x0200 /* Encore enable */ #define B43_PHY_LMS B43_PHY_OFDM(0x55) #define B43_PHY_OFDM61 B43_PHY_OFDM(0x61) /* FIXME rename */ #define B43_PHY_OFDM61_10 0x0010 /* FIXME rename */ #define B43_PHY_IQBAL B43_PHY_OFDM(0x69) /* I/Q balance */ #define B43_PHY_BBTXDC_BIAS B43_PHY_OFDM(0x6B) /* Baseband TX DC bias */ #define B43_PHY_OTABLECTL B43_PHY_OFDM(0x72) /* OFDM table control (see below) */ #define B43_PHY_OTABLEOFF 0x03FF /* OFDM table offset (see below) */ #define B43_PHY_OTABLENR 0xFC00 /* OFDM table number (see below) */ #define B43_PHY_OTABLENR_SHIFT 10 #define B43_PHY_OTABLEI B43_PHY_OFDM(0x73) /* OFDM table data I */ #define B43_PHY_OTABLEQ B43_PHY_OFDM(0x74) /* OFDM table data Q */ #define B43_PHY_HPWR_TSSICTL B43_PHY_OFDM(0x78) /* Hardware power TSSI control */ #define B43_PHY_ADCCTL B43_PHY_OFDM(0x7A) /* ADC control */ #define B43_PHY_IDLE_TSSI B43_PHY_OFDM(0x7B) #define B43_PHY_A_TEMP_SENSE B43_PHY_OFDM(0x7C) /* A PHY temperature sense */ #define B43_PHY_NRSSITHRES B43_PHY_OFDM(0x8A) /* NRSSI threshold */ #define B43_PHY_ANTWRSETT B43_PHY_OFDM(0x8C) /* Antenna WR settle */ #define B43_PHY_ANTWRSETT_ARXDIV 0x2000 /* Automatic RX diversity enabled */ #define B43_PHY_CLIPPWRDOWNT B43_PHY_OFDM(0x93) /* Clip powerdown threshold */ #define B43_PHY_OFDM9B B43_PHY_OFDM(0x9B) /* FIXME rename */ #define B43_PHY_N1P1GAIN B43_PHY_OFDM(0xA0) #define B43_PHY_P1P2GAIN B43_PHY_OFDM(0xA1) #define B43_PHY_N1N2GAIN B43_PHY_OFDM(0xA2) #define B43_PHY_CLIPTHRES B43_PHY_OFDM(0xA3) #define B43_PHY_CLIPN1P2THRES B43_PHY_OFDM(0xA4) #define B43_PHY_CCKSHIFTBITS_WA B43_PHY_OFDM(0xA5) /* CCK shiftbits workaround, FIXME rename */ #define B43_PHY_CCKSHIFTBITS B43_PHY_OFDM(0xA7) /* FIXME rename */ #define B43_PHY_DIVSRCHIDX B43_PHY_OFDM(0xA8) /* Divider search gain/index */ #define B43_PHY_CLIPP2THRES B43_PHY_OFDM(0xA9) #define B43_PHY_CLIPP3THRES B43_PHY_OFDM(0xAA) #define B43_PHY_DIVP1P2GAIN B43_PHY_OFDM(0xAB) #define B43_PHY_DIVSRCHGAINBACK B43_PHY_OFDM(0xAD) /* Divider search gain back */ #define B43_PHY_DIVSRCHGAINCHNG B43_PHY_OFDM(0xAE) /* Divider search gain change */ #define B43_PHY_CRSTHRES1 B43_PHY_OFDM(0xC0) /* CRS Threshold 1 (phy.rev >= 2 only) */ #define B43_PHY_CRSTHRES2 B43_PHY_OFDM(0xC1) /* CRS Threshold 2 (phy.rev >= 2 only) */ #define B43_PHY_TSSIP_LTBASE B43_PHY_OFDM(0x380) /* TSSI power lookup table base */ #define B43_PHY_DC_LTBASE B43_PHY_OFDM(0x3A0) /* DC lookup table base */ #define B43_PHY_GAIN_LTBASE B43_PHY_OFDM(0x3C0) /* Gain lookup table base */ /* CCK (B) PHY Registers */ #define B43_PHY_VERSION_CCK B43_PHY_CCK(0x00) /* Versioning register for B-PHY */ #define B43_PHY_CCKBBANDCFG B43_PHY_CCK(0x01) /* Contains antenna 0/1 control bit */ #define B43_PHY_PGACTL B43_PHY_CCK(0x15) /* PGA control */ #define B43_PHY_PGACTL_LPF 0x1000 /* Low pass filter (?) */ #define B43_PHY_PGACTL_LOWBANDW 0x0040 /* Low bandwidth flag */ #define B43_PHY_PGACTL_UNKNOWN 0xEFA0 #define B43_PHY_FBCTL1 B43_PHY_CCK(0x18) /* Frequency bandwidth control 1 */ #define B43_PHY_ITSSI B43_PHY_CCK(0x29) /* Idle TSSI */ #define B43_PHY_LO_LEAKAGE B43_PHY_CCK(0x2D) /* Measured LO leakage */ #define B43_PHY_ENERGY B43_PHY_CCK(0x33) /* Energy */ #define B43_PHY_SYNCCTL B43_PHY_CCK(0x35) #define B43_PHY_FBCTL2 B43_PHY_CCK(0x38) /* Frequency bandwidth control 2 */ #define B43_PHY_DACCTL B43_PHY_CCK(0x60) /* DAC control */ #define B43_PHY_RCCALOVER B43_PHY_CCK(0x78) /* RC calibration override */ /* Extended G-PHY Registers */ #define B43_PHY_CLASSCTL B43_PHY_EXTG(0x02) /* Classify control */ #define B43_PHY_GTABCTL B43_PHY_EXTG(0x03) /* G-PHY table control (see below) */ #define B43_PHY_GTABOFF 0x03FF /* G-PHY table offset (see below) */ #define B43_PHY_GTABNR 0xFC00 /* G-PHY table number (see below) */ #define B43_PHY_GTABNR_SHIFT 10 #define B43_PHY_GTABDATA B43_PHY_EXTG(0x04) /* G-PHY table data */ #define B43_PHY_LO_MASK B43_PHY_EXTG(0x0F) /* Local Oscillator control mask */ #define B43_PHY_LO_CTL B43_PHY_EXTG(0x10) /* Local Oscillator control */ #define B43_PHY_RFOVER B43_PHY_EXTG(0x11) /* RF override */ #define B43_PHY_RFOVERVAL B43_PHY_EXTG(0x12) /* RF override value */ #define B43_PHY_RFOVERVAL_EXTLNA 0x8000 #define B43_PHY_RFOVERVAL_LNA 0x7000 #define B43_PHY_RFOVERVAL_LNA_SHIFT 12 #define B43_PHY_RFOVERVAL_PGA 0x0F00 #define B43_PHY_RFOVERVAL_PGA_SHIFT 8 #define B43_PHY_RFOVERVAL_UNK 0x0010 /* Unknown, always set. */ #define B43_PHY_RFOVERVAL_TRSWRX 0x00E0 #define B43_PHY_RFOVERVAL_BW 0x0003 /* Bandwidth flags */ #define B43_PHY_RFOVERVAL_BW_LPF 0x0001 /* Low Pass Filter */ #define B43_PHY_RFOVERVAL_BW_LBW 0x0002 /* Low Bandwidth (when set), high when unset */ #define B43_PHY_ANALOGOVER B43_PHY_EXTG(0x14) /* Analog override */ #define B43_PHY_ANALOGOVERVAL B43_PHY_EXTG(0x15) /* Analog override value */ /*** OFDM table numbers ***/ #define B43_OFDMTAB(number, offset) (((number) << B43_PHY_OTABLENR_SHIFT) | (offset)) #define B43_OFDMTAB_AGC1 B43_OFDMTAB(0x00, 0) #define B43_OFDMTAB_GAIN0 B43_OFDMTAB(0x00, 0) #define B43_OFDMTAB_GAINX B43_OFDMTAB(0x01, 0) //TODO rename #define B43_OFDMTAB_GAIN1 B43_OFDMTAB(0x01, 4) #define B43_OFDMTAB_AGC3 B43_OFDMTAB(0x02, 0) #define B43_OFDMTAB_GAIN2 B43_OFDMTAB(0x02, 3) #define B43_OFDMTAB_LNAHPFGAIN1 B43_OFDMTAB(0x03, 0) #define B43_OFDMTAB_WRSSI B43_OFDMTAB(0x04, 0) #define B43_OFDMTAB_LNAHPFGAIN2 B43_O
From 46bf067870156abd61fe24d14c2486d15b8b502c Mon Sep 17 00:00:00 2001
From: Dave Taht <dave@taht.net>
Date: Fri, 14 Dec 2018 18:38:40 +0000
Subject: [PATCH 1/1] Allow class-e address assignment in ifconfig and early
 boot

While the linux kernel became mostly "class-e clean" a decade ago,
and most distributions long ago switched to the iproute2 suite
of utilities, which allow class-e (240.0.0.0/4) address assignment,
distributions relying on busybox, toybox and other forms of
ifconfig cannot assign class-e addresses without this kernel patch.

With this patch, also, a boot command line on these addresses is feasible:
(ip=248.0.1.2::248.0.1.1:255.255.255.0).

While CIDR has been obsolete for 2 decades, and a survey of all the
userspace open source code in the world shows most IN_whatever macros
are also obsolete... rather than obsolete CIDR from this ioctl entirely,
this patch merely enables class-e assignment, sanely.

H/T to Vince Fuller and his original patch here:
    https://lkml.org/lkml/2008/1/7/370

Signed-off-by: Dave Taht <dave.taht@gmail.com>
Reviewed-by: John Gilmore <gnu@toad.com>
---
 include/uapi/linux/in.h | 8 ++++++--
 net/ipv4/devinet.c      | 4 +++-
 net/ipv4/ipconfig.c     | 2 ++
 3 files changed, 11 insertions(+), 3 deletions(-)

--- a/include/uapi/linux/in.h
+++ b/include/uapi/linux/in.h
@@ -268,8 +268,12 @@ struct sockaddr_in {
 #define	IN_MULTICAST(a)		IN_CLASSD(a)
 #define IN_MULTICAST_NET	0xF0000000
 
-#define	IN_EXPERIMENTAL(a)	((((long int) (a)) & 0xf0000000) == 0xf0000000)
-#define	IN_BADCLASS(a)		IN_EXPERIMENTAL((a))
+#define	IN_BADCLASS(a)		(((long int) (a) ) == (long int)0xffffffff)
+#define	IN_EXPERIMENTAL(a)	IN_BADCLASS((a))
+
+#define	IN_CLASSE(a)		((((long int) (a)) & 0xf0000000) == 0xf0000000)
+#define	IN_CLASSE_NET		0xffffffff
+#define	IN_CLASSE_NSHIFT	0
 
 /* Address to accept any incoming messages. */
 #define	INADDR_ANY		((unsigned long int) 0x00000000)
--- a/net/ipv4/devinet.c
+++ b/net/ipv4/devinet.c
@@ -921,7 +921,7 @@ static int inet_abc_len(__be32 addr)
 {
 	int rc = -1;	/* Something else, probably a multicast. */
 
-	if (ipv4_is_zeronet(addr))
+	if (ipv4_is_zeronet(addr) || ipv4_is_lbcast(addr))
 		rc = 0;
 	else {
 		__u32 haddr = ntohl(addr);
@@ -932,6 +932,8 @@ static int inet_abc_len(__be32 addr)
 			rc = 16;
 		else if (IN_CLASSC(haddr))
 			rc = 24;
+		else if (IN_CLASSE(haddr))
+			rc = 32;
 	}
 
 	return rc;
--- a/net/ipv4/ipconfig.c
+++ b/net/ipv4/ipconfig.c
@@ -457,6 +457,8 @@ static int __init ic_defaults(void)
 			ic_netmask = htonl(IN_CLASSB_NET);
 		else if (IN_CLASSC(ntohl(ic_myaddr)))
 			ic_netmask = htonl(IN_CLASSC_NET);
+		else if (IN_CLASSE(ntohl(ic_myaddr)))
+			ic_netmask = htonl(IN_CLASSE_NET);
 		else {
 			pr_err("IP-Config: Unable to guess netmask for address %pI4\n",
 			       &ic_myaddr);
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-11 00:05:23 +0000