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From 28ec0b7e48bb27435a8b3134019b88628faf497f Mon Sep 17 00:00:00 2001
From: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
Date: Tue, 11 Dec 2018 17:37:28 +0800
Subject: [PATCH 4/6] dt-bindings: ARM: MediaTek: Document devicetree bindings
for SPI NAND interface
Change-Id: I9ece142055ae27100da95826fb3ea1960c2994e6
Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
---
.../devicetree/bindings/spi/spi-mtk-snfi.txt | 44 +++++++++++++++++++
1 file changed, 44 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/spi-mtk-snfi.txt
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/spi-mtk-snfi.txt
@@ -0,0 +1,44 @@
+MediaTek SoCs SPI NAND FLASH interface (SNFI) DT binding
+
+This file documents the device tree bindings for MTK SoCs SPI NAND controller.
+Note that Parallel Nand and SPI NAND is alternative on MTK SoCs.
+
+Required properties:
+- compatible: should be "mediatek,mt7622-snfi"
+- reg: base physical address and size of SNFI.
+- interrupts: interrupts of SNFI.
+- clocks: SNFI required clocks.
+- clock-names: SNFI clocks internal names.
+- #address-cells: NAND chip index, should be 1.
+- #size-cells: Should be 0.
+
+Example:
+ snfi: spi@1100d000 {
+ compatible = "mediatek,mt7622-snfi";
+ reg = <0 0x1100d000 0 0x1000>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_NFI_PD>,
+ <&pericfg CLK_PERI_SNFI_PD>;
+ clock-names = "nfi_clk", "spi_clk";
+ ecc-engine = <&bch>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+Subnodes properties:
+- Should use spi-nand framework, see Documentation/devicetree/bindings/mtd/spi-nand.txt
+
+Example:
+&snfi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&serial_nand_pins>;
+ status = "okay";
+
+ spi_nand@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-nand";
+ spi-max-frequency = <104000000>;
+ reg = <0>;
+ };
+};
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