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From 9a3055dad80db43aeb22b247512e18e8f06bf54c Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Mon, 22 Apr 2013 23:11:42 +0200
Subject: [PATCH 02/33] MIPS: ralink: add pinmux driver
Add code to setup the pinmux on ralonk SoC. The SoC has a single 32 bit register
for this functionality with simple on/off bits. Building a full featured pinctrl
driver would be overkill.
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/ralink/Makefile | 2 +-
arch/mips/ralink/common.h | 2 ++
arch/mips/ralink/of.c | 2 ++
arch/mips/ralink/pinmux.c | 77 +++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 82 insertions(+), 1 deletion(-)
create mode 100644 arch/mips/ralink/pinmux.c
--- a/arch/mips/ralink/Makefile
+++ b/arch/mips/ralink/Makefile
@@ -6,7 +6,7 @@
# Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
# Copyright (C) 2013 John Crispin <blogic@openwrt.org>
-obj-y := prom.o of.o reset.o clk.o irq.o timer.o
+obj-y := prom.o of.o reset.o clk.o irq.o timer.o pinmux.o
obj-$(CONFIG_CLKEVT_RT3352) += cevt-rt3352.o
--- a/arch/mips/ralink/common.h
+++ b/arch/mips/ralink/common.h
@@ -52,4 +52,6 @@ extern void prom_soc_init(struct ralink_
__iomem void *plat_of_remap_node(const char *node);
+void ralink_pinmux(void);
+
#endif /* _RALINK_COMMON_H__ */
--- a/arch/mips/ralink/of.c
+++ b/arch/mips/ralink/of.c
@@ -113,6 +113,8 @@ static int __init plat_of_setup(void)
/* make sure ithat the reset controller is setup early */
ralink_rst_init();
+ ralink_pinmux();
+
return 0;
}
--- /dev/null
+++ b/arch/mips/ralink/pinmux.c
@@ -0,0 +1,92 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/kernel.h>
+#include <linux/of.h>
+
+#include <asm/mach-ralink/ralink_regs.h>
+
+#include "common.h"
+
+#define SYSC_REG_GPIO_MODE 0x60
+
+static int ralink_mux_mask(const char *name, struct ralink_pinmux_grp *grps, u32* mask)
+{
+ for (; grps && grps->name; grps++)
+ if (!strcmp(grps->name, name)) {
+ *mask = grps->mask;
+ return 0;
+ }
+
+ return -1;
+}
+
+void ralink_pinmux(void)
+{
+ const __be32 *wdt;
+ struct device_node *np;
+ struct property *prop;
+ const char *uart, *pci, *pin;
+ u32 mode = 0;
+ int m;
+
+ np = of_find_compatible_node(NULL, NULL, "ralink,rt3050-sysc");
+ if (!np)
+ return;
+
+ of_property_for_each_string(np, "ralink,gpiomux", prop, pin) {
+ if (!ralink_mux_mask(pin, rt_gpio_pinmux.mode, &m)) {
+ mode |= m;
+ pr_debug("pinmux: registered gpiomux \"%s\"\n", pin);
+ } else {
+ pr_err("pinmux: failed to load \"%s\"\n", pin);
+ }
+ }
+
+ of_property_for_each_string(np, "ralink,pinmux", prop, pin) {
+ if (!ralink_mux_mask(pin, rt_gpio_pinmux.mode, &m)) {
+ mode &= ~m;
+ pr_debug("pinmux: registered pinmux \"%s\"\n", pin);
+ } else {
+ pr_err("pinmux: failed to load group \"%s\"\n", pin);
+ }
+ }
+
+ of_property_read_string(np, "ralink,uartmux", &uart);
+ if (uart) {
+ mode &= ~(rt_gpio_pinmux.uart_mask << rt_gpio_pinmux.uart_shift);
+ if (ralink_mux_mask(uart, rt_gpio_pinmux.uart, &m)) {
+ pr_err("pinmux: failed to load uartmux \"%s\"\n", uart);
+ mode |= rt_gpio_pinmux.uart_mask << rt_gpio_pinmux.uart_shift;
+ } else {
+ mode |= m << rt_gpio_pinmux.uart_shift;
+ pr_debug("pinmux: registered uartmux \"%s\"\n", uart);
+ }
+ }
+
+ wdt = of_get_property(np, "ralink,wdtmux", NULL);
+ if (wdt && *wdt && rt_gpio_pinmux.wdt_reset)
+ rt_gpio_pinmux.wdt_reset();
+
+ pci = NULL;
+ if (rt_gpio_pinmux.pci)
+ of_property_read_string(np, "ralink,pcimux", &pci);
+
+ if (pci) {
+ mode &= ~(rt_gpio_pinmux.pci_mask << rt_gpio_pinmux.pci_shift);
+ if (ralink_mux_mask(pci, rt_gpio_pinmux.pci, &m)) {
+ mode |= rt_gpio_pinmux.pci_mask << rt_gpio_pinmux.pci_shift;
+ pr_debug("pinmux: failed to load pcimux \"%s\"\n", pci);
+ } else {
+ mode |= m << rt_gpio_pinmux.pci_shift;
+ pr_debug("pinmux: registered pcimux \"%s\"\n", pci);
+ }
+ }
+
+ rt_sysc_w32(mode, SYSC_REG_GPIO_MODE);
+}
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