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| author | Joey Castillo <jose.castillo@gmail.com> | 2021-07-20 14:32:49 -0400 |
|---|---|---|
| committer | Joey Castillo <jose.castillo@gmail.com> | 2021-07-20 14:32:49 -0400 |
| commit | 18054a9e8f77cd9379d09d8f03a2f6243eed027f (patch) | |
| tree | 35301d342877e43fda2a232d56b2456199551610 /Sensor Watch Starter Project/include/pio/saml22n16a.h | |
| parent | de05ad0b9593353bb1fc9cb08267679380d3b8d2 (diff) | |
| download | Sensor-Watch-18054a9e8f77cd9379d09d8f03a2f6243eed027f.tar.gz Sensor-Watch-18054a9e8f77cd9379d09d8f03a2f6243eed027f.tar.bz2 Sensor-Watch-18054a9e8f77cd9379d09d8f03a2f6243eed027f.zip | |
move to a makefile based workflow
Diffstat (limited to 'Sensor Watch Starter Project/include/pio/saml22n16a.h')
| -rwxr-xr-x | Sensor Watch Starter Project/include/pio/saml22n16a.h | 1789 |
1 files changed, 1789 insertions, 0 deletions
diff --git a/Sensor Watch Starter Project/include/pio/saml22n16a.h b/Sensor Watch Starter Project/include/pio/saml22n16a.h new file mode 100755 index 00000000..87834efb --- /dev/null +++ b/Sensor Watch Starter Project/include/pio/saml22n16a.h @@ -0,0 +1,1789 @@ +/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAML22N16A
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAML22N16A_PIO_
+#define _SAML22N16A_PIO_
+
+#define PIN_PA00 0 /**< \brief Pin Number for PA00 */
+#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */
+#define PIN_PA01 1 /**< \brief Pin Number for PA01 */
+#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */
+#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
+#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */
+#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
+#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */
+#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
+#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */
+#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
+#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */
+#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
+#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */
+#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
+#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */
+#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
+#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */
+#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
+#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */
+#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
+#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */
+#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
+#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */
+#define PIN_PA12 12 /**< \brief Pin Number for PA12 */
+#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */
+#define PIN_PA13 13 /**< \brief Pin Number for PA13 */
+#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */
+#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
+#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */
+#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
+#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */
+#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
+#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */
+#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
+#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */
+#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
+#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */
+#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
+#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */
+#define PIN_PA20 20 /**< \brief Pin Number for PA20 */
+#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */
+#define PIN_PA21 21 /**< \brief Pin Number for PA21 */
+#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */
+#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
+#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */
+#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
+#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */
+#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
+#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */
+#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
+#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */
+#define PIN_PA27 27 /**< \brief Pin Number for PA27 */
+#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */
+#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
+#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */
+#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
+#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */
+#define PIN_PB00 32 /**< \brief Pin Number for PB00 */
+#define PORT_PB00 (1ul << 0) /**< \brief PORT Mask for PB00 */
+#define PIN_PB01 33 /**< \brief Pin Number for PB01 */
+#define PORT_PB01 (1ul << 1) /**< \brief PORT Mask for PB01 */
+#define PIN_PB02 34 /**< \brief Pin Number for PB02 */
+#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */
+#define PIN_PB03 35 /**< \brief Pin Number for PB03 */
+#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */
+#define PIN_PB04 36 /**< \brief Pin Number for PB04 */
+#define PORT_PB04 (1ul << 4) /**< \brief PORT Mask for PB04 */
+#define PIN_PB05 37 /**< \brief Pin Number for PB05 */
+#define PORT_PB05 (1ul << 5) /**< \brief PORT Mask for PB05 */
+#define PIN_PB06 38 /**< \brief Pin Number for PB06 */
+#define PORT_PB06 (1ul << 6) /**< \brief PORT Mask for PB06 */
+#define PIN_PB07 39 /**< \brief Pin Number for PB07 */
+#define PORT_PB07 (1ul << 7) /**< \brief PORT Mask for PB07 */
+#define PIN_PB08 40 /**< \brief Pin Number for PB08 */
+#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */
+#define PIN_PB09 41 /**< \brief Pin Number for PB09 */
+#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */
+#define PIN_PB11 43 /**< \brief Pin Number for PB11 */
+#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */
+#define PIN_PB12 44 /**< \brief Pin Number for PB12 */
+#define PORT_PB12 (1ul << 12) /**< \brief PORT Mask for PB12 */
+#define PIN_PB13 45 /**< \brief Pin Number for PB13 */
+#define PORT_PB13 (1ul << 13) /**< \brief PORT Mask for PB13 */
+#define PIN_PB14 46 /**< \brief Pin Number for PB14 */
+#define PORT_PB14 (1ul << 14) /**< \brief PORT Mask for PB14 */
+#define PIN_PB15 47 /**< \brief Pin Number for PB15 */
+#define PORT_PB15 (1ul << 15) /**< \brief PORT Mask for PB15 */
+#define PIN_PB16 48 /**< \brief Pin Number for PB16 */
+#define PORT_PB16 (1ul << 16) /**< \brief PORT Mask for PB16 */
+#define PIN_PB17 49 /**< \brief Pin Number for PB17 */
+#define PORT_PB17 (1ul << 17) /**< \brief PORT Mask for PB17 */
+#define PIN_PB18 50 /**< \brief Pin Number for PB18 */
+#define PORT_PB18 (1ul << 18) /**< \brief PORT Mask for PB18 */
+#define PIN_PB19 51 /**< \brief Pin Number for PB19 */
+#define PORT_PB19 (1ul << 19) /**< \brief PORT Mask for PB19 */
+#define PIN_PB20 52 /**< \brief Pin Number for PB20 */
+#define PORT_PB20 (1ul << 20) /**< \brief PORT Mask for PB20 */
+#define PIN_PB21 53 /**< \brief Pin Number for PB21 */
+#define PORT_PB21 (1ul << 21) /**< \brief PORT Mask for PB21 */
+#define PIN_PB22 54 /**< \brief Pin Number for PB22 */
+#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */
+#define PIN_PB23 55 /**< \brief Pin Number for PB23 */
+#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */
+#define PIN_PB24 56 /**< \brief Pin Number for PB24 */
+#define PORT_PB24 (1ul << 24) /**< \brief PORT Mask for PB24 */
+#define PIN_PB25 57 /**< \brief Pin Number for PB25 */
+#define PORT_PB25 (1ul << 25) /**< \brief PORT Mask for PB25 */
+#define PIN_PB30 62 /**< \brief Pin Number for PB30 */
+#define PORT_PB30 (1ul << 30) /**< \brief PORT Mask for PB30 */
+#define PIN_PB31 63 /**< \brief Pin Number for PB31 */
+#define PORT_PB31 (1ul << 31) /**< \brief PORT Mask for PB31 */
+#define PIN_PC00 64 /**< \brief Pin Number for PC00 */
+#define PORT_PC00 (1ul << 0) /**< \brief PORT Mask for PC00 */
+#define PIN_PC01 65 /**< \brief Pin Number for PC01 */
+#define PORT_PC01 (1ul << 1) /**< \brief PORT Mask for PC01 */
+#define PIN_PC02 66 /**< \brief Pin Number for PC02 */
+#define PORT_PC02 (1ul << 2) /**< \brief PORT Mask for PC02 */
+#define PIN_PC03 67 /**< \brief Pin Number for PC03 */
+#define PORT_PC03 (1ul << 3) /**< \brief PORT Mask for PC03 */
+#define PIN_PC05 69 /**< \brief Pin Number for PC05 */
+#define PORT_PC05 (1ul << 5) /**< \brief PORT Mask for PC05 */
+#define PIN_PC06 70 /**< \brief Pin Number for PC06 */
+#define PORT_PC06 (1ul << 6) /**< \brief PORT Mask for PC06 */
+#define PIN_PC07 71 /**< \brief Pin Number for PC07 */
+#define PORT_PC07 (1ul << 7) /**< \brief PORT Mask for PC07 */
+#define PIN_PC08 72 /**< \brief Pin Number for PC08 */
+#define PORT_PC08 (1ul << 8) /**< \brief PORT Mask for PC08 */
+#define PIN_PC09 73 /**< \brief Pin Number for PC09 */
+#define PORT_PC09 (1ul << 9) /**< \brief PORT Mask for PC09 */
+#define PIN_PC10 74 /**< \brief Pin Number for PC10 */
+#define PORT_PC10 (1ul << 10) /**< \brief PORT Mask for PC10 */
+#define PIN_PC11 75 /**< \brief Pin Number for PC11 */
+#define PORT_PC11 (1ul << 11) /**< \brief PORT Mask for PC11 */
+#define PIN_PC12 76 /**< \brief Pin Number for PC12 */
+#define PORT_PC12 (1ul << 12) /**< \brief PORT Mask for PC12 */
+#define PIN_PC13 77 /**< \brief Pin Number for PC13 */
+#define PORT_PC13 (1ul << 13) /**< \brief PORT Mask for PC13 */
+#define PIN_PC14 78 /**< \brief Pin Number for PC14 */
+#define PORT_PC14 (1ul << 14) /**< \brief PORT Mask for PC14 */
+#define PIN_PC15 79 /**< \brief Pin Number for PC15 */
+#define PORT_PC15 (1ul << 15) /**< \brief PORT Mask for PC15 */
+#define PIN_PC16 80 /**< \brief Pin Number for PC16 */
+#define PORT_PC16 (1ul << 16) /**< \brief PORT Mask for PC16 */
+#define PIN_PC17 81 /**< \brief Pin Number for PC17 */
+#define PORT_PC17 (1ul << 17) /**< \brief PORT Mask for PC17 */
+#define PIN_PC18 82 /**< \brief Pin Number for PC18 */
+#define PORT_PC18 (1ul << 18) /**< \brief PORT Mask for PC18 */
+#define PIN_PC19 83 /**< \brief Pin Number for PC19 */
+#define PORT_PC19 (1ul << 19) /**< \brief PORT Mask for PC19 */
+#define PIN_PC20 84 /**< \brief Pin Number for PC20 */
+#define PORT_PC20 (1ul << 20) /**< \brief PORT Mask for PC20 */
+#define PIN_PC21 85 /**< \brief Pin Number for PC21 */
+#define PORT_PC21 (1ul << 21) /**< \brief PORT Mask for PC21 */
+#define PIN_PC24 88 /**< \brief Pin Number for PC24 */
+#define PORT_PC24 (1ul << 24) /**< \brief PORT Mask for PC24 */
+#define PIN_PC25 89 /**< \brief Pin Number for PC25 */
+#define PORT_PC25 (1ul << 25) /**< \brief PORT Mask for PC25 */
+#define PIN_PC26 90 /**< \brief Pin Number for PC26 */
+#define PORT_PC26 (1ul << 26) /**< \brief PORT Mask for PC26 */
+#define PIN_PC27 91 /**< \brief Pin Number for PC27 */
+#define PORT_PC27 (1ul << 27) /**< \brief PORT Mask for PC27 */
+#define PIN_PC28 92 /**< \brief Pin Number for PC28 */
+#define PORT_PC28 (1ul << 28) /**< \brief PORT Mask for PC28 */
+/* ========== PORT definition for SUPC peripheral ========== */
+#define PIN_PB01H_SUPC_OUT0 33L /**< \brief SUPC signal: OUT0 on PB01 mux H */
+#define MUX_PB01H_SUPC_OUT0 7L
+#define PINMUX_PB01H_SUPC_OUT0 ((PIN_PB01H_SUPC_OUT0 << 16) | MUX_PB01H_SUPC_OUT0)
+#define PORT_PB01H_SUPC_OUT0 (1ul << 1)
+#define PIN_PB02H_SUPC_OUT1 34L /**< \brief SUPC signal: OUT1 on PB02 mux H */
+#define MUX_PB02H_SUPC_OUT1 7L
+#define PINMUX_PB02H_SUPC_OUT1 ((PIN_PB02H_SUPC_OUT1 << 16) | MUX_PB02H_SUPC_OUT1)
+#define PORT_PB02H_SUPC_OUT1 (1ul << 2)
+#define PIN_PB00H_SUPC_PSOK 32L /**< \brief SUPC signal: PSOK on PB00 mux H */
+#define MUX_PB00H_SUPC_PSOK 7L
+#define PINMUX_PB00H_SUPC_PSOK ((PIN_PB00H_SUPC_PSOK << 16) | MUX_PB00H_SUPC_PSOK)
+#define PORT_PB00H_SUPC_PSOK (1ul << 0)
+#define PIN_PB03H_SUPC_VBAT 35L /**< \brief SUPC signal: VBAT on PB03 mux H */
+#define MUX_PB03H_SUPC_VBAT 7L
+#define PINMUX_PB03H_SUPC_VBAT ((PIN_PB03H_SUPC_VBAT << 16) | MUX_PB03H_SUPC_VBAT)
+#define PORT_PB03H_SUPC_VBAT (1ul << 3)
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB14H_GCLK_IO0 46L /**< \brief GCLK signal: IO0 on PB14 mux H */
+#define MUX_PB14H_GCLK_IO0 7L
+#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0)
+#define PORT_PB14H_GCLK_IO0 (1ul << 14)
+#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0 7L
+#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0 (1ul << 22)
+#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0 7L
+#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0 (1ul << 14)
+#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0 7L
+#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0 (1ul << 27)
+#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0 7L
+#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0 (1ul << 30)
+#define PIN_PB15H_GCLK_IO1 47L /**< \brief GCLK signal: IO1 on PB15 mux H */
+#define MUX_PB15H_GCLK_IO1 7L
+#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
+#define PORT_PB15H_GCLK_IO1 (1ul << 15)
+#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1 7L
+#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1 (1ul << 23)
+#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1 7L
+#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1 (1ul << 15)
+#define PIN_PB16H_GCLK_IO2 48L /**< \brief GCLK signal: IO2 on PB16 mux H */
+#define MUX_PB16H_GCLK_IO2 7L
+#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2)
+#define PORT_PB16H_GCLK_IO2 (1ul << 16)
+#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2 7L
+#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2 (1ul << 16)
+#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3 7L
+#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3 (1ul << 17)
+#define PIN_PB17H_GCLK_IO3 49L /**< \brief GCLK signal: IO3 on PB17 mux H */
+#define MUX_PB17H_GCLK_IO3 7L
+#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3)
+#define PORT_PB17H_GCLK_IO3 (1ul << 17)
+#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4 7L
+#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4 (1ul << 10)
+#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4 7L
+#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4 (1ul << 20)
+/* ========== PORT definition for RTC peripheral ========== */
+#define PIN_PB00G_RTC_IN0 32L /**< \brief RTC signal: IN0 on PB00 mux G */
+#define MUX_PB00G_RTC_IN0 6L
+#define PINMUX_PB00G_RTC_IN0 ((PIN_PB00G_RTC_IN0 << 16) | MUX_PB00G_RTC_IN0)
+#define PORT_PB00G_RTC_IN0 (1ul << 0)
+#define PIN_PB02G_RTC_IN1 34L /**< \brief RTC signal: IN1 on PB02 mux G */
+#define MUX_PB02G_RTC_IN1 6L
+#define PINMUX_PB02G_RTC_IN1 ((PIN_PB02G_RTC_IN1 << 16) | MUX_PB02G_RTC_IN1)
+#define PORT_PB02G_RTC_IN1 (1ul << 2)
+#define PIN_PA02G_RTC_IN2 2L /**< \brief RTC signal: IN2 on PA02 mux G */
+#define MUX_PA02G_RTC_IN2 6L
+#define PINMUX_PA02G_RTC_IN2 ((PIN_PA02G_RTC_IN2 << 16) | MUX_PA02G_RTC_IN2)
+#define PORT_PA02G_RTC_IN2 (1ul << 2)
+#define PIN_PB01F_RTC_IN2 33L /**< \brief RTC signal: IN2 on PB01 mux F */
+#define MUX_PB01F_RTC_IN2 5L
+#define PINMUX_PB01F_RTC_IN2 ((PIN_PB01F_RTC_IN2 << 16) | MUX_PB01F_RTC_IN2)
+#define PORT_PB01F_RTC_IN2 (1ul << 1)
+#define PIN_PC00G_RTC_IN3 64L /**< \brief RTC signal: IN3 on PC00 mux G */
+#define MUX_PC00G_RTC_IN3 6L
+#define PINMUX_PC00G_RTC_IN3 ((PIN_PC00G_RTC_IN3 << 16) | MUX_PC00G_RTC_IN3)
+#define PORT_PC00G_RTC_IN3 (1ul << 0)
+#define PIN_PC01G_RTC_IN4 65L /**< \brief RTC signal: IN4 on PC01 mux G */
+#define MUX_PC01G_RTC_IN4 6L
+#define PINMUX_PC01G_RTC_IN4 ((PIN_PC01G_RTC_IN4 << 16) | MUX_PC01G_RTC_IN4)
+#define PORT_PC01G_RTC_IN4 (1ul << 1)
+#define PIN_PB01G_RTC_OUT 33L /**< \brief RTC signal: OUT on PB01 mux G */
+#define MUX_PB01G_RTC_OUT 6L
+#define PINMUX_PB01G_RTC_OUT ((PIN_PB01G_RTC_OUT << 16) | MUX_PB01G_RTC_OUT)
+#define PORT_PB01G_RTC_OUT (1ul << 1)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0 0L
+#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0 (1ul << 16)
+#define PIN_PB00A_EIC_EXTINT0 32L /**< \brief EIC signal: EXTINT0 on PB00 mux A */
+#define MUX_PB00A_EIC_EXTINT0 0L
+#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
+#define PORT_PB00A_EIC_EXTINT0 (1ul << 0)
+#define PIN_PB16A_EIC_EXTINT0 48L /**< \brief EIC signal: EXTINT0 on PB16 mux A */
+#define MUX_PB16A_EIC_EXTINT0 0L
+#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)
+#define PORT_PB16A_EIC_EXTINT0 (1ul << 16)
+#define PIN_PC08A_EIC_EXTINT0 72L /**< \brief EIC signal: EXTINT0 on PC08 mux A */
+#define MUX_PC08A_EIC_EXTINT0 0L
+#define PINMUX_PC08A_EIC_EXTINT0 ((PIN_PC08A_EIC_EXTINT0 << 16) | MUX_PC08A_EIC_EXTINT0)
+#define PORT_PC08A_EIC_EXTINT0 (1ul << 8)
+#define PIN_PC24A_EIC_EXTINT0 88L /**< \brief EIC signal: EXTINT0 on PC24 mux A */
+#define MUX_PC24A_EIC_EXTINT0 0L
+#define PINMUX_PC24A_EIC_EXTINT0 ((PIN_PC24A_EIC_EXTINT0 << 16) | MUX_PC24A_EIC_EXTINT0)
+#define PORT_PC24A_EIC_EXTINT0 (1ul << 24)
+#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0 0L
+#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0 (1ul << 0)
+#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1 0L
+#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1 (1ul << 17)
+#define PIN_PB01A_EIC_EXTINT1 33L /**< \brief EIC signal: EXTINT1 on PB01 mux A */
+#define MUX_PB01A_EIC_EXTINT1 0L
+#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
+#define PORT_PB01A_EIC_EXTINT1 (1ul << 1)
+#define PIN_PB17A_EIC_EXTINT1 49L /**< \brief EIC signal: EXTINT1 on PB17 mux A */
+#define MUX_PB17A_EIC_EXTINT1 0L
+#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)
+#define PORT_PB17A_EIC_EXTINT1 (1ul << 17)
+#define PIN_PC09A_EIC_EXTINT1 73L /**< \brief EIC signal: EXTINT1 on PC09 mux A */
+#define MUX_PC09A_EIC_EXTINT1 0L
+#define PINMUX_PC09A_EIC_EXTINT1 ((PIN_PC09A_EIC_EXTINT1 << 16) | MUX_PC09A_EIC_EXTINT1)
+#define PORT_PC09A_EIC_EXTINT1 (1ul << 9)
+#define PIN_PC25A_EIC_EXTINT1 89L /**< \brief EIC signal: EXTINT1 on PC25 mux A */
+#define MUX_PC25A_EIC_EXTINT1 0L
+#define PINMUX_PC25A_EIC_EXTINT1 ((PIN_PC25A_EIC_EXTINT1 << 16) | MUX_PC25A_EIC_EXTINT1)
+#define PORT_PC25A_EIC_EXTINT1 (1ul << 25)
+#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1 0L
+#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1 (1ul << 1)
+#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2 0L
+#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2 (1ul << 2)
+#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2 0L
+#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2 (1ul << 18)
+#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2 0L
+#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2 (1ul << 2)
+#define PIN_PB18A_EIC_EXTINT2 50L /**< \brief EIC signal: EXTINT2 on PB18 mux A */
+#define MUX_PB18A_EIC_EXTINT2 0L
+#define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2)
+#define PORT_PB18A_EIC_EXTINT2 (1ul << 18)
+#define PIN_PC10A_EIC_EXTINT2 74L /**< \brief EIC signal: EXTINT2 on PC10 mux A */
+#define MUX_PC10A_EIC_EXTINT2 0L
+#define PINMUX_PC10A_EIC_EXTINT2 ((PIN_PC10A_EIC_EXTINT2 << 16) | MUX_PC10A_EIC_EXTINT2)
+#define PORT_PC10A_EIC_EXTINT2 (1ul << 10)
+#define PIN_PC26A_EIC_EXTINT2 90L /**< \brief EIC signal: EXTINT2 on PC26 mux A */
+#define MUX_PC26A_EIC_EXTINT2 0L
+#define PINMUX_PC26A_EIC_EXTINT2 ((PIN_PC26A_EIC_EXTINT2 << 16) | MUX_PC26A_EIC_EXTINT2)
+#define PORT_PC26A_EIC_EXTINT2 (1ul << 26)
+#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3 0L
+#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3 (1ul << 3)
+#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3 0L
+#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3 (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3 0L
+#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3 (1ul << 3)
+#define PIN_PB19A_EIC_EXTINT3 51L /**< \brief EIC signal: EXTINT3 on PB19 mux A */
+#define MUX_PB19A_EIC_EXTINT3 0L
+#define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3)
+#define PORT_PB19A_EIC_EXTINT3 (1ul << 19)
+#define PIN_PC11A_EIC_EXTINT3 75L /**< \brief EIC signal: EXTINT3 on PC11 mux A */
+#define MUX_PC11A_EIC_EXTINT3 0L
+#define PINMUX_PC11A_EIC_EXTINT3 ((PIN_PC11A_EIC_EXTINT3 << 16) | MUX_PC11A_EIC_EXTINT3)
+#define PORT_PC11A_EIC_EXTINT3 (1ul << 11)
+#define PIN_PC27A_EIC_EXTINT3 91L /**< \brief EIC signal: EXTINT3 on PC27 mux A */
+#define MUX_PC27A_EIC_EXTINT3 0L
+#define PINMUX_PC27A_EIC_EXTINT3 ((PIN_PC27A_EIC_EXTINT3 << 16) | MUX_PC27A_EIC_EXTINT3)
+#define PORT_PC27A_EIC_EXTINT3 (1ul << 27)
+#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4 0L
+#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4 (1ul << 4)
+#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4 0L
+#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4 (1ul << 20)
+#define PIN_PB04A_EIC_EXTINT4 36L /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4 0L
+#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4 (1ul << 4)
+#define PIN_PB20A_EIC_EXTINT4 52L /**< \brief EIC signal: EXTINT4 on PB20 mux A */
+#define MUX_PB20A_EIC_EXTINT4 0L
+#define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4)
+#define PORT_PB20A_EIC_EXTINT4 (1ul << 20)
+#define PIN_PC12A_EIC_EXTINT4 76L /**< \brief EIC signal: EXTINT4 on PC12 mux A */
+#define MUX_PC12A_EIC_EXTINT4 0L
+#define PINMUX_PC12A_EIC_EXTINT4 ((PIN_PC12A_EIC_EXTINT4 << 16) | MUX_PC12A_EIC_EXTINT4)
+#define PORT_PC12A_EIC_EXTINT4 (1ul << 12)
+#define PIN_PC28A_EIC_EXTINT4 92L /**< \brief EIC signal: EXTINT4 on PC28 mux A */
+#define MUX_PC28A_EIC_EXTINT4 0L
+#define PINMUX_PC28A_EIC_EXTINT4 ((PIN_PC28A_EIC_EXTINT4 << 16) | MUX_PC28A_EIC_EXTINT4)
+#define PORT_PC28A_EIC_EXTINT4 (1ul << 28)
+#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5 0L
+#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5 (1ul << 5)
+#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5 0L
+#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5 (1ul << 21)
+#define PIN_PB05A_EIC_EXTINT5 37L /**< \brief EIC signal: EXTINT5 on PB05 mux A */
+#define MUX_PB05A_EIC_EXTINT5 0L
+#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
+#define PORT_PB05A_EIC_EXTINT5 (1ul << 5)
+#define PIN_PB21A_EIC_EXTINT5 53L /**< \brief EIC signal: EXTINT5 on PB21 mux A */
+#define MUX_PB21A_EIC_EXTINT5 0L
+#define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5)
+#define PORT_PB21A_EIC_EXTINT5 (1ul << 21)
+#define PIN_PC13A_EIC_EXTINT5 77L /**< \brief EIC signal: EXTINT5 on PC13 mux A */
+#define MUX_PC13A_EIC_EXTINT5 0L
+#define PINMUX_PC13A_EIC_EXTINT5 ((PIN_PC13A_EIC_EXTINT5 << 16) | MUX_PC13A_EIC_EXTINT5)
+#define PORT_PC13A_EIC_EXTINT5 (1ul << 13)
+#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6 0L
+#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6 (1ul << 6)
+#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6 0L
+#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6 (1ul << 22)
+#define PIN_PB06A_EIC_EXTINT6 38L /**< \brief EIC signal: EXTINT6 on PB06 mux A */
+#define MUX_PB06A_EIC_EXTINT6 0L
+#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
+#define PORT_PB06A_EIC_EXTINT6 (1ul << 6)
+#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6 0L
+#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6 (1ul << 22)
+#define PIN_PC14A_EIC_EXTINT6 78L /**< \brief EIC signal: EXTINT6 on PC14 mux A */
+#define MUX_PC14A_EIC_EXTINT6 0L
+#define PINMUX_PC14A_EIC_EXTINT6 ((PIN_PC14A_EIC_EXTINT6 << 16) | MUX_PC14A_EIC_EXTINT6)
+#define PORT_PC14A_EIC_EXTINT6 (1ul << 14)
+#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7 0L
+#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7 (1ul << 7)
+#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7 0L
+#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7 (1ul << 23)
+#define PIN_PB07A_EIC_EXTINT7 39L /**< \brief EIC signal: EXTINT7 on PB07 mux A */
+#define MUX_PB07A_EIC_EXTINT7 0L
+#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)
+#define PORT_PB07A_EIC_EXTINT7 (1ul << 7)
+#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7 0L
+#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7 (1ul << 23)
+#define PIN_PC15A_EIC_EXTINT7 79L /**< \brief EIC signal: EXTINT7 on PC15 mux A */
+#define MUX_PC15A_EIC_EXTINT7 0L
+#define PINMUX_PC15A_EIC_EXTINT7 ((PIN_PC15A_EIC_EXTINT7 << 16) | MUX_PC15A_EIC_EXTINT7)
+#define PORT_PC15A_EIC_EXTINT7 (1ul << 15)
+#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8 0L
+#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8 (1ul << 8)
+#define PIN_PB24A_EIC_EXTINT8 56L /**< \brief EIC signal: EXTINT8 on PB24 mux A */
+#define MUX_PB24A_EIC_EXTINT8 0L
+#define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8)
+#define PORT_PB24A_EIC_EXTINT8 (1ul << 24)
+#define PIN_PC00A_EIC_EXTINT8 64L /**< \brief EIC signal: EXTINT8 on PC00 mux A */
+#define MUX_PC00A_EIC_EXTINT8 0L
+#define PINMUX_PC00A_EIC_EXTINT8 ((PIN_PC00A_EIC_EXTINT8 << 16) | MUX_PC00A_EIC_EXTINT8)
+#define PORT_PC00A_EIC_EXTINT8 (1ul << 0)
+#define PIN_PC16A_EIC_EXTINT8 80L /**< \brief EIC signal: EXTINT8 on PC16 mux A */
+#define MUX_PC16A_EIC_EXTINT8 0L
+#define PINMUX_PC16A_EIC_EXTINT8 ((PIN_PC16A_EIC_EXTINT8 << 16) | MUX_PC16A_EIC_EXTINT8)
+#define PORT_PC16A_EIC_EXTINT8 (1ul << 16)
+#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9 0L
+#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9 (1ul << 9)
+#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9 0L
+#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9 (1ul << 9)
+#define PIN_PB25A_EIC_EXTINT9 57L /**< \brief EIC signal: EXTINT9 on PB25 mux A */
+#define MUX_PB25A_EIC_EXTINT9 0L
+#define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9)
+#define PORT_PB25A_EIC_EXTINT9 (1ul << 25)
+#define PIN_PC01A_EIC_EXTINT9 65L /**< \brief EIC signal: EXTINT9 on PC01 mux A */
+#define MUX_PC01A_EIC_EXTINT9 0L
+#define PINMUX_PC01A_EIC_EXTINT9 ((PIN_PC01A_EIC_EXTINT9 << 16) | MUX_PC01A_EIC_EXTINT9)
+#define PORT_PC01A_EIC_EXTINT9 (1ul << 1)
+#define PIN_PC17A_EIC_EXTINT9 81L /**< \brief EIC signal: EXTINT9 on PC17 mux A */
+#define MUX_PC17A_EIC_EXTINT9 0L
+#define PINMUX_PC17A_EIC_EXTINT9 ((PIN_PC17A_EIC_EXTINT9 << 16) | MUX_PC17A_EIC_EXTINT9)
+#define PORT_PC17A_EIC_EXTINT9 (1ul << 17)
+#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10 0L
+#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10 (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10 0L
+#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10 (1ul << 30)
+#define PIN_PC02A_EIC_EXTINT10 66L /**< \brief EIC signal: EXTINT10 on PC02 mux A */
+#define MUX_PC02A_EIC_EXTINT10 0L
+#define PINMUX_PC02A_EIC_EXTINT10 ((PIN_PC02A_EIC_EXTINT10 << 16) | MUX_PC02A_EIC_EXTINT10)
+#define PORT_PC02A_EIC_EXTINT10 (1ul << 2)
+#define PIN_PC18A_EIC_EXTINT10 82L /**< \brief EIC signal: EXTINT10 on PC18 mux A */
+#define MUX_PC18A_EIC_EXTINT10 0L
+#define PINMUX_PC18A_EIC_EXTINT10 ((PIN_PC18A_EIC_EXTINT10 << 16) | MUX_PC18A_EIC_EXTINT10)
+#define PORT_PC18A_EIC_EXTINT10 (1ul << 18)
+#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11 0L
+#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11 (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11 0L
+#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11 (1ul << 31)
+#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11 0L
+#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11 (1ul << 11)
+#define PIN_PC03A_EIC_EXTINT11 67L /**< \brief EIC signal: EXTINT11 on PC03 mux A */
+#define MUX_PC03A_EIC_EXTINT11 0L
+#define PINMUX_PC03A_EIC_EXTINT11 ((PIN_PC03A_EIC_EXTINT11 << 16) | MUX_PC03A_EIC_EXTINT11)
+#define PORT_PC03A_EIC_EXTINT11 (1ul << 3)
+#define PIN_PC19A_EIC_EXTINT11 83L /**< \brief EIC signal: EXTINT11 on PC19 mux A */
+#define MUX_PC19A_EIC_EXTINT11 0L
+#define PINMUX_PC19A_EIC_EXTINT11 ((PIN_PC19A_EIC_EXTINT11 << 16) | MUX_PC19A_EIC_EXTINT11)
+#define PORT_PC19A_EIC_EXTINT11 (1ul << 19)
+#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12 0L
+#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12 (1ul << 12)
+#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12 0L
+#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12 (1ul << 24)
+#define PIN_PB12A_EIC_EXTINT12 44L /**< \brief EIC signal: EXTINT12 on PB12 mux A */
+#define MUX_PB12A_EIC_EXTINT12 0L
+#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)
+#define PORT_PB12A_EIC_EXTINT12 (1ul << 12)
+#define PIN_PC20A_EIC_EXTINT12 84L /**< \brief EIC signal: EXTINT12 on PC20 mux A */
+#define MUX_PC20A_EIC_EXTINT12 0L
+#define PINMUX_PC20A_EIC_EXTINT12 ((PIN_PC20A_EIC_EXTINT12 << 16) | MUX_PC20A_EIC_EXTINT12)
+#define PORT_PC20A_EIC_EXTINT12 (1ul << 20)
+#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13 0L
+#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13 (1ul << 13)
+#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13 0L
+#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13 (1ul << 25)
+#define PIN_PB13A_EIC_EXTINT13 45L /**< \brief EIC signal: EXTINT13 on PB13 mux A */
+#define MUX_PB13A_EIC_EXTINT13 0L
+#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)
+#define PORT_PB13A_EIC_EXTINT13 (1ul << 13)
+#define PIN_PC05A_EIC_EXTINT13 69L /**< \brief EIC signal: EXTINT13 on PC05 mux A */
+#define MUX_PC05A_EIC_EXTINT13 0L
+#define PINMUX_PC05A_EIC_EXTINT13 ((PIN_PC05A_EIC_EXTINT13 << 16) | MUX_PC05A_EIC_EXTINT13)
+#define PORT_PC05A_EIC_EXTINT13 (1ul << 5)
+#define PIN_PC21A_EIC_EXTINT13 85L /**< \brief EIC signal: EXTINT13 on PC21 mux A */
+#define MUX_PC21A_EIC_EXTINT13 0L
+#define PINMUX_PC21A_EIC_EXTINT13 ((PIN_PC21A_EIC_EXTINT13 << 16) | MUX_PC21A_EIC_EXTINT13)
+#define PORT_PC21A_EIC_EXTINT13 (1ul << 21)
+#define PIN_PB14A_EIC_EXTINT14 46L /**< \brief EIC signal: EXTINT14 on PB14 mux A */
+#define MUX_PB14A_EIC_EXTINT14 0L
+#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)
+#define PORT_PB14A_EIC_EXTINT14 (1ul << 14)
+#define PIN_PB30A_EIC_EXTINT14 62L /**< \brief EIC signal: EXTINT14 on PB30 mux A */
+#define MUX_PB30A_EIC_EXTINT14 0L
+#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)
+#define PORT_PB30A_EIC_EXTINT14 (1ul << 30)
+#define PIN_PC06A_EIC_EXTINT14 70L /**< \brief EIC signal: EXTINT14 on PC06 mux A */
+#define MUX_PC06A_EIC_EXTINT14 0L
+#define PINMUX_PC06A_EIC_EXTINT14 ((PIN_PC06A_EIC_EXTINT14 << 16) | MUX_PC06A_EIC_EXTINT14)
+#define PORT_PC06A_EIC_EXTINT14 (1ul << 6)
+#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14 0L
+#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14 (1ul << 14)
+#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15 0L
+#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15 (1ul << 27)
+#define PIN_PB15A_EIC_EXTINT15 47L /**< \brief EIC signal: EXTINT15 on PB15 mux A */
+#define MUX_PB15A_EIC_EXTINT15 0L
+#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)
+#define PORT_PB15A_EIC_EXTINT15 (1ul << 15)
+#define PIN_PB31A_EIC_EXTINT15 63L /**< \brief EIC signal: EXTINT15 on PB31 mux A */
+#define MUX_PB31A_EIC_EXTINT15 0L
+#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)
+#define PORT_PB31A_EIC_EXTINT15 (1ul << 31)
+#define PIN_PC07A_EIC_EXTINT15 71L /**< \brief EIC signal: EXTINT15 on PC07 mux A */
+#define MUX_PC07A_EIC_EXTINT15 0L
+#define PINMUX_PC07A_EIC_EXTINT15 ((PIN_PC07A_EIC_EXTINT15 << 16) | MUX_PC07A_EIC_EXTINT15)
+#define PORT_PC07A_EIC_EXTINT15 (1ul << 7)
+#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15 0L
+#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15 (1ul << 15)
+#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI 0L
+#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI (1ul << 8)
+/* ========== PORT definition for TAL peripheral ========== */
+#define PIN_PA27G_TAL_BRK 27L /**< \brief TAL signal: BRK on PA27 mux G */
+#define MUX_PA27G_TAL_BRK 6L
+#define PINMUX_PA27G_TAL_BRK ((PIN_PA27G_TAL_BRK << 16) | MUX_PA27G_TAL_BRK)
+#define PORT_PA27G_TAL_BRK (1ul << 27)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM 6L
+#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM (1ul << 24)
+#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP 6L
+#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ 6L
+#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23)
+#define PIN_PB22G_USB_SOF_1KHZ 54L /**< \brief USB signal: SOF_1KHZ on PB22 mux G */
+#define MUX_PB22G_USB_SOF_1KHZ 6L
+#define PINMUX_PB22G_USB_SOF_1KHZ ((PIN_PB22G_USB_SOF_1KHZ << 16) | MUX_PB22G_USB_SOF_1KHZ)
+#define PORT_PB22G_USB_SOF_1KHZ (1ul << 22)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0 3L
+#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4)
+#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0 2L
+#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8)
+#define PIN_PA20C_SERCOM0_PAD0 20L /**< \brief SERCOM0 signal: PAD0 on PA20 mux C */
+#define MUX_PA20C_SERCOM0_PAD0 2L
+#define PINMUX_PA20C_SERCOM0_PAD0 ((PIN_PA20C_SERCOM0_PAD0 << 16) | MUX_PA20C_SERCOM0_PAD0)
+#define PORT_PA20C_SERCOM0_PAD0 (1ul << 20)
+#define PIN_PB24C_SERCOM0_PAD0 56L /**< \brief SERCOM0 signal: PAD0 on PB24 mux C */
+#define MUX_PB24C_SERCOM0_PAD0 2L
+#define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0)
+#define PORT_PB24C_SERCOM0_PAD0 (1ul << 24)
+#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1 3L
+#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5)
+#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1 2L
+#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9)
+#define PIN_PA21C_SERCOM0_PAD1 21L /**< \brief SERCOM0 signal: PAD1 on PA21 mux C */
+#define MUX_PA21C_SERCOM0_PAD1 2L
+#define PINMUX_PA21C_SERCOM0_PAD1 ((PIN_PA21C_SERCOM0_PAD1 << 16) | MUX_PA21C_SERCOM0_PAD1)
+#define PORT_PA21C_SERCOM0_PAD1 (1ul << 21)
+#define PIN_PB25C_SERCOM0_PAD1 57L /**< \brief SERCOM0 signal: PAD1 on PB25 mux C */
+#define MUX_PB25C_SERCOM0_PAD1 2L
+#define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1)
+#define PORT_PB25C_SERCOM0_PAD1 (1ul << 25)
+#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2 3L
+#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6)
+#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2 2L
+#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10)
+#define PIN_PA22C_SERCOM0_PAD2 22L /**< \brief SERCOM0 signal: PAD2 on PA22 mux C */
+#define MUX_PA22C_SERCOM0_PAD2 2L
+#define PINMUX_PA22C_SERCOM0_PAD2 ((PIN_PA22C_SERCOM0_PAD2 << 16) | MUX_PA22C_SERCOM0_PAD2)
+#define PORT_PA22C_SERCOM0_PAD2 (1ul << 22)
+#define PIN_PC24C_SERCOM0_PAD2 88L /**< \brief SERCOM0 signal: PAD2 on PC24 mux C */
+#define MUX_PC24C_SERCOM0_PAD2 2L
+#define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2)
+#define PORT_PC24C_SERCOM0_PAD2 (1ul << 24)
+#define PIN_PB22C_SERCOM0_PAD2 54L /**< \brief SERCOM0 signal: PAD2 on PB22 mux C */
+#define MUX_PB22C_SERCOM0_PAD2 2L
+#define PINMUX_PB22C_SERCOM0_PAD2 ((PIN_PB22C_SERCOM0_PAD2 << 16) | MUX_PB22C_SERCOM0_PAD2)
+#define PORT_PB22C_SERCOM0_PAD2 (1ul << 22)
+#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3 3L
+#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7)
+#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3 2L
+#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11)
+#define PIN_PA23C_SERCOM0_PAD3 23L /**< \brief SERCOM0 signal: PAD3 on PA23 mux C */
+#define MUX_PA23C_SERCOM0_PAD3 2L
+#define PINMUX_PA23C_SERCOM0_PAD3 ((PIN_PA23C_SERCOM0_PAD3 << 16) | MUX_PA23C_SERCOM0_PAD3)
+#define PORT_PA23C_SERCOM0_PAD3 (1ul << 23)
+#define PIN_PC25C_SERCOM0_PAD3 89L /**< \brief SERCOM0 signal: PAD3 on PC25 mux C */
+#define MUX_PC25C_SERCOM0_PAD3 2L
+#define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3)
+#define PORT_PC25C_SERCOM0_PAD3 (1ul << 25)
+#define PIN_PB23C_SERCOM0_PAD3 55L /**< \brief SERCOM0 signal: PAD3 on PB23 mux C */
+#define MUX_PB23C_SERCOM0_PAD3 2L
+#define PINMUX_PB23C_SERCOM0_PAD3 ((PIN_PB23C_SERCOM0_PAD3 << 16) | MUX_PB23C_SERCOM0_PAD3)
+#define PORT_PB23C_SERCOM0_PAD3 (1ul << 23)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PB30C_SERCOM1_PAD0 62L /**< \brief SERCOM1 signal: PAD0 on PB30 mux C */
+#define MUX_PB30C_SERCOM1_PAD0 2L
+#define PINMUX_PB30C_SERCOM1_PAD0 ((PIN_PB30C_SERCOM1_PAD0 << 16) | MUX_PB30C_SERCOM1_PAD0)
+#define PORT_PB30C_SERCOM1_PAD0 (1ul << 30)
+#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0 3L
+#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0)
+#define PIN_PC27D_SERCOM1_PAD0 91L /**< \brief SERCOM1 signal: PAD0 on PC27 mux D */
+#define MUX_PC27D_SERCOM1_PAD0 3L
+#define PINMUX_PC27D_SERCOM1_PAD0 ((PIN_PC27D_SERCOM1_PAD0 << 16) | MUX_PC27D_SERCOM1_PAD0)
+#define PORT_PC27D_SERCOM1_PAD0 (1ul << 27)
+#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0 2L
+#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16)
+#define PIN_PC12C_SERCOM1_PAD0 76L /**< \brief SERCOM1 signal: PAD0 on PC12 mux C */
+#define MUX_PC12C_SERCOM1_PAD0 2L
+#define PINMUX_PC12C_SERCOM1_PAD0 ((PIN_PC12C_SERCOM1_PAD0 << 16) | MUX_PC12C_SERCOM1_PAD0)
+#define PORT_PC12C_SERCOM1_PAD0 (1ul << 12)
+#define PIN_PB31C_SERCOM1_PAD1 63L /**< \brief SERCOM1 signal: PAD1 on PB31 mux C */
+#define MUX_PB31C_SERCOM1_PAD1 2L
+#define PINMUX_PB31C_SERCOM1_PAD1 ((PIN_PB31C_SERCOM1_PAD1 << 16) | MUX_PB31C_SERCOM1_PAD1)
+#define PORT_PB31C_SERCOM1_PAD1 (1ul << 31)
+#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1 3L
+#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1)
+#define PIN_PC28D_SERCOM1_PAD1 92L /**< \brief SERCOM1 signal: PAD1 on PC28 mux D */
+#define MUX_PC28D_SERCOM1_PAD1 3L
+#define PINMUX_PC28D_SERCOM1_PAD1 ((PIN_PC28D_SERCOM1_PAD1 << 16) | MUX_PC28D_SERCOM1_PAD1)
+#define PORT_PC28D_SERCOM1_PAD1 (1ul << 28)
+#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1 2L
+#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17)
+#define PIN_PC13C_SERCOM1_PAD1 77L /**< \brief SERCOM1 signal: PAD1 on PC13 mux C */
+#define MUX_PC13C_SERCOM1_PAD1 2L
+#define PINMUX_PC13C_SERCOM1_PAD1 ((PIN_PC13C_SERCOM1_PAD1 << 16) | MUX_PC13C_SERCOM1_PAD1)
+#define PORT_PC13C_SERCOM1_PAD1 (1ul << 13)
+#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2 3L
+#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2 2L
+#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18)
+#define PIN_PC10C_SERCOM1_PAD2 74L /**< \brief SERCOM1 signal: PAD2 on PC10 mux C */
+#define MUX_PC10C_SERCOM1_PAD2 2L
+#define PINMUX_PC10C_SERCOM1_PAD2 ((PIN_PC10C_SERCOM1_PAD2 << 16) | MUX_PC10C_SERCOM1_PAD2)
+#define PORT_PC10C_SERCOM1_PAD2 (1ul << 10)
+#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3 3L
+#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3 2L
+#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19)
+#define PIN_PC11C_SERCOM1_PAD3 75L /**< \brief SERCOM1 signal: PAD3 on PC11 mux C */
+#define MUX_PC11C_SERCOM1_PAD3 2L
+#define PINMUX_PC11C_SERCOM1_PAD3 ((PIN_PC11C_SERCOM1_PAD3 << 16) | MUX_PC11C_SERCOM1_PAD3)
+#define PORT_PC11C_SERCOM1_PAD3 (1ul << 11)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA22D_SERCOM2_PAD0 22L /**< \brief SERCOM2 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM2_PAD0 3L
+#define PINMUX_PA22D_SERCOM2_PAD0 ((PIN_PA22D_SERCOM2_PAD0 << 16) | MUX_PA22D_SERCOM2_PAD0)
+#define PORT_PA22D_SERCOM2_PAD0 (1ul << 22)
+#define PIN_PA16D_SERCOM2_PAD0 16L /**< \brief SERCOM2 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM2_PAD0 3L
+#define PINMUX_PA16D_SERCOM2_PAD0 ((PIN_PA16D_SERCOM2_PAD0 << 16) | MUX_PA16D_SERCOM2_PAD0)
+#define PORT_PA16D_SERCOM2_PAD0 (1ul << 16)
+#define PIN_PA23D_SERCOM2_PAD1 23L /**< \brief SERCOM2 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM2_PAD1 3L
+#define PINMUX_PA23D_SERCOM2_PAD1 ((PIN_PA23D_SERCOM2_PAD1 << 16) | MUX_PA23D_SERCOM2_PAD1)
+#define PORT_PA23D_SERCOM2_PAD1 (1ul << 23)
+#define PIN_PA17D_SERCOM2_PAD1 17L /**< \brief SERCOM2 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM2_PAD1 3L
+#define PINMUX_PA17D_SERCOM2_PAD1 ((PIN_PA17D_SERCOM2_PAD1 << 16) | MUX_PA17D_SERCOM2_PAD1)
+#define PORT_PA17D_SERCOM2_PAD1 (1ul << 17)
+#define PIN_PA18D_SERCOM2_PAD2 18L /**< \brief SERCOM2 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM2_PAD2 3L
+#define PINMUX_PA18D_SERCOM2_PAD2 ((PIN_PA18D_SERCOM2_PAD2 << 16) | MUX_PA18D_SERCOM2_PAD2)
+#define PORT_PA18D_SERCOM2_PAD2 (1ul << 18)
+#define PIN_PA20D_SERCOM2_PAD2 20L /**< \brief SERCOM2 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM2_PAD2 3L
+#define PINMUX_PA20D_SERCOM2_PAD2 ((PIN_PA20D_SERCOM2_PAD2 << 16) | MUX_PA20D_SERCOM2_PAD2)
+#define PORT_PA20D_SERCOM2_PAD2 (1ul << 20)
+#define PIN_PA24C_SERCOM2_PAD2 24L /**< \brief SERCOM2 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM2_PAD2 2L
+#define PINMUX_PA24C_SERCOM2_PAD2 ((PIN_PA24C_SERCOM2_PAD2 << 16) | MUX_PA24C_SERCOM2_PAD2)
+#define PORT_PA24C_SERCOM2_PAD2 (1ul << 24)
+#define PIN_PA19D_SERCOM2_PAD3 19L /**< \brief SERCOM2 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM2_PAD3 3L
+#define PINMUX_PA19D_SERCOM2_PAD3 ((PIN_PA19D_SERCOM2_PAD3 << 16) | MUX_PA19D_SERCOM2_PAD3)
+#define PORT_PA19D_SERCOM2_PAD3 (1ul << 19)
+#define PIN_PA21D_SERCOM2_PAD3 21L /**< \brief SERCOM2 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM2_PAD3 3L
+#define PINMUX_PA21D_SERCOM2_PAD3 ((PIN_PA21D_SERCOM2_PAD3 << 16) | MUX_PA21D_SERCOM2_PAD3)
+#define PORT_PA21D_SERCOM2_PAD3 (1ul << 21)
+#define PIN_PA25C_SERCOM2_PAD3 25L /**< \brief SERCOM2 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM2_PAD3 2L
+#define PINMUX_PA25C_SERCOM2_PAD3 ((PIN_PA25C_SERCOM2_PAD3 << 16) | MUX_PA25C_SERCOM2_PAD3)
+#define PORT_PA25C_SERCOM2_PAD3 (1ul << 25)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PB12C_SERCOM3_PAD0 44L /**< \brief SERCOM3 signal: PAD0 on PB12 mux C */
+#define MUX_PB12C_SERCOM3_PAD0 2L
+#define PINMUX_PB12C_SERCOM3_PAD0 ((PIN_PB12C_SERCOM3_PAD0 << 16) | MUX_PB12C_SERCOM3_PAD0)
+#define PORT_PB12C_SERCOM3_PAD0 (1ul << 12)
+#define PIN_PA12D_SERCOM3_PAD0 12L /**< \brief SERCOM3 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM3_PAD0 3L
+#define PINMUX_PA12D_SERCOM3_PAD0 ((PIN_PA12D_SERCOM3_PAD0 << 16) | MUX_PA12D_SERCOM3_PAD0)
+#define PORT_PA12D_SERCOM3_PAD0 (1ul << 12)
+#define PIN_PB08D_SERCOM3_PAD0 40L /**< \brief SERCOM3 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM3_PAD0 3L
+#define PINMUX_PB08D_SERCOM3_PAD0 ((PIN_PB08D_SERCOM3_PAD0 << 16) | MUX_PB08D_SERCOM3_PAD0)
+#define PORT_PB08D_SERCOM3_PAD0 (1ul << 8)
+#define PIN_PB02C_SERCOM3_PAD0 34L /**< \brief SERCOM3 signal: PAD0 on PB02 mux C */
+#define MUX_PB02C_SERCOM3_PAD0 2L
+#define PINMUX_PB02C_SERCOM3_PAD0 ((PIN_PB02C_SERCOM3_PAD0 << 16) | MUX_PB02C_SERCOM3_PAD0)
+#define PORT_PB02C_SERCOM3_PAD0 (1ul << 2)
+#define PIN_PB20C_SERCOM3_PAD0 52L /**< \brief SERCOM3 signal: PAD0 on PB20 mux C */
+#define MUX_PB20C_SERCOM3_PAD0 2L
+#define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0)
+#define PORT_PB20C_SERCOM3_PAD0 (1ul << 20)
+#define PIN_PB13C_SERCOM3_PAD1 45L /**< \brief SERCOM3 signal: PAD1 on PB13 mux C */
+#define MUX_PB13C_SERCOM3_PAD1 2L
+#define PINMUX_PB13C_SERCOM3_PAD1 ((PIN_PB13C_SERCOM3_PAD1 << 16) | MUX_PB13C_SERCOM3_PAD1)
+#define PORT_PB13C_SERCOM3_PAD1 (1ul << 13)
+#define PIN_PA13D_SERCOM3_PAD1 13L /**< \brief SERCOM3 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM3_PAD1 3L
+#define PINMUX_PA13D_SERCOM3_PAD1 ((PIN_PA13D_SERCOM3_PAD1 << 16) | MUX_PA13D_SERCOM3_PAD1)
+#define PORT_PA13D_SERCOM3_PAD1 (1ul << 13)
+#define PIN_PB09D_SERCOM3_PAD1 41L /**< \brief SERCOM3 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM3_PAD1 3L
+#define PINMUX_PB09D_SERCOM3_PAD1 ((PIN_PB09D_SERCOM3_PAD1 << 16) | MUX_PB09D_SERCOM3_PAD1)
+#define PORT_PB09D_SERCOM3_PAD1 (1ul << 9)
+#define PIN_PB03C_SERCOM3_PAD1 35L /**< \brief SERCOM3 signal: PAD1 on PB03 mux C */
+#define MUX_PB03C_SERCOM3_PAD1 2L
+#define PINMUX_PB03C_SERCOM3_PAD1 ((PIN_PB03C_SERCOM3_PAD1 << 16) | MUX_PB03C_SERCOM3_PAD1)
+#define PORT_PB03C_SERCOM3_PAD1 (1ul << 3)
+#define PIN_PB21C_SERCOM3_PAD1 53L /**< \brief SERCOM3 signal: PAD1 on PB21 mux C */
+#define MUX_PB21C_SERCOM3_PAD1 2L
+#define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1)
+#define PORT_PB21C_SERCOM3_PAD1 (1ul << 21)
+#define PIN_PB14C_SERCOM3_PAD2 46L /**< \brief SERCOM3 signal: PAD2 on PB14 mux C */
+#define MUX_PB14C_SERCOM3_PAD2 2L
+#define PINMUX_PB14C_SERCOM3_PAD2 ((PIN_PB14C_SERCOM3_PAD2 << 16) | MUX_PB14C_SERCOM3_PAD2)
+#define PORT_PB14C_SERCOM3_PAD2 (1ul << 14)
+#define PIN_PA14D_SERCOM3_PAD2 14L /**< \brief SERCOM3 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM3_PAD2 3L
+#define PINMUX_PA14D_SERCOM3_PAD2 ((PIN_PA14D_SERCOM3_PAD2 << 16) | MUX_PA14D_SERCOM3_PAD2)
+#define PORT_PA14D_SERCOM3_PAD2 (1ul << 14)
+#define PIN_PB18D_SERCOM3_PAD2 50L /**< \brief SERCOM3 signal: PAD2 on PB18 mux D */
+#define MUX_PB18D_SERCOM3_PAD2 3L
+#define PINMUX_PB18D_SERCOM3_PAD2 ((PIN_PB18D_SERCOM3_PAD2 << 16) | MUX_PB18D_SERCOM3_PAD2)
+#define PORT_PB18D_SERCOM3_PAD2 (1ul << 18)
+#define PIN_PB00C_SERCOM3_PAD2 32L /**< \brief SERCOM3 signal: PAD2 on PB00 mux C */
+#define MUX_PB00C_SERCOM3_PAD2 2L
+#define PINMUX_PB00C_SERCOM3_PAD2 ((PIN_PB00C_SERCOM3_PAD2 << 16) | MUX_PB00C_SERCOM3_PAD2)
+#define PORT_PB00C_SERCOM3_PAD2 (1ul << 0)
+#define PIN_PB15C_SERCOM3_PAD3 47L /**< \brief SERCOM3 signal: PAD3 on PB15 mux C */
+#define MUX_PB15C_SERCOM3_PAD3 2L
+#define PINMUX_PB15C_SERCOM3_PAD3 ((PIN_PB15C_SERCOM3_PAD3 << 16) | MUX_PB15C_SERCOM3_PAD3)
+#define PORT_PB15C_SERCOM3_PAD3 (1ul << 15)
+#define PIN_PA15D_SERCOM3_PAD3 15L /**< \brief SERCOM3 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM3_PAD3 3L
+#define PINMUX_PA15D_SERCOM3_PAD3 ((PIN_PA15D_SERCOM3_PAD3 << 16) | MUX_PA15D_SERCOM3_PAD3)
+#define PORT_PA15D_SERCOM3_PAD3 (1ul << 15)
+#define PIN_PB11D_SERCOM3_PAD3 43L /**< \brief SERCOM3 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM3_PAD3 3L
+#define PINMUX_PB11D_SERCOM3_PAD3 ((PIN_PB11D_SERCOM3_PAD3 << 16) | MUX_PB11D_SERCOM3_PAD3)
+#define PORT_PB11D_SERCOM3_PAD3 (1ul << 11)
+#define PIN_PB19D_SERCOM3_PAD3 51L /**< \brief SERCOM3 signal: PAD3 on PB19 mux D */
+#define MUX_PB19D_SERCOM3_PAD3 3L
+#define PINMUX_PB19D_SERCOM3_PAD3 ((PIN_PB19D_SERCOM3_PAD3 << 16) | MUX_PB19D_SERCOM3_PAD3)
+#define PORT_PB19D_SERCOM3_PAD3 (1ul << 19)
+#define PIN_PB01C_SERCOM3_PAD3 33L /**< \brief SERCOM3 signal: PAD3 on PB01 mux C */
+#define MUX_PB01C_SERCOM3_PAD3 2L
+#define PINMUX_PB01C_SERCOM3_PAD3 ((PIN_PB01C_SERCOM3_PAD3 << 16) | MUX_PB01C_SERCOM3_PAD3)
+#define PORT_PB01C_SERCOM3_PAD3 (1ul << 1)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA08D_SERCOM4_PAD0 8L /**< \brief SERCOM4 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM4_PAD0 3L
+#define PINMUX_PA08D_SERCOM4_PAD0 ((PIN_PA08D_SERCOM4_PAD0 << 16) | MUX_PA08D_SERCOM4_PAD0)
+#define PORT_PA08D_SERCOM4_PAD0 (1ul << 8)
+#define PIN_PB24D_SERCOM4_PAD0 56L /**< \brief SERCOM4 signal: PAD0 on PB24 mux D */
+#define MUX_PB24D_SERCOM4_PAD0 3L
+#define PINMUX_PB24D_SERCOM4_PAD0 ((PIN_PB24D_SERCOM4_PAD0 << 16) | MUX_PB24D_SERCOM4_PAD0)
+#define PORT_PB24D_SERCOM4_PAD0 (1ul << 24)
+#define PIN_PA12C_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM4_PAD0 2L
+#define PINMUX_PA12C_SERCOM4_PAD0 ((PIN_PA12C_SERCOM4_PAD0 << 16) | MUX_PA12C_SERCOM4_PAD0)
+#define PORT_PA12C_SERCOM4_PAD0 (1ul << 12)
+#define PIN_PA09D_SERCOM4_PAD1 9L /**< \brief SERCOM4 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM4_PAD1 3L
+#define PINMUX_PA09D_SERCOM4_PAD1 ((PIN_PA09D_SERCOM4_PAD1 << 16) | MUX_PA09D_SERCOM4_PAD1)
+#define PORT_PA09D_SERCOM4_PAD1 (1ul << 9)
+#define PIN_PB25D_SERCOM4_PAD1 57L /**< \brief SERCOM4 signal: PAD1 on PB25 mux D */
+#define MUX_PB25D_SERCOM4_PAD1 3L
+#define PINMUX_PB25D_SERCOM4_PAD1 ((PIN_PB25D_SERCOM4_PAD1 << 16) | MUX_PB25D_SERCOM4_PAD1)
+#define PORT_PB25D_SERCOM4_PAD1 (1ul << 25)
+#define PIN_PA13C_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM4_PAD1 2L
+#define PINMUX_PA13C_SERCOM4_PAD1 ((PIN_PA13C_SERCOM4_PAD1 << 16) | MUX_PA13C_SERCOM4_PAD1)
+#define PORT_PA13C_SERCOM4_PAD1 (1ul << 13)
+#define PIN_PA10D_SERCOM4_PAD2 10L /**< \brief SERCOM4 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM4_PAD2 3L
+#define PINMUX_PA10D_SERCOM4_PAD2 ((PIN_PA10D_SERCOM4_PAD2 << 16) | MUX_PA10D_SERCOM4_PAD2)
+#define PORT_PA10D_SERCOM4_PAD2 (1ul << 10)
+#define PIN_PC24D_SERCOM4_PAD2 88L /**< \brief SERCOM4 signal: PAD2 on PC24 mux D */
+#define MUX_PC24D_SERCOM4_PAD2 3L
+#define PINMUX_PC24D_SERCOM4_PAD2 ((PIN_PC24D_SERCOM4_PAD2 << 16) | MUX_PC24D_SERCOM4_PAD2)
+#define PORT_PC24D_SERCOM4_PAD2 (1ul << 24)
+#define PIN_PA14C_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM4_PAD2 2L
+#define PINMUX_PA14C_SERCOM4_PAD2 ((PIN_PA14C_SERCOM4_PAD2 << 16) | MUX_PA14C_SERCOM4_PAD2)
+#define PORT_PA14C_SERCOM4_PAD2 (1ul << 14)
+#define PIN_PA11D_SERCOM4_PAD3 11L /**< \brief SERCOM4 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM4_PAD3 3L
+#define PINMUX_PA11D_SERCOM4_PAD3 ((PIN_PA11D_SERCOM4_PAD3 << 16) | MUX_PA11D_SERCOM4_PAD3)
+#define PORT_PA11D_SERCOM4_PAD3 (1ul << 11)
+#define PIN_PC25D_SERCOM4_PAD3 89L /**< \brief SERCOM4 signal: PAD3 on PC25 mux D */
+#define MUX_PC25D_SERCOM4_PAD3 3L
+#define PINMUX_PC25D_SERCOM4_PAD3 ((PIN_PC25D_SERCOM4_PAD3 << 16) | MUX_PC25D_SERCOM4_PAD3)
+#define PORT_PC25D_SERCOM4_PAD3 (1ul << 25)
+#define PIN_PA15C_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM4_PAD3 2L
+#define PINMUX_PA15C_SERCOM4_PAD3 ((PIN_PA15C_SERCOM4_PAD3 << 16) | MUX_PA15C_SERCOM4_PAD3)
+#define PORT_PA15C_SERCOM4_PAD3 (1ul << 15)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PB30D_SERCOM5_PAD0 62L /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */
+#define MUX_PB30D_SERCOM5_PAD0 3L
+#define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0)
+#define PORT_PB30D_SERCOM5_PAD0 (1ul << 30)
+#define PIN_PA24D_SERCOM5_PAD0 24L /**< \brief SERCOM5 signal: PAD0 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD0 3L
+#define PINMUX_PA24D_SERCOM5_PAD0 ((PIN_PA24D_SERCOM5_PAD0 << 16) | MUX_PA24D_SERCOM5_PAD0)
+#define PORT_PA24D_SERCOM5_PAD0 (1ul << 24)
+#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0 3L
+#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2)
+#define PIN_PB20D_SERCOM5_PAD0 52L /**< \brief SERCOM5 signal: PAD0 on PB20 mux D */
+#define MUX_PB20D_SERCOM5_PAD0 3L
+#define PINMUX_PB20D_SERCOM5_PAD0 ((PIN_PB20D_SERCOM5_PAD0 << 16) | MUX_PB20D_SERCOM5_PAD0)
+#define PORT_PB20D_SERCOM5_PAD0 (1ul << 20)
+#define PIN_PB16C_SERCOM5_PAD0 48L /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */
+#define MUX_PB16C_SERCOM5_PAD0 2L
+#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)
+#define PORT_PB16C_SERCOM5_PAD0 (1ul << 16)
+#define PIN_PB31D_SERCOM5_PAD1 63L /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */
+#define MUX_PB31D_SERCOM5_PAD1 3L
+#define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1)
+#define PORT_PB31D_SERCOM5_PAD1 (1ul << 31)
+#define PIN_PA25D_SERCOM5_PAD1 25L /**< \brief SERCOM5 signal: PAD1 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD1 3L
+#define PINMUX_PA25D_SERCOM5_PAD1 ((PIN_PA25D_SERCOM5_PAD1 << 16) | MUX_PA25D_SERCOM5_PAD1)
+#define PORT_PA25D_SERCOM5_PAD1 (1ul << 25)
+#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1 3L
+#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3)
+#define PIN_PB21D_SERCOM5_PAD1 53L /**< \brief SERCOM5 signal: PAD1 on PB21 mux D */
+#define MUX_PB21D_SERCOM5_PAD1 3L
+#define PINMUX_PB21D_SERCOM5_PAD1 ((PIN_PB21D_SERCOM5_PAD1 << 16) | MUX_PB21D_SERCOM5_PAD1)
+#define PORT_PB21D_SERCOM5_PAD1 (1ul << 21)
+#define PIN_PB17C_SERCOM5_PAD1 49L /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */
+#define MUX_PB17C_SERCOM5_PAD1 2L
+#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)
+#define PORT_PB17C_SERCOM5_PAD1 (1ul << 17)
+#define PIN_PB18C_SERCOM5_PAD2 50L /**< \brief SERCOM5 signal: PAD2 on PB18 mux C */
+#define MUX_PB18C_SERCOM5_PAD2 2L
+#define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2)
+#define PORT_PB18C_SERCOM5_PAD2 (1ul << 18)
+#define PIN_PB00D_SERCOM5_PAD2 32L /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
+#define MUX_PB00D_SERCOM5_PAD2 3L
+#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
+#define PORT_PB00D_SERCOM5_PAD2 (1ul << 0)
+#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2 3L
+#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22)
+#define PIN_PB19C_SERCOM5_PAD3 51L /**< \brief SERCOM5 signal: PAD3 on PB19 mux C */
+#define MUX_PB19C_SERCOM5_PAD3 2L
+#define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3)
+#define PORT_PB19C_SERCOM5_PAD3 (1ul << 19)
+#define PIN_PB01D_SERCOM5_PAD3 33L /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
+#define MUX_PB01D_SERCOM5_PAD3 3L
+#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
+#define PORT_PB01D_SERCOM5_PAD3 (1ul << 1)
+#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3 3L
+#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA24F_TCC0_WO0 24L /**< \brief TCC0 signal: WO0 on PA24 mux F */
+#define MUX_PA24F_TCC0_WO0 5L
+#define PINMUX_PA24F_TCC0_WO0 ((PIN_PA24F_TCC0_WO0 << 16) | MUX_PA24F_TCC0_WO0)
+#define PORT_PA24F_TCC0_WO0 (1ul << 24)
+#define PIN_PB18F_TCC0_WO0 50L /**< \brief TCC0 signal: WO0 on PB18 mux F */
+#define MUX_PB18F_TCC0_WO0 5L
+#define PINMUX_PB18F_TCC0_WO0 ((PIN_PB18F_TCC0_WO0 << 16) | MUX_PB18F_TCC0_WO0)
+#define PORT_PB18F_TCC0_WO0 (1ul << 18)
+#define PIN_PC24F_TCC0_WO0 88L /**< \brief TCC0 signal: WO0 on PC24 mux F */
+#define MUX_PC24F_TCC0_WO0 5L
+#define PINMUX_PC24F_TCC0_WO0 ((PIN_PC24F_TCC0_WO0 << 16) | MUX_PC24F_TCC0_WO0)
+#define PORT_PC24F_TCC0_WO0 (1ul << 24)
+#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0 4L
+#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0 (1ul << 4)
+#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0 4L
+#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0 (1ul << 8)
+#define PIN_PB30E_TCC0_WO0 62L /**< \brief TCC0 signal: WO0 on PB30 mux E */
+#define MUX_PB30E_TCC0_WO0 4L
+#define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0)
+#define PORT_PB30E_TCC0_WO0 (1ul << 30)
+#define PIN_PA25F_TCC0_WO1 25L /**< \brief TCC0 signal: WO1 on PA25 mux F */
+#define MUX_PA25F_TCC0_WO1 5L
+#define PINMUX_PA25F_TCC0_WO1 ((PIN_PA25F_TCC0_WO1 << 16) | MUX_PA25F_TCC0_WO1)
+#define PORT_PA25F_TCC0_WO1 (1ul << 25)
+#define PIN_PB19F_TCC0_WO1 51L /**< \brief TCC0 signal: WO1 on PB19 mux F */
+#define MUX_PB19F_TCC0_WO1 5L
+#define PINMUX_PB19F_TCC0_WO1 ((PIN_PB19F_TCC0_WO1 << 16) | MUX_PB19F_TCC0_WO1)
+#define PORT_PB19F_TCC0_WO1 (1ul << 19)
+#define PIN_PC25F_TCC0_WO1 89L /**< \brief TCC0 signal: WO1 on PC25 mux F */
+#define MUX_PC25F_TCC0_WO1 5L
+#define PINMUX_PC25F_TCC0_WO1 ((PIN_PC25F_TCC0_WO1 << 16) | MUX_PC25F_TCC0_WO1)
+#define PORT_PC25F_TCC0_WO1 (1ul << 25)
+#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1 4L
+#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1 (1ul << 5)
+#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1 4L
+#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1 (1ul << 9)
+#define PIN_PB31E_TCC0_WO1 63L /**< \brief TCC0 signal: WO1 on PB31 mux E */
+#define MUX_PB31E_TCC0_WO1 4L
+#define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1)
+#define PORT_PB31E_TCC0_WO1 (1ul << 31)
+#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2 5L
+#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2 (1ul << 10)
+#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2 5L
+#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2 (1ul << 18)
+#define PIN_PB20F_TCC0_WO2 52L /**< \brief TCC0 signal: WO2 on PB20 mux F */
+#define MUX_PB20F_TCC0_WO2 5L
+#define PINMUX_PB20F_TCC0_WO2 ((PIN_PB20F_TCC0_WO2 << 16) | MUX_PB20F_TCC0_WO2)
+#define PORT_PB20F_TCC0_WO2 (1ul << 20)
+#define PIN_PB22F_TCC0_WO2 54L /**< \brief TCC0 signal: WO2 on PB22 mux F */
+#define MUX_PB22F_TCC0_WO2 5L
+#define PINMUX_PB22F_TCC0_WO2 ((PIN_PB22F_TCC0_WO2 << 16) | MUX_PB22F_TCC0_WO2)
+#define PORT_PB22F_TCC0_WO2 (1ul << 22)
+#define PIN_PC26F_TCC0_WO2 90L /**< \brief TCC0 signal: WO2 on PC26 mux F */
+#define MUX_PC26F_TCC0_WO2 5L
+#define PINMUX_PC26F_TCC0_WO2 ((PIN_PC26F_TCC0_WO2 << 16) | MUX_PC26F_TCC0_WO2)
+#define PORT_PC26F_TCC0_WO2 (1ul << 26)
+#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3 5L
+#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3 (1ul << 11)
+#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3 5L
+#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3 (1ul << 19)
+#define PIN_PB21F_TCC0_WO3 53L /**< \brief TCC0 signal: WO3 on PB21 mux F */
+#define MUX_PB21F_TCC0_WO3 5L
+#define PINMUX_PB21F_TCC0_WO3 ((PIN_PB21F_TCC0_WO3 << 16) | MUX_PB21F_TCC0_WO3)
+#define PORT_PB21F_TCC0_WO3 (1ul << 21)
+#define PIN_PB23F_TCC0_WO3 55L /**< \brief TCC0 signal: WO3 on PB23 mux F */
+#define MUX_PB23F_TCC0_WO3 5L
+#define PINMUX_PB23F_TCC0_WO3 ((PIN_PB23F_TCC0_WO3 << 16) | MUX_PB23F_TCC0_WO3)
+#define PORT_PB23F_TCC0_WO3 (1ul << 23)
+#define PIN_PC27F_TCC0_WO3 91L /**< \brief TCC0 signal: WO3 on PC27 mux F */
+#define MUX_PC27F_TCC0_WO3 5L
+#define PINMUX_PC27F_TCC0_WO3 ((PIN_PC27F_TCC0_WO3 << 16) | MUX_PC27F_TCC0_WO3)
+#define PORT_PC27F_TCC0_WO3 (1ul << 27)
+#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4 5L
+#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4 (1ul << 22)
+#define PIN_PB16F_TCC0_WO4 48L /**< \brief TCC0 signal: WO4 on PB16 mux F */
+#define MUX_PB16F_TCC0_WO4 5L
+#define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4)
+#define PORT_PB16F_TCC0_WO4 (1ul << 16)
+#define PIN_PC28F_TCC0_WO4 92L /**< \brief TCC0 signal: WO4 on PC28 mux F */
+#define MUX_PC28F_TCC0_WO4 5L
+#define PINMUX_PC28F_TCC0_WO4 ((PIN_PC28F_TCC0_WO4 << 16) | MUX_PC28F_TCC0_WO4)
+#define PORT_PC28F_TCC0_WO4 (1ul << 28)
+#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4 5L
+#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4 (1ul << 14)
+#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5 5L
+#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5 (1ul << 15)
+#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5 5L
+#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5 (1ul << 23)
+#define PIN_PA27F_TCC0_WO5 27L /**< \brief TCC0 signal: WO5 on PA27 mux F */
+#define MUX_PA27F_TCC0_WO5 5L
+#define PINMUX_PA27F_TCC0_WO5 ((PIN_PA27F_TCC0_WO5 << 16) | MUX_PA27F_TCC0_WO5)
+#define PORT_PA27F_TCC0_WO5 (1ul << 27)
+#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5 5L
+#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5 (1ul << 11)
+#define PIN_PB17F_TCC0_WO5 49L /**< \brief TCC0 signal: WO5 on PB17 mux F */
+#define MUX_PB17F_TCC0_WO5 5L
+#define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5)
+#define PORT_PB17F_TCC0_WO5 (1ul << 17)
+#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6 5L
+#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6 (1ul << 12)
+#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6 5L
+#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6 (1ul << 16)
+#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6 5L
+#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6 (1ul << 20)
+#define PIN_PB12F_TCC0_WO6 44L /**< \brief TCC0 signal: WO6 on PB12 mux F */
+#define MUX_PB12F_TCC0_WO6 5L
+#define PINMUX_PB12F_TCC0_WO6 ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6)
+#define PORT_PB12F_TCC0_WO6 (1ul << 12)
+#define PIN_PB24F_TCC0_WO6 56L /**< \brief TCC0 signal: WO6 on PB24 mux F */
+#define MUX_PB24F_TCC0_WO6 5L
+#define PINMUX_PB24F_TCC0_WO6 ((PIN_PB24F_TCC0_WO6 << 16) | MUX_PB24F_TCC0_WO6)
+#define PORT_PB24F_TCC0_WO6 (1ul << 24)
+#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7 5L
+#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7 (1ul << 13)
+#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7 5L
+#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7 (1ul << 17)
+#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7 5L
+#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7 (1ul << 21)
+#define PIN_PB13F_TCC0_WO7 45L /**< \brief TCC0 signal: WO7 on PB13 mux F */
+#define MUX_PB13F_TCC0_WO7 5L
+#define PINMUX_PB13F_TCC0_WO7 ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7)
+#define PORT_PB13F_TCC0_WO7 (1ul << 13)
+#define PIN_PB25F_TCC0_WO7 57L /**< \brief TCC0 signal: WO7 on PB25 mux F */
+#define MUX_PB25F_TCC0_WO7 5L
+#define PINMUX_PB25F_TCC0_WO7 ((PIN_PB25F_TCC0_WO7 << 16) | MUX_PB25F_TCC0_WO7)
+#define PORT_PB25F_TCC0_WO7 (1ul << 25)
+/* ========== PORT definition for TC0 peripheral ========== */
+#define PIN_PA22E_TC0_WO0 22L /**< \brief TC0 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC0_WO0 4L
+#define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0)
+#define PORT_PA22E_TC0_WO0 (1ul << 22)
+#define PIN_PB08E_TC0_WO0 40L /**< \brief TC0 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC0_WO0 4L
+#define PINMUX_PB08E_TC0_WO0 ((PIN_PB08E_TC0_WO0 << 16) | MUX_PB08E_TC0_WO0)
+#define PORT_PB08E_TC0_WO0 (1ul << 8)
+#define PIN_PB12E_TC0_WO0 44L /**< \brief TC0 signal: WO0 on PB12 mux E */
+#define MUX_PB12E_TC0_WO0 4L
+#define PINMUX_PB12E_TC0_WO0 ((PIN_PB12E_TC0_WO0 << 16) | MUX_PB12E_TC0_WO0)
+#define PORT_PB12E_TC0_WO0 (1ul << 12)
+#define PIN_PA23E_TC0_WO1 23L /**< \brief TC0 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC0_WO1 4L
+#define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1)
+#define PORT_PA23E_TC0_WO1 (1ul << 23)
+#define PIN_PB09E_TC0_WO1 41L /**< \brief TC0 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC0_WO1 4L
+#define PINMUX_PB09E_TC0_WO1 ((PIN_PB09E_TC0_WO1 << 16) | MUX_PB09E_TC0_WO1)
+#define PORT_PB09E_TC0_WO1 (1ul << 9)
+#define PIN_PB13E_TC0_WO1 45L /**< \brief TC0 signal: WO1 on PB13 mux E */
+#define MUX_PB13E_TC0_WO1 4L
+#define PINMUX_PB13E_TC0_WO1 ((PIN_PB13E_TC0_WO1 << 16) | MUX_PB13E_TC0_WO1)
+#define PORT_PB13E_TC0_WO1 (1ul << 13)
+/* ========== PORT definition for TC1 peripheral ========== */
+#define PIN_PA24E_TC1_WO0 24L /**< \brief TC1 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC1_WO0 4L
+#define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0)
+#define PORT_PA24E_TC1_WO0 (1ul << 24)
+#define PIN_PB14E_TC1_WO0 46L /**< \brief TC1 signal: WO0 on PB14 mux E */
+#define MUX_PB14E_TC1_WO0 4L
+#define PINMUX_PB14E_TC1_WO0 ((PIN_PB14E_TC1_WO0 << 16) | MUX_PB14E_TC1_WO0)
+#define PORT_PB14E_TC1_WO0 (1ul << 14)
+#define PIN_PA25E_TC1_WO1 25L /**< \brief TC1 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC1_WO1 4L
+#define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1)
+#define PORT_PA25E_TC1_WO1 (1ul << 25)
+#define PIN_PB11E_TC1_WO1 43L /**< \brief TC1 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC1_WO1 4L
+#define PINMUX_PB11E_TC1_WO1 ((PIN_PB11E_TC1_WO1 << 16) | MUX_PB11E_TC1_WO1)
+#define PORT_PB11E_TC1_WO1 (1ul << 11)
+#define PIN_PB15E_TC1_WO1 47L /**< \brief TC1 signal: WO1 on PB15 mux E */
+#define MUX_PB15E_TC1_WO1 4L
+#define PINMUX_PB15E_TC1_WO1 ((PIN_PB15E_TC1_WO1 << 16) | MUX_PB15E_TC1_WO1)
+#define PORT_PB15E_TC1_WO1 (1ul << 15)
+/* ========== PORT definition for TC2 peripheral ========== */
+#define PIN_PB02E_TC2_WO0 34L /**< \brief TC2 signal: WO0 on PB02 mux E */
+#define MUX_PB02E_TC2_WO0 4L
+#define PINMUX_PB02E_TC2_WO0 ((PIN_PB02E_TC2_WO0 << 16) | MUX_PB02E_TC2_WO0)
+#define PORT_PB02E_TC2_WO0 (1ul << 2)
+#define PIN_PB16E_TC2_WO0 48L /**< \brief TC2 signal: WO0 on PB16 mux E */
+#define MUX_PB16E_TC2_WO0 4L
+#define PINMUX_PB16E_TC2_WO0 ((PIN_PB16E_TC2_WO0 << 16) | MUX_PB16E_TC2_WO0)
+#define PORT_PB16E_TC2_WO0 (1ul << 16)
+#define PIN_PC24E_TC2_WO0 88L /**< \brief TC2 signal: WO0 on PC24 mux E */
+#define MUX_PC24E_TC2_WO0 4L
+#define PINMUX_PC24E_TC2_WO0 ((PIN_PC24E_TC2_WO0 << 16) | MUX_PC24E_TC2_WO0)
+#define PORT_PC24E_TC2_WO0 (1ul << 24)
+#define PIN_PB03E_TC2_WO1 35L /**< \brief TC2 signal: WO1 on PB03 mux E */
+#define MUX_PB03E_TC2_WO1 4L
+#define PINMUX_PB03E_TC2_WO1 ((PIN_PB03E_TC2_WO1 << 16) | MUX_PB03E_TC2_WO1)
+#define PORT_PB03E_TC2_WO1 (1ul << 3)
+#define PIN_PB17E_TC2_WO1 49L /**< \brief TC2 signal: WO1 on PB17 mux E */
+#define MUX_PB17E_TC2_WO1 4L
+#define PINMUX_PB17E_TC2_WO1 ((PIN_PB17E_TC2_WO1 << 16) | MUX_PB17E_TC2_WO1)
+#define PORT_PB17E_TC2_WO1 (1ul << 17)
+#define PIN_PC25E_TC2_WO1 89L /**< \brief TC2 signal: WO1 on PC25 mux E */
+#define MUX_PC25E_TC2_WO1 4L
+#define PINMUX_PC25E_TC2_WO1 ((PIN_PC25E_TC2_WO1 << 16) | MUX_PC25E_TC2_WO1)
+#define PORT_PC25E_TC2_WO1 (1ul << 25)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA20E_TC3_WO0 20L /**< \brief TC3 signal: WO0 on PA20 mux E */
+#define MUX_PA20E_TC3_WO0 4L
+#define PINMUX_PA20E_TC3_WO0 ((PIN_PA20E_TC3_WO0 << 16) | MUX_PA20E_TC3_WO0)
+#define PORT_PA20E_TC3_WO0 (1ul << 20)
+#define PIN_PB00E_TC3_WO0 32L /**< \brief TC3 signal: WO0 on PB00 mux E */
+#define MUX_PB00E_TC3_WO0 4L
+#define PINMUX_PB00E_TC3_WO0 ((PIN_PB00E_TC3_WO0 << 16) | MUX_PB00E_TC3_WO0)
+#define PORT_PB00E_TC3_WO0 (1ul << 0)
+#define PIN_PB22E_TC3_WO0 54L /**< \brief TC3 signal: WO0 on PB22 mux E */
+#define MUX_PB22E_TC3_WO0 4L
+#define PINMUX_PB22E_TC3_WO0 ((PIN_PB22E_TC3_WO0 << 16) | MUX_PB22E_TC3_WO0)
+#define PORT_PB22E_TC3_WO0 (1ul << 22)
+#define PIN_PC26E_TC3_WO0 90L /**< \brief TC3 signal: WO0 on PC26 mux E */
+#define MUX_PC26E_TC3_WO0 4L
+#define PINMUX_PC26E_TC3_WO0 ((PIN_PC26E_TC3_WO0 << 16) | MUX_PC26E_TC3_WO0)
+#define PORT_PC26E_TC3_WO0 (1ul << 26)
+#define PIN_PA21E_TC3_WO1 21L /**< \brief TC3 signal: WO1 on PA21 mux E */
+#define MUX_PA21E_TC3_WO1 4L
+#define PINMUX_PA21E_TC3_WO1 ((PIN_PA21E_TC3_WO1 << 16) | MUX_PA21E_TC3_WO1)
+#define PORT_PA21E_TC3_WO1 (1ul << 21)
+#define PIN_PB01E_TC3_WO1 33L /**< \brief TC3 signal: WO1 on PB01 mux E */
+#define MUX_PB01E_TC3_WO1 4L
+#define PINMUX_PB01E_TC3_WO1 ((PIN_PB01E_TC3_WO1 << 16) | MUX_PB01E_TC3_WO1)
+#define PORT_PB01E_TC3_WO1 (1ul << 1)
+#define PIN_PB23E_TC3_WO1 55L /**< \brief TC3 signal: WO1 on PB23 mux E */
+#define MUX_PB23E_TC3_WO1 4L
+#define PINMUX_PB23E_TC3_WO1 ((PIN_PB23E_TC3_WO1 << 16) | MUX_PB23E_TC3_WO1)
+#define PORT_PB23E_TC3_WO1 (1ul << 23)
+#define PIN_PC27E_TC3_WO1 91L /**< \brief TC3 signal: WO1 on PC27 mux E */
+#define MUX_PC27E_TC3_WO1 4L
+#define PINMUX_PC27E_TC3_WO1 ((PIN_PC27E_TC3_WO1 << 16) | MUX_PC27E_TC3_WO1)
+#define PORT_PC27E_TC3_WO1 (1ul << 27)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0 1L
+#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0 (1ul << 2)
+#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1 1L
+#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1 (1ul << 3)
+#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2 1L
+#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2 (1ul << 8)
+#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3 1L
+#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3 (1ul << 9)
+#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4 1L
+#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4 (1ul << 4)
+#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5 1L
+#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5 (1ul << 5)
+#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6 1L
+#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6 (1ul << 6)
+#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7 1L
+#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7 (1ul << 7)
+#define PIN_PB00B_ADC_AIN8 32L /**< \brief ADC signal: AIN8 on PB00 mux B */
+#define MUX_PB00B_ADC_AIN8 1L
+#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8)
+#define PORT_PB00B_ADC_AIN8 (1ul << 0)
+#define PIN_PB01B_ADC_AIN9 33L /**< \brief ADC signal: AIN9 on PB01 mux B */
+#define MUX_PB01B_ADC_AIN9 1L
+#define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9)
+#define PORT_PB01B_ADC_AIN9 (1ul << 1)
+#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10 1L
+#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10 (1ul << 2)
+#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11 1L
+#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11 (1ul << 3)
+#define PIN_PB04B_ADC_AIN12 36L /**< \brief ADC signal: AIN12 on PB04 mux B */
+#define MUX_PB04B_ADC_AIN12 1L
+#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
+#define PORT_PB04B_ADC_AIN12 (1ul << 4)
+#define PIN_PB05B_ADC_AIN13 37L /**< \brief ADC signal: AIN13 on PB05 mux B */
+#define MUX_PB05B_ADC_AIN13 1L
+#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
+#define PORT_PB05B_ADC_AIN13 (1ul << 5)
+#define PIN_PB06B_ADC_AIN14 38L /**< \brief ADC signal: AIN14 on PB06 mux B */
+#define MUX_PB06B_ADC_AIN14 1L
+#define PINMUX_PB06B_ADC_AIN14 ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14)
+#define PORT_PB06B_ADC_AIN14 (1ul << 6)
+#define PIN_PB07B_ADC_AIN15 39L /**< \brief ADC signal: AIN15 on PB07 mux B */
+#define MUX_PB07B_ADC_AIN15 1L
+#define PINMUX_PB07B_ADC_AIN15 ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15)
+#define PORT_PB07B_ADC_AIN15 (1ul << 7)
+#define PIN_PC00B_ADC_AIN16 64L /**< \brief ADC signal: AIN16 on PC00 mux B */
+#define MUX_PC00B_ADC_AIN16 1L
+#define PINMUX_PC00B_ADC_AIN16 ((PIN_PC00B_ADC_AIN16 << 16) | MUX_PC00B_ADC_AIN16)
+#define PORT_PC00B_ADC_AIN16 (1ul << 0)
+#define PIN_PC01B_ADC_AIN17 65L /**< \brief ADC signal: AIN17 on PC01 mux B */
+#define MUX_PC01B_ADC_AIN17 1L
+#define PINMUX_PC01B_ADC_AIN17 ((PIN_PC01B_ADC_AIN17 << 16) | MUX_PC01B_ADC_AIN17)
+#define PORT_PC01B_ADC_AIN17 (1ul << 1)
+#define PIN_PC02B_ADC_AIN18 66L /**< \brief ADC signal: AIN18 on PC02 mux B */
+#define MUX_PC02B_ADC_AIN18 1L
+#define PINMUX_PC02B_ADC_AIN18 ((PIN_PC02B_ADC_AIN18 << 16) | MUX_PC02B_ADC_AIN18)
+#define PORT_PC02B_ADC_AIN18 (1ul << 2)
+#define PIN_PC03B_ADC_AIN19 67L /**< \brief ADC signal: AIN19 on PC03 mux B */
+#define MUX_PC03B_ADC_AIN19 1L
+#define PINMUX_PC03B_ADC_AIN19 ((PIN_PC03B_ADC_AIN19 << 16) | MUX_PC03B_ADC_AIN19)
+#define PORT_PC03B_ADC_AIN19 (1ul << 3)
+#define PIN_PA03B_ADC_VREFA 3L /**< \brief ADC signal: VREFA on PA03 mux B */
+#define MUX_PA03B_ADC_VREFA 1L
+#define PINMUX_PA03B_ADC_VREFA ((PIN_PA03B_ADC_VREFA << 16) | MUX_PA03B_ADC_VREFA)
+#define PORT_PA03B_ADC_VREFA (1ul << 3)
+#define PIN_PA02B_ADC_VREFB 2L /**< \brief ADC signal: VREFB on PA02 mux B */
+#define MUX_PA02B_ADC_VREFB 1L
+#define PINMUX_PA02B_ADC_VREFB ((PIN_PA02B_ADC_VREFB << 16) | MUX_PA02B_ADC_VREFB)
+#define PORT_PA02B_ADC_VREFB (1ul << 2)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA02B_AC_AIN0 2L /**< \brief AC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_AC_AIN0 1L
+#define PINMUX_PA02B_AC_AIN0 ((PIN_PA02B_AC_AIN0 << 16) | MUX_PA02B_AC_AIN0)
+#define PORT_PA02B_AC_AIN0 (1ul << 2)
+#define PIN_PA03B_AC_AIN1 3L /**< \brief AC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_AC_AIN1 1L
+#define PINMUX_PA03B_AC_AIN1 ((PIN_PA03B_AC_AIN1 << 16) | MUX_PA03B_AC_AIN1)
+#define PORT_PA03B_AC_AIN1 (1ul << 3)
+#define PIN_PB04B_AC_AIN2 36L /**< \brief AC signal: AIN2 on PB04 mux B */
+#define MUX_PB04B_AC_AIN2 1L
+#define PINMUX_PB04B_AC_AIN2 ((PIN_PB04B_AC_AIN2 << 16) | MUX_PB04B_AC_AIN2)
+#define PORT_PB04B_AC_AIN2 (1ul << 4)
+#define PIN_PB05B_AC_AIN3 37L /**< \brief AC signal: AIN3 on PB05 mux B */
+#define MUX_PB05B_AC_AIN3 1L
+#define PINMUX_PB05B_AC_AIN3 ((PIN_PB05B_AC_AIN3 << 16) | MUX_PB05B_AC_AIN3)
+#define PORT_PB05B_AC_AIN3 (1ul << 5)
+#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0 7L
+#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0 (1ul << 12)
+#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0 7L
+#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0 (1ul << 18)
+#define PIN_PB24H_AC_CMP0 56L /**< \brief AC signal: CMP0 on PB24 mux H */
+#define MUX_PB24H_AC_CMP0 7L
+#define PINMUX_PB24H_AC_CMP0 ((PIN_PB24H_AC_CMP0 << 16) | MUX_PB24H_AC_CMP0)
+#define PORT_PB24H_AC_CMP0 (1ul << 24)
+#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1 7L
+#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1 (1ul << 13)
+#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1 7L
+#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1 (1ul << 19)
+#define PIN_PB25H_AC_CMP1 57L /**< \brief AC signal: CMP1 on PB25 mux H */
+#define MUX_PB25H_AC_CMP1 7L
+#define PINMUX_PB25H_AC_CMP1 ((PIN_PB25H_AC_CMP1 << 16) | MUX_PB25H_AC_CMP1)
+#define PORT_PB25H_AC_CMP1 (1ul << 25)
+/* ========== PORT definition for SLCD peripheral ========== */
+#define PIN_PB06B_SLCD_LP0 38L /**< \brief SLCD signal: LP0 on PB06 mux B */
+#define MUX_PB06B_SLCD_LP0 1L
+#define PINMUX_PB06B_SLCD_LP0 ((PIN_PB06B_SLCD_LP0 << 16) | MUX_PB06B_SLCD_LP0)
+#define PORT_PB06B_SLCD_LP0 (1ul << 6)
+#define PIN_PB07B_SLCD_LP1 39L /**< \brief SLCD signal: LP1 on PB07 mux B */
+#define MUX_PB07B_SLCD_LP1 1L
+#define PINMUX_PB07B_SLCD_LP1 ((PIN_PB07B_SLCD_LP1 << 16) | MUX_PB07B_SLCD_LP1)
+#define PORT_PB07B_SLCD_LP1 (1ul << 7)
+#define PIN_PB08B_SLCD_LP2 40L /**< \brief SLCD signal: LP2 on PB08 mux B */
+#define MUX_PB08B_SLCD_LP2 1L
+#define PINMUX_PB08B_SLCD_LP2 ((PIN_PB08B_SLCD_LP2 << 16) | MUX_PB08B_SLCD_LP2)
+#define PORT_PB08B_SLCD_LP2 (1ul << 8)
+#define PIN_PB09B_SLCD_LP3 41L /**< \brief SLCD signal: LP3 on PB09 mux B */
+#define MUX_PB09B_SLCD_LP3 1L
+#define PINMUX_PB09B_SLCD_LP3 ((PIN_PB09B_SLCD_LP3 << 16) | MUX_PB09B_SLCD_LP3)
+#define PORT_PB09B_SLCD_LP3 (1ul << 9)
+#define PIN_PA04B_SLCD_LP4 4L /**< \brief SLCD signal: LP4 on PA04 mux B */
+#define MUX_PA04B_SLCD_LP4 1L
+#define PINMUX_PA04B_SLCD_LP4 ((PIN_PA04B_SLCD_LP4 << 16) | MUX_PA04B_SLCD_LP4)
+#define PORT_PA04B_SLCD_LP4 (1ul << 4)
+#define PIN_PA05B_SLCD_LP5 5L /**< \brief SLCD signal: LP5 on PA05 mux B */
+#define MUX_PA05B_SLCD_LP5 1L
+#define PINMUX_PA05B_SLCD_LP5 ((PIN_PA05B_SLCD_LP5 << 16) | MUX_PA05B_SLCD_LP5)
+#define PORT_PA05B_SLCD_LP5 (1ul << 5)
+#define PIN_PA06B_SLCD_LP6 6L /**< \brief SLCD signal: LP6 on PA06 mux B */
+#define MUX_PA06B_SLCD_LP6 1L
+#define PINMUX_PA06B_SLCD_LP6 ((PIN_PA06B_SLCD_LP6 << 16) | MUX_PA06B_SLCD_LP6)
+#define PORT_PA06B_SLCD_LP6 (1ul << 6)
+#define PIN_PA07B_SLCD_LP7 7L /**< \brief SLCD signal: LP7 on PA07 mux B */
+#define MUX_PA07B_SLCD_LP7 1L
+#define PINMUX_PA07B_SLCD_LP7 ((PIN_PA07B_SLCD_LP7 << 16) | MUX_PA07B_SLCD_LP7)
+#define PORT_PA07B_SLCD_LP7 (1ul << 7)
+#define PIN_PC05B_SLCD_LP8 69L /**< \brief SLCD signal: LP8 on PC05 mux B */
+#define MUX_PC05B_SLCD_LP8 1L
+#define PINMUX_PC05B_SLCD_LP8 ((PIN_PC05B_SLCD_LP8 << 16) | MUX_PC05B_SLCD_LP8)
+#define PORT_PC05B_SLCD_LP8 (1ul << 5)
+#define PIN_PC06B_SLCD_LP9 70L /**< \brief SLCD signal: LP9 on PC06 mux B */
+#define MUX_PC06B_SLCD_LP9 1L
+#define PINMUX_PC06B_SLCD_LP9 ((PIN_PC06B_SLCD_LP9 << 16) | MUX_PC06B_SLCD_LP9)
+#define PORT_PC06B_SLCD_LP9 (1ul << 6)
+#define PIN_PC07B_SLCD_LP10 71L /**< \brief SLCD signal: LP10 on PC07 mux B */
+#define MUX_PC07B_SLCD_LP10 1L
+#define PINMUX_PC07B_SLCD_LP10 ((PIN_PC07B_SLCD_LP10 << 16) | MUX_PC07B_SLCD_LP10)
+#define PORT_PC07B_SLCD_LP10 (1ul << 7)
+#define PIN_PA08B_SLCD_LP11 8L /**< \brief SLCD signal: LP11 on PA08 mux B */
+#define MUX_PA08B_SLCD_LP11 1L
+#define PINMUX_PA08B_SLCD_LP11 ((PIN_PA08B_SLCD_LP11 << 16) | MUX_PA08B_SLCD_LP11)
+#define PORT_PA08B_SLCD_LP11 (1ul << 8)
+#define PIN_PA09B_SLCD_LP12 9L /**< \brief SLCD signal: LP12 on PA09 mux B */
+#define MUX_PA09B_SLCD_LP12 1L
+#define PINMUX_PA09B_SLCD_LP12 ((PIN_PA09B_SLCD_LP12 << 16) | MUX_PA09B_SLCD_LP12)
+#define PORT_PA09B_SLCD_LP12 (1ul << 9)
+#define PIN_PA10B_SLCD_LP13 10L /**< \brief SLCD signal: LP13 on PA10 mux B */
+#define MUX_PA10B_SLCD_LP13 1L
+#define PINMUX_PA10B_SLCD_LP13 ((PIN_PA10B_SLCD_LP13 << 16) | MUX_PA10B_SLCD_LP13)
+#define PORT_PA10B_SLCD_LP13 (1ul << 10)
+#define PIN_PA11B_SLCD_LP14 11L /**< \brief SLCD signal: LP14 on PA11 mux B */
+#define MUX_PA11B_SLCD_LP14 1L
+#define PINMUX_PA11B_SLCD_LP14 ((PIN_PA11B_SLCD_LP14 << 16) | MUX_PA11B_SLCD_LP14)
+#define PORT_PA11B_SLCD_LP14 (1ul << 11)
+#define PIN_PC08B_SLCD_LP15 72L /**< \brief SLCD signal: LP15 on PC08 mux B */
+#define MUX_PC08B_SLCD_LP15 1L
+#define PINMUX_PC08B_SLCD_LP15 ((PIN_PC08B_SLCD_LP15 << 16) | MUX_PC08B_SLCD_LP15)
+#define PORT_PC08B_SLCD_LP15 (1ul << 8)
+#define PIN_PC09B_SLCD_LP16 73L /**< \brief SLCD signal: LP16 on PC09 mux B */
+#define MUX_PC09B_SLCD_LP16 1L
+#define PINMUX_PC09B_SLCD_LP16 ((PIN_PC09B_SLCD_LP16 << 16) | MUX_PC09B_SLCD_LP16)
+#define PORT_PC09B_SLCD_LP16 (1ul << 9)
+#define PIN_PC10B_SLCD_LP17 74L /**< \brief SLCD signal: LP17 on PC10 mux B */
+#define MUX_PC10B_SLCD_LP17 1L
+#define PINMUX_PC10B_SLCD_LP17 ((PIN_PC10B_SLCD_LP17 << 16) | MUX_PC10B_SLCD_LP17)
+#define PORT_PC10B_SLCD_LP17 (1ul << 10)
+#define PIN_PC11B_SLCD_LP18 75L /**< \brief SLCD signal: LP18 on PC11 mux B */
+#define MUX_PC11B_SLCD_LP18 1L
+#define PINMUX_PC11B_SLCD_LP18 ((PIN_PC11B_SLCD_LP18 << 16) | MUX_PC11B_SLCD_LP18)
+#define PORT_PC11B_SLCD_LP18 (1ul << 11)
+#define PIN_PC12B_SLCD_LP19 76L /**< \brief SLCD signal: LP19 on PC12 mux B */
+#define MUX_PC12B_SLCD_LP19 1L
+#define PINMUX_PC12B_SLCD_LP19 ((PIN_PC12B_SLCD_LP19 << 16) | MUX_PC12B_SLCD_LP19)
+#define PORT_PC12B_SLCD_LP19 (1ul << 12)
+#define PIN_PC13B_SLCD_LP20 77L /**< \brief SLCD signal: LP20 on PC13 mux B */
+#define MUX_PC13B_SLCD_LP20 1L
+#define PINMUX_PC13B_SLCD_LP20 ((PIN_PC13B_SLCD_LP20 << 16) | MUX_PC13B_SLCD_LP20)
+#define PORT_PC13B_SLCD_LP20 (1ul << 13)
+#define PIN_PB11B_SLCD_LP21 43L /**< \brief SLCD signal: LP21 on PB11 mux B */
+#define MUX_PB11B_SLCD_LP21 1L
+#define PINMUX_PB11B_SLCD_LP21 ((PIN_PB11B_SLCD_LP21 << 16) | MUX_PB11B_SLCD_LP21)
+#define PORT_PB11B_SLCD_LP21 (1ul << 11)
+#define PIN_PB12B_SLCD_LP22 44L /**< \brief SLCD signal: LP22 on PB12 mux B */
+#define MUX_PB12B_SLCD_LP22 1L
+#define PINMUX_PB12B_SLCD_LP22 ((PIN_PB12B_SLCD_LP22 << 16) | MUX_PB12B_SLCD_LP22)
+#define PORT_PB12B_SLCD_LP22 (1ul << 12)
+#define PIN_PB13B_SLCD_LP23 45L /**< \brief SLCD signal: LP23 on PB13 mux B */
+#define MUX_PB13B_SLCD_LP23 1L
+#define PINMUX_PB13B_SLCD_LP23 ((PIN_PB13B_SLCD_LP23 << 16) | MUX_PB13B_SLCD_LP23)
+#define PORT_PB13B_SLCD_LP23 (1ul << 13)
+#define PIN_PB14B_SLCD_LP24 46L /**< \brief SLCD signal: LP24 on PB14 mux B */
+#define MUX_PB14B_SLCD_LP24 1L
+#define PINMUX_PB14B_SLCD_LP24 ((PIN_PB14B_SLCD_LP24 << 16) | MUX_PB14B_SLCD_LP24)
+#define PORT_PB14B_SLCD_LP24 (1ul << 14)
+#define PIN_PB15B_SLCD_LP25 47L /**< \brief SLCD signal: LP25 on PB15 mux B */
+#define MUX_PB15B_SLCD_LP25 1L
+#define PINMUX_PB15B_SLCD_LP25 ((PIN_PB15B_SLCD_LP25 << 16) | MUX_PB15B_SLCD_LP25)
+#define PORT_PB15B_SLCD_LP25 (1ul << 15)
+#define PIN_PC14B_SLCD_LP26 78L /**< \brief SLCD signal: LP26 on PC14 mux B */
+#define MUX_PC14B_SLCD_LP26 1L
+#define PINMUX_PC14B_SLCD_LP26 ((PIN_PC14B_SLCD_LP26 << 16) | MUX_PC14B_SLCD_LP26)
+#define PORT_PC14B_SLCD_LP26 (1ul << 14)
+#define PIN_PC15B_SLCD_LP27 79L /**< \brief SLCD signal: LP27 on PC15 mux B */
+#define MUX_PC15B_SLCD_LP27 1L
+#define PINMUX_PC15B_SLCD_LP27 ((PIN_PC15B_SLCD_LP27 << 16) | MUX_PC15B_SLCD_LP27)
+#define PORT_PC15B_SLCD_LP27 (1ul << 15)
+#define PIN_PA12B_SLCD_LP28 12L /**< \brief SLCD signal: LP28 on PA12 mux B */
+#define MUX_PA12B_SLCD_LP28 1L
+#define PINMUX_PA12B_SLCD_LP28 ((PIN_PA12B_SLCD_LP28 << 16) | MUX_PA12B_SLCD_LP28)
+#define PORT_PA12B_SLCD_LP28 (1ul << 12)
+#define PIN_PA13B_SLCD_LP29 13L /**< \brief SLCD signal: LP29 on PA13 mux B */
+#define MUX_PA13B_SLCD_LP29 1L
+#define PINMUX_PA13B_SLCD_LP29 ((PIN_PA13B_SLCD_LP29 << 16) | MUX_PA13B_SLCD_LP29)
+#define PORT_PA13B_SLCD_LP29 (1ul << 13)
+#define PIN_PA14B_SLCD_LP30 14L /**< \brief SLCD signal: LP30 on PA14 mux B */
+#define MUX_PA14B_SLCD_LP30 1L
+#define PINMUX_PA14B_SLCD_LP30 ((PIN_PA14B_SLCD_LP30 << 16) | MUX_PA14B_SLCD_LP30)
+#define PORT_PA14B_SLCD_LP30 (1ul << 14)
+#define PIN_PA15B_SLCD_LP31 15L /**< \brief SLCD signal: LP31 on PA15 mux B */
+#define MUX_PA15B_SLCD_LP31 1L
+#define PINMUX_PA15B_SLCD_LP31 ((PIN_PA15B_SLCD_LP31 << 16) | MUX_PA15B_SLCD_LP31)
+#define PORT_PA15B_SLCD_LP31 (1ul << 15)
+#define PIN_PA16B_SLCD_LP32 16L /**< \brief SLCD signal: LP32 on PA16 mux B */
+#define MUX_PA16B_SLCD_LP32 1L
+#define PINMUX_PA16B_SLCD_LP32 ((PIN_PA16B_SLCD_LP32 << 16) | MUX_PA16B_SLCD_LP32)
+#define PORT_PA16B_SLCD_LP32 (1ul << 16)
+#define PIN_PA17B_SLCD_LP33 17L /**< \brief SLCD signal: LP33 on PA17 mux B */
+#define MUX_PA17B_SLCD_LP33 1L
+#define PINMUX_PA17B_SLCD_LP33 ((PIN_PA17B_SLCD_LP33 << 16) | MUX_PA17B_SLCD_LP33)
+#define PORT_PA17B_SLCD_LP33 (1ul << 17)
+#define PIN_PA18B_SLCD_LP34 18L /**< \brief SLCD signal: LP34 on PA18 mux B */
+#define MUX_PA18B_SLCD_LP34 1L
+#define PINMUX_PA18B_SLCD_LP34 ((PIN_PA18B_SLCD_LP34 << 16) | MUX_PA18B_SLCD_LP34)
+#define PORT_PA18B_SLCD_LP34 (1ul << 18)
+#define PIN_PA19B_SLCD_LP35 19L /**< \brief SLCD signal: LP35 on PA19 mux B */
+#define MUX_PA19B_SLCD_LP35 1L
+#define PINMUX_PA19B_SLCD_LP35 ((PIN_PA19B_SLCD_LP35 << 16) | MUX_PA19B_SLCD_LP35)
+#define PORT_PA19B_SLCD_LP35 (1ul << 19)
+#define PIN_PC16B_SLCD_LP36 80L /**< \brief SLCD signal: LP36 on PC16 mux B */
+#define MUX_PC16B_SLCD_LP36 1L
+#define PINMUX_PC16B_SLCD_LP36 ((PIN_PC16B_SLCD_LP36 << 16) | MUX_PC16B_SLCD_LP36)
+#define PORT_PC16B_SLCD_LP36 (1ul << 16)
+#define PIN_PC17B_SLCD_LP37 81L /**< \brief SLCD signal: LP37 on PC17 mux B */
+#define MUX_PC17B_SLCD_LP37 1L
+#define PINMUX_PC17B_SLCD_LP37 ((PIN_PC17B_SLCD_LP37 << 16) | MUX_PC17B_SLCD_LP37)
+#define PORT_PC17B_SLCD_LP37 (1ul << 17)
+#define PIN_PC18B_SLCD_LP38 82L /**< \brief SLCD signal: LP38 on PC18 mux B */
+#define MUX_PC18B_SLCD_LP38 1L
+#define PINMUX_PC18B_SLCD_LP38 ((PIN_PC18B_SLCD_LP38 << 16) | MUX_PC18B_SLCD_LP38)
+#define PORT_PC18B_SLCD_LP38 (1ul << 18)
+#define PIN_PC19B_SLCD_LP39 83L /**< \brief SLCD signal: LP39 on PC19 mux B */
+#define MUX_PC19B_SLCD_LP39 1L
+#define PINMUX_PC19B_SLCD_LP39 ((PIN_PC19B_SLCD_LP39 << 16) | MUX_PC19B_SLCD_LP39)
+#define PORT_PC19B_SLCD_LP39 (1ul << 19)
+#define PIN_PC20B_SLCD_LP40 84L /**< \brief SLCD signal: LP40 on PC20 mux B */
+#define MUX_PC20B_SLCD_LP40 1L
+#define PINMUX_PC20B_SLCD_LP40 ((PIN_PC20B_SLCD_LP40 << 16) | MUX_PC20B_SLCD_LP40)
+#define PORT_PC20B_SLCD_LP40 (1ul << 20)
+#define PIN_PC21B_SLCD_LP41 85L /**< \brief SLCD signal: LP41 on PC21 mux B */
+#define MUX_PC21B_SLCD_LP41 1L
+#define PINMUX_PC21B_SLCD_LP41 ((PIN_PC21B_SLCD_LP41 << 16) | MUX_PC21B_SLCD_LP41)
+#define PORT_PC21B_SLCD_LP41 (1ul << 21)
+#define PIN_PB16B_SLCD_LP42 48L /**< \brief SLCD signal: LP42 on PB16 mux B */
+#define MUX_PB16B_SLCD_LP42 1L
+#define PINMUX_PB16B_SLCD_LP42 ((PIN_PB16B_SLCD_LP42 << 16) | MUX_PB16B_SLCD_LP42)
+#define PORT_PB16B_SLCD_LP42 (1ul << 16)
+#define PIN_PB17B_SLCD_LP43 49L /**< \brief SLCD signal: LP43 on PB17 mux B */
+#define MUX_PB17B_SLCD_LP43 1L
+#define PINMUX_PB17B_SLCD_LP43 ((PIN_PB17B_SLCD_LP43 << 16) | MUX_PB17B_SLCD_LP43)
+#define PORT_PB17B_SLCD_LP43 (1ul << 17)
+#define PIN_PB18B_SLCD_LP44 50L /**< \brief SLCD signal: LP44 on PB18 mux B */
+#define MUX_PB18B_SLCD_LP44 1L
+#define PINMUX_PB18B_SLCD_LP44 ((PIN_PB18B_SLCD_LP44 << 16) | MUX_PB18B_SLCD_LP44)
+#define PORT_PB18B_SLCD_LP44 (1ul << 18)
+#define PIN_PB19B_SLCD_LP45 51L /**< \brief SLCD signal: LP45 on PB19 mux B */
+#define MUX_PB19B_SLCD_LP45 1L
+#define PINMUX_PB19B_SLCD_LP45 ((PIN_PB19B_SLCD_LP45 << 16) | MUX_PB19B_SLCD_LP45)
+#define PORT_PB19B_SLCD_LP45 (1ul << 19)
+#define PIN_PB20B_SLCD_LP46 52L /**< \brief SLCD signal: LP46 on PB20 mux B */
+#define MUX_PB20B_SLCD_LP46 1L
+#define PINMUX_PB20B_SLCD_LP46 ((PIN_PB20B_SLCD_LP46 << 16) | MUX_PB20B_SLCD_LP46)
+#define PORT_PB20B_SLCD_LP46 (1ul << 20)
+#define PIN_PB21B_SLCD_LP47 53L /**< \brief SLCD signal: LP47 on PB21 mux B */
+#define MUX_PB21B_SLCD_LP47 1L
+#define PINMUX_PB21B_SLCD_LP47 ((PIN_PB21B_SLCD_LP47 << 16) | MUX_PB21B_SLCD_LP47)
+#define PORT_PB21B_SLCD_LP47 (1ul << 21)
+#define PIN_PA20B_SLCD_LP48 20L /**< \brief SLCD signal: LP48 on PA20 mux B */
+#define MUX_PA20B_SLCD_LP48 1L
+#define PINMUX_PA20B_SLCD_LP48 ((PIN_PA20B_SLCD_LP48 << 16) | MUX_PA20B_SLCD_LP48)
+#define PORT_PA20B_SLCD_LP48 (1ul << 20)
+#define PIN_PA21B_SLCD_LP49 21L /**< \brief SLCD signal: LP49 on PA21 mux B */
+#define MUX_PA21B_SLCD_LP49 1L
+#define PINMUX_PA21B_SLCD_LP49 ((PIN_PA21B_SLCD_LP49 << 16) | MUX_PA21B_SLCD_LP49)
+#define PORT_PA21B_SLCD_LP49 (1ul << 21)
+#define PIN_PA22B_SLCD_LP50 22L /**< \brief SLCD signal: LP50 on PA22 mux B */
+#define MUX_PA22B_SLCD_LP50 1L
+#define PINMUX_PA22B_SLCD_LP50 ((PIN_PA22B_SLCD_LP50 << 16) | MUX_PA22B_SLCD_LP50)
+#define PORT_PA22B_SLCD_LP50 (1ul << 22)
+#define PIN_PA23B_SLCD_LP51 23L /**< \brief SLCD signal: LP51 on PA23 mux B */
+#define MUX_PA23B_SLCD_LP51 1L
+#define PINMUX_PA23B_SLCD_LP51 ((PIN_PA23B_SLCD_LP51 << 16) | MUX_PA23B_SLCD_LP51)
+#define PORT_PA23B_SLCD_LP51 (1ul << 23)
+/* ========== PORT definition for CCL peripheral ========== */
+#define PIN_PA04I_CCL_IN0 4L /**< \brief CCL signal: IN0 on PA04 mux I */
+#define MUX_PA04I_CCL_IN0 8L
+#define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0)
+#define PORT_PA04I_CCL_IN0 (1ul << 4)
+#define PIN_PA16I_CCL_IN0 16L /**< \brief CCL signal: IN0 on PA16 mux I */
+#define MUX_PA16I_CCL_IN0 8L
+#define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0)
+#define PORT_PA16I_CCL_IN0 (1ul << 16)
+#define PIN_PB22I_CCL_IN0 54L /**< \brief CCL signal: IN0 on PB22 mux I */
+#define MUX_PB22I_CCL_IN0 8L
+#define PINMUX_PB22I_CCL_IN0 ((PIN_PB22I_CCL_IN0 << 16) | MUX_PB22I_CCL_IN0)
+#define PORT_PB22I_CCL_IN0 (1ul << 22)
+#define PIN_PA05I_CCL_IN1 5L /**< \brief CCL signal: IN1 on PA05 mux I */
+#define MUX_PA05I_CCL_IN1 8L
+#define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1)
+#define PORT_PA05I_CCL_IN1 (1ul << 5)
+#define PIN_PA17I_CCL_IN1 17L /**< \brief CCL signal: IN1 on PA17 mux I */
+#define MUX_PA17I_CCL_IN1 8L
+#define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1)
+#define PORT_PA17I_CCL_IN1 (1ul << 17)
+#define PIN_PB00I_CCL_IN1 32L /**< \brief CCL signal: IN1 on PB00 mux I */
+#define MUX_PB00I_CCL_IN1 8L
+#define PINMUX_PB00I_CCL_IN1 ((PIN_PB00I_CCL_IN1 << 16) | MUX_PB00I_CCL_IN1)
+#define PORT_PB00I_CCL_IN1 (1ul << 0)
+#define PIN_PA06I_CCL_IN2 6L /**< \brief CCL signal: IN2 on PA06 mux I */
+#define MUX_PA06I_CCL_IN2 8L
+#define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2)
+#define PORT_PA06I_CCL_IN2 (1ul << 6)
+#define PIN_PA18I_CCL_IN2 18L /**< \brief CCL signal: IN2 on PA18 mux I */
+#define MUX_PA18I_CCL_IN2 8L
+#define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2)
+#define PORT_PA18I_CCL_IN2 (1ul << 18)
+#define PIN_PB01I_CCL_IN2 33L /**< \brief CCL signal: IN2 on PB01 mux I */
+#define MUX_PB01I_CCL_IN2 8L
+#define PINMUX_PB01I_CCL_IN2 ((PIN_PB01I_CCL_IN2 << 16) | MUX_PB01I_CCL_IN2)
+#define PORT_PB01I_CCL_IN2 (1ul << 1)
+#define PIN_PA08I_CCL_IN3 8L /**< \brief CCL signal: IN3 on PA08 mux I */
+#define MUX_PA08I_CCL_IN3 8L
+#define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3)
+#define PORT_PA08I_CCL_IN3 (1ul << 8)
+#define PIN_PA30I_CCL_IN3 30L /**< \brief CCL signal: IN3 on PA30 mux I */
+#define MUX_PA30I_CCL_IN3 8L
+#define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3)
+#define PORT_PA30I_CCL_IN3 (1ul << 30)
+#define PIN_PA09I_CCL_IN4 9L /**< \brief CCL signal: IN4 on PA09 mux I */
+#define MUX_PA09I_CCL_IN4 8L
+#define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4)
+#define PORT_PA09I_CCL_IN4 (1ul << 9)
+#define PIN_PC27I_CCL_IN4 91L /**< \brief CCL signal: IN4 on PC27 mux I */
+#define MUX_PC27I_CCL_IN4 8L
+#define PINMUX_PC27I_CCL_IN4 ((PIN_PC27I_CCL_IN4 << 16) | MUX_PC27I_CCL_IN4)
+#define PORT_PC27I_CCL_IN4 (1ul << 27)
+#define PIN_PA10I_CCL_IN5 10L /**< \brief CCL signal: IN5 on PA10 mux I */
+#define MUX_PA10I_CCL_IN5 8L
+#define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5)
+#define PORT_PA10I_CCL_IN5 (1ul << 10)
+#define PIN_PC28I_CCL_IN5 92L /**< \brief CCL signal: IN5 on PC28 mux I */
+#define MUX_PC28I_CCL_IN5 8L
+#define PINMUX_PC28I_CCL_IN5 ((PIN_PC28I_CCL_IN5 << 16) | MUX_PC28I_CCL_IN5)
+#define PORT_PC28I_CCL_IN5 (1ul << 28)
+#define PIN_PA22I_CCL_IN6 22L /**< \brief CCL signal: IN6 on PA22 mux I */
+#define MUX_PA22I_CCL_IN6 8L
+#define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6)
+#define PORT_PA22I_CCL_IN6 (1ul << 22)
+#define PIN_PB06I_CCL_IN6 38L /**< \brief CCL signal: IN6 on PB06 mux I */
+#define MUX_PB06I_CCL_IN6 8L
+#define PINMUX_PB06I_CCL_IN6 ((PIN_PB06I_CCL_IN6 << 16) | MUX_PB06I_CCL_IN6)
+#define PORT_PB06I_CCL_IN6 (1ul << 6)
+#define PIN_PA23I_CCL_IN7 23L /**< \brief CCL signal: IN7 on PA23 mux I */
+#define MUX_PA23I_CCL_IN7 8L
+#define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7)
+#define PORT_PA23I_CCL_IN7 (1ul << 23)
+#define PIN_PB07I_CCL_IN7 39L /**< \brief CCL signal: IN7 on PB07 mux I */
+#define MUX_PB07I_CCL_IN7 8L
+#define PINMUX_PB07I_CCL_IN7 ((PIN_PB07I_CCL_IN7 << 16) | MUX_PB07I_CCL_IN7)
+#define PORT_PB07I_CCL_IN7 (1ul << 7)
+#define PIN_PA24I_CCL_IN8 24L /**< \brief CCL signal: IN8 on PA24 mux I */
+#define MUX_PA24I_CCL_IN8 8L
+#define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8)
+#define PORT_PA24I_CCL_IN8 (1ul << 24)
+#define PIN_PB08I_CCL_IN8 40L /**< \brief CCL signal: IN8 on PB08 mux I */
+#define MUX_PB08I_CCL_IN8 8L
+#define PINMUX_PB08I_CCL_IN8 ((PIN_PB08I_CCL_IN8 << 16) | MUX_PB08I_CCL_IN8)
+#define PORT_PB08I_CCL_IN8 (1ul << 8)
+#define PIN_PB14I_CCL_IN9 46L /**< \brief CCL signal: IN9 on PB14 mux I */
+#define MUX_PB14I_CCL_IN9 8L
+#define PINMUX_PB14I_CCL_IN9 ((PIN_PB14I_CCL_IN9 << 16) | MUX_PB14I_CCL_IN9)
+#define PORT_PB14I_CCL_IN9 (1ul << 14)
+#define PIN_PC20I_CCL_IN9 84L /**< \brief CCL signal: IN9 on PC20 mux I */
+#define MUX_PC20I_CCL_IN9 8L
+#define PINMUX_PC20I_CCL_IN9 ((PIN_PC20I_CCL_IN9 << 16) | MUX_PC20I_CCL_IN9)
+#define PORT_PC20I_CCL_IN9 (1ul << 20)
+#define PIN_PB15I_CCL_IN10 47L /**< \brief CCL signal: IN10 on PB15 mux I */
+#define MUX_PB15I_CCL_IN10 8L
+#define PINMUX_PB15I_CCL_IN10 ((PIN_PB15I_CCL_IN10 << 16) | MUX_PB15I_CCL_IN10)
+#define PORT_PB15I_CCL_IN10 (1ul << 15)
+#define PIN_PC21I_CCL_IN10 85L /**< \brief CCL signal: IN10 on PC21 mux I */
+#define MUX_PC21I_CCL_IN10 8L
+#define PINMUX_PC21I_CCL_IN10 ((PIN_PC21I_CCL_IN10 << 16) | MUX_PC21I_CCL_IN10)
+#define PORT_PC21I_CCL_IN10 (1ul << 21)
+#define PIN_PB16I_CCL_IN11 48L /**< \brief CCL signal: IN11 on PB16 mux I */
+#define MUX_PB16I_CCL_IN11 8L
+#define PINMUX_PB16I_CCL_IN11 ((PIN_PB16I_CCL_IN11 << 16) | MUX_PB16I_CCL_IN11)
+#define PORT_PB16I_CCL_IN11 (1ul << 16)
+#define PIN_PA07I_CCL_OUT0 7L /**< \brief CCL signal: OUT0 on PA07 mux I */
+#define MUX_PA07I_CCL_OUT0 8L
+#define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0)
+#define PORT_PA07I_CCL_OUT0 (1ul << 7)
+#define PIN_PA19I_CCL_OUT0 19L /**< \brief CCL signal: OUT0 on PA19 mux I */
+#define MUX_PA19I_CCL_OUT0 8L
+#define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0)
+#define PORT_PA19I_CCL_OUT0 (1ul << 19)
+#define PIN_PB02I_CCL_OUT0 34L /**< \brief CCL signal: OUT0 on PB02 mux I */
+#define MUX_PB02I_CCL_OUT0 8L
+#define PINMUX_PB02I_CCL_OUT0 ((PIN_PB02I_CCL_OUT0 << 16) | MUX_PB02I_CCL_OUT0)
+#define PORT_PB02I_CCL_OUT0 (1ul << 2)
+#define PIN_PB23I_CCL_OUT0 55L /**< \brief CCL signal: OUT0 on PB23 mux I */
+#define MUX_PB23I_CCL_OUT0 8L
+#define PINMUX_PB23I_CCL_OUT0 ((PIN_PB23I_CCL_OUT0 << 16) | MUX_PB23I_CCL_OUT0)
+#define PORT_PB23I_CCL_OUT0 (1ul << 23)
+#define PIN_PA11I_CCL_OUT1 11L /**< \brief CCL signal: OUT1 on PA11 mux I */
+#define MUX_PA11I_CCL_OUT1 8L
+#define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1)
+#define PORT_PA11I_CCL_OUT1 (1ul << 11)
+#define PIN_PA31I_CCL_OUT1 31L /**< \brief CCL signal: OUT1 on PA31 mux I */
+#define MUX_PA31I_CCL_OUT1 8L
+#define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1)
+#define PORT_PA31I_CCL_OUT1 (1ul << 31)
+#define PIN_PB11I_CCL_OUT1 43L /**< \brief CCL signal: OUT1 on PB11 mux I */
+#define MUX_PB11I_CCL_OUT1 8L
+#define PINMUX_PB11I_CCL_OUT1 ((PIN_PB11I_CCL_OUT1 << 16) | MUX_PB11I_CCL_OUT1)
+#define PORT_PB11I_CCL_OUT1 (1ul << 11)
+#define PIN_PA25I_CCL_OUT2 25L /**< \brief CCL signal: OUT2 on PA25 mux I */
+#define MUX_PA25I_CCL_OUT2 8L
+#define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2)
+#define PORT_PA25I_CCL_OUT2 (1ul << 25)
+#define PIN_PB09I_CCL_OUT2 41L /**< \brief CCL signal: OUT2 on PB09 mux I */
+#define MUX_PB09I_CCL_OUT2 8L
+#define PINMUX_PB09I_CCL_OUT2 ((PIN_PB09I_CCL_OUT2 << 16) | MUX_PB09I_CCL_OUT2)
+#define PORT_PB09I_CCL_OUT2 (1ul << 9)
+#define PIN_PB17I_CCL_OUT3 49L /**< \brief CCL signal: OUT3 on PB17 mux I */
+#define MUX_PB17I_CCL_OUT3 8L
+#define PINMUX_PB17I_CCL_OUT3 ((PIN_PB17I_CCL_OUT3 << 16) | MUX_PB17I_CCL_OUT3)
+#define PORT_PB17I_CCL_OUT3 (1ul << 17)
+
+#endif /* _SAML22N16A_PIO_ */
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