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author | joeycastillo <joeycastillo@utexas.edu> | 2021-12-08 15:52:07 -0500 |
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committer | GitHub <noreply@github.com> | 2021-12-08 15:52:07 -0500 |
commit | c0d02ceddd233ccccd4926b6eb5b6fe54771aac0 (patch) | |
tree | 88c257f6b70111b4ae09fd8518e38e9197cd2a4e /tinyusb/hw/bsp/fomu/crt0-vexriscv.S | |
parent | c25b6929cd4a3db9daa33738350b969ec590cd28 (diff) | |
parent | d33d3fbd51253e3e072186a71959fdf97c8d2e75 (diff) | |
download | Sensor-Watch-c0d02ceddd233ccccd4926b6eb5b6fe54771aac0.tar.gz Sensor-Watch-c0d02ceddd233ccccd4926b6eb5b6fe54771aac0.tar.bz2 Sensor-Watch-c0d02ceddd233ccccd4926b6eb5b6fe54771aac0.zip |
Merge pull request #25 from willianpaixao/add-submodules
Add tinyusb as git submodules
Diffstat (limited to 'tinyusb/hw/bsp/fomu/crt0-vexriscv.S')
m--------- | tinyusb | 0 | ||||
-rwxr-xr-x | tinyusb/hw/bsp/fomu/crt0-vexriscv.S | 83 |
2 files changed, 0 insertions, 83 deletions
diff --git a/tinyusb b/tinyusb new file mode 160000 +Subproject f8288be03f28ad7b944e6925f49422dfa39202c diff --git a/tinyusb/hw/bsp/fomu/crt0-vexriscv.S b/tinyusb/hw/bsp/fomu/crt0-vexriscv.S deleted file mode 100755 index d80a29e0..00000000 --- a/tinyusb/hw/bsp/fomu/crt0-vexriscv.S +++ /dev/null @@ -1,83 +0,0 @@ -.global main -.global isr - -.section .text.start -.global _start - -_start: - j crt_init - -.section .text -.global trap_entry -trap_entry: - sw x1, - 1*4(sp) - sw x5, - 2*4(sp) - sw x6, - 3*4(sp) - sw x7, - 4*4(sp) - sw x10, - 5*4(sp) - sw x11, - 6*4(sp) - sw x12, - 7*4(sp) - sw x13, - 8*4(sp) - sw x14, - 9*4(sp) - sw x15, -10*4(sp) - sw x16, -11*4(sp) - sw x17, -12*4(sp) - sw x28, -13*4(sp) - sw x29, -14*4(sp) - sw x30, -15*4(sp) - sw x31, -16*4(sp) - addi sp,sp,-16*4 - call isr - lw x1 , 15*4(sp) - lw x5, 14*4(sp) - lw x6, 13*4(sp) - lw x7, 12*4(sp) - lw x10, 11*4(sp) - lw x11, 10*4(sp) - lw x12, 9*4(sp) - lw x13, 8*4(sp) - lw x14, 7*4(sp) - lw x15, 6*4(sp) - lw x16, 5*4(sp) - lw x17, 4*4(sp) - lw x28, 3*4(sp) - lw x29, 2*4(sp) - lw x30, 1*4(sp) - lw x31, 0*4(sp) - addi sp,sp,16*4 - mret - -.text -crt_init: - la sp, _estack - 4 - la a0, trap_entry - csrw mtvec, a0 - -bss_init: - la a0, _sbss - la a1, _ebss + 4 -bss_loop: - beq a0,a1,bss_done - sw zero,0(a0) - add a0,a0,4 - j bss_loop -bss_done: - - /* Load DATA */ - la t0, _etext - la t1, _srelocate - la t2, _erelocate + 4 -3: - lw t3, 0(t0) - sw t3, 0(t1) - /* _edata is aligned to 4 bytes. Use word-xfers. */ - addi t0, t0, 4 - addi t1, t1, 4 - bltu t1, t2, 3b - - li a0, 0x880 //880 enable timer + external interrupt sources (until mstatus.MIE is set, they will never trigger an interrupt) - csrw mie,a0 - - call main -infinite_loop: - j infinite_loop |