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author | Joey Castillo <jose.castillo@gmail.com> | 2021-09-20 17:37:55 -0400 |
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committer | Joey Castillo <jose.castillo@gmail.com> | 2021-09-20 17:37:55 -0400 |
commit | 24e160611e12df8d31edc02af21ce07ad0929e1b (patch) | |
tree | b49190496ee47d657ab2d1c7bfc5abacf6e36687 /watch-library/config/peripheral_clk_config.h | |
parent | 63322a3b7f7f5d5534fbd933576c7fcf69103afb (diff) | |
download | Sensor-Watch-24e160611e12df8d31edc02af21ce07ad0929e1b.tar.gz Sensor-Watch-24e160611e12df8d31edc02af21ce07ad0929e1b.tar.bz2 Sensor-Watch-24e160611e12df8d31edc02af21ce07ad0929e1b.zip |
add more atmel studio framework code
Diffstat (limited to 'watch-library/config/peripheral_clk_config.h')
-rw-r--r-- | watch-library/config/peripheral_clk_config.h | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/watch-library/config/peripheral_clk_config.h b/watch-library/config/peripheral_clk_config.h index 61619b6a..523b036c 100644 --- a/watch-library/config/peripheral_clk_config.h +++ b/watch-library/config/peripheral_clk_config.h @@ -132,6 +132,58 @@ #define CONF_GCLK_SERCOM1_SLOW_FREQUENCY 32768 #endif +// <y> Core Clock Source +// <id> core_gclk_selection + +// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 + +// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 + +// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 + +// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 + +// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 + +// <i> Select the clock source for CORE. +#ifndef CONF_GCLK_SERCOM3_CORE_SRC +#define CONF_GCLK_SERCOM3_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +// <y> Slow Clock Source +// <id> slow_gclk_selection + +// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 + +// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 + +// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 + +// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 + +// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 + +// <i> Select the slow clock source. +#ifndef CONF_GCLK_SERCOM3_SLOW_SRC +#define CONF_GCLK_SERCOM3_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val +#endif + +/** + * \def CONF_GCLK_SERCOM3_CORE_FREQUENCY + * \brief SERCOM3's Core Clock frequency + */ +#ifndef CONF_GCLK_SERCOM3_CORE_FREQUENCY +#define CONF_GCLK_SERCOM3_CORE_FREQUENCY 4000000 +#endif + +/** + * \def CONF_GCLK_SERCOM3_SLOW_FREQUENCY + * \brief SERCOM3's Slow Clock frequency + */ +#ifndef CONF_GCLK_SERCOM3_SLOW_FREQUENCY +#define CONF_GCLK_SERCOM3_SLOW_FREQUENCY 32768 +#endif + // <y> TC Clock Source // <id> tc_gclk_selection |