add more atmel studio framework code

5 files changed, 327 insertions, 0 deletions

diff --git a/watch-library/config/hpl_nvmctrl_config.h b/watch-library/config/hpl_nvmctrl_config.h
new file mode 100755
index 00000000..76d49bac
--- /dev/null
+++ b/watch-library/config/hpl_nvmctrl_config.h
@@ -0,0 +1,38 @@
+/* Auto-generated config file hpl_nvmctrl_config.h */
+#ifndef HPL_NVMCTRL_CONFIG_H
+#define HPL_NVMCTRL_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <h> Basic Settings
+
+// <o> Read Mode Selection
+// <0x00=> No Miss Penalty
+// <0x01=> Low Power
+// <0x02=> Deterministic
+// <id> nvm_arch_read_mode
+#ifndef CONF_NVM_READ_MODE
+#define CONF_NVM_READ_MODE 1
+#endif
+
+// <o> Power Reduction Mode During Sleep
+// <0x00=> Wake On Access
+// <0x01=> Wake Up Instant
+// <0x03=> Disabled
+// <id> nvm_arch_sleepprm
+#ifndef CONF_NVM_SLEEPPRM
+#define CONF_NVM_SLEEPPRM 0
+#endif
+
+// <q> Cache Disable
+// <i> Indicate whether cache is disable or not
+// <id> nvm_arch_cache
+#ifndef CONF_NVM_CACHE
+#define CONF_NVM_CACHE 0
+#endif
+
+// </h>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_NVMCTRL_CONFIG_H
diff --git a/watch-library/config/hpl_sercom_config.h b/watch-library/config/hpl_sercom_config.h
index ad16e642..a0eb1206 100644
--- a/watch-library/config/hpl_sercom_config.h
+++ b/watch-library/config/hpl_sercom_config.h
@@ -139,6 +139,165 @@
 #endif
 #endif
 
+#include <peripheral_clk_config.h>
+
+// Enable configuration of module
+#ifndef CONF_SERCOM_3_SPI_ENABLE
+#define CONF_SERCOM_3_SPI_ENABLE 0
+#endif
+
+// Set module in SPI Master mode
+#ifndef CONF_SERCOM_3_SPI_MODE
+#define CONF_SERCOM_3_SPI_MODE 0x03
+#endif
+
+// <h> Basic Configuration
+
+// <q> Receive buffer enable
+// <i> Enable receive buffer to receive data from slave (RXEN)
+// <id> spi_master_rx_enable
+#ifndef CONF_SERCOM_3_SPI_RXEN
+#define CONF_SERCOM_3_SPI_RXEN 0x1
+#endif
+
+// <o> Character Size
+// <i> Bit size for all characters sent over the SPI bus (CHSIZE)
+// <0x0=>8 bits
+// <0x1=>9 bits
+// <id> spi_master_character_size
+#ifndef CONF_SERCOM_3_SPI_CHSIZE
+#define CONF_SERCOM_3_SPI_CHSIZE 0x0
+#endif
+// <o> Baud rate <1-12000000>
+// <i> The SPI data transfer rate
+// <id> spi_master_baud_rate
+#ifndef CONF_SERCOM_3_SPI_BAUD
+#define CONF_SERCOM_3_SPI_BAUD 50000
+#endif
+
+// </h>
+
+// <e> Advanced Configuration
+// <id> spi_master_advanced
+#ifndef CONF_SERCOM_3_SPI_ADVANCED
+#define CONF_SERCOM_3_SPI_ADVANCED 0
+#endif
+
+// <o> Dummy byte <0x00-0x1ff>
+// <id> spi_master_dummybyte
+// <i> Dummy byte used when reading data from the slave without sending any data
+#ifndef CONF_SERCOM_3_SPI_DUMMYBYTE
+#define CONF_SERCOM_3_SPI_DUMMYBYTE 0x1ff
+#endif
+
+// <o> Data Order
+// <0=>MSB first
+// <1=>LSB first
+// <i> I least significant or most significant bit is shifted out first (DORD)
+// <id> spi_master_arch_dord
+#ifndef CONF_SERCOM_3_SPI_DORD
+#define CONF_SERCOM_3_SPI_DORD 0x0
+#endif
+
+// <o> Clock Polarity
+// <0=>SCK is low when idle
+// <1=>SCK is high when idle
+// <i> Determines if the leading edge is rising or falling with a corresponding opposite edge at the trailing edge. (CPOL)
+// <id> spi_master_arch_cpol
+#ifndef CONF_SERCOM_3_SPI_CPOL
+#define CONF_SERCOM_3_SPI_CPOL 0x0
+#endif
+
+// <o> Clock Phase
+// <0x0=>Sample input on leading edge
+// <0x1=>Sample input on trailing edge
+// <i> Determines if input data is sampled on leading or trailing SCK edge. (CPHA)
+// <id> spi_master_arch_cpha
+#ifndef CONF_SERCOM_3_SPI_CPHA
+#define CONF_SERCOM_3_SPI_CPHA 0x0
+#endif
+
+// <o> Immediate Buffer Overflow Notification
+// <i> Controls when OVF is asserted (IBON)
+// <0x0=>In data stream
+// <0x1=>On buffer overflow
+// <id> spi_master_arch_ibon
+#ifndef CONF_SERCOM_3_SPI_IBON
+#define CONF_SERCOM_3_SPI_IBON 0x0
+#endif
+
+// <q> Run in stand-by
+// <i> Module stays active in stand-by sleep mode. (RUNSTDBY)
+// <id> spi_master_arch_runstdby
+#ifndef CONF_SERCOM_3_SPI_RUNSTDBY
+#define CONF_SERCOM_3_SPI_RUNSTDBY 0x0
+#endif
+
+// <o> Debug Stop Mode
+// <i> Behavior of the baud-rate generator when CPU is halted by external debugger. (DBGSTOP)
+// <0=>Keep running
+// <1=>Halt
+// <id> spi_master_arch_dbgstop
+#ifndef CONF_SERCOM_3_SPI_DBGSTOP
+#define CONF_SERCOM_3_SPI_DBGSTOP 0
+#endif
+
+// </e>
+
+// Address mode disabled in master mode
+#ifndef CONF_SERCOM_3_SPI_AMODE_EN
+#define CONF_SERCOM_3_SPI_AMODE_EN 0
+#endif
+
+#ifndef CONF_SERCOM_3_SPI_AMODE
+#define CONF_SERCOM_3_SPI_AMODE 0
+#endif
+
+#ifndef CONF_SERCOM_3_SPI_ADDR
+#define CONF_SERCOM_3_SPI_ADDR 0
+#endif
+
+#ifndef CONF_SERCOM_3_SPI_ADDRMASK
+#define CONF_SERCOM_3_SPI_ADDRMASK 0
+#endif
+
+#ifndef CONF_SERCOM_3_SPI_SSDE
+#define CONF_SERCOM_3_SPI_SSDE 0
+#endif
+
+#ifndef CONF_SERCOM_3_SPI_MSSEN
+#define CONF_SERCOM_3_SPI_MSSEN 0x0
+#endif
+
+#ifndef CONF_SERCOM_3_SPI_PLOADEN
+#define CONF_SERCOM_3_SPI_PLOADEN 0
+#endif
+
+// <o> Receive Data Pinout
+// <0x0=>PAD[0]
+// <0x1=>PAD[1]
+// <0x2=>PAD[2]
+// <0x3=>PAD[3]
+// <id> spi_master_rxpo
+#ifndef CONF_SERCOM_3_SPI_RXPO
+#define CONF_SERCOM_3_SPI_RXPO 2
+#endif
+
+// <o> Transmit Data Pinout
+// <0x0=>PAD[0,1]_DO_SCK
+// <0x1=>PAD[2,3]_DO_SCK
+// <0x2=>PAD[3,1]_DO_SCK
+// <0x3=>PAD[0,3]_DO_SCK
+// <id> spi_master_txpo
+#ifndef CONF_SERCOM_3_SPI_TXPO
+#define CONF_SERCOM_3_SPI_TXPO 3
+#endif
+
+// Calculate baud register value from requested baudrate value
+#ifndef CONF_SERCOM_3_SPI_BAUD_RATE
+#define CONF_SERCOM_3_SPI_BAUD_RATE ((float)CONF_GCLK_SERCOM3_CORE_FREQUENCY / (float)(2 * CONF_SERCOM_3_SPI_BAUD)) - 1
+#endif
+
 // <<< end of configuration section >>>
 
 #endif // HPL_SERCOM_CONFIG_H
diff --git a/watch-library/config/hpl_trng_config.h b/watch-library/config/hpl_trng_config.h
new file mode 100755
index 00000000..ba901498
--- /dev/null
+++ b/watch-library/config/hpl_trng_config.h
@@ -0,0 +1,27 @@
+/* Auto-generated config file hpl_trng_config.h */
+#ifndef HPL_TRNG_CONFIG_H
+#define HPL_TRNG_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <h> Advanced configurations
+
+// <q> Run In Standby
+// <i> Indicates whether the TRNG works in standby mode
+// <id> trng_runstdby
+#ifndef CONF_TRNG_RUNSTDBY
+#define CONF_TRNG_RUNSTDBY 0
+#endif
+
+// <q> Data Ready Event Output Enable
+// <i> Indicates whether the TRNG generates event on Data Ready
+// <id> trng_datardyeo
+#ifndef CONF_TRNG_DATARDYEO
+#define CONF_TRNG_DATARDYEO 0
+#endif
+
+// </h>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_TRNG_CONFIG_H
diff --git a/watch-library/config/nv_storage_config.h b/watch-library/config/nv_storage_config.h
new file mode 100755
index 00000000..4888d1bd
--- /dev/null
+++ b/watch-library/config/nv_storage_config.h
@@ -0,0 +1,51 @@
+/* Auto-generated config file nv_storage_config.h */
+#ifndef NV_STORAGE_CONFIG_H
+#define NV_STORAGE_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+//<o> Storage start address <0x00000000-0xFFFFFFFF>
+//<i> This defines the start address of device flash for storage.
+//<i> The start address should be in device flash area.
+//<i> The start address and (start address + Item Number * Sector size) cannot beyond device flash area.
+//<id> conf_storage_memory_start
+#ifndef CONF_STORAGE_MEMORY_START
+#define CONF_STORAGE_MEMORY_START 0x10000
+#endif
+
+//<o> Item number <0-65535>
+//<i> This defines the maximum number of elements stored in persistent storage
+//<id> conf_max_item_number
+#ifndef CONF_MAX_ITEM_NUMBER
+#define CONF_MAX_ITEM_NUMBER 10
+#endif
+
+//<o> Sector size <0-65535>
+//<i> This defines the size of one storage sector in bytes
+//<id> conf_sector_size
+#ifndef CONF_SECTOR_SIZE
+#define CONF_SECTOR_SIZE 4096
+#endif
+
+/**
+ * Check If the Storage configuration out of the flash area.
+ */
+#ifdef FLASH_SIZE
+#if (CONF_STORAGE_MEMORY_START + (SECTOR_AMOUNT * CONF_SECTOR_SIZE)) > FLASH_SIZE
+#error Invalidate storage configuration, make sure the configuration with \
+the sector start address (CONF_STORAGE_MEMORY_START) and sector size (CONF_SECTOR_SIZE) \
+are located within the device flash size.
+#endif
+#endif
+
+#ifdef IFLASH_SIZE
+#if (CONF_STORAGE_MEMORY_START + (SECTOR_AMOUNT * CONF_SECTOR_SIZE)) > IFLASH_SIZE
+#error Invalidate storage configuration, make sure the configuration with \
+the sector start address (CONF_STORAGE_MEMORY_START) and sector size (CONF_SECTOR_SIZE) \
+are located within the device flash size.
+#endif
+#endif
+
+// <<< end of configuration section >>>
+
+#endif // NV_STORAGE_CONFIG_H
diff --git a/watch-library/config/peripheral_clk_config.h b/watch-library/config/peripheral_clk_config.h
index 61619b6a..523b036c 100644
--- a/watch-library/config/peripheral_clk_config.h
+++ b/watch-library/config/peripheral_clk_config.h
@@ -132,6 +132,58 @@
 #define CONF_GCLK_SERCOM1_SLOW_FREQUENCY 32768
 #endif
 
+// <y> Core Clock Source
+// <id> core_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <i> Select the clock source for CORE.
+#ifndef CONF_GCLK_SERCOM3_CORE_SRC
+#define CONF_GCLK_SERCOM3_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+// <y> Slow Clock Source
+// <id> slow_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <i> Select the slow clock source.
+#ifndef CONF_GCLK_SERCOM3_SLOW_SRC
+#define CONF_GCLK_SERCOM3_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM3_CORE_FREQUENCY
+ * \brief SERCOM3's Core Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM3_CORE_FREQUENCY
+#define CONF_GCLK_SERCOM3_CORE_FREQUENCY 4000000
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM3_SLOW_FREQUENCY
+ * \brief SERCOM3's Slow Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM3_SLOW_FREQUENCY
+#define CONF_GCLK_SERCOM3_SLOW_FREQUENCY 32768
+#endif
+
 // <y> TC Clock Source
 // <id> tc_gclk_selection