diff options
| author | Alexsander Akers <me@a2.io> | 2022-01-25 15:03:22 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-01-25 15:03:22 -0500 |
| commit | b8de35658ffd78ad8b22f91ccbbd3d63663afda9 (patch) | |
| tree | 1f265ddfcc8e5abf0316b81b15f80bf5c70fa7b7 /watch-library/config | |
| parent | 9e24f6c336773c7404139ab4db0eaab2f99504e2 (diff) | |
| download | Sensor-Watch-b8de35658ffd78ad8b22f91ccbbd3d63663afda9.tar.gz Sensor-Watch-b8de35658ffd78ad8b22f91ccbbd3d63663afda9.tar.bz2 Sensor-Watch-b8de35658ffd78ad8b22f91ccbbd3d63663afda9.zip | |
Sensor Watch Simulator (#35)
* Put something on screen
* Use the 32bit watch_date_time repr to pass from JS
* Implement periodic callbacks
* Clear display on enabling
* Hook up watch_set_led_color() to SVG (green-only)
* Make debug output full-width
* Remove default Emscripten canvas
* Implement sleep and button clicks
* Fix time zone conversion bug in beats-time app
* Clean up warnings
* Fix pin levels
* Set time zone to browser value (if available)
* Add basic backup data saving
* Silence format specifier warnings in both targets
* Remove unnecessary, copied files
* Use RTC pointer to clear callbacks (if available)
* Use preprocessor define to avoid hardcoding MOVEMENT_NUM_FACES
* Change each face to const preprocessor definition
* Remove Intl.DateTimeFormat usage
* Update shell.html title, header
* Add touch start/end event handlers on SVG buttons
* Update shell.html
* Update folder structure (shared, simulator, hardware under watch-library)
* Tease out shared components from watch_slcd
* Clean up simulator watch_slcd.c inline JS calls
* Fix missing newlines at end of file
* Add simulator warnings (except format, unused-paremter)
* Implement remaining watch_rtc functions
* Fix button bug on mouse down then drag out
* Implement remaining watch_slcd functions
* Link keyboard events to buttons (for keys A, L, M)
* Rewrite event handling (mouse, touch, keyboard) in C
* Set explicit text UTF-8 charset in shell.html
* Address PR comments
* Remove unused directories from include paths
Diffstat (limited to 'watch-library/config')
| -rw-r--r-- | watch-library/config/RTE_Components.h | 54 | ||||
| -rw-r--r-- | watch-library/config/hpl_dmac_config.h | 3122 | ||||
| -rw-r--r-- | watch-library/config/hpl_eic_config.h | 736 | ||||
| -rw-r--r-- | watch-library/config/hpl_gclk_config.h | 388 | ||||
| -rw-r--r-- | watch-library/config/hpl_mclk_config.h | 85 | ||||
| -rwxr-xr-x | watch-library/config/hpl_nvmctrl_config.h | 38 | ||||
| -rw-r--r-- | watch-library/config/hpl_osc32kctrl_config.h | 177 | ||||
| -rw-r--r-- | watch-library/config/hpl_oscctrl_config.h | 483 | ||||
| -rw-r--r-- | watch-library/config/hpl_port_config.h | 284 | ||||
| -rw-r--r-- | watch-library/config/hpl_rtc_config.h | 318 | ||||
| -rw-r--r-- | watch-library/config/hpl_sercom_config.h | 303 | ||||
| -rw-r--r-- | watch-library/config/hpl_slcd_config.h | 239 | ||||
| -rw-r--r-- | watch-library/config/hpl_systick_config.h | 18 | ||||
| -rwxr-xr-x | watch-library/config/hpl_trng_config.h | 27 | ||||
| -rwxr-xr-x | watch-library/config/nv_storage_config.h | 51 | ||||
| -rw-r--r-- | watch-library/config/peripheral_clk_config.h | 266 |
16 files changed, 0 insertions, 6589 deletions
diff --git a/watch-library/config/RTE_Components.h b/watch-library/config/RTE_Components.h deleted file mode 100644 index 3ba6b1ba..00000000 --- a/watch-library/config/RTE_Components.h +++ /dev/null @@ -1,54 +0,0 @@ - /**
- * \file
- *
- * \brief Autogenerated API include file for the Atmel Configuration Management Engine (ACME)
- *
- * Copyright (c) 2012 Atmel Corporation. All rights reserved.
- *
- * \acme_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \acme_license_stop
- *
- * Project: My Project
- * Target: ATSAML22J18A
- *
- **/
-
-
-#ifndef RTE_COMPONENTS_H
-#define RTE_COMPONENTS_H
-
-
-#define ATMEL_START
-
-#endif /* RTE_COMPONENTS_H */
diff --git a/watch-library/config/hpl_dmac_config.h b/watch-library/config/hpl_dmac_config.h deleted file mode 100644 index 36adb88b..00000000 --- a/watch-library/config/hpl_dmac_config.h +++ /dev/null @@ -1,3122 +0,0 @@ -/* Auto-generated config file hpl_dmac_config.h */ -#ifndef HPL_DMAC_CONFIG_H -#define HPL_DMAC_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// <e> DMAC enable -// <i> Indicates whether dmac is enabled or not -// <id> dmac_enable -#ifndef CONF_DMAC_ENABLE -#define CONF_DMAC_ENABLE 0 -#endif - -// <q> Priority Level 0 -// <i> Indicates whether Priority Level 0 is enabled or not -// <id> dmac_lvlen0 -#ifndef CONF_DMAC_LVLEN0 -#define CONF_DMAC_LVLEN0 0 -#endif - -// <o> Level 0 Round-Robin Arbitration -// <0=> Static arbitration scheme for channel with priority 0 -// <1=> Round-robin arbitration scheme for channel with priority 0 -// <i> Defines Level 0 Arbitration for DMA channels -// <id> dmac_rrlvlen0 -#ifndef CONF_DMAC_RRLVLEN0 -#define CONF_DMAC_RRLVLEN0 0 -#endif - -// <o> Level 0 Channel Priority Number <0x00-0xFF> -// <id> dmac_lvlpri0 -#ifndef CONF_DMAC_LVLPRI0 -#define CONF_DMAC_LVLPRI0 0 -#endif - -// <q> Priority Level 1 -// <i> Indicates whether Priority Level 1 is enabled or not -// <id> dmac_lvlen1 -#ifndef CONF_DMAC_LVLEN1 -#define CONF_DMAC_LVLEN1 0 -#endif - -// <o> Level 1 Round-Robin Arbitration -// <0=> Static arbitration scheme for channel with priority 1 -// <1=> Round-robin arbitration scheme for channel with priority 1 -// <i> Defines Level 1 Arbitration for DMA channels -// <id> dmac_rrlvlen1 -#ifndef CONF_DMAC_RRLVLEN1 -#define CONF_DMAC_RRLVLEN1 0 -#endif - -// <o> Level 1 Channel Priority Number <0x00-0xFF> -// <id> dmac_lvlpri1 -#ifndef CONF_DMAC_LVLPRI1 -#define CONF_DMAC_LVLPRI1 0 -#endif - -// <q> Priority Level 2 -// <i> Indicates whether Priority Level 2 is enabled or not -// <id> dmac_lvlen2 -#ifndef CONF_DMAC_LVLEN2 -#define CONF_DMAC_LVLEN2 0 -#endif - -// <o> Level 2 Round-Robin Arbitration -// <0=> Static arbitration scheme for channel with priority 2 -// <1=> Round-robin arbitration scheme for channel with priority 2 -// <i> Defines Level 2 Arbitration for DMA channels -// <id> dmac_rrlvlen2 -#ifndef CONF_DMAC_RRLVLEN2 -#define CONF_DMAC_RRLVLEN2 0 -#endif - -// <o> Level 2 Channel Priority Number <0x00-0xFF> -// <id> dmac_lvlpri2 -#ifndef CONF_DMAC_LVLPRI2 -#define CONF_DMAC_LVLPRI2 0 -#endif - -// <q> Priority Level 3 -// <i> Indicates whether Priority Level 3 is enabled or not -// <id> dmac_lvlen3 -#ifndef CONF_DMAC_LVLEN3 -#define CONF_DMAC_LVLEN3 0 -#endif - -// <o> Level 3 Round-Robin Arbitration -// <0=> Static arbitration scheme for channel with priority 3 -// <1=> Round-robin arbitration scheme for channel with priority 3 -// <i> Defines Level 3 Arbitration for DMA channels -// <id> dmac_rrlvlen3 -#ifndef CONF_DMAC_RRLVLEN3 -#define CONF_DMAC_RRLVLEN3 0 -#endif - -// <o> Level 3 Channel Priority Number <0x00-0xFF> -// <id> dmac_lvlpri3 -#ifndef CONF_DMAC_LVLPRI3 -#define CONF_DMAC_LVLPRI3 0 -#endif - -// <o> Data Transfer Quality of Service -// <0=> Background (no sensitive operation) -// <1=> Sensitive bandwidth -// <2=> Sensitive latency -// <3=> Critical latency -// <i> Defines the memory priority access during the data transfer operation -// <id> dmac_dqos -#ifndef CONF_DMAC_DQOS -#define CONF_DMAC_DQOS 0 -#endif - -// <o> Fetch Quality of Service -// <0=> Background (no sensitive operation) -// <1=> Sensitive bandwidth -// <2=> Sensitive latency -// <3=> Critical latency -// <i> Defines the memory priority access during the fetch operation -// <id> dmac_fqos -#ifndef CONF_DMAC_FQOS -#define CONF_DMAC_FQOS 0 -#endif - -// <o> Write-Back Quality of Service -// <0=> Background (no sensitive operation) -// <1=> Sensitive bandwidth -// <2=> Sensitive latency -// <3=> Critical latency -// <i> Defines the memory priority access during the write-back operation -// <id> dmac_wrbqos -#ifndef CONF_DMAC_WRBQOS -#define CONF_DMAC_WRBQOS 0 -#endif - -// <q> Debug Run -// <i> Indicates whether Debug Run is enabled or not -// <id> dmac_dbgrun -#ifndef CONF_DMAC_DBGRUN -#define CONF_DMAC_DBGRUN 0 -#endif - -// <e> Channel 0 settings -// <id> dmac_channel_0_settings -#ifndef CONF_DMAC_CHANNEL_0_SETTINGS -#define CONF_DMAC_CHANNEL_0_SETTINGS 0 -#endif - -// <q> Channel Enable -// <i> Indicates whether channel 0 is enabled or not -// <id> dmac_enable_0 -#ifndef CONF_DMAC_ENABLE_0 -#define CONF_DMAC_ENABLE_0 0 -#endif - -// <q> Channel Run in Standby -// <i> Indicates whether channel 0 is running in standby mode or not -// <id> dmac_runstdby_0 -#ifndef CONF_DMAC_RUNSTDBY_0 -#define CONF_DMAC_RUNSTDBY_0 0 -#endif - -// <o> Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// <i> Defines the trigger action used for a transfer -// <id> dmac_trigact_0 -#ifndef CONF_DMAC_TRIGACT_0 -#define CONF_DMAC_TRIGACT_0 0 -#endif - -// <o> Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Timestamp -// <0x02=> SERCOM0 RX Trigger -// <0x03=> SERCOM0 TX Trigger -// <0x04=> SERCOM1 RX Trigger -// <0x05=> SERCOM1 TX Trigger -// <0x06=> SERCOM2 RX Trigger -// <0x07=> SERCOM2 TX Trigger -// <0x08=> SERCOM3 RX Trigger -// <0x09=> SERCOM3 TX Trigger -// <0x0A=> SERCOM4 RX Trigger -// <0x0B=> SERCOM4 TX Trigger -// <0x0C=> SERCOM5 RX Trigger -// <0x0D=> SERCOM5 TX Trigger -// <0x0E=> TCC0 Overflow Trigger -// <0x0F=> TCC0 Match/Compare 0 Trigger -// <0x10=> TCC0 Match/Compare 1 Trigger -// <0x11=> TCC0 Match/Compare 2 Trigger -// <0x12=> TCC0 Match/Compare 3 Trigger -// <0x13=> TC0 Overflow Trigger -// <0x14=> TC0 Match/Compare 0 Trigger -// <0x15=> TC0 Match/Compare 1 Trigger -// <0x16=> TC1 Overflow Trigger -// <0x17=> TC1 Match/Compare 0 Trigger -// <0x18=> TC1 Match/Compare 1 Trigger -// <0x19=> TC2 Overflow Trigger -// <0x1A=> TC2 Match/Compare 0 Trigger -// <0x1B=> TC2 Match/Compare 1 Trigger -// <0x1C=> TC3 Overflow Trigger -// <0x1D=> TC3 Match/Compare 0 Trigger -// <0x1E=> TC3 Match/Compare 1 Trigger -// <0x1F=> ADC Result Ready Trigger -// <0x20=> SLCD Display Memory Update Trigger -// <0x21=> SLCD Automated Character Mapping Data Ready Trigger -// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger -// <0x23=> AES Write Trigger -// <0x24=> AES Read Trigger -// <0x25=> PTC End of Conversion Trigger -// <0x26=> PTC Sequence Trigger -// <0x27=> PTC Window Comparator Trigger -// <i> Defines the peripheral trigger which is source of the transfer -// <id> dmac_trifsrc_0 -#ifndef CONF_DMAC_TRIGSRC_0 -#define CONF_DMAC_TRIGSRC_0 0 -#endif - -// <o> Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// <i> Defines the arbitration level for this channel -// <id> dmac_lvl_0 -#ifndef CONF_DMAC_LVL_0 -#define CONF_DMAC_LVL_0 0 -#endif - -// <q> Channel Event Output -// <i> Indicates whether channel event generation is enabled or not -// <id> dmac_evoe_0 -#ifndef CONF_DMAC_EVOE_0 -#define CONF_DMAC_EVOE_0 0 -#endif - -// <q> Channel Event Input -// <i> Indicates whether channel event reception is enabled or not -// <id> dmac_evie_0 -#ifndef CONF_DMAC_EVIE_0 -#define CONF_DMAC_EVIE_0 0 -#endif - -// <o> Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// <i> Defines the event input action -// <id> dmac_evact_0 -#ifndef CONF_DMAC_EVACT_0 -#define CONF_DMAC_EVACT_0 0 -#endif - -// <o> Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// <i> Defines the address increment step size, applies to source or destination address -// <id> dmac_stepsize_0 -#ifndef CONF_DMAC_STEPSIZE_0 -#define CONF_DMAC_STEPSIZE_0 0 -#endif - -// <o> Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// <i> Defines whether source or destination addresses are using the step size settings -// <id> dmac_stepsel_0 -#ifndef CONF_DMAC_STEPSEL_0 -#define CONF_DMAC_STEPSEL_0 0 -#endif - -// <q> Source Address Increment -// <i> Indicates whether the source address incrementation is enabled or not -// <id> dmac_srcinc_0 -#ifndef CONF_DMAC_SRCINC_0 -#define CONF_DMAC_SRCINC_0 0 -#endif - -// <q> Destination Address Increment -// <i> Indicates whether the destination address incrementation is enabled or not -// <id> dmac_dstinc_0 -#ifndef CONF_DMAC_DSTINC_0 -#define CONF_DMAC_DSTINC_0 0 -#endif - -// <o> Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// <i> Defines the size of one beat -// <id> dmac_beatsize_0 -#ifndef CONF_DMAC_BEATSIZE_0 -#define CONF_DMAC_BEATSIZE_0 0 -#endif - -// <o> Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// <i> Defines the the DMAC should take after a block transfer has completed -// <id> dmac_blockact_0 -#ifndef CONF_DMAC_BLOCKACT_0 -#define CONF_DMAC_BLOCKACT_0 0 -#endif - -// <o> Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// <i> Defines the event output selection -// <id> dmac_evosel_0 -#ifndef CONF_DMAC_EVOSEL_0 -#define CONF_DMAC_EVOSEL_0 0 -#endif -// </e> - -// <e> Channel 1 settings -// <id> dmac_channel_1_settings -#ifndef CONF_DMAC_CHANNEL_1_SETTINGS -#define CONF_DMAC_CHANNEL_1_SETTINGS 0 -#endif - -// <q> Channel Enable -// <i> Indicates whether channel 1 is enabled or not -// <id> dmac_enable_1 -#ifndef CONF_DMAC_ENABLE_1 -#define CONF_DMAC_ENABLE_1 0 -#endif - -// <q> Channel Run in Standby -// <i> Indicates whether channel 1 is running in standby mode or not -// <id> dmac_runstdby_1 -#ifndef CONF_DMAC_RUNSTDBY_1 -#define CONF_DMAC_RUNSTDBY_1 0 -#endif - -// <o> Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// <i> Defines the trigger action used for a transfer -// <id> dmac_trigact_1 -#ifndef CONF_DMAC_TRIGACT_1 -#define CONF_DMAC_TRIGACT_1 0 -#endif - -// <o> Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Timestamp -// <0x02=> SERCOM0 RX Trigger -// <0x03=> SERCOM0 TX Trigger -// <0x04=> SERCOM1 RX Trigger -// <0x05=> SERCOM1 TX Trigger -// <0x06=> SERCOM2 RX Trigger -// <0x07=> SERCOM2 TX Trigger -// <0x08=> SERCOM3 RX Trigger -// <0x09=> SERCOM3 TX Trigger -// <0x0A=> SERCOM4 RX Trigger -// <0x0B=> SERCOM4 TX Trigger -// <0x0C=> SERCOM5 RX Trigger -// <0x0D=> SERCOM5 TX Trigger -// <0x0E=> TCC0 Overflow Trigger -// <0x0F=> TCC0 Match/Compare 0 Trigger -// <0x10=> TCC0 Match/Compare 1 Trigger -// <0x11=> TCC0 Match/Compare 2 Trigger -// <0x12=> TCC0 Match/Compare 3 Trigger -// <0x13=> TC0 Overflow Trigger -// <0x14=> TC0 Match/Compare 0 Trigger -// <0x15=> TC0 Match/Compare 1 Trigger -// <0x16=> TC1 Overflow Trigger -// <0x17=> TC1 Match/Compare 0 Trigger -// <0x18=> TC1 Match/Compare 1 Trigger -// <0x19=> TC2 Overflow Trigger -// <0x1A=> TC2 Match/Compare 0 Trigger -// <0x1B=> TC2 Match/Compare 1 Trigger -// <0x1C=> TC3 Overflow Trigger -// <0x1D=> TC3 Match/Compare 0 Trigger -// <0x1E=> TC3 Match/Compare 1 Trigger -// <0x1F=> ADC Result Ready Trigger -// <0x20=> SLCD Display Memory Update Trigger -// <0x21=> SLCD Automated Character Mapping Data Ready Trigger -// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger -// <0x23=> AES Write Trigger -// <0x24=> AES Read Trigger -// <0x25=> PTC End of Conversion Trigger -// <0x26=> PTC Sequence Trigger -// <0x27=> PTC Window Comparator Trigger -// <i> Defines the peripheral trigger which is source of the transfer -// <id> dmac_trifsrc_1 -#ifndef CONF_DMAC_TRIGSRC_1 -#define CONF_DMAC_TRIGSRC_1 0 -#endif - -// <o> Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// <i> Defines the arbitration level for this channel -// <id> dmac_lvl_1 -#ifndef CONF_DMAC_LVL_1 -#define CONF_DMAC_LVL_1 0 -#endif - -// <q> Channel Event Output -// <i> Indicates whether channel event generation is enabled or not -// <id> dmac_evoe_1 -#ifndef CONF_DMAC_EVOE_1 -#define CONF_DMAC_EVOE_1 0 -#endif - -// <q> Channel Event Input -// <i> Indicates whether channel event reception is enabled or not -// <id> dmac_evie_1 -#ifndef CONF_DMAC_EVIE_1 -#define CONF_DMAC_EVIE_1 0 -#endif - -// <o> Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// <i> Defines the event input action -// <id> dmac_evact_1 -#ifndef CONF_DMAC_EVACT_1 -#define CONF_DMAC_EVACT_1 0 -#endif - -// <o> Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// <i> Defines the address increment step size, applies to source or destination address -// <id> dmac_stepsize_1 -#ifndef CONF_DMAC_STEPSIZE_1 -#define CONF_DMAC_STEPSIZE_1 0 -#endif - -// <o> Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// <i> Defines whether source or destination addresses are using the step size settings -// <id> dmac_stepsel_1 -#ifndef CONF_DMAC_STEPSEL_1 -#define CONF_DMAC_STEPSEL_1 0 -#endif - -// <q> Source Address Increment -// <i> Indicates whether the source address incrementation is enabled or not -// <id> dmac_srcinc_1 -#ifndef CONF_DMAC_SRCINC_1 -#define CONF_DMAC_SRCINC_1 0 -#endif - -// <q> Destination Address Increment -// <i> Indicates whether the destination address incrementation is enabled or not -// <id> dmac_dstinc_1 -#ifndef CONF_DMAC_DSTINC_1 -#define CONF_DMAC_DSTINC_1 0 -#endif - -// <o> Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// <i> Defines the size of one beat -// <id> dmac_beatsize_1 -#ifndef CONF_DMAC_BEATSIZE_1 -#define CONF_DMAC_BEATSIZE_1 0 -#endif - -// <o> Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// <i> Defines the the DMAC should take after a block transfer has completed -// <id> dmac_blockact_1 -#ifndef CONF_DMAC_BLOCKACT_1 -#define CONF_DMAC_BLOCKACT_1 0 -#endif - -// <o> Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// <i> Defines the event output selection -// <id> dmac_evosel_1 -#ifndef CONF_DMAC_EVOSEL_1 -#define CONF_DMAC_EVOSEL_1 0 -#endif -// </e> - -// <e> Channel 2 settings -// <id> dmac_channel_2_settings -#ifndef CONF_DMAC_CHANNEL_2_SETTINGS -#define CONF_DMAC_CHANNEL_2_SETTINGS 0 -#endif - -// <q> Channel Enable -// <i> Indicates whether channel 2 is enabled or not -// <id> dmac_enable_2 -#ifndef CONF_DMAC_ENABLE_2 -#define CONF_DMAC_ENABLE_2 0 -#endif - -// <q> Channel Run in Standby -// <i> Indicates whether channel 2 is running in standby mode or not -// <id> dmac_runstdby_2 -#ifndef CONF_DMAC_RUNSTDBY_2 -#define CONF_DMAC_RUNSTDBY_2 0 -#endif - -// <o> Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// <i> Defines the trigger action used for a transfer -// <id> dmac_trigact_2 -#ifndef CONF_DMAC_TRIGACT_2 -#define CONF_DMAC_TRIGACT_2 0 -#endif - -// <o> Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Timestamp -// <0x02=> SERCOM0 RX Trigger -// <0x03=> SERCOM0 TX Trigger -// <0x04=> SERCOM1 RX Trigger -// <0x05=> SERCOM1 TX Trigger -// <0x06=> SERCOM2 RX Trigger -// <0x07=> SERCOM2 TX Trigger -// <0x08=> SERCOM3 RX Trigger -// <0x09=> SERCOM3 TX Trigger -// <0x0A=> SERCOM4 RX Trigger -// <0x0B=> SERCOM4 TX Trigger -// <0x0C=> SERCOM5 RX Trigger -// <0x0D=> SERCOM5 TX Trigger -// <0x0E=> TCC0 Overflow Trigger -// <0x0F=> TCC0 Match/Compare 0 Trigger -// <0x10=> TCC0 Match/Compare 1 Trigger -// <0x11=> TCC0 Match/Compare 2 Trigger -// <0x12=> TCC0 Match/Compare 3 Trigger -// <0x13=> TC0 Overflow Trigger -// <0x14=> TC0 Match/Compare 0 Trigger -// <0x15=> TC0 Match/Compare 1 Trigger -// <0x16=> TC1 Overflow Trigger -// <0x17=> TC1 Match/Compare 0 Trigger -// <0x18=> TC1 Match/Compare 1 Trigger -// <0x19=> TC2 Overflow Trigger -// <0x1A=> TC2 Match/Compare 0 Trigger -// <0x1B=> TC2 Match/Compare 1 Trigger -// <0x1C=> TC3 Overflow Trigger -// <0x1D=> TC3 Match/Compare 0 Trigger -// <0x1E=> TC3 Match/Compare 1 Trigger -// <0x1F=> ADC Result Ready Trigger -// <0x20=> SLCD Display Memory Update Trigger -// <0x21=> SLCD Automated Character Mapping Data Ready Trigger -// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger -// <0x23=> AES Write Trigger -// <0x24=> AES Read Trigger -// <0x25=> PTC End of Conversion Trigger -// <0x26=> PTC Sequence Trigger -// <0x27=> PTC Window Comparator Trigger -// <i> Defines the peripheral trigger which is source of the transfer -// <id> dmac_trifsrc_2 -#ifndef CONF_DMAC_TRIGSRC_2 -#define CONF_DMAC_TRIGSRC_2 0 -#endif - -// <o> Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// <i> Defines the arbitration level for this channel -// <id> dmac_lvl_2 -#ifndef CONF_DMAC_LVL_2 -#define CONF_DMAC_LVL_2 0 -#endif - -// <q> Channel Event Output -// <i> Indicates whether channel event generation is enabled or not -// <id> dmac_evoe_2 -#ifndef CONF_DMAC_EVOE_2 -#define CONF_DMAC_EVOE_2 0 -#endif - -// <q> Channel Event Input -// <i> Indicates whether channel event reception is enabled or not -// <id> dmac_evie_2 -#ifndef CONF_DMAC_EVIE_2 -#define CONF_DMAC_EVIE_2 0 -#endif - -// <o> Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// <i> Defines the event input action -// <id> dmac_evact_2 -#ifndef CONF_DMAC_EVACT_2 -#define CONF_DMAC_EVACT_2 0 -#endif - -// <o> Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// <i> Defines the address increment step size, applies to source or destination address -// <id> dmac_stepsize_2 -#ifndef CONF_DMAC_STEPSIZE_2 -#define CONF_DMAC_STEPSIZE_2 0 -#endif - -// <o> Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// <i> Defines whether source or destination addresses are using the step size settings -// <id> dmac_stepsel_2 -#ifndef CONF_DMAC_STEPSEL_2 -#define CONF_DMAC_STEPSEL_2 0 -#endif - -// <q> Source Address Increment -// <i> Indicates whether the source address incrementation is enabled or not -// <id> dmac_srcinc_2 -#ifndef CONF_DMAC_SRCINC_2 -#define CONF_DMAC_SRCINC_2 0 -#endif - -// <q> Destination Address Increment -// <i> Indicates whether the destination address incrementation is enabled or not -// <id> dmac_dstinc_2 -#ifndef CONF_DMAC_DSTINC_2 -#define CONF_DMAC_DSTINC_2 0 -#endif - -// <o> Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// <i> Defines the size of one beat -// <id> dmac_beatsize_2 -#ifndef CONF_DMAC_BEATSIZE_2 -#define CONF_DMAC_BEATSIZE_2 0 -#endif - -// <o> Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// <i> Defines the the DMAC should take after a block transfer has completed -// <id> dmac_blockact_2 -#ifndef CONF_DMAC_BLOCKACT_2 -#define CONF_DMAC_BLOCKACT_2 0 -#endif - -// <o> Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// <i> Defines the event output selection -// <id> dmac_evosel_2 -#ifndef CONF_DMAC_EVOSEL_2 -#define CONF_DMAC_EVOSEL_2 0 -#endif -// </e> - -// <e> Channel 3 settings -// <id> dmac_channel_3_settings -#ifndef CONF_DMAC_CHANNEL_3_SETTINGS -#define CONF_DMAC_CHANNEL_3_SETTINGS 0 -#endif - -// <q> Channel Enable -// <i> Indicates whether channel 3 is enabled or not -// <id> dmac_enable_3 -#ifndef CONF_DMAC_ENABLE_3 -#define CONF_DMAC_ENABLE_3 0 -#endif - -// <q> Channel Run in Standby -// <i> Indicates whether channel 3 is running in standby mode or not -// <id> dmac_runstdby_3 -#ifndef CONF_DMAC_RUNSTDBY_3 -#define CONF_DMAC_RUNSTDBY_3 0 -#endif - -// <o> Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// <i> Defines the trigger action used for a transfer -// <id> dmac_trigact_3 -#ifndef CONF_DMAC_TRIGACT_3 -#define CONF_DMAC_TRIGACT_3 0 -#endif - -// <o> Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Timestamp -// <0x02=> SERCOM0 RX Trigger -// <0x03=> SERCOM0 TX Trigger -// <0x04=> SERCOM1 RX Trigger -// <0x05=> SERCOM1 TX Trigger -// <0x06=> SERCOM2 RX Trigger -// <0x07=> SERCOM2 TX Trigger -// <0x08=> SERCOM3 RX Trigger -// <0x09=> SERCOM3 TX Trigger -// <0x0A=> SERCOM4 RX Trigger -// <0x0B=> SERCOM4 TX Trigger -// <0x0C=> SERCOM5 RX Trigger -// <0x0D=> SERCOM5 TX Trigger -// <0x0E=> TCC0 Overflow Trigger -// <0x0F=> TCC0 Match/Compare 0 Trigger -// <0x10=> TCC0 Match/Compare 1 Trigger -// <0x11=> TCC0 Match/Compare 2 Trigger -// <0x12=> TCC0 Match/Compare 3 Trigger -// <0x13=> TC0 Overflow Trigger -// <0x14=> TC0 Match/Compare 0 Trigger -// <0x15=> TC0 Match/Compare 1 Trigger -// <0x16=> TC1 Overflow Trigger -// <0x17=> TC1 Match/Compare 0 Trigger -// <0x18=> TC1 Match/Compare 1 Trigger -// <0x19=> TC2 Overflow Trigger -// <0x1A=> TC2 Match/Compare 0 Trigger -// <0x1B=> TC2 Match/Compare 1 Trigger -// <0x1C=> TC3 Overflow Trigger -// <0x1D=> TC3 Match/Compare 0 Trigger -// <0x1E=> TC3 Match/Compare 1 Trigger -// <0x1F=> ADC Result Ready Trigger -// <0x20=> SLCD Display Memory Update Trigger -// <0x21=> SLCD Automated Character Mapping Data Ready Trigger -// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger -// <0x23=> AES Write Trigger -// <0x24=> AES Read Trigger -// <0x25=> PTC End of Conversion Trigger -// <0x26=> PTC Sequence Trigger -// <0x27=> PTC Window Comparator Trigger -// <i> Defines the peripheral trigger which is source of the transfer -// <id> dmac_trifsrc_3 -#ifndef CONF_DMAC_TRIGSRC_3 -#define CONF_DMAC_TRIGSRC_3 0 -#endif - -// <o> Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// <i> Defines the arbitration level for this channel -// <id> dmac_lvl_3 -#ifndef CONF_DMAC_LVL_3 -#define CONF_DMAC_LVL_3 0 -#endif - -// <q> Channel Event Output -// <i> Indicates whether channel event generation is enabled or not -// <id> dmac_evoe_3 -#ifndef CONF_DMAC_EVOE_3 -#define CONF_DMAC_EVOE_3 0 -#endif - -// <q> Channel Event Input -// <i> Indicates whether channel event reception is enabled or not -// <id> dmac_evie_3 -#ifndef CONF_DMAC_EVIE_3 -#define CONF_DMAC_EVIE_3 0 -#endif - -// <o> Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// <i> Defines the event input action -// <id> dmac_evact_3 -#ifndef CONF_DMAC_EVACT_3 -#define CONF_DMAC_EVACT_3 0 -#endif - -// <o> Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// <i> Defines the address increment step size, applies to source or destination address -// <id> dmac_stepsize_3 -#ifndef CONF_DMAC_STEPSIZE_3 -#define CONF_DMAC_STEPSIZE_3 0 -#endif - -// <o> Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// <i> Defines whether source or destination addresses are using the step size settings -// <id> dmac_stepsel_3 -#ifndef CONF_DMAC_STEPSEL_3 -#define CONF_DMAC_STEPSEL_3 0 -#endif - -// <q> Source Address Increment -// <i> Indicates whether the source address incrementation is enabled or not -// <id> dmac_srcinc_3 -#ifndef CONF_DMAC_SRCINC_3 -#define CONF_DMAC_SRCINC_3 0 -#endif - -// <q> Destination Address Increment -// <i> Indicates whether the destination address incrementation is enabled or not -// <id> dmac_dstinc_3 -#ifndef CONF_DMAC_DSTINC_3 -#define CONF_DMAC_DSTINC_3 0 -#endif - -// <o> Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// <i> Defines the size of one beat -// <id> dmac_beatsize_3 -#ifndef CONF_DMAC_BEATSIZE_3 -#define CONF_DMAC_BEATSIZE_3 0 -#endif - -// <o> Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// <i> Defines the the DMAC should take after a block transfer has completed -// <id> dmac_blockact_3 -#ifndef CONF_DMAC_BLOCKACT_3 -#define CONF_DMAC_BLOCKACT_3 0 -#endif - -// <o> Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// <i> Defines the event output selection -// <id> dmac_evosel_3 -#ifndef CONF_DMAC_EVOSEL_3 -#define CONF_DMAC_EVOSEL_3 0 -#endif -// </e> - -// <e> Channel 4 settings -// <id> dmac_channel_4_settings -#ifndef CONF_DMAC_CHANNEL_4_SETTINGS -#define CONF_DMAC_CHANNEL_4_SETTINGS 0 -#endif - -// <q> Channel Enable -// <i> Indicates whether channel 4 is enabled or not -// <id> dmac_enable_4 -#ifndef CONF_DMAC_ENABLE_4 -#define CONF_DMAC_ENABLE_4 0 -#endif - -// <q> Channel Run in Standby -// <i> Indicates whether channel 4 is running in standby mode or not -// <id> dmac_runstdby_4 -#ifndef CONF_DMAC_RUNSTDBY_4 -#define CONF_DMAC_RUNSTDBY_4 0 -#endif - -// <o> Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// <i> Defines the trigger action used for a transfer -// <id> dmac_trigact_4 -#ifndef CONF_DMAC_TRIGACT_4 -#define CONF_DMAC_TRIGACT_4 0 -#endif - -// <o> Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Timestamp -// <0x02=> SERCOM0 RX Trigger -// <0x03=> SERCOM0 TX Trigger -// <0x04=> SERCOM1 RX Trigger -// <0x05=> SERCOM1 TX Trigger -// <0x06=> SERCOM2 RX Trigger -// <0x07=> SERCOM2 TX Trigger -// <0x08=> SERCOM3 RX Trigger -// <0x09=> SERCOM3 TX Trigger -// <0x0A=> SERCOM4 RX Trigger -// <0x0B=> SERCOM4 TX Trigger -// <0x0C=> SERCOM5 RX Trigger -// <0x0D=> SERCOM5 TX Trigger -// <0x0E=> TCC0 Overflow Trigger -// <0x0F=> TCC0 Match/Compare 0 Trigger -// <0x10=> TCC0 Match/Compare 1 Trigger -// <0x11=> TCC0 Match/Compare 2 Trigger -// <0x12=> TCC0 Match/Compare 3 Trigger -// <0x13=> TC0 Overflow Trigger -// <0x14=> TC0 Match/Compare 0 Trigger -// <0x15=> TC0 Match/Compare 1 Trigger -// <0x16=> TC1 Overflow Trigger -// <0x17=> TC1 Match/Compare 0 Trigger -// <0x18=> TC1 Match/Compare 1 Trigger -// <0x19=> TC2 Overflow Trigger -// <0x1A=> TC2 Match/Compare 0 Trigger -// <0x1B=> TC2 Match/Compare 1 Trigger -// <0x1C=> TC3 Overflow Trigger -// <0x1D=> TC3 Match/Compare 0 Trigger -// <0x1E=> TC3 Match/Compare 1 Trigger -// <0x1F=> ADC Result Ready Trigger -// <0x20=> SLCD Display Memory Update Trigger -// <0x21=> SLCD Automated Character Mapping Data Ready Trigger -// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger -// <0x23=> AES Write Trigger -// <0x24=> AES Read Trigger -// <0x25=> PTC End of Conversion Trigger -// <0x26=> PTC Sequence Trigger -// <0x27=> PTC Window Comparator Trigger -// <i> Defines the peripheral trigger which is source of the transfer -// <id> dmac_trifsrc_4 -#ifndef CONF_DMAC_TRIGSRC_4 -#define CONF_DMAC_TRIGSRC_4 0 -#endif - -// <o> Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// <i> Defines the arbitration level for this channel -// <id> dmac_lvl_4 -#ifndef CONF_DMAC_LVL_4 -#define CONF_DMAC_LVL_4 0 -#endif - -// <q> Channel Event Output -// <i> Indicates whether channel event generation is enabled or not -// <id> dmac_evoe_4 -#ifndef CONF_DMAC_EVOE_4 -#define CONF_DMAC_EVOE_4 0 -#endif - -// <q> Channel Event Input -// <i> Indicates whether channel event reception is enabled or not -// <id> dmac_evie_4 -#ifndef CONF_DMAC_EVIE_4 -#define CONF_DMAC_EVIE_4 0 -#endif - -// <o> Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// <i> Defines the event input action -// <id> dmac_evact_4 -#ifndef CONF_DMAC_EVACT_4 -#define CONF_DMAC_EVACT_4 0 -#endif - -// <o> Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// <i> Defines the address increment step size, applies to source or destination address -// <id> dmac_stepsize_4 -#ifndef CONF_DMAC_STEPSIZE_4 -#define CONF_DMAC_STEPSIZE_4 0 -#endif - -// <o> Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// <i> Defines whether source or destination addresses are using the step size settings -// <id> dmac_stepsel_4 -#ifndef CONF_DMAC_STEPSEL_4 -#define CONF_DMAC_STEPSEL_4 0 -#endif - -// <q> Source Address Increment -// <i> Indicates whether the source address incrementation is enabled or not -// <id> dmac_srcinc_4 -#ifndef CONF_DMAC_SRCINC_4 -#define CONF_DMAC_SRCINC_4 0 -#endif - -// <q> Destination Address Increment -// <i> Indicates whether the destination address incrementation is enabled or not -// <id> dmac_dstinc_4 -#ifndef CONF_DMAC_DSTINC_4 -#define CONF_DMAC_DSTINC_4 0 -#endif - -// <o> Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// <i> Defines the size of one beat -// <id> dmac_beatsize_4 -#ifndef CONF_DMAC_BEATSIZE_4 -#define CONF_DMAC_BEATSIZE_4 0 -#endif - -// <o> Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// <i> Defines the the DMAC should take after a block transfer has completed -// <id> dmac_blockact_4 -#ifndef CONF_DMAC_BLOCKACT_4 -#define CONF_DMAC_BLOCKACT_4 0 -#endif - -// <o> Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// <i> Defines the event output selection -// <id> dmac_evosel_4 -#ifndef CONF_DMAC_EVOSEL_4 -#define CONF_DMAC_EVOSEL_4 0 -#endif -// </e> - -// <e> Channel 5 settings -// <id> dmac_channel_5_settings -#ifndef CONF_DMAC_CHANNEL_5_SETTINGS -#define CONF_DMAC_CHANNEL_5_SETTINGS 0 -#endif - -// <q> Channel Enable -// <i> Indicates whether channel 5 is enabled or not -// <id> dmac_enable_5 -#ifndef CONF_DMAC_ENABLE_5 -#define CONF_DMAC_ENABLE_5 0 -#endif - -// <q> Channel Run in Standby -// <i> Indicates whether channel 5 is running in standby mode or not -// <id> dmac_runstdby_5 -#ifndef CONF_DMAC_RUNSTDBY_5 -#define CONF_DMAC_RUNSTDBY_5 0 -#endif - -// <o> Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// <i> Defines the trigger action used for a transfer -// <id> dmac_trigact_5 -#ifndef CONF_DMAC_TRIGACT_5 -#define CONF_DMAC_TRIGACT_5 0 -#endif - -// <o> Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Timestamp -// <0x02=> SERCOM0 RX Trigger -// <0x03=> SERCOM0 TX Trigger -// <0x04=> SERCOM1 RX Trigger -// <0x05=> SERCOM1 TX Trigger -// <0x06=> SERCOM2 RX Trigger -// <0x07=> SERCOM2 TX Trigger -// <0x08=> SERCOM3 RX Trigger -// <0x09=> SERCOM3 TX Trigger -// <0x0A=> SERCOM4 RX Trigger -// <0x0B=> SERCOM4 TX Trigger -// <0x0C=> SERCOM5 RX Trigger -// <0x0D=> SERCOM5 TX Trigger -// <0x0E=> TCC0 Overflow Trigger -// <0x0F=> TCC0 Match/Compare 0 Trigger -// <0x10=> TCC0 Match/Compare 1 Trigger -// <0x11=> TCC0 Match/Compare 2 Trigger -// <0x12=> TCC0 Match/Compare 3 Trigger -// <0x13=> TC0 Overflow Trigger -// <0x14=> TC0 Match/Compare 0 Trigger -// <0x15=> TC0 Match/Compare 1 Trigger -// <0x16=> TC1 Overflow Trigger -// <0x17=> TC1 Match/Compare 0 Trigger -// <0x18=> TC1 Match/Compare 1 Trigger -// <0x19=> TC2 Overflow Trigger -// <0x1A=> TC2 Match/Compare 0 Trigger -// <0x1B=> TC2 Match/Compare 1 Trigger -// <0x1C=> TC3 Overflow Trigger -// <0x1D=> TC3 Match/Compare 0 Trigger -// <0x1E=> TC3 Match/Compare 1 Trigger -// <0x1F=> ADC Result Ready Trigger -// <0x20=> SLCD Display Memory Update Trigger -// <0x21=> SLCD Automated Character Mapping Data Ready Trigger -// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger -// <0x23=> AES Write Trigger -// <0x24=> AES Read Trigger -// <0x25=> PTC End of Conversion Trigger -// <0x26=> PTC Sequence Trigger -// <0x27=> PTC Window Comparator Trigger -// <i> Defines the peripheral trigger which is source of the transfer -// <id> dmac_trifsrc_5 -#ifndef CONF_DMAC_TRIGSRC_5 -#define CONF_DMAC_TRIGSRC_5 0 -#endif - -// <o> Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// <i> Defines the arbitration level for this channel -// <id> dmac_lvl_5 -#ifndef CONF_DMAC_LVL_5 -#define CONF_DMAC_LVL_5 0 -#endif - -// <q> Channel Event Output -// <i> Indicates whether channel event generation is enabled or not -// <id> dmac_evoe_5 -#ifndef CONF_DMAC_EVOE_5 -#define CONF_DMAC_EVOE_5 0 -#endif - -// <q> Channel Event Input -// <i> Indicates whether channel event reception is enabled or not -// <id> dmac_evie_5 -#ifndef CONF_DMAC_EVIE_5 -#define CONF_DMAC_EVIE_5 0 -#endif - -// <o> Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// <i> Defines the event input action -// <id> dmac_evact_5 -#ifndef CONF_DMAC_EVACT_5 -#define CONF_DMAC_EVACT_5 0 -#endif - -// <o> Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// <i> Defines the address increment step size, applies to source or destination address -// <id> dmac_stepsize_5 -#ifndef CONF_DMAC_STEPSIZE_5 -#define CONF_DMAC_STEPSIZE_5 0 -#endif - -// <o> Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// <i> Defines whether source or destination addresses are using the step size settings -// <id> dmac_stepsel_5 -#ifndef CONF_DMAC_STEPSEL_5 -#define CONF_DMAC_STEPSEL_5 0 -#endif - -// <q> Source Address Increment -// <i> Indicates whether the source address incrementation is enabled or not -// <id> dmac_srcinc_5 -#ifndef CONF_DMAC_SRCINC_5 -#define CONF_DMAC_SRCINC_5 0 -#endif - -// <q> Destination Address Increment -// <i> Indicates whether the destination address incrementation is enabled or not -// <id> dmac_dstinc_5 -#ifndef CONF_DMAC_DSTINC_5 -#define CONF_DMAC_DSTINC_5 0 -#endif - -// <o> Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// <i> Defines the size of one beat -// <id> dmac_beatsize_5 -#ifndef CONF_DMAC_BEATSIZE_5 -#define CONF_DMAC_BEATSIZE_5 0 -#endif - -// <o> Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// <i> Defines the the DMAC should take after a block transfer has completed -// <id> dmac_blockact_5 -#ifndef CONF_DMAC_BLOCKACT_5 -#define CONF_DMAC_BLOCKACT_5 0 -#endif - -// <o> Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// <i> Defines the event output selection -// <id> dmac_evosel_5 -#ifndef CONF_DMAC_EVOSEL_5 -#define CONF_DMAC_EVOSEL_5 0 -#endif -// </e> - -// <e> Channel 6 settings -// <id> dmac_channel_6_settings -#ifndef CONF_DMAC_CHANNEL_6_SETTINGS -#define CONF_DMAC_CHANNEL_6_SETTINGS 0 -#endif - -// <q> Channel Enable -// <i> Indicates whether channel 6 is enabled or not -// <id> dmac_enable_6 -#ifndef CONF_DMAC_ENABLE_6 -#define CONF_DMAC_ENABLE_6 0 -#endif - -// <q> Channel Run in Standby -// <i> Indicates whether channel 6 is running in standby mode or not -// <id> dmac_runstdby_6 -#ifndef CONF_DMAC_RUNSTDBY_6 -#define CONF_DMAC_RUNSTDBY_6 0 -#endif - -// <o> Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// <i> Defines the trigger action used for a transfer -// <id> dmac_trigact_6 -#ifndef CONF_DMAC_TRIGACT_6 -#define CONF_DMAC_TRIGACT_6 0 -#endif - -// <o> Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Timestamp -// <0x02=> SERCOM0 RX Trigger -// <0x03=> SERCOM0 TX Trigger -// <0x04=> SERCOM1 RX Trigger -// <0x05=> SERCOM1 TX Trigger -// <0x06=> SERCOM2 RX Trigger -// <0x07=> SERCOM2 TX Trigger -// <0x08=> SERCOM3 RX Trigger -// <0x09=> SERCOM3 TX Trigger -// <0x0A=> SERCOM4 RX Trigger -// <0x0B=> SERCOM4 TX Trigger -// <0x0C=> SERCOM5 RX Trigger -// <0x0D=> SERCOM5 TX Trigger -// <0x0E=> TCC0 Overflow Trigger -// <0x0F=> TCC0 Match/Compare 0 Trigger -// <0x10=> TCC0 Match/Compare 1 Trigger -// <0x11=> TCC0 Match/Compare 2 Trigger -// <0x12=> TCC0 Match/Compare 3 Trigger -// <0x13=> TC0 Overflow Trigger -// <0x14=> TC0 Match/Compare 0 Trigger -// <0x15=> TC0 Match/Compare 1 Trigger -// <0x16=> TC1 Overflow Trigger -// <0x17=> TC1 Match/Compare 0 Trigger -// <0x18=> TC1 Match/Compare 1 Trigger -// <0x19=> TC2 Overflow Trigger -// <0x1A=> TC2 Match/Compare 0 Trigger -// <0x1B=> TC2 Match/Compare 1 Trigger -// <0x1C=> TC3 Overflow Trigger -// <0x1D=> TC3 Match/Compare 0 Trigger -// <0x1E=> TC3 Match/Compare 1 Trigger -// <0x1F=> ADC Result Ready Trigger -// <0x20=> SLCD Display Memory Update Trigger -// <0x21=> SLCD Automated Character Mapping Data Ready Trigger -// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger -// <0x23=> AES Write Trigger -// <0x24=> AES Read Trigger -// <0x25=> PTC End of Conversion Trigger -// <0x26=> PTC Sequence Trigger -// <0x27=> PTC Window Comparator Trigger -// <i> Defines the peripheral trigger which is source of the transfer -// <id> dmac_trifsrc_6 -#ifndef CONF_DMAC_TRIGSRC_6 -#define CONF_DMAC_TRIGSRC_6 0 -#endif - -// <o> Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// <i> Defines the arbitration level for this channel -// <id> dmac_lvl_6 -#ifndef CONF_DMAC_LVL_6 -#define CONF_DMAC_LVL_6 0 -#endif - -// <q> Channel Event Output -// <i> Indicates whether channel event generation is enabled or not -// <id> dmac_evoe_6 -#ifndef CONF_DMAC_EVOE_6 -#define CONF_DMAC_EVOE_6 0 -#endif - -// <q> Channel Event Input -// <i> Indicates whether channel event reception is enabled or not -// <id> dmac_evie_6 -#ifndef CONF_DMAC_EVIE_6 -#define CONF_DMAC_EVIE_6 0 -#endif - -// <o> Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// <i> Defines the event input action -// <id> dmac_evact_6 -#ifndef CONF_DMAC_EVACT_6 -#define CONF_DMAC_EVACT_6 0 -#endif - -// <o> Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// <i> Defines the address increment step size, applies to source or destination address -// <id> dmac_stepsize_6 -#ifndef CONF_DMAC_STEPSIZE_6 -#define CONF_DMAC_STEPSIZE_6 0 -#endif - -// <o> Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// <i> Defines whether source or destination addresses are using the step size settings -// <id> dmac_stepsel_6 -#ifndef CONF_DMAC_STEPSEL_6 -#define CONF_DMAC_STEPSEL_6 0 -#endif - -// <q> Source Address Increment -// <i> Indicates whether the source address incrementation is enabled or not -// <id> dmac_srcinc_6 -#ifndef CONF_DMAC_SRCINC_6 -#define CONF_DMAC_SRCINC_6 0 -#endif - -// <q> Destination Address Increment -// <i> Indicates whether the destination address incrementation is enabled or not -// <id> dmac_dstinc_6 -#ifndef CONF_DMAC_DSTINC_6 -#define CONF_DMAC_DSTINC_6 0 -#endif - -// <o> Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// <i> Defines the size of one beat -// <id> dmac_beatsize_6 -#ifndef CONF_DMAC_BEATSIZE_6 -#define CONF_DMAC_BEATSIZE_6 0 -#endif - -// <o> Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// <i> Defines the the DMAC should take after a block transfer has completed -// <id> dmac_blockact_6 -#ifndef CONF_DMAC_BLOCKACT_6 -#define CONF_DMAC_BLOCKACT_6 0 -#endif - -// <o> Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// <i> Defines the event output selection -// <id> dmac_evosel_6 -#ifndef CONF_DMAC_EVOSEL_6 -#define CONF_DMAC_EVOSEL_6 0 -#endif -// </e> - -// <e> Channel 7 settings -// <id> dmac_channel_7_settings -#ifndef CONF_DMAC_CHANNEL_7_SETTINGS -#define CONF_DMAC_CHANNEL_7_SETTINGS 0 -#endif - -// <q> Channel Enable -// <i> Indicates whether channel 7 is enabled or not -// <id> dmac_enable_7 -#ifndef CONF_DMAC_ENABLE_7 -#define CONF_DMAC_ENABLE_7 0 -#endif - -// <q> Channel Run in Standby -// <i> Indicates whether channel 7 is running in standby mode or not -// <id> dmac_runstdby_7 -#ifndef CONF_DMAC_RUNSTDBY_7 -#define CONF_DMAC_RUNSTDBY_7 0 -#endif - -// <o> Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// <i> Defines the trigger action used for a transfer -// <id> dmac_trigact_7 -#ifndef CONF_DMAC_TRIGACT_7 -#define CONF_DMAC_TRIGACT_7 0 -#endif - -// <o> Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Timestamp -// <0x02=> SERCOM0 RX Trigger -// <0x03=> SERCOM0 TX Trigger -// <0x04=> SERCOM1 RX Trigger -// <0x05=> SERCOM1 TX Trigger -// <0x06=> SERCOM2 RX Trigger -// <0x07=> SERCOM2 TX Trigger -// <0x08=> SERCOM3 RX Trigger -// <0x09=> SERCOM3 TX Trigger -// <0x0A=> SERCOM4 RX Trigger -// <0x0B=> SERCOM4 TX Trigger -// <0x0C=> SERCOM5 RX Trigger -// <0x0D=> SERCOM5 TX Trigger -// <0x0E=> TCC0 Overflow Trigger -// <0x0F=> TCC0 Match/Compare 0 Trigger -// <0x10=> TCC0 Match/Compare 1 Trigger -// <0x11=> TCC0 Match/Compare 2 Trigger -// <0x12=> TCC0 Match/Compare 3 Trigger -// <0x13=> TC0 Overflow Trigger -// <0x14=> TC0 Match/Compare 0 Trigger -// <0x15=> TC0 Match/Compare 1 Trigger -// <0x16=> TC1 Overflow Trigger -// <0x17=> TC1 Match/Compare 0 Trigger -// <0x18=> TC1 Match/Compare 1 Trigger -// <0x19=> TC2 Overflow Trigger -// <0x1A=> TC2 Match/Compare 0 Trigger -// <0x1B=> TC2 Match/Compare 1 Trigger -// <0x1C=> TC3 Overflow Trigger -// <0x1D=> TC3 Match/Compare 0 Trigger -// <0x1E=> TC3 Match/Compare 1 Trigger -// <0x1F=> ADC Result Ready Trigger -// <0x20=> SLCD Display Memory Update Trigger -// <0x21=> SLCD Automated Character Mapping Data Ready Trigger -// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger -// <0x23=> AES Write Trigger -// <0x24=> AES Read Trigger -// <0x25=> PTC End of Conversion Trigger -// <0x26=> PTC Sequence Trigger -// <0x27=> PTC Window Comparator Trigger -// <i> Defines the peripheral trigger which is source of the transfer -// <id> dmac_trifsrc_7 -#ifndef CONF_DMAC_TRIGSRC_7 -#define CONF_DMAC_TRIGSRC_7 0 -#endif - -// <o> Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// <i> Defines the arbitration level for this channel -// <id> dmac_lvl_7 -#ifndef CONF_DMAC_LVL_7 -#define CONF_DMAC_LVL_7 0 -#endif - -// <q> Channel Event Output -// <i> Indicates whether channel event generation is enabled or not -// <id> dmac_evoe_7 -#ifndef CONF_DMAC_EVOE_7 -#define CONF_DMAC_EVOE_7 0 -#endif - -// <q> Channel Event Input -// <i> Indicates whether channel event reception is enabled or not -// <id> dmac_evie_7 -#ifndef CONF_DMAC_EVIE_7 -#define CONF_DMAC_EVIE_7 0 -#endif - -// <o> Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// <i> Defines the event input action -// <id> dmac_evact_7 -#ifndef CONF_DMAC_EVACT_7 -#define CONF_DMAC_EVACT_7 0 -#endif - -// <o> Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// <i> Defines the address increment step size, applies to source or destination address -// <id> dmac_stepsize_7 -#ifndef CONF_DMAC_STEPSIZE_7 -#define CONF_DMAC_STEPSIZE_7 0 -#endif - -// <o> Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// <i> Defines whether source or destination addresses are using the step size settings -// <id> dmac_stepsel_7 -#ifndef CONF_DMAC_STEPSEL_7 -#define CONF_DMAC_STEPSEL_7 0 -#endif - -// <q> Source Address Increment -// <i> Indicates whether the source address incrementation is enabled or not -// <id> dmac_srcinc_7 -#ifndef CONF_DMAC_SRCINC_7 -#define CONF_DMAC_SRCINC_7 0 -#endif - -// <q> Destination Address Increment -// <i> Indicates whether the destination address incrementation is enabled or not -// <id> dmac_dstinc_7 -#ifndef CONF_DMAC_DSTINC_7 -#define CONF_DMAC_DSTINC_7 0 -#endif - -// <o> Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// <i> Defines the size of one beat -// <id> dmac_beatsize_7 -#ifndef CONF_DMAC_BEATSIZE_7 -#define CONF_DMAC_BEATSIZE_7 0 -#endif - -// <o> Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// <i> Defines the the DMAC should take after a block transfer has completed -// <id> dmac_blockact_7 -#ifndef CONF_DMAC_BLOCKACT_7 -#define CONF_DMAC_BLOCKACT_7 0 -#endif - -// <o> Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// <i> Defines the event output selection -// <id> dmac_evosel_7 -#ifndef CONF_DMAC_EVOSEL_7 -#define CONF_DMAC_EVOSEL_7 0 -#endif -// </e> - -// <e> Channel 8 settings -// <id> dmac_channel_8_settings -#ifndef CONF_DMAC_CHANNEL_8_SETTINGS -#define CONF_DMAC_CHANNEL_8_SETTINGS 0 -#endif - -// <q> Channel Enable -// <i> Indicates whether channel 8 is enabled or not -// <id> dmac_enable_8 -#ifndef CONF_DMAC_ENABLE_8 -#define CONF_DMAC_ENABLE_8 0 -#endif - -// <q> Channel Run in Standby -// <i> Indicates whether channel 8 is running in standby mode or not -// <id> dmac_runstdby_8 -#ifndef CONF_DMAC_RUNSTDBY_8 -#define CONF_DMAC_RUNSTDBY_8 0 -#endif - -// <o> Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// <i> Defines the trigger action used for a transfer -// <id> dmac_trigact_8 -#ifndef CONF_DMAC_TRIGACT_8 -#define CONF_DMAC_TRIGACT_8 0 -#endif - -// <o> Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Timestamp -// <0x02=> SERCOM0 RX Trigger -// <0x03=> SERCOM0 TX Trigger -// <0x04=> SERCOM1 RX Trigger -// <0x05=> SERCOM1 TX Trigger -// <0x06=> SERCOM2 RX Trigger -// <0x07=> SERCOM2 TX Trigger -// <0x08=> SERCOM3 RX Trigger -// <0x09=> SERCOM3 TX Trigger -// <0x0A=> SERCOM4 RX Trigger -// <0x0B=> SERCOM4 TX Trigger -// <0x0C=> SERCOM5 RX Trigger -// <0x0D=> SERCOM5 TX Trigger -// <0x0E=> TCC0 Overflow Trigger -// <0x0F=> TCC0 Match/Compare 0 Trigger -// <0x10=> TCC0 Match/Compare 1 Trigger -// <0x11=> TCC0 Match/Compare 2 Trigger -// <0x12=> TCC0 Match/Compare 3 Trigger -// <0x13=> TC0 Overflow Trigger -// <0x14=> TC0 Match/Compare 0 Trigger -// <0x15=> TC0 Match/Compare 1 Trigger -// <0x16=> TC1 Overflow Trigger -// <0x17=> TC1 Match/Compare 0 Trigger -// <0x18=> TC1 Match/Compare 1 Trigger -// <0x19=> TC2 Overflow Trigger -// <0x1A=> TC2 Match/Compare 0 Trigger -// <0x1B=> TC2 Match/Compare 1 Trigger -// <0x1C=> TC3 Overflow Trigger -// <0x1D=> TC3 Match/Compare 0 Trigger -// <0x1E=> TC3 Match/Compare 1 Trigger -// <0x1F=> ADC Result Ready Trigger -// <0x20=> SLCD Display Memory Update Trigger -// <0x21=> SLCD Automated Character Mapping Data Ready Trigger -// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger -// <0x23=> AES Write Trigger -// <0x24=> AES Read Trigger -// <0x25=> PTC End of Conversion Trigger -// <0x26=> PTC Sequence Trigger -// <0x27=> PTC Window Comparator Trigger -// <i> Defines the peripheral trigger which is source of the transfer -// <id> dmac_trifsrc_8 -#ifndef CONF_DMAC_TRIGSRC_8 -#define CONF_DMAC_TRIGSRC_8 0 -#endif - -// <o> Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// <i> Defines the arbitration level for this channel -// <id> dmac_lvl_8 -#ifndef CONF_DMAC_LVL_8 -#define CONF_DMAC_LVL_8 0 -#endif - -// <q> Channel Event Output -// <i> Indicates whether channel event generation is enabled or not -// <id> dmac_evoe_8 -#ifndef CONF_DMAC_EVOE_8 -#define CONF_DMAC_EVOE_8 0 -#endif - -// <q> Channel Event Input -// <i> Indicates whether channel event reception is enabled or not -// <id> dmac_evie_8 -#ifndef CONF_DMAC_EVIE_8 -#define CONF_DMAC_EVIE_8 0 -#endif - -// <o> Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// <i> Defines the event input action -// <id> dmac_evact_8 -#ifndef CONF_DMAC_EVACT_8 -#define CONF_DMAC_EVACT_8 0 -#endif - -// <o> Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// <i> Defines the address increment step size, applies to source or destination address -// <id> dmac_stepsize_8 -#ifndef CONF_DMAC_STEPSIZE_8 -#define CONF_DMAC_STEPSIZE_8 0 -#endif - -// <o> Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// <i> Defines whether source or destination addresses are using the step size settings -// <id> dmac_stepsel_8 -#ifndef CONF_DMAC_STEPSEL_8 -#define CONF_DMAC_STEPSEL_8 0 -#endif - -// <q> Source Address Increment -// <i> Indicates whether the source address incrementation is enabled or not -// <id> dmac_srcinc_8 -#ifndef CONF_DMAC_SRCINC_8 -#define CONF_DMAC_SRCINC_8 0 -#endif - -// <q> Destination Address Increment -// <i> Indicates whether the destination address incrementation is enabled or not -// <id> dmac_dstinc_8 -#ifndef CONF_DMAC_DSTINC_8 -#define CONF_DMAC_DSTINC_8 0 -#endif - -// <o> Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// <i> Defines the size of one beat -// <id> dmac_beatsize_8 -#ifndef CONF_DMAC_BEATSIZE_8 -#define CONF_DMAC_BEATSIZE_8 0 -#endif - -// <o> Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// <i> Defines the the DMAC should take after a block transfer has completed -// <id> dmac_blockact_8 -#ifndef CONF_DMAC_BLOCKACT_8 -#define CONF_DMAC_BLOCKACT_8 0 -#endif - -// <o> Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// <i> Defines the event output selection -// <id> dmac_evosel_8 -#ifndef CONF_DMAC_EVOSEL_8 -#define CONF_DMAC_EVOSEL_8 0 -#endif -// </e> - -// <e> Channel 9 settings -// <id> dmac_channel_9_settings -#ifndef CONF_DMAC_CHANNEL_9_SETTINGS -#define CONF_DMAC_CHANNEL_9_SETTINGS 0 -#endif - -// <q> Channel Enable -// <i> Indicates whether channel 9 is enabled or not -// <id> dmac_enable_9 -#ifndef CONF_DMAC_ENABLE_9 -#define CONF_DMAC_ENABLE_9 0 -#endif - -// <q> Channel Run in Standby -// <i> Indicates whether channel 9 is running in standby mode or not -// <id> dmac_runstdby_9 -#ifndef CONF_DMAC_RUNSTDBY_9 -#define CONF_DMAC_RUNSTDBY_9 0 -#endif - -// <o> Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// <i> Defines the trigger action used for a transfer -// <id> dmac_trigact_9 -#ifndef CONF_DMAC_TRIGACT_9 -#define CONF_DMAC_TRIGACT_9 0 -#endif - -// <o> Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Timestamp -// <0x02=> SERCOM0 RX Trigger -// <0x03=> SERCOM0 TX Trigger -// <0x04=> SERCOM1 RX Trigger -// <0x05=> SERCOM1 TX Trigger -// <0x06=> SERCOM2 RX Trigger -// <0x07=> SERCOM2 TX Trigger -// <0x08=> SERCOM3 RX Trigger -// <0x09=> SERCOM3 TX Trigger -// <0x0A=> SERCOM4 RX Trigger -// <0x0B=> SERCOM4 TX Trigger -// <0x0C=> SERCOM5 RX Trigger -// <0x0D=> SERCOM5 TX Trigger -// <0x0E=> TCC0 Overflow Trigger -// <0x0F=> TCC0 Match/Compare 0 Trigger -// <0x10=> TCC0 Match/Compare 1 Trigger -// <0x11=> TCC0 Match/Compare 2 Trigger -// <0x12=> TCC0 Match/Compare 3 Trigger -// <0x13=> TC0 Overflow Trigger -// <0x14=> TC0 Match/Compare 0 Trigger -// <0x15=> TC0 Match/Compare 1 Trigger -// <0x16=> TC1 Overflow Trigger -// <0x17=> TC1 Match/Compare 0 Trigger -// <0x18=> TC1 Match/Compare 1 Trigger -// <0x19=> TC2 Overflow Trigger -// <0x1A=> TC2 Match/Compare 0 Trigger -// <0x1B=> TC2 Match/Compare 1 Trigger -// <0x1C=> TC3 Overflow Trigger -// <0x1D=> TC3 Match/Compare 0 Trigger -// <0x1E=> TC3 Match/Compare 1 Trigger -// <0x1F=> ADC Result Ready Trigger -// <0x20=> SLCD Display Memory Update Trigger -// <0x21=> SLCD Automated Character Mapping Data Ready Trigger -// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger -// <0x23=> AES Write Trigger -// <0x24=> AES Read Trigger -// <0x25=> PTC End of Conversion Trigger -// <0x26=> PTC Sequence Trigger -// <0x27=> PTC Window Comparator Trigger -// <i> Defines the peripheral trigger which is source of the transfer -// <id> dmac_trifsrc_9 -#ifndef CONF_DMAC_TRIGSRC_9 -#define CONF_DMAC_TRIGSRC_9 0 -#endif - -// <o> Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// <i> Defines the arbitration level for this channel -// <id> dmac_lvl_9 -#ifndef CONF_DMAC_LVL_9 -#define CONF_DMAC_LVL_9 0 -#endif - -// <q> Channel Event Output -// <i> Indicates whether channel event generation is enabled or not -// <id> dmac_evoe_9 -#ifndef CONF_DMAC_EVOE_9 -#define CONF_DMAC_EVOE_9 0 -#endif - -// <q> Channel Event Input -// <i> Indicates whether channel event reception is enabled or not -// <id> dmac_evie_9 -#ifndef CONF_DMAC_EVIE_9 -#define CONF_DMAC_EVIE_9 0 -#endif - -// <o> Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// <i> Defines the event input action -// <id> dmac_evact_9 -#ifndef CONF_DMAC_EVACT_9 -#define CONF_DMAC_EVACT_9 0 -#endif - -// <o> Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// <i> Defines the address increment step size, applies to source or destination address -// <id> dmac_stepsize_9 -#ifndef CONF_DMAC_STEPSIZE_9 -#define CONF_DMAC_STEPSIZE_9 0 -#endif - -// <o> Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// <i> Defines whether source or destination addresses are using the step size settings -// <id> dmac_stepsel_9 -#ifndef CONF_DMAC_STEPSEL_9 -#define CONF_DMAC_STEPSEL_9 0 -#endif - -// <q> Source Address Increment -// <i> Indicates whether the source address incrementation is enabled or not -// <id> dmac_srcinc_9 -#ifndef CONF_DMAC_SRCINC_9 -#define CONF_DMAC_SRCINC_9 0 -#endif - -// <q> Destination Address Increment -// <i> Indicates whether the destination address incrementation is enabled or not -// <id> dmac_dstinc_9 -#ifndef CONF_DMAC_DSTINC_9 -#define CONF_DMAC_DSTINC_9 0 -#endif - -// <o> Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// <i> Defines the size of one beat -// <id> dmac_beatsize_9 -#ifndef CONF_DMAC_BEATSIZE_9 -#define CONF_DMAC_BEATSIZE_9 0 -#endif - -// <o> Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// <i> Defines the the DMAC should take after a block transfer has completed -// <id> dmac_blockact_9 -#ifndef CONF_DMAC_BLOCKACT_9 -#define CONF_DMAC_BLOCKACT_9 0 -#endif - -// <o> Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// <i> Defines the event output selection -// <id> dmac_evosel_9 -#ifndef CONF_DMAC_EVOSEL_9 -#define CONF_DMAC_EVOSEL_9 0 -#endif -// </e> - -// <e> Channel 10 settings -// <id> dmac_channel_10_settings -#ifndef CONF_DMAC_CHANNEL_10_SETTINGS -#define CONF_DMAC_CHANNEL_10_SETTINGS 0 -#endif - -// <q> Channel Enable -// <i> Indicates whether channel 10 is enabled or not -// <id> dmac_enable_10 -#ifndef CONF_DMAC_ENABLE_10 -#define CONF_DMAC_ENABLE_10 0 -#endif - -// <q> Channel Run in Standby -// <i> Indicates whether channel 10 is running in standby mode or not -// <id> dmac_runstdby_10 -#ifndef CONF_DMAC_RUNSTDBY_10 -#define CONF_DMAC_RUNSTDBY_10 0 -#endif - -// <o> Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// <i> Defines the trigger action used for a transfer -// <id> dmac_trigact_10 -#ifndef CONF_DMAC_TRIGACT_10 -#define CONF_DMAC_TRIGACT_10 0 -#endif - -// <o> Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Timestamp -// <0x02=> SERCOM0 RX Trigger -// <0x03=> SERCOM0 TX Trigger -// <0x04=> SERCOM1 RX Trigger -// <0x05=> SERCOM1 TX Trigger -// <0x06=> SERCOM2 RX Trigger -// <0x07=> SERCOM2 TX Trigger -// <0x08=> SERCOM3 RX Trigger -// <0x09=> SERCOM3 TX Trigger -// <0x0A=> SERCOM4 RX Trigger -// <0x0B=> SERCOM4 TX Trigger -// <0x0C=> SERCOM5 RX Trigger -// <0x0D=> SERCOM5 TX Trigger -// <0x0E=> TCC0 Overflow Trigger -// <0x0F=> TCC0 Match/Compare 0 Trigger -// <0x10=> TCC0 Match/Compare 1 Trigger -// <0x11=> TCC0 Match/Compare 2 Trigger -// <0x12=> TCC0 Match/Compare 3 Trigger -// <0x13=> TC0 Overflow Trigger -// <0x14=> TC0 Match/Compare 0 Trigger -// <0x15=> TC0 Match/Compare 1 Trigger -// <0x16=> TC1 Overflow Trigger -// <0x17=> TC1 Match/Compare 0 Trigger -// <0x18=> TC1 Match/Compare 1 Trigger -// <0x19=> TC2 Overflow Trigger -// <0x1A=> TC2 Match/Compare 0 Trigger -// <0x1B=> TC2 Match/Compare 1 Trigger -// <0x1C=> TC3 Overflow Trigger -// <0x1D=> TC3 Match/Compare 0 Trigger -// <0x1E=> TC3 Match/Compare 1 Trigger -// <0x1F=> ADC Result Ready Trigger -// <0x20=> SLCD Display Memory Update Trigger -// <0x21=> SLCD Automated Character Mapping Data Ready Trigger -// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger -// <0x23=> AES Write Trigger -// <0x24=> AES Read Trigger -// <0x25=> PTC End of Conversion Trigger -// <0x26=> PTC Sequence Trigger -// <0x27=> PTC Window Comparator Trigger -// <i> Defines the peripheral trigger which is source of the transfer -// <id> dmac_trifsrc_10 -#ifndef CONF_DMAC_TRIGSRC_10 -#define CONF_DMAC_TRIGSRC_10 0 -#endif - -// <o> Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// <i> Defines the arbitration level for this channel -// <id> dmac_lvl_10 -#ifndef CONF_DMAC_LVL_10 -#define CONF_DMAC_LVL_10 0 -#endif - -// <q> Channel Event Output -// <i> Indicates whether channel event generation is enabled or not -// <id> dmac_evoe_10 -#ifndef CONF_DMAC_EVOE_10 -#define CONF_DMAC_EVOE_10 0 -#endif - -// <q> Channel Event Input -// <i> Indicates whether channel event reception is enabled or not -// <id> dmac_evie_10 -#ifndef CONF_DMAC_EVIE_10 -#define CONF_DMAC_EVIE_10 0 -#endif - -// <o> Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// <i> Defines the event input action -// <id> dmac_evact_10 -#ifndef CONF_DMAC_EVACT_10 -#define CONF_DMAC_EVACT_10 0 -#endif - -// <o> Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// <i> Defines the address increment step size, applies to source or destination address -// <id> dmac_stepsize_10 -#ifndef CONF_DMAC_STEPSIZE_10 -#define CONF_DMAC_STEPSIZE_10 0 -#endif - -// <o> Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// <i> Defines whether source or destination addresses are using the step size settings -// <id> dmac_stepsel_10 -#ifndef CONF_DMAC_STEPSEL_10 -#define CONF_DMAC_STEPSEL_10 0 -#endif - -// <q> Source Address Increment -// <i> Indicates whether the source address incrementation is enabled or not -// <id> dmac_srcinc_10 -#ifndef CONF_DMAC_SRCINC_10 -#define CONF_DMAC_SRCINC_10 0 -#endif - -// <q> Destination Address Increment -// <i> Indicates whether the destination address incrementation is enabled or not -// <id> dmac_dstinc_10 -#ifndef CONF_DMAC_DSTINC_10 -#define CONF_DMAC_DSTINC_10 0 -#endif - -// <o> Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// <i> Defines the size of one beat -// <id> dmac_beatsize_10 -#ifndef CONF_DMAC_BEATSIZE_10 -#define CONF_DMAC_BEATSIZE_10 0 -#endif - -// <o> Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// <i> Defines the the DMAC should take after a block transfer has completed -// <id> dmac_blockact_10 -#ifndef CONF_DMAC_BLOCKACT_10 -#define CONF_DMAC_BLOCKACT_10 0 -#endif - -// <o> Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// <i> Defines the event output selection -// <id> dmac_evosel_10 -#ifndef CONF_DMAC_EVOSEL_10 -#define CONF_DMAC_EVOSEL_10 0 -#endif -// </e> - -// <e> Channel 11 settings -// <id> dmac_channel_11_settings -#ifndef CONF_DMAC_CHANNEL_11_SETTINGS -#define CONF_DMAC_CHANNEL_11_SETTINGS 0 -#endif - -// <q> Channel Enable -// <i> Indicates whether channel 11 is enabled or not -// <id> dmac_enable_11 -#ifndef CONF_DMAC_ENABLE_11 -#define CONF_DMAC_ENABLE_11 0 -#endif - -// <q> Channel Run in Standby -// <i> Indicates whether channel 11 is running in standby mode or not -// <id> dmac_runstdby_11 -#ifndef CONF_DMAC_RUNSTDBY_11 -#define CONF_DMAC_RUNSTDBY_11 0 -#endif - -// <o> Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// <i> Defines the trigger action used for a transfer -// <id> dmac_trigact_11 -#ifndef CONF_DMAC_TRIGACT_11 -#define CONF_DMAC_TRIGACT_11 0 -#endif - -// <o> Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Timestamp -// <0x02=> SERCOM0 RX Trigger -// <0x03=> SERCOM0 TX Trigger -// <0x04=> SERCOM1 RX Trigger -// <0x05=> SERCOM1 TX Trigger -// <0x06=> SERCOM2 RX Trigger -// <0x07=> SERCOM2 TX Trigger -// <0x08=> SERCOM3 RX Trigger -// <0x09=> SERCOM3 TX Trigger -// <0x0A=> SERCOM4 RX Trigger -// <0x0B=> SERCOM4 TX Trigger -// <0x0C=> SERCOM5 RX Trigger -// <0x0D=> SERCOM5 TX Trigger -// <0x0E=> TCC0 Overflow Trigger -// <0x0F=> TCC0 Match/Compare 0 Trigger -// <0x10=> TCC0 Match/Compare 1 Trigger -// <0x11=> TCC0 Match/Compare 2 Trigger -// <0x12=> TCC0 Match/Compare 3 Trigger -// <0x13=> TC0 Overflow Trigger -// <0x14=> TC0 Match/Compare 0 Trigger -// <0x15=> TC0 Match/Compare 1 Trigger -// <0x16=> TC1 Overflow Trigger -// <0x17=> TC1 Match/Compare 0 Trigger -// <0x18=> TC1 Match/Compare 1 Trigger -// <0x19=> TC2 Overflow Trigger -// <0x1A=> TC2 Match/Compare 0 Trigger -// <0x1B=> TC2 Match/Compare 1 Trigger -// <0x1C=> TC3 Overflow Trigger -// <0x1D=> TC3 Match/Compare 0 Trigger -// <0x1E=> TC3 Match/Compare 1 Trigger -// <0x1F=> ADC Result Ready Trigger -// <0x20=> SLCD Display Memory Update Trigger -// <0x21=> SLCD Automated Character Mapping Data Ready Trigger -// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger -// <0x23=> AES Write Trigger -// <0x24=> AES Read Trigger -// <0x25=> PTC End of Conversion Trigger -// <0x26=> PTC Sequence Trigger -// <0x27=> PTC Window Comparator Trigger -// <i> Defines the peripheral trigger which is source of the transfer -// <id> dmac_trifsrc_11 -#ifndef CONF_DMAC_TRIGSRC_11 -#define CONF_DMAC_TRIGSRC_11 0 -#endif - -// <o> Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// <i> Defines the arbitration level for this channel -// <id> dmac_lvl_11 -#ifndef CONF_DMAC_LVL_11 -#define CONF_DMAC_LVL_11 0 -#endif - -// <q> Channel Event Output -// <i> Indicates whether channel event generation is enabled or not -// <id> dmac_evoe_11 -#ifndef CONF_DMAC_EVOE_11 -#define CONF_DMAC_EVOE_11 0 -#endif - -// <q> Channel Event Input -// <i> Indicates whether channel event reception is enabled or not -// <id> dmac_evie_11 -#ifndef CONF_DMAC_EVIE_11 -#define CONF_DMAC_EVIE_11 0 -#endif - -// <o> Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// <i> Defines the event input action -// <id> dmac_evact_11 -#ifndef CONF_DMAC_EVACT_11 -#define CONF_DMAC_EVACT_11 0 -#endif - -// <o> Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// <i> Defines the address increment step size, applies to source or destination address -// <id> dmac_stepsize_11 -#ifndef CONF_DMAC_STEPSIZE_11 -#define CONF_DMAC_STEPSIZE_11 0 -#endif - -// <o> Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// <i> Defines whether source or destination addresses are using the step size settings -// <id> dmac_stepsel_11 -#ifndef CONF_DMAC_STEPSEL_11 -#define CONF_DMAC_STEPSEL_11 0 -#endif - -// <q> Source Address Increment -// <i> Indicates whether the source address incrementation is enabled or not -// <id> dmac_srcinc_11 -#ifndef CONF_DMAC_SRCINC_11 -#define CONF_DMAC_SRCINC_11 0 -#endif - -// <q> Destination Address Increment -// <i> Indicates whether the destination address incrementation is enabled or not -// <id> dmac_dstinc_11 -#ifndef CONF_DMAC_DSTINC_11 -#define CONF_DMAC_DSTINC_11 0 -#endif - -// <o> Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// <i> Defines the size of one beat -// <id> dmac_beatsize_11 -#ifndef CONF_DMAC_BEATSIZE_11 -#define CONF_DMAC_BEATSIZE_11 0 -#endif - -// <o> Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// <i> Defines the the DMAC should take after a block transfer has completed -// <id> dmac_blockact_11 -#ifndef CONF_DMAC_BLOCKACT_11 -#define CONF_DMAC_BLOCKACT_11 0 -#endif - -// <o> Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// <i> Defines the event output selection -// <id> dmac_evosel_11 -#ifndef CONF_DMAC_EVOSEL_11 -#define CONF_DMAC_EVOSEL_11 0 -#endif -// </e> - -// <e> Channel 12 settings -// <id> dmac_channel_12_settings -#ifndef CONF_DMAC_CHANNEL_12_SETTINGS -#define CONF_DMAC_CHANNEL_12_SETTINGS 0 -#endif - -// <q> Channel Enable -// <i> Indicates whether channel 12 is enabled or not -// <id> dmac_enable_12 -#ifndef CONF_DMAC_ENABLE_12 -#define CONF_DMAC_ENABLE_12 0 -#endif - -// <q> Channel Run in Standby -// <i> Indicates whether channel 12 is running in standby mode or not -// <id> dmac_runstdby_12 -#ifndef CONF_DMAC_RUNSTDBY_12 -#define CONF_DMAC_RUNSTDBY_12 0 -#endif - -// <o> Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// <i> Defines the trigger action used for a transfer -// <id> dmac_trigact_12 -#ifndef CONF_DMAC_TRIGACT_12 -#define CONF_DMAC_TRIGACT_12 0 -#endif - -// <o> Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Timestamp -// <0x02=> SERCOM0 RX Trigger -// <0x03=> SERCOM0 TX Trigger -// <0x04=> SERCOM1 RX Trigger -// <0x05=> SERCOM1 TX Trigger -// <0x06=> SERCOM2 RX Trigger -// <0x07=> SERCOM2 TX Trigger -// <0x08=> SERCOM3 RX Trigger -// <0x09=> SERCOM3 TX Trigger -// <0x0A=> SERCOM4 RX Trigger -// <0x0B=> SERCOM4 TX Trigger -// <0x0C=> SERCOM5 RX Trigger -// <0x0D=> SERCOM5 TX Trigger -// <0x0E=> TCC0 Overflow Trigger -// <0x0F=> TCC0 Match/Compare 0 Trigger -// <0x10=> TCC0 Match/Compare 1 Trigger -// <0x11=> TCC0 Match/Compare 2 Trigger -// <0x12=> TCC0 Match/Compare 3 Trigger -// <0x13=> TC0 Overflow Trigger -// <0x14=> TC0 Match/Compare 0 Trigger -// <0x15=> TC0 Match/Compare 1 Trigger -// <0x16=> TC1 Overflow Trigger -// <0x17=> TC1 Match/Compare 0 Trigger -// <0x18=> TC1 Match/Compare 1 Trigger -// <0x19=> TC2 Overflow Trigger -// <0x1A=> TC2 Match/Compare 0 Trigger -// <0x1B=> TC2 Match/Compare 1 Trigger -// <0x1C=> TC3 Overflow Trigger -// <0x1D=> TC3 Match/Compare 0 Trigger -// <0x1E=> TC3 Match/Compare 1 Trigger -// <0x1F=> ADC Result Ready Trigger -// <0x20=> SLCD Display Memory Update Trigger -// <0x21=> SLCD Automated Character Mapping Data Ready Trigger -// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger -// <0x23=> AES Write Trigger -// <0x24=> AES Read Trigger -// <0x25=> PTC End of Conversion Trigger -// <0x26=> PTC Sequence Trigger -// <0x27=> PTC Window Comparator Trigger -// <i> Defines the peripheral trigger which is source of the transfer -// <id> dmac_trifsrc_12 -#ifndef CONF_DMAC_TRIGSRC_12 -#define CONF_DMAC_TRIGSRC_12 0 -#endif - -// <o> Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// <i> Defines the arbitration level for this channel -// <id> dmac_lvl_12 -#ifndef CONF_DMAC_LVL_12 -#define CONF_DMAC_LVL_12 0 -#endif - -// <q> Channel Event Output -// <i> Indicates whether channel event generation is enabled or not -// <id> dmac_evoe_12 -#ifndef CONF_DMAC_EVOE_12 -#define CONF_DMAC_EVOE_12 0 -#endif - -// <q> Channel Event Input -// <i> Indicates whether channel event reception is enabled or not -// <id> dmac_evie_12 -#ifndef CONF_DMAC_EVIE_12 -#define CONF_DMAC_EVIE_12 0 -#endif - -// <o> Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// <i> Defines the event input action -// <id> dmac_evact_12 -#ifndef CONF_DMAC_EVACT_12 -#define CONF_DMAC_EVACT_12 0 -#endif - -// <o> Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// <i> Defines the address increment step size, applies to source or destination address -// <id> dmac_stepsize_12 -#ifndef CONF_DMAC_STEPSIZE_12 -#define CONF_DMAC_STEPSIZE_12 0 -#endif - -// <o> Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// <i> Defines whether source or destination addresses are using the step size settings -// <id> dmac_stepsel_12 -#ifndef CONF_DMAC_STEPSEL_12 -#define CONF_DMAC_STEPSEL_12 0 -#endif - -// <q> Source Address Increment -// <i> Indicates whether the source address incrementation is enabled or not -// <id> dmac_srcinc_12 -#ifndef CONF_DMAC_SRCINC_12 -#define CONF_DMAC_SRCINC_12 0 -#endif - -// <q> Destination Address Increment -// <i> Indicates whether the destination address incrementation is enabled or not -// <id> dmac_dstinc_12 -#ifndef CONF_DMAC_DSTINC_12 -#define CONF_DMAC_DSTINC_12 0 -#endif - -// <o> Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// <i> Defines the size of one beat -// <id> dmac_beatsize_12 -#ifndef CONF_DMAC_BEATSIZE_12 -#define CONF_DMAC_BEATSIZE_12 0 -#endif - -// <o> Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// <i> Defines the the DMAC should take after a block transfer has completed -// <id> dmac_blockact_12 -#ifndef CONF_DMAC_BLOCKACT_12 -#define CONF_DMAC_BLOCKACT_12 0 -#endif - -// <o> Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// <i> Defines the event output selection -// <id> dmac_evosel_12 -#ifndef CONF_DMAC_EVOSEL_12 -#define CONF_DMAC_EVOSEL_12 0 -#endif -// </e> - -// <e> Channel 13 settings -// <id> dmac_channel_13_settings -#ifndef CONF_DMAC_CHANNEL_13_SETTINGS -#define CONF_DMAC_CHANNEL_13_SETTINGS 0 -#endif - -// <q> Channel Enable -// <i> Indicates whether channel 13 is enabled or not -// <id> dmac_enable_13 -#ifndef CONF_DMAC_ENABLE_13 -#define CONF_DMAC_ENABLE_13 0 -#endif - -// <q> Channel Run in Standby -// <i> Indicates whether channel 13 is running in standby mode or not -// <id> dmac_runstdby_13 -#ifndef CONF_DMAC_RUNSTDBY_13 -#define CONF_DMAC_RUNSTDBY_13 0 -#endif - -// <o> Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// <i> Defines the trigger action used for a transfer -// <id> dmac_trigact_13 -#ifndef CONF_DMAC_TRIGACT_13 -#define CONF_DMAC_TRIGACT_13 0 -#endif - -// <o> Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Timestamp -// <0x02=> SERCOM0 RX Trigger -// <0x03=> SERCOM0 TX Trigger -// <0x04=> SERCOM1 RX Trigger -// <0x05=> SERCOM1 TX Trigger -// <0x06=> SERCOM2 RX Trigger -// <0x07=> SERCOM2 TX Trigger -// <0x08=> SERCOM3 RX Trigger -// <0x09=> SERCOM3 TX Trigger -// <0x0A=> SERCOM4 RX Trigger -// <0x0B=> SERCOM4 TX Trigger -// <0x0C=> SERCOM5 RX Trigger -// <0x0D=> SERCOM5 TX Trigger -// <0x0E=> TCC0 Overflow Trigger -// <0x0F=> TCC0 Match/Compare 0 Trigger -// <0x10=> TCC0 Match/Compare 1 Trigger -// <0x11=> TCC0 Match/Compare 2 Trigger -// <0x12=> TCC0 Match/Compare 3 Trigger -// <0x13=> TC0 Overflow Trigger -// <0x14=> TC0 Match/Compare 0 Trigger -// <0x15=> TC0 Match/Compare 1 Trigger -// <0x16=> TC1 Overflow Trigger -// <0x17=> TC1 Match/Compare 0 Trigger -// <0x18=> TC1 Match/Compare 1 Trigger -// <0x19=> TC2 Overflow Trigger -// <0x1A=> TC2 Match/Compare 0 Trigger -// <0x1B=> TC2 Match/Compare 1 Trigger -// <0x1C=> TC3 Overflow Trigger -// <0x1D=> TC3 Match/Compare 0 Trigger -// <0x1E=> TC3 Match/Compare 1 Trigger -// <0x1F=> ADC Result Ready Trigger -// <0x20=> SLCD Display Memory Update Trigger -// <0x21=> SLCD Automated Character Mapping Data Ready Trigger -// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger -// <0x23=> AES Write Trigger -// <0x24=> AES Read Trigger -// <0x25=> PTC End of Conversion Trigger -// <0x26=> PTC Sequence Trigger -// <0x27=> PTC Window Comparator Trigger -// <i> Defines the peripheral trigger which is source of the transfer -// <id> dmac_trifsrc_13 -#ifndef CONF_DMAC_TRIGSRC_13 -#define CONF_DMAC_TRIGSRC_13 0 -#endif - -// <o> Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// <i> Defines the arbitration level for this channel -// <id> dmac_lvl_13 -#ifndef CONF_DMAC_LVL_13 -#define CONF_DMAC_LVL_13 0 -#endif - -// <q> Channel Event Output -// <i> Indicates whether channel event generation is enabled or not -// <id> dmac_evoe_13 -#ifndef CONF_DMAC_EVOE_13 -#define CONF_DMAC_EVOE_13 0 -#endif - -// <q> Channel Event Input -// <i> Indicates whether channel event reception is enabled or not -// <id> dmac_evie_13 -#ifndef CONF_DMAC_EVIE_13 -#define CONF_DMAC_EVIE_13 0 -#endif - -// <o> Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// <i> Defines the event input action -// <id> dmac_evact_13 -#ifndef CONF_DMAC_EVACT_13 -#define CONF_DMAC_EVACT_13 0 -#endif - -// <o> Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// <i> Defines the address increment step size, applies to source or destination address -// <id> dmac_stepsize_13 -#ifndef CONF_DMAC_STEPSIZE_13 -#define CONF_DMAC_STEPSIZE_13 0 -#endif - -// <o> Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// <i> Defines whether source or destination addresses are using the step size settings -// <id> dmac_stepsel_13 -#ifndef CONF_DMAC_STEPSEL_13 -#define CONF_DMAC_STEPSEL_13 0 -#endif - -// <q> Source Address Increment -// <i> Indicates whether the source address incrementation is enabled or not -// <id> dmac_srcinc_13 -#ifndef CONF_DMAC_SRCINC_13 -#define CONF_DMAC_SRCINC_13 0 -#endif - -// <q> Destination Address Increment -// <i> Indicates whether the destination address incrementation is enabled or not -// <id> dmac_dstinc_13 -#ifndef CONF_DMAC_DSTINC_13 -#define CONF_DMAC_DSTINC_13 0 -#endif - -// <o> Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// <i> Defines the size of one beat -// <id> dmac_beatsize_13 -#ifndef CONF_DMAC_BEATSIZE_13 -#define CONF_DMAC_BEATSIZE_13 0 -#endif - -// <o> Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// <i> Defines the the DMAC should take after a block transfer has completed -// <id> dmac_blockact_13 -#ifndef CONF_DMAC_BLOCKACT_13 -#define CONF_DMAC_BLOCKACT_13 0 -#endif - -// <o> Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// <i> Defines the event output selection -// <id> dmac_evosel_13 -#ifndef CONF_DMAC_EVOSEL_13 -#define CONF_DMAC_EVOSEL_13 0 -#endif -// </e> - -// <e> Channel 14 settings -// <id> dmac_channel_14_settings -#ifndef CONF_DMAC_CHANNEL_14_SETTINGS -#define CONF_DMAC_CHANNEL_14_SETTINGS 0 -#endif - -// <q> Channel Enable -// <i> Indicates whether channel 14 is enabled or not -// <id> dmac_enable_14 -#ifndef CONF_DMAC_ENABLE_14 -#define CONF_DMAC_ENABLE_14 0 -#endif - -// <q> Channel Run in Standby -// <i> Indicates whether channel 14 is running in standby mode or not -// <id> dmac_runstdby_14 -#ifndef CONF_DMAC_RUNSTDBY_14 -#define CONF_DMAC_RUNSTDBY_14 0 -#endif - -// <o> Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// <i> Defines the trigger action used for a transfer -// <id> dmac_trigact_14 -#ifndef CONF_DMAC_TRIGACT_14 -#define CONF_DMAC_TRIGACT_14 0 -#endif - -// <o> Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Timestamp -// <0x02=> SERCOM0 RX Trigger -// <0x03=> SERCOM0 TX Trigger -// <0x04=> SERCOM1 RX Trigger -// <0x05=> SERCOM1 TX Trigger -// <0x06=> SERCOM2 RX Trigger -// <0x07=> SERCOM2 TX Trigger -// <0x08=> SERCOM3 RX Trigger -// <0x09=> SERCOM3 TX Trigger -// <0x0A=> SERCOM4 RX Trigger -// <0x0B=> SERCOM4 TX Trigger -// <0x0C=> SERCOM5 RX Trigger -// <0x0D=> SERCOM5 TX Trigger -// <0x0E=> TCC0 Overflow Trigger -// <0x0F=> TCC0 Match/Compare 0 Trigger -// <0x10=> TCC0 Match/Compare 1 Trigger -// <0x11=> TCC0 Match/Compare 2 Trigger -// <0x12=> TCC0 Match/Compare 3 Trigger -// <0x13=> TC0 Overflow Trigger -// <0x14=> TC0 Match/Compare 0 Trigger -// <0x15=> TC0 Match/Compare 1 Trigger -// <0x16=> TC1 Overflow Trigger -// <0x17=> TC1 Match/Compare 0 Trigger -// <0x18=> TC1 Match/Compare 1 Trigger -// <0x19=> TC2 Overflow Trigger -// <0x1A=> TC2 Match/Compare 0 Trigger -// <0x1B=> TC2 Match/Compare 1 Trigger -// <0x1C=> TC3 Overflow Trigger -// <0x1D=> TC3 Match/Compare 0 Trigger -// <0x1E=> TC3 Match/Compare 1 Trigger -// <0x1F=> ADC Result Ready Trigger -// <0x20=> SLCD Display Memory Update Trigger -// <0x21=> SLCD Automated Character Mapping Data Ready Trigger -// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger -// <0x23=> AES Write Trigger -// <0x24=> AES Read Trigger -// <0x25=> PTC End of Conversion Trigger -// <0x26=> PTC Sequence Trigger -// <0x27=> PTC Window Comparator Trigger -// <i> Defines the peripheral trigger which is source of the transfer -// <id> dmac_trifsrc_14 -#ifndef CONF_DMAC_TRIGSRC_14 -#define CONF_DMAC_TRIGSRC_14 0 -#endif - -// <o> Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// <i> Defines the arbitration level for this channel -// <id> dmac_lvl_14 -#ifndef CONF_DMAC_LVL_14 -#define CONF_DMAC_LVL_14 0 -#endif - -// <q> Channel Event Output -// <i> Indicates whether channel event generation is enabled or not -// <id> dmac_evoe_14 -#ifndef CONF_DMAC_EVOE_14 -#define CONF_DMAC_EVOE_14 0 -#endif - -// <q> Channel Event Input -// <i> Indicates whether channel event reception is enabled or not -// <id> dmac_evie_14 -#ifndef CONF_DMAC_EVIE_14 -#define CONF_DMAC_EVIE_14 0 -#endif - -// <o> Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// <i> Defines the event input action -// <id> dmac_evact_14 -#ifndef CONF_DMAC_EVACT_14 -#define CONF_DMAC_EVACT_14 0 -#endif - -// <o> Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// <i> Defines the address increment step size, applies to source or destination address -// <id> dmac_stepsize_14 -#ifndef CONF_DMAC_STEPSIZE_14 -#define CONF_DMAC_STEPSIZE_14 0 -#endif - -// <o> Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// <i> Defines whether source or destination addresses are using the step size settings -// <id> dmac_stepsel_14 -#ifndef CONF_DMAC_STEPSEL_14 -#define CONF_DMAC_STEPSEL_14 0 -#endif - -// <q> Source Address Increment -// <i> Indicates whether the source address incrementation is enabled or not -// <id> dmac_srcinc_14 -#ifndef CONF_DMAC_SRCINC_14 -#define CONF_DMAC_SRCINC_14 0 -#endif - -// <q> Destination Address Increment -// <i> Indicates whether the destination address incrementation is enabled or not -// <id> dmac_dstinc_14 -#ifndef CONF_DMAC_DSTINC_14 -#define CONF_DMAC_DSTINC_14 0 -#endif - -// <o> Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// <i> Defines the size of one beat -// <id> dmac_beatsize_14 -#ifndef CONF_DMAC_BEATSIZE_14 -#define CONF_DMAC_BEATSIZE_14 0 -#endif - -// <o> Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// <i> Defines the the DMAC should take after a block transfer has completed -// <id> dmac_blockact_14 -#ifndef CONF_DMAC_BLOCKACT_14 -#define CONF_DMAC_BLOCKACT_14 0 -#endif - -// <o> Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// <i> Defines the event output selection -// <id> dmac_evosel_14 -#ifndef CONF_DMAC_EVOSEL_14 -#define CONF_DMAC_EVOSEL_14 0 -#endif -// </e> - -// <e> Channel 15 settings -// <id> dmac_channel_15_settings -#ifndef CONF_DMAC_CHANNEL_15_SETTINGS -#define CONF_DMAC_CHANNEL_15_SETTINGS 0 -#endif - -// <q> Channel Enable -// <i> Indicates whether channel 15 is enabled or not -// <id> dmac_enable_15 -#ifndef CONF_DMAC_ENABLE_15 -#define CONF_DMAC_ENABLE_15 0 -#endif - -// <q> Channel Run in Standby -// <i> Indicates whether channel 15 is running in standby mode or not -// <id> dmac_runstdby_15 -#ifndef CONF_DMAC_RUNSTDBY_15 -#define CONF_DMAC_RUNSTDBY_15 0 -#endif - -// <o> Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// <i> Defines the trigger action used for a transfer -// <id> dmac_trigact_15 -#ifndef CONF_DMAC_TRIGACT_15 -#define CONF_DMAC_TRIGACT_15 0 -#endif - -// <o> Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Timestamp -// <0x02=> SERCOM0 RX Trigger -// <0x03=> SERCOM0 TX Trigger -// <0x04=> SERCOM1 RX Trigger -// <0x05=> SERCOM1 TX Trigger -// <0x06=> SERCOM2 RX Trigger -// <0x07=> SERCOM2 TX Trigger -// <0x08=> SERCOM3 RX Trigger -// <0x09=> SERCOM3 TX Trigger -// <0x0A=> SERCOM4 RX Trigger -// <0x0B=> SERCOM4 TX Trigger -// <0x0C=> SERCOM5 RX Trigger -// <0x0D=> SERCOM5 TX Trigger -// <0x0E=> TCC0 Overflow Trigger -// <0x0F=> TCC0 Match/Compare 0 Trigger -// <0x10=> TCC0 Match/Compare 1 Trigger -// <0x11=> TCC0 Match/Compare 2 Trigger -// <0x12=> TCC0 Match/Compare 3 Trigger -// <0x13=> TC0 Overflow Trigger -// <0x14=> TC0 Match/Compare 0 Trigger -// <0x15=> TC0 Match/Compare 1 Trigger -// <0x16=> TC1 Overflow Trigger -// <0x17=> TC1 Match/Compare 0 Trigger -// <0x18=> TC1 Match/Compare 1 Trigger -// <0x19=> TC2 Overflow Trigger -// <0x1A=> TC2 Match/Compare 0 Trigger -// <0x1B=> TC2 Match/Compare 1 Trigger -// <0x1C=> TC3 Overflow Trigger -// <0x1D=> TC3 Match/Compare 0 Trigger -// <0x1E=> TC3 Match/Compare 1 Trigger -// <0x1F=> ADC Result Ready Trigger -// <0x20=> SLCD Display Memory Update Trigger -// <0x21=> SLCD Automated Character Mapping Data Ready Trigger -// <0x22=> SLCD Automated Bit Mapping Data Ready Trigger -// <0x23=> AES Write Trigger -// <0x24=> AES Read Trigger -// <0x25=> PTC End of Conversion Trigger -// <0x26=> PTC Sequence Trigger -// <0x27=> PTC Window Comparator Trigger -// <i> Defines the peripheral trigger which is source of the transfer -// <id> dmac_trifsrc_15 -#ifndef CONF_DMAC_TRIGSRC_15 -#define CONF_DMAC_TRIGSRC_15 0 -#endif - -// <o> Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// <i> Defines the arbitration level for this channel -// <id> dmac_lvl_15 -#ifndef CONF_DMAC_LVL_15 -#define CONF_DMAC_LVL_15 0 -#endif - -// <q> Channel Event Output -// <i> Indicates whether channel event generation is enabled or not -// <id> dmac_evoe_15 -#ifndef CONF_DMAC_EVOE_15 -#define CONF_DMAC_EVOE_15 0 -#endif - -// <q> Channel Event Input -// <i> Indicates whether channel event reception is enabled or not -// <id> dmac_evie_15 -#ifndef CONF_DMAC_EVIE_15 -#define CONF_DMAC_EVIE_15 0 -#endif - -// <o> Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// <i> Defines the event input action -// <id> dmac_evact_15 -#ifndef CONF_DMAC_EVACT_15 -#define CONF_DMAC_EVACT_15 0 -#endif - -// <o> Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// <i> Defines the address increment step size, applies to source or destination address -// <id> dmac_stepsize_15 -#ifndef CONF_DMAC_STEPSIZE_15 -#define CONF_DMAC_STEPSIZE_15 0 -#endif - -// <o> Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// <i> Defines whether source or destination addresses are using the step size settings -// <id> dmac_stepsel_15 -#ifndef CONF_DMAC_STEPSEL_15 -#define CONF_DMAC_STEPSEL_15 0 -#endif - -// <q> Source Address Increment -// <i> Indicates whether the source address incrementation is enabled or not -// <id> dmac_srcinc_15 -#ifndef CONF_DMAC_SRCINC_15 -#define CONF_DMAC_SRCINC_15 0 -#endif - -// <q> Destination Address Increment -// <i> Indicates whether the destination address incrementation is enabled or not -// <id> dmac_dstinc_15 -#ifndef CONF_DMAC_DSTINC_15 -#define CONF_DMAC_DSTINC_15 0 -#endif - -// <o> Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// <i> Defines the size of one beat -// <id> dmac_beatsize_15 -#ifndef CONF_DMAC_BEATSIZE_15 -#define CONF_DMAC_BEATSIZE_15 0 -#endif - -// <o> Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// <i> Defines the the DMAC should take after a block transfer has completed -// <id> dmac_blockact_15 -#ifndef CONF_DMAC_BLOCKACT_15 -#define CONF_DMAC_BLOCKACT_15 0 -#endif - -// <o> Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// <i> Defines the event output selection -// <id> dmac_evosel_15 -#ifndef CONF_DMAC_EVOSEL_15 -#define CONF_DMAC_EVOSEL_15 0 -#endif -// </e> - -// </e> - -// <<< end of configuration section >>> - -#endif // HPL_DMAC_CONFIG_H diff --git a/watch-library/config/hpl_eic_config.h b/watch-library/config/hpl_eic_config.h deleted file mode 100644 index be54c2e1..00000000 --- a/watch-library/config/hpl_eic_config.h +++ /dev/null @@ -1,736 +0,0 @@ -/* Auto-generated config file hpl_eic_config.h */ -#ifndef HPL_EIC_CONFIG_H -#define HPL_EIC_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// <h> Basic Settings -// <o> Clock Selection -// <i> Indicates which clock used, The EIC can be clocked either by GCLK_EIC when higher frequency than 32KHz is required for filtering or -// <i> either by CLK_ULP32K when power consumption is the priority. -// <0x0=> Clocked by GCLK -// <0x1=> Clocked by ULPOSC32K -// <id> eic_arch_cksel -#ifndef CONF_EIC_CKSEL -#define CONF_EIC_CKSEL 0 -#endif - -// </h> - -// <e> Non-Maskable Interrupt Control -// <id> eic_arch_nmi_ctrl -#ifndef CONF_EIC_ENABLE_NMI_CTRL -#define CONF_EIC_ENABLE_NMI_CTRL 0 -#endif - -// <q> Non-Maskable Interrupt Filter Enable -// <i> Indicates whether the mon-maskable interrupt filter is enabled or not -// <id> eic_arch_nmifilten -#ifndef CONF_EIC_NMIFILTEN -#define CONF_EIC_NMIFILTEN 0 -#endif - -// <y> Non-Maskable Interrupt Sense -// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection -// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection -// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection -// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection -// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection -// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection -// <i> This defines non-maskable interrupt sense -// <id> eic_arch_nmisense -#ifndef CONF_EIC_NMISENSE -#define CONF_EIC_NMISENSE EIC_NMICTRL_NMISENSE_NONE_Val -#endif - -// <q> Asynchronous Edge Detection Mode -// <i> Indicates the interrupt detection mode operated synchronously or asynchronousl -// <id> eic_arch_nmiasynch -#ifndef CONF_EIC_NMIASYNCH -#define CONF_EIC_NMIASYNCH 0 -#endif -// </e> - -// <e> Interrupt 0 Settings -// <id> eic_arch_enable_irq_setting0 -#ifndef CONF_EIC_ENABLE_IRQ_SETTING0 -#define CONF_EIC_ENABLE_IRQ_SETTING0 0 -#endif - -// <q> External Interrupt 0 Filter Enable -// <i> Indicates whether the external interrupt 0 filter is enabled or not -// <id> eic_arch_filten0 -#ifndef CONF_EIC_FILTEN0 -#define CONF_EIC_FILTEN0 1 -#endif - -// <q> External Interrupt 0 Event Output Enable -// <i> Indicates whether the external interrupt 0 event output is enabled or not -// <id> eic_arch_extinteo0 -#ifndef CONF_EIC_EXTINTEO0 -#define CONF_EIC_EXTINTEO0 0 -#endif - -// <y> Input 0 Sense Configuration -// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection -// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection -// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection -// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection -// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection -// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection -// <i> This defines input sense trigger -// <id> eic_arch_sense0 -#ifndef CONF_EIC_SENSE0 -#define CONF_EIC_SENSE0 EIC_NMICTRL_NMISENSE_NONE_Val -#endif - -// <q> External Interrupt 0 Asynchronous Edge Detection Mode -// <i> Indicates the external interrupt 0 detection mode operated synchronously or asynchronousl -// <id> eic_arch_asynch0 -#ifndef CONF_EIC_ASYNCH0 -#define CONF_EIC_ASYNCH0 0 -#endif - -// </e> - -// <e> Interrupt 1 Settings -// <id> eic_arch_enable_irq_setting1 -#ifndef CONF_EIC_ENABLE_IRQ_SETTING1 -#define CONF_EIC_ENABLE_IRQ_SETTING1 0 -#endif - -// <q> External Interrupt 1 Filter Enable -// <i> Indicates whether the external interrupt 1 filter is enabled or not -// <id> eic_arch_filten1 -#ifndef CONF_EIC_FILTEN1 -#define CONF_EIC_FILTEN1 1 -#endif - -// <q> External Interrupt 1 Event Output Enable -// <i> Indicates whether the external interrupt 1 event output is enabled or not -// <id> eic_arch_extinteo1 -#ifndef CONF_EIC_EXTINTEO1 -#define CONF_EIC_EXTINTEO1 0 -#endif - -// <y> Input 1 Sense Configuration -// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection -// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection -// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection -// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection -// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection -// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection -// <i> This defines input sense trigger -// <id> eic_arch_sense1 -#ifndef CONF_EIC_SENSE1 -#define CONF_EIC_SENSE1 EIC_NMICTRL_NMISENSE_NONE_Val -#endif - -// <q> External Interrupt 1 Asynchronous Edge Detection Mode -// <i> Indicates the external interrupt 1 detection mode operated synchronously or asynchronousl -// <id> eic_arch_asynch1 -#ifndef CONF_EIC_ASYNCH1 -#define CONF_EIC_ASYNCH1 0 -#endif - -// </e> - -// <e> Interrupt 2 Settings -// <id> eic_arch_enable_irq_setting2 -#ifndef CONF_EIC_ENABLE_IRQ_SETTING2 -#define CONF_EIC_ENABLE_IRQ_SETTING2 0 -#endif - -// <q> External Interrupt 2 Filter Enable -// <i> Indicates whether the external interrupt 2 filter is enabled or not -// <id> eic_arch_filten2 -#ifndef CONF_EIC_FILTEN2 -#define CONF_EIC_FILTEN2 1 -#endif - -// <q> External Interrupt 2 Event Output Enable -// <i> Indicates whether the external interrupt 2 event output is enabled or not -// <id> eic_arch_extinteo2 -#ifndef CONF_EIC_EXTINTEO2 -#define CONF_EIC_EXTINTEO2 0 -#endif - -// <y> Input 2 Sense Configuration -// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection -// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection -// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection -// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection -// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection -// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection -// <i> This defines input sense trigger -// <id> eic_arch_sense2 -#ifndef CONF_EIC_SENSE2 -#define CONF_EIC_SENSE2 EIC_NMICTRL_NMISENSE_NONE_Val -#endif - -// <q> External Interrupt 2 Asynchronous Edge Detection Mode -// <i> Indicates the external interrupt 2 detection mode operated synchronously or asynchronousl -// <id> eic_arch_asynch2 -#ifndef CONF_EIC_ASYNCH2 -#define CONF_EIC_ASYNCH2 0 -#endif - -// </e> - -// <e> Interrupt 3 Settings -// <id> eic_arch_enable_irq_setting3 -#ifndef CONF_EIC_ENABLE_IRQ_SETTING3 -#define CONF_EIC_ENABLE_IRQ_SETTING3 0 -#endif - -// <q> External Interrupt 3 Filter Enable -// <i> Indicates whether the external interrupt 3 filter is enabled or not -// <id> eic_arch_filten3 -#ifndef CONF_EIC_FILTEN3 -#define CONF_EIC_FILTEN3 1 -#endif - -// <q> External Interrupt 3 Event Output Enable -// <i> Indicates whether the external interrupt 3 event output is enabled or not -// <id> eic_arch_extinteo3 -#ifndef CONF_EIC_EXTINTEO3 -#define CONF_EIC_EXTINTEO3 0 -#endif - -// <y> Input 3 Sense Configuration -// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection -// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection -// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection -// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection -// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection -// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection -// <i> This defines input sense trigger -// <id> eic_arch_sense3 -#ifndef CONF_EIC_SENSE3 -#define CONF_EIC_SENSE3 EIC_NMICTRL_NMISENSE_NONE_Val -#endif - -// <q> External Interrupt 3 Asynchronous Edge Detection Mode -// <i> Indicates the external interrupt 3 detection mode operated synchronously or asynchronousl -// <id> eic_arch_asynch3 -#ifndef CONF_EIC_ASYNCH3 -#define CONF_EIC_ASYNCH3 0 -#endif - -// </e> - -// <e> Interrupt 4 Settings -// <id> eic_arch_enable_irq_setting4 -#ifndef CONF_EIC_ENABLE_IRQ_SETTING4 -#define CONF_EIC_ENABLE_IRQ_SETTING4 0 -#endif - -// <q> External Interrupt 4 Filter Enable -// <i> Indicates whether the external interrupt 4 filter is enabled or not -// <id> eic_arch_filten4 -#ifndef CONF_EIC_FILTEN4 -#define CONF_EIC_FILTEN4 1 -#endif - -// <q> External Interrupt 4 Event Output Enable -// <i> Indicates whether the external interrupt 4 event output is enabled or not -// <id> eic_arch_extinteo4 -#ifndef CONF_EIC_EXTINTEO4 -#define CONF_EIC_EXTINTEO4 0 -#endif - -// <y> Input 4 Sense Configuration -// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection -// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection -// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection -// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection -// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection -// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection -// <i> This defines input sense trigger -// <id> eic_arch_sense4 -#ifndef CONF_EIC_SENSE4 -#define CONF_EIC_SENSE4 EIC_NMICTRL_NMISENSE_NONE_Val -#endif - -// <q> External Interrupt 4 Asynchronous Edge Detection Mode -// <i> Indicates the external interrupt 4 detection mode operated synchronously or asynchronousl -// <id> eic_arch_asynch4 -#ifndef CONF_EIC_ASYNCH4 -#define CONF_EIC_ASYNCH4 0 -#endif - -// </e> - -// <e> Interrupt 5 Settings -// <id> eic_arch_enable_irq_setting5 -#ifndef CONF_EIC_ENABLE_IRQ_SETTING5 -#define CONF_EIC_ENABLE_IRQ_SETTING5 0 -#endif - -// <q> External Interrupt 5 Filter Enable -// <i> Indicates whether the external interrupt 5 filter is enabled or not -// <id> eic_arch_filten5 -#ifndef CONF_EIC_FILTEN5 -#define CONF_EIC_FILTEN5 1 -#endif - -// <q> External Interrupt 5 Event Output Enable -// <i> Indicates whether the external interrupt 5 event output is enabled or not -// <id> eic_arch_extinteo5 -#ifndef CONF_EIC_EXTINTEO5 -#define CONF_EIC_EXTINTEO5 0 -#endif - -// <y> Input 5 Sense Configuration -// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection -// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection -// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection -// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection -// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection -// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection -// <i> This defines input sense trigger -// <id> eic_arch_sense5 -#ifndef CONF_EIC_SENSE5 -#define CONF_EIC_SENSE5 EIC_NMICTRL_NMISENSE_NONE_Val -#endif - -// <q> External Interrupt 5 Asynchronous Edge Detection Mode -// <i> Indicates the external interrupt 5 detection mode operated synchronously or asynchronousl -// <id> eic_arch_asynch5 -#ifndef CONF_EIC_ASYNCH5 -#define CONF_EIC_ASYNCH5 0 -#endif - -// </e> - -// <e> Interrupt 6 Settings -// <id> eic_arch_enable_irq_setting6 -#ifndef CONF_EIC_ENABLE_IRQ_SETTING6 -#define CONF_EIC_ENABLE_IRQ_SETTING6 0 -#endif - -// <q> External Interrupt 6 Filter Enable -// <i> Indicates whether the external interrupt 6 filter is enabled or not -// <id> eic_arch_filten6 -#ifndef CONF_EIC_FILTEN6 -#define CONF_EIC_FILTEN6 1 -#endif - -// <q> External Interrupt 6 Event Output Enable -// <i> Indicates whether the external interrupt 6 event output is enabled or not -// <id> eic_arch_extinteo6 -#ifndef CONF_EIC_EXTINTEO6 -#define CONF_EIC_EXTINTEO6 0 -#endif - -// <y> Input 6 Sense Configuration -// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection -// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection -// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection -// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection -// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection -// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection -// <i> This defines input sense trigger -// <id> eic_arch_sense6 -#ifndef CONF_EIC_SENSE6 -#define CONF_EIC_SENSE6 EIC_NMICTRL_NMISENSE_NONE_Val -#endif - -// <q> External Interrupt 6 Asynchronous Edge Detection Mode -// <i> Indicates the external interrupt 6 detection mode operated synchronously or asynchronousl -// <id> eic_arch_asynch6 -#ifndef CONF_EIC_ASYNCH6 -#define CONF_EIC_ASYNCH6 0 -#endif - -// </e> - -// <e> Interrupt 7 Settings -// <id> eic_arch_enable_irq_setting7 -#ifndef CONF_EIC_ENABLE_IRQ_SETTING7 -#define CONF_EIC_ENABLE_IRQ_SETTING7 0 -#endif - -// <q> External Interrupt 7 Filter Enable -// <i> Indicates whether the external interrupt 7 filter is enabled or not -// <id> eic_arch_filten7 -#ifndef CONF_EIC_FILTEN7 -#define CONF_EIC_FILTEN7 1 -#endif - -// <q> External Interrupt 7 Event Output Enable -// <i> Indicates whether the external interrupt 7 event output is enabled or not -// <id> eic_arch_extinteo7 -#ifndef CONF_EIC_EXTINTEO7 -#define CONF_EIC_EXTINTEO7 0 -#endif - -// <y> Input 7 Sense Configuration -// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection -// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection -// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection -// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection -// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection -// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection -// <i> This defines input sense trigger -// <id> eic_arch_sense7 -#ifndef CONF_EIC_SENSE7 -#define CONF_EIC_SENSE7 EIC_NMICTRL_NMISENSE_NONE_Val -#endif - -// <q> External Interrupt 7 Asynchronous Edge Detection Mode -// <i> Indicates the external interrupt 7 detection mode operated synchronously or asynchronousl -// <id> eic_arch_asynch7 -#ifndef CONF_EIC_ASYNCH7 -#define CONF_EIC_ASYNCH7 0 -#endif - -// </e> - -// <e> Interrupt 8 Settings -// <id> eic_arch_enable_irq_setting8 -#ifndef CONF_EIC_ENABLE_IRQ_SETTING8 -#define CONF_EIC_ENABLE_IRQ_SETTING8 0 -#endif - -// <q> External Interrupt 8 Filter Enable -// <i> Indicates whether the external interrupt 8 filter is enabled or not -// <id> eic_arch_filten8 -#ifndef CONF_EIC_FILTEN8 -#define CONF_EIC_FILTEN8 0 -#endif - -// <q> External Interrupt 8 Event Output Enable -// <i> Indicates whether the external interrupt 8 event output is enabled or not -// <id> eic_arch_extinteo8 -#ifndef CONF_EIC_EXTINTEO8 -#define CONF_EIC_EXTINTEO8 0 -#endif - -// <y> Input 8 Sense Configuration -// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection -// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection -// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection -// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection -// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection -// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection -// <i> This defines input sense trigger -// <id> eic_arch_sense8 -#ifndef CONF_EIC_SENSE8 -#define CONF_EIC_SENSE8 EIC_NMICTRL_NMISENSE_NONE_Val -#endif - -// <q> External Interrupt 8 Asynchronous Edge Detection Mode -// <i> Indicates the external interrupt 8 detection mode operated synchronously or asynchronousl -// <id> eic_arch_asynch8 -#ifndef CONF_EIC_ASYNCH8 -#define CONF_EIC_ASYNCH8 0 -#endif - -// </e> - -// <e> Interrupt 9 Settings -// <id> eic_arch_enable_irq_setting9 -#ifndef CONF_EIC_ENABLE_IRQ_SETTING9 -#define CONF_EIC_ENABLE_IRQ_SETTING9 0 -#endif - -// <q> External Interrupt 9 Filter Enable -// <i> Indicates whether the external interrupt 9 filter is enabled or not -// <id> eic_arch_filten9 -#ifndef CONF_EIC_FILTEN9 -#define CONF_EIC_FILTEN9 0 -#endif - -// <q> External Interrupt 9 Event Output Enable -// <i> Indicates whether the external interrupt 9 event output is enabled or not -// <id> eic_arch_extinteo9 -#ifndef CONF_EIC_EXTINTEO9 -#define CONF_EIC_EXTINTEO9 0 -#endif - -// <y> Input 9 Sense Configuration -// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection -// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection -// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection -// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection -// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection -// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection -// <i> This defines input sense trigger -// <id> eic_arch_sense9 -#ifndef CONF_EIC_SENSE9 -#define CONF_EIC_SENSE9 EIC_NMICTRL_NMISENSE_NONE_Val -#endif - -// <q> External Interrupt 9 Asynchronous Edge Detection Mode -// <i> Indicates the external interrupt 9 detection mode operated synchronously or asynchronousl -// <id> eic_arch_asynch9 -#ifndef CONF_EIC_ASYNCH9 -#define CONF_EIC_ASYNCH9 0 -#endif - -// </e> - -// <e> Interrupt 10 Settings -// <id> eic_arch_enable_irq_setting10 -#ifndef CONF_EIC_ENABLE_IRQ_SETTING10 -#define CONF_EIC_ENABLE_IRQ_SETTING10 0 -#endif - -// <q> External Interrupt 10 Filter Enable -// <i> Indicates whether the external interrupt 10 filter is enabled or not -// <id> eic_arch_filten10 -#ifndef CONF_EIC_FILTEN10 -#define CONF_EIC_FILTEN10 0 -#endif - -// <q> External Interrupt 10 Event Output Enable -// <i> Indicates whether the external interrupt 10 event output is enabled or not -// <id> eic_arch_extinteo10 -#ifndef CONF_EIC_EXTINTEO10 -#define CONF_EIC_EXTINTEO10 0 -#endif - -// <y> Input 10 Sense Configuration -// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection -// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection -// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection -// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection -// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection -// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection -// <i> This defines input sense trigger -// <id> eic_arch_sense10 -#ifndef CONF_EIC_SENSE10 -#define CONF_EIC_SENSE10 EIC_NMICTRL_NMISENSE_NONE_Val -#endif - -// <q> External Interrupt 10 Asynchronous Edge Detection Mode -// <i> Indicates the external interrupt 10 detection mode operated synchronously or asynchronousl -// <id> eic_arch_asynch10 -#ifndef CONF_EIC_ASYNCH10 -#define CONF_EIC_ASYNCH10 0 -#endif - -// </e> - -// <e> Interrupt 11 Settings -// <id> eic_arch_enable_irq_setting11 -#ifndef CONF_EIC_ENABLE_IRQ_SETTING11 -#define CONF_EIC_ENABLE_IRQ_SETTING11 0 -#endif - -// <q> External Interrupt 11 Filter Enable -// <i> Indicates whether the external interrupt 11 filter is enabled or not -// <id> eic_arch_filten11 -#ifndef CONF_EIC_FILTEN11 -#define CONF_EIC_FILTEN11 0 -#endif - -// <q> External Interrupt 11 Event Output Enable -// <i> Indicates whether the external interrupt 11 event output is enabled or not -// <id> eic_arch_extinteo11 -#ifndef CONF_EIC_EXTINTEO11 -#define CONF_EIC_EXTINTEO11 0 -#endif - -// <y> Input 11 Sense Configuration -// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection -// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection -// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection -// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection -// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection -// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection -// <i> This defines input sense trigger -// <id> eic_arch_sense11 -#ifndef CONF_EIC_SENSE11 -#define CONF_EIC_SENSE11 EIC_NMICTRL_NMISENSE_NONE_Val -#endif - -// <q> External Interrupt 11 Asynchronous Edge Detection Mode -// <i> Indicates the external interrupt 11 detection mode operated synchronously or asynchronousl -// <id> eic_arch_asynch11 -#ifndef CONF_EIC_ASYNCH11 -#define CONF_EIC_ASYNCH11 0 -#endif - -// </e> - -// <e> Interrupt 12 Settings -// <id> eic_arch_enable_irq_setting12 -#ifndef CONF_EIC_ENABLE_IRQ_SETTING12 -#define CONF_EIC_ENABLE_IRQ_SETTING12 0 -#endif - -// <q> External Interrupt 12 Filter Enable -// <i> Indicates whether the external interrupt 12 filter is enabled or not -// <id> eic_arch_filten12 -#ifndef CONF_EIC_FILTEN12 -#define CONF_EIC_FILTEN12 0 -#endif - -// <q> External Interrupt 12 Event Output Enable -// <i> Indicates whether the external interrupt 12 event output is enabled or not -// <id> eic_arch_extinteo12 -#ifndef CONF_EIC_EXTINTEO12 -#define CONF_EIC_EXTINTEO12 0 -#endif - -// <y> Input 12 Sense Configuration -// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection -// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection -// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection -// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection -// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection -// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection -// <i> This defines input sense trigger -// <id> eic_arch_sense12 -#ifndef CONF_EIC_SENSE12 -#define CONF_EIC_SENSE12 EIC_NMICTRL_NMISENSE_NONE_Val -#endif - -// <q> External Interrupt 12 Asynchronous Edge Detection Mode -// <i> Indicates the external interrupt 12 detection mode operated synchronously or asynchronousl -// <id> eic_arch_asynch12 -#ifndef CONF_EIC_ASYNCH12 -#define CONF_EIC_ASYNCH12 0 -#endif - -// </e> - -// <e> Interrupt 13 Settings -// <id> eic_arch_enable_irq_setting13 -#ifndef CONF_EIC_ENABLE_IRQ_SETTING13 -#define CONF_EIC_ENABLE_IRQ_SETTING13 0 -#endif - -// <q> External Interrupt 13 Filter Enable -// <i> Indicates whether the external interrupt 13 filter is enabled or not -// <id> eic_arch_filten13 -#ifndef CONF_EIC_FILTEN13 -#define CONF_EIC_FILTEN13 0 -#endif - -// <q> External Interrupt 13 Event Output Enable -// <i> Indicates whether the external interrupt 13 event output is enabled or not -// <id> eic_arch_extinteo13 -#ifndef CONF_EIC_EXTINTEO13 -#define CONF_EIC_EXTINTEO13 0 -#endif - -// <y> Input 13 Sense Configuration -// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection -// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection -// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection -// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection -// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection -// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection -// <i> This defines input sense trigger -// <id> eic_arch_sense13 -#ifndef CONF_EIC_SENSE13 -#define CONF_EIC_SENSE13 EIC_NMICTRL_NMISENSE_NONE_Val -#endif - -// <q> External Interrupt 13 Asynchronous Edge Detection Mode -// <i> Indicates the external interrupt 13 detection mode operated synchronously or asynchronousl -// <id> eic_arch_asynch13 -#ifndef CONF_EIC_ASYNCH13 -#define CONF_EIC_ASYNCH13 0 -#endif - -// </e> - -// <e> Interrupt 14 Settings -// <id> eic_arch_enable_irq_setting14 -#ifndef CONF_EIC_ENABLE_IRQ_SETTING14 -#define CONF_EIC_ENABLE_IRQ_SETTING14 0 -#endif - -// <q> External Interrupt 14 Filter Enable -// <i> Indicates whether the external interrupt 14 filter is enabled or not -// <id> eic_arch_filten14 -#ifndef CONF_EIC_FILTEN14 -#define CONF_EIC_FILTEN14 0 -#endif - -// <q> External Interrupt 14 Event Output Enable -// <i> Indicates whether the external interrupt 14 event output is enabled or not -// <id> eic_arch_extinteo14 -#ifndef CONF_EIC_EXTINTEO14 -#define CONF_EIC_EXTINTEO14 0 -#endif - -// <y> Input 14 Sense Configuration -// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection -// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection -// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection -// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection -// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection -// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection -// <i> This defines input sense trigger -// <id> eic_arch_sense14 -#ifndef CONF_EIC_SENSE14 -#define CONF_EIC_SENSE14 EIC_NMICTRL_NMISENSE_NONE_Val -#endif - -// <q> External Interrupt 14 Asynchronous Edge Detection Mode -// <i> Indicates the external interrupt 14 detection mode operated synchronously or asynchronousl -// <id> eic_arch_asynch14 -#ifndef CONF_EIC_ASYNCH14 -#define CONF_EIC_ASYNCH14 0 -#endif - -// </e> - -// <e> Interrupt 15 Settings -// <id> eic_arch_enable_irq_setting15 -#ifndef CONF_EIC_ENABLE_IRQ_SETTING15 -#define CONF_EIC_ENABLE_IRQ_SETTING15 0 -#endif - -// <q> External Interrupt 15 Filter Enable -// <i> Indicates whether the external interrupt 15 filter is enabled or not -// <id> eic_arch_filten15 -#ifndef CONF_EIC_FILTEN15 -#define CONF_EIC_FILTEN15 0 -#endif - -// <q> External Interrupt 15 Event Output Enable -// <i> Indicates whether the external interrupt 15 event output is enabled or not -// <id> eic_arch_extinteo15 -#ifndef CONF_EIC_EXTINTEO15 -#define CONF_EIC_EXTINTEO15 0 -#endif - -// <y> Input 15 Sense Configuration -// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection -// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection -// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection -// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection -// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection -// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection -// <i> This defines input sense trigger -// <id> eic_arch_sense15 -#ifndef CONF_EIC_SENSE15 -#define CONF_EIC_SENSE15 EIC_NMICTRL_NMISENSE_NONE_Val -#endif - -// <q> External Interrupt 15 Asynchronous Edge Detection Mode -// <i> Indicates the external interrupt 15 detection mode operated synchronously or asynchronousl -// <id> eic_arch_asynch15 -#ifndef CONF_EIC_ASYNCH15 -#define CONF_EIC_ASYNCH15 0 -#endif - -// </e> - -// this is still a hack: if the user wants to use PA02 (alarm button) as an RTC interrupt pin and PB02 (9-pin A2) on the EIC, we don't support that. -// TODO item: refactor out our reliance on the ASF external interrupt driver. - joey 11/30 -#ifdef CRYSTALLESS -#define CONFIG_EIC_EXTINT_MAP {0, PIN_PB00}, {1, PIN_PB01}, {2, PIN_PA02}, {3, PIN_PB03}, {5, PIN_PB05}, {7, PIN_PA07}, -#else -#define CONFIG_EIC_EXTINT_MAP {0, PIN_PB00}, {1, PIN_PB01}, {2, PIN_PA02}, {3, PIN_PB03}, {6, PIN_PA22}, {7, PIN_PA23}, -#endif - -// <<< end of configuration section >>> - -#endif // HPL_EIC_CONFIG_H diff --git a/watch-library/config/hpl_gclk_config.h b/watch-library/config/hpl_gclk_config.h deleted file mode 100644 index ee7aace3..00000000 --- a/watch-library/config/hpl_gclk_config.h +++ /dev/null @@ -1,388 +0,0 @@ -/* Auto-generated config file hpl_gclk_config.h */ -#ifndef HPL_GCLK_CONFIG_H -#define HPL_GCLK_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// <e> Generic clock generator 0 configuration -// <i> Indicates whether generic clock 0 configuration is enabled or not -// <id> enable_gclk_gen_0 -#ifndef CONF_GCLK_GENERATOR_0_CONFIG -#define CONF_GCLK_GENERATOR_0_CONFIG 1 -#endif - -// <h> Generic Clock Generator Control -// <y> Generic clock generator 0 source -// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC) -// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad -// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1 -// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) -// <GCLK_GENCTRL_SRC_OSC16M"> 16MHz Internal Oscillator (OSC16M) -// <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M) -// <GCLK_GENCTRL_SRC_DPLL96M"> Fractional Digital Phase Locked Loop (FDPLL96M) -// <i> This defines the clock source for generic clock generator 0 -// <id> gclk_gen_0_oscillator -#ifndef CONF_GCLK_GEN_0_SOURCE -#define CONF_GCLK_GEN_0_SOURCE GCLK_GENCTRL_SRC_OSC16M -#endif - -// <q> Run in Standby -// <i> Indicates whether Run in Standby is enabled or not -// <id> gclk_arch_gen_0_runstdby -#ifndef CONF_GCLK_GEN_0_RUNSTDBY -#define CONF_GCLK_GEN_0_RUNSTDBY 0 -#endif - -// <q> Divide Selection -// <i> Indicates whether Divide Selection is enabled or not -//<id> gclk_gen_0_div_sel -#ifndef CONF_GCLK_GEN_0_DIVSEL -#define CONF_GCLK_GEN_0_DIVSEL 0 -#endif - -// <q> Output Enable -// <i> Indicates whether Output Enable is enabled or not -// <id> gclk_arch_gen_0_oe -#ifndef CONF_GCLK_GEN_0_OE -#define CONF_GCLK_GEN_0_OE 0 -#endif - -// <q> Output Off Value -// <i> Indicates whether Output Off Value is enabled or not -// <id> gclk_arch_gen_0_oov -#ifndef CONF_GCLK_GEN_0_OOV -#define CONF_GCLK_GEN_0_OOV 0 -#endif - -// <q> Improve Duty Cycle -// <i> Indicates whether Improve Duty Cycle is enabled or not -// <id> gclk_arch_gen_0_idc -#ifndef CONF_GCLK_GEN_0_IDC -#define CONF_GCLK_GEN_0_IDC 0 -#endif - -// <q> Generic Clock Generator Enable -// <i> Indicates whether Generic Clock Generator Enable is enabled or not -// <id> gclk_arch_gen_0_enable -#ifndef CONF_GCLK_GEN_0_GENEN -#define CONF_GCLK_GEN_0_GENEN 1 -#endif -// </h> - -//<h> Generic Clock Generator Division -//<o> Generic clock generator 0 division <0x0000-0xFFFF> -// <id> gclk_gen_0_div -#ifndef CONF_GCLK_GEN_0_DIV -#define CONF_GCLK_GEN_0_DIV 1 -#endif -// </h> -// </e> - -// <e> Generic clock generator 1 configuration -// <i> Indicates whether generic clock 1 configuration is enabled or not -// <id> enable_gclk_gen_1 -#ifndef CONF_GCLK_GENERATOR_1_CONFIG -#define CONF_GCLK_GENERATOR_1_CONFIG 0 -#endif - -// <h> Generic Clock Generator Control -// <y> Generic clock generator 1 source -// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC) -// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad -// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) -// <GCLK_GENCTRL_SRC_OSC16M"> 16MHz Internal Oscillator (OSC16M) -// <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M) -// <GCLK_GENCTRL_SRC_DPLL96M"> Fractional Digital Phase Locked Loop (FDPLL96M) -// <i> This defines the clock source for generic clock generator 1 -// <id> gclk_gen_1_oscillator -#ifndef CONF_GCLK_GEN_1_SOURCE -#define CONF_GCLK_GEN_1_SOURCE GCLK_GENCTRL_SRC_XOSC -#endif - -// <q> Run in Standby -// <i> Indicates whether Run in Standby is enabled or not -// <id> gclk_arch_gen_1_runstdby -#ifndef CONF_GCLK_GEN_1_RUNSTDBY -#define CONF_GCLK_GEN_1_RUNSTDBY 0 -#endif - -// <q> Divide Selection -// <i> Indicates whether Divide Selection is enabled or not -//<id> gclk_gen_1_div_sel -#ifndef CONF_GCLK_GEN_1_DIVSEL -#define CONF_GCLK_GEN_1_DIVSEL 0 -#endif - -// <q> Output Enable -// <i> Indicates whether Output Enable is enabled or not -// <id> gclk_arch_gen_1_oe -#ifndef CONF_GCLK_GEN_1_OE -#define CONF_GCLK_GEN_1_OE 0 -#endif - -// <q> Output Off Value -// <i> Indicates whether Output Off Value is enabled or not -// <id> gclk_arch_gen_1_oov -#ifndef CONF_GCLK_GEN_1_OOV -#define CONF_GCLK_GEN_1_OOV 0 -#endif - -// <q> Improve Duty Cycle -// <i> Indicates whether Improve Duty Cycle is enabled or not -// <id> gclk_arch_gen_1_idc -#ifndef CONF_GCLK_GEN_1_IDC -#define CONF_GCLK_GEN_1_IDC 0 -#endif - -// <q> Generic Clock Generator Enable -// <i> Indicates whether Generic Clock Generator Enable is enabled or not -// <id> gclk_arch_gen_1_enable -#ifndef CONF_GCLK_GEN_1_GENEN -#define CONF_GCLK_GEN_1_GENEN 0 -#endif -// </h> - -//<h> Generic Clock Generator Division -//<o> Generic clock generator 1 division <0x0000-0xFFFF> -// <id> gclk_gen_1_div -#ifndef CONF_GCLK_GEN_1_DIV -#define CONF_GCLK_GEN_1_DIV 1 -#endif -// </h> -// </e> - -// <e> Generic clock generator 2 configuration -// <i> Indicates whether generic clock 2 configuration is enabled or not -// <id> enable_gclk_gen_2 -#ifndef CONF_GCLK_GENERATOR_2_CONFIG -#define CONF_GCLK_GENERATOR_2_CONFIG 0 -#endif - -// <h> Generic Clock Generator Control -// <y> Generic clock generator 2 source -// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC) -// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad -// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1 -// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) -// <GCLK_GENCTRL_SRC_OSC16M"> 16MHz Internal Oscillator (OSC16M) -// <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M) -// <GCLK_GENCTRL_SRC_DPLL96M"> Fractional Digital Phase Locked Loop (FDPLL96M) -// <i> This defines the clock source for generic clock generator 2 -// <id> gclk_gen_2_oscillator -#ifndef CONF_GCLK_GEN_2_SOURCE -#define CONF_GCLK_GEN_2_SOURCE GCLK_GENCTRL_SRC_XOSC -#endif - -// <q> Run in Standby -// <i> Indicates whether Run in Standby is enabled or not -// <id> gclk_arch_gen_2_runstdby -#ifndef CONF_GCLK_GEN_2_RUNSTDBY -#define CONF_GCLK_GEN_2_RUNSTDBY 0 -#endif - -// <q> Divide Selection -// <i> Indicates whether Divide Selection is enabled or not -//<id> gclk_gen_2_div_sel -#ifndef CONF_GCLK_GEN_2_DIVSEL -#define CONF_GCLK_GEN_2_DIVSEL 0 -#endif - -// <q> Output Enable -// <i> Indicates whether Output Enable is enabled or not -// <id> gclk_arch_gen_2_oe -#ifndef CONF_GCLK_GEN_2_OE -#define CONF_GCLK_GEN_2_OE 0 -#endif - -// <q> Output Off Value -// <i> Indicates whether Output Off Value is enabled or not -// <id> gclk_arch_gen_2_oov -#ifndef CONF_GCLK_GEN_2_OOV -#define CONF_GCLK_GEN_2_OOV 0 -#endif - -// <q> Improve Duty Cycle -// <i> Indicates whether Improve Duty Cycle is enabled or not -// <id> gclk_arch_gen_2_idc -#ifndef CONF_GCLK_GEN_2_IDC -#define CONF_GCLK_GEN_2_IDC 0 -#endif - -// <q> Generic Clock Generator Enable -// <i> Indicates whether Generic Clock Generator Enable is enabled or not -// <id> gclk_arch_gen_2_enable -#ifndef CONF_GCLK_GEN_2_GENEN -#define CONF_GCLK_GEN_2_GENEN 0 -#endif -// </h> - -//<h> Generic Clock Generator Division -//<o> Generic clock generator 2 division <0x0000-0xFFFF> -// <id> gclk_gen_2_div -#ifndef CONF_GCLK_GEN_2_DIV -#define CONF_GCLK_GEN_2_DIV 1 -#endif -// </h> -// </e> - -// <e> Generic clock generator 3 configuration -// <i> Indicates whether generic clock 3 configuration is enabled or not -// <id> enable_gclk_gen_3 -#ifndef CONF_GCLK_GENERATOR_3_CONFIG -#define CONF_GCLK_GENERATOR_3_CONFIG 1 -#endif - -// <h> Generic Clock Generator Control -// <y> Generic clock generator 3 source -// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC) -// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad -// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1 -// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) -// <GCLK_GENCTRL_SRC_OSC16M"> 16MHz Internal Oscillator (OSC16M) -// <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M) -// <GCLK_GENCTRL_SRC_DPLL96M"> Fractional Digital Phase Locked Loop (FDPLL96M) -// <i> This defines the clock source for generic clock generator 3 -// <id> gclk_gen_3_oscillator -#ifndef CONF_GCLK_GEN_3_SOURCE -#ifdef CRYSTALLESS -#define CONF_GCLK_GEN_3_SOURCE GCLK_GENCTRL_SRC_OSCULP32K -#else -#define CONF_GCLK_GEN_3_SOURCE GCLK_GENCTRL_SRC_XOSC32K -#endif - -#endif - -// <q> Run in Standby -// <i> Indicates whether Run in Standby is enabled or not -// <id> gclk_arch_gen_3_runstdby -#ifndef CONF_GCLK_GEN_3_RUNSTDBY -#define CONF_GCLK_GEN_3_RUNSTDBY 1 -#endif - -// <q> Divide Selection -// <i> Indicates whether Divide Selection is enabled or not -//<id> gclk_gen_3_div_sel -#ifndef CONF_GCLK_GEN_3_DIVSEL -#define CONF_GCLK_GEN_3_DIVSEL 0 -#endif - -// <q> Output Enable -// <i> Indicates whether Output Enable is enabled or not -// <id> gclk_arch_gen_3_oe -#ifndef CONF_GCLK_GEN_3_OE -#define CONF_GCLK_GEN_3_OE 0 -#endif - -// <q> Output Off Value -// <i> Indicates whether Output Off Value is enabled or not -// <id> gclk_arch_gen_3_oov -#ifndef CONF_GCLK_GEN_3_OOV -#define CONF_GCLK_GEN_3_OOV 0 -#endif - -// <q> Improve Duty Cycle -// <i> Indicates whether Improve Duty Cycle is enabled or not -// <id> gclk_arch_gen_3_idc -#ifndef CONF_GCLK_GEN_3_IDC -#define CONF_GCLK_GEN_3_IDC 1 -#endif - -// <q> Generic Clock Generator Enable -// <i> Indicates whether Generic Clock Generator Enable is enabled or not -// <id> gclk_arch_gen_3_enable -#ifndef CONF_GCLK_GEN_3_GENEN -#define CONF_GCLK_GEN_3_GENEN 1 -#endif -// </h> - -//<h> Generic Clock Generator Division -//<o> Generic clock generator 3 division <0x0000-0xFFFF> -// <id> gclk_gen_3_div -#ifndef CONF_GCLK_GEN_3_DIV -#define CONF_GCLK_GEN_3_DIV 1 -#endif -// </h> -// </e> - -// <e> Generic clock generator 4 configuration -// <i> Indicates whether generic clock 4 configuration is enabled or not -// <id> enable_gclk_gen_4 -#ifndef CONF_GCLK_GENERATOR_4_CONFIG -#define CONF_GCLK_GENERATOR_4_CONFIG 0 -#endif - -// <h> Generic Clock Generator Control -// <y> Generic clock generator 4 source -// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC) -// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad -// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1 -// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) -// <GCLK_GENCTRL_SRC_OSC16M"> 16MHz Internal Oscillator (OSC16M) -// <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M) -// <GCLK_GENCTRL_SRC_DPLL96M"> Fractional Digital Phase Locked Loop (FDPLL96M) -// <i> This defines the clock source for generic clock generator 4 -// <id> gclk_gen_4_oscillator -#ifndef CONF_GCLK_GEN_4_SOURCE -#define CONF_GCLK_GEN_4_SOURCE GCLK_GENCTRL_SRC_XOSC -#endif - -// <q> Run in Standby -// <i> Indicates whether Run in Standby is enabled or not -// <id> gclk_arch_gen_4_runstdby -#ifndef CONF_GCLK_GEN_4_RUNSTDBY -#define CONF_GCLK_GEN_4_RUNSTDBY 0 -#endif - -// <q> Divide Selection -// <i> Indicates whether Divide Selection is enabled or not -//<id> gclk_gen_4_div_sel -#ifndef CONF_GCLK_GEN_4_DIVSEL -#define CONF_GCLK_GEN_4_DIVSEL 0 -#endif - -// <q> Output Enable -// <i> Indicates whether Output Enable is enabled or not -// <id> gclk_arch_gen_4_oe -#ifndef CONF_GCLK_GEN_4_OE -#define CONF_GCLK_GEN_4_OE 0 -#endif - -// <q> Output Off Value -// <i> Indicates whether Output Off Value is enabled or not -// <id> gclk_arch_gen_4_oov -#ifndef CONF_GCLK_GEN_4_OOV -#define CONF_GCLK_GEN_4_OOV 0 -#endif - -// <q> Improve Duty Cycle -// <i> Indicates whether Improve Duty Cycle is enabled or not -// <id> gclk_arch_gen_4_idc -#ifndef CONF_GCLK_GEN_4_IDC -#define CONF_GCLK_GEN_4_IDC 0 -#endif - -// <q> Generic Clock Generator Enable -// <i> Indicates whether Generic Clock Generator Enable is enabled or not -// <id> gclk_arch_gen_4_enable -#ifndef CONF_GCLK_GEN_4_GENEN -#define CONF_GCLK_GEN_4_GENEN 0 -#endif -// </h> - -//<h> Generic Clock Generator Division -//<o> Generic clock generator 4 division <0x0000-0xFFFF> -// <id> gclk_gen_4_div -#ifndef CONF_GCLK_GEN_4_DIV -#define CONF_GCLK_GEN_4_DIV 1 -#endif -// </h> -// </e> - -// <<< end of configuration section >>> - -#endif // HPL_GCLK_CONFIG_H diff --git a/watch-library/config/hpl_mclk_config.h b/watch-library/config/hpl_mclk_config.h deleted file mode 100644 index 3358edcf..00000000 --- a/watch-library/config/hpl_mclk_config.h +++ /dev/null @@ -1,85 +0,0 @@ -/* Auto-generated config file hpl_mclk_config.h */ -#ifndef HPL_MCLK_CONFIG_H -#define HPL_MCLK_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -#include <peripheral_clk_config.h> - -// <e> System Configuration -// <i> Indicates whether configuration for system is enabled or not -// <id> enable_cpu_clock -#ifndef CONF_SYSTEM_CONFIG -#define CONF_SYSTEM_CONFIG 1 -#endif - -// <h> Basic settings -// <y> CPU Clock source -// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 -// <i> This defines the clock source for the CPU -// <id> cpu_clock_source -#ifndef CONF_CPU_SRC -#define CONF_CPU_SRC GCLK_PCHCTRL_GEN_GCLK0_Val -#endif - -// <y> CPU Clock Division Factor -// <MCLK_CPUDIV_CPUDIV_DIV1_Val"> 1 -// <MCLK_CPUDIV_CPUDIV_DIV2_Val"> 2 -// <MCLK_CPUDIV_CPUDIV_DIV4_Val"> 4 -// <MCLK_CPUDIV_CPUDIV_DIV8_Val"> 8 -// <MCLK_CPUDIV_CPUDIV_DIV16_Val"> 16 -// <MCLK_CPUDIV_CPUDIV_DIV32_Val"> 32 -// <MCLK_CPUDIV_CPUDIV_DIV64_Val"> 64 -// <MCLK_CPUDIV_CPUDIV_DIV128_Val"> 128 -// <i> Prescalar for CPU clock -// <id> cpu_div -#ifndef CONF_MCLK_CPUDIV -#define CONF_MCLK_CPUDIV MCLK_CPUDIV_CPUDIV_DIV1_Val -#endif - -// <y> Backup Clock Division -// <MCLK_BUPDIV_BUPDIV_DIV1_Val"> Divide by 1 -// <MCLK_BUPDIV_BUPDIV_DIV2_Val"> Divide by 2 -// <MCLK_BUPDIV_BUPDIV_DIV4_Val"> Divide by 4 -// <MCLK_BUPDIV_BUPDIV_DIV8_Val"> Divide by 8 -// <MCLK_BUPDIV_BUPDIV_DIV16_Val"> Divide by 16 -// <MCLK_BUPDIV_BUPDIV_DIV32_Val"> Divide by 32 -// <MCLK_BUPDIV_BUPDIV_DIV64_Val"> Divide by 64 -// <MCLK_BUPDIV_BUPDIV_DIV128_Val"> Divide by 128 -// <id> mclk_arch_bupdiv -#ifndef CONF_MCLK_BUPDIV -#define CONF_MCLK_BUPDIV MCLK_BUPDIV_BUPDIV_DIV1_Val -#endif -// </h> - -// <h> NVM Settings -// <o> NVM Wait States -// <i> These bits select the number of wait states for a read operation. -// <0=> 0 -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 -// <8=> 8 -// <9=> 9 -// <10=> 10 -// <11=> 11 -// <12=> 12 -// <13=> 13 -// <14=> 14 -// <15=> 15 -// <id> nvm_wait_states -#ifndef CONF_NVM_WAIT_STATE -#define CONF_NVM_WAIT_STATE 0 -#endif - -// </h> - -// </e> - -// <<< end of configuration section >>> - -#endif // HPL_MCLK_CONFIG_H diff --git a/watch-library/config/hpl_nvmctrl_config.h b/watch-library/config/hpl_nvmctrl_config.h deleted file mode 100755 index 76d49bac..00000000 --- a/watch-library/config/hpl_nvmctrl_config.h +++ /dev/null @@ -1,38 +0,0 @@ -/* Auto-generated config file hpl_nvmctrl_config.h */ -#ifndef HPL_NVMCTRL_CONFIG_H -#define HPL_NVMCTRL_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// <h> Basic Settings - -// <o> Read Mode Selection -// <0x00=> No Miss Penalty -// <0x01=> Low Power -// <0x02=> Deterministic -// <id> nvm_arch_read_mode -#ifndef CONF_NVM_READ_MODE -#define CONF_NVM_READ_MODE 1 -#endif - -// <o> Power Reduction Mode During Sleep -// <0x00=> Wake On Access -// <0x01=> Wake Up Instant -// <0x03=> Disabled -// <id> nvm_arch_sleepprm -#ifndef CONF_NVM_SLEEPPRM -#define CONF_NVM_SLEEPPRM 0 -#endif - -// <q> Cache Disable -// <i> Indicate whether cache is disable or not -// <id> nvm_arch_cache -#ifndef CONF_NVM_CACHE -#define CONF_NVM_CACHE 0 -#endif - -// </h> - -// <<< end of configuration section >>> - -#endif // HPL_NVMCTRL_CONFIG_H diff --git a/watch-library/config/hpl_osc32kctrl_config.h b/watch-library/config/hpl_osc32kctrl_config.h deleted file mode 100644 index 540f1c60..00000000 --- a/watch-library/config/hpl_osc32kctrl_config.h +++ /dev/null @@ -1,177 +0,0 @@ -/* Auto-generated config file hpl_osc32kctrl_config.h */ -#ifndef HPL_OSC32KCTRL_CONFIG_H -#define HPL_OSC32KCTRL_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// <e> RTC Source configuration -// <id> enable_rtc_source -#ifndef CONF_RTCCTRL_CONFIG -#define CONF_RTCCTRL_CONFIG 0 -#endif - -// <h> RTC source control -// <y> RTC Clock Source Selection -// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) -// <i> This defines the clock source for RTC -// <id> rtc_source_oscillator -#ifndef CONF_RTCCTRL_SRC -#ifdef CRYSTALLESS -#define CONF_RTCCTRL_SRC GCLK_GENCTRL_SRC_OSCULP32K -#else -#define CONF_RTCCTRL_SRC GCLK_GENCTRL_SRC_XOSC32K -#endif -#endif - -// <q> Use 1 kHz output -// <id> rtc_1khz_selection -#ifndef CONF_RTCCTRL_1KHZ - -#define CONF_RTCCTRL_1KHZ 1 - -#endif - -#if CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_OSCULP32K -#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val) -#elif CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_XOSC32K -#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val) -#else -#error unexpected CONF_RTCCTRL_SRC -#endif - -// </h> -// </e> -// <e> SLCD Source configuration -// <id> enable_slcd_source -#ifndef CONF_SLCDCTRL_CONFIG -#define CONF_SLCDCTRL_CONFIG 0 -#endif - -// <h> SLCD source control -// <y> SLCD Clock Source Selection -// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) -// <i> This defines the clock source for SLCD -// <id> slcd_source_oscillator -#ifndef CONF_SLCDCTRL_SRC -#define CONF_SLCDCTRL_SRC GCLK_GENCTRL_SRC_XOSC32K -#endif - -// </h> -// </e> -// <e> 32kHz External Crystal Oscillator Configuration -// <i> Indicates whether configuration for External 32K Osc is enabled or not -// <id> enable_xosc32k -#ifndef CONF_XOSC32K_CONFIG -#define CONF_XOSC32K_CONFIG 1 -#endif - -// <h> 32kHz External Crystal Oscillator Control -// <q> Oscillator enable -// <i> Indicates whether 32kHz External Crystal Oscillator is enabled or not -// <id> xosc32k_arch_enable -#ifndef CONF_XOSC32K_ENABLE -#define CONF_XOSC32K_ENABLE 1 -#endif - -// <o> Start-Up Time -// <0x0=>62592us -// <0x1=>125092us -// <0x2=>500092us -// <0x3=>1000092us -// <0x4=>2000092us -// <0x5=>4000092us -// <0x6=>8000092us -// <id> xosc32k_arch_startup -#ifndef CONF_XOSC32K_STARTUP -#define CONF_XOSC32K_STARTUP 0x3 -#endif - -// <q> On Demand Control -// <i> Indicates whether On Demand Control is enabled or not -// <id> xosc32k_arch_ondemand -#ifndef CONF_XOSC32K_ONDEMAND -#define CONF_XOSC32K_ONDEMAND 0 -#endif - -// <q> Run in Standby -// <i> Indicates whether Run in Standby is enabled or not -// <id> xosc32k_arch_runstdby -#ifndef CONF_XOSC32K_RUNSTDBY -#define CONF_XOSC32K_RUNSTDBY 1 -#endif - -// <q> 1kHz Output Enable -// <i> Indicates whether 1kHz Output is enabled or not -// <id> xosc32k_arch_en1k -#ifndef CONF_XOSC32K_EN1K -#define CONF_XOSC32K_EN1K 1 -#endif - -// <q> 32kHz Output Enable -// <i> Indicates whether 32kHz Output is enabled or not -// <id> xosc32k_arch_en32k -#ifndef CONF_XOSC32K_EN32K -#define CONF_XOSC32K_EN32K 1 -#endif - -// <q> Clock Switch Back -// <i> Indicates whether Clock Switch Back is enabled or not -// <id> xosc32k_arch_swben -#ifndef CONF_XOSC32K_SWBEN -#define CONF_XOSC32K_SWBEN 0 -#endif - -// <q> Clock Failure Detector -// <i> Indicates whether Clock Failure Detector is enabled or not -// <id> xosc32k_arch_cfden -#ifndef CONF_XOSC32K_CFDEN -#define CONF_XOSC32K_CFDEN 0 -#endif - -// <q> Clock Failure Detector Event Out -// <i> Indicates whether Clock Failure Detector Event Out is enabled or not -// <id> xosc32k_arch_cfdeo -#ifndef CONF_XOSC32K_CFDEO -#define CONF_XOSC32K_CFDEO 0 -#endif - -// <q> Crystal connected to XIN32/XOUT32 Enable -// <i> Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not -// <id> xosc32k_arch_xtalen -#ifndef CONF_XOSC32K_XTALEN -#define CONF_XOSC32K_XTALEN 1 -#endif - -// </h> -// </e> - -// <e> 32kHz Ultra Low Power Internal Oscillator Configuration -// <i> Indicates whether configuration for OSCULP32K is enabled or not -// <id> enable_osculp32k -#ifndef CONF_OSCULP32K_CONFIG -#define CONF_OSCULP32K_CONFIG 1 -#endif - -// <h> 32kHz Ultra Low Power Internal Oscillator Control - -// <q> Oscillator Calibration Control -// <i> Indicates whether Oscillator Calibration is enabled or not -// <id> osculp32k_calib_enable -#ifndef CONF_OSCULP32K_CALIB_ENABLE -#define CONF_OSCULP32K_CALIB_ENABLE 0 -#endif - -// <o> Oscillator Calibration <0x0-0x1F> -// <id> osculp32k_calib -#ifndef CONF_OSCULP32K_CALIB -#define CONF_OSCULP32K_CALIB 0x0 -#endif - -// </h> -// </e> - -// <<< end of configuration section >>> - -#endif // HPL_OSC32KCTRL_CONFIG_H diff --git a/watch-library/config/hpl_oscctrl_config.h b/watch-library/config/hpl_oscctrl_config.h deleted file mode 100644 index ba2d42e6..00000000 --- a/watch-library/config/hpl_oscctrl_config.h +++ /dev/null @@ -1,483 +0,0 @@ -/* Auto-generated config file hpl_oscctrl_config.h */ -#ifndef HPL_OSCCTRL_CONFIG_H -#define HPL_OSCCTRL_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// <e> External Multipurpose Crystal Oscillator Configuration -// <i> Indicates whether configuration for XOSC is enabled or not -// <id> enable_xosc -#ifndef CONF_XOSC_CONFIG -#define CONF_XOSC_CONFIG 0 -#endif - -// <o> Frequency <400000-32000000> -// <i> Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator. -// <id> xosc_frequency -#ifndef CONF_XOSC_FREQUENCY -#define CONF_XOSC_FREQUENCY 400000 -#endif - -// <h> External Multipurpose Crystal Oscillator Control -// <q> Oscillator enable -// <i> Indicates whether External Multipurpose Crystal Oscillator is enabled or not -// <id> xosc_arch_enable -#ifndef CONF_XOSC_ENABLE -#define CONF_XOSC_ENABLE 0 -#endif - -// <o> Start-Up Time -// <0x0=>31us -// <0x1=>61us -// <0x2=>122us -// <0x3=>244us -// <0x4=>488us -// <0x5=>977us -// <0x6=>1953us -// <0x7=>3906us -// <0x8=>7813us -// <0x9=>15625us -// <0xA=>31250us -// <0xB=>62500us -// <0xC=>125000us -// <0xD=>250000us -// <0xE=>500000us -// <0xF=>1000000us -// <id> xosc_arch_startup -#ifndef CONF_XOSC_STARTUP -#define CONF_XOSC_STARTUP 0x0 -#endif - -// <q> Automatic Amplitude Gain Control -// <i> Indicates whether Automatic Amplitude Gain Control is enabled or not -// <id> xosc_arch_ampgc -#ifndef CONF_XOSC_AMPGC -#define CONF_XOSC_AMPGC 0 -#endif - -// <o> External Multipurpose Crystal Oscillator Gain -// <0x0=>2MHz -// <0x1=>4MHz -// <0x2=>8MHz -// <0x3=>16MHz -// <0x4=>30MHz -// <id> xosc_arch_gain -#ifndef CONF_XOSC_GAIN -#define CONF_XOSC_GAIN 0x0 -#endif - -// <q> On Demand Control -// <i> Indicates whether On Demand Control is enabled or not -// <id> xosc_arch_ondemand -#ifndef CONF_XOSC_ONDEMAND -#define CONF_XOSC_ONDEMAND 1 -#endif - -// <q> Run in Standby -// <i> Indicates whether Run in Standby is enabled or not -// <id> xosc_arch_runstdby -#ifndef CONF_XOSC_RUNSTDBY -#define CONF_XOSC_RUNSTDBY 0 -#endif - -// <q> Clock Switch Back -// <i> Indicates whether Clock Switch Back is enabled or not -// <id> xosc_arch_swben -#ifndef CONF_XOSC_SWBEN -#define CONF_XOSC_SWBEN 0 -#endif - -// <q> Clock Failure Detector -// <i> Indicates whether Clock Failure Detector is enabled or not -// <id> xosc_arch_cfden -#ifndef CONF_XOSC_CFDEN -#define CONF_XOSC_CFDEN 0 -#endif - -// <q> Clock Failure Detector Event Out -// <i> Indicates whether Clock Failure Detector Event Out is enabled or not -// <id> xosc_arch_cfdeo -#ifndef CONF_XOSC_CFDEO -#define CONF_XOSC_CFDEO 0 -#endif - -// <q> Crystal connected to XIN/XOUT Enable -// <i> Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not -// <id> xosc_arch_xtalen -#ifndef CONF_XOSC_XTALEN -#define CONF_XOSC_XTALEN 0 -#endif -//</h> -//</e> - -// <e> 16MHz Internal Oscillator Configuration -// <i> Indicates whether configuration for OSC8M is enabled or not -// <id> enable_osc16m -#ifndef CONF_OSC16M_CONFIG -#define CONF_OSC16M_CONFIG 1 -#endif - -// <h> 16MHz Internal Oscillator Control -// <q> Enable -// <i> Indicates whether 16MHz Internal Oscillator is enabled or not -// <id> osc16m_arch_enable -#ifndef CONF_OSC16M_ENABLE -#define CONF_OSC16M_ENABLE 1 -#endif - -// <q> On Demand Control -// <i> Indicates whether On Demand Control is enabled or not -// <id> osc16m_arch_ondemand -#ifndef CONF_OSC16M_ONDEMAND -#define CONF_OSC16M_ONDEMAND 1 -#endif - -// <q> Run in Standby -// <i> Indicates whether Run in Standby is enabled or not -// <id> osc16m_arch_runstdby -#ifndef CONF_OSC16M_RUNSTDBY -#define CONF_OSC16M_RUNSTDBY 0 -#endif - -// <y> Oscillator Frequency Selection(Mhz) -// <OSCCTRL_OSC16MCTRL_FSEL_4_Val"> 4 -// <OSCCTRL_OSC16MCTRL_FSEL_8_Val"> 8 -// <OSCCTRL_OSC16MCTRL_FSEL_12_Val"> 12 -// <OSCCTRL_OSC16MCTRL_FSEL_16_Val"> 16 -// <i> This defines the oscillator frequency (Mhz) -// <id> osc16m_freq -#ifndef CONF_OSC16M_FSEL -#define CONF_OSC16M_FSEL OSCCTRL_OSC16MCTRL_FSEL_4_Val -#endif - -// <q> Oscillator Calibration Control -// <i> Indicates whether Oscillator Calibration is enabled or not -// <id> osc16m_arch_calib_enable -#ifndef CONF_OSC16M_CALIB_ENABLE -#define CONF_OSC16M_CALIB_ENABLE 0 -#endif - -// <o> 4MHz Frequency Calibration <0x0-0x3F> -// <id> osc16m_arch_4m_fcal -#ifndef CONF_OSC16M_FCAL -#define CONF_OSC16M_4M_FCAL 0 -#endif - -// <o> 4MHz Temperature Calibration <0x0-0x3F> -// <id> osc16m_arch_4m_tcal -#ifndef CONF_OSC16M_TCAL -#define CONF_OSC16M_4M_TCAL 0 -#endif - -// <o> 8MHz Frequency Calibration <0x0-0x3F> -// <id> osc16m_arch_8m_fcal -#ifndef CONF_OSC16M_FCAL -#define CONF_OSC16M_8M_FCAL 0 -#endif - -// <o> 8MHz Temperature Calibration <0x0-0x3F> -// <id> osc16m_arch_8m_tcal -#ifndef CONF_OSC16M_TCAL -#define CONF_OSC16M_8M_TCAL 0 -#endif - -// <o> 12MHz Frequency Calibration <0x0-0x3F> -// <id> osc16m_arch_12m_fcal -#ifndef CONF_OSC16M_FCAL -#define CONF_OSC16M_12M_FCAL 0 -#endif - -// <o> 12MHz Temperature Calibration <0x0-0x3F> -// <id> osc16m_arch_12m_tcal -#ifndef CONF_OSC16M_TCAL -#define CONF_OSC16M_12M_TCAL 0 -#endif - -// <o> 16MHz Frequency Calibration <0x0-0x3F> -// <id> osc16m_arch_fcal -#ifndef CONF_OSC16M_FCAL -#define CONF_OSC16M_16M_FCAL 0 -#endif - -// <o> 16MHz Temperature Calibration <0x0-0x3F> -// <id> osc16m_arch_16m_tcal -#ifndef CONF_OSC16M_TCAL -#define CONF_OSC16M_16M_TCAL 0 -#endif -//</h> -//</e> - -// <e> DFLL Configuration -// <i> Indicates whether configuration for DFLL is enabled or not -// <id> enable_dfll48m -#ifndef CONF_DFLL_CONFIG -#define CONF_DFLL_CONFIG 0 -#endif - -// <y> Reference Clock Source -// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 -// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 -// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 -// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 -// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 -// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 -// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 -// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 -// <i> Select the clock source. -// <id> dfll48m_ref_clock -#ifndef CONF_DFLL_GCLK -#define CONF_DFLL_GCLK GCLK_PCHCTRL_GEN_GCLK3_Val -#endif - -// <h> Digital Frequency Locked Loop Control -// <q> DFLL Enable -// <i> Indicates whether DFLL is enabled or not -// <id> dfll48m_arch_enable -#ifndef CONF_DFLL_ENABLE -#define CONF_DFLL_ENABLE 0 -#endif - -// <q> Wait Lock -// <i> Indicates whether Wait Lock is enabled or not -// <id> dfll_arch_waitlock -#ifndef CONF_DFLL_WAITLOCK -#define CONF_DFLL_WAITLOCK 0 -#endif - -// <q> Bypass Coarse Lock -// <i> Indicates whether Bypass Coarse Lock is enabled or not -// <id> dfll_arch_bplckc -#ifndef CONF_DFLL_BPLCKC -#define CONF_DFLL_BPLCKC 0 -#endif - -// <q> Quick Lock Disable -// <i> Indicates whether Quick Lock Disable is enabled or not -// <id> dfll_arch_qldis -#ifndef CONF_DFLL_QLDIS -#define CONF_DFLL_QLDIS 0 -#endif - -// <q> Chill Cycle Disable -// <i> Indicates whether Chill Cycle Disable is enabled or not -// <id> dfll_arch_ccdis -#ifndef CONF_DFLL_CCDIS -#define CONF_DFLL_CCDIS 0 -#endif - -// <q> On Demand Control -// <i> Indicates whether On Demand Control is enabled or not -// <id> dfll_arch_ondemand -#ifndef CONF_DFLL_ONDEMAND -#define CONF_DFLL_ONDEMAND 1 -#endif - -// <q> Run in Standby -// <i> Indicates whether Run in Standby is enabled or not -// <id> dfll_arch_runstdby -#ifndef CONF_DFLL_RUNSTDBY -#define CONF_DFLL_RUNSTDBY 0 -#endif - -// <q> USB Clock Recovery Mode -// <i> Indicates whether USB Clock Recovery Mode is enabled or not -// <id> dfll_arch_usbcrm -#ifndef CONF_DFLL_USBCRM -#define CONF_DFLL_USBCRM 0 -#endif - -// <q> Lose Lock After Wake -// <i> Indicates whether Lose Lock After Wake is enabled or not -// <id> dfll_arch_llaw -#ifndef CONF_DFLL_LLAW -#define CONF_DFLL_LLAW 0 -#endif - -// <q> Stable DFLL Frequency -// <i> Indicates whether Stable DFLL Frequency is enabled or not -// <id> dfll_arch_stable -#ifndef CONF_DFLL_STABLE -#define CONF_DFLL_STABLE 0 -#endif - -// <o> Operating Mode Selection -// <0=>Open Loop Mode -// <1=>Closed Loop Mode -// <id> dfll48m_mode -#ifndef CONF_DFLL_MODE -#define CONF_DFLL_MODE 0 -#endif - -// <o> Coarse Maximum Step <0x0-0x1F> -// <id> dfll_arch_cstep -#ifndef CONF_DFLL_CSTEP -#define CONF_DFLL_CSTEP 1 -#endif - -// <o> Fine Maximum Step <0x0-0x3FF> -// <id> dfll_arch_fstep -#ifndef CONF_DFLL_FSTEP -#define CONF_DFLL_FSTEP 1 -#endif - -// <o> DFLL Multiply Factor <0x0-0xFFFF> -// <id> dfll48m_mul -#ifndef CONF_DFLL_MUL -#define CONF_DFLL_MUL 0 -#endif - -// <e> DFLL Calibration Overwrite -// <i> Indicates whether Overwrite Calibration value of DFLL -// <id> dfll_arch_calibration -#ifndef CONF_DFLL_OVERWRITE_CALIBRATION -#define CONF_DFLL_OVERWRITE_CALIBRATION 0 -#endif - -// <o> Coarse Value <0x0-0x3F> -// <id> dfll_arch_coarse -#ifndef CONF_DFLL_COARSE -#define CONF_DFLL_COARSE (0x1f / 4) -#endif - -// <o> Fine Value <0x0-0x3FF> -// <id> dfll_arch_fine -#ifndef CONF_DFLL_FINE -#define CONF_DFLL_FINE (0x200) -#endif - -//</e> - -//</h> - -//</e> - -// <e> DPLL Configuration -// <i> Indicates whether configuration for DPLL is enabled or not -// <id> enable_fdpll96m -#ifndef CONF_DPLL_CONFIG -#define CONF_DPLL_CONFIG 0 -#endif - -// <y> Reference Clock Source -// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) -// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC) -// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 -// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 -// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 -// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 -// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 -// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 -// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 -// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 -// <i> Select the clock source. -// <id> fdpll96m_ref_clock -#ifndef CONF_DPLL_GCLK -#define CONF_DPLL_GCLK GCLK_GENCTRL_SRC_XOSC32K - -#endif - -// <h> Digital Phase Locked Loop Control -// <q> Enable -// <i> Indicates whether Digital Phase Locked Loop is enabled or not -// <id> fdpll96m_arch_enable -#ifndef CONF_DPLL_ENABLE -#define CONF_DPLL_ENABLE 0 -#endif - -// <q> On Demand Control -// <i> Indicates whether On Demand Control is enabled or not -// <id> fdpll96m_arch_ondemand -#ifndef CONF_DPLL_ONDEMAND -#define CONF_DPLL_ONDEMAND 1 -#endif - -// <q> Run in Standby -// <i> Indicates whether Run in Standby is enabled or not -// <id> fdpll96m_arch_runstdby -#ifndef CONF_DPLL_RUNSTDBY -#define CONF_DPLL_RUNSTDBY 0 -#endif - -// <o> Loop Divider Ratio Fractional Part <0x0-0xF> -// <id> fdpll96m_ldrfrac -#ifndef CONF_DPLL_LDRFRAC -#define CONF_DPLL_LDRFRAC 0xd -#endif - -// <o> Loop Divider Ratio Integer Part <0x0-0xFFF> -// <id> fdpll96m_ldr -#ifndef CONF_DPLL_LDR -#define CONF_DPLL_LDR 0x5b7 -#endif - -// <o> Clock Divider <0x0-0x3FF> -// <id> fdpll96m_clock_div -#ifndef CONF_DPLL_DIV -#define CONF_DPLL_DIV 0 -#endif - -// <q> Lock Bypass -// <i> Indicates whether Lock Bypass is enabled or not -// <id> fdpll96m_arch_lbypass -#ifndef CONF_DPLL_LBYPASS -#define CONF_DPLL_LBYPASS 0 -#endif - -// <o> Lock Time -// <0=>No time-out, automatic lock -// <4=>The Time-out if no lock within 8 ms -// <5=>The Time-out if no lock within 9 ms -// <6=>The Time-out if no lock within 10 ms -// <7=>The Time-out if no lock within 11 ms -// <id> fdpll96m_arch_ltime -#ifndef CONF_DPLL_LTIME -#define CONF_DPLL_LTIME 0 -#endif - -// <o> Reference Clock Selection -// <0=>XOSC32K clock reference -// <1=>XOSC clock reference -// <2=>GCLK clock reference -// <id> fdpll96m_arch_refclk -#ifndef CONF_DPLL_REFCLK -#define CONF_DPLL_REFCLK 0 -#endif - -// <q> Wake Up Fast -// <i> Indicates whether Wake Up Fast is enabled or not -// <id> fdpll96m_arch_wuf -#ifndef CONF_DPLL_WUF -#define CONF_DPLL_WUF 0 -#endif - -// <q> Low-Power Enable -// <i> Indicates whether Low-Power Enable is enabled or not -// <id> fdpll96m_arch_lpen -#ifndef CONF_DPLL_LPEN -#define CONF_DPLL_LPEN 0 -#endif - -// <o> Reference Clock Selection -// <0=>Default filter mode -// <1=>Low bandwidth filter -// <2=>High bandwidth filter -// <3=>High damping filter -// <id> fdpll96m_arch_filter -#ifndef CONF_DPLL_FILTER -#define CONF_DPLL_FILTER 0 -#endif - -// <y> Output Clock Prescaler -// <OSCCTRL_DPLLPRESC_PRESC_DIV1_Val"> 1 -// <OSCCTRL_DPLLPRESC_PRESC_DIV2_Val"> 2 -// <OSCCTRL_DPLLPRESC_PRESC_DIV4_Val"> 4 -// <id> fdpll96m_presc -#ifndef CONF_DPLL_PRESC -#define CONF_DPLL_PRESC OSCCTRL_DPLLPRESC_PRESC_DIV1_Val -#endif -//</h> -//</e> - -// <<< end of configuration section >>> - -#endif // HPL_OSCCTRL_CONFIG_H diff --git a/watch-library/config/hpl_port_config.h b/watch-library/config/hpl_port_config.h deleted file mode 100644 index 1efce33e..00000000 --- a/watch-library/config/hpl_port_config.h +++ /dev/null @@ -1,284 +0,0 @@ -/* Auto-generated config file hpl_port_config.h */ -#ifndef HPL_PORT_CONFIG_H -#define HPL_PORT_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// <e> PORT Input Event 0 configuration -// <id> enable_port_input_event_0 -#ifndef CONF_PORT_EVCTRL_PORT_0 -#define CONF_PORT_EVCTRL_PORT_0 0 -#endif - -// <h> PORT Input Event 0 configuration on PORT A - -// <q> PORTA Input Event 0 Enable -// <i> The event action will be triggered on any incoming event if PORT A Input Event 0 configuration is enabled -// <id> porta_input_event_enable_0 -#ifndef CONF_PORTA_EVCTRL_PORTEI_0 -#define CONF_PORTA_EVCTRL_PORTEI_0 0x0 -#endif - -// <o> PORTA Event 0 Pin Identifier <0x00-0x1F> -// <i> These bits define the I/O pin from port A on which the event action will be performed -// <id> porta_event_pin_identifier_0 -#ifndef CONF_PORTA_EVCTRL_PID_0 -#define CONF_PORTA_EVCTRL_PID_0 0x0 -#endif - -// <o> PORTA Event 0 Action -// <0=> Output register of pin will be set to level of event -// <1=> Set output register of pin on event -// <2=> Clear output register of pin on event -// <3=> Toggle output register of pin on event -// <i> These bits define the event action the PORT A will perform on event input 0 -// <id> porta_event_action_0 -#ifndef CONF_PORTA_EVCTRL_EVACT_0 -#define CONF_PORTA_EVCTRL_EVACT_0 0 -#endif - -// </h> -// <h> PORT Input Event 0 configuration on PORT B - -// <q> PORTB Input Event 0 Enable -// <i> The event action will be triggered on any incoming event if PORT B Input Event 0 configuration is enabled -// <id> portb_input_event_enable_0 -#ifndef CONF_PORTB_EVCTRL_PORTEI_0 -#define CONF_PORTB_EVCTRL_PORTEI_0 0x0 -#endif - -// <o> PORTB Event 0 Pin Identifier <0x00-0x1F> -// <i> These bits define the I/O pin from port B on which the event action will be performed -// <id> portb_event_pin_identifier_0 -#ifndef CONF_PORTB_EVCTRL_PID_0 -#define CONF_PORTB_EVCTRL_PID_0 0x0 -#endif - -// <o> PORTB Event 0 Action -// <0=> Output register of pin will be set to level of event -// <1=> Set output register of pin on event -// <2=> Clear output register of pin on event -// <3=> Toggle output register of pin on event -// <i> These bits define the event action the PORT B will perform on event input 0 -// <id> portb_event_action_0 -#ifndef CONF_PORTB_EVCTRL_EVACT_0 -#define CONF_PORTB_EVCTRL_EVACT_0 0 -#endif - -// </h> - -// </e> - -// <e> PORT Input Event 1 configuration -// <id> enable_port_input_event_1 -#ifndef CONF_PORT_EVCTRL_PORT_1 -#define CONF_PORT_EVCTRL_PORT_1 0 -#endif - -// <h> PORT Input Event 1 configuration on PORT A - -// <q> PORTA Input Event 1 Enable -// <i> The event action will be triggered on any incoming event if PORT A Input Event 1 configuration is enabled -// <id> porta_input_event_enable_1 -#ifndef CONF_PORTA_EVCTRL_PORTEI_1 -#define CONF_PORTA_EVCTRL_PORTEI_1 0x0 -#endif - -// <o> PORTA Event 1 Pin Identifier <0x00-0x1F> -// <i> These bits define the I/O pin from port A on which the event action will be performed -// <id> porta_event_pin_identifier_1 -#ifndef CONF_PORTA_EVCTRL_PID_1 -#define CONF_PORTA_EVCTRL_PID_1 0x0 -#endif - -// <o> PORTA Event 1 Action -// <0=> Output register of pin will be set to level of event -// <1=> Set output register of pin on event -// <2=> Clear output register of pin on event -// <3=> Toggle output register of pin on event -// <i> These bits define the event action the PORT A will perform on event input 1 -// <id> porta_event_action_1 -#ifndef CONF_PORTA_EVCTRL_EVACT_1 -#define CONF_PORTA_EVCTRL_EVACT_1 0 -#endif - -// </h> -// <h> PORT Input Event 1 configuration on PORT B - -// <q> PORTB Input Event 1 Enable -// <i> The event action will be triggered on any incoming event if PORT B Input Event 1 configuration is enabled -// <id> portb_input_event_enable_1 -#ifndef CONF_PORTB_EVCTRL_PORTEI_1 -#define CONF_PORTB_EVCTRL_PORTEI_1 0x0 -#endif - -// <o> PORTB Event 1 Pin Identifier <0x00-0x1F> -// <i> These bits define the I/O pin from port B on which the event action will be performed -// <id> portb_event_pin_identifier_1 -#ifndef CONF_PORTB_EVCTRL_PID_1 -#define CONF_PORTB_EVCTRL_PID_1 0x0 -#endif - -// <o> PORTB Event 1 Action -// <0=> Output register of pin will be set to level of event -// <1=> Set output register of pin on event -// <2=> Clear output register of pin on event -// <3=> Toggle output register of pin on event -// <i> These bits define the event action the PORT B will perform on event input 1 -// <id> portb_event_action_1 -#ifndef CONF_PORTB_EVCTRL_EVACT_1 -#define CONF_PORTB_EVCTRL_EVACT_1 0 -#endif - -// </h> - -// </e> - -// <e> PORT Input Event 2 configuration -// <id> enable_port_input_event_2 -#ifndef CONF_PORT_EVCTRL_PORT_2 -#define CONF_PORT_EVCTRL_PORT_2 0 -#endif - -// <h> PORT Input Event 2 configuration on PORT A - -// <q> PORTA Input Event 2 Enable -// <i> The event action will be triggered on any incoming event if PORT A Input Event 2 configuration is enabled -// <id> porta_input_event_enable_2 -#ifndef CONF_PORTA_EVCTRL_PORTEI_2 -#define CONF_PORTA_EVCTRL_PORTEI_2 0x0 -#endif - -// <o> PORTA Event 2 Pin Identifier <0x00-0x1F> -// <i> These bits define the I/O pin from port A on which the event action will be performed -// <id> porta_event_pin_identifier_2 -#ifndef CONF_PORTA_EVCTRL_PID_2 -#define CONF_PORTA_EVCTRL_PID_2 0x0 -#endif - -// <o> PORTA Event 2 Action -// <0=> Output register of pin will be set to level of event -// <1=> Set output register of pin on event -// <2=> Clear output register of pin on event -// <3=> Toggle output register of pin on event -// <i> These bits define the event action the PORT A will perform on event input 2 -// <id> porta_event_action_2 -#ifndef CONF_PORTA_EVCTRL_EVACT_2 -#define CONF_PORTA_EVCTRL_EVACT_2 0 -#endif - -// </h> -// <h> PORT Input Event 2 configuration on PORT B - -// <q> PORTB Input Event 2 Enable -// <i> The event action will be triggered on any incoming event if PORT B Input Event 2 configuration is enabled -// <id> portb_input_event_enable_2 -#ifndef CONF_PORTB_EVCTRL_PORTEI_2 -#define CONF_PORTB_EVCTRL_PORTEI_2 0x0 -#endif - -// <o> PORTB Event 2 Pin Identifier <0x00-0x1F> -// <i> These bits define the I/O pin from port B on which the event action will be performed -// <id> portb_event_pin_identifier_2 -#ifndef CONF_PORTB_EVCTRL_PID_2 -#define CONF_PORTB_EVCTRL_PID_2 0x0 -#endif - -// <o> PORTB Event 2 Action -// <0=> Output register of pin will be set to level of event -// <1=> Set output register of pin on event -// <2=> Clear output register of pin on event -// <3=> Toggle output register of pin on event -// <i> These bits define the event action the PORT B will perform on event input 2 -// <id> portb_event_action_2 -#ifndef CONF_PORTB_EVCTRL_EVACT_2 -#define CONF_PORTB_EVCTRL_EVACT_2 0 -#endif - -// </h> - -// </e> - -// <e> PORT Input Event 3 configuration -// <id> enable_port_input_event_3 -#ifndef CONF_PORT_EVCTRL_PORT_3 -#define CONF_PORT_EVCTRL_PORT_3 0 -#endif - -// <h> PORT Input Event 3 configuration on PORT A - -// <q> PORTA Input Event 3 Enable -// <i> The event action will be triggered on any incoming event if PORT A Input Event 3 configuration is enabled -// <id> porta_input_event_enable_3 -#ifndef CONF_PORTA_EVCTRL_PORTEI_3 -#define CONF_PORTA_EVCTRL_PORTEI_3 0x0 -#endif - -// <o> PORTA Event 3 Pin Identifier <0x00-0x1F> -// <i> These bits define the I/O pin from port A on which the event action will be performed -// <id> porta_event_pin_identifier_3 -#ifndef CONF_PORTA_EVCTRL_PID_3 -#define CONF_PORTA_EVCTRL_PID_3 0x0 -#endif - -// <o> PORTA Event 3 Action -// <0=> Output register of pin will be set to level of event -// <1=> Set output register of pin on event -// <2=> Clear output register of pin on event -// <3=> Toggle output register of pin on event -// <i> These bits define the event action the PORT A will perform on event input 3 -// <id> porta_event_action_3 -#ifndef CONF_PORTA_EVCTRL_EVACT_3 -#define CONF_PORTA_EVCTRL_EVACT_3 0 -#endif - -// </h> -// <h> PORT Input Event 3 configuration on PORT B - -// <q> PORTB Input Event 3 Enable -// <i> The event action will be triggered on any incoming event if PORT B Input Event 3 configuration is enabled -// <id> portb_input_event_enable_3 -#ifndef CONF_PORTB_EVCTRL_PORTEI_3 -#define CONF_PORTB_EVCTRL_PORTEI_3 0x0 -#endif - -// <o> PORTB Event 3 Pin Identifier <0x00-0x1F> -// <i> These bits define the I/O pin from port B on which the event action will be performed -// <id> portb_event_pin_identifier_3 -#ifndef CONF_PORTB_EVCTRL_PID_3 -#define CONF_PORTB_EVCTRL_PID_3 0x0 -#endif - -// <o> PORTB Event 3 Action -// <0=> Output register of pin will be set to level of event -// <1=> Set output register of pin on event -// <2=> Clear output register of pin on event -// <3=> Toggle output register of pin on event -// <i> These bits define the event action the PORT B will perform on event input 3 -// <id> portb_event_action_3 -#ifndef CONF_PORTB_EVCTRL_EVACT_3 -#define CONF_PORTB_EVCTRL_EVACT_3 0 -#endif - -// </h> - -// </e> - -#define CONF_PORTA_EVCTRL \ - (0 | PORT_EVCTRL_EVACT0(CONF_PORTA_EVCTRL_EVACT_0) | CONF_PORTA_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \ - | PORT_EVCTRL_PID0(CONF_PORTA_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTA_EVCTRL_EVACT_1) \ - | CONF_PORTA_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTA_EVCTRL_PID_1) \ - | PORT_EVCTRL_EVACT2(CONF_PORTA_EVCTRL_EVACT_2) | CONF_PORTA_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ - | PORT_EVCTRL_PID2(CONF_PORTA_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTA_EVCTRL_EVACT_3) \ - | CONF_PORTA_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTA_EVCTRL_PID_3)) -#define CONF_PORTB_EVCTRL \ - (0 | PORT_EVCTRL_EVACT0(CONF_PORTB_EVCTRL_EVACT_0) | CONF_PORTB_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \ - | PORT_EVCTRL_PID0(CONF_PORTB_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTB_EVCTRL_EVACT_1) \ - | CONF_PORTB_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTB_EVCTRL_PID_1) \ - | PORT_EVCTRL_EVACT2(CONF_PORTB_EVCTRL_EVACT_2) | CONF_PORTB_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ - | PORT_EVCTRL_PID2(CONF_PORTB_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTB_EVCTRL_EVACT_3) \ - | CONF_PORTB_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTB_EVCTRL_PID_3)) - -// <<< end of configuration section >>> - -#endif // HPL_PORT_CONFIG_H diff --git a/watch-library/config/hpl_rtc_config.h b/watch-library/config/hpl_rtc_config.h deleted file mode 100644 index 9085ca37..00000000 --- a/watch-library/config/hpl_rtc_config.h +++ /dev/null @@ -1,318 +0,0 @@ -/* Auto-generated config file hpl_rtc_config.h */ -#ifndef HPL_RTC_CONFIG_H -#define HPL_RTC_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// <h> Basic settings - -#ifndef CONF_RTC_ENABLE -#define CONF_RTC_ENABLE 1 -#endif - -// <q> Force reset RTC on initialization -// <i> Force RTC to reset on initialization. -// <i> Note that the previous power down data in RTC is lost if it's enabled. -// <id> rtc_arch_init_reset -#ifndef CONF_RTC_INIT_RESET -#define CONF_RTC_INIT_RESET 0 -#endif - -// <o> Prescaler configuration -// <0x0=>OFF(Peripheral clock divided by 1) -// <0x1=>Peripheral clock divided by 1 -// <0x2=>Peripheral clock divided by 2 -// <0x3=>Peripheral clock divided by 4 -// <0x4=>Peripheral clock divided by 8 -// <0x5=>Peripheral clock divided by 16 -// <0x6=>Peripheral clock divided by 32 -// <0x7=>Peripheral clock divided by 64 -// <0x8=>Peripheral clock divided by 128 -// <0x9=>Peripheral clock divided by 256 -// <0xA=>Peripheral clock divided by 512 -// <0xB=>Peripheral clock divided by 1024 -// <i> These bits define the RTC clock relative to the peripheral clock -// <id> rtc_arch_prescaler -#ifndef CONF_RTC_PRESCALER - -#define CONF_RTC_PRESCALER 0xb - -#endif - -#ifndef CONF_RTC_COMP_VAL - -#define CONF_RTC_COMP_VAL 0 - -#endif - -// <e> RTC Tamper Input 0 settings -// <id> tamper_input_0_settings -#ifndef CONF_TAMPER_INPUT_0_SETTINGS -#define CONF_TAMPER_INPUT_0_SETTINGS 0 -#endif - -// <q> Tamper Level Settings -// <i> Indicates Tamper input 0 level -// <id> tamper_level_0 -#ifndef CONF_RTC_TAMP_LVL_0 -#define CONF_RTC_TAMP_LVL_0 0 -#endif - -// <o> RTC Tamper Input Action -// <0x0=>OFF(Disabled) -// <0x1=>Wake and Set Tamper Flag -// <0x2=>Capture Timestamp and Set Tamper Flag -// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured. -// <i> These bits define the RTC Tamper Input Action to be performed -// <id> rtc_tamper_input_action_0 -#ifndef CONF_RTC_TAMPER_INACT_0 -#define CONF_RTC_TAMPER_INACT_0 0 -#endif - -// <q> Debounce Enable for Tamper Input -// <i> Indicates Debounce should be enabled for Tamper input 0 -// <id> tamper_debounce_enable_0 -#ifndef CONF_RTC_TAMP_DEBNC_0 -#define CONF_RTC_TAMP_DEBNC_0 0 -#endif - -// </e> - -// <e> RTC Tamper Input 1 settings -// <id> tamper_input_1_settings -#ifndef CONF_TAMPER_INPUT_1_SETTINGS -#define CONF_TAMPER_INPUT_1_SETTINGS 0 -#endif - -// <q> Tamper Level Settings -// <i> Indicates Tamper input 1 level -// <id> tamper_level_1 -#ifndef CONF_RTC_TAMP_LVL_1 -#define CONF_RTC_TAMP_LVL_1 0 -#endif - -// <o> RTC Tamper Input Action -// <0x0=>OFF(Disabled) -// <0x1=>Wake and Set Tamper Flag -// <0x2=>Capture Timestamp and Set Tamper Flag -// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured. -// <i> These bits define the RTC Tamper Input Action to be performed -// <id> rtc_tamper_input_action_1 -#ifndef CONF_RTC_TAMPER_INACT_1 -#define CONF_RTC_TAMPER_INACT_1 0 -#endif - -// <q> Debounce Enable for Tamper Input -// <i> Indicates Debounce should be enabled for Tamper input 1 -// <id> tamper_debounce_enable_1 -#ifndef CONF_RTC_TAMP_DEBNC_1 -#define CONF_RTC_TAMP_DEBNC_1 0 -#endif - -// </e> - -// <e> RTC Tamper Input 2 settings -// <id> tamper_input_2_settings -#ifndef CONF_TAMPER_INPUT_2_SETTINGS -#define CONF_TAMPER_INPUT_2_SETTINGS 0 -#endif - -// <q> Tamper Level Settings -// <i> Indicates Tamper input 2 level -// <id> tamper_level_2 -#ifndef CONF_RTC_TAMP_LVL_2 -#define CONF_RTC_TAMP_LVL_2 0 -#endif - -// <o> RTC Tamper Input Action -// <0x0=>OFF(Disabled) -// <0x1=>Wake and Set Tamper Flag -// <0x2=>Capture Timestamp and Set Tamper Flag -// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured. -// <i> These bits define the RTC Tamper Input Action to be performed -// <id> rtc_tamper_input_action_2 -#ifndef CONF_RTC_TAMPER_INACT_2 -#define CONF_RTC_TAMPER_INACT_2 0 -#endif - -// <q> Debounce Enable for Tamper Input -// <i> Indicates Debounce should be enabled for Tamper input 2 -// <id> tamper_debounce_enable_2 -#ifndef CONF_RTC_TAMP_DEBNC_2 -#define CONF_RTC_TAMP_DEBNC_2 0 -#endif - -// </e> - -// <e> RTC Tamper Input 3 settings -// <id> tamper_input_3_settings -#ifndef CONF_TAMPER_INPUT_3_SETTINGS -#define CONF_TAMPER_INPUT_3_SETTINGS 0 -#endif - -// <q> Tamper Level Settings -// <i> Indicates Tamper input 3 level -// <id> tamper_level_3 -#ifndef CONF_RTC_TAMP_LVL_3 -#define CONF_RTC_TAMP_LVL_3 0 -#endif - -// <o> RTC Tamper Input Action -// <0x0=>OFF(Disabled) -// <0x1=>Wake and Set Tamper Flag -// <0x2=>Capture Timestamp and Set Tamper Flag -// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured. -// <i> These bits define the RTC Tamper Input Action to be performed -// <id> rtc_tamper_input_action_3 -#ifndef CONF_RTC_TAMPER_INACT_3 -#define CONF_RTC_TAMPER_INACT_3 0 -#endif - -// <q> Debounce Enable for Tamper Input -// <i> Indicates Debounce should be enabled for Tamper input 3 -// <id> tamper_debounce_enable_3 -#ifndef CONF_RTC_TAMP_DEBNC_3 -#define CONF_RTC_TAMP_DEBNC_3 0 -#endif - -// </e> - -// <e> RTC Tamper Input 4 settings -// <id> tamper_input_4_settings -#ifndef CONF_TAMPER_INPUT_4_SETTINGS -#define CONF_TAMPER_INPUT_4_SETTINGS 0 -#endif - -// <q> Tamper Level Settings -// <i> Indicates Tamper input 4 level -// <id> tamper_level_4 -#ifndef CONF_RTC_TAMP_LVL_4 -#define CONF_RTC_TAMP_LVL_4 0 -#endif - -// <o> RTC Tamper Input Action -// <0x0=>OFF(Disabled) -// <0x1=>Wake and Set Tamper Flag -// <0x2=>Capture Timestamp and Set Tamper Flag -// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured. -// <i> These bits define the RTC Tamper Input Action to be performed -// <id> rtc_tamper_input_action_4 -#ifndef CONF_RTC_TAMPER_INACT_4 -#define CONF_RTC_TAMPER_INACT_4 0 -#endif - -// <q> Debounce Enable for Tamper Input -// <i> Indicates Debounce should be enabled for Tamper input 4 -// <id> tamper_debounce_enable_4 -#ifndef CONF_RTC_TAMP_DEBNC_4 -#define CONF_RTC_TAMP_DEBNC_4 0 -#endif - -// </e> - -// <o> RTC Tamper Active Layer Frequency Prescalar -// <0x0=>DIV2 CLK_RTC_OUT is CLK_RTC /2 -// <0x1=>DIV4 CLK_RTC_OUT is CLK_RTC /4 -// <0x2=>DIV8 CLK_RTC_OUT is CLK_RTC /8 -// <0x3=>DIV16 CLK_RTC_OUT is CLK_RTC /16 -// <0x4=>DIV32 CLK_RTC_OUT is CLK_RTC /32 -// <0x5=>DIV64 CLK_RTC_OUT is CLK_RTC /64 -// <0x6=>DIV128 CLK_RTC_OUT is CLK_RTC /128 -// <0x7=>DIV256 CLK_RTC_OUT is CLK_RTC /256 -// <i> These bits define the RTC Tamper Active Layer Frequecny Prescalar -// <id> rtc_tamper_active_layer_frequency_prescalar -#ifndef CONF_RTC_TAMP_ACT_LAYER_FREQ_PRES -#define CONF_RTC_TAMP_ACT_LAYER_FREQ_PRES 0 -#endif - -// <o> RTC Tamper Debounce Frequency Prescalar -// <0x0=>DIV2 CLK_RTC_DEB is CLK_RTC /2 -// <0x1=>DIV4 CLK_RTC_DEB is CLK_RTC /4 -// <0x2=>DIV8 CLK_RTC_DEB is CLK_RTC /8 -// <0x3=>DIV16 CLK_RTC_DEB is CLK_RTC /16 -// <0x4=>DIV32 CLK_RTC_DEB is CLK_RTC /32 -// <0x5=>DIV64 CLK_RTC_DEB is CLK_RTC /64 -// <0x6=>DIV128 CLK_RTC_DEB is CLK_RTC /128 -// <0x7=>DIV256 CLK_RTC_DEB is CLK_RTC /256 -// <i> These bits define the RTC Debounce Frequency Prescalar -// <id> rtc_tamper_debounce_frequency_prescalar -#ifndef CONF_RTC_TAMP_DEBF_PRES -#define CONF_RTC_TAMP_DEBF_PRES 0 -#endif - -// <e> Event control -// <id> rtc_event_control -#ifndef CONF_RTC_EVENT_CONTROL_ENABLE -#define CONF_RTC_EVENT_CONTROL_ENABLE 0 -#endif - -// <q> Periodic Interval 0 Event Output -// <i> This bit indicates whether Periodic interval 0 event is enabled and will be generated -// <id> rtc_pereo0 -#ifndef CONF_RTC_PEREO0 -#define CONF_RTC_PEREO0 0 -#endif -// <q> Periodic Interval 1 Event Output -// <i> This bit indicates whether Periodic interval 1 event is enabled and will be generated -// <id> rtc_pereo1 -#ifndef CONF_RTC_PEREO1 -#define CONF_RTC_PEREO1 0 -#endif -// <q> Periodic Interval 2 Event Output -// <i> This bit indicates whether Periodic interval 2 event is enabled and will be generated -// <id> rtc_pereo2 -#ifndef CONF_RTC_PEREO2 -#define CONF_RTC_PEREO2 0 -#endif -// <q> Periodic Interval 3 Event Output -// <i> This bit indicates whether Periodic interval 3 event is enabled and will be generated -// <id> rtc_pereo3 -#ifndef CONF_RTC_PEREO3 -#define CONF_RTC_PEREO3 0 -#endif -// <q> Periodic Interval 4 Event Output -// <i> This bit indicates whether Periodic interval 4 event is enabled and will be generated -// <id> rtc_pereo4 -#ifndef CONF_RTC_PEREO4 -#define CONF_RTC_PEREO4 0 -#endif -// <q> Periodic Interval 5 Event Output -// <i> This bit indicates whether Periodic interval 5 event is enabled and will be generated -// <id> rtc_pereo5 -#ifndef CONF_RTC_PEREO5 -#define CONF_RTC_PEREO5 0 -#endif -// <q> Periodic Interval 6 Event Output -// <i> This bit indicates whether Periodic interval 6 event is enabled and will be generated -// <id> rtc_pereo6 -#ifndef CONF_RTC_PEREO6 -#define CONF_RTC_PEREO6 0 -#endif -// <q> Periodic Interval 7 Event Output -// <i> This bit indicates whether Periodic interval 7 event is enabled and will be generated -// <id> rtc_pereo7 -#ifndef CONF_RTC_PEREO7 -#define CONF_RTC_PEREO7 0 -#endif - -// <q> Compare 0 Event Output -// <i> This bit indicates whether Compare O event is enabled and will be generated -// <id> rtc_cmpeo0 -#ifndef CONF_RTC_COMPE0 -#define CONF_RTC_COMPE0 0 -#endif - -// <q> Overflow Event Output -// <i> This bit indicates whether Overflow event is enabled and will be generated -// <id> rtc_ovfeo -#ifndef CONF_RTC_OVFEO -#define CONF_RTC_OVFEO 0 -#endif - -// </e> - -// </h> - -// <<< end of configuration section >>> - -#endif // HPL_RTC_CONFIG_H diff --git a/watch-library/config/hpl_sercom_config.h b/watch-library/config/hpl_sercom_config.h deleted file mode 100644 index 6df4b08e..00000000 --- a/watch-library/config/hpl_sercom_config.h +++ /dev/null @@ -1,303 +0,0 @@ -/* Auto-generated config file hpl_sercom_config.h */ -#ifndef HPL_SERCOM_CONFIG_H -#define HPL_SERCOM_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -#include <peripheral_clk_config.h> - -#ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER -#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2) -#endif - -#ifndef CONF_SERCOM_1_I2CM_ENABLE -#define CONF_SERCOM_1_I2CM_ENABLE 1 -#endif - -// <h> Basic - -// <o> I2C Bus clock speed (Hz) <1-400000> -// <i> I2C Bus clock (SCL) speed measured in Hz -// <id> i2c_master_baud_rate -#ifndef CONF_SERCOM_1_I2CM_BAUD -#define CONF_SERCOM_1_I2CM_BAUD 100000 -#endif - -// </h> - -// <e> Advanced -// <id> i2c_master_advanced -#ifndef CONF_SERCOM_1_I2CM_ADVANCED_CONFIG -#define CONF_SERCOM_1_I2CM_ADVANCED_CONFIG 0 -#endif - -// <o> TRise (ns) <0-300> -// <i> Determined by the bus impedance, check electric characteristics in the datasheet -// <i> Standard Fast Mode: typical 215ns, max 300ns -// <i> Fast Mode +: typical 60ns, max 100ns -// <i> High Speed Mode: typical 20ns, max 40ns -// <id> i2c_master_arch_trise - -#ifndef CONF_SERCOM_1_I2CM_TRISE -#define CONF_SERCOM_1_I2CM_TRISE 215 -#endif - -// <q> Master SCL Low Extended Time-Out (MEXTTOEN) -// <i> This enables the master SCL low extend time-out -// <id> i2c_master_arch_mexttoen -#ifndef CONF_SERCOM_1_I2CM_MEXTTOEN -#define CONF_SERCOM_1_I2CM_MEXTTOEN 0 -#endif - -// <q> Slave SCL Low Extend Time-Out (SEXTTOEN) -// <i> Enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine -// <id> i2c_master_arch_sexttoen -#ifndef CONF_SERCOM_1_I2CM_SEXTTOEN -#define CONF_SERCOM_1_I2CM_SEXTTOEN 0 -#endif - -// <q> SCL Low Time-Out (LOWTOUT) -// <i> Enables SCL low time-out. If SCL is held low for 25ms-35ms, the master will release it's clock hold -// <id> i2c_master_arch_lowtout -#ifndef CONF_SERCOM_1_I2CM_LOWTOUT -#define CONF_SERCOM_1_I2CM_LOWTOUT 0 -#endif - -// <o> Inactive Time-Out (INACTOUT) -// <0x0=>Disabled -// <0x1=>5-6 SCL cycle time-out(50-60us) -// <0x2=>10-11 SCL cycle time-out(100-110us) -// <0x3=>20-21 SCL cycle time-out(200-210us) -// <i> Defines if inactivity time-out should be enabled, and how long the time-out should be -// <id> i2c_master_arch_inactout -#ifndef CONF_SERCOM_1_I2CM_INACTOUT -#define CONF_SERCOM_1_I2CM_INACTOUT 0x0 -#endif - -// <o> SDA Hold Time (SDAHOLD) -// <0=>Disabled -// <1=>50-100ns hold time -// <2=>300-600ns hold time -// <3=>400-800ns hold time -// <i> Defines the SDA hold time with respect to the negative edge of SCL -// <id> i2c_master_arch_sdahold -#ifndef CONF_SERCOM_1_I2CM_SDAHOLD -#define CONF_SERCOM_1_I2CM_SDAHOLD 0x2 -#endif - -// <q> Run in stand-by -// <i> Determine if the module shall run in standby sleep mode -// <id> i2c_master_arch_runstdby -#ifndef CONF_SERCOM_1_I2CM_RUNSTDBY -#define CONF_SERCOM_1_I2CM_RUNSTDBY 0 -#endif - -// <o> Debug Stop Mode -// <i> Behavior of the baud-rate generator when CPU is halted by external debugger. -// <0=>Keep running -// <1=>Halt -// <id> i2c_master_arch_dbgstop -#ifndef CONF_SERCOM_1_I2CM_DEBUG_STOP_MODE -#define CONF_SERCOM_1_I2CM_DEBUG_STOP_MODE 0 -#endif - -// </e> - -#ifndef CONF_SERCOM_1_I2CM_SPEED -#define CONF_SERCOM_1_I2CM_SPEED 0x00 // Speed: Standard/Fast mode -#endif -#if CONF_SERCOM_1_I2CM_TRISE < 215 || CONF_SERCOM_1_I2CM_TRISE > 300 -#warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns -#undef CONF_SERCOM_1_I2CM_TRISE -#define CONF_SERCOM_1_I2CM_TRISE 215U -#endif - -// gclk_freq - (i2c_scl_freq * 10) - (gclk_freq * i2c_scl_freq * Trise) -// BAUD + BAUDLOW = -------------------------------------------------------------------- -// i2c_scl_freq -// BAUD: register value low [7:0] -// BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW -#define CONF_SERCOM_1_I2CM_BAUD_BAUDLOW \ - (((CONF_GCLK_SERCOM1_CORE_FREQUENCY - (CONF_SERCOM_1_I2CM_BAUD * 10U) \ - - (CONF_SERCOM_1_I2CM_TRISE * (CONF_SERCOM_1_I2CM_BAUD / 100U) * (CONF_GCLK_SERCOM1_CORE_FREQUENCY / 10000U) \ - / 1000U)) \ - * 10U \ - + 5U) \ - / (CONF_SERCOM_1_I2CM_BAUD * 10U)) -#ifndef CONF_SERCOM_1_I2CM_BAUD_RATE -#if CONF_SERCOM_1_I2CM_BAUD_BAUDLOW > (0xFF * 2) -#warning Requested I2C baudrate too low, please check -#define CONF_SERCOM_1_I2CM_BAUD_RATE 0xFF -#elif CONF_SERCOM_1_I2CM_BAUD_BAUDLOW <= 1 -#warning Requested I2C baudrate too high, please check -#define CONF_SERCOM_1_I2CM_BAUD_RATE 1 -#else -#define CONF_SERCOM_1_I2CM_BAUD_RATE \ - ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW & 0x1) \ - ? (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2 + 1) << 8) \ - : (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2)) -#endif -#endif - -#include <peripheral_clk_config.h> - -// Enable configuration of module -#ifndef CONF_SERCOM_3_SPI_ENABLE -#define CONF_SERCOM_3_SPI_ENABLE 1 -#endif - -// Set module in SPI Master mode -#ifndef CONF_SERCOM_3_SPI_MODE -#define CONF_SERCOM_3_SPI_MODE 0x03 -#endif - -// <h> Basic Configuration - -// <q> Receive buffer enable -// <i> Enable receive buffer to receive data from slave (RXEN) -// <id> spi_master_rx_enable -#ifndef CONF_SERCOM_3_SPI_RXEN -#define CONF_SERCOM_3_SPI_RXEN 0x1 -#endif - -// <o> Character Size -// <i> Bit size for all characters sent over the SPI bus (CHSIZE) -// <0x0=>8 bits -// <0x1=>9 bits -// <id> spi_master_character_size -#ifndef CONF_SERCOM_3_SPI_CHSIZE -#define CONF_SERCOM_3_SPI_CHSIZE 0x0 -#endif -// <o> Baud rate <1-12000000> -// <i> The SPI data transfer rate -// <id> spi_master_baud_rate -#ifndef CONF_SERCOM_3_SPI_BAUD -#define CONF_SERCOM_3_SPI_BAUD 50000 -#endif - -// </h> - -// <e> Advanced Configuration -// <id> spi_master_advanced -#ifndef CONF_SERCOM_3_SPI_ADVANCED -#define CONF_SERCOM_3_SPI_ADVANCED 1 -#endif - -// <o> Dummy byte <0x00-0x1ff> -// <id> spi_master_dummybyte -// <i> Dummy byte used when reading data from the slave without sending any data -#ifndef CONF_SERCOM_3_SPI_DUMMYBYTE -#define CONF_SERCOM_3_SPI_DUMMYBYTE 0x1ff -#endif - -// <o> Data Order -// <0=>MSB first -// <1=>LSB first -// <i> I least significant or most significant bit is shifted out first (DORD) -// <id> spi_master_arch_dord -#ifndef CONF_SERCOM_3_SPI_DORD -#define CONF_SERCOM_3_SPI_DORD 0x0 -#endif - -// <o> Clock Polarity -// <0=>SCK is low when idle -// <1=>SCK is high when idle -// <i> Determines if the leading edge is rising or falling with a corresponding opposite edge at the trailing edge. (CPOL) -// <id> spi_master_arch_cpol -#ifndef CONF_SERCOM_3_SPI_CPOL -#define CONF_SERCOM_3_SPI_CPOL 0x0 -#endif - -// <o> Clock Phase -// <0x0=>Sample input on leading edge -// <0x1=>Sample input on trailing edge -// <i> Determines if input data is sampled on leading or trailing SCK edge. (CPHA) -// <id> spi_master_arch_cpha -#ifndef CONF_SERCOM_3_SPI_CPHA -#define CONF_SERCOM_3_SPI_CPHA 0x0 -#endif - -// <o> Immediate Buffer Overflow Notification -// <i> Controls when OVF is asserted (IBON) -// <0x0=>In data stream -// <0x1=>On buffer overflow -// <id> spi_master_arch_ibon -#ifndef CONF_SERCOM_3_SPI_IBON -#define CONF_SERCOM_3_SPI_IBON 0x0 -#endif - -// <q> Run in stand-by -// <i> Module stays active in stand-by sleep mode. (RUNSTDBY) -// <id> spi_master_arch_runstdby -#ifndef CONF_SERCOM_3_SPI_RUNSTDBY -#define CONF_SERCOM_3_SPI_RUNSTDBY 0x0 -#endif - -// <o> Debug Stop Mode -// <i> Behavior of the baud-rate generator when CPU is halted by external debugger. (DBGSTOP) -// <0=>Keep running -// <1=>Halt -// <id> spi_master_arch_dbgstop -#ifndef CONF_SERCOM_3_SPI_DBGSTOP -#define CONF_SERCOM_3_SPI_DBGSTOP 0 -#endif - -// </e> - -// Address mode disabled in master mode -#ifndef CONF_SERCOM_3_SPI_AMODE_EN -#define CONF_SERCOM_3_SPI_AMODE_EN 0 -#endif - -#ifndef CONF_SERCOM_3_SPI_AMODE -#define CONF_SERCOM_3_SPI_AMODE 0 -#endif - -#ifndef CONF_SERCOM_3_SPI_ADDR -#define CONF_SERCOM_3_SPI_ADDR 0 -#endif - -#ifndef CONF_SERCOM_3_SPI_ADDRMASK -#define CONF_SERCOM_3_SPI_ADDRMASK 0 -#endif - -#ifndef CONF_SERCOM_3_SPI_SSDE -#define CONF_SERCOM_3_SPI_SSDE 0 -#endif - -#ifndef CONF_SERCOM_3_SPI_MSSEN -#define CONF_SERCOM_3_SPI_MSSEN 0x0 -#endif - -#ifndef CONF_SERCOM_3_SPI_PLOADEN -#define CONF_SERCOM_3_SPI_PLOADEN 0 -#endif - -// <o> Receive Data Pinout -// <0x0=>PAD[0] -// <0x1=>PAD[1] -// <0x2=>PAD[2] -// <0x3=>PAD[3] -// <id> spi_master_rxpo -#ifndef CONF_SERCOM_3_SPI_RXPO -#define CONF_SERCOM_3_SPI_RXPO 2 -#endif - -// <o> Transmit Data Pinout -// <0x0=>PAD[0,1]_DO_SCK -// <0x1=>PAD[2,3]_DO_SCK -// <0x2=>PAD[3,1]_DO_SCK -// <0x3=>PAD[0,3]_DO_SCK -// <id> spi_master_txpo -#ifndef CONF_SERCOM_3_SPI_TXPO -#define CONF_SERCOM_3_SPI_TXPO 3 -#endif - -// Calculate baud register value from requested baudrate value -#ifndef CONF_SERCOM_3_SPI_BAUD_RATE -#define CONF_SERCOM_3_SPI_BAUD_RATE ((float)CONF_GCLK_SERCOM3_CORE_FREQUENCY / (float)(2 * CONF_SERCOM_3_SPI_BAUD)) - 1 -#endif - -// <<< end of configuration section >>> - -#endif // HPL_SERCOM_CONFIG_H diff --git a/watch-library/config/hpl_slcd_config.h b/watch-library/config/hpl_slcd_config.h deleted file mode 100644 index d78e3391..00000000 --- a/watch-library/config/hpl_slcd_config.h +++ /dev/null @@ -1,239 +0,0 @@ -/* Auto-generated config file hpl_slcd_config.h */ -#ifndef HPL_SLCD_CONFIG_H -#define HPL_SLCD_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -#include <hpl_slcd_cm.h> -#include <peripheral_clk_config.h> -#include "pins.h" - -// <h> Standard configuration - -// <o> Number of COM Lines -// <i> Number of COM Lines -// <0=>1 -// <1=>2 -// <2=>3 -// <3=>4 -// <4=>6 -// <5=>8 -// <id> slcd_arch_com_num -#ifndef CONF_SLCD_COM_NUM -#define CONF_SLCD_COM_NUM 2 -#endif - -// <o> Number of Segment Lines <1-44> -// <i> Number of Segment Lines -// <id> slcd_arch_seg_num -#ifndef CONF_SLCD_SEG_NUM -#define CONF_SLCD_SEG_NUM 24 -#endif - -#if CONF_SLCD_COM_NUM == SLCD_CTRLA_DUTY_SIXTH_Val && CONF_SLCD_SEG_NUM > 42 -#warning Segment number should less than or equals to 42 -#endif -#if CONF_SLCD_COM_NUM == SLCD_CTRLA_DUTY_EIGHT_Val && CONF_SLCD_SEG_NUM > 40 -#warning Segment number should less than or equals to 40 -#endif - -// <o> Bias -// <i> Bias Settting -// <0=>STATIC -// <1=>HALF -// <2=>THIRD -// <3=>FOURTH -// <id> slcd_arch_bias -#ifndef CONF_SLCD_BIAS -#define CONF_SLCD_BIAS 2 -#endif - -#if CONF_SLCD_COM_NUM == 0 && CONF_SLCD_BIAS != 0 -#warning Recommended Bias for 1 common terminal is STATIC -#elif CONF_SLCD_COM_NUM == 1 && CONF_SLCD_BIAS != 1 -#warning Recommended Bias for 2 Common Terminals is HALF -#elif CONF_SLCD_COM_NUM <= 4 && CONF_SLCD_BIAS != 2 -#warning Recommended Bias for 3/4/6 Common Terminals is THIRD -#elif CONF_SLCD_COM_NUM == 5 && CONF_SLCD_BIAS != 3 -#warning Recommended Bias for 8 Common Terminals is FOURTH -#endif - -// <q> Bias Buffer Enable -// <i> Enable Bias Buffer -// <id> slcd_arch_bben -#ifndef CONF_SLCD_BBEN -#define CONF_SLCD_BBEN 1 -#endif - -// <o> Bias Buffer Enable Duration <1-16> -// <i> Configure the enable duration of the bias buffer, unit is cycle of SLCD OSC clock source -// <id> slcd_arch_bbd -#ifndef CONF_SLCD_BBD -#define CONF_SLCD_BBD 2 -#endif - -// <o> Clock Prescaler -// <i> Setting for LCD frame frequency -// <0=>16 -// <1=>32 -// <2=>64 -// <3=>128 -// <id> slcd_arch_presc -#ifndef CONF_SLCD_PRESC -#define CONF_SLCD_PRESC 1 -#endif - -// <o> Clock Divider -// <i> Setting for LCD frame frequency -// <0=>1 -// <1=>2 -// <2=>3 -// <3=>4 -// <4=>5 -// <5=>6 -// <6=>7 -// <7=>8 -// <id> slcd_arch_ckdiv -#ifndef CONF_SLCD_CKDIV -#define CONF_SLCD_CKDIV 5 -#endif - -/* TODO add frame frequency check */ - -// <o> Reference Refresh Frequency -// <i> Setting for Reference Refresh Frequency -// <0=>2kHz -// <1=>1kHz -// <2=>500Hz -// <3=>250Hz -// <4=>125Hz -// <5=>62.5Hz -// <id> slcd_arch_rrf -#ifndef CONF_SLCD_RRF -#define CONF_SLCD_RRF 0 -#endif - -// <o> Power Refresh Frequency -// <i> Setting for Charge pump Refresh Frequency -// <0=>2kHz -// <1=>1kHz -// <2=>500Hz -// <3=>250Hz -// <id> slcd_arch_prf -#ifndef CONF_SLCD_PRF -#define CONF_SLCD_PRF 3 -#endif - -// <q> External VLCD -// <i> Setting for how VLCD is generated -// <id> slcd_arch_xvlcd -#ifndef CONF_SLCD_XVLCD -#define CONF_SLCD_XVLCD 0 -#endif - -// <o> Waveform Mode -// <i> Setting for Waveform Mode -// <0=>Low Power Waveform(frame-inversion) -// <1=>Standard Waveform Mode(bit-inversion) -// <id> slcd_arch_wmod -#ifndef CONF_SLCD_WMOD -#define CONF_SLCD_WMOD 0 -#endif - -// <o> Contrast Adjustment -// <i> The contrast of the LCD is determined by the value of VLCD voltage. -// <i> The higher the VLCD voltage, the higher is the contrast. -// <i> The software contrast adjustment is only possible in internal supply mode. -// <0=>2.5056V -// <1=>2.5731V -// <2=>2.6379V -// <3=>2.7054V -// <4=>2.7729V -// <5=>2.8404V -// <6=>2.9052V -// <7=>2.9727V -// <8=>3.0402V -// <9=>3.1077V -// <10=>3.1725V -// <11=>3.24V -// <12=>3.3075V -// <13=>3.375V -// <14=>3.4398V -// <15=>3.5073V -// <id> slcd_arch_contrast_adjust -#ifndef CONF_SLCD_CONTRAST_ADJUST -#define CONF_SLCD_CONTRAST_ADJUST 14 -#endif - -// </h> - -// <e> Advanced configuration -// <id> slcd_arch_advanced_settings -#ifndef CONF_SLCD_ADVANCED_SETTINGS -#define CONF_SLCD_ADVANCED_SETTINGS 1 -#endif - -// <q> Run in standby -// <i> Indicates whether the SLCD will continue running in standby sleep mode or not -// <id> slcd_arch_runstdby -#ifndef CONF_SLCD_RUNSTDBY -#define CONF_SLCD_RUNSTDBY 1 -#endif - -// </e> - -#if SLCD_FRAME_FREQUENCY < 30 || SLCD_FRAME_FREQUENCY > 100 -#warning The optimal frame frequency should be in range from 30Hz up to 100Hz to avoid flickering and ghosting effect. -#endif - -#define SLCD_FC_MAX_MS (((0x1F + 1) * 8) * (1000 / SLCD_FRAME_FREQUENCY)) -#define SLCD_FC_MIN_MS (1000 / SLCD_FRAME_FREQUENCY) -#define SLCD_FC_BYPASS_MAX_MS ((0x1F + 1) * (1000 / SLCD_FRAME_FREQUENCY)) - -// <e> Character Mapping Setting -// <id> slcd_arch_cm_setting -#ifndef CONF_SLCD_CM_ENABLE -#define CONF_SLCD_CM_ENABLE 0 -#endif - -/** - * character lookup table - */ -#ifndef CONF_SLCD_LPENL -#define CONF_SLCD_LPENL (\ - (uint32_t)1 << 0 | \ - (uint32_t)1 << 1 | \ - (uint32_t)1 << 2 | \ - (uint32_t)1 << 3 | \ - (uint32_t)1 << 4 | \ - (uint32_t)1 << 5 | \ - (uint32_t)1 << 6 | \ - (uint32_t)1 << 7 | \ - (uint32_t)1 << 11 | \ - (uint32_t)1 << 12 | \ - (uint32_t)1 << 13 | \ - (uint32_t)1 << 14 | \ - (uint32_t)1 << 21 | \ - (uint32_t)1 << 22 | \ - (uint32_t)1 << 23 | \ - (uint32_t)1 << 24 | \ - (uint32_t)1 << 25 | \ - (uint32_t)1 << 28 | \ - (uint32_t)1 << 29 | \ - (uint32_t)1 << 30 | \ - (uint32_t)1 << 31 | 0) -#endif // CONF_SLCD_LPENL - -#ifndef CONF_SLCD_LPENH -#define CONF_SLCD_LPENH (\ - (uint32_t)1 << (32 - 32) | \ - (uint32_t)1 << (33 - 32) | \ - (uint32_t)1 << (34 - 32) | \ - (uint32_t)1 << (35 - 32) | \ - (uint32_t)1 << (42 - 32) | \ - (uint32_t)1 << (43 - 32) | 0) -#endif // CONF_SLCD_LPENH - -// <<< end of configuration section >>> - -#endif // HPL_SLCD_CONFIG_H diff --git a/watch-library/config/hpl_systick_config.h b/watch-library/config/hpl_systick_config.h deleted file mode 100644 index a7f2f362..00000000 --- a/watch-library/config/hpl_systick_config.h +++ /dev/null @@ -1,18 +0,0 @@ -/* Auto-generated config file hpl_systick_config.h */ -#ifndef HPL_SYSTICK_CONFIG_H -#define HPL_SYSTICK_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// <h> Advanced settings -// <q> SysTick exception request -// <i> Indicates whether the generation of SysTick exception is enabled or not -// <id> systick_arch_tickint -#ifndef CONF_SYSTICK_TICKINT -#define CONF_SYSTICK_TICKINT 0 -#endif -// </h> - -// <<< end of configuration section >>> - -#endif // HPL_SYSTICK_CONFIG_H diff --git a/watch-library/config/hpl_trng_config.h b/watch-library/config/hpl_trng_config.h deleted file mode 100755 index ba901498..00000000 --- a/watch-library/config/hpl_trng_config.h +++ /dev/null @@ -1,27 +0,0 @@ -/* Auto-generated config file hpl_trng_config.h */ -#ifndef HPL_TRNG_CONFIG_H -#define HPL_TRNG_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// <h> Advanced configurations - -// <q> Run In Standby -// <i> Indicates whether the TRNG works in standby mode -// <id> trng_runstdby -#ifndef CONF_TRNG_RUNSTDBY -#define CONF_TRNG_RUNSTDBY 0 -#endif - -// <q> Data Ready Event Output Enable -// <i> Indicates whether the TRNG generates event on Data Ready -// <id> trng_datardyeo -#ifndef CONF_TRNG_DATARDYEO -#define CONF_TRNG_DATARDYEO 0 -#endif - -// </h> - -// <<< end of configuration section >>> - -#endif // HPL_TRNG_CONFIG_H diff --git a/watch-library/config/nv_storage_config.h b/watch-library/config/nv_storage_config.h deleted file mode 100755 index 4888d1bd..00000000 --- a/watch-library/config/nv_storage_config.h +++ /dev/null @@ -1,51 +0,0 @@ -/* Auto-generated config file nv_storage_config.h */ -#ifndef NV_STORAGE_CONFIG_H -#define NV_STORAGE_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -//<o> Storage start address <0x00000000-0xFFFFFFFF> -//<i> This defines the start address of device flash for storage. -//<i> The start address should be in device flash area. -//<i> The start address and (start address + Item Number * Sector size) cannot beyond device flash area. -//<id> conf_storage_memory_start -#ifndef CONF_STORAGE_MEMORY_START -#define CONF_STORAGE_MEMORY_START 0x10000 -#endif - -//<o> Item number <0-65535> -//<i> This defines the maximum number of elements stored in persistent storage -//<id> conf_max_item_number -#ifndef CONF_MAX_ITEM_NUMBER -#define CONF_MAX_ITEM_NUMBER 10 -#endif - -//<o> Sector size <0-65535> -//<i> This defines the size of one storage sector in bytes -//<id> conf_sector_size -#ifndef CONF_SECTOR_SIZE -#define CONF_SECTOR_SIZE 4096 -#endif - -/** - * Check If the Storage configuration out of the flash area. - */ -#ifdef FLASH_SIZE -#if (CONF_STORAGE_MEMORY_START + (SECTOR_AMOUNT * CONF_SECTOR_SIZE)) > FLASH_SIZE -#error Invalidate storage configuration, make sure the configuration with \ -the sector start address (CONF_STORAGE_MEMORY_START) and sector size (CONF_SECTOR_SIZE) \ -are located within the device flash size. -#endif -#endif - -#ifdef IFLASH_SIZE -#if (CONF_STORAGE_MEMORY_START + (SECTOR_AMOUNT * CONF_SECTOR_SIZE)) > IFLASH_SIZE -#error Invalidate storage configuration, make sure the configuration with \ -the sector start address (CONF_STORAGE_MEMORY_START) and sector size (CONF_SECTOR_SIZE) \ -are located within the device flash size. -#endif -#endif - -// <<< end of configuration section >>> - -#endif // NV_STORAGE_CONFIG_H diff --git a/watch-library/config/peripheral_clk_config.h b/watch-library/config/peripheral_clk_config.h deleted file mode 100644 index 523b036c..00000000 --- a/watch-library/config/peripheral_clk_config.h +++ /dev/null @@ -1,266 +0,0 @@ -/* Auto-generated config file peripheral_clk_config.h */ -#ifndef PERIPHERAL_CLK_CONFIG_H -#define PERIPHERAL_CLK_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// <y> ADC Clock Source -// <id> adc_gclk_selection - -// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 - -// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 - -// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 - -// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 - -// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 - -// <i> Select the clock source for ADC. -#ifndef CONF_GCLK_ADC_SRC -#define CONF_GCLK_ADC_SRC GCLK_PCHCTRL_GEN_GCLK0_Val -#endif - -/** - * \def CONF_GCLK_ADC_FREQUENCY - * \brief ADC's Clock frequency - */ -#ifndef CONF_GCLK_ADC_FREQUENCY -#define CONF_GCLK_ADC_FREQUENCY 4000000 -#endif - -// <y> EIC Clock Source -// <id> eic_gclk_selection - -// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 - -// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 - -// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 - -// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 - -// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 - -// <i> Select the clock source for EIC. -#ifndef CONF_GCLK_EIC_SRC -#define CONF_GCLK_EIC_SRC GCLK_PCHCTRL_GEN_GCLK3_Val -#endif - -/** - * \def CONF_GCLK_EIC_FREQUENCY - * \brief EIC's Clock frequency - */ -#ifndef CONF_GCLK_EIC_FREQUENCY -#define CONF_GCLK_EIC_FREQUENCY 32768 -#endif - -/** - * \def CONF_CPU_FREQUENCY - * \brief CPU's Clock frequency - */ -#ifndef CONF_CPU_FREQUENCY -#define CONF_CPU_FREQUENCY 4000000 -#endif - -// <y> RTC Clock Source -// <id> rtc_clk_selection -// <RTC_CLOCK_SOURCE"> RTC source -// <i> Select the clock source for RTC. -#ifndef CONF_GCLK_RTC_SRC -#define CONF_GCLK_RTC_SRC RTC_CLOCK_SOURCE -#endif - -/** - * \def CONF_GCLK_RTC_FREQUENCY - * \brief RTC's Clock frequency - */ -#ifndef CONF_GCLK_RTC_FREQUENCY -#define CONF_GCLK_RTC_FREQUENCY 1024 -#endif - -// <y> Core Clock Source -// <id> core_gclk_selection - -// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 - -// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 - -// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 - -// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 - -// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 - -// <i> Select the clock source for CORE. -#ifndef CONF_GCLK_SERCOM1_CORE_SRC -#define CONF_GCLK_SERCOM1_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val -#endif - -// <y> Slow Clock Source -// <id> slow_gclk_selection - -// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 - -// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 - -// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 - -// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 - -// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 - -// <i> Select the slow clock source. -#ifndef CONF_GCLK_SERCOM1_SLOW_SRC -#define CONF_GCLK_SERCOM1_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val -#endif - -/** - * \def CONF_GCLK_SERCOM1_CORE_FREQUENCY - * \brief SERCOM1's Core Clock frequency - */ -#ifndef CONF_GCLK_SERCOM1_CORE_FREQUENCY -#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 4000000 -#endif - -/** - * \def CONF_GCLK_SERCOM1_SLOW_FREQUENCY - * \brief SERCOM1's Slow Clock frequency - */ -#ifndef CONF_GCLK_SERCOM1_SLOW_FREQUENCY -#define CONF_GCLK_SERCOM1_SLOW_FREQUENCY 32768 -#endif - -// <y> Core Clock Source -// <id> core_gclk_selection - -// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 - -// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 - -// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 - -// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 - -// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 - -// <i> Select the clock source for CORE. -#ifndef CONF_GCLK_SERCOM3_CORE_SRC -#define CONF_GCLK_SERCOM3_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val -#endif - -// <y> Slow Clock Source -// <id> slow_gclk_selection - -// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 - -// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 - -// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 - -// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 - -// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 - -// <i> Select the slow clock source. -#ifndef CONF_GCLK_SERCOM3_SLOW_SRC -#define CONF_GCLK_SERCOM3_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val -#endif - -/** - * \def CONF_GCLK_SERCOM3_CORE_FREQUENCY - * \brief SERCOM3's Core Clock frequency - */ -#ifndef CONF_GCLK_SERCOM3_CORE_FREQUENCY -#define CONF_GCLK_SERCOM3_CORE_FREQUENCY 4000000 -#endif - -/** - * \def CONF_GCLK_SERCOM3_SLOW_FREQUENCY - * \brief SERCOM3's Slow Clock frequency - */ -#ifndef CONF_GCLK_SERCOM3_SLOW_FREQUENCY -#define CONF_GCLK_SERCOM3_SLOW_FREQUENCY 32768 -#endif - -// <y> TC Clock Source -// <id> tc_gclk_selection - -// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 - -// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 - -// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 - -// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 - -// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 - -// <i> Select the clock source for TC. -#ifndef CONF_GCLK_TC3_SRC -#define CONF_GCLK_TC3_SRC GCLK_PCHCTRL_GEN_GCLK3_Val -#endif - -/** - * \def CONF_GCLK_TC3_FREQUENCY - * \brief TC3's Clock frequency - */ -#ifndef CONF_GCLK_TC3_FREQUENCY -#define CONF_GCLK_TC3_FREQUENCY 32768 -#endif - -// <y> TCC Clock Source -// <id> tcc_gclk_selection - -// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 - -// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 - -// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 - -// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 - -// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 - -// <i> Select the clock source for TCC. -#ifndef CONF_GCLK_TCC0_SRC -#define CONF_GCLK_TCC0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val -#endif - -/** - * \def CONF_GCLK_TCC0_FREQUENCY - * \brief TCC0's Clock frequency - */ -#ifndef CONF_GCLK_TCC0_FREQUENCY -#define CONF_GCLK_TCC0_FREQUENCY 16000000 -#endif - -#include <hpl_osc32kctrl_config.h> - -// <y> SLCD Clock Source -// <id> slcd_clk_selection -// <SLCD_CLOCK_SOURCE"> SLCD source -// <i> Select the clock source for SLCD. -#ifndef CONF_GCLK_SLCD_SRC -#define CONF_GCLK_SLCD_SRC SLCD_CLOCK_SOURCE -#endif - -/** - * \def CONF_GCLK_SLCD_FREQUENCY - * \brief SLCD's Clock frequency - */ -#ifndef CONF_GCLK_SLCD_FREQUENCY -#define CONF_GCLK_SLCD_FREQUENCY 32768 -#endif - -#ifndef SLCD_FRAME_FREQUENCY -#define SLCD_FRAME_FREQUENCY \ - (CONF_GCLK_SLCD_FREQUENCY \ - / (((CONF_SLCD_PRESC + 1) * 16) * (CONF_SLCD_CKDIV + 1) \ - * ((CONF_SLCD_COM_NUM == 4) ? 6 : ((CONF_SLCD_COM_NUM == 5) ? 8 : (CONF_SLCD_COM_NUM + 1))))) -#endif - -// <<< end of configuration section >>> - -#endif // PERIPHERAL_CLK_CONFIG_H |