Sensor Watch Simulator (#35)

* Put something on screen

* Use the 32bit watch_date_time repr to pass from JS

* Implement periodic callbacks

* Clear display on enabling

* Hook up watch_set_led_color() to SVG (green-only)

* Make debug output full-width

* Remove default Emscripten canvas

* Implement sleep and button clicks

* Fix time zone conversion bug in beats-time app

* Clean up warnings

* Fix pin levels

* Set time zone to browser value (if available)

* Add basic backup data saving

* Silence format specifier warnings in both targets

* Remove unnecessary, copied files

* Use RTC pointer to clear callbacks (if available)

* Use preprocessor define to avoid hardcoding MOVEMENT_NUM_FACES

* Change each face to const preprocessor definition

* Remove Intl.DateTimeFormat usage

* Update shell.html title, header

* Add touch start/end event handlers on SVG buttons

* Update shell.html

* Update folder structure (shared, simulator, hardware under watch-library)

* Tease out shared components from watch_slcd

* Clean up simulator watch_slcd.c inline JS calls

* Fix missing newlines at end of file

* Add simulator warnings (except format, unused-paremter)

* Implement remaining watch_rtc functions

* Fix button bug on mouse down then drag out

* Implement remaining watch_slcd functions

* Link keyboard events to buttons (for keys A, L, M)

* Rewrite event handling (mouse, touch, keyboard) in C

* Set explicit text UTF-8 charset in shell.html

* Address PR comments

* Remove unused directories from include paths

32 files changed, 73096 insertions, 0 deletions

diff --git a/watch-library/hardware/hri/hri_ac_l22.h b/watch-library/hardware/hri/hri_ac_l22.h
new file mode 100644
index 00000000..f1e17cef
--- /dev/null
+++ b/watch-library/hardware/hri/hri_ac_l22.h
@@ -0,0 +1,1746 @@
+/**
+ * \file
+ *
+ * \brief SAM AC
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_AC_COMPONENT_
+#ifndef _HRI_AC_L22_H_INCLUDED_
+#define _HRI_AC_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_AC_CRITICAL_SECTIONS)
+#define AC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define AC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define AC_CRITICAL_SECTION_ENTER()
+#define AC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_ac_evctrl_reg_t;
+typedef uint32_t hri_ac_compctrl_reg_t;
+typedef uint32_t hri_ac_syncbusy_reg_t;
+typedef uint8_t  hri_ac_ctrla_reg_t;
+typedef uint8_t  hri_ac_ctrlb_reg_t;
+typedef uint8_t  hri_ac_dbgctrl_reg_t;
+typedef uint8_t  hri_ac_intenset_reg_t;
+typedef uint8_t  hri_ac_intflag_reg_t;
+typedef uint8_t  hri_ac_scaler_reg_t;
+typedef uint8_t  hri_ac_statusa_reg_t;
+typedef uint8_t  hri_ac_statusb_reg_t;
+typedef uint8_t  hri_ac_winctrl_reg_t;
+
+static inline void hri_ac_wait_for_sync(const void *const hw, hri_ac_syncbusy_reg_t reg)
+{
+	while (((Ac *)hw)->SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_ac_is_syncing(const void *const hw, hri_ac_syncbusy_reg_t reg)
+{
+	return ((Ac *)hw)->SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_ac_get_INTFLAG_COMP0_bit(const void *const hw)
+{
+	return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP0) >> AC_INTFLAG_COMP0_Pos;
+}
+
+static inline void hri_ac_clear_INTFLAG_COMP0_bit(const void *const hw)
+{
+	((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP0;
+}
+
+static inline bool hri_ac_get_INTFLAG_COMP1_bit(const void *const hw)
+{
+	return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP1) >> AC_INTFLAG_COMP1_Pos;
+}
+
+static inline void hri_ac_clear_INTFLAG_COMP1_bit(const void *const hw)
+{
+	((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP1;
+}
+
+static inline bool hri_ac_get_INTFLAG_WIN0_bit(const void *const hw)
+{
+	return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_WIN0) >> AC_INTFLAG_WIN0_Pos;
+}
+
+static inline void hri_ac_clear_INTFLAG_WIN0_bit(const void *const hw)
+{
+	((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_WIN0;
+}
+
+static inline bool hri_ac_get_interrupt_COMP0_bit(const void *const hw)
+{
+	return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP0) >> AC_INTFLAG_COMP0_Pos;
+}
+
+static inline void hri_ac_clear_interrupt_COMP0_bit(const void *const hw)
+{
+	((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP0;
+}
+
+static inline bool hri_ac_get_interrupt_COMP1_bit(const void *const hw)
+{
+	return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP1) >> AC_INTFLAG_COMP1_Pos;
+}
+
+static inline void hri_ac_clear_interrupt_COMP1_bit(const void *const hw)
+{
+	((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP1;
+}
+
+static inline bool hri_ac_get_interrupt_WIN0_bit(const void *const hw)
+{
+	return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_WIN0) >> AC_INTFLAG_WIN0_Pos;
+}
+
+static inline void hri_ac_clear_interrupt_WIN0_bit(const void *const hw)
+{
+	((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_WIN0;
+}
+
+static inline hri_ac_intflag_reg_t hri_ac_get_INTFLAG_reg(const void *const hw, hri_ac_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_ac_intflag_reg_t hri_ac_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Ac *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_ac_clear_INTFLAG_reg(const void *const hw, hri_ac_intflag_reg_t mask)
+{
+	((Ac *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_ac_set_INTEN_COMP0_bit(const void *const hw)
+{
+	((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP0;
+}
+
+static inline bool hri_ac_get_INTEN_COMP0_bit(const void *const hw)
+{
+	return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_COMP0) >> AC_INTENSET_COMP0_Pos;
+}
+
+static inline void hri_ac_write_INTEN_COMP0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP0;
+	} else {
+		((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP0;
+	}
+}
+
+static inline void hri_ac_clear_INTEN_COMP0_bit(const void *const hw)
+{
+	((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP0;
+}
+
+static inline void hri_ac_set_INTEN_COMP1_bit(const void *const hw)
+{
+	((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP1;
+}
+
+static inline bool hri_ac_get_INTEN_COMP1_bit(const void *const hw)
+{
+	return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_COMP1) >> AC_INTENSET_COMP1_Pos;
+}
+
+static inline void hri_ac_write_INTEN_COMP1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP1;
+	} else {
+		((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP1;
+	}
+}
+
+static inline void hri_ac_clear_INTEN_COMP1_bit(const void *const hw)
+{
+	((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP1;
+}
+
+static inline void hri_ac_set_INTEN_WIN0_bit(const void *const hw)
+{
+	((Ac *)hw)->INTENSET.reg = AC_INTENSET_WIN0;
+}
+
+static inline bool hri_ac_get_INTEN_WIN0_bit(const void *const hw)
+{
+	return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_WIN0) >> AC_INTENSET_WIN0_Pos;
+}
+
+static inline void hri_ac_write_INTEN_WIN0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Ac *)hw)->INTENCLR.reg = AC_INTENSET_WIN0;
+	} else {
+		((Ac *)hw)->INTENSET.reg = AC_INTENSET_WIN0;
+	}
+}
+
+static inline void hri_ac_clear_INTEN_WIN0_bit(const void *const hw)
+{
+	((Ac *)hw)->INTENCLR.reg = AC_INTENSET_WIN0;
+}
+
+static inline void hri_ac_set_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask)
+{
+	((Ac *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_ac_intenset_reg_t hri_ac_get_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_ac_intenset_reg_t hri_ac_read_INTEN_reg(const void *const hw)
+{
+	return ((Ac *)hw)->INTENSET.reg;
+}
+
+static inline void hri_ac_write_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t data)
+{
+	((Ac *)hw)->INTENSET.reg = data;
+	((Ac *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_ac_clear_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask)
+{
+	((Ac *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_ac_get_STATUSA_STATE0_bit(const void *const hw)
+{
+	return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_STATE0) >> AC_STATUSA_STATE0_Pos;
+}
+
+static inline bool hri_ac_get_STATUSA_STATE1_bit(const void *const hw)
+{
+	return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_STATE1) >> AC_STATUSA_STATE1_Pos;
+}
+
+static inline hri_ac_statusa_reg_t hri_ac_get_STATUSA_WSTATE0_bf(const void *const hw, hri_ac_statusa_reg_t mask)
+{
+	return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_WSTATE0(mask)) >> AC_STATUSA_WSTATE0_Pos;
+}
+
+static inline hri_ac_statusa_reg_t hri_ac_read_STATUSA_WSTATE0_bf(const void *const hw)
+{
+	return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_WSTATE0_Msk) >> AC_STATUSA_WSTATE0_Pos;
+}
+
+static inline hri_ac_statusa_reg_t hri_ac_get_STATUSA_reg(const void *const hw, hri_ac_statusa_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->STATUSA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_ac_statusa_reg_t hri_ac_read_STATUSA_reg(const void *const hw)
+{
+	return ((Ac *)hw)->STATUSA.reg;
+}
+
+static inline bool hri_ac_get_STATUSB_READY0_bit(const void *const hw)
+{
+	return (((Ac *)hw)->STATUSB.reg & AC_STATUSB_READY0) >> AC_STATUSB_READY0_Pos;
+}
+
+static inline bool hri_ac_get_STATUSB_READY1_bit(const void *const hw)
+{
+	return (((Ac *)hw)->STATUSB.reg & AC_STATUSB_READY1) >> AC_STATUSB_READY1_Pos;
+}
+
+static inline hri_ac_statusb_reg_t hri_ac_get_STATUSB_reg(const void *const hw, hri_ac_statusb_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->STATUSB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_ac_statusb_reg_t hri_ac_read_STATUSB_reg(const void *const hw)
+{
+	return ((Ac *)hw)->STATUSB.reg;
+}
+
+static inline bool hri_ac_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_SWRST) >> AC_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_ac_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_ENABLE) >> AC_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_ac_get_SYNCBUSY_WINCTRL_bit(const void *const hw)
+{
+	return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_WINCTRL) >> AC_SYNCBUSY_WINCTRL_Pos;
+}
+
+static inline bool hri_ac_get_SYNCBUSY_COMPCTRL0_bit(const void *const hw)
+{
+	return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_COMPCTRL0) >> AC_SYNCBUSY_COMPCTRL0_Pos;
+}
+
+static inline bool hri_ac_get_SYNCBUSY_COMPCTRL1_bit(const void *const hw)
+{
+	return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_COMPCTRL1) >> AC_SYNCBUSY_COMPCTRL1_Pos;
+}
+
+static inline hri_ac_syncbusy_reg_t hri_ac_get_SYNCBUSY_reg(const void *const hw, hri_ac_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_ac_syncbusy_reg_t hri_ac_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Ac *)hw)->SYNCBUSY.reg;
+}
+
+static inline void hri_ac_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CTRLA.reg |= AC_CTRLA_SWRST;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST);
+	tmp = ((Ac *)hw)->CTRLA.reg;
+	tmp = (tmp & AC_CTRLA_SWRST) >> AC_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CTRLA.reg |= AC_CTRLA_ENABLE;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
+	tmp = ((Ac *)hw)->CTRLA.reg;
+	tmp = (tmp & AC_CTRLA_ENABLE) >> AC_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->CTRLA.reg;
+	tmp &= ~AC_CTRLA_ENABLE;
+	tmp |= value << AC_CTRLA_ENABLE_Pos;
+	((Ac *)hw)->CTRLA.reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CTRLA.reg &= ~AC_CTRLA_ENABLE;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CTRLA.reg ^= AC_CTRLA_ENABLE;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CTRLA.reg |= mask;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_ctrla_reg_t hri_ac_get_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
+	tmp = ((Ac *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ac_write_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t data)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CTRLA.reg = data;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CTRLA.reg &= ~mask;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CTRLA.reg ^= mask;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_ctrla_reg_t hri_ac_read_CTRLA_reg(const void *const hw)
+{
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
+	return ((Ac *)hw)->CTRLA.reg;
+}
+
+static inline void hri_ac_set_EVCTRL_COMPEO0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEO0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_EVCTRL_COMPEO0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp = (tmp & AC_EVCTRL_COMPEO0) >> AC_EVCTRL_COMPEO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_EVCTRL_COMPEO0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp &= ~AC_EVCTRL_COMPEO0;
+	tmp |= value << AC_EVCTRL_COMPEO0_Pos;
+	((Ac *)hw)->EVCTRL.reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_EVCTRL_COMPEO0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEO0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_EVCTRL_COMPEO0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEO0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_EVCTRL_COMPEO1_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEO1;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_EVCTRL_COMPEO1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp = (tmp & AC_EVCTRL_COMPEO1) >> AC_EVCTRL_COMPEO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_EVCTRL_COMPEO1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp &= ~AC_EVCTRL_COMPEO1;
+	tmp |= value << AC_EVCTRL_COMPEO1_Pos;
+	((Ac *)hw)->EVCTRL.reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_EVCTRL_COMPEO1_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEO1;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_EVCTRL_COMPEO1_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEO1;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_EVCTRL_WINEO0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_WINEO0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_EVCTRL_WINEO0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp = (tmp & AC_EVCTRL_WINEO0) >> AC_EVCTRL_WINEO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_EVCTRL_WINEO0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp &= ~AC_EVCTRL_WINEO0;
+	tmp |= value << AC_EVCTRL_WINEO0_Pos;
+	((Ac *)hw)->EVCTRL.reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_EVCTRL_WINEO0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_WINEO0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_EVCTRL_WINEO0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_WINEO0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_EVCTRL_COMPEI0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEI0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_EVCTRL_COMPEI0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp = (tmp & AC_EVCTRL_COMPEI0) >> AC_EVCTRL_COMPEI0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_EVCTRL_COMPEI0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp &= ~AC_EVCTRL_COMPEI0;
+	tmp |= value << AC_EVCTRL_COMPEI0_Pos;
+	((Ac *)hw)->EVCTRL.reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_EVCTRL_COMPEI0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEI0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_EVCTRL_COMPEI0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEI0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_EVCTRL_COMPEI1_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEI1;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_EVCTRL_COMPEI1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp = (tmp & AC_EVCTRL_COMPEI1) >> AC_EVCTRL_COMPEI1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_EVCTRL_COMPEI1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp &= ~AC_EVCTRL_COMPEI1;
+	tmp |= value << AC_EVCTRL_COMPEI1_Pos;
+	((Ac *)hw)->EVCTRL.reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_EVCTRL_COMPEI1_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEI1;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_EVCTRL_COMPEI1_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEI1;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_EVCTRL_INVEI0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_INVEI0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_EVCTRL_INVEI0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp = (tmp & AC_EVCTRL_INVEI0) >> AC_EVCTRL_INVEI0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_EVCTRL_INVEI0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp &= ~AC_EVCTRL_INVEI0;
+	tmp |= value << AC_EVCTRL_INVEI0_Pos;
+	((Ac *)hw)->EVCTRL.reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_EVCTRL_INVEI0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_INVEI0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_EVCTRL_INVEI0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_INVEI0;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_EVCTRL_INVEI1_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_INVEI1;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_EVCTRL_INVEI1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp = (tmp & AC_EVCTRL_INVEI1) >> AC_EVCTRL_INVEI1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_EVCTRL_INVEI1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp &= ~AC_EVCTRL_INVEI1;
+	tmp |= value << AC_EVCTRL_INVEI1_Pos;
+	((Ac *)hw)->EVCTRL.reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_EVCTRL_INVEI1_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_INVEI1;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_EVCTRL_INVEI1_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_INVEI1;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg |= mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_evctrl_reg_t hri_ac_get_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Ac *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ac_write_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t data)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg = data;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg &= ~mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->EVCTRL.reg ^= mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_evctrl_reg_t hri_ac_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Ac *)hw)->EVCTRL.reg;
+}
+
+static inline void hri_ac_set_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->DBGCTRL.reg |= AC_DBGCTRL_DBGRUN;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->DBGCTRL.reg;
+	tmp = (tmp & AC_DBGCTRL_DBGRUN) >> AC_DBGCTRL_DBGRUN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->DBGCTRL.reg;
+	tmp &= ~AC_DBGCTRL_DBGRUN;
+	tmp |= value << AC_DBGCTRL_DBGRUN_Pos;
+	((Ac *)hw)->DBGCTRL.reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->DBGCTRL.reg &= ~AC_DBGCTRL_DBGRUN;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->DBGCTRL.reg ^= AC_DBGCTRL_DBGRUN;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->DBGCTRL.reg |= mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_dbgctrl_reg_t hri_ac_get_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ac_write_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t data)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->DBGCTRL.reg = data;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->DBGCTRL.reg &= ~mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->DBGCTRL.reg ^= mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_dbgctrl_reg_t hri_ac_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Ac *)hw)->DBGCTRL.reg;
+}
+
+static inline void hri_ac_set_WINCTRL_WEN0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->WINCTRL.reg |= AC_WINCTRL_WEN0;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_WINCTRL_WEN0_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->WINCTRL.reg;
+	tmp = (tmp & AC_WINCTRL_WEN0) >> AC_WINCTRL_WEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_WINCTRL_WEN0_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->WINCTRL.reg;
+	tmp &= ~AC_WINCTRL_WEN0;
+	tmp |= value << AC_WINCTRL_WEN0_Pos;
+	((Ac *)hw)->WINCTRL.reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_WINCTRL_WEN0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->WINCTRL.reg &= ~AC_WINCTRL_WEN0;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_WINCTRL_WEN0_bit(const void *const hw)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->WINCTRL.reg ^= AC_WINCTRL_WEN0;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->WINCTRL.reg |= AC_WINCTRL_WINTSEL0(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_winctrl_reg_t hri_ac_get_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->WINCTRL.reg;
+	tmp = (tmp & AC_WINCTRL_WINTSEL0(mask)) >> AC_WINCTRL_WINTSEL0_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t data)
+{
+	uint8_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->WINCTRL.reg;
+	tmp &= ~AC_WINCTRL_WINTSEL0_Msk;
+	tmp |= AC_WINCTRL_WINTSEL0(data);
+	((Ac *)hw)->WINCTRL.reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->WINCTRL.reg &= ~AC_WINCTRL_WINTSEL0(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->WINCTRL.reg ^= AC_WINCTRL_WINTSEL0(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_winctrl_reg_t hri_ac_read_WINCTRL_WINTSEL0_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->WINCTRL.reg;
+	tmp = (tmp & AC_WINCTRL_WINTSEL0_Msk) >> AC_WINCTRL_WINTSEL0_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->WINCTRL.reg |= mask;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_winctrl_reg_t hri_ac_get_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask)
+{
+	uint8_t tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	tmp = ((Ac *)hw)->WINCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ac_write_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t data)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->WINCTRL.reg = data;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->WINCTRL.reg &= ~mask;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->WINCTRL.reg ^= mask;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_winctrl_reg_t hri_ac_read_WINCTRL_reg(const void *const hw)
+{
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	return ((Ac *)hw)->WINCTRL.reg;
+}
+
+static inline void hri_ac_set_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->SCALER[index].reg |= AC_SCALER_VALUE(mask);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_scaler_reg_t hri_ac_get_SCALER_VALUE_bf(const void *const hw, uint8_t index,
+                                                             hri_ac_scaler_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->SCALER[index].reg;
+	tmp = (tmp & AC_SCALER_VALUE(mask)) >> AC_SCALER_VALUE_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t data)
+{
+	uint8_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->SCALER[index].reg;
+	tmp &= ~AC_SCALER_VALUE_Msk;
+	tmp |= AC_SCALER_VALUE(data);
+	((Ac *)hw)->SCALER[index].reg = tmp;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->SCALER[index].reg &= ~AC_SCALER_VALUE(mask);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->SCALER[index].reg ^= AC_SCALER_VALUE(mask);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_scaler_reg_t hri_ac_read_SCALER_VALUE_bf(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->SCALER[index].reg;
+	tmp = (tmp & AC_SCALER_VALUE_Msk) >> AC_SCALER_VALUE_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->SCALER[index].reg |= mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_scaler_reg_t hri_ac_get_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ac *)hw)->SCALER[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ac_write_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t data)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->SCALER[index].reg = data;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->SCALER[index].reg &= ~mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->SCALER[index].reg ^= mask;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_scaler_reg_t hri_ac_read_SCALER_reg(const void *const hw, uint8_t index)
+{
+	return ((Ac *)hw)->SCALER[index].reg;
+}
+
+static inline void hri_ac_set_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_ENABLE;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_ENABLE) >> AC_COMPCTRL_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_ENABLE;
+	tmp |= value << AC_COMPCTRL_ENABLE_Pos;
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_ENABLE;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_ENABLE;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SINGLE;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_SINGLE) >> AC_COMPCTRL_SINGLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_SINGLE;
+	tmp |= value << AC_COMPCTRL_SINGLE_Pos;
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SINGLE;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SINGLE;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_RUNSTDBY;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_RUNSTDBY) >> AC_COMPCTRL_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_RUNSTDBY;
+	tmp |= value << AC_COMPCTRL_RUNSTDBY_Pos;
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_RUNSTDBY;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_RUNSTDBY;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SWAP;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_SWAP) >> AC_COMPCTRL_SWAP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_SWAP;
+	tmp |= value << AC_COMPCTRL_SWAP_Pos;
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SWAP;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SWAP;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_HYSTEN;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ac_get_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_HYSTEN) >> AC_COMPCTRL_HYSTEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_HYSTEN;
+	tmp |= value << AC_COMPCTRL_HYSTEN_Pos;
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_HYSTEN;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_HYSTEN;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_set_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_INTSEL(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index,
+                                                                  hri_ac_compctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_INTSEL(mask)) >> AC_COMPCTRL_INTSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_INTSEL_Msk;
+	tmp |= AC_COMPCTRL_INTSEL(data);
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_INTSEL(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_INTSEL(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_INTSEL_Msk) >> AC_COMPCTRL_INTSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_MUXNEG(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index,
+                                                                  hri_ac_compctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_MUXNEG(mask)) >> AC_COMPCTRL_MUXNEG_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_MUXNEG_Msk;
+	tmp |= AC_COMPCTRL_MUXNEG(data);
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_MUXNEG(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_MUXNEG(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_MUXNEG_Msk) >> AC_COMPCTRL_MUXNEG_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_MUXPOS(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index,
+                                                                  hri_ac_compctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_MUXPOS(mask)) >> AC_COMPCTRL_MUXPOS_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_MUXPOS_Msk;
+	tmp |= AC_COMPCTRL_MUXPOS(data);
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_MUXPOS(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_MUXPOS(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_MUXPOS_Msk) >> AC_COMPCTRL_MUXPOS_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SPEED(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index,
+                                                                 hri_ac_compctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_SPEED(mask)) >> AC_COMPCTRL_SPEED_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_SPEED_Msk;
+	tmp |= AC_COMPCTRL_SPEED(data);
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SPEED(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SPEED(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_SPEED_Msk) >> AC_COMPCTRL_SPEED_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_HYST(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_HYST_bf(const void *const hw, uint8_t index,
+                                                                hri_ac_compctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_HYST(mask)) >> AC_COMPCTRL_HYST_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_HYST_Msk;
+	tmp |= AC_COMPCTRL_HYST(data);
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_HYST(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_HYST(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_HYST_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_HYST_Msk) >> AC_COMPCTRL_HYST_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_FLEN(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index,
+                                                                hri_ac_compctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_FLEN(mask)) >> AC_COMPCTRL_FLEN_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_FLEN_Msk;
+	tmp |= AC_COMPCTRL_FLEN(data);
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_FLEN(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_FLEN(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_FLEN_Msk) >> AC_COMPCTRL_FLEN_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_OUT(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_OUT_bf(const void *const hw, uint8_t index,
+                                                               hri_ac_compctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_OUT(mask)) >> AC_COMPCTRL_OUT_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data)
+{
+	uint32_t tmp;
+	AC_CRITICAL_SECTION_ENTER();
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= ~AC_COMPCTRL_OUT_Msk;
+	tmp |= AC_COMPCTRL_OUT(data);
+	((Ac *)hw)->COMPCTRL[index].reg = tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_OUT(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_OUT(mask);
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_OUT_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp = (tmp & AC_COMPCTRL_OUT_Msk) >> AC_COMPCTRL_OUT_Pos;
+	return tmp;
+}
+
+static inline void hri_ac_set_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg |= mask;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_reg(const void *const hw, uint8_t index,
+                                                            hri_ac_compctrl_reg_t mask)
+{
+	uint32_t tmp;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
+	tmp = ((Ac *)hw)->COMPCTRL[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ac_write_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg = data;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_clear_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg &= ~mask;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ac_toggle_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->COMPCTRL[index].reg ^= mask;
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_reg(const void *const hw, uint8_t index)
+{
+	hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
+	return ((Ac *)hw)->COMPCTRL[index].reg;
+}
+
+static inline void hri_ac_write_CTRLB_reg(const void *const hw, hri_ac_ctrlb_reg_t data)
+{
+	AC_CRITICAL_SECTION_ENTER();
+	((Ac *)hw)->CTRLB.reg = data;
+	AC_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_AC_L22_H_INCLUDED */
+#endif /* _SAML22_AC_COMPONENT_ */
diff --git a/watch-library/hardware/hri/hri_adc_l22.h b/watch-library/hardware/hri/hri_adc_l22.h
new file mode 100644
index 00000000..53ba6af8
--- /dev/null
+++ b/watch-library/hardware/hri/hri_adc_l22.h
@@ -0,0 +1,2803 @@
+/**
+ * \file
+ *
+ * \brief SAM ADC
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_ADC_COMPONENT_
+#ifndef _HRI_ADC_L22_H_INCLUDED_
+#define _HRI_ADC_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_ADC_CRITICAL_SECTIONS)
+#define ADC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define ADC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define ADC_CRITICAL_SECTION_ENTER()
+#define ADC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_adc_calib_reg_t;
+typedef uint16_t hri_adc_ctrlc_reg_t;
+typedef uint16_t hri_adc_gaincorr_reg_t;
+typedef uint16_t hri_adc_inputctrl_reg_t;
+typedef uint16_t hri_adc_offsetcorr_reg_t;
+typedef uint16_t hri_adc_result_reg_t;
+typedef uint16_t hri_adc_syncbusy_reg_t;
+typedef uint16_t hri_adc_winlt_reg_t;
+typedef uint16_t hri_adc_winut_reg_t;
+typedef uint32_t hri_adc_seqctrl_reg_t;
+typedef uint8_t  hri_adc_avgctrl_reg_t;
+typedef uint8_t  hri_adc_ctrla_reg_t;
+typedef uint8_t  hri_adc_ctrlb_reg_t;
+typedef uint8_t  hri_adc_dbgctrl_reg_t;
+typedef uint8_t  hri_adc_evctrl_reg_t;
+typedef uint8_t  hri_adc_intenset_reg_t;
+typedef uint8_t  hri_adc_intflag_reg_t;
+typedef uint8_t  hri_adc_refctrl_reg_t;
+typedef uint8_t  hri_adc_sampctrl_reg_t;
+typedef uint8_t  hri_adc_seqstatus_reg_t;
+typedef uint8_t  hri_adc_swtrig_reg_t;
+
+static inline void hri_adc_wait_for_sync(const void *const hw, hri_adc_syncbusy_reg_t reg)
+{
+	while (((Adc *)hw)->SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_adc_is_syncing(const void *const hw, hri_adc_syncbusy_reg_t reg)
+{
+	return ((Adc *)hw)->SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_adc_get_INTFLAG_RESRDY_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_RESRDY) >> ADC_INTFLAG_RESRDY_Pos;
+}
+
+static inline void hri_adc_clear_INTFLAG_RESRDY_bit(const void *const hw)
+{
+	((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_RESRDY;
+}
+
+static inline bool hri_adc_get_INTFLAG_OVERRUN_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_OVERRUN) >> ADC_INTFLAG_OVERRUN_Pos;
+}
+
+static inline void hri_adc_clear_INTFLAG_OVERRUN_bit(const void *const hw)
+{
+	((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_OVERRUN;
+}
+
+static inline bool hri_adc_get_INTFLAG_WINMON_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_WINMON) >> ADC_INTFLAG_WINMON_Pos;
+}
+
+static inline void hri_adc_clear_INTFLAG_WINMON_bit(const void *const hw)
+{
+	((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_WINMON;
+}
+
+static inline bool hri_adc_get_interrupt_RESRDY_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_RESRDY) >> ADC_INTFLAG_RESRDY_Pos;
+}
+
+static inline void hri_adc_clear_interrupt_RESRDY_bit(const void *const hw)
+{
+	((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_RESRDY;
+}
+
+static inline bool hri_adc_get_interrupt_OVERRUN_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_OVERRUN) >> ADC_INTFLAG_OVERRUN_Pos;
+}
+
+static inline void hri_adc_clear_interrupt_OVERRUN_bit(const void *const hw)
+{
+	((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_OVERRUN;
+}
+
+static inline bool hri_adc_get_interrupt_WINMON_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_WINMON) >> ADC_INTFLAG_WINMON_Pos;
+}
+
+static inline void hri_adc_clear_interrupt_WINMON_bit(const void *const hw)
+{
+	((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_WINMON;
+}
+
+static inline hri_adc_intflag_reg_t hri_adc_get_INTFLAG_reg(const void *const hw, hri_adc_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_adc_intflag_reg_t hri_adc_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Adc *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_adc_clear_INTFLAG_reg(const void *const hw, hri_adc_intflag_reg_t mask)
+{
+	((Adc *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_adc_set_INTEN_RESRDY_bit(const void *const hw)
+{
+	((Adc *)hw)->INTENSET.reg = ADC_INTENSET_RESRDY;
+}
+
+static inline bool hri_adc_get_INTEN_RESRDY_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_RESRDY) >> ADC_INTENSET_RESRDY_Pos;
+}
+
+static inline void hri_adc_write_INTEN_RESRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_RESRDY;
+	} else {
+		((Adc *)hw)->INTENSET.reg = ADC_INTENSET_RESRDY;
+	}
+}
+
+static inline void hri_adc_clear_INTEN_RESRDY_bit(const void *const hw)
+{
+	((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_RESRDY;
+}
+
+static inline void hri_adc_set_INTEN_OVERRUN_bit(const void *const hw)
+{
+	((Adc *)hw)->INTENSET.reg = ADC_INTENSET_OVERRUN;
+}
+
+static inline bool hri_adc_get_INTEN_OVERRUN_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_OVERRUN) >> ADC_INTENSET_OVERRUN_Pos;
+}
+
+static inline void hri_adc_write_INTEN_OVERRUN_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_OVERRUN;
+	} else {
+		((Adc *)hw)->INTENSET.reg = ADC_INTENSET_OVERRUN;
+	}
+}
+
+static inline void hri_adc_clear_INTEN_OVERRUN_bit(const void *const hw)
+{
+	((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_OVERRUN;
+}
+
+static inline void hri_adc_set_INTEN_WINMON_bit(const void *const hw)
+{
+	((Adc *)hw)->INTENSET.reg = ADC_INTENSET_WINMON;
+}
+
+static inline bool hri_adc_get_INTEN_WINMON_bit(const void *const hw)
+{
+	return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_WINMON) >> ADC_INTENSET_WINMON_Pos;
+}
+
+static inline void hri_adc_write_INTEN_WINMON_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_WINMON;
+	} else {
+		((Adc *)hw)->INTENSET.reg = ADC_INTENSET_WINMON;
+	}
+}
+
+static inline void hri_adc_clear_INTEN_WINMON_bit(const void *const hw)
+{
+	((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_WINMON;
+}
+
+static inline void hri_adc_set_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask)
+{
+	((Adc *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_adc_intenset_reg_t hri_adc_get_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_adc_intenset_reg_t hri_adc_read_INTEN_reg(const void *const hw)
+{
+	return ((Adc *)hw)->INTENSET.reg;
+}
+
+static inline void hri_adc_write_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t data)
+{
+	((Adc *)hw)->INTENSET.reg = data;
+	((Adc *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_adc_clear_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask)
+{
+	((Adc *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_adc_get_SEQSTATUS_SEQBUSY_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SEQSTATUS.reg & ADC_SEQSTATUS_SEQBUSY) >> ADC_SEQSTATUS_SEQBUSY_Pos;
+}
+
+static inline hri_adc_seqstatus_reg_t hri_adc_get_SEQSTATUS_SEQSTATE_bf(const void *const       hw,
+                                                                        hri_adc_seqstatus_reg_t mask)
+{
+	return (((Adc *)hw)->SEQSTATUS.reg & ADC_SEQSTATUS_SEQSTATE(mask)) >> ADC_SEQSTATUS_SEQSTATE_Pos;
+}
+
+static inline hri_adc_seqstatus_reg_t hri_adc_read_SEQSTATUS_SEQSTATE_bf(const void *const hw)
+{
+	return (((Adc *)hw)->SEQSTATUS.reg & ADC_SEQSTATUS_SEQSTATE_Msk) >> ADC_SEQSTATUS_SEQSTATE_Pos;
+}
+
+static inline hri_adc_seqstatus_reg_t hri_adc_get_SEQSTATUS_reg(const void *const hw, hri_adc_seqstatus_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->SEQSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_adc_seqstatus_reg_t hri_adc_read_SEQSTATUS_reg(const void *const hw)
+{
+	return ((Adc *)hw)->SEQSTATUS.reg;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SWRST) >> ADC_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_ENABLE) >> ADC_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_INPUTCTRL_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_INPUTCTRL) >> ADC_SYNCBUSY_INPUTCTRL_Pos;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_CTRLC_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_CTRLC) >> ADC_SYNCBUSY_CTRLC_Pos;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_AVGCTRL_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_AVGCTRL) >> ADC_SYNCBUSY_AVGCTRL_Pos;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_SAMPCTRL_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SAMPCTRL) >> ADC_SYNCBUSY_SAMPCTRL_Pos;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_WINLT_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_WINLT) >> ADC_SYNCBUSY_WINLT_Pos;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_WINUT_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_WINUT) >> ADC_SYNCBUSY_WINUT_Pos;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_GAINCORR_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_GAINCORR) >> ADC_SYNCBUSY_GAINCORR_Pos;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_OFFSETCORR_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_OFFSETCORR) >> ADC_SYNCBUSY_OFFSETCORR_Pos;
+}
+
+static inline bool hri_adc_get_SYNCBUSY_SWTRIG_bit(const void *const hw)
+{
+	return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SWTRIG) >> ADC_SYNCBUSY_SWTRIG_Pos;
+}
+
+static inline hri_adc_syncbusy_reg_t hri_adc_get_SYNCBUSY_reg(const void *const hw, hri_adc_syncbusy_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_adc_syncbusy_reg_t hri_adc_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Adc *)hw)->SYNCBUSY.reg;
+}
+
+static inline hri_adc_result_reg_t hri_adc_get_RESULT_RESULT_bf(const void *const hw, hri_adc_result_reg_t mask)
+{
+	return (((Adc *)hw)->RESULT.reg & ADC_RESULT_RESULT(mask)) >> ADC_RESULT_RESULT_Pos;
+}
+
+static inline hri_adc_result_reg_t hri_adc_read_RESULT_RESULT_bf(const void *const hw)
+{
+	return (((Adc *)hw)->RESULT.reg & ADC_RESULT_RESULT_Msk) >> ADC_RESULT_RESULT_Pos;
+}
+
+static inline hri_adc_result_reg_t hri_adc_get_RESULT_reg(const void *const hw, hri_adc_result_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->RESULT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_adc_result_reg_t hri_adc_read_RESULT_reg(const void *const hw)
+{
+	return ((Adc *)hw)->RESULT.reg;
+}
+
+static inline void hri_adc_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_SWRST;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST);
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp = (tmp & ADC_CTRLA_SWRST) >> ADC_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_ENABLE;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp = (tmp & ADC_CTRLA_ENABLE) >> ADC_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp &= ~ADC_CTRLA_ENABLE;
+	tmp |= value << ADC_CTRLA_ENABLE_Pos;
+	((Adc *)hw)->CTRLA.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_ENABLE;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_ENABLE;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_RUNSTDBY;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp = (tmp & ADC_CTRLA_RUNSTDBY) >> ADC_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp &= ~ADC_CTRLA_RUNSTDBY;
+	tmp |= value << ADC_CTRLA_RUNSTDBY_Pos;
+	((Adc *)hw)->CTRLA.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_RUNSTDBY;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_RUNSTDBY;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_CTRLA_ONDEMAND_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_ONDEMAND;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_CTRLA_ONDEMAND_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp = (tmp & ADC_CTRLA_ONDEMAND) >> ADC_CTRLA_ONDEMAND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_CTRLA_ONDEMAND_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp &= ~ADC_CTRLA_ONDEMAND;
+	tmp |= value << ADC_CTRLA_ONDEMAND_Pos;
+	((Adc *)hw)->CTRLA.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLA_ONDEMAND_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_ONDEMAND;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLA_ONDEMAND_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_ONDEMAND;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg |= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrla_reg_t hri_adc_get_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
+	tmp = ((Adc *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg = data;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg &= ~mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLA.reg ^= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrla_reg_t hri_adc_read_CTRLA_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE);
+	return ((Adc *)hw)->CTRLA.reg;
+}
+
+static inline void hri_adc_set_CTRLB_PRESCALER_bf(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_PRESCALER(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_PRESCALER_bf(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp = (tmp & ADC_CTRLB_PRESCALER(mask)) >> ADC_CTRLB_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_CTRLB_PRESCALER_bf(const void *const hw, hri_adc_ctrlb_reg_t data)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp &= ~ADC_CTRLB_PRESCALER_Msk;
+	tmp |= ADC_CTRLB_PRESCALER(data);
+	((Adc *)hw)->CTRLB.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLB_PRESCALER_bf(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_PRESCALER(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLB_PRESCALER_bf(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_PRESCALER(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_PRESCALER_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp = (tmp & ADC_CTRLB_PRESCALER_Msk) >> ADC_CTRLB_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg |= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg = data;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg &= ~mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLB.reg ^= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_reg(const void *const hw)
+{
+	return ((Adc *)hw)->CTRLB.reg;
+}
+
+static inline void hri_adc_set_REFCTRL_REFCOMP_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg |= ADC_REFCTRL_REFCOMP;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_REFCTRL_REFCOMP_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->REFCTRL.reg;
+	tmp = (tmp & ADC_REFCTRL_REFCOMP) >> ADC_REFCTRL_REFCOMP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_REFCTRL_REFCOMP_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->REFCTRL.reg;
+	tmp &= ~ADC_REFCTRL_REFCOMP;
+	tmp |= value << ADC_REFCTRL_REFCOMP_Pos;
+	((Adc *)hw)->REFCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_REFCTRL_REFCOMP_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg &= ~ADC_REFCTRL_REFCOMP;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_REFCTRL_REFCOMP_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg ^= ADC_REFCTRL_REFCOMP;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg |= ADC_REFCTRL_REFSEL(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_refctrl_reg_t hri_adc_get_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->REFCTRL.reg;
+	tmp = (tmp & ADC_REFCTRL_REFSEL(mask)) >> ADC_REFCTRL_REFSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t data)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->REFCTRL.reg;
+	tmp &= ~ADC_REFCTRL_REFSEL_Msk;
+	tmp |= ADC_REFCTRL_REFSEL(data);
+	((Adc *)hw)->REFCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg &= ~ADC_REFCTRL_REFSEL(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg ^= ADC_REFCTRL_REFSEL(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_refctrl_reg_t hri_adc_read_REFCTRL_REFSEL_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->REFCTRL.reg;
+	tmp = (tmp & ADC_REFCTRL_REFSEL_Msk) >> ADC_REFCTRL_REFSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg |= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_refctrl_reg_t hri_adc_get_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->REFCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg = data;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg &= ~mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->REFCTRL.reg ^= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_refctrl_reg_t hri_adc_read_REFCTRL_reg(const void *const hw)
+{
+	return ((Adc *)hw)->REFCTRL.reg;
+}
+
+static inline void hri_adc_set_EVCTRL_FLUSHEI_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_FLUSHEI;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_EVCTRL_FLUSHEI_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp = (tmp & ADC_EVCTRL_FLUSHEI) >> ADC_EVCTRL_FLUSHEI_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_EVCTRL_FLUSHEI_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp &= ~ADC_EVCTRL_FLUSHEI;
+	tmp |= value << ADC_EVCTRL_FLUSHEI_Pos;
+	((Adc *)hw)->EVCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_EVCTRL_FLUSHEI_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_FLUSHEI;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_EVCTRL_FLUSHEI_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_FLUSHEI;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_EVCTRL_STARTEI_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_STARTEI;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_EVCTRL_STARTEI_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp = (tmp & ADC_EVCTRL_STARTEI) >> ADC_EVCTRL_STARTEI_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_EVCTRL_STARTEI_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp &= ~ADC_EVCTRL_STARTEI;
+	tmp |= value << ADC_EVCTRL_STARTEI_Pos;
+	((Adc *)hw)->EVCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_EVCTRL_STARTEI_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_STARTEI;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_EVCTRL_STARTEI_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_STARTEI;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_EVCTRL_FLUSHINV_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_FLUSHINV;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_EVCTRL_FLUSHINV_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp = (tmp & ADC_EVCTRL_FLUSHINV) >> ADC_EVCTRL_FLUSHINV_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_EVCTRL_FLUSHINV_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp &= ~ADC_EVCTRL_FLUSHINV;
+	tmp |= value << ADC_EVCTRL_FLUSHINV_Pos;
+	((Adc *)hw)->EVCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_EVCTRL_FLUSHINV_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_FLUSHINV;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_EVCTRL_FLUSHINV_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_FLUSHINV;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_EVCTRL_STARTINV_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_STARTINV;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_EVCTRL_STARTINV_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp = (tmp & ADC_EVCTRL_STARTINV) >> ADC_EVCTRL_STARTINV_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_EVCTRL_STARTINV_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp &= ~ADC_EVCTRL_STARTINV;
+	tmp |= value << ADC_EVCTRL_STARTINV_Pos;
+	((Adc *)hw)->EVCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_EVCTRL_STARTINV_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_STARTINV;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_EVCTRL_STARTINV_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_STARTINV;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_EVCTRL_RESRDYEO_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_RESRDYEO;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_EVCTRL_RESRDYEO_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp = (tmp & ADC_EVCTRL_RESRDYEO) >> ADC_EVCTRL_RESRDYEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_EVCTRL_RESRDYEO_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp &= ~ADC_EVCTRL_RESRDYEO;
+	tmp |= value << ADC_EVCTRL_RESRDYEO_Pos;
+	((Adc *)hw)->EVCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_EVCTRL_RESRDYEO_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_RESRDYEO;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_EVCTRL_RESRDYEO_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_RESRDYEO;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_EVCTRL_WINMONEO_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_WINMONEO;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_EVCTRL_WINMONEO_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp = (tmp & ADC_EVCTRL_WINMONEO) >> ADC_EVCTRL_WINMONEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_EVCTRL_WINMONEO_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp &= ~ADC_EVCTRL_WINMONEO;
+	tmp |= value << ADC_EVCTRL_WINMONEO_Pos;
+	((Adc *)hw)->EVCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_EVCTRL_WINMONEO_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_WINMONEO;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_EVCTRL_WINMONEO_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_WINMONEO;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg |= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_evctrl_reg_t hri_adc_get_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg = data;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg &= ~mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->EVCTRL.reg ^= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_evctrl_reg_t hri_adc_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Adc *)hw)->EVCTRL.reg;
+}
+
+static inline void hri_adc_set_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_MUXPOS(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_MUXPOS_bf(const void *const       hw,
+                                                                      hri_adc_inputctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp = (tmp & ADC_INPUTCTRL_MUXPOS(mask)) >> ADC_INPUTCTRL_MUXPOS_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp &= ~ADC_INPUTCTRL_MUXPOS_Msk;
+	tmp |= ADC_INPUTCTRL_MUXPOS(data);
+	((Adc *)hw)->INPUTCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_MUXPOS(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_MUXPOS(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_MUXPOS_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp = (tmp & ADC_INPUTCTRL_MUXPOS_Msk) >> ADC_INPUTCTRL_MUXPOS_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_MUXNEG(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_MUXNEG_bf(const void *const       hw,
+                                                                      hri_adc_inputctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp = (tmp & ADC_INPUTCTRL_MUXNEG(mask)) >> ADC_INPUTCTRL_MUXNEG_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp &= ~ADC_INPUTCTRL_MUXNEG_Msk;
+	tmp |= ADC_INPUTCTRL_MUXNEG(data);
+	((Adc *)hw)->INPUTCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_MUXNEG(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_MUXNEG(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_MUXNEG_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp = (tmp & ADC_INPUTCTRL_MUXNEG_Msk) >> ADC_INPUTCTRL_MUXNEG_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg |= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	tmp = ((Adc *)hw)->INPUTCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg = data;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg &= ~mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->INPUTCTRL.reg ^= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	return ((Adc *)hw)->INPUTCTRL.reg;
+}
+
+static inline void hri_adc_set_CTRLC_DIFFMODE_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_DIFFMODE;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_CTRLC_DIFFMODE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLC.reg;
+	tmp = (tmp & ADC_CTRLC_DIFFMODE) >> ADC_CTRLC_DIFFMODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_CTRLC_DIFFMODE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLC.reg;
+	tmp &= ~ADC_CTRLC_DIFFMODE;
+	tmp |= value << ADC_CTRLC_DIFFMODE_Pos;
+	((Adc *)hw)->CTRLC.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLC_DIFFMODE_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_DIFFMODE;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLC_DIFFMODE_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_DIFFMODE;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_CTRLC_LEFTADJ_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_LEFTADJ;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_CTRLC_LEFTADJ_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLC.reg;
+	tmp = (tmp & ADC_CTRLC_LEFTADJ) >> ADC_CTRLC_LEFTADJ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_CTRLC_LEFTADJ_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLC.reg;
+	tmp &= ~ADC_CTRLC_LEFTADJ;
+	tmp |= value << ADC_CTRLC_LEFTADJ_Pos;
+	((Adc *)hw)->CTRLC.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLC_LEFTADJ_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_LEFTADJ;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLC_LEFTADJ_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_LEFTADJ;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_CTRLC_FREERUN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_FREERUN;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_CTRLC_FREERUN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLC.reg;
+	tmp = (tmp & ADC_CTRLC_FREERUN) >> ADC_CTRLC_FREERUN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_CTRLC_FREERUN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLC.reg;
+	tmp &= ~ADC_CTRLC_FREERUN;
+	tmp |= value << ADC_CTRLC_FREERUN_Pos;
+	((Adc *)hw)->CTRLC.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLC_FREERUN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_FREERUN;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLC_FREERUN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_FREERUN;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_CTRLC_CORREN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_CORREN;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_CTRLC_CORREN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLC.reg;
+	tmp = (tmp & ADC_CTRLC_CORREN) >> ADC_CTRLC_CORREN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_CTRLC_CORREN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLC.reg;
+	tmp &= ~ADC_CTRLC_CORREN;
+	tmp |= value << ADC_CTRLC_CORREN_Pos;
+	((Adc *)hw)->CTRLC.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLC_CORREN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_CORREN;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLC_CORREN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_CORREN;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_CTRLC_R2R_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_R2R;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_CTRLC_R2R_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLC.reg;
+	tmp = (tmp & ADC_CTRLC_R2R) >> ADC_CTRLC_R2R_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_CTRLC_R2R_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLC.reg;
+	tmp &= ~ADC_CTRLC_R2R;
+	tmp |= value << ADC_CTRLC_R2R_Pos;
+	((Adc *)hw)->CTRLC.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLC_R2R_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_R2R;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLC_R2R_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_R2R;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_CTRLC_RESSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_RESSEL(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrlc_reg_t hri_adc_get_CTRLC_RESSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLC.reg;
+	tmp = (tmp & ADC_CTRLC_RESSEL(mask)) >> ADC_CTRLC_RESSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_CTRLC_RESSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLC.reg;
+	tmp &= ~ADC_CTRLC_RESSEL_Msk;
+	tmp |= ADC_CTRLC_RESSEL(data);
+	((Adc *)hw)->CTRLC.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLC_RESSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_RESSEL(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLC_RESSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_RESSEL(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrlc_reg_t hri_adc_read_CTRLC_RESSEL_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLC.reg;
+	tmp = (tmp & ADC_CTRLC_RESSEL_Msk) >> ADC_CTRLC_RESSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_CTRLC_WINMODE_bf(const void *const hw, hri_adc_ctrlc_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_WINMODE(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrlc_reg_t hri_adc_get_CTRLC_WINMODE_bf(const void *const hw, hri_adc_ctrlc_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLC.reg;
+	tmp = (tmp & ADC_CTRLC_WINMODE(mask)) >> ADC_CTRLC_WINMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_CTRLC_WINMODE_bf(const void *const hw, hri_adc_ctrlc_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLC.reg;
+	tmp &= ~ADC_CTRLC_WINMODE_Msk;
+	tmp |= ADC_CTRLC_WINMODE(data);
+	((Adc *)hw)->CTRLC.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLC_WINMODE_bf(const void *const hw, hri_adc_ctrlc_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_WINMODE(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLC_WINMODE_bf(const void *const hw, hri_adc_ctrlc_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_WINMODE(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrlc_reg_t hri_adc_read_CTRLC_WINMODE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLC.reg;
+	tmp = (tmp & ADC_CTRLC_WINMODE_Msk) >> ADC_CTRLC_WINMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_CTRLC_DUALSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_DUALSEL(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrlc_reg_t hri_adc_get_CTRLC_DUALSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLC.reg;
+	tmp = (tmp & ADC_CTRLC_DUALSEL(mask)) >> ADC_CTRLC_DUALSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_CTRLC_DUALSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CTRLC.reg;
+	tmp &= ~ADC_CTRLC_DUALSEL_Msk;
+	tmp |= ADC_CTRLC_DUALSEL(data);
+	((Adc *)hw)->CTRLC.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLC_DUALSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_DUALSEL(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLC_DUALSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_DUALSEL(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrlc_reg_t hri_adc_read_CTRLC_DUALSEL_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CTRLC.reg;
+	tmp = (tmp & ADC_CTRLC_DUALSEL_Msk) >> ADC_CTRLC_DUALSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_CTRLC_reg(const void *const hw, hri_adc_ctrlc_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg |= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrlc_reg_t hri_adc_get_CTRLC_reg(const void *const hw, hri_adc_ctrlc_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	tmp = ((Adc *)hw)->CTRLC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_CTRLC_reg(const void *const hw, hri_adc_ctrlc_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg = data;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CTRLC_reg(const void *const hw, hri_adc_ctrlc_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg &= ~mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CTRLC_reg(const void *const hw, hri_adc_ctrlc_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CTRLC.reg ^= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_ctrlc_reg_t hri_adc_read_CTRLC_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	return ((Adc *)hw)->CTRLC.reg;
+}
+
+static inline void hri_adc_set_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg |= ADC_AVGCTRL_SAMPLENUM(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->AVGCTRL.reg;
+	tmp = (tmp & ADC_AVGCTRL_SAMPLENUM(mask)) >> ADC_AVGCTRL_SAMPLENUM_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t data)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->AVGCTRL.reg;
+	tmp &= ~ADC_AVGCTRL_SAMPLENUM_Msk;
+	tmp |= ADC_AVGCTRL_SAMPLENUM(data);
+	((Adc *)hw)->AVGCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg &= ~ADC_AVGCTRL_SAMPLENUM(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg ^= ADC_AVGCTRL_SAMPLENUM(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_SAMPLENUM_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->AVGCTRL.reg;
+	tmp = (tmp & ADC_AVGCTRL_SAMPLENUM_Msk) >> ADC_AVGCTRL_SAMPLENUM_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg |= ADC_AVGCTRL_ADJRES(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->AVGCTRL.reg;
+	tmp = (tmp & ADC_AVGCTRL_ADJRES(mask)) >> ADC_AVGCTRL_ADJRES_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t data)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->AVGCTRL.reg;
+	tmp &= ~ADC_AVGCTRL_ADJRES_Msk;
+	tmp |= ADC_AVGCTRL_ADJRES(data);
+	((Adc *)hw)->AVGCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg &= ~ADC_AVGCTRL_ADJRES(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg ^= ADC_AVGCTRL_ADJRES(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_ADJRES_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->AVGCTRL.reg;
+	tmp = (tmp & ADC_AVGCTRL_ADJRES_Msk) >> ADC_AVGCTRL_ADJRES_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg |= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	tmp = ((Adc *)hw)->AVGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg = data;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg &= ~mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->AVGCTRL.reg ^= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	return ((Adc *)hw)->AVGCTRL.reg;
+}
+
+static inline void hri_adc_set_SAMPCTRL_OFFCOMP_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg |= ADC_SAMPCTRL_OFFCOMP;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_SAMPCTRL_OFFCOMP_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->SAMPCTRL.reg;
+	tmp = (tmp & ADC_SAMPCTRL_OFFCOMP) >> ADC_SAMPCTRL_OFFCOMP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_SAMPCTRL_OFFCOMP_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->SAMPCTRL.reg;
+	tmp &= ~ADC_SAMPCTRL_OFFCOMP;
+	tmp |= value << ADC_SAMPCTRL_OFFCOMP_Pos;
+	((Adc *)hw)->SAMPCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_SAMPCTRL_OFFCOMP_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg &= ~ADC_SAMPCTRL_OFFCOMP;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_SAMPCTRL_OFFCOMP_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg ^= ADC_SAMPCTRL_OFFCOMP;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg |= ADC_SAMPCTRL_SAMPLEN(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_sampctrl_reg_t hri_adc_get_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->SAMPCTRL.reg;
+	tmp = (tmp & ADC_SAMPCTRL_SAMPLEN(mask)) >> ADC_SAMPCTRL_SAMPLEN_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t data)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->SAMPCTRL.reg;
+	tmp &= ~ADC_SAMPCTRL_SAMPLEN_Msk;
+	tmp |= ADC_SAMPCTRL_SAMPLEN(data);
+	((Adc *)hw)->SAMPCTRL.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg &= ~ADC_SAMPCTRL_SAMPLEN(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg ^= ADC_SAMPCTRL_SAMPLEN(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_sampctrl_reg_t hri_adc_read_SAMPCTRL_SAMPLEN_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->SAMPCTRL.reg;
+	tmp = (tmp & ADC_SAMPCTRL_SAMPLEN_Msk) >> ADC_SAMPCTRL_SAMPLEN_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg |= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_sampctrl_reg_t hri_adc_get_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask)
+{
+	uint8_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	tmp = ((Adc *)hw)->SAMPCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg = data;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg &= ~mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SAMPCTRL.reg ^= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_sampctrl_reg_t hri_adc_read_SAMPCTRL_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	return ((Adc *)hw)->SAMPCTRL.reg;
+}
+
+static inline void hri_adc_set_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINLT.reg |= ADC_WINLT_WINLT(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_winlt_reg_t hri_adc_get_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	tmp = ((Adc *)hw)->WINLT.reg;
+	tmp = (tmp & ADC_WINLT_WINLT(mask)) >> ADC_WINLT_WINLT_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->WINLT.reg;
+	tmp &= ~ADC_WINLT_WINLT_Msk;
+	tmp |= ADC_WINLT_WINLT(data);
+	((Adc *)hw)->WINLT.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINLT.reg &= ~ADC_WINLT_WINLT(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINLT.reg ^= ADC_WINLT_WINLT(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_winlt_reg_t hri_adc_read_WINLT_WINLT_bf(const void *const hw)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	tmp = ((Adc *)hw)->WINLT.reg;
+	tmp = (tmp & ADC_WINLT_WINLT_Msk) >> ADC_WINLT_WINLT_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINLT.reg |= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_winlt_reg_t hri_adc_get_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	tmp = ((Adc *)hw)->WINLT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINLT.reg = data;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINLT.reg &= ~mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINLT.reg ^= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_winlt_reg_t hri_adc_read_WINLT_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT);
+	return ((Adc *)hw)->WINLT.reg;
+}
+
+static inline void hri_adc_set_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINUT.reg |= ADC_WINUT_WINUT(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_winut_reg_t hri_adc_get_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	tmp = ((Adc *)hw)->WINUT.reg;
+	tmp = (tmp & ADC_WINUT_WINUT(mask)) >> ADC_WINUT_WINUT_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->WINUT.reg;
+	tmp &= ~ADC_WINUT_WINUT_Msk;
+	tmp |= ADC_WINUT_WINUT(data);
+	((Adc *)hw)->WINUT.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINUT.reg &= ~ADC_WINUT_WINUT(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINUT.reg ^= ADC_WINUT_WINUT(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_winut_reg_t hri_adc_read_WINUT_WINUT_bf(const void *const hw)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	tmp = ((Adc *)hw)->WINUT.reg;
+	tmp = (tmp & ADC_WINUT_WINUT_Msk) >> ADC_WINUT_WINUT_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINUT.reg |= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_winut_reg_t hri_adc_get_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	tmp = ((Adc *)hw)->WINUT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_WINUT_reg(const void *const hw, hri_adc_winut_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINUT.reg = data;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINUT.reg &= ~mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->WINUT.reg ^= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_winut_reg_t hri_adc_read_WINUT_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT);
+	return ((Adc *)hw)->WINUT.reg;
+}
+
+static inline void hri_adc_set_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->GAINCORR.reg |= ADC_GAINCORR_GAINCORR(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_gaincorr_reg_t hri_adc_get_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	tmp = ((Adc *)hw)->GAINCORR.reg;
+	tmp = (tmp & ADC_GAINCORR_GAINCORR(mask)) >> ADC_GAINCORR_GAINCORR_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->GAINCORR.reg;
+	tmp &= ~ADC_GAINCORR_GAINCORR_Msk;
+	tmp |= ADC_GAINCORR_GAINCORR(data);
+	((Adc *)hw)->GAINCORR.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->GAINCORR.reg &= ~ADC_GAINCORR_GAINCORR(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->GAINCORR.reg ^= ADC_GAINCORR_GAINCORR(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_gaincorr_reg_t hri_adc_read_GAINCORR_GAINCORR_bf(const void *const hw)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	tmp = ((Adc *)hw)->GAINCORR.reg;
+	tmp = (tmp & ADC_GAINCORR_GAINCORR_Msk) >> ADC_GAINCORR_GAINCORR_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->GAINCORR.reg |= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_gaincorr_reg_t hri_adc_get_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	tmp = ((Adc *)hw)->GAINCORR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->GAINCORR.reg = data;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->GAINCORR.reg &= ~mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->GAINCORR.reg ^= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_gaincorr_reg_t hri_adc_read_GAINCORR_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR);
+	return ((Adc *)hw)->GAINCORR.reg;
+}
+
+static inline void hri_adc_set_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->OFFSETCORR.reg |= ADC_OFFSETCORR_OFFSETCORR(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_offsetcorr_reg_t hri_adc_get_OFFSETCORR_OFFSETCORR_bf(const void *const        hw,
+                                                                            hri_adc_offsetcorr_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	tmp = ((Adc *)hw)->OFFSETCORR.reg;
+	tmp = (tmp & ADC_OFFSETCORR_OFFSETCORR(mask)) >> ADC_OFFSETCORR_OFFSETCORR_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->OFFSETCORR.reg;
+	tmp &= ~ADC_OFFSETCORR_OFFSETCORR_Msk;
+	tmp |= ADC_OFFSETCORR_OFFSETCORR(data);
+	((Adc *)hw)->OFFSETCORR.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->OFFSETCORR.reg &= ~ADC_OFFSETCORR_OFFSETCORR(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->OFFSETCORR.reg ^= ADC_OFFSETCORR_OFFSETCORR(mask);
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_offsetcorr_reg_t hri_adc_read_OFFSETCORR_OFFSETCORR_bf(const void *const hw)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	tmp = ((Adc *)hw)->OFFSETCORR.reg;
+	tmp = (tmp & ADC_OFFSETCORR_OFFSETCORR_Msk) >> ADC_OFFSETCORR_OFFSETCORR_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->OFFSETCORR.reg |= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_offsetcorr_reg_t hri_adc_get_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask)
+{
+	uint16_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	tmp = ((Adc *)hw)->OFFSETCORR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->OFFSETCORR.reg = data;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->OFFSETCORR.reg &= ~mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->OFFSETCORR.reg ^= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_offsetcorr_reg_t hri_adc_read_OFFSETCORR_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR);
+	return ((Adc *)hw)->OFFSETCORR.reg;
+}
+
+static inline void hri_adc_set_SWTRIG_FLUSH_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SWTRIG.reg |= ADC_SWTRIG_FLUSH;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_SWTRIG_FLUSH_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->SWTRIG.reg;
+	tmp = (tmp & ADC_SWTRIG_FLUSH) >> ADC_SWTRIG_FLUSH_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_SWTRIG_FLUSH_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->SWTRIG.reg;
+	tmp &= ~ADC_SWTRIG_FLUSH;
+	tmp |= value << ADC_SWTRIG_FLUSH_Pos;
+	((Adc *)hw)->SWTRIG.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_SWTRIG_FLUSH_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SWTRIG.reg &= ~ADC_SWTRIG_FLUSH;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_SWTRIG_FLUSH_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SWTRIG.reg ^= ADC_SWTRIG_FLUSH;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_SWTRIG_START_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SWTRIG.reg |= ADC_SWTRIG_START;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_SWTRIG_START_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->SWTRIG.reg;
+	tmp = (tmp & ADC_SWTRIG_START) >> ADC_SWTRIG_START_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_SWTRIG_START_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->SWTRIG.reg;
+	tmp &= ~ADC_SWTRIG_START;
+	tmp |= value << ADC_SWTRIG_START_Pos;
+	((Adc *)hw)->SWTRIG.reg = tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_SWTRIG_START_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SWTRIG.reg &= ~ADC_SWTRIG_START;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_SWTRIG_START_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SWTRIG.reg ^= ADC_SWTRIG_START;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SWTRIG.reg |= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_swtrig_reg_t hri_adc_get_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask)
+{
+	uint8_t tmp;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	tmp = ((Adc *)hw)->SWTRIG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SWTRIG.reg = data;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SWTRIG.reg &= ~mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SWTRIG.reg ^= mask;
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_swtrig_reg_t hri_adc_read_SWTRIG_reg(const void *const hw)
+{
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK);
+	return ((Adc *)hw)->SWTRIG.reg;
+}
+
+static inline void hri_adc_set_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DBGCTRL.reg |= ADC_DBGCTRL_DBGRUN;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_adc_get_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->DBGCTRL.reg;
+	tmp = (tmp & ADC_DBGCTRL_DBGRUN) >> ADC_DBGCTRL_DBGRUN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_adc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->DBGCTRL.reg;
+	tmp &= ~ADC_DBGCTRL_DBGRUN;
+	tmp |= value << ADC_DBGCTRL_DBGRUN_Pos;
+	((Adc *)hw)->DBGCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DBGCTRL.reg &= ~ADC_DBGCTRL_DBGRUN;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DBGCTRL.reg ^= ADC_DBGCTRL_DBGRUN;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_set_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DBGCTRL.reg |= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_dbgctrl_reg_t hri_adc_get_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Adc *)hw)->DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DBGCTRL.reg = data;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DBGCTRL.reg &= ~mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->DBGCTRL.reg ^= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_dbgctrl_reg_t hri_adc_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Adc *)hw)->DBGCTRL.reg;
+}
+
+static inline void hri_adc_set_SEQCTRL_SEQEN_bf(const void *const hw, hri_adc_seqctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SEQCTRL.reg |= ADC_SEQCTRL_SEQEN(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_seqctrl_reg_t hri_adc_get_SEQCTRL_SEQEN_bf(const void *const hw, hri_adc_seqctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Adc *)hw)->SEQCTRL.reg;
+	tmp = (tmp & ADC_SEQCTRL_SEQEN(mask)) >> ADC_SEQCTRL_SEQEN_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_SEQCTRL_SEQEN_bf(const void *const hw, hri_adc_seqctrl_reg_t data)
+{
+	uint32_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->SEQCTRL.reg;
+	tmp &= ~ADC_SEQCTRL_SEQEN_Msk;
+	tmp |= ADC_SEQCTRL_SEQEN(data);
+	((Adc *)hw)->SEQCTRL.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_SEQCTRL_SEQEN_bf(const void *const hw, hri_adc_seqctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SEQCTRL.reg &= ~ADC_SEQCTRL_SEQEN(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_SEQCTRL_SEQEN_bf(const void *const hw, hri_adc_seqctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SEQCTRL.reg ^= ADC_SEQCTRL_SEQEN(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_seqctrl_reg_t hri_adc_read_SEQCTRL_SEQEN_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Adc *)hw)->SEQCTRL.reg;
+	tmp = (tmp & ADC_SEQCTRL_SEQEN_Msk) >> ADC_SEQCTRL_SEQEN_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_SEQCTRL_reg(const void *const hw, hri_adc_seqctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SEQCTRL.reg |= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_seqctrl_reg_t hri_adc_get_SEQCTRL_reg(const void *const hw, hri_adc_seqctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Adc *)hw)->SEQCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_SEQCTRL_reg(const void *const hw, hri_adc_seqctrl_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SEQCTRL.reg = data;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_SEQCTRL_reg(const void *const hw, hri_adc_seqctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SEQCTRL.reg &= ~mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_SEQCTRL_reg(const void *const hw, hri_adc_seqctrl_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->SEQCTRL.reg ^= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_seqctrl_reg_t hri_adc_read_SEQCTRL_reg(const void *const hw)
+{
+	return ((Adc *)hw)->SEQCTRL.reg;
+}
+
+static inline void hri_adc_set_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg |= ADC_CALIB_BIASCOMP(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_calib_reg_t hri_adc_get_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CALIB.reg;
+	tmp = (tmp & ADC_CALIB_BIASCOMP(mask)) >> ADC_CALIB_BIASCOMP_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CALIB.reg;
+	tmp &= ~ADC_CALIB_BIASCOMP_Msk;
+	tmp |= ADC_CALIB_BIASCOMP(data);
+	((Adc *)hw)->CALIB.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_BIASCOMP(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg ^= ADC_CALIB_BIASCOMP(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_calib_reg_t hri_adc_read_CALIB_BIASCOMP_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CALIB.reg;
+	tmp = (tmp & ADC_CALIB_BIASCOMP_Msk) >> ADC_CALIB_BIASCOMP_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg |= ADC_CALIB_BIASREFBUF(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_calib_reg_t hri_adc_get_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CALIB.reg;
+	tmp = (tmp & ADC_CALIB_BIASREFBUF(mask)) >> ADC_CALIB_BIASREFBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_write_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t data)
+{
+	uint16_t tmp;
+	ADC_CRITICAL_SECTION_ENTER();
+	tmp = ((Adc *)hw)->CALIB.reg;
+	tmp &= ~ADC_CALIB_BIASREFBUF_Msk;
+	tmp |= ADC_CALIB_BIASREFBUF(data);
+	((Adc *)hw)->CALIB.reg = tmp;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_BIASREFBUF(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg ^= ADC_CALIB_BIASREFBUF(mask);
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_calib_reg_t hri_adc_read_CALIB_BIASREFBUF_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CALIB.reg;
+	tmp = (tmp & ADC_CALIB_BIASREFBUF_Msk) >> ADC_CALIB_BIASREFBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_adc_set_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg |= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_calib_reg_t hri_adc_get_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Adc *)hw)->CALIB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_adc_write_CALIB_reg(const void *const hw, hri_adc_calib_reg_t data)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg = data;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_clear_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg &= ~mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_adc_toggle_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask)
+{
+	ADC_CRITICAL_SECTION_ENTER();
+	((Adc *)hw)->CALIB.reg ^= mask;
+	ADC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_adc_calib_reg_t hri_adc_read_CALIB_reg(const void *const hw)
+{
+	return ((Adc *)hw)->CALIB.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_ADC_L22_H_INCLUDED */
+#endif /* _SAML22_ADC_COMPONENT_ */
diff --git a/watch-library/hardware/hri/hri_aes_l22.h b/watch-library/hardware/hri/hri_aes_l22.h
new file mode 100644
index 00000000..f88f081e
--- /dev/null
+++ b/watch-library/hardware/hri/hri_aes_l22.h
@@ -0,0 +1,1213 @@
+/**
+ * \file
+ *
+ * \brief SAM AES
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_AES_COMPONENT_
+#ifndef _HRI_AES_L22_H_INCLUDED_
+#define _HRI_AES_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_AES_CRITICAL_SECTIONS)
+#define AES_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define AES_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define AES_CRITICAL_SECTION_ENTER()
+#define AES_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_aes_ciplen_reg_t;
+typedef uint32_t hri_aes_ctrla_reg_t;
+typedef uint32_t hri_aes_ghash_reg_t;
+typedef uint32_t hri_aes_hashkey_reg_t;
+typedef uint32_t hri_aes_indata_reg_t;
+typedef uint32_t hri_aes_intvectv_reg_t;
+typedef uint32_t hri_aes_keyword_reg_t;
+typedef uint32_t hri_aes_randseed_reg_t;
+typedef uint8_t  hri_aes_ctrlb_reg_t;
+typedef uint8_t  hri_aes_databufptr_reg_t;
+typedef uint8_t  hri_aes_dbgctrl_reg_t;
+typedef uint8_t  hri_aes_intenset_reg_t;
+typedef uint8_t  hri_aes_intflag_reg_t;
+
+static inline bool hri_aes_get_INTFLAG_ENCCMP_bit(const void *const hw)
+{
+	return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_ENCCMP) >> AES_INTFLAG_ENCCMP_Pos;
+}
+
+static inline void hri_aes_clear_INTFLAG_ENCCMP_bit(const void *const hw)
+{
+	((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_ENCCMP;
+}
+
+static inline bool hri_aes_get_INTFLAG_GFMCMP_bit(const void *const hw)
+{
+	return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_GFMCMP) >> AES_INTFLAG_GFMCMP_Pos;
+}
+
+static inline void hri_aes_clear_INTFLAG_GFMCMP_bit(const void *const hw)
+{
+	((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_GFMCMP;
+}
+
+static inline bool hri_aes_get_interrupt_ENCCMP_bit(const void *const hw)
+{
+	return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_ENCCMP) >> AES_INTFLAG_ENCCMP_Pos;
+}
+
+static inline void hri_aes_clear_interrupt_ENCCMP_bit(const void *const hw)
+{
+	((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_ENCCMP;
+}
+
+static inline bool hri_aes_get_interrupt_GFMCMP_bit(const void *const hw)
+{
+	return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_GFMCMP) >> AES_INTFLAG_GFMCMP_Pos;
+}
+
+static inline void hri_aes_clear_interrupt_GFMCMP_bit(const void *const hw)
+{
+	((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_GFMCMP;
+}
+
+static inline hri_aes_intflag_reg_t hri_aes_get_INTFLAG_reg(const void *const hw, hri_aes_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_aes_intflag_reg_t hri_aes_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Aes *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_aes_clear_INTFLAG_reg(const void *const hw, hri_aes_intflag_reg_t mask)
+{
+	((Aes *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_aes_set_INTEN_ENCCMP_bit(const void *const hw)
+{
+	((Aes *)hw)->INTENSET.reg = AES_INTENSET_ENCCMP;
+}
+
+static inline bool hri_aes_get_INTEN_ENCCMP_bit(const void *const hw)
+{
+	return (((Aes *)hw)->INTENSET.reg & AES_INTENSET_ENCCMP) >> AES_INTENSET_ENCCMP_Pos;
+}
+
+static inline void hri_aes_write_INTEN_ENCCMP_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Aes *)hw)->INTENCLR.reg = AES_INTENSET_ENCCMP;
+	} else {
+		((Aes *)hw)->INTENSET.reg = AES_INTENSET_ENCCMP;
+	}
+}
+
+static inline void hri_aes_clear_INTEN_ENCCMP_bit(const void *const hw)
+{
+	((Aes *)hw)->INTENCLR.reg = AES_INTENSET_ENCCMP;
+}
+
+static inline void hri_aes_set_INTEN_GFMCMP_bit(const void *const hw)
+{
+	((Aes *)hw)->INTENSET.reg = AES_INTENSET_GFMCMP;
+}
+
+static inline bool hri_aes_get_INTEN_GFMCMP_bit(const void *const hw)
+{
+	return (((Aes *)hw)->INTENSET.reg & AES_INTENSET_GFMCMP) >> AES_INTENSET_GFMCMP_Pos;
+}
+
+static inline void hri_aes_write_INTEN_GFMCMP_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Aes *)hw)->INTENCLR.reg = AES_INTENSET_GFMCMP;
+	} else {
+		((Aes *)hw)->INTENSET.reg = AES_INTENSET_GFMCMP;
+	}
+}
+
+static inline void hri_aes_clear_INTEN_GFMCMP_bit(const void *const hw)
+{
+	((Aes *)hw)->INTENCLR.reg = AES_INTENSET_GFMCMP;
+}
+
+static inline void hri_aes_set_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t mask)
+{
+	((Aes *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_aes_intenset_reg_t hri_aes_get_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_aes_intenset_reg_t hri_aes_read_INTEN_reg(const void *const hw)
+{
+	return ((Aes *)hw)->INTENSET.reg;
+}
+
+static inline void hri_aes_write_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t data)
+{
+	((Aes *)hw)->INTENSET.reg = data;
+	((Aes *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_aes_clear_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t mask)
+{
+	((Aes *)hw)->INTENCLR.reg = mask;
+}
+
+static inline void hri_aes_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= AES_CTRLA_SWRST;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_SWRST) >> AES_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= AES_CTRLA_ENABLE;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_ENABLE) >> AES_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp &= ~AES_CTRLA_ENABLE;
+	tmp |= value << AES_CTRLA_ENABLE_Pos;
+	((Aes *)hw)->CTRLA.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_ENABLE;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_ENABLE;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_set_CTRLA_CIPHER_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= AES_CTRLA_CIPHER;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_CTRLA_CIPHER_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_CIPHER) >> AES_CTRLA_CIPHER_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_write_CTRLA_CIPHER_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp &= ~AES_CTRLA_CIPHER;
+	tmp |= value << AES_CTRLA_CIPHER_Pos;
+	((Aes *)hw)->CTRLA.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLA_CIPHER_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_CIPHER;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLA_CIPHER_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_CIPHER;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_set_CTRLA_STARTMODE_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= AES_CTRLA_STARTMODE;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_CTRLA_STARTMODE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_STARTMODE) >> AES_CTRLA_STARTMODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_write_CTRLA_STARTMODE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp &= ~AES_CTRLA_STARTMODE;
+	tmp |= value << AES_CTRLA_STARTMODE_Pos;
+	((Aes *)hw)->CTRLA.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLA_STARTMODE_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_STARTMODE;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLA_STARTMODE_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_STARTMODE;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_set_CTRLA_LOD_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= AES_CTRLA_LOD;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_CTRLA_LOD_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_LOD) >> AES_CTRLA_LOD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_write_CTRLA_LOD_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp &= ~AES_CTRLA_LOD;
+	tmp |= value << AES_CTRLA_LOD_Pos;
+	((Aes *)hw)->CTRLA.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLA_LOD_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_LOD;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLA_LOD_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_LOD;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_set_CTRLA_KEYGEN_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= AES_CTRLA_KEYGEN;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_CTRLA_KEYGEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_KEYGEN) >> AES_CTRLA_KEYGEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_write_CTRLA_KEYGEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp &= ~AES_CTRLA_KEYGEN;
+	tmp |= value << AES_CTRLA_KEYGEN_Pos;
+	((Aes *)hw)->CTRLA.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLA_KEYGEN_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_KEYGEN;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLA_KEYGEN_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_KEYGEN;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_set_CTRLA_XORKEY_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= AES_CTRLA_XORKEY;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_CTRLA_XORKEY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_XORKEY) >> AES_CTRLA_XORKEY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_write_CTRLA_XORKEY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp &= ~AES_CTRLA_XORKEY;
+	tmp |= value << AES_CTRLA_XORKEY_Pos;
+	((Aes *)hw)->CTRLA.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLA_XORKEY_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_XORKEY;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLA_XORKEY_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_XORKEY;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_set_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= AES_CTRLA_AESMODE(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_AESMODE(mask)) >> AES_CTRLA_AESMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_aes_write_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp &= ~AES_CTRLA_AESMODE_Msk;
+	tmp |= AES_CTRLA_AESMODE(data);
+	((Aes *)hw)->CTRLA.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_AESMODE(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_AESMODE(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_AESMODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_AESMODE_Msk) >> AES_CTRLA_AESMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_aes_set_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= AES_CTRLA_CFBS(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_CFBS(mask)) >> AES_CTRLA_CFBS_Pos;
+	return tmp;
+}
+
+static inline void hri_aes_write_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp &= ~AES_CTRLA_CFBS_Msk;
+	tmp |= AES_CTRLA_CFBS(data);
+	((Aes *)hw)->CTRLA.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_CFBS(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_CFBS(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_CFBS_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_CFBS_Msk) >> AES_CTRLA_CFBS_Pos;
+	return tmp;
+}
+
+static inline void hri_aes_set_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= AES_CTRLA_KEYSIZE(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_KEYSIZE(mask)) >> AES_CTRLA_KEYSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_aes_write_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp &= ~AES_CTRLA_KEYSIZE_Msk;
+	tmp |= AES_CTRLA_KEYSIZE(data);
+	((Aes *)hw)->CTRLA.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_KEYSIZE(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_KEYSIZE(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_KEYSIZE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_KEYSIZE_Msk) >> AES_CTRLA_KEYSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_aes_set_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= AES_CTRLA_CTYPE(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_CTYPE(mask)) >> AES_CTRLA_CTYPE_Pos;
+	return tmp;
+}
+
+static inline void hri_aes_write_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp &= ~AES_CTRLA_CTYPE_Msk;
+	tmp |= AES_CTRLA_CTYPE(data);
+	((Aes *)hw)->CTRLA.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_CTYPE(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_CTYPE(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_CTYPE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp = (tmp & AES_CTRLA_CTYPE_Msk) >> AES_CTRLA_CTYPE_Pos;
+	return tmp;
+}
+
+static inline void hri_aes_set_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg |= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_aes_write_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t data)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg = data;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg &= ~mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLA.reg ^= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_reg(const void *const hw)
+{
+	return ((Aes *)hw)->CTRLA.reg;
+}
+
+static inline void hri_aes_set_CTRLB_START_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg |= AES_CTRLB_START;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_CTRLB_START_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->CTRLB.reg;
+	tmp = (tmp & AES_CTRLB_START) >> AES_CTRLB_START_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_write_CTRLB_START_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLB.reg;
+	tmp &= ~AES_CTRLB_START;
+	tmp |= value << AES_CTRLB_START_Pos;
+	((Aes *)hw)->CTRLB.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLB_START_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_START;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLB_START_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_START;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_set_CTRLB_NEWMSG_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg |= AES_CTRLB_NEWMSG;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_CTRLB_NEWMSG_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->CTRLB.reg;
+	tmp = (tmp & AES_CTRLB_NEWMSG) >> AES_CTRLB_NEWMSG_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_write_CTRLB_NEWMSG_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLB.reg;
+	tmp &= ~AES_CTRLB_NEWMSG;
+	tmp |= value << AES_CTRLB_NEWMSG_Pos;
+	((Aes *)hw)->CTRLB.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLB_NEWMSG_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_NEWMSG;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLB_NEWMSG_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_NEWMSG;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_set_CTRLB_EOM_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg |= AES_CTRLB_EOM;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_CTRLB_EOM_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->CTRLB.reg;
+	tmp = (tmp & AES_CTRLB_EOM) >> AES_CTRLB_EOM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_write_CTRLB_EOM_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLB.reg;
+	tmp &= ~AES_CTRLB_EOM;
+	tmp |= value << AES_CTRLB_EOM_Pos;
+	((Aes *)hw)->CTRLB.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLB_EOM_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_EOM;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLB_EOM_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_EOM;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_set_CTRLB_GFMUL_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg |= AES_CTRLB_GFMUL;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_aes_get_CTRLB_GFMUL_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->CTRLB.reg;
+	tmp = (tmp & AES_CTRLB_GFMUL) >> AES_CTRLB_GFMUL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_aes_write_CTRLB_GFMUL_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->CTRLB.reg;
+	tmp &= ~AES_CTRLB_GFMUL;
+	tmp |= value << AES_CTRLB_GFMUL_Pos;
+	((Aes *)hw)->CTRLB.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLB_GFMUL_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_GFMUL;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLB_GFMUL_bit(const void *const hw)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_GFMUL;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_set_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg |= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrlb_reg_t hri_aes_get_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_aes_write_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t data)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg = data;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg &= ~mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CTRLB.reg ^= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ctrlb_reg_t hri_aes_read_CTRLB_reg(const void *const hw)
+{
+	return ((Aes *)hw)->CTRLB.reg;
+}
+
+static inline void hri_aes_set_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DATABUFPTR.reg |= AES_DATABUFPTR_INDATAPTR(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_databufptr_reg_t hri_aes_get_DATABUFPTR_INDATAPTR_bf(const void *const        hw,
+                                                                           hri_aes_databufptr_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->DATABUFPTR.reg;
+	tmp = (tmp & AES_DATABUFPTR_INDATAPTR(mask)) >> AES_DATABUFPTR_INDATAPTR_Pos;
+	return tmp;
+}
+
+static inline void hri_aes_write_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t data)
+{
+	uint8_t tmp;
+	AES_CRITICAL_SECTION_ENTER();
+	tmp = ((Aes *)hw)->DATABUFPTR.reg;
+	tmp &= ~AES_DATABUFPTR_INDATAPTR_Msk;
+	tmp |= AES_DATABUFPTR_INDATAPTR(data);
+	((Aes *)hw)->DATABUFPTR.reg = tmp;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DATABUFPTR.reg &= ~AES_DATABUFPTR_INDATAPTR(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DATABUFPTR.reg ^= AES_DATABUFPTR_INDATAPTR(mask);
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_databufptr_reg_t hri_aes_read_DATABUFPTR_INDATAPTR_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->DATABUFPTR.reg;
+	tmp = (tmp & AES_DATABUFPTR_INDATAPTR_Msk) >> AES_DATABUFPTR_INDATAPTR_Pos;
+	return tmp;
+}
+
+static inline void hri_aes_set_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DATABUFPTR.reg |= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_databufptr_reg_t hri_aes_get_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Aes *)hw)->DATABUFPTR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_aes_write_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t data)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DATABUFPTR.reg = data;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DATABUFPTR.reg &= ~mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DATABUFPTR.reg ^= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_databufptr_reg_t hri_aes_read_DATABUFPTR_reg(const void *const hw)
+{
+	return ((Aes *)hw)->DATABUFPTR.reg;
+}
+
+static inline void hri_aes_set_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->INDATA.reg |= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_indata_reg_t hri_aes_get_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->INDATA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_aes_write_INDATA_reg(const void *const hw, hri_aes_indata_reg_t data)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->INDATA.reg = data;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->INDATA.reg &= ~mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->INDATA.reg ^= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_indata_reg_t hri_aes_read_INDATA_reg(const void *const hw)
+{
+	return ((Aes *)hw)->INDATA.reg;
+}
+
+static inline void hri_aes_set_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->HASHKEY[index].reg |= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_hashkey_reg_t hri_aes_get_HASHKEY_reg(const void *const hw, uint8_t index,
+                                                            hri_aes_hashkey_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->HASHKEY[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_aes_write_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t data)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->HASHKEY[index].reg = data;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->HASHKEY[index].reg &= ~mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->HASHKEY[index].reg ^= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_hashkey_reg_t hri_aes_read_HASHKEY_reg(const void *const hw, uint8_t index)
+{
+	return ((Aes *)hw)->HASHKEY[index].reg;
+}
+
+static inline void hri_aes_set_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->GHASH[index].reg |= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ghash_reg_t hri_aes_get_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->GHASH[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_aes_write_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t data)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->GHASH[index].reg = data;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->GHASH[index].reg &= ~mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->GHASH[index].reg ^= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ghash_reg_t hri_aes_read_GHASH_reg(const void *const hw, uint8_t index)
+{
+	return ((Aes *)hw)->GHASH[index].reg;
+}
+
+static inline void hri_aes_set_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CIPLEN.reg |= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ciplen_reg_t hri_aes_get_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->CIPLEN.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_aes_write_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t data)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CIPLEN.reg = data;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CIPLEN.reg &= ~mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->CIPLEN.reg ^= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_ciplen_reg_t hri_aes_read_CIPLEN_reg(const void *const hw)
+{
+	return ((Aes *)hw)->CIPLEN.reg;
+}
+
+static inline void hri_aes_set_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->RANDSEED.reg |= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_randseed_reg_t hri_aes_get_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Aes *)hw)->RANDSEED.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_aes_write_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t data)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->RANDSEED.reg = data;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_clear_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->RANDSEED.reg &= ~mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_toggle_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->RANDSEED.reg ^= mask;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_aes_randseed_reg_t hri_aes_read_RANDSEED_reg(const void *const hw)
+{
+	return ((Aes *)hw)->RANDSEED.reg;
+}
+
+static inline void hri_aes_write_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t data)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->DBGCTRL.reg = data;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_write_KEYWORD_reg(const void *const hw, uint8_t index, hri_aes_keyword_reg_t data)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->KEYWORD[index].reg = data;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_aes_write_INTVECTV_reg(const void *const hw, uint8_t index, hri_aes_intvectv_reg_t data)
+{
+	AES_CRITICAL_SECTION_ENTER();
+	((Aes *)hw)->INTVECTV[index].reg = data;
+	AES_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_AES_L22_H_INCLUDED */
+#endif /* _SAML22_AES_COMPONENT_ */
diff --git a/watch-library/hardware/hri/hri_ccl_l22.h b/watch-library/hardware/hri/hri_ccl_l22.h
new file mode 100644
index 00000000..b510c86a
--- /dev/null
+++ b/watch-library/hardware/hri/hri_ccl_l22.h
@@ -0,0 +1,776 @@
+/**
+ * \file
+ *
+ * \brief SAM CCL
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_CCL_COMPONENT_
+#ifndef _HRI_CCL_L22_H_INCLUDED_
+#define _HRI_CCL_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_CCL_CRITICAL_SECTIONS)
+#define CCL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define CCL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define CCL_CRITICAL_SECTION_ENTER()
+#define CCL_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_ccl_lutctrl_reg_t;
+typedef uint8_t  hri_ccl_ctrl_reg_t;
+typedef uint8_t  hri_ccl_seqctrl_reg_t;
+
+static inline void hri_ccl_set_CTRL_SWRST_bit(const void *const hw)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->CTRL.reg |= CCL_CTRL_SWRST;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ccl_get_CTRL_SWRST_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Ccl *)hw)->CTRL.reg;
+	tmp = (tmp & CCL_CTRL_SWRST) >> CCL_CTRL_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ccl_set_CTRL_ENABLE_bit(const void *const hw)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->CTRL.reg |= CCL_CTRL_ENABLE;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ccl_get_CTRL_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Ccl *)hw)->CTRL.reg;
+	tmp = (tmp & CCL_CTRL_ENABLE) >> CCL_CTRL_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ccl_write_CTRL_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->CTRL.reg;
+	tmp &= ~CCL_CTRL_ENABLE;
+	tmp |= value << CCL_CTRL_ENABLE_Pos;
+	((Ccl *)hw)->CTRL.reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_CTRL_ENABLE_bit(const void *const hw)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->CTRL.reg &= ~CCL_CTRL_ENABLE;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_CTRL_ENABLE_bit(const void *const hw)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->CTRL.reg ^= CCL_CTRL_ENABLE;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_set_CTRL_RUNSTDBY_bit(const void *const hw)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->CTRL.reg |= CCL_CTRL_RUNSTDBY;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ccl_get_CTRL_RUNSTDBY_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Ccl *)hw)->CTRL.reg;
+	tmp = (tmp & CCL_CTRL_RUNSTDBY) >> CCL_CTRL_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ccl_write_CTRL_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->CTRL.reg;
+	tmp &= ~CCL_CTRL_RUNSTDBY;
+	tmp |= value << CCL_CTRL_RUNSTDBY_Pos;
+	((Ccl *)hw)->CTRL.reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_CTRL_RUNSTDBY_bit(const void *const hw)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->CTRL.reg &= ~CCL_CTRL_RUNSTDBY;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_CTRL_RUNSTDBY_bit(const void *const hw)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->CTRL.reg ^= CCL_CTRL_RUNSTDBY;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_set_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->CTRL.reg |= mask;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_ctrl_reg_t hri_ccl_get_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ccl *)hw)->CTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ccl_write_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t data)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->CTRL.reg = data;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->CTRL.reg &= ~mask;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->CTRL.reg ^= mask;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_ctrl_reg_t hri_ccl_read_CTRL_reg(const void *const hw)
+{
+	return ((Ccl *)hw)->CTRL.reg;
+}
+
+static inline void hri_ccl_set_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->SEQCTRL[index].reg |= CCL_SEQCTRL_SEQSEL(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_seqctrl_reg_t hri_ccl_get_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index,
+                                                                  hri_ccl_seqctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ccl *)hw)->SEQCTRL[index].reg;
+	tmp = (tmp & CCL_SEQCTRL_SEQSEL(mask)) >> CCL_SEQCTRL_SEQSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_write_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t data)
+{
+	uint8_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->SEQCTRL[index].reg;
+	tmp &= ~CCL_SEQCTRL_SEQSEL_Msk;
+	tmp |= CCL_SEQCTRL_SEQSEL(data);
+	((Ccl *)hw)->SEQCTRL[index].reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->SEQCTRL[index].reg &= ~CCL_SEQCTRL_SEQSEL(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->SEQCTRL[index].reg ^= CCL_SEQCTRL_SEQSEL(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_seqctrl_reg_t hri_ccl_read_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((Ccl *)hw)->SEQCTRL[index].reg;
+	tmp = (tmp & CCL_SEQCTRL_SEQSEL_Msk) >> CCL_SEQCTRL_SEQSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_set_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->SEQCTRL[index].reg |= mask;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_seqctrl_reg_t hri_ccl_get_SEQCTRL_reg(const void *const hw, uint8_t index,
+                                                            hri_ccl_seqctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Ccl *)hw)->SEQCTRL[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ccl_write_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t data)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->SEQCTRL[index].reg = data;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->SEQCTRL[index].reg &= ~mask;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->SEQCTRL[index].reg ^= mask;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_seqctrl_reg_t hri_ccl_read_SEQCTRL_reg(const void *const hw, uint8_t index)
+{
+	return ((Ccl *)hw)->SEQCTRL[index].reg;
+}
+
+static inline void hri_ccl_set_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_ENABLE;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ccl_get_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_ENABLE) >> CCL_LUTCTRL_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ccl_write_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp &= ~CCL_LUTCTRL_ENABLE;
+	tmp |= value << CCL_LUTCTRL_ENABLE_Pos;
+	((Ccl *)hw)->LUTCTRL[index].reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_ENABLE;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_ENABLE;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_set_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_EDGESEL;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ccl_get_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_EDGESEL) >> CCL_LUTCTRL_EDGESEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ccl_write_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp &= ~CCL_LUTCTRL_EDGESEL;
+	tmp |= value << CCL_LUTCTRL_EDGESEL_Pos;
+	((Ccl *)hw)->LUTCTRL[index].reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_EDGESEL;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_EDGESEL;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_set_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INVEI;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ccl_get_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_INVEI) >> CCL_LUTCTRL_INVEI_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ccl_write_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp &= ~CCL_LUTCTRL_INVEI;
+	tmp |= value << CCL_LUTCTRL_INVEI_Pos;
+	((Ccl *)hw)->LUTCTRL[index].reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INVEI;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INVEI;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_set_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_LUTEI;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ccl_get_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_LUTEI) >> CCL_LUTCTRL_LUTEI_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ccl_write_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp &= ~CCL_LUTCTRL_LUTEI;
+	tmp |= value << CCL_LUTCTRL_LUTEI_Pos;
+	((Ccl *)hw)->LUTCTRL[index].reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_LUTEI;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_LUTEI;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_set_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_LUTEO;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_ccl_get_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_LUTEO) >> CCL_LUTCTRL_LUTEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_ccl_write_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp &= ~CCL_LUTCTRL_LUTEO;
+	tmp |= value << CCL_LUTCTRL_LUTEO_Pos;
+	((Ccl *)hw)->LUTCTRL[index].reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_LUTEO;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_LUTEO;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_set_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_FILTSEL(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index,
+                                                                   hri_ccl_lutctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_FILTSEL(mask)) >> CCL_LUTCTRL_FILTSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_write_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data)
+{
+	uint32_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp &= ~CCL_LUTCTRL_FILTSEL_Msk;
+	tmp |= CCL_LUTCTRL_FILTSEL(data);
+	((Ccl *)hw)->LUTCTRL[index].reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_FILTSEL(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_FILTSEL(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_FILTSEL_Msk) >> CCL_LUTCTRL_FILTSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_set_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL0(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index,
+                                                                  hri_ccl_lutctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_INSEL0(mask)) >> CCL_LUTCTRL_INSEL0_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_write_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data)
+{
+	uint32_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp &= ~CCL_LUTCTRL_INSEL0_Msk;
+	tmp |= CCL_LUTCTRL_INSEL0(data);
+	((Ccl *)hw)->LUTCTRL[index].reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL0(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL0(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_INSEL0_Msk) >> CCL_LUTCTRL_INSEL0_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_set_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL1(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index,
+                                                                  hri_ccl_lutctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_INSEL1(mask)) >> CCL_LUTCTRL_INSEL1_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_write_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data)
+{
+	uint32_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp &= ~CCL_LUTCTRL_INSEL1_Msk;
+	tmp |= CCL_LUTCTRL_INSEL1(data);
+	((Ccl *)hw)->LUTCTRL[index].reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL1(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL1(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_INSEL1_Msk) >> CCL_LUTCTRL_INSEL1_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_set_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL2(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index,
+                                                                  hri_ccl_lutctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_INSEL2(mask)) >> CCL_LUTCTRL_INSEL2_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_write_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data)
+{
+	uint32_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp &= ~CCL_LUTCTRL_INSEL2_Msk;
+	tmp |= CCL_LUTCTRL_INSEL2(data);
+	((Ccl *)hw)->LUTCTRL[index].reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL2(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL2(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_INSEL2_Msk) >> CCL_LUTCTRL_INSEL2_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_set_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_TRUTH(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index,
+                                                                 hri_ccl_lutctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_TRUTH(mask)) >> CCL_LUTCTRL_TRUTH_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_write_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data)
+{
+	uint32_t tmp;
+	CCL_CRITICAL_SECTION_ENTER();
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp &= ~CCL_LUTCTRL_TRUTH_Msk;
+	tmp |= CCL_LUTCTRL_TRUTH(data);
+	((Ccl *)hw)->LUTCTRL[index].reg = tmp;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_TRUTH(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_TRUTH(mask);
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp = (tmp & CCL_LUTCTRL_TRUTH_Msk) >> CCL_LUTCTRL_TRUTH_Pos;
+	return tmp;
+}
+
+static inline void hri_ccl_set_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg |= mask;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_reg(const void *const hw, uint8_t index,
+                                                            hri_ccl_lutctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Ccl *)hw)->LUTCTRL[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_ccl_write_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg = data;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_clear_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg &= ~mask;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_ccl_toggle_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask)
+{
+	CCL_CRITICAL_SECTION_ENTER();
+	((Ccl *)hw)->LUTCTRL[index].reg ^= mask;
+	CCL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_reg(const void *const hw, uint8_t index)
+{
+	return ((Ccl *)hw)->LUTCTRL[index].reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_CCL_L22_H_INCLUDED */
+#endif /* _SAML22_CCL_COMPONENT_ */
diff --git a/watch-library/hardware/hri/hri_dmac_l22.h b/watch-library/hardware/hri/hri_dmac_l22.h
new file mode 100644
index 00000000..a20e28ee
--- /dev/null
+++ b/watch-library/hardware/hri/hri_dmac_l22.h
@@ -0,0 +1,4559 @@
+/**
+ * \file
+ *
+ * \brief SAM DMAC
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_DMAC_COMPONENT_
+#ifndef _HRI_DMAC_L22_H_INCLUDED_
+#define _HRI_DMAC_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_DMAC_CRITICAL_SECTIONS)
+#define DMAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define DMAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define DMAC_CRITICAL_SECTION_ENTER()
+#define DMAC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_dmac_crcctrl_reg_t;
+typedef uint16_t hri_dmac_ctrl_reg_t;
+typedef uint16_t hri_dmac_intpend_reg_t;
+typedef uint16_t hri_dmacdescriptor_btcnt_reg_t;
+typedef uint16_t hri_dmacdescriptor_btctrl_reg_t;
+typedef uint32_t hri_dmac_active_reg_t;
+typedef uint32_t hri_dmac_baseaddr_reg_t;
+typedef uint32_t hri_dmac_busych_reg_t;
+typedef uint32_t hri_dmac_chctrlb_reg_t;
+typedef uint32_t hri_dmac_crcchksum_reg_t;
+typedef uint32_t hri_dmac_crcdatain_reg_t;
+typedef uint32_t hri_dmac_intstatus_reg_t;
+typedef uint32_t hri_dmac_pendch_reg_t;
+typedef uint32_t hri_dmac_prictrl0_reg_t;
+typedef uint32_t hri_dmac_swtrigctrl_reg_t;
+typedef uint32_t hri_dmac_wrbaddr_reg_t;
+typedef uint32_t hri_dmacdescriptor_descaddr_reg_t;
+typedef uint32_t hri_dmacdescriptor_dstaddr_reg_t;
+typedef uint32_t hri_dmacdescriptor_srcaddr_reg_t;
+typedef uint8_t  hri_dmac_chctrla_reg_t;
+typedef uint8_t  hri_dmac_chid_reg_t;
+typedef uint8_t  hri_dmac_chintenset_reg_t;
+typedef uint8_t  hri_dmac_chintflag_reg_t;
+typedef uint8_t  hri_dmac_chstatus_reg_t;
+typedef uint8_t  hri_dmac_crcstatus_reg_t;
+typedef uint8_t  hri_dmac_dbgctrl_reg_t;
+typedef uint8_t  hri_dmac_qosctrl_reg_t;
+
+static inline bool hri_dmac_get_CHINTFLAG_TERR_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos;
+}
+
+static inline void hri_dmac_clear_CHINTFLAG_TERR_bit(const void *const hw)
+{
+	((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TERR;
+}
+
+static inline bool hri_dmac_get_CHINTFLAG_TCMPL_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos;
+}
+
+static inline void hri_dmac_clear_CHINTFLAG_TCMPL_bit(const void *const hw)
+{
+	((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL;
+}
+
+static inline bool hri_dmac_get_CHINTFLAG_SUSP_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos;
+}
+
+static inline void hri_dmac_clear_CHINTFLAG_SUSP_bit(const void *const hw)
+{
+	((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP;
+}
+
+static inline bool hri_dmac_get_interrupt_TERR_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos;
+}
+
+static inline void hri_dmac_clear_interrupt_TERR_bit(const void *const hw)
+{
+	((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TERR;
+}
+
+static inline bool hri_dmac_get_interrupt_TCMPL_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos;
+}
+
+static inline void hri_dmac_clear_interrupt_TCMPL_bit(const void *const hw)
+{
+	((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL;
+}
+
+static inline bool hri_dmac_get_interrupt_SUSP_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos;
+}
+
+static inline void hri_dmac_clear_interrupt_SUSP_bit(const void *const hw)
+{
+	((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP;
+}
+
+static inline hri_dmac_chintflag_reg_t hri_dmac_get_CHINTFLAG_reg(const void *const hw, hri_dmac_chintflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->CHINTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dmac_chintflag_reg_t hri_dmac_read_CHINTFLAG_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->CHINTFLAG.reg;
+}
+
+static inline void hri_dmac_clear_CHINTFLAG_reg(const void *const hw, hri_dmac_chintflag_reg_t mask)
+{
+	((Dmac *)hw)->CHINTFLAG.reg = mask;
+}
+
+static inline void hri_dmac_set_CHINTEN_TERR_bit(const void *const hw)
+{
+	((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TERR;
+}
+
+static inline bool hri_dmac_get_CHINTEN_TERR_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_TERR) >> DMAC_CHINTENSET_TERR_Pos;
+}
+
+static inline void hri_dmac_write_CHINTEN_TERR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TERR;
+	} else {
+		((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TERR;
+	}
+}
+
+static inline void hri_dmac_clear_CHINTEN_TERR_bit(const void *const hw)
+{
+	((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TERR;
+}
+
+static inline void hri_dmac_set_CHINTEN_TCMPL_bit(const void *const hw)
+{
+	((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL;
+}
+
+static inline bool hri_dmac_get_CHINTEN_TCMPL_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_TCMPL) >> DMAC_CHINTENSET_TCMPL_Pos;
+}
+
+static inline void hri_dmac_write_CHINTEN_TCMPL_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL;
+	} else {
+		((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL;
+	}
+}
+
+static inline void hri_dmac_clear_CHINTEN_TCMPL_bit(const void *const hw)
+{
+	((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL;
+}
+
+static inline void hri_dmac_set_CHINTEN_SUSP_bit(const void *const hw)
+{
+	((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_SUSP;
+}
+
+static inline bool hri_dmac_get_CHINTEN_SUSP_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_SUSP) >> DMAC_CHINTENSET_SUSP_Pos;
+}
+
+static inline void hri_dmac_write_CHINTEN_SUSP_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_SUSP;
+	} else {
+		((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_SUSP;
+	}
+}
+
+static inline void hri_dmac_clear_CHINTEN_SUSP_bit(const void *const hw)
+{
+	((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_SUSP;
+}
+
+static inline void hri_dmac_set_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask)
+{
+	((Dmac *)hw)->CHINTENSET.reg = mask;
+}
+
+static inline hri_dmac_chintenset_reg_t hri_dmac_get_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->CHINTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dmac_chintenset_reg_t hri_dmac_read_CHINTEN_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->CHINTENSET.reg;
+}
+
+static inline void hri_dmac_write_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t data)
+{
+	((Dmac *)hw)->CHINTENSET.reg = data;
+	((Dmac *)hw)->CHINTENCLR.reg = ~data;
+}
+
+static inline void hri_dmac_clear_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask)
+{
+	((Dmac *)hw)->CHINTENCLR.reg = mask;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT0_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT0) >> DMAC_INTSTATUS_CHINT0_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT1_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT1) >> DMAC_INTSTATUS_CHINT1_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT2_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT2) >> DMAC_INTSTATUS_CHINT2_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT3_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT3) >> DMAC_INTSTATUS_CHINT3_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT4_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT4) >> DMAC_INTSTATUS_CHINT4_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT5_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT5) >> DMAC_INTSTATUS_CHINT5_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT6_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT6) >> DMAC_INTSTATUS_CHINT6_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT7_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT7) >> DMAC_INTSTATUS_CHINT7_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT8_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT8) >> DMAC_INTSTATUS_CHINT8_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT9_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT9) >> DMAC_INTSTATUS_CHINT9_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT10_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT10) >> DMAC_INTSTATUS_CHINT10_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT11_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT11) >> DMAC_INTSTATUS_CHINT11_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT12_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT12) >> DMAC_INTSTATUS_CHINT12_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT13_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT13) >> DMAC_INTSTATUS_CHINT13_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT14_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT14) >> DMAC_INTSTATUS_CHINT14_Pos;
+}
+
+static inline bool hri_dmac_get_INTSTATUS_CHINT15_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT15) >> DMAC_INTSTATUS_CHINT15_Pos;
+}
+
+static inline hri_dmac_intstatus_reg_t hri_dmac_get_INTSTATUS_reg(const void *const hw, hri_dmac_intstatus_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->INTSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dmac_intstatus_reg_t hri_dmac_read_INTSTATUS_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->INTSTATUS.reg;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH0_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH0) >> DMAC_BUSYCH_BUSYCH0_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH1_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH1) >> DMAC_BUSYCH_BUSYCH1_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH2_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH2) >> DMAC_BUSYCH_BUSYCH2_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH3_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH3) >> DMAC_BUSYCH_BUSYCH3_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH4_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH4) >> DMAC_BUSYCH_BUSYCH4_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH5_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH5) >> DMAC_BUSYCH_BUSYCH5_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH6_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH6) >> DMAC_BUSYCH_BUSYCH6_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH7_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH7) >> DMAC_BUSYCH_BUSYCH7_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH8_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH8) >> DMAC_BUSYCH_BUSYCH8_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH9_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH9) >> DMAC_BUSYCH_BUSYCH9_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH10_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH10) >> DMAC_BUSYCH_BUSYCH10_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH11_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH11) >> DMAC_BUSYCH_BUSYCH11_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH12_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH12) >> DMAC_BUSYCH_BUSYCH12_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH13_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH13) >> DMAC_BUSYCH_BUSYCH13_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH14_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH14) >> DMAC_BUSYCH_BUSYCH14_Pos;
+}
+
+static inline bool hri_dmac_get_BUSYCH_BUSYCH15_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH15) >> DMAC_BUSYCH_BUSYCH15_Pos;
+}
+
+static inline hri_dmac_busych_reg_t hri_dmac_get_BUSYCH_reg(const void *const hw, hri_dmac_busych_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->BUSYCH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dmac_busych_reg_t hri_dmac_read_BUSYCH_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->BUSYCH.reg;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH0_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH0) >> DMAC_PENDCH_PENDCH0_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH1_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH1) >> DMAC_PENDCH_PENDCH1_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH2_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH2) >> DMAC_PENDCH_PENDCH2_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH3_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH3) >> DMAC_PENDCH_PENDCH3_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH4_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH4) >> DMAC_PENDCH_PENDCH4_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH5_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH5) >> DMAC_PENDCH_PENDCH5_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH6_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH6) >> DMAC_PENDCH_PENDCH6_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH7_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH7) >> DMAC_PENDCH_PENDCH7_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH8_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH8) >> DMAC_PENDCH_PENDCH8_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH9_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH9) >> DMAC_PENDCH_PENDCH9_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH10_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH10) >> DMAC_PENDCH_PENDCH10_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH11_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH11) >> DMAC_PENDCH_PENDCH11_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH12_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH12) >> DMAC_PENDCH_PENDCH12_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH13_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH13) >> DMAC_PENDCH_PENDCH13_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH14_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH14) >> DMAC_PENDCH_PENDCH14_Pos;
+}
+
+static inline bool hri_dmac_get_PENDCH_PENDCH15_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH15) >> DMAC_PENDCH_PENDCH15_Pos;
+}
+
+static inline hri_dmac_pendch_reg_t hri_dmac_get_PENDCH_reg(const void *const hw, hri_dmac_pendch_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PENDCH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dmac_pendch_reg_t hri_dmac_read_PENDCH_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->PENDCH.reg;
+}
+
+static inline bool hri_dmac_get_ACTIVE_LVLEX0_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX0) >> DMAC_ACTIVE_LVLEX0_Pos;
+}
+
+static inline bool hri_dmac_get_ACTIVE_LVLEX1_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX1) >> DMAC_ACTIVE_LVLEX1_Pos;
+}
+
+static inline bool hri_dmac_get_ACTIVE_LVLEX2_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX2) >> DMAC_ACTIVE_LVLEX2_Pos;
+}
+
+static inline bool hri_dmac_get_ACTIVE_LVLEX3_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX3) >> DMAC_ACTIVE_LVLEX3_Pos;
+}
+
+static inline bool hri_dmac_get_ACTIVE_ABUSY_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ABUSY) >> DMAC_ACTIVE_ABUSY_Pos;
+}
+
+static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_ID_bf(const void *const hw, hri_dmac_active_reg_t mask)
+{
+	return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ID(mask)) >> DMAC_ACTIVE_ID_Pos;
+}
+
+static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_ID_bf(const void *const hw)
+{
+	return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ID_Msk) >> DMAC_ACTIVE_ID_Pos;
+}
+
+static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_BTCNT_bf(const void *const hw, hri_dmac_active_reg_t mask)
+{
+	return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_BTCNT(mask)) >> DMAC_ACTIVE_BTCNT_Pos;
+}
+
+static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_BTCNT_bf(const void *const hw)
+{
+	return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_BTCNT_Msk) >> DMAC_ACTIVE_BTCNT_Pos;
+}
+
+static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_reg(const void *const hw, hri_dmac_active_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->ACTIVE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->ACTIVE.reg;
+}
+
+static inline bool hri_dmac_get_CHSTATUS_PEND_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_PEND) >> DMAC_CHSTATUS_PEND_Pos;
+}
+
+static inline bool hri_dmac_get_CHSTATUS_BUSY_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_BUSY) >> DMAC_CHSTATUS_BUSY_Pos;
+}
+
+static inline bool hri_dmac_get_CHSTATUS_FERR_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_FERR) >> DMAC_CHSTATUS_FERR_Pos;
+}
+
+static inline hri_dmac_chstatus_reg_t hri_dmac_get_CHSTATUS_reg(const void *const hw, hri_dmac_chstatus_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->CHSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dmac_chstatus_reg_t hri_dmac_read_CHSTATUS_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->CHSTATUS.reg;
+}
+
+static inline void hri_dmac_set_CTRL_SWRST_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_SWRST;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CTRL_SWRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp = (tmp & DMAC_CTRL_SWRST) >> DMAC_CTRL_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_set_CTRL_DMAENABLE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_DMAENABLE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CTRL_DMAENABLE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp = (tmp & DMAC_CTRL_DMAENABLE) >> DMAC_CTRL_DMAENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CTRL_DMAENABLE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp &= ~DMAC_CTRL_DMAENABLE;
+	tmp |= value << DMAC_CTRL_DMAENABLE_Pos;
+	((Dmac *)hw)->CTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CTRL_DMAENABLE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_DMAENABLE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CTRL_DMAENABLE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_DMAENABLE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CTRL_CRCENABLE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_CRCENABLE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CTRL_CRCENABLE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp = (tmp & DMAC_CTRL_CRCENABLE) >> DMAC_CTRL_CRCENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CTRL_CRCENABLE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp &= ~DMAC_CTRL_CRCENABLE;
+	tmp |= value << DMAC_CTRL_CRCENABLE_Pos;
+	((Dmac *)hw)->CTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CTRL_CRCENABLE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_CRCENABLE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CTRL_CRCENABLE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_CRCENABLE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CTRL_LVLEN0_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN0;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CTRL_LVLEN0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp = (tmp & DMAC_CTRL_LVLEN0) >> DMAC_CTRL_LVLEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CTRL_LVLEN0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp &= ~DMAC_CTRL_LVLEN0;
+	tmp |= value << DMAC_CTRL_LVLEN0_Pos;
+	((Dmac *)hw)->CTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CTRL_LVLEN0_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN0;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CTRL_LVLEN0_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN0;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CTRL_LVLEN1_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN1;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CTRL_LVLEN1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp = (tmp & DMAC_CTRL_LVLEN1) >> DMAC_CTRL_LVLEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CTRL_LVLEN1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp &= ~DMAC_CTRL_LVLEN1;
+	tmp |= value << DMAC_CTRL_LVLEN1_Pos;
+	((Dmac *)hw)->CTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CTRL_LVLEN1_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN1;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CTRL_LVLEN1_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN1;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CTRL_LVLEN2_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN2;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CTRL_LVLEN2_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp = (tmp & DMAC_CTRL_LVLEN2) >> DMAC_CTRL_LVLEN2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CTRL_LVLEN2_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp &= ~DMAC_CTRL_LVLEN2;
+	tmp |= value << DMAC_CTRL_LVLEN2_Pos;
+	((Dmac *)hw)->CTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CTRL_LVLEN2_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN2;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CTRL_LVLEN2_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN2;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CTRL_LVLEN3_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN3;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CTRL_LVLEN3_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp = (tmp & DMAC_CTRL_LVLEN3) >> DMAC_CTRL_LVLEN3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CTRL_LVLEN3_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp &= ~DMAC_CTRL_LVLEN3;
+	tmp |= value << DMAC_CTRL_LVLEN3_Pos;
+	((Dmac *)hw)->CTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CTRL_LVLEN3_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN3;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CTRL_LVLEN3_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN3;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_ctrl_reg_t hri_dmac_get_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CTRL.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_ctrl_reg_t hri_dmac_read_CTRL_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->CTRL.reg;
+}
+
+static inline void hri_dmac_set_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCBEATSIZE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCBEATSIZE_bf(const void *const      hw,
+                                                                         hri_dmac_crcctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp = (tmp & DMAC_CRCCTRL_CRCBEATSIZE(mask)) >> DMAC_CRCCTRL_CRCBEATSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp &= ~DMAC_CRCCTRL_CRCBEATSIZE_Msk;
+	tmp |= DMAC_CRCCTRL_CRCBEATSIZE(data);
+	((Dmac *)hw)->CRCCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCBEATSIZE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCBEATSIZE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCBEATSIZE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp = (tmp & DMAC_CRCCTRL_CRCBEATSIZE_Msk) >> DMAC_CRCCTRL_CRCBEATSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCPOLY(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp = (tmp & DMAC_CRCCTRL_CRCPOLY(mask)) >> DMAC_CRCCTRL_CRCPOLY_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp &= ~DMAC_CRCCTRL_CRCPOLY_Msk;
+	tmp |= DMAC_CRCCTRL_CRCPOLY(data);
+	((Dmac *)hw)->CRCCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCPOLY(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCPOLY(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCPOLY_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp = (tmp & DMAC_CRCCTRL_CRCPOLY_Msk) >> DMAC_CRCCTRL_CRCPOLY_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCSRC(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp = (tmp & DMAC_CRCCTRL_CRCSRC(mask)) >> DMAC_CRCCTRL_CRCSRC_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp &= ~DMAC_CRCCTRL_CRCSRC_Msk;
+	tmp |= DMAC_CRCCTRL_CRCSRC(data);
+	((Dmac *)hw)->CRCCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCSRC(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCSRC(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCSRC_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp = (tmp & DMAC_CRCCTRL_CRCSRC_Msk) >> DMAC_CRCCTRL_CRCSRC_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->CRCCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCTRL.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->CRCCTRL.reg;
+}
+
+static inline void hri_dmac_set_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCDATAIN.reg |= DMAC_CRCDATAIN_CRCDATAIN(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcdatain_reg_t hri_dmac_get_CRCDATAIN_CRCDATAIN_bf(const void *const        hw,
+                                                                           hri_dmac_crcdatain_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CRCDATAIN.reg;
+	tmp = (tmp & DMAC_CRCDATAIN_CRCDATAIN(mask)) >> DMAC_CRCDATAIN_CRCDATAIN_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CRCDATAIN.reg;
+	tmp &= ~DMAC_CRCDATAIN_CRCDATAIN_Msk;
+	tmp |= DMAC_CRCDATAIN_CRCDATAIN(data);
+	((Dmac *)hw)->CRCDATAIN.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCDATAIN.reg &= ~DMAC_CRCDATAIN_CRCDATAIN(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCDATAIN.reg ^= DMAC_CRCDATAIN_CRCDATAIN(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcdatain_reg_t hri_dmac_read_CRCDATAIN_CRCDATAIN_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CRCDATAIN.reg;
+	tmp = (tmp & DMAC_CRCDATAIN_CRCDATAIN_Msk) >> DMAC_CRCDATAIN_CRCDATAIN_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCDATAIN.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcdatain_reg_t hri_dmac_get_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CRCDATAIN.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCDATAIN.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCDATAIN.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCDATAIN.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcdatain_reg_t hri_dmac_read_CRCDATAIN_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->CRCDATAIN.reg;
+}
+
+static inline void hri_dmac_set_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCHKSUM.reg |= DMAC_CRCCHKSUM_CRCCHKSUM(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcchksum_reg_t hri_dmac_get_CRCCHKSUM_CRCCHKSUM_bf(const void *const        hw,
+                                                                           hri_dmac_crcchksum_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CRCCHKSUM.reg;
+	tmp = (tmp & DMAC_CRCCHKSUM_CRCCHKSUM(mask)) >> DMAC_CRCCHKSUM_CRCCHKSUM_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CRCCHKSUM.reg;
+	tmp &= ~DMAC_CRCCHKSUM_CRCCHKSUM_Msk;
+	tmp |= DMAC_CRCCHKSUM_CRCCHKSUM(data);
+	((Dmac *)hw)->CRCCHKSUM.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCHKSUM.reg &= ~DMAC_CRCCHKSUM_CRCCHKSUM(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCHKSUM.reg ^= DMAC_CRCCHKSUM_CRCCHKSUM(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcchksum_reg_t hri_dmac_read_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CRCCHKSUM.reg;
+	tmp = (tmp & DMAC_CRCCHKSUM_CRCCHKSUM_Msk) >> DMAC_CRCCHKSUM_CRCCHKSUM_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCHKSUM.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcchksum_reg_t hri_dmac_get_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CRCCHKSUM.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCHKSUM.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCHKSUM.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCCHKSUM.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcchksum_reg_t hri_dmac_read_CRCCHKSUM_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->CRCCHKSUM.reg;
+}
+
+static inline void hri_dmac_set_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->DBGCTRL.reg |= DMAC_DBGCTRL_DBGRUN;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->DBGCTRL.reg;
+	tmp = (tmp & DMAC_DBGCTRL_DBGRUN) >> DMAC_DBGCTRL_DBGRUN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->DBGCTRL.reg;
+	tmp &= ~DMAC_DBGCTRL_DBGRUN;
+	tmp |= value << DMAC_DBGCTRL_DBGRUN_Pos;
+	((Dmac *)hw)->DBGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->DBGCTRL.reg &= ~DMAC_DBGCTRL_DBGRUN;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->DBGCTRL.reg ^= DMAC_DBGCTRL_DBGRUN;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->DBGCTRL.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_dbgctrl_reg_t hri_dmac_get_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->DBGCTRL.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->DBGCTRL.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->DBGCTRL.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_dbgctrl_reg_t hri_dmac_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->DBGCTRL.reg;
+}
+
+static inline void hri_dmac_set_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->QOSCTRL.reg |= DMAC_QOSCTRL_WRBQOS(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_qosctrl_reg_t hri_dmac_get_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->QOSCTRL.reg;
+	tmp = (tmp & DMAC_QOSCTRL_WRBQOS(mask)) >> DMAC_QOSCTRL_WRBQOS_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t data)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->QOSCTRL.reg;
+	tmp &= ~DMAC_QOSCTRL_WRBQOS_Msk;
+	tmp |= DMAC_QOSCTRL_WRBQOS(data);
+	((Dmac *)hw)->QOSCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->QOSCTRL.reg &= ~DMAC_QOSCTRL_WRBQOS(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->QOSCTRL.reg ^= DMAC_QOSCTRL_WRBQOS(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_qosctrl_reg_t hri_dmac_read_QOSCTRL_WRBQOS_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->QOSCTRL.reg;
+	tmp = (tmp & DMAC_QOSCTRL_WRBQOS_Msk) >> DMAC_QOSCTRL_WRBQOS_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->QOSCTRL.reg |= DMAC_QOSCTRL_FQOS(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_qosctrl_reg_t hri_dmac_get_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->QOSCTRL.reg;
+	tmp = (tmp & DMAC_QOSCTRL_FQOS(mask)) >> DMAC_QOSCTRL_FQOS_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t data)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->QOSCTRL.reg;
+	tmp &= ~DMAC_QOSCTRL_FQOS_Msk;
+	tmp |= DMAC_QOSCTRL_FQOS(data);
+	((Dmac *)hw)->QOSCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->QOSCTRL.reg &= ~DMAC_QOSCTRL_FQOS(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->QOSCTRL.reg ^= DMAC_QOSCTRL_FQOS(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_qosctrl_reg_t hri_dmac_read_QOSCTRL_FQOS_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->QOSCTRL.reg;
+	tmp = (tmp & DMAC_QOSCTRL_FQOS_Msk) >> DMAC_QOSCTRL_FQOS_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->QOSCTRL.reg |= DMAC_QOSCTRL_DQOS(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_qosctrl_reg_t hri_dmac_get_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->QOSCTRL.reg;
+	tmp = (tmp & DMAC_QOSCTRL_DQOS(mask)) >> DMAC_QOSCTRL_DQOS_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t data)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->QOSCTRL.reg;
+	tmp &= ~DMAC_QOSCTRL_DQOS_Msk;
+	tmp |= DMAC_QOSCTRL_DQOS(data);
+	((Dmac *)hw)->QOSCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->QOSCTRL.reg &= ~DMAC_QOSCTRL_DQOS(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->QOSCTRL.reg ^= DMAC_QOSCTRL_DQOS(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_qosctrl_reg_t hri_dmac_read_QOSCTRL_DQOS_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->QOSCTRL.reg;
+	tmp = (tmp & DMAC_QOSCTRL_DQOS_Msk) >> DMAC_QOSCTRL_DQOS_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->QOSCTRL.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_qosctrl_reg_t hri_dmac_get_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->QOSCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->QOSCTRL.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->QOSCTRL.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->QOSCTRL.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_qosctrl_reg_t hri_dmac_read_QOSCTRL_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->QOSCTRL.reg;
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG0_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG0;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG0) >> DMAC_SWTRIGCTRL_SWTRIG0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG0;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG0_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG0_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG0;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG0_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG0;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG1_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG1;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG1) >> DMAC_SWTRIGCTRL_SWTRIG1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG1;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG1_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG1_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG1;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG1_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG1;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG2_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG2;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG2) >> DMAC_SWTRIGCTRL_SWTRIG2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG2;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG2_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG2_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG2;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG2_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG2;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG3_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG3;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG3) >> DMAC_SWTRIGCTRL_SWTRIG3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG3;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG3_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG3_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG3;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG3_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG3;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG4_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG4;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG4) >> DMAC_SWTRIGCTRL_SWTRIG4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG4;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG4_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG4_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG4;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG4_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG4;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG5_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG5;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG5) >> DMAC_SWTRIGCTRL_SWTRIG5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG5;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG5_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG5_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG5;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG5_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG5;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG6_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG6;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG6) >> DMAC_SWTRIGCTRL_SWTRIG6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG6;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG6_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG6_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG6;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG6_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG6;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG7_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG7;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG7) >> DMAC_SWTRIGCTRL_SWTRIG7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG7;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG7_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG7_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG7;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG7_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG7;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG8_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG8;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG8_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG8) >> DMAC_SWTRIGCTRL_SWTRIG8_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG8_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG8;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG8_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG8_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG8;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG8_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG8;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG9_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG9;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG9_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG9) >> DMAC_SWTRIGCTRL_SWTRIG9_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG9_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG9;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG9_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG9_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG9;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG9_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG9;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG10_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG10;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG10_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG10) >> DMAC_SWTRIGCTRL_SWTRIG10_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG10_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG10;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG10_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG10_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG10;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG10_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG10;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG11_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG11;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG11_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG11) >> DMAC_SWTRIGCTRL_SWTRIG11_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG11_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG11;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG11_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG11_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG11;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG11_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG11;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG12_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG12;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG12_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG12) >> DMAC_SWTRIGCTRL_SWTRIG12_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG12_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG12;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG12_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG12_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG12;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG12_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG12;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG13_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG13;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG13_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG13) >> DMAC_SWTRIGCTRL_SWTRIG13_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG13_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG13;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG13_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG13_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG13;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG13_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG13;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG14_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG14;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG14_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG14) >> DMAC_SWTRIGCTRL_SWTRIG14_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG14_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG14;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG14_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG14_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG14;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG14_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG14;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG15_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG15;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG15_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG15) >> DMAC_SWTRIGCTRL_SWTRIG15_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG15_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= ~DMAC_SWTRIGCTRL_SWTRIG15;
+	tmp |= value << DMAC_SWTRIGCTRL_SWTRIG15_Pos;
+	((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG15_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG15;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG15_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG15;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_swtrigctrl_reg_t hri_dmac_get_SWTRIGCTRL_reg(const void *const         hw,
+                                                                    hri_dmac_swtrigctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->SWTRIGCTRL.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_swtrigctrl_reg_t hri_dmac_read_SWTRIGCTRL_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->SWTRIGCTRL.reg;
+}
+
+static inline void hri_dmac_set_PRICTRL0_RRLVLEN0_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN0;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_PRICTRL0_RRLVLEN0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_RRLVLEN0) >> DMAC_PRICTRL0_RRLVLEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_RRLVLEN0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_RRLVLEN0;
+	tmp |= value << DMAC_PRICTRL0_RRLVLEN0_Pos;
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_RRLVLEN0_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN0;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN0_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN0;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_PRICTRL0_RRLVLEN1_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN1;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_PRICTRL0_RRLVLEN1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_RRLVLEN1) >> DMAC_PRICTRL0_RRLVLEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_RRLVLEN1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_RRLVLEN1;
+	tmp |= value << DMAC_PRICTRL0_RRLVLEN1_Pos;
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_RRLVLEN1_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN1;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN1_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN1;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_PRICTRL0_RRLVLEN2_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN2;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_PRICTRL0_RRLVLEN2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_RRLVLEN2) >> DMAC_PRICTRL0_RRLVLEN2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_RRLVLEN2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_RRLVLEN2;
+	tmp |= value << DMAC_PRICTRL0_RRLVLEN2_Pos;
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_RRLVLEN2_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN2;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN2_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN2;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_PRICTRL0_RRLVLEN3_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN3;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_PRICTRL0_RRLVLEN3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_RRLVLEN3) >> DMAC_PRICTRL0_RRLVLEN3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_RRLVLEN3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_RRLVLEN3;
+	tmp |= value << DMAC_PRICTRL0_RRLVLEN3_Pos;
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_RRLVLEN3_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN3;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN3_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN3;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI0(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI0_bf(const void *const       hw,
+                                                                       hri_dmac_prictrl0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_LVLPRI0(mask)) >> DMAC_PRICTRL0_LVLPRI0_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_LVLPRI0_Msk;
+	tmp |= DMAC_PRICTRL0_LVLPRI0(data);
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI0(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI0(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI0_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_LVLPRI0_Msk) >> DMAC_PRICTRL0_LVLPRI0_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI1(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI1_bf(const void *const       hw,
+                                                                       hri_dmac_prictrl0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_LVLPRI1(mask)) >> DMAC_PRICTRL0_LVLPRI1_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_LVLPRI1_Msk;
+	tmp |= DMAC_PRICTRL0_LVLPRI1(data);
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI1(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI1(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI1_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_LVLPRI1_Msk) >> DMAC_PRICTRL0_LVLPRI1_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI2(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI2_bf(const void *const       hw,
+                                                                       hri_dmac_prictrl0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_LVLPRI2(mask)) >> DMAC_PRICTRL0_LVLPRI2_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_LVLPRI2_Msk;
+	tmp |= DMAC_PRICTRL0_LVLPRI2(data);
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI2(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI2(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI2_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_LVLPRI2_Msk) >> DMAC_PRICTRL0_LVLPRI2_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI3(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI3_bf(const void *const       hw,
+                                                                       hri_dmac_prictrl0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_LVLPRI3(mask)) >> DMAC_PRICTRL0_LVLPRI3_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= ~DMAC_PRICTRL0_LVLPRI3_Msk;
+	tmp |= DMAC_PRICTRL0_LVLPRI3(data);
+	((Dmac *)hw)->PRICTRL0.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI3(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI3(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI3_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp = (tmp & DMAC_PRICTRL0_LVLPRI3_Msk) >> DMAC_PRICTRL0_LVLPRI3_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->PRICTRL0.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->PRICTRL0.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->PRICTRL0.reg;
+}
+
+static inline void hri_dmac_set_INTPEND_TERR_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_TERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_INTPEND_TERR_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp = (tmp & DMAC_INTPEND_TERR) >> DMAC_INTPEND_TERR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_INTPEND_TERR_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp &= ~DMAC_INTPEND_TERR;
+	tmp |= value << DMAC_INTPEND_TERR_Pos;
+	((Dmac *)hw)->INTPEND.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_INTPEND_TERR_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_TERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_INTPEND_TERR_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_TERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_INTPEND_TCMPL_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_TCMPL;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_INTPEND_TCMPL_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp = (tmp & DMAC_INTPEND_TCMPL) >> DMAC_INTPEND_TCMPL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_INTPEND_TCMPL_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp &= ~DMAC_INTPEND_TCMPL;
+	tmp |= value << DMAC_INTPEND_TCMPL_Pos;
+	((Dmac *)hw)->INTPEND.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_INTPEND_TCMPL_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_TCMPL;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_INTPEND_TCMPL_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_TCMPL;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_INTPEND_SUSP_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_SUSP;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_INTPEND_SUSP_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp = (tmp & DMAC_INTPEND_SUSP) >> DMAC_INTPEND_SUSP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_INTPEND_SUSP_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp &= ~DMAC_INTPEND_SUSP;
+	tmp |= value << DMAC_INTPEND_SUSP_Pos;
+	((Dmac *)hw)->INTPEND.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_INTPEND_SUSP_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_SUSP;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_INTPEND_SUSP_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_SUSP;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_INTPEND_FERR_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_FERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_INTPEND_FERR_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp = (tmp & DMAC_INTPEND_FERR) >> DMAC_INTPEND_FERR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_INTPEND_FERR_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp &= ~DMAC_INTPEND_FERR;
+	tmp |= value << DMAC_INTPEND_FERR_Pos;
+	((Dmac *)hw)->INTPEND.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_INTPEND_FERR_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_FERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_INTPEND_FERR_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_FERR;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_INTPEND_BUSY_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_BUSY;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_INTPEND_BUSY_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp = (tmp & DMAC_INTPEND_BUSY) >> DMAC_INTPEND_BUSY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_INTPEND_BUSY_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp &= ~DMAC_INTPEND_BUSY;
+	tmp |= value << DMAC_INTPEND_BUSY_Pos;
+	((Dmac *)hw)->INTPEND.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_INTPEND_BUSY_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_BUSY;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_INTPEND_BUSY_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_BUSY;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_INTPEND_PEND_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_PEND;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_INTPEND_PEND_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp = (tmp & DMAC_INTPEND_PEND) >> DMAC_INTPEND_PEND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_INTPEND_PEND_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp &= ~DMAC_INTPEND_PEND;
+	tmp |= value << DMAC_INTPEND_PEND_Pos;
+	((Dmac *)hw)->INTPEND.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_INTPEND_PEND_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_PEND;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_INTPEND_PEND_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_PEND;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_ID(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_intpend_reg_t hri_dmac_get_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp = (tmp & DMAC_INTPEND_ID(mask)) >> DMAC_INTPEND_ID_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp &= ~DMAC_INTPEND_ID_Msk;
+	tmp |= DMAC_INTPEND_ID(data);
+	((Dmac *)hw)->INTPEND.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_ID(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_ID(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_intpend_reg_t hri_dmac_read_INTPEND_ID_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp = (tmp & DMAC_INTPEND_ID_Msk) >> DMAC_INTPEND_ID_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_intpend_reg_t hri_dmac_get_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Dmac *)hw)->INTPEND.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->INTPEND.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_intpend_reg_t hri_dmac_read_INTPEND_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->INTPEND.reg;
+}
+
+static inline void hri_dmac_set_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->BASEADDR.reg |= DMAC_BASEADDR_BASEADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_baseaddr_reg_t hri_dmac_get_BASEADDR_BASEADDR_bf(const void *const       hw,
+                                                                        hri_dmac_baseaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->BASEADDR.reg;
+	tmp = (tmp & DMAC_BASEADDR_BASEADDR(mask)) >> DMAC_BASEADDR_BASEADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->BASEADDR.reg;
+	tmp &= ~DMAC_BASEADDR_BASEADDR_Msk;
+	tmp |= DMAC_BASEADDR_BASEADDR(data);
+	((Dmac *)hw)->BASEADDR.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->BASEADDR.reg &= ~DMAC_BASEADDR_BASEADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->BASEADDR.reg ^= DMAC_BASEADDR_BASEADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_baseaddr_reg_t hri_dmac_read_BASEADDR_BASEADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->BASEADDR.reg;
+	tmp = (tmp & DMAC_BASEADDR_BASEADDR_Msk) >> DMAC_BASEADDR_BASEADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->BASEADDR.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_baseaddr_reg_t hri_dmac_get_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->BASEADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->BASEADDR.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->BASEADDR.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->BASEADDR.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_baseaddr_reg_t hri_dmac_read_BASEADDR_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->BASEADDR.reg;
+}
+
+static inline void hri_dmac_set_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->WRBADDR.reg |= DMAC_WRBADDR_WRBADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_wrbaddr_reg_t hri_dmac_get_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->WRBADDR.reg;
+	tmp = (tmp & DMAC_WRBADDR_WRBADDR(mask)) >> DMAC_WRBADDR_WRBADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->WRBADDR.reg;
+	tmp &= ~DMAC_WRBADDR_WRBADDR_Msk;
+	tmp |= DMAC_WRBADDR_WRBADDR(data);
+	((Dmac *)hw)->WRBADDR.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->WRBADDR.reg &= ~DMAC_WRBADDR_WRBADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->WRBADDR.reg ^= DMAC_WRBADDR_WRBADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_wrbaddr_reg_t hri_dmac_read_WRBADDR_WRBADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->WRBADDR.reg;
+	tmp = (tmp & DMAC_WRBADDR_WRBADDR_Msk) >> DMAC_WRBADDR_WRBADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->WRBADDR.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_wrbaddr_reg_t hri_dmac_get_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->WRBADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->WRBADDR.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->WRBADDR.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->WRBADDR.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_wrbaddr_reg_t hri_dmac_read_WRBADDR_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->WRBADDR.reg;
+}
+
+static inline void hri_dmac_set_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHID.reg |= DMAC_CHID_ID(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chid_reg_t hri_dmac_get_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->CHID.reg;
+	tmp = (tmp & DMAC_CHID_ID(mask)) >> DMAC_CHID_ID_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t data)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CHID.reg;
+	tmp &= ~DMAC_CHID_ID_Msk;
+	tmp |= DMAC_CHID_ID(data);
+	((Dmac *)hw)->CHID.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHID.reg &= ~DMAC_CHID_ID(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHID.reg ^= DMAC_CHID_ID(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chid_reg_t hri_dmac_read_CHID_ID_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->CHID.reg;
+	tmp = (tmp & DMAC_CHID_ID_Msk) >> DMAC_CHID_ID_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CHID_reg(const void *const hw, hri_dmac_chid_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHID.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chid_reg_t hri_dmac_get_CHID_reg(const void *const hw, hri_dmac_chid_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->CHID.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHID_reg(const void *const hw, hri_dmac_chid_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHID.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHID_reg(const void *const hw, hri_dmac_chid_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHID.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHID_reg(const void *const hw, hri_dmac_chid_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHID.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chid_reg_t hri_dmac_read_CHID_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->CHID.reg;
+}
+
+static inline void hri_dmac_set_CHCTRLA_SWRST_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_SWRST;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CHCTRLA_SWRST_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_SWRST) >> DMAC_CHCTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_set_CHCTRLA_ENABLE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CHCTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_ENABLE) >> DMAC_CHCTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CHCTRLA.reg;
+	tmp &= ~DMAC_CHCTRLA_ENABLE;
+	tmp |= value << DMAC_CHCTRLA_ENABLE_Pos;
+	((Dmac *)hw)->CHCTRLA.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLA_ENABLE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLA_ENABLE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_ENABLE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CHCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_RUNSTDBY;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CHCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->CHCTRLA.reg;
+	tmp = (tmp & DMAC_CHCTRLA_RUNSTDBY) >> DMAC_CHCTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CHCTRLA.reg;
+	tmp &= ~DMAC_CHCTRLA_RUNSTDBY;
+	tmp |= value << DMAC_CHCTRLA_RUNSTDBY_Pos;
+	((Dmac *)hw)->CHCTRLA.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_RUNSTDBY;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_RUNSTDBY;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLA.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->CHCTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLA.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLA.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLA.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->CHCTRLA.reg;
+}
+
+static inline void hri_dmac_set_CHCTRLB_EVIE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_EVIE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CHCTRLB_EVIE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp = (tmp & DMAC_CHCTRLB_EVIE) >> DMAC_CHCTRLB_EVIE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLB_EVIE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp &= ~DMAC_CHCTRLB_EVIE;
+	tmp |= value << DMAC_CHCTRLB_EVIE_Pos;
+	((Dmac *)hw)->CHCTRLB.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLB_EVIE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_EVIE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLB_EVIE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_EVIE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CHCTRLB_EVOE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_EVOE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CHCTRLB_EVOE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp = (tmp & DMAC_CHCTRLB_EVOE) >> DMAC_CHCTRLB_EVOE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLB_EVOE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp &= ~DMAC_CHCTRLB_EVOE;
+	tmp |= value << DMAC_CHCTRLB_EVOE_Pos;
+	((Dmac *)hw)->CHCTRLB.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLB_EVOE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_EVOE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLB_EVOE_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_EVOE;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_set_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_EVACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp = (tmp & DMAC_CHCTRLB_EVACT(mask)) >> DMAC_CHCTRLB_EVACT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp &= ~DMAC_CHCTRLB_EVACT_Msk;
+	tmp |= DMAC_CHCTRLB_EVACT(data);
+	((Dmac *)hw)->CHCTRLB.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_EVACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_EVACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_EVACT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp = (tmp & DMAC_CHCTRLB_EVACT_Msk) >> DMAC_CHCTRLB_EVACT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_LVL(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp = (tmp & DMAC_CHCTRLB_LVL(mask)) >> DMAC_CHCTRLB_LVL_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp &= ~DMAC_CHCTRLB_LVL_Msk;
+	tmp |= DMAC_CHCTRLB_LVL(data);
+	((Dmac *)hw)->CHCTRLB.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_LVL(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_LVL(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_LVL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp = (tmp & DMAC_CHCTRLB_LVL_Msk) >> DMAC_CHCTRLB_LVL_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_TRIGSRC(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp = (tmp & DMAC_CHCTRLB_TRIGSRC(mask)) >> DMAC_CHCTRLB_TRIGSRC_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp &= ~DMAC_CHCTRLB_TRIGSRC_Msk;
+	tmp |= DMAC_CHCTRLB_TRIGSRC(data);
+	((Dmac *)hw)->CHCTRLB.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_TRIGSRC(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_TRIGSRC(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_TRIGSRC_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp = (tmp & DMAC_CHCTRLB_TRIGSRC_Msk) >> DMAC_CHCTRLB_TRIGSRC_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_TRIGACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp = (tmp & DMAC_CHCTRLB_TRIGACT(mask)) >> DMAC_CHCTRLB_TRIGACT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp &= ~DMAC_CHCTRLB_TRIGACT_Msk;
+	tmp |= DMAC_CHCTRLB_TRIGACT(data);
+	((Dmac *)hw)->CHCTRLB.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_TRIGACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_TRIGACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_TRIGACT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp = (tmp & DMAC_CHCTRLB_TRIGACT_Msk) >> DMAC_CHCTRLB_TRIGACT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_CMD(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp = (tmp & DMAC_CHCTRLB_CMD(mask)) >> DMAC_CHCTRLB_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp &= ~DMAC_CHCTRLB_CMD_Msk;
+	tmp |= DMAC_CHCTRLB_CMD(data);
+	((Dmac *)hw)->CHCTRLB.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_CMD(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_CMD(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_CMD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp = (tmp & DMAC_CHCTRLB_CMD_Msk) >> DMAC_CHCTRLB_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_dmac_set_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dmac *)hw)->CHCTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_write_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_clear_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmac_toggle_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CHCTRLB.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->CHCTRLB.reg;
+}
+
+static inline bool hri_dmac_get_CRCSTATUS_CRCBUSY_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCBUSY) >> DMAC_CRCSTATUS_CRCBUSY_Pos;
+}
+
+static inline void hri_dmac_clear_CRCSTATUS_CRCBUSY_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCBUSY;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmac_get_CRCSTATUS_CRCZERO_bit(const void *const hw)
+{
+	return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCZERO) >> DMAC_CRCSTATUS_CRCZERO_Pos;
+}
+
+static inline void hri_dmac_clear_CRCSTATUS_CRCZERO_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCZERO;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcstatus_reg_t hri_dmac_get_CRCSTATUS_reg(const void *const hw, hri_dmac_crcstatus_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dmac *)hw)->CRCSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmac_clear_CRCSTATUS_reg(const void *const hw, hri_dmac_crcstatus_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((Dmac *)hw)->CRCSTATUS.reg = mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmac_crcstatus_reg_t hri_dmac_read_CRCSTATUS_reg(const void *const hw)
+{
+	return ((Dmac *)hw)->CRCSTATUS.reg;
+}
+
+static inline void hri_dmacdescriptor_set_BTCTRL_VALID_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_VALID;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmacdescriptor_get_BTCTRL_VALID_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_VALID) >> DMAC_BTCTRL_VALID_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCTRL_VALID_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp &= ~DMAC_BTCTRL_VALID;
+	tmp |= value << DMAC_BTCTRL_VALID_Pos;
+	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCTRL_VALID_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_VALID;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCTRL_VALID_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_VALID;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_set_BTCTRL_SRCINC_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_SRCINC;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmacdescriptor_get_BTCTRL_SRCINC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_SRCINC) >> DMAC_BTCTRL_SRCINC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCTRL_SRCINC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp &= ~DMAC_BTCTRL_SRCINC;
+	tmp |= value << DMAC_BTCTRL_SRCINC_Pos;
+	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCTRL_SRCINC_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_SRCINC;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCTRL_SRCINC_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_SRCINC;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_set_BTCTRL_DSTINC_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_DSTINC;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmacdescriptor_get_BTCTRL_DSTINC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_DSTINC) >> DMAC_BTCTRL_DSTINC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCTRL_DSTINC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp &= ~DMAC_BTCTRL_DSTINC;
+	tmp |= value << DMAC_BTCTRL_DSTINC_Pos;
+	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCTRL_DSTINC_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_DSTINC;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCTRL_DSTINC_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_DSTINC;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_set_BTCTRL_STEPSEL_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_STEPSEL;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dmacdescriptor_get_BTCTRL_STEPSEL_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_STEPSEL) >> DMAC_BTCTRL_STEPSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCTRL_STEPSEL_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp &= ~DMAC_BTCTRL_STEPSEL;
+	tmp |= value << DMAC_BTCTRL_STEPSEL_Pos;
+	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCTRL_STEPSEL_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_STEPSEL;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCTRL_STEPSEL_bit(const void *const hw)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_STEPSEL;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_set_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_EVOSEL(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t
+hri_dmacdescriptor_get_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_EVOSEL(mask)) >> DMAC_BTCTRL_EVOSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp &= ~DMAC_BTCTRL_EVOSEL_Msk;
+	tmp |= DMAC_BTCTRL_EVOSEL(data);
+	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_EVOSEL(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCTRL_EVOSEL_bf(const void *const               hw,
+                                                              hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_EVOSEL(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_EVOSEL_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_EVOSEL_Msk) >> DMAC_BTCTRL_EVOSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_set_BTCTRL_BLOCKACT_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_BLOCKACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t
+hri_dmacdescriptor_get_BTCTRL_BLOCKACT_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_BLOCKACT(mask)) >> DMAC_BTCTRL_BLOCKACT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCTRL_BLOCKACT_bf(const void *const               hw,
+                                                               hri_dmacdescriptor_btctrl_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp &= ~DMAC_BTCTRL_BLOCKACT_Msk;
+	tmp |= DMAC_BTCTRL_BLOCKACT(data);
+	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCTRL_BLOCKACT_bf(const void *const               hw,
+                                                               hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_BLOCKACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCTRL_BLOCKACT_bf(const void *const               hw,
+                                                                hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_BLOCKACT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_BLOCKACT_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_BLOCKACT_Msk) >> DMAC_BTCTRL_BLOCKACT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_set_BTCTRL_BEATSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_BEATSIZE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t
+hri_dmacdescriptor_get_BTCTRL_BEATSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_BEATSIZE(mask)) >> DMAC_BTCTRL_BEATSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCTRL_BEATSIZE_bf(const void *const               hw,
+                                                               hri_dmacdescriptor_btctrl_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp &= ~DMAC_BTCTRL_BEATSIZE_Msk;
+	tmp |= DMAC_BTCTRL_BEATSIZE(data);
+	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCTRL_BEATSIZE_bf(const void *const               hw,
+                                                               hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_BEATSIZE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCTRL_BEATSIZE_bf(const void *const               hw,
+                                                                hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_BEATSIZE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_BEATSIZE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_BEATSIZE_Msk) >> DMAC_BTCTRL_BEATSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_set_BTCTRL_STEPSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_STEPSIZE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t
+hri_dmacdescriptor_get_BTCTRL_STEPSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_STEPSIZE(mask)) >> DMAC_BTCTRL_STEPSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCTRL_STEPSIZE_bf(const void *const               hw,
+                                                               hri_dmacdescriptor_btctrl_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp &= ~DMAC_BTCTRL_STEPSIZE_Msk;
+	tmp |= DMAC_BTCTRL_STEPSIZE(data);
+	((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCTRL_STEPSIZE_bf(const void *const               hw,
+                                                               hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_STEPSIZE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCTRL_STEPSIZE_bf(const void *const               hw,
+                                                                hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_STEPSIZE(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_STEPSIZE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp = (tmp & DMAC_BTCTRL_STEPSIZE_Msk) >> DMAC_BTCTRL_STEPSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_set_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_get_BTCTRL_reg(const void *const               hw,
+                                                                                hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCTRL.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_reg(const void *const hw)
+{
+	return ((DmacDescriptor *)hw)->BTCTRL.reg;
+}
+
+static inline void hri_dmacdescriptor_set_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCNT.reg |= DMAC_BTCNT_BTCNT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_get_BTCNT_BTCNT_bf(const void *const              hw,
+                                                                                   hri_dmacdescriptor_btcnt_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCNT.reg;
+	tmp = (tmp & DMAC_BTCNT_BTCNT(mask)) >> DMAC_BTCNT_BTCNT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t data)
+{
+	uint16_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->BTCNT.reg;
+	tmp &= ~DMAC_BTCNT_BTCNT_Msk;
+	tmp |= DMAC_BTCNT_BTCNT(data);
+	((DmacDescriptor *)hw)->BTCNT.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCNT.reg &= ~DMAC_BTCNT_BTCNT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCNT.reg ^= DMAC_BTCNT_BTCNT(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_read_BTCNT_BTCNT_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCNT.reg;
+	tmp = (tmp & DMAC_BTCNT_BTCNT_Msk) >> DMAC_BTCNT_BTCNT_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_set_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCNT.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_get_BTCNT_reg(const void *const              hw,
+                                                                              hri_dmacdescriptor_btcnt_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((DmacDescriptor *)hw)->BTCNT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCNT.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCNT.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->BTCNT.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_read_BTCNT_reg(const void *const hw)
+{
+	return ((DmacDescriptor *)hw)->BTCNT.reg;
+}
+
+static inline void hri_dmacdescriptor_set_SRCADDR_SRCADDR_bf(const void *const                hw,
+                                                             hri_dmacdescriptor_srcaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->SRCADDR.reg |= DMAC_SRCADDR_SRCADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_srcaddr_reg_t
+hri_dmacdescriptor_get_SRCADDR_SRCADDR_bf(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->SRCADDR.reg;
+	tmp = (tmp & DMAC_SRCADDR_SRCADDR(mask)) >> DMAC_SRCADDR_SRCADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_SRCADDR_SRCADDR_bf(const void *const                hw,
+                                                               hri_dmacdescriptor_srcaddr_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->SRCADDR.reg;
+	tmp &= ~DMAC_SRCADDR_SRCADDR_Msk;
+	tmp |= DMAC_SRCADDR_SRCADDR(data);
+	((DmacDescriptor *)hw)->SRCADDR.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_SRCADDR_SRCADDR_bf(const void *const                hw,
+                                                               hri_dmacdescriptor_srcaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->SRCADDR.reg &= ~DMAC_SRCADDR_SRCADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_SRCADDR_SRCADDR_bf(const void *const                hw,
+                                                                hri_dmacdescriptor_srcaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->SRCADDR.reg ^= DMAC_SRCADDR_SRCADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_read_SRCADDR_SRCADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->SRCADDR.reg;
+	tmp = (tmp & DMAC_SRCADDR_SRCADDR_Msk) >> DMAC_SRCADDR_SRCADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_set_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->SRCADDR.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_get_SRCADDR_reg(const void *const                hw,
+                                                                                  hri_dmacdescriptor_srcaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->SRCADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->SRCADDR.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->SRCADDR.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->SRCADDR.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_read_SRCADDR_reg(const void *const hw)
+{
+	return ((DmacDescriptor *)hw)->SRCADDR.reg;
+}
+
+static inline void hri_dmacdescriptor_set_DSTADDR_DSTADDR_bf(const void *const                hw,
+                                                             hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DSTADDR.reg |= DMAC_DSTADDR_DSTADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_dstaddr_reg_t
+hri_dmacdescriptor_get_DSTADDR_DSTADDR_bf(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->DSTADDR.reg;
+	tmp = (tmp & DMAC_DSTADDR_DSTADDR(mask)) >> DMAC_DSTADDR_DSTADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_DSTADDR_DSTADDR_bf(const void *const                hw,
+                                                               hri_dmacdescriptor_dstaddr_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->DSTADDR.reg;
+	tmp &= ~DMAC_DSTADDR_DSTADDR_Msk;
+	tmp |= DMAC_DSTADDR_DSTADDR(data);
+	((DmacDescriptor *)hw)->DSTADDR.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_DSTADDR_DSTADDR_bf(const void *const                hw,
+                                                               hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DSTADDR.reg &= ~DMAC_DSTADDR_DSTADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_DSTADDR_DSTADDR_bf(const void *const                hw,
+                                                                hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DSTADDR.reg ^= DMAC_DSTADDR_DSTADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_DSTADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->DSTADDR.reg;
+	tmp = (tmp & DMAC_DSTADDR_DSTADDR_Msk) >> DMAC_DSTADDR_DSTADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_set_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DSTADDR.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_get_DSTADDR_reg(const void *const                hw,
+                                                                                  hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->DSTADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DSTADDR.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DSTADDR.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DSTADDR.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_reg(const void *const hw)
+{
+	return ((DmacDescriptor *)hw)->DSTADDR.reg;
+}
+
+static inline void hri_dmacdescriptor_set_DESCADDR_DESCADDR_bf(const void *const                 hw,
+                                                               hri_dmacdescriptor_descaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DESCADDR.reg |= DMAC_DESCADDR_DESCADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_descaddr_reg_t
+hri_dmacdescriptor_get_DESCADDR_DESCADDR_bf(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->DESCADDR.reg;
+	tmp = (tmp & DMAC_DESCADDR_DESCADDR(mask)) >> DMAC_DESCADDR_DESCADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_DESCADDR_DESCADDR_bf(const void *const                 hw,
+                                                                 hri_dmacdescriptor_descaddr_reg_t data)
+{
+	uint32_t tmp;
+	DMAC_CRITICAL_SECTION_ENTER();
+	tmp = ((DmacDescriptor *)hw)->DESCADDR.reg;
+	tmp &= ~DMAC_DESCADDR_DESCADDR_Msk;
+	tmp |= DMAC_DESCADDR_DESCADDR(data);
+	((DmacDescriptor *)hw)->DESCADDR.reg = tmp;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_DESCADDR_DESCADDR_bf(const void *const                 hw,
+                                                                 hri_dmacdescriptor_descaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DESCADDR.reg &= ~DMAC_DESCADDR_DESCADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_DESCADDR_DESCADDR_bf(const void *const                 hw,
+                                                                  hri_dmacdescriptor_descaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DESCADDR.reg ^= DMAC_DESCADDR_DESCADDR(mask);
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_descaddr_reg_t hri_dmacdescriptor_read_DESCADDR_DESCADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->DESCADDR.reg;
+	tmp = (tmp & DMAC_DESCADDR_DESCADDR_Msk) >> DMAC_DESCADDR_DESCADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_set_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DESCADDR.reg |= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_descaddr_reg_t
+hri_dmacdescriptor_get_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((DmacDescriptor *)hw)->DESCADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dmacdescriptor_write_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t data)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DESCADDR.reg = data;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_clear_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DESCADDR.reg &= ~mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dmacdescriptor_toggle_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask)
+{
+	DMAC_CRITICAL_SECTION_ENTER();
+	((DmacDescriptor *)hw)->DESCADDR.reg ^= mask;
+	DMAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dmacdescriptor_descaddr_reg_t hri_dmacdescriptor_read_DESCADDR_reg(const void *const hw)
+{
+	return ((DmacDescriptor *)hw)->DESCADDR.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_DMAC_L22_H_INCLUDED */
+#endif /* _SAML22_DMAC_COMPONENT_ */
diff --git a/watch-library/hardware/hri/hri_dsu_l22.h b/watch-library/hardware/hri/hri_dsu_l22.h
new file mode 100644
index 00000000..2e8bbe8b
--- /dev/null
+++ b/watch-library/hardware/hri/hri_dsu_l22.h
@@ -0,0 +1,1163 @@
+/**
+ * \file
+ *
+ * \brief SAM DSU
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_DSU_COMPONENT_
+#ifndef _HRI_DSU_L22_H_INCLUDED_
+#define _HRI_DSU_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_DSU_CRITICAL_SECTIONS)
+#define DSU_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define DSU_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define DSU_CRITICAL_SECTION_ENTER()
+#define DSU_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_dsu_addr_reg_t;
+typedef uint32_t hri_dsu_cid0_reg_t;
+typedef uint32_t hri_dsu_cid1_reg_t;
+typedef uint32_t hri_dsu_cid2_reg_t;
+typedef uint32_t hri_dsu_cid3_reg_t;
+typedef uint32_t hri_dsu_data_reg_t;
+typedef uint32_t hri_dsu_dcc_reg_t;
+typedef uint32_t hri_dsu_dcfg_reg_t;
+typedef uint32_t hri_dsu_did_reg_t;
+typedef uint32_t hri_dsu_end_reg_t;
+typedef uint32_t hri_dsu_entry0_reg_t;
+typedef uint32_t hri_dsu_entry1_reg_t;
+typedef uint32_t hri_dsu_length_reg_t;
+typedef uint32_t hri_dsu_memtype_reg_t;
+typedef uint32_t hri_dsu_pid0_reg_t;
+typedef uint32_t hri_dsu_pid1_reg_t;
+typedef uint32_t hri_dsu_pid2_reg_t;
+typedef uint32_t hri_dsu_pid3_reg_t;
+typedef uint32_t hri_dsu_pid4_reg_t;
+typedef uint32_t hri_dsu_pid5_reg_t;
+typedef uint32_t hri_dsu_pid6_reg_t;
+typedef uint32_t hri_dsu_pid7_reg_t;
+typedef uint8_t  hri_dsu_ctrl_reg_t;
+typedef uint8_t  hri_dsu_statusa_reg_t;
+typedef uint8_t  hri_dsu_statusb_reg_t;
+
+static inline bool hri_dsu_get_STATUSB_PROT_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_PROT) >> DSU_STATUSB_PROT_Pos;
+}
+
+static inline bool hri_dsu_get_STATUSB_DBGPRES_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DBGPRES) >> DSU_STATUSB_DBGPRES_Pos;
+}
+
+static inline bool hri_dsu_get_STATUSB_DCCD0_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DCCD0) >> DSU_STATUSB_DCCD0_Pos;
+}
+
+static inline bool hri_dsu_get_STATUSB_DCCD1_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DCCD1) >> DSU_STATUSB_DCCD1_Pos;
+}
+
+static inline bool hri_dsu_get_STATUSB_HPE_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_HPE) >> DSU_STATUSB_HPE_Pos;
+}
+
+static inline hri_dsu_statusb_reg_t hri_dsu_get_STATUSB_reg(const void *const hw, hri_dsu_statusb_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dsu *)hw)->STATUSB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_statusb_reg_t hri_dsu_read_STATUSB_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->STATUSB.reg;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_get_DID_DEVSEL_bf(const void *const hw, hri_dsu_did_reg_t mask)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_DEVSEL(mask)) >> DSU_DID_DEVSEL_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_read_DID_DEVSEL_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_DEVSEL_Msk) >> DSU_DID_DEVSEL_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_get_DID_REVISION_bf(const void *const hw, hri_dsu_did_reg_t mask)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_REVISION(mask)) >> DSU_DID_REVISION_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_read_DID_REVISION_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_REVISION_Msk) >> DSU_DID_REVISION_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_get_DID_DIE_bf(const void *const hw, hri_dsu_did_reg_t mask)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_DIE(mask)) >> DSU_DID_DIE_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_read_DID_DIE_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_DIE_Msk) >> DSU_DID_DIE_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_get_DID_SERIES_bf(const void *const hw, hri_dsu_did_reg_t mask)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_SERIES(mask)) >> DSU_DID_SERIES_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_read_DID_SERIES_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_SERIES_Msk) >> DSU_DID_SERIES_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_get_DID_FAMILY_bf(const void *const hw, hri_dsu_did_reg_t mask)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_FAMILY(mask)) >> DSU_DID_FAMILY_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_read_DID_FAMILY_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_FAMILY_Msk) >> DSU_DID_FAMILY_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_get_DID_PROCESSOR_bf(const void *const hw, hri_dsu_did_reg_t mask)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_PROCESSOR(mask)) >> DSU_DID_PROCESSOR_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_read_DID_PROCESSOR_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->DID.reg & DSU_DID_PROCESSOR_Msk) >> DSU_DID_PROCESSOR_Pos;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_get_DID_reg(const void *const hw, hri_dsu_did_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->DID.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_did_reg_t hri_dsu_read_DID_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->DID.reg;
+}
+
+static inline bool hri_dsu_get_ENTRY0_EPRES_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_EPRES) >> DSU_ENTRY0_EPRES_Pos;
+}
+
+static inline bool hri_dsu_get_ENTRY0_FMT_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_FMT) >> DSU_ENTRY0_FMT_Pos;
+}
+
+static inline hri_dsu_entry0_reg_t hri_dsu_get_ENTRY0_ADDOFF_bf(const void *const hw, hri_dsu_entry0_reg_t mask)
+{
+	return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_ADDOFF(mask)) >> DSU_ENTRY0_ADDOFF_Pos;
+}
+
+static inline hri_dsu_entry0_reg_t hri_dsu_read_ENTRY0_ADDOFF_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_ADDOFF_Msk) >> DSU_ENTRY0_ADDOFF_Pos;
+}
+
+static inline hri_dsu_entry0_reg_t hri_dsu_get_ENTRY0_reg(const void *const hw, hri_dsu_entry0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->ENTRY0.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_entry0_reg_t hri_dsu_read_ENTRY0_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->ENTRY0.reg;
+}
+
+static inline hri_dsu_entry1_reg_t hri_dsu_get_ENTRY1_reg(const void *const hw, hri_dsu_entry1_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->ENTRY1.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_entry1_reg_t hri_dsu_read_ENTRY1_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->ENTRY1.reg;
+}
+
+static inline hri_dsu_end_reg_t hri_dsu_get_END_END_bf(const void *const hw, hri_dsu_end_reg_t mask)
+{
+	return (((Dsu *)hw)->END.reg & DSU_END_END(mask)) >> DSU_END_END_Pos;
+}
+
+static inline hri_dsu_end_reg_t hri_dsu_read_END_END_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->END.reg & DSU_END_END_Msk) >> DSU_END_END_Pos;
+}
+
+static inline hri_dsu_end_reg_t hri_dsu_get_END_reg(const void *const hw, hri_dsu_end_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->END.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_end_reg_t hri_dsu_read_END_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->END.reg;
+}
+
+static inline bool hri_dsu_get_MEMTYPE_SMEMP_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->MEMTYPE.reg & DSU_MEMTYPE_SMEMP) >> DSU_MEMTYPE_SMEMP_Pos;
+}
+
+static inline hri_dsu_memtype_reg_t hri_dsu_get_MEMTYPE_reg(const void *const hw, hri_dsu_memtype_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->MEMTYPE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_memtype_reg_t hri_dsu_read_MEMTYPE_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->MEMTYPE.reg;
+}
+
+static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_JEPCC_bf(const void *const hw, hri_dsu_pid4_reg_t mask)
+{
+	return (((Dsu *)hw)->PID4.reg & DSU_PID4_JEPCC(mask)) >> DSU_PID4_JEPCC_Pos;
+}
+
+static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_JEPCC_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->PID4.reg & DSU_PID4_JEPCC_Msk) >> DSU_PID4_JEPCC_Pos;
+}
+
+static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_FKBC_bf(const void *const hw, hri_dsu_pid4_reg_t mask)
+{
+	return (((Dsu *)hw)->PID4.reg & DSU_PID4_FKBC(mask)) >> DSU_PID4_FKBC_Pos;
+}
+
+static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_FKBC_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->PID4.reg & DSU_PID4_FKBC_Msk) >> DSU_PID4_FKBC_Pos;
+}
+
+static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_reg(const void *const hw, hri_dsu_pid4_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->PID4.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->PID4.reg;
+}
+
+static inline hri_dsu_pid5_reg_t hri_dsu_get_PID5_reg(const void *const hw, hri_dsu_pid5_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->PID5.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_pid5_reg_t hri_dsu_read_PID5_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->PID5.reg;
+}
+
+static inline hri_dsu_pid6_reg_t hri_dsu_get_PID6_reg(const void *const hw, hri_dsu_pid6_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->PID6.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_pid6_reg_t hri_dsu_read_PID6_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->PID6.reg;
+}
+
+static inline hri_dsu_pid7_reg_t hri_dsu_get_PID7_reg(const void *const hw, hri_dsu_pid7_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->PID7.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_pid7_reg_t hri_dsu_read_PID7_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->PID7.reg;
+}
+
+static inline hri_dsu_pid0_reg_t hri_dsu_get_PID0_PARTNBL_bf(const void *const hw, hri_dsu_pid0_reg_t mask)
+{
+	return (((Dsu *)hw)->PID0.reg & DSU_PID0_PARTNBL(mask)) >> DSU_PID0_PARTNBL_Pos;
+}
+
+static inline hri_dsu_pid0_reg_t hri_dsu_read_PID0_PARTNBL_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->PID0.reg & DSU_PID0_PARTNBL_Msk) >> DSU_PID0_PARTNBL_Pos;
+}
+
+static inline hri_dsu_pid0_reg_t hri_dsu_get_PID0_reg(const void *const hw, hri_dsu_pid0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->PID0.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_pid0_reg_t hri_dsu_read_PID0_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->PID0.reg;
+}
+
+static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_PARTNBH_bf(const void *const hw, hri_dsu_pid1_reg_t mask)
+{
+	return (((Dsu *)hw)->PID1.reg & DSU_PID1_PARTNBH(mask)) >> DSU_PID1_PARTNBH_Pos;
+}
+
+static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_PARTNBH_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->PID1.reg & DSU_PID1_PARTNBH_Msk) >> DSU_PID1_PARTNBH_Pos;
+}
+
+static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_JEPIDCL_bf(const void *const hw, hri_dsu_pid1_reg_t mask)
+{
+	return (((Dsu *)hw)->PID1.reg & DSU_PID1_JEPIDCL(mask)) >> DSU_PID1_JEPIDCL_Pos;
+}
+
+static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_JEPIDCL_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->PID1.reg & DSU_PID1_JEPIDCL_Msk) >> DSU_PID1_JEPIDCL_Pos;
+}
+
+static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_reg(const void *const hw, hri_dsu_pid1_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->PID1.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->PID1.reg;
+}
+
+static inline bool hri_dsu_get_PID2_JEPU_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPU) >> DSU_PID2_JEPU_Pos;
+}
+
+static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_JEPIDCH_bf(const void *const hw, hri_dsu_pid2_reg_t mask)
+{
+	return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPIDCH(mask)) >> DSU_PID2_JEPIDCH_Pos;
+}
+
+static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_JEPIDCH_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPIDCH_Msk) >> DSU_PID2_JEPIDCH_Pos;
+}
+
+static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_REVISION_bf(const void *const hw, hri_dsu_pid2_reg_t mask)
+{
+	return (((Dsu *)hw)->PID2.reg & DSU_PID2_REVISION(mask)) >> DSU_PID2_REVISION_Pos;
+}
+
+static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_REVISION_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->PID2.reg & DSU_PID2_REVISION_Msk) >> DSU_PID2_REVISION_Pos;
+}
+
+static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_reg(const void *const hw, hri_dsu_pid2_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->PID2.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->PID2.reg;
+}
+
+static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_CUSMOD_bf(const void *const hw, hri_dsu_pid3_reg_t mask)
+{
+	return (((Dsu *)hw)->PID3.reg & DSU_PID3_CUSMOD(mask)) >> DSU_PID3_CUSMOD_Pos;
+}
+
+static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_CUSMOD_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->PID3.reg & DSU_PID3_CUSMOD_Msk) >> DSU_PID3_CUSMOD_Pos;
+}
+
+static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_REVAND_bf(const void *const hw, hri_dsu_pid3_reg_t mask)
+{
+	return (((Dsu *)hw)->PID3.reg & DSU_PID3_REVAND(mask)) >> DSU_PID3_REVAND_Pos;
+}
+
+static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_REVAND_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->PID3.reg & DSU_PID3_REVAND_Msk) >> DSU_PID3_REVAND_Pos;
+}
+
+static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_reg(const void *const hw, hri_dsu_pid3_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->PID3.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->PID3.reg;
+}
+
+static inline hri_dsu_cid0_reg_t hri_dsu_get_CID0_PREAMBLEB0_bf(const void *const hw, hri_dsu_cid0_reg_t mask)
+{
+	return (((Dsu *)hw)->CID0.reg & DSU_CID0_PREAMBLEB0(mask)) >> DSU_CID0_PREAMBLEB0_Pos;
+}
+
+static inline hri_dsu_cid0_reg_t hri_dsu_read_CID0_PREAMBLEB0_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->CID0.reg & DSU_CID0_PREAMBLEB0_Msk) >> DSU_CID0_PREAMBLEB0_Pos;
+}
+
+static inline hri_dsu_cid0_reg_t hri_dsu_get_CID0_reg(const void *const hw, hri_dsu_cid0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->CID0.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_cid0_reg_t hri_dsu_read_CID0_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->CID0.reg;
+}
+
+static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_PREAMBLE_bf(const void *const hw, hri_dsu_cid1_reg_t mask)
+{
+	return (((Dsu *)hw)->CID1.reg & DSU_CID1_PREAMBLE(mask)) >> DSU_CID1_PREAMBLE_Pos;
+}
+
+static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_PREAMBLE_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->CID1.reg & DSU_CID1_PREAMBLE_Msk) >> DSU_CID1_PREAMBLE_Pos;
+}
+
+static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_CCLASS_bf(const void *const hw, hri_dsu_cid1_reg_t mask)
+{
+	return (((Dsu *)hw)->CID1.reg & DSU_CID1_CCLASS(mask)) >> DSU_CID1_CCLASS_Pos;
+}
+
+static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_CCLASS_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->CID1.reg & DSU_CID1_CCLASS_Msk) >> DSU_CID1_CCLASS_Pos;
+}
+
+static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_reg(const void *const hw, hri_dsu_cid1_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->CID1.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->CID1.reg;
+}
+
+static inline hri_dsu_cid2_reg_t hri_dsu_get_CID2_PREAMBLEB2_bf(const void *const hw, hri_dsu_cid2_reg_t mask)
+{
+	return (((Dsu *)hw)->CID2.reg & DSU_CID2_PREAMBLEB2(mask)) >> DSU_CID2_PREAMBLEB2_Pos;
+}
+
+static inline hri_dsu_cid2_reg_t hri_dsu_read_CID2_PREAMBLEB2_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->CID2.reg & DSU_CID2_PREAMBLEB2_Msk) >> DSU_CID2_PREAMBLEB2_Pos;
+}
+
+static inline hri_dsu_cid2_reg_t hri_dsu_get_CID2_reg(const void *const hw, hri_dsu_cid2_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->CID2.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_cid2_reg_t hri_dsu_read_CID2_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->CID2.reg;
+}
+
+static inline hri_dsu_cid3_reg_t hri_dsu_get_CID3_PREAMBLEB3_bf(const void *const hw, hri_dsu_cid3_reg_t mask)
+{
+	return (((Dsu *)hw)->CID3.reg & DSU_CID3_PREAMBLEB3(mask)) >> DSU_CID3_PREAMBLEB3_Pos;
+}
+
+static inline hri_dsu_cid3_reg_t hri_dsu_read_CID3_PREAMBLEB3_bf(const void *const hw)
+{
+	return (((Dsu *)hw)->CID3.reg & DSU_CID3_PREAMBLEB3_Msk) >> DSU_CID3_PREAMBLEB3_Pos;
+}
+
+static inline hri_dsu_cid3_reg_t hri_dsu_get_CID3_reg(const void *const hw, hri_dsu_cid3_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->CID3.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_dsu_cid3_reg_t hri_dsu_read_CID3_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->CID3.reg;
+}
+
+static inline void hri_dsu_set_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg |= DSU_ADDR_AMOD(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->ADDR.reg;
+	tmp = (tmp & DSU_ADDR_AMOD(mask)) >> DSU_ADDR_AMOD_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_write_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t data)
+{
+	uint32_t tmp;
+	DSU_CRITICAL_SECTION_ENTER();
+	tmp = ((Dsu *)hw)->ADDR.reg;
+	tmp &= ~DSU_ADDR_AMOD_Msk;
+	tmp |= DSU_ADDR_AMOD(data);
+	((Dsu *)hw)->ADDR.reg = tmp;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg &= ~DSU_ADDR_AMOD(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg ^= DSU_ADDR_AMOD(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_AMOD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->ADDR.reg;
+	tmp = (tmp & DSU_ADDR_AMOD_Msk) >> DSU_ADDR_AMOD_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_set_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg |= DSU_ADDR_ADDR(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->ADDR.reg;
+	tmp = (tmp & DSU_ADDR_ADDR(mask)) >> DSU_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_write_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t data)
+{
+	uint32_t tmp;
+	DSU_CRITICAL_SECTION_ENTER();
+	tmp = ((Dsu *)hw)->ADDR.reg;
+	tmp &= ~DSU_ADDR_ADDR_Msk;
+	tmp |= DSU_ADDR_ADDR(data);
+	((Dsu *)hw)->ADDR.reg = tmp;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg &= ~DSU_ADDR_ADDR(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg ^= DSU_ADDR_ADDR(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_ADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->ADDR.reg;
+	tmp = (tmp & DSU_ADDR_ADDR_Msk) >> DSU_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_set_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg |= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->ADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dsu_write_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t data)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg = data;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg &= ~mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->ADDR.reg ^= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->ADDR.reg;
+}
+
+static inline void hri_dsu_set_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->LENGTH.reg |= DSU_LENGTH_LENGTH(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_length_reg_t hri_dsu_get_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->LENGTH.reg;
+	tmp = (tmp & DSU_LENGTH_LENGTH(mask)) >> DSU_LENGTH_LENGTH_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_write_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t data)
+{
+	uint32_t tmp;
+	DSU_CRITICAL_SECTION_ENTER();
+	tmp = ((Dsu *)hw)->LENGTH.reg;
+	tmp &= ~DSU_LENGTH_LENGTH_Msk;
+	tmp |= DSU_LENGTH_LENGTH(data);
+	((Dsu *)hw)->LENGTH.reg = tmp;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->LENGTH.reg &= ~DSU_LENGTH_LENGTH(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->LENGTH.reg ^= DSU_LENGTH_LENGTH(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_length_reg_t hri_dsu_read_LENGTH_LENGTH_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->LENGTH.reg;
+	tmp = (tmp & DSU_LENGTH_LENGTH_Msk) >> DSU_LENGTH_LENGTH_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_set_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->LENGTH.reg |= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_length_reg_t hri_dsu_get_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->LENGTH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dsu_write_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t data)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->LENGTH.reg = data;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->LENGTH.reg &= ~mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->LENGTH.reg ^= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_length_reg_t hri_dsu_read_LENGTH_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->LENGTH.reg;
+}
+
+static inline void hri_dsu_set_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DATA.reg |= DSU_DATA_DATA(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_data_reg_t hri_dsu_get_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->DATA.reg;
+	tmp = (tmp & DSU_DATA_DATA(mask)) >> DSU_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_write_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t data)
+{
+	uint32_t tmp;
+	DSU_CRITICAL_SECTION_ENTER();
+	tmp = ((Dsu *)hw)->DATA.reg;
+	tmp &= ~DSU_DATA_DATA_Msk;
+	tmp |= DSU_DATA_DATA(data);
+	((Dsu *)hw)->DATA.reg = tmp;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DATA.reg &= ~DSU_DATA_DATA(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DATA.reg ^= DSU_DATA_DATA(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_data_reg_t hri_dsu_read_DATA_DATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->DATA.reg;
+	tmp = (tmp & DSU_DATA_DATA_Msk) >> DSU_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_set_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DATA.reg |= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_data_reg_t hri_dsu_get_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->DATA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dsu_write_DATA_reg(const void *const hw, hri_dsu_data_reg_t data)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DATA.reg = data;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DATA.reg &= ~mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DATA.reg ^= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_data_reg_t hri_dsu_read_DATA_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->DATA.reg;
+}
+
+static inline void hri_dsu_set_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCC[index].reg |= DSU_DCC_DATA(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_dcc_reg_t hri_dsu_get_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->DCC[index].reg;
+	tmp = (tmp & DSU_DCC_DATA(mask)) >> DSU_DCC_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_write_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t data)
+{
+	uint32_t tmp;
+	DSU_CRITICAL_SECTION_ENTER();
+	tmp = ((Dsu *)hw)->DCC[index].reg;
+	tmp &= ~DSU_DCC_DATA_Msk;
+	tmp |= DSU_DCC_DATA(data);
+	((Dsu *)hw)->DCC[index].reg = tmp;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCC[index].reg &= ~DSU_DCC_DATA(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCC[index].reg ^= DSU_DCC_DATA(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_dcc_reg_t hri_dsu_read_DCC_DATA_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->DCC[index].reg;
+	tmp = (tmp & DSU_DCC_DATA_Msk) >> DSU_DCC_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_set_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCC[index].reg |= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_dcc_reg_t hri_dsu_get_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->DCC[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dsu_write_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t data)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCC[index].reg = data;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCC[index].reg &= ~mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCC[index].reg ^= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_dcc_reg_t hri_dsu_read_DCC_reg(const void *const hw, uint8_t index)
+{
+	return ((Dsu *)hw)->DCC[index].reg;
+}
+
+static inline void hri_dsu_set_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCFG[index].reg |= DSU_DCFG_DCFG(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_dcfg_reg_t hri_dsu_get_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->DCFG[index].reg;
+	tmp = (tmp & DSU_DCFG_DCFG(mask)) >> DSU_DCFG_DCFG_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_write_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t data)
+{
+	uint32_t tmp;
+	DSU_CRITICAL_SECTION_ENTER();
+	tmp = ((Dsu *)hw)->DCFG[index].reg;
+	tmp &= ~DSU_DCFG_DCFG_Msk;
+	tmp |= DSU_DCFG_DCFG(data);
+	((Dsu *)hw)->DCFG[index].reg = tmp;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCFG[index].reg &= ~DSU_DCFG_DCFG(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCFG[index].reg ^= DSU_DCFG_DCFG(mask);
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_dcfg_reg_t hri_dsu_read_DCFG_DCFG_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->DCFG[index].reg;
+	tmp = (tmp & DSU_DCFG_DCFG_Msk) >> DSU_DCFG_DCFG_Pos;
+	return tmp;
+}
+
+static inline void hri_dsu_set_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCFG[index].reg |= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_dcfg_reg_t hri_dsu_get_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Dsu *)hw)->DCFG[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dsu_write_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t data)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCFG[index].reg = data;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_clear_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCFG[index].reg &= ~mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_dsu_toggle_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->DCFG[index].reg ^= mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_dcfg_reg_t hri_dsu_read_DCFG_reg(const void *const hw, uint8_t index)
+{
+	return ((Dsu *)hw)->DCFG[index].reg;
+}
+
+static inline bool hri_dsu_get_STATUSA_DONE_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_DONE) >> DSU_STATUSA_DONE_Pos;
+}
+
+static inline void hri_dsu_clear_STATUSA_DONE_bit(const void *const hw)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_DONE;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dsu_get_STATUSA_CRSTEXT_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_CRSTEXT) >> DSU_STATUSA_CRSTEXT_Pos;
+}
+
+static inline void hri_dsu_clear_STATUSA_CRSTEXT_bit(const void *const hw)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_CRSTEXT;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dsu_get_STATUSA_BERR_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_BERR) >> DSU_STATUSA_BERR_Pos;
+}
+
+static inline void hri_dsu_clear_STATUSA_BERR_bit(const void *const hw)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_BERR;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dsu_get_STATUSA_FAIL_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_FAIL) >> DSU_STATUSA_FAIL_Pos;
+}
+
+static inline void hri_dsu_clear_STATUSA_FAIL_bit(const void *const hw)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_FAIL;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_dsu_get_STATUSA_PERR_bit(const void *const hw)
+{
+	return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_PERR) >> DSU_STATUSA_PERR_Pos;
+}
+
+static inline void hri_dsu_clear_STATUSA_PERR_bit(const void *const hw)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_PERR;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_statusa_reg_t hri_dsu_get_STATUSA_reg(const void *const hw, hri_dsu_statusa_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Dsu *)hw)->STATUSA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_dsu_clear_STATUSA_reg(const void *const hw, hri_dsu_statusa_reg_t mask)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->STATUSA.reg = mask;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_dsu_statusa_reg_t hri_dsu_read_STATUSA_reg(const void *const hw)
+{
+	return ((Dsu *)hw)->STATUSA.reg;
+}
+
+static inline void hri_dsu_write_CTRL_reg(const void *const hw, hri_dsu_ctrl_reg_t data)
+{
+	DSU_CRITICAL_SECTION_ENTER();
+	((Dsu *)hw)->CTRL.reg = data;
+	DSU_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_DSU_L22_H_INCLUDED */
+#endif /* _SAML22_DSU_COMPONENT_ */
diff --git a/watch-library/hardware/hri/hri_eic_l22.h b/watch-library/hardware/hri/hri_eic_l22.h
new file mode 100644
index 00000000..058012bf
--- /dev/null
+++ b/watch-library/hardware/hri/hri_eic_l22.h
@@ -0,0 +1,1463 @@
+/**
+ * \file
+ *
+ * \brief SAM EIC
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_EIC_COMPONENT_
+#ifndef _HRI_EIC_L22_H_INCLUDED_
+#define _HRI_EIC_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_EIC_CRITICAL_SECTIONS)
+#define EIC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define EIC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define EIC_CRITICAL_SECTION_ENTER()
+#define EIC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_eic_nmiflag_reg_t;
+typedef uint32_t hri_eic_asynch_reg_t;
+typedef uint32_t hri_eic_config_reg_t;
+typedef uint32_t hri_eic_evctrl_reg_t;
+typedef uint32_t hri_eic_intenset_reg_t;
+typedef uint32_t hri_eic_intflag_reg_t;
+typedef uint32_t hri_eic_syncbusy_reg_t;
+typedef uint8_t  hri_eic_ctrla_reg_t;
+typedef uint8_t  hri_eic_nmictrl_reg_t;
+
+static inline void hri_eic_wait_for_sync(const void *const hw, hri_eic_syncbusy_reg_t reg)
+{
+	while (((Eic *)hw)->SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_eic_is_syncing(const void *const hw, hri_eic_syncbusy_reg_t reg)
+{
+	return ((Eic *)hw)->SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_eic_get_NMIFLAG_NMI_bit(const void *const hw)
+{
+	return (((Eic *)hw)->NMIFLAG.reg & EIC_NMIFLAG_NMI) >> EIC_NMIFLAG_NMI_Pos;
+}
+
+static inline void hri_eic_clear_NMIFLAG_NMI_bit(const void *const hw)
+{
+	((Eic *)hw)->NMIFLAG.reg = EIC_NMIFLAG_NMI;
+}
+
+static inline hri_eic_nmiflag_reg_t hri_eic_get_NMIFLAG_reg(const void *const hw, hri_eic_nmiflag_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Eic *)hw)->NMIFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_eic_nmiflag_reg_t hri_eic_read_NMIFLAG_reg(const void *const hw)
+{
+	return ((Eic *)hw)->NMIFLAG.reg;
+}
+
+static inline void hri_eic_clear_NMIFLAG_reg(const void *const hw, hri_eic_nmiflag_reg_t mask)
+{
+	((Eic *)hw)->NMIFLAG.reg = mask;
+}
+
+static inline hri_eic_intflag_reg_t hri_eic_get_INTFLAG_reg(const void *const hw, hri_eic_intflag_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_eic_intflag_reg_t hri_eic_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Eic *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_eic_clear_INTFLAG_reg(const void *const hw, hri_eic_intflag_reg_t mask)
+{
+	((Eic *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_eic_set_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask)
+{
+	((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT(mask);
+}
+
+static inline hri_eic_intenset_reg_t hri_eic_get_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->INTENSET.reg;
+	tmp = (tmp & EIC_INTENSET_EXTINT(mask)) >> EIC_INTENSET_EXTINT_Pos;
+	return tmp;
+}
+
+static inline hri_eic_intenset_reg_t hri_eic_read_INTEN_EXTINT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->INTENSET.reg;
+	tmp = (tmp & EIC_INTENSET_EXTINT_Msk) >> EIC_INTENSET_EXTINT_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t data)
+{
+	((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT(data);
+	((Eic *)hw)->INTENCLR.reg = ~EIC_INTENSET_EXTINT(data);
+}
+
+static inline void hri_eic_clear_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask)
+{
+	((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT(mask);
+}
+
+static inline void hri_eic_set_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask)
+{
+	((Eic *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_eic_intenset_reg_t hri_eic_get_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_eic_intenset_reg_t hri_eic_read_INTEN_reg(const void *const hw)
+{
+	return ((Eic *)hw)->INTENSET.reg;
+}
+
+static inline void hri_eic_write_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t data)
+{
+	((Eic *)hw)->INTENSET.reg = data;
+	((Eic *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_eic_clear_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask)
+{
+	((Eic *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_eic_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Eic *)hw)->SYNCBUSY.reg & EIC_SYNCBUSY_SWRST) >> EIC_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_eic_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Eic *)hw)->SYNCBUSY.reg & EIC_SYNCBUSY_ENABLE) >> EIC_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline hri_eic_syncbusy_reg_t hri_eic_get_SYNCBUSY_reg(const void *const hw, hri_eic_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_eic_syncbusy_reg_t hri_eic_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Eic *)hw)->SYNCBUSY.reg;
+}
+
+static inline void hri_eic_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_SWRST;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST);
+	tmp = ((Eic *)hw)->CTRLA.reg;
+	tmp = (tmp & EIC_CTRLA_SWRST) >> EIC_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_ENABLE;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE);
+	tmp = ((Eic *)hw)->CTRLA.reg;
+	tmp = (tmp & EIC_CTRLA_ENABLE) >> EIC_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CTRLA.reg;
+	tmp &= ~EIC_CTRLA_ENABLE;
+	tmp |= value << EIC_CTRLA_ENABLE_Pos;
+	((Eic *)hw)->CTRLA.reg = tmp;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRLA.reg &= ~EIC_CTRLA_ENABLE;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRLA.reg ^= EIC_CTRLA_ENABLE;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CTRLA_CKSEL_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_CKSEL;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CTRLA_CKSEL_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Eic *)hw)->CTRLA.reg;
+	tmp = (tmp & EIC_CTRLA_CKSEL) >> EIC_CTRLA_CKSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CTRLA_CKSEL_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CTRLA.reg;
+	tmp &= ~EIC_CTRLA_CKSEL;
+	tmp |= value << EIC_CTRLA_CKSEL_Pos;
+	((Eic *)hw)->CTRLA.reg = tmp;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CTRLA_CKSEL_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRLA.reg &= ~EIC_CTRLA_CKSEL;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CTRLA_CKSEL_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRLA.reg ^= EIC_CTRLA_CKSEL;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRLA.reg |= mask;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_ctrla_reg_t hri_eic_get_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
+	tmp = ((Eic *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_eic_write_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t data)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRLA.reg = data;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRLA.reg &= ~mask;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CTRLA.reg ^= mask;
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_ctrla_reg_t hri_eic_read_CTRLA_reg(const void *const hw)
+{
+	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
+	return ((Eic *)hw)->CTRLA.reg;
+}
+
+static inline void hri_eic_set_NMICTRL_NMIFILTEN_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMIFILTEN;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_NMICTRL_NMIFILTEN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Eic *)hw)->NMICTRL.reg;
+	tmp = (tmp & EIC_NMICTRL_NMIFILTEN) >> EIC_NMICTRL_NMIFILTEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_NMICTRL_NMIFILTEN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->NMICTRL.reg;
+	tmp &= ~EIC_NMICTRL_NMIFILTEN;
+	tmp |= value << EIC_NMICTRL_NMIFILTEN_Pos;
+	((Eic *)hw)->NMICTRL.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_NMICTRL_NMIFILTEN_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMIFILTEN;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_NMICTRL_NMIFILTEN_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMIFILTEN;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_NMICTRL_NMIASYNCH_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMIASYNCH;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_NMICTRL_NMIASYNCH_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Eic *)hw)->NMICTRL.reg;
+	tmp = (tmp & EIC_NMICTRL_NMIASYNCH) >> EIC_NMICTRL_NMIASYNCH_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_NMICTRL_NMIASYNCH_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->NMICTRL.reg;
+	tmp &= ~EIC_NMICTRL_NMIASYNCH;
+	tmp |= value << EIC_NMICTRL_NMIASYNCH_Pos;
+	((Eic *)hw)->NMICTRL.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_NMICTRL_NMIASYNCH_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMIASYNCH;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_NMICTRL_NMIASYNCH_bit(const void *const hw)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMIASYNCH;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMISENSE(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_nmictrl_reg_t hri_eic_get_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Eic *)hw)->NMICTRL.reg;
+	tmp = (tmp & EIC_NMICTRL_NMISENSE(mask)) >> EIC_NMICTRL_NMISENSE_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t data)
+{
+	uint8_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->NMICTRL.reg;
+	tmp &= ~EIC_NMICTRL_NMISENSE_Msk;
+	tmp |= EIC_NMICTRL_NMISENSE(data);
+	((Eic *)hw)->NMICTRL.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMISENSE(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMISENSE(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_nmictrl_reg_t hri_eic_read_NMICTRL_NMISENSE_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Eic *)hw)->NMICTRL.reg;
+	tmp = (tmp & EIC_NMICTRL_NMISENSE_Msk) >> EIC_NMICTRL_NMISENSE_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg |= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_nmictrl_reg_t hri_eic_get_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Eic *)hw)->NMICTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_eic_write_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t data)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg = data;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg &= ~mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->NMICTRL.reg ^= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_nmictrl_reg_t hri_eic_read_NMICTRL_reg(const void *const hw)
+{
+	return ((Eic *)hw)->NMICTRL.reg;
+}
+
+static inline void hri_eic_set_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_evctrl_reg_t hri_eic_get_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->EVCTRL.reg;
+	tmp = (tmp & EIC_EVCTRL_EXTINTEO(mask)) >> EIC_EVCTRL_EXTINTEO_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->EVCTRL.reg;
+	tmp &= ~EIC_EVCTRL_EXTINTEO_Msk;
+	tmp |= EIC_EVCTRL_EXTINTEO(data);
+	((Eic *)hw)->EVCTRL.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_evctrl_reg_t hri_eic_read_EVCTRL_EXTINTEO_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->EVCTRL.reg;
+	tmp = (tmp & EIC_EVCTRL_EXTINTEO_Msk) >> EIC_EVCTRL_EXTINTEO_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg |= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_evctrl_reg_t hri_eic_get_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_eic_write_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t data)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg = data;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg &= ~mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->EVCTRL.reg ^= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_evctrl_reg_t hri_eic_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Eic *)hw)->EVCTRL.reg;
+}
+
+static inline void hri_eic_set_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->ASYNCH.reg |= EIC_ASYNCH_ASYNCH(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_asynch_reg_t hri_eic_get_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->ASYNCH.reg;
+	tmp = (tmp & EIC_ASYNCH_ASYNCH(mask)) >> EIC_ASYNCH_ASYNCH_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->ASYNCH.reg;
+	tmp &= ~EIC_ASYNCH_ASYNCH_Msk;
+	tmp |= EIC_ASYNCH_ASYNCH(data);
+	((Eic *)hw)->ASYNCH.reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->ASYNCH.reg &= ~EIC_ASYNCH_ASYNCH(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->ASYNCH.reg ^= EIC_ASYNCH_ASYNCH(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_asynch_reg_t hri_eic_read_ASYNCH_ASYNCH_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->ASYNCH.reg;
+	tmp = (tmp & EIC_ASYNCH_ASYNCH_Msk) >> EIC_ASYNCH_ASYNCH_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->ASYNCH.reg |= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_asynch_reg_t hri_eic_get_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->ASYNCH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_eic_write_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t data)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->ASYNCH.reg = data;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->ASYNCH.reg &= ~mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->ASYNCH.reg ^= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_asynch_reg_t hri_eic_read_ASYNCH_reg(const void *const hw)
+{
+	return ((Eic *)hw)->ASYNCH.reg;
+}
+
+static inline void hri_eic_set_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN0;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_FILTEN0) >> EIC_CONFIG_FILTEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_FILTEN0;
+	tmp |= value << EIC_CONFIG_FILTEN0_Pos;
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN0;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN0;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN1;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_FILTEN1) >> EIC_CONFIG_FILTEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_FILTEN1;
+	tmp |= value << EIC_CONFIG_FILTEN1_Pos;
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN1;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN1;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN2;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_FILTEN2) >> EIC_CONFIG_FILTEN2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_FILTEN2;
+	tmp |= value << EIC_CONFIG_FILTEN2_Pos;
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN2;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN2;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN3;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_FILTEN3) >> EIC_CONFIG_FILTEN3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_FILTEN3;
+	tmp |= value << EIC_CONFIG_FILTEN3_Pos;
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN3;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN3;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN4;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_FILTEN4) >> EIC_CONFIG_FILTEN4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_FILTEN4;
+	tmp |= value << EIC_CONFIG_FILTEN4_Pos;
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN4;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN4;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN5;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_FILTEN5) >> EIC_CONFIG_FILTEN5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_FILTEN5;
+	tmp |= value << EIC_CONFIG_FILTEN5_Pos;
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN5;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN5;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN6;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_FILTEN6) >> EIC_CONFIG_FILTEN6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_FILTEN6;
+	tmp |= value << EIC_CONFIG_FILTEN6_Pos;
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN6;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN6;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN7;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_eic_get_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_FILTEN7) >> EIC_CONFIG_FILTEN7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_eic_write_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_FILTEN7;
+	tmp |= value << EIC_CONFIG_FILTEN7_Pos;
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN7;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN7;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_set_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE0(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE0_bf(const void *const hw, uint8_t index,
+                                                                hri_eic_config_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE0(mask)) >> EIC_CONFIG_SENSE0_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_SENSE0_Msk;
+	tmp |= EIC_CONFIG_SENSE0(data);
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE0(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE0(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE0_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE0_Msk) >> EIC_CONFIG_SENSE0_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE1(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE1_bf(const void *const hw, uint8_t index,
+                                                                hri_eic_config_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE1(mask)) >> EIC_CONFIG_SENSE1_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_SENSE1_Msk;
+	tmp |= EIC_CONFIG_SENSE1(data);
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE1(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE1(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE1_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE1_Msk) >> EIC_CONFIG_SENSE1_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE2(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE2_bf(const void *const hw, uint8_t index,
+                                                                hri_eic_config_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE2(mask)) >> EIC_CONFIG_SENSE2_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_SENSE2_Msk;
+	tmp |= EIC_CONFIG_SENSE2(data);
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE2(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE2(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE2_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE2_Msk) >> EIC_CONFIG_SENSE2_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE3(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE3_bf(const void *const hw, uint8_t index,
+                                                                hri_eic_config_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE3(mask)) >> EIC_CONFIG_SENSE3_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_SENSE3_Msk;
+	tmp |= EIC_CONFIG_SENSE3(data);
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE3(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE3(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE3_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE3_Msk) >> EIC_CONFIG_SENSE3_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE4(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE4_bf(const void *const hw, uint8_t index,
+                                                                hri_eic_config_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE4(mask)) >> EIC_CONFIG_SENSE4_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_SENSE4_Msk;
+	tmp |= EIC_CONFIG_SENSE4(data);
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE4(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE4(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE4_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE4_Msk) >> EIC_CONFIG_SENSE4_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE5(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE5_bf(const void *const hw, uint8_t index,
+                                                                hri_eic_config_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE5(mask)) >> EIC_CONFIG_SENSE5_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_SENSE5_Msk;
+	tmp |= EIC_CONFIG_SENSE5(data);
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE5(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE5(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE5_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE5_Msk) >> EIC_CONFIG_SENSE5_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE6(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE6_bf(const void *const hw, uint8_t index,
+                                                                hri_eic_config_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE6(mask)) >> EIC_CONFIG_SENSE6_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_SENSE6_Msk;
+	tmp |= EIC_CONFIG_SENSE6(data);
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE6(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE6(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE6_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE6_Msk) >> EIC_CONFIG_SENSE6_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE7(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE7_bf(const void *const hw, uint8_t index,
+                                                                hri_eic_config_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE7(mask)) >> EIC_CONFIG_SENSE7_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_write_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
+{
+	uint32_t tmp;
+	EIC_CRITICAL_SECTION_ENTER();
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= ~EIC_CONFIG_SENSE7_Msk;
+	tmp |= EIC_CONFIG_SENSE7(data);
+	((Eic *)hw)->CONFIG[index].reg = tmp;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE7(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE7(mask);
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE7_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp = (tmp & EIC_CONFIG_SENSE7_Msk) >> EIC_CONFIG_SENSE7_Pos;
+	return tmp;
+}
+
+static inline void hri_eic_set_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg |= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_get_CONFIG_reg(const void *const hw, uint8_t index,
+                                                          hri_eic_config_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Eic *)hw)->CONFIG[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_eic_write_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg = data;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_clear_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg &= ~mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_eic_toggle_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
+{
+	EIC_CRITICAL_SECTION_ENTER();
+	((Eic *)hw)->CONFIG[index].reg ^= mask;
+	EIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_eic_config_reg_t hri_eic_read_CONFIG_reg(const void *const hw, uint8_t index)
+{
+	return ((Eic *)hw)->CONFIG[index].reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_EIC_L22_H_INCLUDED */
+#endif /* _SAML22_EIC_COMPONENT_ */
diff --git a/watch-library/hardware/hri/hri_evsys_l22.h b/watch-library/hardware/hri/hri_evsys_l22.h
new file mode 100644
index 00000000..a2964f94
--- /dev/null
+++ b/watch-library/hardware/hri/hri_evsys_l22.h
@@ -0,0 +1,1333 @@
+/**
+ * \file
+ *
+ * \brief SAM EVSYS
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_EVSYS_COMPONENT_
+#ifndef _HRI_EVSYS_L22_H_INCLUDED_
+#define _HRI_EVSYS_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_EVSYS_CRITICAL_SECTIONS)
+#define EVSYS_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define EVSYS_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define EVSYS_CRITICAL_SECTION_ENTER()
+#define EVSYS_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_evsys_channel_reg_t;
+typedef uint32_t hri_evsys_chstatus_reg_t;
+typedef uint32_t hri_evsys_intenset_reg_t;
+typedef uint32_t hri_evsys_intflag_reg_t;
+typedef uint32_t hri_evsys_swevt_reg_t;
+typedef uint32_t hri_evsys_user_reg_t;
+typedef uint8_t  hri_evsys_ctrla_reg_t;
+
+static inline bool hri_evsys_get_INTFLAG_OVR0_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR0) >> EVSYS_INTFLAG_OVR0_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_OVR0_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR0;
+}
+
+static inline bool hri_evsys_get_INTFLAG_OVR1_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR1) >> EVSYS_INTFLAG_OVR1_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_OVR1_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR1;
+}
+
+static inline bool hri_evsys_get_INTFLAG_OVR2_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR2) >> EVSYS_INTFLAG_OVR2_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_OVR2_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR2;
+}
+
+static inline bool hri_evsys_get_INTFLAG_OVR3_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR3) >> EVSYS_INTFLAG_OVR3_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_OVR3_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR3;
+}
+
+static inline bool hri_evsys_get_INTFLAG_OVR4_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR4) >> EVSYS_INTFLAG_OVR4_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_OVR4_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR4;
+}
+
+static inline bool hri_evsys_get_INTFLAG_OVR5_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR5) >> EVSYS_INTFLAG_OVR5_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_OVR5_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR5;
+}
+
+static inline bool hri_evsys_get_INTFLAG_OVR6_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR6) >> EVSYS_INTFLAG_OVR6_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_OVR6_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR6;
+}
+
+static inline bool hri_evsys_get_INTFLAG_OVR7_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR7) >> EVSYS_INTFLAG_OVR7_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_OVR7_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR7;
+}
+
+static inline bool hri_evsys_get_INTFLAG_EVD0_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD0) >> EVSYS_INTFLAG_EVD0_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_EVD0_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD0;
+}
+
+static inline bool hri_evsys_get_INTFLAG_EVD1_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD1) >> EVSYS_INTFLAG_EVD1_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_EVD1_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD1;
+}
+
+static inline bool hri_evsys_get_INTFLAG_EVD2_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD2) >> EVSYS_INTFLAG_EVD2_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_EVD2_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD2;
+}
+
+static inline bool hri_evsys_get_INTFLAG_EVD3_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD3) >> EVSYS_INTFLAG_EVD3_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_EVD3_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD3;
+}
+
+static inline bool hri_evsys_get_INTFLAG_EVD4_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD4) >> EVSYS_INTFLAG_EVD4_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_EVD4_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD4;
+}
+
+static inline bool hri_evsys_get_INTFLAG_EVD5_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD5) >> EVSYS_INTFLAG_EVD5_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_EVD5_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD5;
+}
+
+static inline bool hri_evsys_get_INTFLAG_EVD6_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD6) >> EVSYS_INTFLAG_EVD6_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_EVD6_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD6;
+}
+
+static inline bool hri_evsys_get_INTFLAG_EVD7_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD7) >> EVSYS_INTFLAG_EVD7_Pos;
+}
+
+static inline void hri_evsys_clear_INTFLAG_EVD7_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD7;
+}
+
+static inline bool hri_evsys_get_interrupt_OVR0_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR0) >> EVSYS_INTFLAG_OVR0_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_OVR0_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR0;
+}
+
+static inline bool hri_evsys_get_interrupt_OVR1_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR1) >> EVSYS_INTFLAG_OVR1_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_OVR1_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR1;
+}
+
+static inline bool hri_evsys_get_interrupt_OVR2_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR2) >> EVSYS_INTFLAG_OVR2_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_OVR2_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR2;
+}
+
+static inline bool hri_evsys_get_interrupt_OVR3_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR3) >> EVSYS_INTFLAG_OVR3_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_OVR3_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR3;
+}
+
+static inline bool hri_evsys_get_interrupt_OVR4_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR4) >> EVSYS_INTFLAG_OVR4_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_OVR4_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR4;
+}
+
+static inline bool hri_evsys_get_interrupt_OVR5_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR5) >> EVSYS_INTFLAG_OVR5_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_OVR5_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR5;
+}
+
+static inline bool hri_evsys_get_interrupt_OVR6_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR6) >> EVSYS_INTFLAG_OVR6_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_OVR6_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR6;
+}
+
+static inline bool hri_evsys_get_interrupt_OVR7_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR7) >> EVSYS_INTFLAG_OVR7_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_OVR7_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR7;
+}
+
+static inline bool hri_evsys_get_interrupt_EVD0_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD0) >> EVSYS_INTFLAG_EVD0_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_EVD0_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD0;
+}
+
+static inline bool hri_evsys_get_interrupt_EVD1_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD1) >> EVSYS_INTFLAG_EVD1_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_EVD1_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD1;
+}
+
+static inline bool hri_evsys_get_interrupt_EVD2_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD2) >> EVSYS_INTFLAG_EVD2_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_EVD2_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD2;
+}
+
+static inline bool hri_evsys_get_interrupt_EVD3_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD3) >> EVSYS_INTFLAG_EVD3_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_EVD3_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD3;
+}
+
+static inline bool hri_evsys_get_interrupt_EVD4_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD4) >> EVSYS_INTFLAG_EVD4_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_EVD4_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD4;
+}
+
+static inline bool hri_evsys_get_interrupt_EVD5_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD5) >> EVSYS_INTFLAG_EVD5_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_EVD5_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD5;
+}
+
+static inline bool hri_evsys_get_interrupt_EVD6_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD6) >> EVSYS_INTFLAG_EVD6_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_EVD6_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD6;
+}
+
+static inline bool hri_evsys_get_interrupt_EVD7_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD7) >> EVSYS_INTFLAG_EVD7_Pos;
+}
+
+static inline void hri_evsys_clear_interrupt_EVD7_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD7;
+}
+
+static inline hri_evsys_intflag_reg_t hri_evsys_get_INTFLAG_reg(const void *const hw, hri_evsys_intflag_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_evsys_intflag_reg_t hri_evsys_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Evsys *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_evsys_clear_INTFLAG_reg(const void *const hw, hri_evsys_intflag_reg_t mask)
+{
+	((Evsys *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_evsys_set_INTEN_OVR0_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR0;
+}
+
+static inline bool hri_evsys_get_INTEN_OVR0_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR0) >> EVSYS_INTENSET_OVR0_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_OVR0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR0;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR0;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_OVR0_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR0;
+}
+
+static inline void hri_evsys_set_INTEN_OVR1_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR1;
+}
+
+static inline bool hri_evsys_get_INTEN_OVR1_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR1) >> EVSYS_INTENSET_OVR1_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_OVR1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR1;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR1;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_OVR1_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR1;
+}
+
+static inline void hri_evsys_set_INTEN_OVR2_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR2;
+}
+
+static inline bool hri_evsys_get_INTEN_OVR2_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR2) >> EVSYS_INTENSET_OVR2_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_OVR2_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR2;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR2;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_OVR2_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR2;
+}
+
+static inline void hri_evsys_set_INTEN_OVR3_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR3;
+}
+
+static inline bool hri_evsys_get_INTEN_OVR3_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR3) >> EVSYS_INTENSET_OVR3_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_OVR3_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR3;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR3;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_OVR3_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR3;
+}
+
+static inline void hri_evsys_set_INTEN_OVR4_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR4;
+}
+
+static inline bool hri_evsys_get_INTEN_OVR4_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR4) >> EVSYS_INTENSET_OVR4_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_OVR4_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR4;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR4;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_OVR4_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR4;
+}
+
+static inline void hri_evsys_set_INTEN_OVR5_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR5;
+}
+
+static inline bool hri_evsys_get_INTEN_OVR5_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR5) >> EVSYS_INTENSET_OVR5_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_OVR5_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR5;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR5;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_OVR5_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR5;
+}
+
+static inline void hri_evsys_set_INTEN_OVR6_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR6;
+}
+
+static inline bool hri_evsys_get_INTEN_OVR6_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR6) >> EVSYS_INTENSET_OVR6_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_OVR6_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR6;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR6;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_OVR6_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR6;
+}
+
+static inline void hri_evsys_set_INTEN_OVR7_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR7;
+}
+
+static inline bool hri_evsys_get_INTEN_OVR7_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR7) >> EVSYS_INTENSET_OVR7_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_OVR7_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR7;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR7;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_OVR7_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR7;
+}
+
+static inline void hri_evsys_set_INTEN_EVD0_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD0;
+}
+
+static inline bool hri_evsys_get_INTEN_EVD0_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD0) >> EVSYS_INTENSET_EVD0_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_EVD0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD0;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD0;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_EVD0_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD0;
+}
+
+static inline void hri_evsys_set_INTEN_EVD1_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD1;
+}
+
+static inline bool hri_evsys_get_INTEN_EVD1_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD1) >> EVSYS_INTENSET_EVD1_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_EVD1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD1;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD1;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_EVD1_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD1;
+}
+
+static inline void hri_evsys_set_INTEN_EVD2_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD2;
+}
+
+static inline bool hri_evsys_get_INTEN_EVD2_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD2) >> EVSYS_INTENSET_EVD2_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_EVD2_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD2;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD2;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_EVD2_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD2;
+}
+
+static inline void hri_evsys_set_INTEN_EVD3_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD3;
+}
+
+static inline bool hri_evsys_get_INTEN_EVD3_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD3) >> EVSYS_INTENSET_EVD3_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_EVD3_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD3;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD3;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_EVD3_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD3;
+}
+
+static inline void hri_evsys_set_INTEN_EVD4_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD4;
+}
+
+static inline bool hri_evsys_get_INTEN_EVD4_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD4) >> EVSYS_INTENSET_EVD4_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_EVD4_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD4;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD4;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_EVD4_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD4;
+}
+
+static inline void hri_evsys_set_INTEN_EVD5_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD5;
+}
+
+static inline bool hri_evsys_get_INTEN_EVD5_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD5) >> EVSYS_INTENSET_EVD5_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_EVD5_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD5;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD5;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_EVD5_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD5;
+}
+
+static inline void hri_evsys_set_INTEN_EVD6_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD6;
+}
+
+static inline bool hri_evsys_get_INTEN_EVD6_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD6) >> EVSYS_INTENSET_EVD6_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_EVD6_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD6;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD6;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_EVD6_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD6;
+}
+
+static inline void hri_evsys_set_INTEN_EVD7_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD7;
+}
+
+static inline bool hri_evsys_get_INTEN_EVD7_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD7) >> EVSYS_INTENSET_EVD7_Pos;
+}
+
+static inline void hri_evsys_write_INTEN_EVD7_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD7;
+	} else {
+		((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD7;
+	}
+}
+
+static inline void hri_evsys_clear_INTEN_EVD7_bit(const void *const hw)
+{
+	((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD7;
+}
+
+static inline void hri_evsys_set_INTEN_reg(const void *const hw, hri_evsys_intenset_reg_t mask)
+{
+	((Evsys *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_evsys_intenset_reg_t hri_evsys_get_INTEN_reg(const void *const hw, hri_evsys_intenset_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_evsys_intenset_reg_t hri_evsys_read_INTEN_reg(const void *const hw)
+{
+	return ((Evsys *)hw)->INTENSET.reg;
+}
+
+static inline void hri_evsys_write_INTEN_reg(const void *const hw, hri_evsys_intenset_reg_t data)
+{
+	((Evsys *)hw)->INTENSET.reg = data;
+	((Evsys *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_evsys_clear_INTEN_reg(const void *const hw, hri_evsys_intenset_reg_t mask)
+{
+	((Evsys *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_USRRDY0_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY0) >> EVSYS_CHSTATUS_USRRDY0_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_USRRDY1_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY1) >> EVSYS_CHSTATUS_USRRDY1_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_USRRDY2_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY2) >> EVSYS_CHSTATUS_USRRDY2_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_USRRDY3_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY3) >> EVSYS_CHSTATUS_USRRDY3_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_USRRDY4_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY4) >> EVSYS_CHSTATUS_USRRDY4_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_USRRDY5_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY5) >> EVSYS_CHSTATUS_USRRDY5_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_USRRDY6_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY6) >> EVSYS_CHSTATUS_USRRDY6_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_USRRDY7_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY7) >> EVSYS_CHSTATUS_USRRDY7_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_CHBUSY0_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY0) >> EVSYS_CHSTATUS_CHBUSY0_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_CHBUSY1_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY1) >> EVSYS_CHSTATUS_CHBUSY1_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_CHBUSY2_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY2) >> EVSYS_CHSTATUS_CHBUSY2_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_CHBUSY3_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY3) >> EVSYS_CHSTATUS_CHBUSY3_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_CHBUSY4_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY4) >> EVSYS_CHSTATUS_CHBUSY4_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_CHBUSY5_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY5) >> EVSYS_CHSTATUS_CHBUSY5_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_CHBUSY6_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY6) >> EVSYS_CHSTATUS_CHBUSY6_Pos;
+}
+
+static inline bool hri_evsys_get_CHSTATUS_CHBUSY7_bit(const void *const hw)
+{
+	return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY7) >> EVSYS_CHSTATUS_CHBUSY7_Pos;
+}
+
+static inline hri_evsys_chstatus_reg_t hri_evsys_get_CHSTATUS_reg(const void *const hw, hri_evsys_chstatus_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->CHSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_evsys_chstatus_reg_t hri_evsys_read_CHSTATUS_reg(const void *const hw)
+{
+	return ((Evsys *)hw)->CHSTATUS.reg;
+}
+
+static inline void hri_evsys_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CTRLA.reg |= EVSYS_CTRLA_SWRST;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_evsys_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Evsys *)hw)->CTRLA.reg;
+	tmp = (tmp & EVSYS_CTRLA_SWRST) >> EVSYS_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_evsys_set_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CTRLA.reg |= mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_ctrla_reg_t hri_evsys_get_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Evsys *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_evsys_write_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t data)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CTRLA.reg = data;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CTRLA.reg &= ~mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CTRLA.reg ^= mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_ctrla_reg_t hri_evsys_read_CTRLA_reg(const void *const hw)
+{
+	return ((Evsys *)hw)->CTRLA.reg;
+}
+
+static inline void hri_evsys_set_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL[index].reg |= EVSYS_CHANNEL_RUNSTDBY;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_evsys_get_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->CHANNEL[index].reg;
+	tmp = (tmp & EVSYS_CHANNEL_RUNSTDBY) >> EVSYS_CHANNEL_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_evsys_write_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->CHANNEL[index].reg;
+	tmp &= ~EVSYS_CHANNEL_RUNSTDBY;
+	tmp |= value << EVSYS_CHANNEL_RUNSTDBY_Pos;
+	((Evsys *)hw)->CHANNEL[index].reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL[index].reg &= ~EVSYS_CHANNEL_RUNSTDBY;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL[index].reg ^= EVSYS_CHANNEL_RUNSTDBY;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_set_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t index)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL[index].reg |= EVSYS_CHANNEL_ONDEMAND;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_evsys_get_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->CHANNEL[index].reg;
+	tmp = (tmp & EVSYS_CHANNEL_ONDEMAND) >> EVSYS_CHANNEL_ONDEMAND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_evsys_write_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->CHANNEL[index].reg;
+	tmp &= ~EVSYS_CHANNEL_ONDEMAND;
+	tmp |= value << EVSYS_CHANNEL_ONDEMAND_Pos;
+	((Evsys *)hw)->CHANNEL[index].reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t index)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL[index].reg &= ~EVSYS_CHANNEL_ONDEMAND;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t index)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL[index].reg ^= EVSYS_CHANNEL_ONDEMAND;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_set_CHANNEL_EVGEN_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL[index].reg |= EVSYS_CHANNEL_EVGEN(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_EVGEN_bf(const void *const hw, uint8_t index,
+                                                                     hri_evsys_channel_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->CHANNEL[index].reg;
+	tmp = (tmp & EVSYS_CHANNEL_EVGEN(mask)) >> EVSYS_CHANNEL_EVGEN_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_write_CHANNEL_EVGEN_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t data)
+{
+	uint32_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->CHANNEL[index].reg;
+	tmp &= ~EVSYS_CHANNEL_EVGEN_Msk;
+	tmp |= EVSYS_CHANNEL_EVGEN(data);
+	((Evsys *)hw)->CHANNEL[index].reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_CHANNEL_EVGEN_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL[index].reg &= ~EVSYS_CHANNEL_EVGEN(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_CHANNEL_EVGEN_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL[index].reg ^= EVSYS_CHANNEL_EVGEN(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_EVGEN_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->CHANNEL[index].reg;
+	tmp = (tmp & EVSYS_CHANNEL_EVGEN_Msk) >> EVSYS_CHANNEL_EVGEN_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_set_CHANNEL_PATH_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL[index].reg |= EVSYS_CHANNEL_PATH(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_PATH_bf(const void *const hw, uint8_t index,
+                                                                    hri_evsys_channel_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->CHANNEL[index].reg;
+	tmp = (tmp & EVSYS_CHANNEL_PATH(mask)) >> EVSYS_CHANNEL_PATH_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_write_CHANNEL_PATH_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t data)
+{
+	uint32_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->CHANNEL[index].reg;
+	tmp &= ~EVSYS_CHANNEL_PATH_Msk;
+	tmp |= EVSYS_CHANNEL_PATH(data);
+	((Evsys *)hw)->CHANNEL[index].reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_CHANNEL_PATH_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL[index].reg &= ~EVSYS_CHANNEL_PATH(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_CHANNEL_PATH_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL[index].reg ^= EVSYS_CHANNEL_PATH(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_PATH_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->CHANNEL[index].reg;
+	tmp = (tmp & EVSYS_CHANNEL_PATH_Msk) >> EVSYS_CHANNEL_PATH_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_set_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL[index].reg |= EVSYS_CHANNEL_EDGSEL(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t index,
+                                                                      hri_evsys_channel_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->CHANNEL[index].reg;
+	tmp = (tmp & EVSYS_CHANNEL_EDGSEL(mask)) >> EVSYS_CHANNEL_EDGSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_write_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t data)
+{
+	uint32_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->CHANNEL[index].reg;
+	tmp &= ~EVSYS_CHANNEL_EDGSEL_Msk;
+	tmp |= EVSYS_CHANNEL_EDGSEL(data);
+	((Evsys *)hw)->CHANNEL[index].reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL[index].reg &= ~EVSYS_CHANNEL_EDGSEL(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL[index].reg ^= EVSYS_CHANNEL_EDGSEL(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->CHANNEL[index].reg;
+	tmp = (tmp & EVSYS_CHANNEL_EDGSEL_Msk) >> EVSYS_CHANNEL_EDGSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_set_CHANNEL_reg(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL[index].reg |= mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_reg(const void *const hw, uint8_t index,
+                                                                hri_evsys_channel_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->CHANNEL[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_evsys_write_CHANNEL_reg(const void *const hw, uint8_t index, hri_evsys_channel_reg_t data)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL[index].reg = data;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_CHANNEL_reg(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL[index].reg &= ~mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_CHANNEL_reg(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->CHANNEL[index].reg ^= mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_reg(const void *const hw, uint8_t index)
+{
+	return ((Evsys *)hw)->CHANNEL[index].reg;
+}
+
+static inline void hri_evsys_set_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->USER[index].reg |= EVSYS_USER_CHANNEL(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_user_reg_t hri_evsys_get_USER_CHANNEL_bf(const void *const hw, uint8_t index,
+                                                                 hri_evsys_user_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->USER[index].reg;
+	tmp = (tmp & EVSYS_USER_CHANNEL(mask)) >> EVSYS_USER_CHANNEL_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_write_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t data)
+{
+	uint32_t tmp;
+	EVSYS_CRITICAL_SECTION_ENTER();
+	tmp = ((Evsys *)hw)->USER[index].reg;
+	tmp &= ~EVSYS_USER_CHANNEL_Msk;
+	tmp |= EVSYS_USER_CHANNEL(data);
+	((Evsys *)hw)->USER[index].reg = tmp;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->USER[index].reg &= ~EVSYS_USER_CHANNEL(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->USER[index].reg ^= EVSYS_USER_CHANNEL(mask);
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_user_reg_t hri_evsys_read_USER_CHANNEL_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->USER[index].reg;
+	tmp = (tmp & EVSYS_USER_CHANNEL_Msk) >> EVSYS_USER_CHANNEL_Pos;
+	return tmp;
+}
+
+static inline void hri_evsys_set_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->USER[index].reg |= mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_user_reg_t hri_evsys_get_USER_reg(const void *const hw, uint8_t index,
+                                                          hri_evsys_user_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Evsys *)hw)->USER[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_evsys_write_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t data)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->USER[index].reg = data;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_clear_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->USER[index].reg &= ~mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_evsys_toggle_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->USER[index].reg ^= mask;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_evsys_user_reg_t hri_evsys_read_USER_reg(const void *const hw, uint8_t index)
+{
+	return ((Evsys *)hw)->USER[index].reg;
+}
+
+static inline void hri_evsys_write_SWEVT_reg(const void *const hw, hri_evsys_swevt_reg_t data)
+{
+	EVSYS_CRITICAL_SECTION_ENTER();
+	((Evsys *)hw)->SWEVT.reg = data;
+	EVSYS_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_EVSYS_L22_H_INCLUDED */
+#endif /* _SAML22_EVSYS_COMPONENT_ */
diff --git a/watch-library/hardware/hri/hri_freqm_l22.h b/watch-library/hardware/hri/hri_freqm_l22.h
new file mode 100644
index 00000000..e221bbfd
--- /dev/null
+++ b/watch-library/hardware/hri/hri_freqm_l22.h
@@ -0,0 +1,464 @@
+/**
+ * \file
+ *
+ * \brief SAM FREQM
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_FREQM_COMPONENT_
+#ifndef _HRI_FREQM_L22_H_INCLUDED_
+#define _HRI_FREQM_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_FREQM_CRITICAL_SECTIONS)
+#define FREQM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define FREQM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define FREQM_CRITICAL_SECTION_ENTER()
+#define FREQM_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_freqm_cfga_reg_t;
+typedef uint32_t hri_freqm_syncbusy_reg_t;
+typedef uint32_t hri_freqm_value_reg_t;
+typedef uint8_t  hri_freqm_ctrla_reg_t;
+typedef uint8_t  hri_freqm_ctrlb_reg_t;
+typedef uint8_t  hri_freqm_intenset_reg_t;
+typedef uint8_t  hri_freqm_intflag_reg_t;
+typedef uint8_t  hri_freqm_status_reg_t;
+
+static inline void hri_freqm_wait_for_sync(const void *const hw, hri_freqm_syncbusy_reg_t reg)
+{
+	while (((Freqm *)hw)->SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_freqm_is_syncing(const void *const hw, hri_freqm_syncbusy_reg_t reg)
+{
+	return ((Freqm *)hw)->SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_freqm_get_INTFLAG_DONE_bit(const void *const hw)
+{
+	return (((Freqm *)hw)->INTFLAG.reg & FREQM_INTFLAG_DONE) >> FREQM_INTFLAG_DONE_Pos;
+}
+
+static inline void hri_freqm_clear_INTFLAG_DONE_bit(const void *const hw)
+{
+	((Freqm *)hw)->INTFLAG.reg = FREQM_INTFLAG_DONE;
+}
+
+static inline bool hri_freqm_get_interrupt_DONE_bit(const void *const hw)
+{
+	return (((Freqm *)hw)->INTFLAG.reg & FREQM_INTFLAG_DONE) >> FREQM_INTFLAG_DONE_Pos;
+}
+
+static inline void hri_freqm_clear_interrupt_DONE_bit(const void *const hw)
+{
+	((Freqm *)hw)->INTFLAG.reg = FREQM_INTFLAG_DONE;
+}
+
+static inline hri_freqm_intflag_reg_t hri_freqm_get_INTFLAG_reg(const void *const hw, hri_freqm_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Freqm *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_freqm_intflag_reg_t hri_freqm_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Freqm *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_freqm_clear_INTFLAG_reg(const void *const hw, hri_freqm_intflag_reg_t mask)
+{
+	((Freqm *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_freqm_set_INTEN_DONE_bit(const void *const hw)
+{
+	((Freqm *)hw)->INTENSET.reg = FREQM_INTENSET_DONE;
+}
+
+static inline bool hri_freqm_get_INTEN_DONE_bit(const void *const hw)
+{
+	return (((Freqm *)hw)->INTENSET.reg & FREQM_INTENSET_DONE) >> FREQM_INTENSET_DONE_Pos;
+}
+
+static inline void hri_freqm_write_INTEN_DONE_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Freqm *)hw)->INTENCLR.reg = FREQM_INTENSET_DONE;
+	} else {
+		((Freqm *)hw)->INTENSET.reg = FREQM_INTENSET_DONE;
+	}
+}
+
+static inline void hri_freqm_clear_INTEN_DONE_bit(const void *const hw)
+{
+	((Freqm *)hw)->INTENCLR.reg = FREQM_INTENSET_DONE;
+}
+
+static inline void hri_freqm_set_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask)
+{
+	((Freqm *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_freqm_intenset_reg_t hri_freqm_get_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Freqm *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_freqm_intenset_reg_t hri_freqm_read_INTEN_reg(const void *const hw)
+{
+	return ((Freqm *)hw)->INTENSET.reg;
+}
+
+static inline void hri_freqm_write_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t data)
+{
+	((Freqm *)hw)->INTENSET.reg = data;
+	((Freqm *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_freqm_clear_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask)
+{
+	((Freqm *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_freqm_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Freqm *)hw)->SYNCBUSY.reg & FREQM_SYNCBUSY_SWRST) >> FREQM_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_freqm_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Freqm *)hw)->SYNCBUSY.reg & FREQM_SYNCBUSY_ENABLE) >> FREQM_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline hri_freqm_syncbusy_reg_t hri_freqm_get_SYNCBUSY_reg(const void *const hw, hri_freqm_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Freqm *)hw)->SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_freqm_syncbusy_reg_t hri_freqm_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Freqm *)hw)->SYNCBUSY.reg;
+}
+
+static inline hri_freqm_value_reg_t hri_freqm_get_VALUE_VALUE_bf(const void *const hw, hri_freqm_value_reg_t mask)
+{
+	return (((Freqm *)hw)->VALUE.reg & FREQM_VALUE_VALUE(mask)) >> FREQM_VALUE_VALUE_Pos;
+}
+
+static inline hri_freqm_value_reg_t hri_freqm_read_VALUE_VALUE_bf(const void *const hw)
+{
+	return (((Freqm *)hw)->VALUE.reg & FREQM_VALUE_VALUE_Msk) >> FREQM_VALUE_VALUE_Pos;
+}
+
+static inline hri_freqm_value_reg_t hri_freqm_get_VALUE_reg(const void *const hw, hri_freqm_value_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Freqm *)hw)->VALUE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_freqm_value_reg_t hri_freqm_read_VALUE_reg(const void *const hw)
+{
+	return ((Freqm *)hw)->VALUE.reg;
+}
+
+static inline void hri_freqm_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CTRLA.reg |= FREQM_CTRLA_SWRST;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_freqm_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST);
+	tmp = ((Freqm *)hw)->CTRLA.reg;
+	tmp = (tmp & FREQM_CTRLA_SWRST) >> FREQM_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_freqm_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CTRLA.reg |= FREQM_CTRLA_ENABLE;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_freqm_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE);
+	tmp = ((Freqm *)hw)->CTRLA.reg;
+	tmp = (tmp & FREQM_CTRLA_ENABLE) >> FREQM_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_freqm_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	FREQM_CRITICAL_SECTION_ENTER();
+	tmp = ((Freqm *)hw)->CTRLA.reg;
+	tmp &= ~FREQM_CTRLA_ENABLE;
+	tmp |= value << FREQM_CTRLA_ENABLE_Pos;
+	((Freqm *)hw)->CTRLA.reg = tmp;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_freqm_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CTRLA.reg &= ~FREQM_CTRLA_ENABLE;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_freqm_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CTRLA.reg ^= FREQM_CTRLA_ENABLE;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_freqm_set_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CTRLA.reg |= mask;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_freqm_ctrla_reg_t hri_freqm_get_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK);
+	tmp = ((Freqm *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_freqm_write_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t data)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CTRLA.reg = data;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_freqm_clear_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CTRLA.reg &= ~mask;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_freqm_toggle_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CTRLA.reg ^= mask;
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_freqm_ctrla_reg_t hri_freqm_read_CTRLA_reg(const void *const hw)
+{
+	hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK);
+	return ((Freqm *)hw)->CTRLA.reg;
+}
+
+static inline void hri_freqm_set_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CFGA.reg |= FREQM_CFGA_REFNUM(mask);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_freqm_cfga_reg_t hri_freqm_get_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Freqm *)hw)->CFGA.reg;
+	tmp = (tmp & FREQM_CFGA_REFNUM(mask)) >> FREQM_CFGA_REFNUM_Pos;
+	return tmp;
+}
+
+static inline void hri_freqm_write_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t data)
+{
+	uint16_t tmp;
+	FREQM_CRITICAL_SECTION_ENTER();
+	tmp = ((Freqm *)hw)->CFGA.reg;
+	tmp &= ~FREQM_CFGA_REFNUM_Msk;
+	tmp |= FREQM_CFGA_REFNUM(data);
+	((Freqm *)hw)->CFGA.reg = tmp;
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_freqm_clear_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CFGA.reg &= ~FREQM_CFGA_REFNUM(mask);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_freqm_toggle_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CFGA.reg ^= FREQM_CFGA_REFNUM(mask);
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_freqm_cfga_reg_t hri_freqm_read_CFGA_REFNUM_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Freqm *)hw)->CFGA.reg;
+	tmp = (tmp & FREQM_CFGA_REFNUM_Msk) >> FREQM_CFGA_REFNUM_Pos;
+	return tmp;
+}
+
+static inline void hri_freqm_set_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CFGA.reg |= mask;
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_freqm_cfga_reg_t hri_freqm_get_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Freqm *)hw)->CFGA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_freqm_write_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t data)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CFGA.reg = data;
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_freqm_clear_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CFGA.reg &= ~mask;
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_freqm_toggle_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CFGA.reg ^= mask;
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_freqm_cfga_reg_t hri_freqm_read_CFGA_reg(const void *const hw)
+{
+	return ((Freqm *)hw)->CFGA.reg;
+}
+
+static inline bool hri_freqm_get_STATUS_BUSY_bit(const void *const hw)
+{
+	return (((Freqm *)hw)->STATUS.reg & FREQM_STATUS_BUSY) >> FREQM_STATUS_BUSY_Pos;
+}
+
+static inline void hri_freqm_clear_STATUS_BUSY_bit(const void *const hw)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->STATUS.reg = FREQM_STATUS_BUSY;
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_freqm_get_STATUS_OVF_bit(const void *const hw)
+{
+	return (((Freqm *)hw)->STATUS.reg & FREQM_STATUS_OVF) >> FREQM_STATUS_OVF_Pos;
+}
+
+static inline void hri_freqm_clear_STATUS_OVF_bit(const void *const hw)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->STATUS.reg = FREQM_STATUS_OVF;
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_freqm_status_reg_t hri_freqm_get_STATUS_reg(const void *const hw, hri_freqm_status_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Freqm *)hw)->STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_freqm_clear_STATUS_reg(const void *const hw, hri_freqm_status_reg_t mask)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->STATUS.reg = mask;
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_freqm_status_reg_t hri_freqm_read_STATUS_reg(const void *const hw)
+{
+	return ((Freqm *)hw)->STATUS.reg;
+}
+
+static inline void hri_freqm_write_CTRLB_reg(const void *const hw, hri_freqm_ctrlb_reg_t data)
+{
+	FREQM_CRITICAL_SECTION_ENTER();
+	((Freqm *)hw)->CTRLB.reg = data;
+	FREQM_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_FREQM_L22_H_INCLUDED */
+#endif /* _SAML22_FREQM_COMPONENT_ */
diff --git a/watch-library/hardware/hri/hri_gclk_l22.h b/watch-library/hardware/hri/hri_gclk_l22.h
new file mode 100644
index 00000000..2ae6d491
--- /dev/null
+++ b/watch-library/hardware/hri/hri_gclk_l22.h
@@ -0,0 +1,770 @@
+/**
+ * \file
+ *
+ * \brief SAM GCLK
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_GCLK_COMPONENT_
+#ifndef _HRI_GCLK_L22_H_INCLUDED_
+#define _HRI_GCLK_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_GCLK_CRITICAL_SECTIONS)
+#define GCLK_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define GCLK_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define GCLK_CRITICAL_SECTION_ENTER()
+#define GCLK_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_gclk_genctrl_reg_t;
+typedef uint32_t hri_gclk_pchctrl_reg_t;
+typedef uint32_t hri_gclk_syncbusy_reg_t;
+typedef uint8_t  hri_gclk_ctrla_reg_t;
+
+static inline void hri_gclk_wait_for_sync(const void *const hw, hri_gclk_syncbusy_reg_t reg)
+{
+	while (((Gclk *)hw)->SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_gclk_is_syncing(const void *const hw, hri_gclk_syncbusy_reg_t reg)
+{
+	return ((Gclk *)hw)->SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_gclk_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_SWRST) >> GCLK_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_gclk_get_SYNCBUSY_GENCTRL0_bit(const void *const hw)
+{
+	return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL0) >> GCLK_SYNCBUSY_GENCTRL0_Pos;
+}
+
+static inline bool hri_gclk_get_SYNCBUSY_GENCTRL1_bit(const void *const hw)
+{
+	return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL1) >> GCLK_SYNCBUSY_GENCTRL1_Pos;
+}
+
+static inline bool hri_gclk_get_SYNCBUSY_GENCTRL2_bit(const void *const hw)
+{
+	return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL2) >> GCLK_SYNCBUSY_GENCTRL2_Pos;
+}
+
+static inline bool hri_gclk_get_SYNCBUSY_GENCTRL3_bit(const void *const hw)
+{
+	return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL3) >> GCLK_SYNCBUSY_GENCTRL3_Pos;
+}
+
+static inline bool hri_gclk_get_SYNCBUSY_GENCTRL4_bit(const void *const hw)
+{
+	return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL4) >> GCLK_SYNCBUSY_GENCTRL4_Pos;
+}
+
+static inline hri_gclk_syncbusy_reg_t hri_gclk_get_SYNCBUSY_reg(const void *const hw, hri_gclk_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_gclk_syncbusy_reg_t hri_gclk_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Gclk *)hw)->SYNCBUSY.reg;
+}
+
+static inline void hri_gclk_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->CTRLA.reg |= GCLK_CTRLA_SWRST;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_gclk_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
+	tmp = ((Gclk *)hw)->CTRLA.reg;
+	tmp = (tmp & GCLK_CTRLA_SWRST) >> GCLK_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_gclk_set_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->CTRLA.reg |= mask;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_ctrla_reg_t hri_gclk_get_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
+	tmp = ((Gclk *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gclk_write_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t data)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->CTRLA.reg = data;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->CTRLA.reg &= ~mask;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->CTRLA.reg ^= mask;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_ctrla_reg_t hri_gclk_read_CTRLA_reg(const void *const hw)
+{
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
+	return ((Gclk *)hw)->CTRLA.reg;
+}
+
+static inline void hri_gclk_set_GENCTRL_GENEN_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_GENEN;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_gclk_get_GENCTRL_GENEN_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp = (tmp & GCLK_GENCTRL_GENEN) >> GCLK_GENCTRL_GENEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_gclk_write_GENCTRL_GENEN_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp &= ~GCLK_GENCTRL_GENEN;
+	tmp |= value << GCLK_GENCTRL_GENEN_Pos;
+	((Gclk *)hw)->GENCTRL[index].reg = tmp;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENCTRL_GENEN_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_GENEN;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENCTRL_GENEN_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_GENEN;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_set_GENCTRL_IDC_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_IDC;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_gclk_get_GENCTRL_IDC_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp = (tmp & GCLK_GENCTRL_IDC) >> GCLK_GENCTRL_IDC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_gclk_write_GENCTRL_IDC_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp &= ~GCLK_GENCTRL_IDC;
+	tmp |= value << GCLK_GENCTRL_IDC_Pos;
+	((Gclk *)hw)->GENCTRL[index].reg = tmp;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENCTRL_IDC_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_IDC;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENCTRL_IDC_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_IDC;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_set_GENCTRL_OOV_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_OOV;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_gclk_get_GENCTRL_OOV_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp = (tmp & GCLK_GENCTRL_OOV) >> GCLK_GENCTRL_OOV_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_gclk_write_GENCTRL_OOV_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp &= ~GCLK_GENCTRL_OOV;
+	tmp |= value << GCLK_GENCTRL_OOV_Pos;
+	((Gclk *)hw)->GENCTRL[index].reg = tmp;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENCTRL_OOV_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_OOV;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENCTRL_OOV_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_OOV;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_set_GENCTRL_OE_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_OE;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_gclk_get_GENCTRL_OE_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp = (tmp & GCLK_GENCTRL_OE) >> GCLK_GENCTRL_OE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_gclk_write_GENCTRL_OE_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp &= ~GCLK_GENCTRL_OE;
+	tmp |= value << GCLK_GENCTRL_OE_Pos;
+	((Gclk *)hw)->GENCTRL[index].reg = tmp;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENCTRL_OE_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_OE;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENCTRL_OE_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_OE;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_set_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_DIVSEL;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_gclk_get_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp = (tmp & GCLK_GENCTRL_DIVSEL) >> GCLK_GENCTRL_DIVSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_gclk_write_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp &= ~GCLK_GENCTRL_DIVSEL;
+	tmp |= value << GCLK_GENCTRL_DIVSEL_Pos;
+	((Gclk *)hw)->GENCTRL[index].reg = tmp;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_DIVSEL;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_DIVSEL;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_set_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_RUNSTDBY;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_gclk_get_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp = (tmp & GCLK_GENCTRL_RUNSTDBY) >> GCLK_GENCTRL_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_gclk_write_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp &= ~GCLK_GENCTRL_RUNSTDBY;
+	tmp |= value << GCLK_GENCTRL_RUNSTDBY_Pos;
+	((Gclk *)hw)->GENCTRL[index].reg = tmp;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_RUNSTDBY;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_RUNSTDBY;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_set_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_SRC(mask);
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_SRC_bf(const void *const hw, uint8_t index,
+                                                                 hri_gclk_genctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp = (tmp & GCLK_GENCTRL_SRC(mask)) >> GCLK_GENCTRL_SRC_Pos;
+	return tmp;
+}
+
+static inline void hri_gclk_write_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp &= ~GCLK_GENCTRL_SRC_Msk;
+	tmp |= GCLK_GENCTRL_SRC(data);
+	((Gclk *)hw)->GENCTRL[index].reg = tmp;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_SRC(mask);
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_SRC(mask);
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_SRC_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp = (tmp & GCLK_GENCTRL_SRC_Msk) >> GCLK_GENCTRL_SRC_Pos;
+	return tmp;
+}
+
+static inline void hri_gclk_set_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_DIV(mask);
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_DIV_bf(const void *const hw, uint8_t index,
+                                                                 hri_gclk_genctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp = (tmp & GCLK_GENCTRL_DIV(mask)) >> GCLK_GENCTRL_DIV_Pos;
+	return tmp;
+}
+
+static inline void hri_gclk_write_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp &= ~GCLK_GENCTRL_DIV_Msk;
+	tmp |= GCLK_GENCTRL_DIV(data);
+	((Gclk *)hw)->GENCTRL[index].reg = tmp;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_DIV(mask);
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_DIV(mask);
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_DIV_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp = (tmp & GCLK_GENCTRL_DIV_Msk) >> GCLK_GENCTRL_DIV_Pos;
+	return tmp;
+}
+
+static inline void hri_gclk_set_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg |= mask;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_reg(const void *const hw, uint8_t index,
+                                                              hri_gclk_genctrl_reg_t mask)
+{
+	uint32_t tmp;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	tmp = ((Gclk *)hw)->GENCTRL[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gclk_write_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg = data;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg &= ~mask;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->GENCTRL[index].reg ^= mask;
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_reg(const void *const hw, uint8_t index)
+{
+	hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
+	return ((Gclk *)hw)->GENCTRL[index].reg;
+}
+
+static inline void hri_gclk_set_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_CHEN;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_gclk_get_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
+	tmp = (tmp & GCLK_PCHCTRL_CHEN) >> GCLK_PCHCTRL_CHEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_gclk_write_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
+	tmp &= ~GCLK_PCHCTRL_CHEN;
+	tmp |= value << GCLK_PCHCTRL_CHEN_Pos;
+	((Gclk *)hw)->PCHCTRL[index].reg = tmp;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_CHEN;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_CHEN;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_set_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_WRTLOCK;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_gclk_get_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
+	tmp = (tmp & GCLK_PCHCTRL_WRTLOCK) >> GCLK_PCHCTRL_WRTLOCK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_gclk_write_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
+	tmp &= ~GCLK_PCHCTRL_WRTLOCK;
+	tmp |= value << GCLK_PCHCTRL_WRTLOCK_Pos;
+	((Gclk *)hw)->PCHCTRL[index].reg = tmp;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_WRTLOCK;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_WRTLOCK;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_set_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_GEN(mask);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_pchctrl_reg_t hri_gclk_get_PCHCTRL_GEN_bf(const void *const hw, uint8_t index,
+                                                                 hri_gclk_pchctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
+	tmp = (tmp & GCLK_PCHCTRL_GEN(mask)) >> GCLK_PCHCTRL_GEN_Pos;
+	return tmp;
+}
+
+static inline void hri_gclk_write_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data)
+{
+	uint32_t tmp;
+	GCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
+	tmp &= ~GCLK_PCHCTRL_GEN_Msk;
+	tmp |= GCLK_PCHCTRL_GEN(data);
+	((Gclk *)hw)->PCHCTRL[index].reg = tmp;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_GEN(mask);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_GEN(mask);
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_pchctrl_reg_t hri_gclk_read_PCHCTRL_GEN_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
+	tmp = (tmp & GCLK_PCHCTRL_GEN_Msk) >> GCLK_PCHCTRL_GEN_Pos;
+	return tmp;
+}
+
+static inline void hri_gclk_set_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg |= mask;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_pchctrl_reg_t hri_gclk_get_PCHCTRL_reg(const void *const hw, uint8_t index,
+                                                              hri_gclk_pchctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_gclk_write_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg = data;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_clear_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg &= ~mask;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_gclk_toggle_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask)
+{
+	GCLK_CRITICAL_SECTION_ENTER();
+	((Gclk *)hw)->PCHCTRL[index].reg ^= mask;
+	GCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_gclk_pchctrl_reg_t hri_gclk_read_PCHCTRL_reg(const void *const hw, uint8_t index)
+{
+	return ((Gclk *)hw)->PCHCTRL[index].reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_GCLK_L22_H_INCLUDED */
+#endif /* _SAML22_GCLK_COMPONENT_ */
diff --git a/watch-library/hardware/hri/hri_l22.h b/watch-library/hardware/hri/hri_l22.h
new file mode 100644
index 00000000..d99268c1
--- /dev/null
+++ b/watch-library/hardware/hri/hri_l22.h
@@ -0,0 +1,70 @@
+/**
+ * \file
+ *
+ * \brief SAM L22 HRI top-level header file
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HRI_L22_H_INCLUDED_
+#define _HRI_L22_H_INCLUDED_
+
+#include <sam.h>
+#include <hri_ac_l22.h>
+#include <hri_adc_l22.h>
+#include <hri_aes_l22.h>
+#include <hri_ccl_l22.h>
+#include <hri_dmac_l22.h>
+#include <hri_dsu_l22.h>
+#include <hri_eic_l22.h>
+#include <hri_evsys_l22.h>
+#include <hri_freqm_l22.h>
+#include <hri_gclk_l22.h>
+#include <hri_mclk_l22.h>
+#include <hri_mtb_l22.h>
+#include <hri_nvic_l22.h>
+#include <hri_nvmctrl_l22.h>
+#include <hri_osc32kctrl_l22.h>
+#include <hri_oscctrl_l22.h>
+#include <hri_pac_l22.h>
+#include <hri_pm_l22.h>
+#include <hri_port_l22.h>
+#include <hri_rstc_l22.h>
+#include <hri_rtc_l22.h>
+#include <hri_sercom_l22.h>
+#include <hri_slcd_l22.h>
+#include <hri_supc_l22.h>
+#include <hri_systemcontrol_l22.h>
+#include <hri_systick_l22.h>
+#include <hri_tc_l22.h>
+#include <hri_tcc_l22.h>
+#include <hri_trng_l22.h>
+#include <hri_usb_l22.h>
+#include <hri_wdt_l22.h>
+
+#endif /* _HRI_L22_H_INCLUDED_ */
diff --git a/watch-library/hardware/hri/hri_mclk_l22.h b/watch-library/hardware/hri/hri_mclk_l22.h
new file mode 100644
index 00000000..b03c0064
--- /dev/null
+++ b/watch-library/hardware/hri/hri_mclk_l22.h
@@ -0,0 +1,2300 @@
+/**
+ * \file
+ *
+ * \brief SAM MCLK
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_MCLK_COMPONENT_
+#ifndef _HRI_MCLK_L22_H_INCLUDED_
+#define _HRI_MCLK_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_MCLK_CRITICAL_SECTIONS)
+#define MCLK_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define MCLK_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define MCLK_CRITICAL_SECTION_ENTER()
+#define MCLK_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_mclk_ahbmask_reg_t;
+typedef uint32_t hri_mclk_apbamask_reg_t;
+typedef uint32_t hri_mclk_apbbmask_reg_t;
+typedef uint32_t hri_mclk_apbcmask_reg_t;
+typedef uint8_t  hri_mclk_bupdiv_reg_t;
+typedef uint8_t  hri_mclk_cpudiv_reg_t;
+typedef uint8_t  hri_mclk_intenset_reg_t;
+typedef uint8_t  hri_mclk_intflag_reg_t;
+
+static inline bool hri_mclk_get_INTFLAG_CKRDY_bit(const void *const hw)
+{
+	return (((Mclk *)hw)->INTFLAG.reg & MCLK_INTFLAG_CKRDY) >> MCLK_INTFLAG_CKRDY_Pos;
+}
+
+static inline void hri_mclk_clear_INTFLAG_CKRDY_bit(const void *const hw)
+{
+	((Mclk *)hw)->INTFLAG.reg = MCLK_INTFLAG_CKRDY;
+}
+
+static inline bool hri_mclk_get_interrupt_CKRDY_bit(const void *const hw)
+{
+	return (((Mclk *)hw)->INTFLAG.reg & MCLK_INTFLAG_CKRDY) >> MCLK_INTFLAG_CKRDY_Pos;
+}
+
+static inline void hri_mclk_clear_interrupt_CKRDY_bit(const void *const hw)
+{
+	((Mclk *)hw)->INTFLAG.reg = MCLK_INTFLAG_CKRDY;
+}
+
+static inline hri_mclk_intflag_reg_t hri_mclk_get_INTFLAG_reg(const void *const hw, hri_mclk_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Mclk *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mclk_intflag_reg_t hri_mclk_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Mclk *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_mclk_clear_INTFLAG_reg(const void *const hw, hri_mclk_intflag_reg_t mask)
+{
+	((Mclk *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_mclk_set_INTEN_CKRDY_bit(const void *const hw)
+{
+	((Mclk *)hw)->INTENSET.reg = MCLK_INTENSET_CKRDY;
+}
+
+static inline bool hri_mclk_get_INTEN_CKRDY_bit(const void *const hw)
+{
+	return (((Mclk *)hw)->INTENSET.reg & MCLK_INTENSET_CKRDY) >> MCLK_INTENSET_CKRDY_Pos;
+}
+
+static inline void hri_mclk_write_INTEN_CKRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Mclk *)hw)->INTENCLR.reg = MCLK_INTENSET_CKRDY;
+	} else {
+		((Mclk *)hw)->INTENSET.reg = MCLK_INTENSET_CKRDY;
+	}
+}
+
+static inline void hri_mclk_clear_INTEN_CKRDY_bit(const void *const hw)
+{
+	((Mclk *)hw)->INTENCLR.reg = MCLK_INTENSET_CKRDY;
+}
+
+static inline void hri_mclk_set_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask)
+{
+	((Mclk *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_mclk_intenset_reg_t hri_mclk_get_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Mclk *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mclk_intenset_reg_t hri_mclk_read_INTEN_reg(const void *const hw)
+{
+	return ((Mclk *)hw)->INTENSET.reg;
+}
+
+static inline void hri_mclk_write_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t data)
+{
+	((Mclk *)hw)->INTENSET.reg = data;
+	((Mclk *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_mclk_clear_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask)
+{
+	((Mclk *)hw)->INTENCLR.reg = mask;
+}
+
+static inline void hri_mclk_set_CPUDIV_CPUDIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->CPUDIV.reg |= MCLK_CPUDIV_CPUDIV(mask);
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_cpudiv_reg_t hri_mclk_get_CPUDIV_CPUDIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Mclk *)hw)->CPUDIV.reg;
+	tmp = (tmp & MCLK_CPUDIV_CPUDIV(mask)) >> MCLK_CPUDIV_CPUDIV_Pos;
+	return tmp;
+}
+
+static inline void hri_mclk_write_CPUDIV_CPUDIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t data)
+{
+	uint8_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->CPUDIV.reg;
+	tmp &= ~MCLK_CPUDIV_CPUDIV_Msk;
+	tmp |= MCLK_CPUDIV_CPUDIV(data);
+	((Mclk *)hw)->CPUDIV.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_CPUDIV_CPUDIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->CPUDIV.reg &= ~MCLK_CPUDIV_CPUDIV(mask);
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_CPUDIV_CPUDIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->CPUDIV.reg ^= MCLK_CPUDIV_CPUDIV(mask);
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_cpudiv_reg_t hri_mclk_read_CPUDIV_CPUDIV_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Mclk *)hw)->CPUDIV.reg;
+	tmp = (tmp & MCLK_CPUDIV_CPUDIV_Msk) >> MCLK_CPUDIV_CPUDIV_Pos;
+	return tmp;
+}
+
+static inline void hri_mclk_set_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->CPUDIV.reg |= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_cpudiv_reg_t hri_mclk_get_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Mclk *)hw)->CPUDIV.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_mclk_write_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t data)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->CPUDIV.reg = data;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->CPUDIV.reg &= ~mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->CPUDIV.reg ^= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_cpudiv_reg_t hri_mclk_read_CPUDIV_reg(const void *const hw)
+{
+	return ((Mclk *)hw)->CPUDIV.reg;
+}
+
+static inline void hri_mclk_set_BUPDIV_BUPDIV_bf(const void *const hw, hri_mclk_bupdiv_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->BUPDIV.reg |= MCLK_BUPDIV_BUPDIV(mask);
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_bupdiv_reg_t hri_mclk_get_BUPDIV_BUPDIV_bf(const void *const hw, hri_mclk_bupdiv_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Mclk *)hw)->BUPDIV.reg;
+	tmp = (tmp & MCLK_BUPDIV_BUPDIV(mask)) >> MCLK_BUPDIV_BUPDIV_Pos;
+	return tmp;
+}
+
+static inline void hri_mclk_write_BUPDIV_BUPDIV_bf(const void *const hw, hri_mclk_bupdiv_reg_t data)
+{
+	uint8_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->BUPDIV.reg;
+	tmp &= ~MCLK_BUPDIV_BUPDIV_Msk;
+	tmp |= MCLK_BUPDIV_BUPDIV(data);
+	((Mclk *)hw)->BUPDIV.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_BUPDIV_BUPDIV_bf(const void *const hw, hri_mclk_bupdiv_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->BUPDIV.reg &= ~MCLK_BUPDIV_BUPDIV(mask);
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_BUPDIV_BUPDIV_bf(const void *const hw, hri_mclk_bupdiv_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->BUPDIV.reg ^= MCLK_BUPDIV_BUPDIV(mask);
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_bupdiv_reg_t hri_mclk_read_BUPDIV_BUPDIV_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Mclk *)hw)->BUPDIV.reg;
+	tmp = (tmp & MCLK_BUPDIV_BUPDIV_Msk) >> MCLK_BUPDIV_BUPDIV_Pos;
+	return tmp;
+}
+
+static inline void hri_mclk_set_BUPDIV_reg(const void *const hw, hri_mclk_bupdiv_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->BUPDIV.reg |= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_bupdiv_reg_t hri_mclk_get_BUPDIV_reg(const void *const hw, hri_mclk_bupdiv_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Mclk *)hw)->BUPDIV.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_mclk_write_BUPDIV_reg(const void *const hw, hri_mclk_bupdiv_reg_t data)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->BUPDIV.reg = data;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_BUPDIV_reg(const void *const hw, hri_mclk_bupdiv_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->BUPDIV.reg &= ~mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_BUPDIV_reg(const void *const hw, hri_mclk_bupdiv_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->BUPDIV.reg ^= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_bupdiv_reg_t hri_mclk_read_BUPDIV_reg(const void *const hw)
+{
+	return ((Mclk *)hw)->BUPDIV.reg;
+}
+
+static inline void hri_mclk_set_AHBMASK_HPB0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_HPB0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_HPB0) >> MCLK_AHBMASK_HPB0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_HPB0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_HPB0;
+	tmp |= value << MCLK_AHBMASK_HPB0_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_HPB0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_HPB0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_HPB1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_HPB1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_HPB1) >> MCLK_AHBMASK_HPB1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_HPB1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_HPB1;
+	tmp |= value << MCLK_AHBMASK_HPB1_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_HPB1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_HPB1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_HPB2_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB2;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_HPB2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_HPB2) >> MCLK_AHBMASK_HPB2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_HPB2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_HPB2;
+	tmp |= value << MCLK_AHBMASK_HPB2_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_HPB2_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB2;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_HPB2_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB2;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_DMAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_DMAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_DMAC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_DMAC) >> MCLK_AHBMASK_DMAC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_DMAC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_DMAC;
+	tmp |= value << MCLK_AHBMASK_DMAC_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_DMAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_DMAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_DMAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_DMAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_USB_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_USB;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_USB_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_USB) >> MCLK_AHBMASK_USB_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_USB_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_USB;
+	tmp |= value << MCLK_AHBMASK_USB_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_USB_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_USB;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_USB_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_USB;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_DSU_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_DSU;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_DSU_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_DSU) >> MCLK_AHBMASK_DSU_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_DSU_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_DSU;
+	tmp |= value << MCLK_AHBMASK_DSU_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_DSU_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_DSU;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_DSU_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_DSU;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_PAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_PAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_PAC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_PAC) >> MCLK_AHBMASK_PAC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_PAC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_PAC;
+	tmp |= value << MCLK_AHBMASK_PAC_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_PAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_PAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_PAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_PAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_NVMCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_NVMCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_NVMCTRL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_NVMCTRL) >> MCLK_AHBMASK_NVMCTRL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_NVMCTRL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_NVMCTRL;
+	tmp |= value << MCLK_AHBMASK_NVMCTRL_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_NVMCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_NVMCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_NVMCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_NVMCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_HSRAM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HSRAM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_HSRAM_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_HSRAM) >> MCLK_AHBMASK_HSRAM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_HSRAM_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_HSRAM;
+	tmp |= value << MCLK_AHBMASK_HSRAM_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_HSRAM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HSRAM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_HSRAM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HSRAM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_NVMCTRL_PICACHU_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_NVMCTRL_PICACHU;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_AHBMASK_NVMCTRL_PICACHU_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp = (tmp & MCLK_AHBMASK_NVMCTRL_PICACHU) >> MCLK_AHBMASK_NVMCTRL_PICACHU_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_NVMCTRL_PICACHU_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= ~MCLK_AHBMASK_NVMCTRL_PICACHU;
+	tmp |= value << MCLK_AHBMASK_NVMCTRL_PICACHU_Pos;
+	((Mclk *)hw)->AHBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_NVMCTRL_PICACHU_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_NVMCTRL_PICACHU;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_NVMCTRL_PICACHU_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_NVMCTRL_PICACHU;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg |= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_ahbmask_reg_t hri_mclk_get_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->AHBMASK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_mclk_write_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t data)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg = data;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg &= ~mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->AHBMASK.reg ^= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_ahbmask_reg_t hri_mclk_read_AHBMASK_reg(const void *const hw)
+{
+	return ((Mclk *)hw)->AHBMASK.reg;
+}
+
+static inline void hri_mclk_set_APBAMASK_PAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_PAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_PAC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_PAC) >> MCLK_APBAMASK_PAC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_PAC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_PAC;
+	tmp |= value << MCLK_APBAMASK_PAC_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_PAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_PAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_PAC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_PAC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_PM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_PM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_PM_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_PM) >> MCLK_APBAMASK_PM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_PM_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_PM;
+	tmp |= value << MCLK_APBAMASK_PM_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_PM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_PM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_PM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_PM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_MCLK_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_MCLK;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_MCLK_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_MCLK) >> MCLK_APBAMASK_MCLK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_MCLK_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_MCLK;
+	tmp |= value << MCLK_APBAMASK_MCLK_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_MCLK_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_MCLK;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_MCLK_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_MCLK;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_RSTC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_RSTC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_RSTC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_RSTC) >> MCLK_APBAMASK_RSTC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_RSTC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_RSTC;
+	tmp |= value << MCLK_APBAMASK_RSTC_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_RSTC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_RSTC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_RSTC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_RSTC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_OSCCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_OSCCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_OSCCTRL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_OSCCTRL) >> MCLK_APBAMASK_OSCCTRL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_OSCCTRL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_OSCCTRL;
+	tmp |= value << MCLK_APBAMASK_OSCCTRL_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_OSCCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_OSCCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_OSCCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_OSCCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_OSC32KCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_OSC32KCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_OSC32KCTRL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_OSC32KCTRL) >> MCLK_APBAMASK_OSC32KCTRL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_OSC32KCTRL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_OSC32KCTRL;
+	tmp |= value << MCLK_APBAMASK_OSC32KCTRL_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_OSC32KCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_OSC32KCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_OSC32KCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_OSC32KCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_SUPC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_SUPC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_SUPC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_SUPC) >> MCLK_APBAMASK_SUPC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_SUPC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_SUPC;
+	tmp |= value << MCLK_APBAMASK_SUPC_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_SUPC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_SUPC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_SUPC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_SUPC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_GCLK_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_GCLK;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_GCLK_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_GCLK) >> MCLK_APBAMASK_GCLK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_GCLK_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_GCLK;
+	tmp |= value << MCLK_APBAMASK_GCLK_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_GCLK_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_GCLK;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_GCLK_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_GCLK;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_WDT_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_WDT;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_WDT_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_WDT) >> MCLK_APBAMASK_WDT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_WDT_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_WDT;
+	tmp |= value << MCLK_APBAMASK_WDT_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_WDT_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_WDT;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_WDT_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_WDT;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_RTC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_RTC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_RTC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_RTC) >> MCLK_APBAMASK_RTC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_RTC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_RTC;
+	tmp |= value << MCLK_APBAMASK_RTC_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_RTC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_RTC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_RTC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_RTC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_EIC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_EIC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_EIC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_EIC) >> MCLK_APBAMASK_EIC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_EIC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_EIC;
+	tmp |= value << MCLK_APBAMASK_EIC_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_EIC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_EIC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_EIC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_EIC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_FREQM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_FREQM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBAMASK_FREQM_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp = (tmp & MCLK_APBAMASK_FREQM) >> MCLK_APBAMASK_FREQM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_FREQM_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= ~MCLK_APBAMASK_FREQM;
+	tmp |= value << MCLK_APBAMASK_FREQM_Pos;
+	((Mclk *)hw)->APBAMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_FREQM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_FREQM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_FREQM_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_FREQM;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg |= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_apbamask_reg_t hri_mclk_get_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBAMASK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_mclk_write_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t data)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg = data;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg &= ~mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBAMASK.reg ^= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_apbamask_reg_t hri_mclk_read_APBAMASK_reg(const void *const hw)
+{
+	return ((Mclk *)hw)->APBAMASK.reg;
+}
+
+static inline void hri_mclk_set_APBBMASK_USB_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_USB;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBBMASK_USB_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp = (tmp & MCLK_APBBMASK_USB) >> MCLK_APBBMASK_USB_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBBMASK_USB_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp &= ~MCLK_APBBMASK_USB;
+	tmp |= value << MCLK_APBBMASK_USB_Pos;
+	((Mclk *)hw)->APBBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBBMASK_USB_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_USB;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBBMASK_USB_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_USB;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBBMASK_DSU_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_DSU;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBBMASK_DSU_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp = (tmp & MCLK_APBBMASK_DSU) >> MCLK_APBBMASK_DSU_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBBMASK_DSU_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp &= ~MCLK_APBBMASK_DSU;
+	tmp |= value << MCLK_APBBMASK_DSU_Pos;
+	((Mclk *)hw)->APBBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBBMASK_DSU_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_DSU;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBBMASK_DSU_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_DSU;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBBMASK_NVMCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_NVMCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBBMASK_NVMCTRL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp = (tmp & MCLK_APBBMASK_NVMCTRL) >> MCLK_APBBMASK_NVMCTRL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBBMASK_NVMCTRL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp &= ~MCLK_APBBMASK_NVMCTRL;
+	tmp |= value << MCLK_APBBMASK_NVMCTRL_Pos;
+	((Mclk *)hw)->APBBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBBMASK_NVMCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_NVMCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBBMASK_NVMCTRL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_NVMCTRL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBBMASK_PORT_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_PORT;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBBMASK_PORT_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp = (tmp & MCLK_APBBMASK_PORT) >> MCLK_APBBMASK_PORT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBBMASK_PORT_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp &= ~MCLK_APBBMASK_PORT;
+	tmp |= value << MCLK_APBBMASK_PORT_Pos;
+	((Mclk *)hw)->APBBMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBBMASK_PORT_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_PORT;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBBMASK_PORT_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_PORT;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg |= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_apbbmask_reg_t hri_mclk_get_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBBMASK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_mclk_write_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t data)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg = data;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg &= ~mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBBMASK.reg ^= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_apbbmask_reg_t hri_mclk_read_APBBMASK_reg(const void *const hw)
+{
+	return ((Mclk *)hw)->APBBMASK.reg;
+}
+
+static inline void hri_mclk_set_APBCMASK_EVSYS_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_EVSYS;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_EVSYS_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_EVSYS) >> MCLK_APBCMASK_EVSYS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_EVSYS_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_EVSYS;
+	tmp |= value << MCLK_APBCMASK_EVSYS_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_EVSYS_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_EVSYS;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_EVSYS_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_EVSYS;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_SERCOM0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SERCOM0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_SERCOM0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_SERCOM0) >> MCLK_APBCMASK_SERCOM0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_SERCOM0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_SERCOM0;
+	tmp |= value << MCLK_APBCMASK_SERCOM0_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_SERCOM0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SERCOM0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_SERCOM0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SERCOM0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_SERCOM1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SERCOM1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_SERCOM1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_SERCOM1) >> MCLK_APBCMASK_SERCOM1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_SERCOM1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_SERCOM1;
+	tmp |= value << MCLK_APBCMASK_SERCOM1_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_SERCOM1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SERCOM1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_SERCOM1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SERCOM1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_SERCOM2_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SERCOM2;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_SERCOM2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_SERCOM2) >> MCLK_APBCMASK_SERCOM2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_SERCOM2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_SERCOM2;
+	tmp |= value << MCLK_APBCMASK_SERCOM2_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_SERCOM2_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SERCOM2;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_SERCOM2_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SERCOM2;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_SERCOM3_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SERCOM3;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_SERCOM3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_SERCOM3) >> MCLK_APBCMASK_SERCOM3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_SERCOM3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_SERCOM3;
+	tmp |= value << MCLK_APBCMASK_SERCOM3_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_SERCOM3_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SERCOM3;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_SERCOM3_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SERCOM3;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_SERCOM4_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SERCOM4;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_SERCOM4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_SERCOM4) >> MCLK_APBCMASK_SERCOM4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_SERCOM4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_SERCOM4;
+	tmp |= value << MCLK_APBCMASK_SERCOM4_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_SERCOM4_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SERCOM4;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_SERCOM4_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SERCOM4;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_SERCOM5_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SERCOM5;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_SERCOM5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_SERCOM5) >> MCLK_APBCMASK_SERCOM5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_SERCOM5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_SERCOM5;
+	tmp |= value << MCLK_APBCMASK_SERCOM5_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_SERCOM5_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SERCOM5;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_SERCOM5_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SERCOM5;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_TCC0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TCC0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_TCC0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_TCC0) >> MCLK_APBCMASK_TCC0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_TCC0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_TCC0;
+	tmp |= value << MCLK_APBCMASK_TCC0_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_TCC0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TCC0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_TCC0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TCC0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_TC0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_TC0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_TC0) >> MCLK_APBCMASK_TC0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_TC0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_TC0;
+	tmp |= value << MCLK_APBCMASK_TC0_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_TC0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_TC0_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC0;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_TC1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_TC1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_TC1) >> MCLK_APBCMASK_TC1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_TC1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_TC1;
+	tmp |= value << MCLK_APBCMASK_TC1_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_TC1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_TC1_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC1;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_TC2_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC2;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_TC2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_TC2) >> MCLK_APBCMASK_TC2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_TC2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_TC2;
+	tmp |= value << MCLK_APBCMASK_TC2_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_TC2_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC2;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_TC2_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC2;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_TC3_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC3;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_TC3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_TC3) >> MCLK_APBCMASK_TC3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_TC3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_TC3;
+	tmp |= value << MCLK_APBCMASK_TC3_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_TC3_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC3;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_TC3_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC3;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_ADC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_ADC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_ADC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_ADC) >> MCLK_APBCMASK_ADC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_ADC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_ADC;
+	tmp |= value << MCLK_APBCMASK_ADC_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_ADC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_ADC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_ADC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_ADC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_AC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_AC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_AC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_AC) >> MCLK_APBCMASK_AC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_AC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_AC;
+	tmp |= value << MCLK_APBCMASK_AC_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_AC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_AC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_AC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_AC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_PTC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_PTC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_PTC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_PTC) >> MCLK_APBCMASK_PTC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_PTC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_PTC;
+	tmp |= value << MCLK_APBCMASK_PTC_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_PTC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_PTC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_PTC_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_PTC;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_SLCD_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SLCD;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_SLCD_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_SLCD) >> MCLK_APBCMASK_SLCD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_SLCD_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_SLCD;
+	tmp |= value << MCLK_APBCMASK_SLCD_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_SLCD_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SLCD;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_SLCD_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SLCD;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_AES_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_AES;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_AES_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_AES) >> MCLK_APBCMASK_AES_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_AES_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_AES;
+	tmp |= value << MCLK_APBCMASK_AES_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_AES_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_AES;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_AES_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_AES;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_TRNG_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TRNG;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_TRNG_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_TRNG) >> MCLK_APBCMASK_TRNG_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_TRNG_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_TRNG;
+	tmp |= value << MCLK_APBCMASK_TRNG_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_TRNG_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TRNG;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_TRNG_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TRNG;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_CCL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_CCL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_mclk_get_APBCMASK_CCL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp = (tmp & MCLK_APBCMASK_CCL) >> MCLK_APBCMASK_CCL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_CCL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	MCLK_CRITICAL_SECTION_ENTER();
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= ~MCLK_APBCMASK_CCL;
+	tmp |= value << MCLK_APBCMASK_CCL_Pos;
+	((Mclk *)hw)->APBCMASK.reg = tmp;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_CCL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_CCL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_CCL_bit(const void *const hw)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_CCL;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_set_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg |= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_apbcmask_reg_t hri_mclk_get_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mclk *)hw)->APBCMASK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_mclk_write_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t data)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg = data;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_clear_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg &= ~mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mclk_toggle_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask)
+{
+	MCLK_CRITICAL_SECTION_ENTER();
+	((Mclk *)hw)->APBCMASK.reg ^= mask;
+	MCLK_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mclk_apbcmask_reg_t hri_mclk_read_APBCMASK_reg(const void *const hw)
+{
+	return ((Mclk *)hw)->APBCMASK.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_MCLK_L22_H_INCLUDED */
+#endif /* _SAML22_MCLK_COMPONENT_ */
diff --git a/watch-library/hardware/hri/hri_mtb_l22.h b/watch-library/hardware/hri/hri_mtb_l22.h
new file mode 100644
index 00000000..f8cb66d5
--- /dev/null
+++ b/watch-library/hardware/hri/hri_mtb_l22.h
@@ -0,0 +1,551 @@
+/**
+ * \file
+ *
+ * \brief SAM MTB
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_MTB_COMPONENT_
+#ifndef _HRI_MTB_L22_H_INCLUDED_
+#define _HRI_MTB_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_MTB_CRITICAL_SECTIONS)
+#define MTB_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define MTB_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define MTB_CRITICAL_SECTION_ENTER()
+#define MTB_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_mtb_authstatus_reg_t;
+typedef uint32_t hri_mtb_base_reg_t;
+typedef uint32_t hri_mtb_cid0_reg_t;
+typedef uint32_t hri_mtb_cid1_reg_t;
+typedef uint32_t hri_mtb_cid2_reg_t;
+typedef uint32_t hri_mtb_cid3_reg_t;
+typedef uint32_t hri_mtb_claimset_reg_t;
+typedef uint32_t hri_mtb_devarch_reg_t;
+typedef uint32_t hri_mtb_devid_reg_t;
+typedef uint32_t hri_mtb_devtype_reg_t;
+typedef uint32_t hri_mtb_flow_reg_t;
+typedef uint32_t hri_mtb_itctrl_reg_t;
+typedef uint32_t hri_mtb_lockaccess_reg_t;
+typedef uint32_t hri_mtb_lockstatus_reg_t;
+typedef uint32_t hri_mtb_master_reg_t;
+typedef uint32_t hri_mtb_pid0_reg_t;
+typedef uint32_t hri_mtb_pid1_reg_t;
+typedef uint32_t hri_mtb_pid2_reg_t;
+typedef uint32_t hri_mtb_pid3_reg_t;
+typedef uint32_t hri_mtb_pid4_reg_t;
+typedef uint32_t hri_mtb_pid5_reg_t;
+typedef uint32_t hri_mtb_pid6_reg_t;
+typedef uint32_t hri_mtb_pid7_reg_t;
+typedef uint32_t hri_mtb_position_reg_t;
+
+static inline void hri_mtb_set_CLAIM_reg(const void *const hw, hri_mtb_claimset_reg_t mask)
+{
+	((Mtb *)hw)->CLAIMSET.reg = mask;
+}
+
+static inline hri_mtb_claimset_reg_t hri_mtb_get_CLAIM_reg(const void *const hw, hri_mtb_claimset_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->CLAIMSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_claimset_reg_t hri_mtb_read_CLAIM_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->CLAIMSET.reg;
+}
+
+static inline void hri_mtb_write_CLAIM_reg(const void *const hw, hri_mtb_claimset_reg_t data)
+{
+	((Mtb *)hw)->CLAIMSET.reg = data;
+	((Mtb *)hw)->CLAIMCLR.reg = ~data;
+}
+
+static inline void hri_mtb_clear_CLAIM_reg(const void *const hw, hri_mtb_claimset_reg_t mask)
+{
+	((Mtb *)hw)->CLAIMCLR.reg = mask;
+}
+
+static inline hri_mtb_base_reg_t hri_mtb_get_BASE_reg(const void *const hw, hri_mtb_base_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->BASE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_base_reg_t hri_mtb_read_BASE_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->BASE.reg;
+}
+
+static inline hri_mtb_lockstatus_reg_t hri_mtb_get_LOCKSTATUS_reg(const void *const hw, hri_mtb_lockstatus_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->LOCKSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_lockstatus_reg_t hri_mtb_read_LOCKSTATUS_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->LOCKSTATUS.reg;
+}
+
+static inline hri_mtb_authstatus_reg_t hri_mtb_get_AUTHSTATUS_reg(const void *const hw, hri_mtb_authstatus_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->AUTHSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_authstatus_reg_t hri_mtb_read_AUTHSTATUS_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->AUTHSTATUS.reg;
+}
+
+static inline hri_mtb_devarch_reg_t hri_mtb_get_DEVARCH_reg(const void *const hw, hri_mtb_devarch_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->DEVARCH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_devarch_reg_t hri_mtb_read_DEVARCH_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->DEVARCH.reg;
+}
+
+static inline hri_mtb_devid_reg_t hri_mtb_get_DEVID_reg(const void *const hw, hri_mtb_devid_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->DEVID.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_devid_reg_t hri_mtb_read_DEVID_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->DEVID.reg;
+}
+
+static inline hri_mtb_devtype_reg_t hri_mtb_get_DEVTYPE_reg(const void *const hw, hri_mtb_devtype_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->DEVTYPE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_devtype_reg_t hri_mtb_read_DEVTYPE_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->DEVTYPE.reg;
+}
+
+static inline hri_mtb_pid4_reg_t hri_mtb_get_PID4_reg(const void *const hw, hri_mtb_pid4_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->PID4.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_pid4_reg_t hri_mtb_read_PID4_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->PID4.reg;
+}
+
+static inline hri_mtb_pid5_reg_t hri_mtb_get_PID5_reg(const void *const hw, hri_mtb_pid5_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->PID5.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_pid5_reg_t hri_mtb_read_PID5_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->PID5.reg;
+}
+
+static inline hri_mtb_pid6_reg_t hri_mtb_get_PID6_reg(const void *const hw, hri_mtb_pid6_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->PID6.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_pid6_reg_t hri_mtb_read_PID6_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->PID6.reg;
+}
+
+static inline hri_mtb_pid7_reg_t hri_mtb_get_PID7_reg(const void *const hw, hri_mtb_pid7_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->PID7.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_pid7_reg_t hri_mtb_read_PID7_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->PID7.reg;
+}
+
+static inline hri_mtb_pid0_reg_t hri_mtb_get_PID0_reg(const void *const hw, hri_mtb_pid0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->PID0.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_pid0_reg_t hri_mtb_read_PID0_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->PID0.reg;
+}
+
+static inline hri_mtb_pid1_reg_t hri_mtb_get_PID1_reg(const void *const hw, hri_mtb_pid1_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->PID1.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_pid1_reg_t hri_mtb_read_PID1_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->PID1.reg;
+}
+
+static inline hri_mtb_pid2_reg_t hri_mtb_get_PID2_reg(const void *const hw, hri_mtb_pid2_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->PID2.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_pid2_reg_t hri_mtb_read_PID2_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->PID2.reg;
+}
+
+static inline hri_mtb_pid3_reg_t hri_mtb_get_PID3_reg(const void *const hw, hri_mtb_pid3_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->PID3.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_pid3_reg_t hri_mtb_read_PID3_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->PID3.reg;
+}
+
+static inline hri_mtb_cid0_reg_t hri_mtb_get_CID0_reg(const void *const hw, hri_mtb_cid0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->CID0.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_cid0_reg_t hri_mtb_read_CID0_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->CID0.reg;
+}
+
+static inline hri_mtb_cid1_reg_t hri_mtb_get_CID1_reg(const void *const hw, hri_mtb_cid1_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->CID1.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_cid1_reg_t hri_mtb_read_CID1_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->CID1.reg;
+}
+
+static inline hri_mtb_cid2_reg_t hri_mtb_get_CID2_reg(const void *const hw, hri_mtb_cid2_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->CID2.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_cid2_reg_t hri_mtb_read_CID2_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->CID2.reg;
+}
+
+static inline hri_mtb_cid3_reg_t hri_mtb_get_CID3_reg(const void *const hw, hri_mtb_cid3_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->CID3.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_mtb_cid3_reg_t hri_mtb_read_CID3_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->CID3.reg;
+}
+
+static inline void hri_mtb_set_POSITION_reg(const void *const hw, hri_mtb_position_reg_t mask)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->POSITION.reg |= mask;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mtb_position_reg_t hri_mtb_get_POSITION_reg(const void *const hw, hri_mtb_position_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->POSITION.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_mtb_write_POSITION_reg(const void *const hw, hri_mtb_position_reg_t data)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->POSITION.reg = data;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mtb_clear_POSITION_reg(const void *const hw, hri_mtb_position_reg_t mask)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->POSITION.reg &= ~mask;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mtb_toggle_POSITION_reg(const void *const hw, hri_mtb_position_reg_t mask)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->POSITION.reg ^= mask;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mtb_position_reg_t hri_mtb_read_POSITION_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->POSITION.reg;
+}
+
+static inline void hri_mtb_set_MASTER_reg(const void *const hw, hri_mtb_master_reg_t mask)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->MASTER.reg |= mask;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mtb_master_reg_t hri_mtb_get_MASTER_reg(const void *const hw, hri_mtb_master_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->MASTER.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_mtb_write_MASTER_reg(const void *const hw, hri_mtb_master_reg_t data)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->MASTER.reg = data;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mtb_clear_MASTER_reg(const void *const hw, hri_mtb_master_reg_t mask)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->MASTER.reg &= ~mask;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mtb_toggle_MASTER_reg(const void *const hw, hri_mtb_master_reg_t mask)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->MASTER.reg ^= mask;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mtb_master_reg_t hri_mtb_read_MASTER_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->MASTER.reg;
+}
+
+static inline void hri_mtb_set_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t mask)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->FLOW.reg |= mask;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mtb_flow_reg_t hri_mtb_get_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->FLOW.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_mtb_write_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t data)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->FLOW.reg = data;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mtb_clear_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t mask)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->FLOW.reg &= ~mask;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mtb_toggle_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t mask)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->FLOW.reg ^= mask;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mtb_flow_reg_t hri_mtb_read_FLOW_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->FLOW.reg;
+}
+
+static inline void hri_mtb_set_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t mask)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->ITCTRL.reg |= mask;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mtb_itctrl_reg_t hri_mtb_get_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->ITCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_mtb_write_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t data)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->ITCTRL.reg = data;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mtb_clear_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t mask)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->ITCTRL.reg &= ~mask;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mtb_toggle_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t mask)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->ITCTRL.reg ^= mask;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mtb_itctrl_reg_t hri_mtb_read_ITCTRL_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->ITCTRL.reg;
+}
+
+static inline void hri_mtb_set_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t mask)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->LOCKACCESS.reg |= mask;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mtb_lockaccess_reg_t hri_mtb_get_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Mtb *)hw)->LOCKACCESS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_mtb_write_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t data)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->LOCKACCESS.reg = data;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mtb_clear_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t mask)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->LOCKACCESS.reg &= ~mask;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_mtb_toggle_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t mask)
+{
+	MTB_CRITICAL_SECTION_ENTER();
+	((Mtb *)hw)->LOCKACCESS.reg ^= mask;
+	MTB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_mtb_lockaccess_reg_t hri_mtb_read_LOCKACCESS_reg(const void *const hw)
+{
+	return ((Mtb *)hw)->LOCKACCESS.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_MTB_L22_H_INCLUDED */
+#endif /* _SAML22_MTB_COMPONENT_ */
diff --git a/watch-library/hardware/hri/hri_nvic_l22.h b/watch-library/hardware/hri/hri_nvic_l22.h
new file mode 100644
index 00000000..5596c99a
--- /dev/null
+++ b/watch-library/hardware/hri/hri_nvic_l22.h
@@ -0,0 +1,269 @@
+/**
+ * \file
+ *
+ * \brief SAM NVIC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_NVIC_COMPONENT_
+#ifndef _HRI_NVIC_L22_H_INCLUDED_
+#define _HRI_NVIC_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_NVIC_CRITICAL_SECTIONS)
+#define NVIC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define NVIC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define NVIC_CRITICAL_SECTION_ENTER()
+#define NVIC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_nvic_icer_reg_t;
+typedef uint32_t hri_nvic_icpr_reg_t;
+typedef uint32_t hri_nvic_ipr_reg_t;
+typedef uint32_t hri_nvic_iser_reg_t;
+typedef uint32_t hri_nvic_ispr_reg_t;
+
+static inline void hri_nvic_set_ISER_reg(const void *const hw, hri_nvic_iser_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->ISER.reg |= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_iser_reg_t hri_nvic_get_ISER_reg(const void *const hw, hri_nvic_iser_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->ISER.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvic_write_ISER_reg(const void *const hw, hri_nvic_iser_reg_t data)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->ISER.reg = data;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_ISER_reg(const void *const hw, hri_nvic_iser_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->ISER.reg &= ~mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_ISER_reg(const void *const hw, hri_nvic_iser_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->ISER.reg ^= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_iser_reg_t hri_nvic_read_ISER_reg(const void *const hw)
+{
+	return ((Nvic *)hw)->ISER.reg;
+}
+
+static inline void hri_nvic_set_ICER_reg(const void *const hw, hri_nvic_icer_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->ICER.reg |= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_icer_reg_t hri_nvic_get_ICER_reg(const void *const hw, hri_nvic_icer_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->ICER.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvic_write_ICER_reg(const void *const hw, hri_nvic_icer_reg_t data)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->ICER.reg = data;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_ICER_reg(const void *const hw, hri_nvic_icer_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->ICER.reg &= ~mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_ICER_reg(const void *const hw, hri_nvic_icer_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->ICER.reg ^= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_icer_reg_t hri_nvic_read_ICER_reg(const void *const hw)
+{
+	return ((Nvic *)hw)->ICER.reg;
+}
+
+static inline void hri_nvic_set_ISPR_reg(const void *const hw, hri_nvic_ispr_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->ISPR.reg |= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_ispr_reg_t hri_nvic_get_ISPR_reg(const void *const hw, hri_nvic_ispr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->ISPR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvic_write_ISPR_reg(const void *const hw, hri_nvic_ispr_reg_t data)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->ISPR.reg = data;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_ISPR_reg(const void *const hw, hri_nvic_ispr_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->ISPR.reg &= ~mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_ISPR_reg(const void *const hw, hri_nvic_ispr_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->ISPR.reg ^= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_ispr_reg_t hri_nvic_read_ISPR_reg(const void *const hw)
+{
+	return ((Nvic *)hw)->ISPR.reg;
+}
+
+static inline void hri_nvic_set_ICPR_reg(const void *const hw, hri_nvic_icpr_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->ICPR.reg |= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_icpr_reg_t hri_nvic_get_ICPR_reg(const void *const hw, hri_nvic_icpr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->ICPR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvic_write_ICPR_reg(const void *const hw, hri_nvic_icpr_reg_t data)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->ICPR.reg = data;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_ICPR_reg(const void *const hw, hri_nvic_icpr_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->ICPR.reg &= ~mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_ICPR_reg(const void *const hw, hri_nvic_icpr_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->ICPR.reg ^= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_icpr_reg_t hri_nvic_read_ICPR_reg(const void *const hw)
+{
+	return ((Nvic *)hw)->ICPR.reg;
+}
+
+static inline void hri_nvic_set_IPR_reg(const void *const hw, uint8_t index, hri_nvic_ipr_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->IPR[index].reg |= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_ipr_reg_t hri_nvic_get_IPR_reg(const void *const hw, uint8_t index, hri_nvic_ipr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvic *)hw)->IPR[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvic_write_IPR_reg(const void *const hw, uint8_t index, hri_nvic_ipr_reg_t data)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->IPR[index].reg = data;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_clear_IPR_reg(const void *const hw, uint8_t index, hri_nvic_ipr_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->IPR[index].reg &= ~mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvic_toggle_IPR_reg(const void *const hw, uint8_t index, hri_nvic_ipr_reg_t mask)
+{
+	NVIC_CRITICAL_SECTION_ENTER();
+	((Nvic *)hw)->IPR[index].reg ^= mask;
+	NVIC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvic_ipr_reg_t hri_nvic_read_IPR_reg(const void *const hw, uint8_t index)
+{
+	return ((Nvic *)hw)->IPR[index].reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_NVIC_L22_H_INCLUDED */
+#endif /* _SAML22_NVIC_COMPONENT_ */
diff --git a/watch-library/hardware/hri/hri_nvmctrl_l22.h b/watch-library/hardware/hri/hri_nvmctrl_l22.h
new file mode 100644
index 00000000..07629fba
--- /dev/null
+++ b/watch-library/hardware/hri/hri_nvmctrl_l22.h
@@ -0,0 +1,1104 @@
+/**
+ * \file
+ *
+ * \brief SAM NVMCTRL
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_NVMCTRL_COMPONENT_
+#ifndef _HRI_NVMCTRL_L22_H_INCLUDED_
+#define _HRI_NVMCTRL_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_NVMCTRL_CRITICAL_SECTIONS)
+#define NVMCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define NVMCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define NVMCTRL_CRITICAL_SECTION_ENTER()
+#define NVMCTRL_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_nvmctrl_ctrla_reg_t;
+typedef uint16_t hri_nvmctrl_lock_reg_t;
+typedef uint16_t hri_nvmctrl_status_reg_t;
+typedef uint32_t hri_nvmctrl_addr_reg_t;
+typedef uint32_t hri_nvmctrl_ctrlb_reg_t;
+typedef uint32_t hri_nvmctrl_param_reg_t;
+typedef uint8_t  hri_nvmctrl_intenset_reg_t;
+typedef uint8_t  hri_nvmctrl_intflag_reg_t;
+
+static inline bool hri_nvmctrl_get_INTFLAG_READY_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_READY) >> NVMCTRL_INTFLAG_READY_Pos;
+}
+
+static inline void hri_nvmctrl_clear_INTFLAG_READY_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_READY;
+}
+
+static inline bool hri_nvmctrl_get_INTFLAG_ERROR_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ERROR) >> NVMCTRL_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_nvmctrl_clear_INTFLAG_ERROR_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ERROR;
+}
+
+static inline bool hri_nvmctrl_get_interrupt_READY_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_READY) >> NVMCTRL_INTFLAG_READY_Pos;
+}
+
+static inline void hri_nvmctrl_clear_interrupt_READY_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_READY;
+}
+
+static inline bool hri_nvmctrl_get_interrupt_ERROR_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ERROR) >> NVMCTRL_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_nvmctrl_clear_interrupt_ERROR_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ERROR;
+}
+
+static inline hri_nvmctrl_intflag_reg_t hri_nvmctrl_get_INTFLAG_reg(const void *const         hw,
+                                                                    hri_nvmctrl_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Nvmctrl *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_nvmctrl_intflag_reg_t hri_nvmctrl_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_nvmctrl_clear_INTFLAG_reg(const void *const hw, hri_nvmctrl_intflag_reg_t mask)
+{
+	((Nvmctrl *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_nvmctrl_set_INTEN_READY_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_READY;
+}
+
+static inline bool hri_nvmctrl_get_INTEN_READY_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_READY) >> NVMCTRL_INTENSET_READY_Pos;
+}
+
+static inline void hri_nvmctrl_write_INTEN_READY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_READY;
+	} else {
+		((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_READY;
+	}
+}
+
+static inline void hri_nvmctrl_clear_INTEN_READY_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_READY;
+}
+
+static inline void hri_nvmctrl_set_INTEN_ERROR_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ERROR;
+}
+
+static inline bool hri_nvmctrl_get_INTEN_ERROR_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_ERROR) >> NVMCTRL_INTENSET_ERROR_Pos;
+}
+
+static inline void hri_nvmctrl_write_INTEN_ERROR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ERROR;
+	} else {
+		((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ERROR;
+	}
+}
+
+static inline void hri_nvmctrl_clear_INTEN_ERROR_bit(const void *const hw)
+{
+	((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ERROR;
+}
+
+static inline void hri_nvmctrl_set_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t mask)
+{
+	((Nvmctrl *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_nvmctrl_intenset_reg_t hri_nvmctrl_get_INTEN_reg(const void *const          hw,
+                                                                   hri_nvmctrl_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Nvmctrl *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_nvmctrl_intenset_reg_t hri_nvmctrl_read_INTEN_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->INTENSET.reg;
+}
+
+static inline void hri_nvmctrl_write_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t data)
+{
+	((Nvmctrl *)hw)->INTENSET.reg = data;
+	((Nvmctrl *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_nvmctrl_clear_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t mask)
+{
+	((Nvmctrl *)hw)->INTENCLR.reg = mask;
+}
+
+static inline void hri_nvmctrl_set_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_CMD(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp = (tmp & NVMCTRL_CTRLA_CMD(mask)) >> NVMCTRL_CTRLA_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data)
+{
+	uint16_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp &= ~NVMCTRL_CTRLA_CMD_Msk;
+	tmp |= NVMCTRL_CTRLA_CMD(data);
+	((Nvmctrl *)hw)->CTRLA.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_CMD(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_CMD(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_CMD_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp = (tmp & NVMCTRL_CTRLA_CMD_Msk) >> NVMCTRL_CTRLA_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_set_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_CMDEX(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp = (tmp & NVMCTRL_CTRLA_CMDEX(mask)) >> NVMCTRL_CTRLA_CMDEX_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data)
+{
+	uint16_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp &= ~NVMCTRL_CTRLA_CMDEX_Msk;
+	tmp |= NVMCTRL_CTRLA_CMDEX(data);
+	((Nvmctrl *)hw)->CTRLA.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_CMDEX(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_CMDEX(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_CMDEX_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp = (tmp & NVMCTRL_CTRLA_CMDEX_Msk) >> NVMCTRL_CTRLA_CMDEX_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_set_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg |= mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t data)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg = data;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg &= ~mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLA.reg ^= mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->CTRLA.reg;
+}
+
+static inline void hri_nvmctrl_set_CTRLB_MANW_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_MANW;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_nvmctrl_get_CTRLB_MANW_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLB.reg;
+	tmp = (tmp & NVMCTRL_CTRLB_MANW) >> NVMCTRL_CTRLB_MANW_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLB_MANW_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->CTRLB.reg;
+	tmp &= ~NVMCTRL_CTRLB_MANW;
+	tmp |= value << NVMCTRL_CTRLB_MANW_Pos;
+	((Nvmctrl *)hw)->CTRLB.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLB_MANW_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_MANW;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLB_MANW_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_MANW;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_set_CTRLB_FWUP_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_FWUP;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_nvmctrl_get_CTRLB_FWUP_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLB.reg;
+	tmp = (tmp & NVMCTRL_CTRLB_FWUP) >> NVMCTRL_CTRLB_FWUP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLB_FWUP_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->CTRLB.reg;
+	tmp &= ~NVMCTRL_CTRLB_FWUP;
+	tmp |= value << NVMCTRL_CTRLB_FWUP_Pos;
+	((Nvmctrl *)hw)->CTRLB.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLB_FWUP_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_FWUP;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLB_FWUP_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_FWUP;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_set_CTRLB_CACHEDIS_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_CACHEDIS;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_nvmctrl_get_CTRLB_CACHEDIS_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLB.reg;
+	tmp = (tmp & NVMCTRL_CTRLB_CACHEDIS) >> NVMCTRL_CTRLB_CACHEDIS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLB_CACHEDIS_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->CTRLB.reg;
+	tmp &= ~NVMCTRL_CTRLB_CACHEDIS;
+	tmp |= value << NVMCTRL_CTRLB_CACHEDIS_Pos;
+	((Nvmctrl *)hw)->CTRLB.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLB_CACHEDIS_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_CACHEDIS;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLB_CACHEDIS_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_CACHEDIS;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_set_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_RWS(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_get_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLB.reg;
+	tmp = (tmp & NVMCTRL_CTRLB_RWS(mask)) >> NVMCTRL_CTRLB_RWS_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->CTRLB.reg;
+	tmp &= ~NVMCTRL_CTRLB_RWS_Msk;
+	tmp |= NVMCTRL_CTRLB_RWS(data);
+	((Nvmctrl *)hw)->CTRLB.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_RWS(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_RWS(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_read_CTRLB_RWS_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLB.reg;
+	tmp = (tmp & NVMCTRL_CTRLB_RWS_Msk) >> NVMCTRL_CTRLB_RWS_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_set_CTRLB_SLEEPPRM_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_SLEEPPRM(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_get_CTRLB_SLEEPPRM_bf(const void *const       hw,
+                                                                        hri_nvmctrl_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLB.reg;
+	tmp = (tmp & NVMCTRL_CTRLB_SLEEPPRM(mask)) >> NVMCTRL_CTRLB_SLEEPPRM_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLB_SLEEPPRM_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->CTRLB.reg;
+	tmp &= ~NVMCTRL_CTRLB_SLEEPPRM_Msk;
+	tmp |= NVMCTRL_CTRLB_SLEEPPRM(data);
+	((Nvmctrl *)hw)->CTRLB.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLB_SLEEPPRM_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_SLEEPPRM(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLB_SLEEPPRM_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_SLEEPPRM(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_read_CTRLB_SLEEPPRM_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLB.reg;
+	tmp = (tmp & NVMCTRL_CTRLB_SLEEPPRM_Msk) >> NVMCTRL_CTRLB_SLEEPPRM_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_set_CTRLB_READMODE_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_READMODE(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_get_CTRLB_READMODE_bf(const void *const       hw,
+                                                                        hri_nvmctrl_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLB.reg;
+	tmp = (tmp & NVMCTRL_CTRLB_READMODE(mask)) >> NVMCTRL_CTRLB_READMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLB_READMODE_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->CTRLB.reg;
+	tmp &= ~NVMCTRL_CTRLB_READMODE_Msk;
+	tmp |= NVMCTRL_CTRLB_READMODE(data);
+	((Nvmctrl *)hw)->CTRLB.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLB_READMODE_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_READMODE(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLB_READMODE_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_READMODE(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_read_CTRLB_READMODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLB.reg;
+	tmp = (tmp & NVMCTRL_CTRLB_READMODE_Msk) >> NVMCTRL_CTRLB_READMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_set_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg |= mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_get_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t data)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg = data;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg &= ~mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->CTRLB.reg ^= mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_read_CTRLB_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->CTRLB.reg;
+}
+
+static inline void hri_nvmctrl_set_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->PARAM.reg |= NVMCTRL_PARAM_NVMP(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->PARAM.reg;
+	tmp = (tmp & NVMCTRL_PARAM_NVMP(mask)) >> NVMCTRL_PARAM_NVMP_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t data)
+{
+	uint32_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->PARAM.reg;
+	tmp &= ~NVMCTRL_PARAM_NVMP_Msk;
+	tmp |= NVMCTRL_PARAM_NVMP(data);
+	((Nvmctrl *)hw)->PARAM.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->PARAM.reg &= ~NVMCTRL_PARAM_NVMP(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->PARAM.reg ^= NVMCTRL_PARAM_NVMP(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_NVMP_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->PARAM.reg;
+	tmp = (tmp & NVMCTRL_PARAM_NVMP_Msk) >> NVMCTRL_PARAM_NVMP_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_set_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->PARAM.reg |= NVMCTRL_PARAM_PSZ(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->PARAM.reg;
+	tmp = (tmp & NVMCTRL_PARAM_PSZ(mask)) >> NVMCTRL_PARAM_PSZ_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t data)
+{
+	uint32_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->PARAM.reg;
+	tmp &= ~NVMCTRL_PARAM_PSZ_Msk;
+	tmp |= NVMCTRL_PARAM_PSZ(data);
+	((Nvmctrl *)hw)->PARAM.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->PARAM.reg &= ~NVMCTRL_PARAM_PSZ(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->PARAM.reg ^= NVMCTRL_PARAM_PSZ(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_PSZ_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->PARAM.reg;
+	tmp = (tmp & NVMCTRL_PARAM_PSZ_Msk) >> NVMCTRL_PARAM_PSZ_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_set_PARAM_RWWEEP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->PARAM.reg |= NVMCTRL_PARAM_RWWEEP(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_RWWEEP_bf(const void *const       hw,
+                                                                      hri_nvmctrl_param_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->PARAM.reg;
+	tmp = (tmp & NVMCTRL_PARAM_RWWEEP(mask)) >> NVMCTRL_PARAM_RWWEEP_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_PARAM_RWWEEP_bf(const void *const hw, hri_nvmctrl_param_reg_t data)
+{
+	uint32_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->PARAM.reg;
+	tmp &= ~NVMCTRL_PARAM_RWWEEP_Msk;
+	tmp |= NVMCTRL_PARAM_RWWEEP(data);
+	((Nvmctrl *)hw)->PARAM.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_PARAM_RWWEEP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->PARAM.reg &= ~NVMCTRL_PARAM_RWWEEP(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_PARAM_RWWEEP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->PARAM.reg ^= NVMCTRL_PARAM_RWWEEP(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_RWWEEP_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->PARAM.reg;
+	tmp = (tmp & NVMCTRL_PARAM_RWWEEP_Msk) >> NVMCTRL_PARAM_RWWEEP_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_set_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->PARAM.reg |= mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->PARAM.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t data)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->PARAM.reg = data;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->PARAM.reg &= ~mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->PARAM.reg ^= mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->PARAM.reg;
+}
+
+static inline void hri_nvmctrl_set_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->ADDR.reg |= NVMCTRL_ADDR_ADDR(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_get_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->ADDR.reg;
+	tmp = (tmp & NVMCTRL_ADDR_ADDR(mask)) >> NVMCTRL_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t data)
+{
+	uint32_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->ADDR.reg;
+	tmp &= ~NVMCTRL_ADDR_ADDR_Msk;
+	tmp |= NVMCTRL_ADDR_ADDR(data);
+	((Nvmctrl *)hw)->ADDR.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->ADDR.reg &= ~NVMCTRL_ADDR_ADDR(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->ADDR.reg ^= NVMCTRL_ADDR_ADDR(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_read_ADDR_ADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->ADDR.reg;
+	tmp = (tmp & NVMCTRL_ADDR_ADDR_Msk) >> NVMCTRL_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_set_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->ADDR.reg |= mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_get_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Nvmctrl *)hw)->ADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t data)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->ADDR.reg = data;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->ADDR.reg &= ~mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->ADDR.reg ^= mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_read_ADDR_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->ADDR.reg;
+}
+
+static inline void hri_nvmctrl_set_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->LOCK.reg |= NVMCTRL_LOCK_LOCK(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_lock_reg_t hri_nvmctrl_get_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->LOCK.reg;
+	tmp = (tmp & NVMCTRL_LOCK_LOCK(mask)) >> NVMCTRL_LOCK_LOCK_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t data)
+{
+	uint16_t tmp;
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Nvmctrl *)hw)->LOCK.reg;
+	tmp &= ~NVMCTRL_LOCK_LOCK_Msk;
+	tmp |= NVMCTRL_LOCK_LOCK(data);
+	((Nvmctrl *)hw)->LOCK.reg = tmp;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->LOCK.reg &= ~NVMCTRL_LOCK_LOCK(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->LOCK.reg ^= NVMCTRL_LOCK_LOCK(mask);
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_lock_reg_t hri_nvmctrl_read_LOCK_LOCK_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->LOCK.reg;
+	tmp = (tmp & NVMCTRL_LOCK_LOCK_Msk) >> NVMCTRL_LOCK_LOCK_Pos;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_set_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->LOCK.reg |= mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_lock_reg_t hri_nvmctrl_get_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->LOCK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_write_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t data)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->LOCK.reg = data;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_clear_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->LOCK.reg &= ~mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_nvmctrl_toggle_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->LOCK.reg ^= mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_lock_reg_t hri_nvmctrl_read_LOCK_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->LOCK.reg;
+}
+
+static inline bool hri_nvmctrl_get_STATUS_PRM_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_PRM) >> NVMCTRL_STATUS_PRM_Pos;
+}
+
+static inline void hri_nvmctrl_clear_STATUS_PRM_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_PRM;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_nvmctrl_get_STATUS_LOAD_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_LOAD) >> NVMCTRL_STATUS_LOAD_Pos;
+}
+
+static inline void hri_nvmctrl_clear_STATUS_LOAD_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_LOAD;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_nvmctrl_get_STATUS_PROGE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_PROGE) >> NVMCTRL_STATUS_PROGE_Pos;
+}
+
+static inline void hri_nvmctrl_clear_STATUS_PROGE_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_PROGE;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_nvmctrl_get_STATUS_LOCKE_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_LOCKE) >> NVMCTRL_STATUS_LOCKE_Pos;
+}
+
+static inline void hri_nvmctrl_clear_STATUS_LOCKE_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_LOCKE;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_nvmctrl_get_STATUS_NVME_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_NVME) >> NVMCTRL_STATUS_NVME_Pos;
+}
+
+static inline void hri_nvmctrl_clear_STATUS_NVME_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_NVME;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_nvmctrl_get_STATUS_SB_bit(const void *const hw)
+{
+	return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_SB) >> NVMCTRL_STATUS_SB_Pos;
+}
+
+static inline void hri_nvmctrl_clear_STATUS_SB_bit(const void *const hw)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_SB;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_status_reg_t hri_nvmctrl_get_STATUS_reg(const void *const hw, hri_nvmctrl_status_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Nvmctrl *)hw)->STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_nvmctrl_clear_STATUS_reg(const void *const hw, hri_nvmctrl_status_reg_t mask)
+{
+	NVMCTRL_CRITICAL_SECTION_ENTER();
+	((Nvmctrl *)hw)->STATUS.reg = mask;
+	NVMCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_nvmctrl_status_reg_t hri_nvmctrl_read_STATUS_reg(const void *const hw)
+{
+	return ((Nvmctrl *)hw)->STATUS.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_NVMCTRL_L22_H_INCLUDED */
+#endif /* _SAML22_NVMCTRL_COMPONENT_ */
diff --git a/watch-library/hardware/hri/hri_osc32kctrl_l22.h b/watch-library/hardware/hri/hri_osc32kctrl_l22.h
new file mode 100644
index 00000000..44bb32ba
--- /dev/null
+++ b/watch-library/hardware/hri/hri_osc32kctrl_l22.h
@@ -0,0 +1,1233 @@
+/**
+ * \file
+ *
+ * \brief SAM OSC32KCTRL
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_OSC32KCTRL_COMPONENT_
+#ifndef _HRI_OSC32KCTRL_L22_H_INCLUDED_
+#define _HRI_OSC32KCTRL_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_OSC32KCTRL_CRITICAL_SECTIONS)
+#define OSC32KCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define OSC32KCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define OSC32KCTRL_CRITICAL_SECTION_ENTER()
+#define OSC32KCTRL_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_osc32kctrl_xosc32k_reg_t;
+typedef uint32_t hri_osc32kctrl_intenset_reg_t;
+typedef uint32_t hri_osc32kctrl_intflag_reg_t;
+typedef uint32_t hri_osc32kctrl_osculp32k_reg_t;
+typedef uint32_t hri_osc32kctrl_status_reg_t;
+typedef uint8_t  hri_osc32kctrl_cfdctrl_reg_t;
+typedef uint8_t  hri_osc32kctrl_evctrl_reg_t;
+typedef uint8_t  hri_osc32kctrl_rtcctrl_reg_t;
+typedef uint8_t  hri_osc32kctrl_slcdctrl_reg_t;
+
+static inline bool hri_osc32kctrl_get_INTFLAG_XOSC32KRDY_bit(const void *const hw)
+{
+	return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KRDY) >> OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos;
+}
+
+static inline void hri_osc32kctrl_clear_INTFLAG_XOSC32KRDY_bit(const void *const hw)
+{
+	((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KRDY;
+}
+
+static inline bool hri_osc32kctrl_get_INTFLAG_CLKFAIL_bit(const void *const hw)
+{
+	return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_CLKFAIL) >> OSC32KCTRL_INTFLAG_CLKFAIL_Pos;
+}
+
+static inline void hri_osc32kctrl_clear_INTFLAG_CLKFAIL_bit(const void *const hw)
+{
+	((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_CLKFAIL;
+}
+
+static inline bool hri_osc32kctrl_get_interrupt_XOSC32KRDY_bit(const void *const hw)
+{
+	return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KRDY) >> OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos;
+}
+
+static inline void hri_osc32kctrl_clear_interrupt_XOSC32KRDY_bit(const void *const hw)
+{
+	((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KRDY;
+}
+
+static inline bool hri_osc32kctrl_get_interrupt_CLKFAIL_bit(const void *const hw)
+{
+	return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_CLKFAIL) >> OSC32KCTRL_INTFLAG_CLKFAIL_Pos;
+}
+
+static inline void hri_osc32kctrl_clear_interrupt_CLKFAIL_bit(const void *const hw)
+{
+	((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_CLKFAIL;
+}
+
+static inline hri_osc32kctrl_intflag_reg_t hri_osc32kctrl_get_INTFLAG_reg(const void *const            hw,
+                                                                          hri_osc32kctrl_intflag_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Osc32kctrl *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_osc32kctrl_intflag_reg_t hri_osc32kctrl_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Osc32kctrl *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_osc32kctrl_clear_INTFLAG_reg(const void *const hw, hri_osc32kctrl_intflag_reg_t mask)
+{
+	((Osc32kctrl *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_osc32kctrl_set_INTEN_XOSC32KRDY_bit(const void *const hw)
+{
+	((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KRDY;
+}
+
+static inline bool hri_osc32kctrl_get_INTEN_XOSC32KRDY_bit(const void *const hw)
+{
+	return (((Osc32kctrl *)hw)->INTENSET.reg & OSC32KCTRL_INTENSET_XOSC32KRDY) >> OSC32KCTRL_INTENSET_XOSC32KRDY_Pos;
+}
+
+static inline void hri_osc32kctrl_write_INTEN_XOSC32KRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KRDY;
+	} else {
+		((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KRDY;
+	}
+}
+
+static inline void hri_osc32kctrl_clear_INTEN_XOSC32KRDY_bit(const void *const hw)
+{
+	((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KRDY;
+}
+
+static inline void hri_osc32kctrl_set_INTEN_CLKFAIL_bit(const void *const hw)
+{
+	((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_CLKFAIL;
+}
+
+static inline bool hri_osc32kctrl_get_INTEN_CLKFAIL_bit(const void *const hw)
+{
+	return (((Osc32kctrl *)hw)->INTENSET.reg & OSC32KCTRL_INTENSET_CLKFAIL) >> OSC32KCTRL_INTENSET_CLKFAIL_Pos;
+}
+
+static inline void hri_osc32kctrl_write_INTEN_CLKFAIL_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_CLKFAIL;
+	} else {
+		((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_CLKFAIL;
+	}
+}
+
+static inline void hri_osc32kctrl_clear_INTEN_CLKFAIL_bit(const void *const hw)
+{
+	((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_CLKFAIL;
+}
+
+static inline void hri_osc32kctrl_set_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t mask)
+{
+	((Osc32kctrl *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_osc32kctrl_intenset_reg_t hri_osc32kctrl_get_INTEN_reg(const void *const             hw,
+                                                                         hri_osc32kctrl_intenset_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Osc32kctrl *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_osc32kctrl_intenset_reg_t hri_osc32kctrl_read_INTEN_reg(const void *const hw)
+{
+	return ((Osc32kctrl *)hw)->INTENSET.reg;
+}
+
+static inline void hri_osc32kctrl_write_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t data)
+{
+	((Osc32kctrl *)hw)->INTENSET.reg = data;
+	((Osc32kctrl *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_osc32kctrl_clear_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t mask)
+{
+	((Osc32kctrl *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_osc32kctrl_get_STATUS_XOSC32KRDY_bit(const void *const hw)
+{
+	return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_XOSC32KRDY) >> OSC32KCTRL_STATUS_XOSC32KRDY_Pos;
+}
+
+static inline bool hri_osc32kctrl_get_STATUS_CLKFAIL_bit(const void *const hw)
+{
+	return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_CLKFAIL) >> OSC32KCTRL_STATUS_CLKFAIL_Pos;
+}
+
+static inline bool hri_osc32kctrl_get_STATUS_CLKSW_bit(const void *const hw)
+{
+	return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_CLKSW) >> OSC32KCTRL_STATUS_CLKSW_Pos;
+}
+
+static inline hri_osc32kctrl_status_reg_t hri_osc32kctrl_get_STATUS_reg(const void *const           hw,
+                                                                        hri_osc32kctrl_status_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Osc32kctrl *)hw)->STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_osc32kctrl_status_reg_t hri_osc32kctrl_read_STATUS_reg(const void *const hw)
+{
+	return ((Osc32kctrl *)hw)->STATUS.reg;
+}
+
+static inline void hri_osc32kctrl_set_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->RTCCTRL.reg |= OSC32KCTRL_RTCCTRL_RTCSEL(mask);
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_get_RTCCTRL_RTCSEL_bf(const void *const            hw,
+                                                                                hri_osc32kctrl_rtcctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg;
+	tmp = (tmp & OSC32KCTRL_RTCCTRL_RTCSEL(mask)) >> OSC32KCTRL_RTCCTRL_RTCSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_write_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t data)
+{
+	uint8_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg;
+	tmp &= ~OSC32KCTRL_RTCCTRL_RTCSEL_Msk;
+	tmp |= OSC32KCTRL_RTCCTRL_RTCSEL(data);
+	((Osc32kctrl *)hw)->RTCCTRL.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->RTCCTRL.reg &= ~OSC32KCTRL_RTCCTRL_RTCSEL(mask);
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->RTCCTRL.reg ^= OSC32KCTRL_RTCCTRL_RTCSEL(mask);
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_read_RTCCTRL_RTCSEL_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg;
+	tmp = (tmp & OSC32KCTRL_RTCCTRL_RTCSEL_Msk) >> OSC32KCTRL_RTCCTRL_RTCSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_set_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->RTCCTRL.reg |= mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_get_RTCCTRL_reg(const void *const            hw,
+                                                                          hri_osc32kctrl_rtcctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_write_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t data)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->RTCCTRL.reg = data;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->RTCCTRL.reg &= ~mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->RTCCTRL.reg ^= mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_read_RTCCTRL_reg(const void *const hw)
+{
+	return ((Osc32kctrl *)hw)->RTCCTRL.reg;
+}
+
+static inline void hri_osc32kctrl_set_SLCDCTRL_SLCDSEL_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->SLCDCTRL.reg |= OSC32KCTRL_SLCDCTRL_SLCDSEL;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_SLCDCTRL_SLCDSEL_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Osc32kctrl *)hw)->SLCDCTRL.reg;
+	tmp = (tmp & OSC32KCTRL_SLCDCTRL_SLCDSEL) >> OSC32KCTRL_SLCDCTRL_SLCDSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_SLCDCTRL_SLCDSEL_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->SLCDCTRL.reg;
+	tmp &= ~OSC32KCTRL_SLCDCTRL_SLCDSEL;
+	tmp |= value << OSC32KCTRL_SLCDCTRL_SLCDSEL_Pos;
+	((Osc32kctrl *)hw)->SLCDCTRL.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_SLCDCTRL_SLCDSEL_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->SLCDCTRL.reg &= ~OSC32KCTRL_SLCDCTRL_SLCDSEL;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_SLCDCTRL_SLCDSEL_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->SLCDCTRL.reg ^= OSC32KCTRL_SLCDCTRL_SLCDSEL;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_SLCDCTRL_reg(const void *const hw, hri_osc32kctrl_slcdctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->SLCDCTRL.reg |= mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_slcdctrl_reg_t hri_osc32kctrl_get_SLCDCTRL_reg(const void *const             hw,
+                                                                            hri_osc32kctrl_slcdctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Osc32kctrl *)hw)->SLCDCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_write_SLCDCTRL_reg(const void *const hw, hri_osc32kctrl_slcdctrl_reg_t data)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->SLCDCTRL.reg = data;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_SLCDCTRL_reg(const void *const hw, hri_osc32kctrl_slcdctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->SLCDCTRL.reg &= ~mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_SLCDCTRL_reg(const void *const hw, hri_osc32kctrl_slcdctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->SLCDCTRL.reg ^= mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_slcdctrl_reg_t hri_osc32kctrl_read_SLCDCTRL_reg(const void *const hw)
+{
+	return ((Osc32kctrl *)hw)->SLCDCTRL.reg;
+}
+
+static inline void hri_osc32kctrl_set_XOSC32K_ENABLE_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_ENABLE;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_XOSC32K_ENABLE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & OSC32KCTRL_XOSC32K_ENABLE) >> OSC32KCTRL_XOSC32K_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_XOSC32K_ENABLE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp &= ~OSC32KCTRL_XOSC32K_ENABLE;
+	tmp |= value << OSC32KCTRL_XOSC32K_ENABLE_Pos;
+	((Osc32kctrl *)hw)->XOSC32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_XOSC32K_ENABLE_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_ENABLE;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_XOSC32K_ENABLE_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_ENABLE;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_XOSC32K_XTALEN_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_XTALEN;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_XOSC32K_XTALEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & OSC32KCTRL_XOSC32K_XTALEN) >> OSC32KCTRL_XOSC32K_XTALEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_XOSC32K_XTALEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp &= ~OSC32KCTRL_XOSC32K_XTALEN;
+	tmp |= value << OSC32KCTRL_XOSC32K_XTALEN_Pos;
+	((Osc32kctrl *)hw)->XOSC32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_XOSC32K_XTALEN_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_XTALEN;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_XOSC32K_XTALEN_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_XTALEN;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_XOSC32K_EN32K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_EN32K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_XOSC32K_EN32K_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & OSC32KCTRL_XOSC32K_EN32K) >> OSC32KCTRL_XOSC32K_EN32K_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_XOSC32K_EN32K_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp &= ~OSC32KCTRL_XOSC32K_EN32K;
+	tmp |= value << OSC32KCTRL_XOSC32K_EN32K_Pos;
+	((Osc32kctrl *)hw)->XOSC32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_XOSC32K_EN32K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_EN32K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_XOSC32K_EN32K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_EN32K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_XOSC32K_EN1K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_EN1K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_XOSC32K_EN1K_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & OSC32KCTRL_XOSC32K_EN1K) >> OSC32KCTRL_XOSC32K_EN1K_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_XOSC32K_EN1K_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp &= ~OSC32KCTRL_XOSC32K_EN1K;
+	tmp |= value << OSC32KCTRL_XOSC32K_EN1K_Pos;
+	((Osc32kctrl *)hw)->XOSC32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_XOSC32K_EN1K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_EN1K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_XOSC32K_EN1K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_EN1K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_XOSC32K_RUNSTDBY_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_RUNSTDBY;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_XOSC32K_RUNSTDBY_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & OSC32KCTRL_XOSC32K_RUNSTDBY) >> OSC32KCTRL_XOSC32K_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_XOSC32K_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp &= ~OSC32KCTRL_XOSC32K_RUNSTDBY;
+	tmp |= value << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos;
+	((Osc32kctrl *)hw)->XOSC32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_XOSC32K_RUNSTDBY_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_RUNSTDBY;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_XOSC32K_RUNSTDBY_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_RUNSTDBY;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_XOSC32K_ONDEMAND_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_ONDEMAND;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_XOSC32K_ONDEMAND_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & OSC32KCTRL_XOSC32K_ONDEMAND) >> OSC32KCTRL_XOSC32K_ONDEMAND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_XOSC32K_ONDEMAND_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp &= ~OSC32KCTRL_XOSC32K_ONDEMAND;
+	tmp |= value << OSC32KCTRL_XOSC32K_ONDEMAND_Pos;
+	((Osc32kctrl *)hw)->XOSC32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_XOSC32K_ONDEMAND_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_ONDEMAND;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_XOSC32K_ONDEMAND_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_ONDEMAND;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_XOSC32K_WRTLOCK_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_WRTLOCK;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_XOSC32K_WRTLOCK_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & OSC32KCTRL_XOSC32K_WRTLOCK) >> OSC32KCTRL_XOSC32K_WRTLOCK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_XOSC32K_WRTLOCK_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp &= ~OSC32KCTRL_XOSC32K_WRTLOCK;
+	tmp |= value << OSC32KCTRL_XOSC32K_WRTLOCK_Pos;
+	((Osc32kctrl *)hw)->XOSC32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_XOSC32K_WRTLOCK_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_WRTLOCK;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_XOSC32K_WRTLOCK_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_WRTLOCK;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_STARTUP(mask);
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_get_XOSC32K_STARTUP_bf(const void *const            hw,
+                                                                                 hri_osc32kctrl_xosc32k_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & OSC32KCTRL_XOSC32K_STARTUP(mask)) >> OSC32KCTRL_XOSC32K_STARTUP_Pos;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_write_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data)
+{
+	uint16_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp &= ~OSC32KCTRL_XOSC32K_STARTUP_Msk;
+	tmp |= OSC32KCTRL_XOSC32K_STARTUP(data);
+	((Osc32kctrl *)hw)->XOSC32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_STARTUP(mask);
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_STARTUP(mask);
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_read_XOSC32K_STARTUP_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp = (tmp & OSC32KCTRL_XOSC32K_STARTUP_Msk) >> OSC32KCTRL_XOSC32K_STARTUP_Pos;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_set_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg |= mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_get_XOSC32K_reg(const void *const            hw,
+                                                                          hri_osc32kctrl_xosc32k_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Osc32kctrl *)hw)->XOSC32K.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_write_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg = data;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg &= ~mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->XOSC32K.reg ^= mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_read_XOSC32K_reg(const void *const hw)
+{
+	return ((Osc32kctrl *)hw)->XOSC32K.reg;
+}
+
+static inline void hri_osc32kctrl_set_CFDCTRL_CFDEN_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_CFDEN;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_CFDCTRL_CFDEN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg;
+	tmp = (tmp & OSC32KCTRL_CFDCTRL_CFDEN) >> OSC32KCTRL_CFDCTRL_CFDEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_CFDCTRL_CFDEN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg;
+	tmp &= ~OSC32KCTRL_CFDCTRL_CFDEN;
+	tmp |= value << OSC32KCTRL_CFDCTRL_CFDEN_Pos;
+	((Osc32kctrl *)hw)->CFDCTRL.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_CFDCTRL_CFDEN_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_CFDEN;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_CFDCTRL_CFDEN_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_CFDEN;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_CFDCTRL_SWBACK_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_SWBACK;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_CFDCTRL_SWBACK_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg;
+	tmp = (tmp & OSC32KCTRL_CFDCTRL_SWBACK) >> OSC32KCTRL_CFDCTRL_SWBACK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_CFDCTRL_SWBACK_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg;
+	tmp &= ~OSC32KCTRL_CFDCTRL_SWBACK;
+	tmp |= value << OSC32KCTRL_CFDCTRL_SWBACK_Pos;
+	((Osc32kctrl *)hw)->CFDCTRL.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_CFDCTRL_SWBACK_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_SWBACK;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_CFDCTRL_SWBACK_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_SWBACK;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_CFDCTRL_CFDPRESC_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_CFDPRESC;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_CFDCTRL_CFDPRESC_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg;
+	tmp = (tmp & OSC32KCTRL_CFDCTRL_CFDPRESC) >> OSC32KCTRL_CFDCTRL_CFDPRESC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_CFDCTRL_CFDPRESC_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg;
+	tmp &= ~OSC32KCTRL_CFDCTRL_CFDPRESC;
+	tmp |= value << OSC32KCTRL_CFDCTRL_CFDPRESC_Pos;
+	((Osc32kctrl *)hw)->CFDCTRL.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_CFDCTRL_CFDPRESC_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_CFDPRESC;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_CFDCTRL_CFDPRESC_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_CFDPRESC;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg |= mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_cfdctrl_reg_t hri_osc32kctrl_get_CFDCTRL_reg(const void *const            hw,
+                                                                          hri_osc32kctrl_cfdctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_write_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t data)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg = data;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg &= ~mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->CFDCTRL.reg ^= mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_cfdctrl_reg_t hri_osc32kctrl_read_CFDCTRL_reg(const void *const hw)
+{
+	return ((Osc32kctrl *)hw)->CFDCTRL.reg;
+}
+
+static inline void hri_osc32kctrl_set_EVCTRL_CFDEO_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->EVCTRL.reg |= OSC32KCTRL_EVCTRL_CFDEO;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_EVCTRL_CFDEO_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Osc32kctrl *)hw)->EVCTRL.reg;
+	tmp = (tmp & OSC32KCTRL_EVCTRL_CFDEO) >> OSC32KCTRL_EVCTRL_CFDEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_EVCTRL_CFDEO_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->EVCTRL.reg;
+	tmp &= ~OSC32KCTRL_EVCTRL_CFDEO;
+	tmp |= value << OSC32KCTRL_EVCTRL_CFDEO_Pos;
+	((Osc32kctrl *)hw)->EVCTRL.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_EVCTRL_CFDEO_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->EVCTRL.reg &= ~OSC32KCTRL_EVCTRL_CFDEO;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_EVCTRL_CFDEO_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->EVCTRL.reg ^= OSC32KCTRL_EVCTRL_CFDEO;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->EVCTRL.reg |= mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_evctrl_reg_t hri_osc32kctrl_get_EVCTRL_reg(const void *const           hw,
+                                                                        hri_osc32kctrl_evctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Osc32kctrl *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_write_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t data)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->EVCTRL.reg = data;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->EVCTRL.reg &= ~mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->EVCTRL.reg ^= mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_evctrl_reg_t hri_osc32kctrl_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Osc32kctrl *)hw)->EVCTRL.reg;
+}
+
+static inline void hri_osc32kctrl_set_OSCULP32K_EN32K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_EN32K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_OSCULP32K_EN32K_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
+	tmp = (tmp & OSC32KCTRL_OSCULP32K_EN32K) >> OSC32KCTRL_OSCULP32K_EN32K_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_OSCULP32K_EN32K_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
+	tmp &= ~OSC32KCTRL_OSCULP32K_EN32K;
+	tmp |= value << OSC32KCTRL_OSCULP32K_EN32K_Pos;
+	((Osc32kctrl *)hw)->OSCULP32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_OSCULP32K_EN32K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_EN32K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_OSCULP32K_EN32K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_EN32K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_OSCULP32K_EN1K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_EN1K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_OSCULP32K_EN1K_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
+	tmp = (tmp & OSC32KCTRL_OSCULP32K_EN1K) >> OSC32KCTRL_OSCULP32K_EN1K_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_OSCULP32K_EN1K_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
+	tmp &= ~OSC32KCTRL_OSCULP32K_EN1K;
+	tmp |= value << OSC32KCTRL_OSCULP32K_EN1K_Pos;
+	((Osc32kctrl *)hw)->OSCULP32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_OSCULP32K_EN1K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_EN1K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_OSCULP32K_EN1K_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_EN1K;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_OSCULP32K_WRTLOCK_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_WRTLOCK;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_osc32kctrl_get_OSCULP32K_WRTLOCK_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
+	tmp = (tmp & OSC32KCTRL_OSCULP32K_WRTLOCK) >> OSC32KCTRL_OSCULP32K_WRTLOCK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_osc32kctrl_write_OSCULP32K_WRTLOCK_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
+	tmp &= ~OSC32KCTRL_OSCULP32K_WRTLOCK;
+	tmp |= value << OSC32KCTRL_OSCULP32K_WRTLOCK_Pos;
+	((Osc32kctrl *)hw)->OSCULP32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_OSCULP32K_WRTLOCK_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_WRTLOCK;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_OSCULP32K_WRTLOCK_bit(const void *const hw)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_WRTLOCK;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_set_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_CALIB(mask);
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_get_OSCULP32K_CALIB_bf(const void *const              hw,
+                                                                                   hri_osc32kctrl_osculp32k_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
+	tmp = (tmp & OSC32KCTRL_OSCULP32K_CALIB(mask)) >> OSC32KCTRL_OSCULP32K_CALIB_Pos;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_write_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t data)
+{
+	uint32_t tmp;
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
+	tmp &= ~OSC32KCTRL_OSCULP32K_CALIB_Msk;
+	tmp |= OSC32KCTRL_OSCULP32K_CALIB(data);
+	((Osc32kctrl *)hw)->OSCULP32K.reg = tmp;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_CALIB(mask);
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_CALIB(mask);
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_read_OSCULP32K_CALIB_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
+	tmp = (tmp & OSC32KCTRL_OSCULP32K_CALIB_Msk) >> OSC32KCTRL_OSCULP32K_CALIB_Pos;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_set_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg |= mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_get_OSCULP32K_reg(const void *const              hw,
+                                                                              hri_osc32kctrl_osculp32k_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_osc32kctrl_write_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t data)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg = data;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_clear_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg &= ~mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_osc32kctrl_toggle_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask)
+{
+	OSC32KCTRL_CRITICAL_SECTION_ENTER();
+	((Osc32kctrl *)hw)->OSCULP32K.reg ^= mask;
+	OSC32KCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_read_OSCULP32K_reg(const void *const hw)
+{
+	return ((Osc32kctrl *)hw)->OSCULP32K.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_OSC32KCTRL_L22_H_INCLUDED */
+#endif /* _SAML22_OSC32KCTRL_COMPONENT_ */
diff --git a/watch-library/hardware/hri/hri_oscctrl_l22.h b/watch-library/hardware/hri/hri_oscctrl_l22.h
new file mode 100644
index 00000000..d1bc4b60
--- /dev/null
+++ b/watch-library/hardware/hri/hri_oscctrl_l22.h
@@ -0,0 +1,3451 @@
+/**
+ * \file
+ *
+ * \brief SAM OSCCTRL
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_OSCCTRL_COMPONENT_
+#ifndef _HRI_OSCCTRL_L22_H_INCLUDED_
+#define _HRI_OSCCTRL_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_OSCCTRL_CRITICAL_SECTIONS)
+#define OSCCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define OSCCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define OSCCTRL_CRITICAL_SECTION_ENTER()
+#define OSCCTRL_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_oscctrl_dfllctrl_reg_t;
+typedef uint16_t hri_oscctrl_xoscctrl_reg_t;
+typedef uint32_t hri_oscctrl_dfllmul_reg_t;
+typedef uint32_t hri_oscctrl_dfllval_reg_t;
+typedef uint32_t hri_oscctrl_dpllctrlb_reg_t;
+typedef uint32_t hri_oscctrl_dpllratio_reg_t;
+typedef uint32_t hri_oscctrl_intenset_reg_t;
+typedef uint32_t hri_oscctrl_intflag_reg_t;
+typedef uint32_t hri_oscctrl_status_reg_t;
+typedef uint8_t  hri_oscctrl_cfdpresc_reg_t;
+typedef uint8_t  hri_oscctrl_dfllsync_reg_t;
+typedef uint8_t  hri_oscctrl_dpllctrla_reg_t;
+typedef uint8_t  hri_oscctrl_dpllpresc_reg_t;
+typedef uint8_t  hri_oscctrl_dpllstatus_reg_t;
+typedef uint8_t  hri_oscctrl_dpllsyncbusy_reg_t;
+typedef uint8_t  hri_oscctrl_evctrl_reg_t;
+typedef uint8_t  hri_oscctrl_osc16mctrl_reg_t;
+
+static inline void hri_oscctrl_wait_for_sync(const void *const hw, hri_oscctrl_dpllsyncbusy_reg_t reg)
+{
+	while (((Oscctrl *)hw)->DPLLSYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_oscctrl_is_syncing(const void *const hw, hri_oscctrl_dpllsyncbusy_reg_t reg)
+{
+	return ((Oscctrl *)hw)->DPLLSYNCBUSY.reg & reg;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_XOSCRDY_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY) >> OSCCTRL_INTFLAG_XOSCRDY_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_XOSCRDY_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_XOSCFAIL_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL) >> OSCCTRL_INTFLAG_XOSCFAIL_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_XOSCFAIL_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_OSC16MRDY_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_OSC16MRDY) >> OSCCTRL_INTFLAG_OSC16MRDY_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_OSC16MRDY_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_OSC16MRDY;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DFLLRDY_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRDY) >> OSCCTRL_INTFLAG_DFLLRDY_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DFLLRDY_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRDY;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DFLLOOB_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLOOB) >> OSCCTRL_INTFLAG_DFLLOOB_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DFLLOOB_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLOOB;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DFLLLCKF_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKF) >> OSCCTRL_INTFLAG_DFLLLCKF_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DFLLLCKF_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKF;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DFLLLCKC_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKC) >> OSCCTRL_INTFLAG_DFLLLCKC_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DFLLLCKC_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKC;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DFLLRCS_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRCS) >> OSCCTRL_INTFLAG_DFLLRCS_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DFLLRCS_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRCS;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DPLLLCKR_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLCKR) >> OSCCTRL_INTFLAG_DPLLLCKR_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DPLLLCKR_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLCKR;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DPLLLCKF_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLCKF) >> OSCCTRL_INTFLAG_DPLLLCKF_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DPLLLCKF_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLCKF;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DPLLLTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLTO) >> OSCCTRL_INTFLAG_DPLLLTO_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DPLLLTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLTO;
+}
+
+static inline bool hri_oscctrl_get_INTFLAG_DPLLLDRTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLDRTO) >> OSCCTRL_INTFLAG_DPLLLDRTO_Pos;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_DPLLLDRTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLDRTO;
+}
+
+static inline bool hri_oscctrl_get_interrupt_XOSCRDY_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY) >> OSCCTRL_INTFLAG_XOSCRDY_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_XOSCRDY_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY;
+}
+
+static inline bool hri_oscctrl_get_interrupt_XOSCFAIL_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL) >> OSCCTRL_INTFLAG_XOSCFAIL_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_XOSCFAIL_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL;
+}
+
+static inline bool hri_oscctrl_get_interrupt_OSC16MRDY_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_OSC16MRDY) >> OSCCTRL_INTFLAG_OSC16MRDY_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_OSC16MRDY_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_OSC16MRDY;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DFLLRDY_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRDY) >> OSCCTRL_INTFLAG_DFLLRDY_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DFLLRDY_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRDY;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DFLLOOB_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLOOB) >> OSCCTRL_INTFLAG_DFLLOOB_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DFLLOOB_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLOOB;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DFLLLCKF_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKF) >> OSCCTRL_INTFLAG_DFLLLCKF_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DFLLLCKF_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKF;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DFLLLCKC_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKC) >> OSCCTRL_INTFLAG_DFLLLCKC_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DFLLLCKC_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKC;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DFLLRCS_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRCS) >> OSCCTRL_INTFLAG_DFLLRCS_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DFLLRCS_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRCS;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DPLLLCKR_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLCKR) >> OSCCTRL_INTFLAG_DPLLLCKR_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DPLLLCKR_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLCKR;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DPLLLCKF_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLCKF) >> OSCCTRL_INTFLAG_DPLLLCKF_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DPLLLCKF_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLCKF;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DPLLLTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLTO) >> OSCCTRL_INTFLAG_DPLLLTO_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DPLLLTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLTO;
+}
+
+static inline bool hri_oscctrl_get_interrupt_DPLLLDRTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLDRTO) >> OSCCTRL_INTFLAG_DPLLLDRTO_Pos;
+}
+
+static inline void hri_oscctrl_clear_interrupt_DPLLLDRTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLDRTO;
+}
+
+static inline hri_oscctrl_intflag_reg_t hri_oscctrl_get_INTFLAG_reg(const void *const         hw,
+                                                                    hri_oscctrl_intflag_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_oscctrl_intflag_reg_t hri_oscctrl_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Oscctrl *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_oscctrl_clear_INTFLAG_reg(const void *const hw, hri_oscctrl_intflag_reg_t mask)
+{
+	((Oscctrl *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_oscctrl_set_INTEN_XOSCRDY_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY;
+}
+
+static inline bool hri_oscctrl_get_INTEN_XOSCRDY_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCRDY) >> OSCCTRL_INTENSET_XOSCRDY_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_XOSCRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_XOSCRDY_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY;
+}
+
+static inline void hri_oscctrl_set_INTEN_XOSCFAIL_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL;
+}
+
+static inline bool hri_oscctrl_get_INTEN_XOSCFAIL_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCFAIL) >> OSCCTRL_INTENSET_XOSCFAIL_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_XOSCFAIL_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_XOSCFAIL_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL;
+}
+
+static inline void hri_oscctrl_set_INTEN_OSC16MRDY_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_OSC16MRDY;
+}
+
+static inline bool hri_oscctrl_get_INTEN_OSC16MRDY_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_OSC16MRDY) >> OSCCTRL_INTENSET_OSC16MRDY_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_OSC16MRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_OSC16MRDY;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_OSC16MRDY;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_OSC16MRDY_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_OSC16MRDY;
+}
+
+static inline void hri_oscctrl_set_INTEN_DFLLRDY_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRDY;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DFLLRDY_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLRDY) >> OSCCTRL_INTENSET_DFLLRDY_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DFLLRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRDY;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRDY;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DFLLRDY_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRDY;
+}
+
+static inline void hri_oscctrl_set_INTEN_DFLLOOB_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLOOB;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DFLLOOB_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLOOB) >> OSCCTRL_INTENSET_DFLLOOB_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DFLLOOB_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLOOB;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLOOB;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DFLLOOB_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLOOB;
+}
+
+static inline void hri_oscctrl_set_INTEN_DFLLLCKF_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKF;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DFLLLCKF_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLLCKF) >> OSCCTRL_INTENSET_DFLLLCKF_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DFLLLCKF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKF;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKF;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DFLLLCKF_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKF;
+}
+
+static inline void hri_oscctrl_set_INTEN_DFLLLCKC_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKC;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DFLLLCKC_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLLCKC) >> OSCCTRL_INTENSET_DFLLLCKC_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DFLLLCKC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKC;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKC;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DFLLLCKC_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKC;
+}
+
+static inline void hri_oscctrl_set_INTEN_DFLLRCS_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRCS;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DFLLRCS_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLRCS) >> OSCCTRL_INTENSET_DFLLRCS_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DFLLRCS_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRCS;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRCS;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DFLLRCS_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRCS;
+}
+
+static inline void hri_oscctrl_set_INTEN_DPLLLCKR_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLCKR;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DPLLLCKR_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLLLCKR) >> OSCCTRL_INTENSET_DPLLLCKR_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DPLLLCKR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLCKR;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLCKR;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DPLLLCKR_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLCKR;
+}
+
+static inline void hri_oscctrl_set_INTEN_DPLLLCKF_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLCKF;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DPLLLCKF_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLLLCKF) >> OSCCTRL_INTENSET_DPLLLCKF_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DPLLLCKF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLCKF;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLCKF;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DPLLLCKF_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLCKF;
+}
+
+static inline void hri_oscctrl_set_INTEN_DPLLLTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLTO;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DPLLLTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLLLTO) >> OSCCTRL_INTENSET_DPLLLTO_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DPLLLTO_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLTO;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLTO;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DPLLLTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLTO;
+}
+
+static inline void hri_oscctrl_set_INTEN_DPLLLDRTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLDRTO;
+}
+
+static inline bool hri_oscctrl_get_INTEN_DPLLLDRTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLLLDRTO) >> OSCCTRL_INTENSET_DPLLLDRTO_Pos;
+}
+
+static inline void hri_oscctrl_write_INTEN_DPLLLDRTO_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLDRTO;
+	} else {
+		((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLDRTO;
+	}
+}
+
+static inline void hri_oscctrl_clear_INTEN_DPLLLDRTO_bit(const void *const hw)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLDRTO;
+}
+
+static inline void hri_oscctrl_set_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t mask)
+{
+	((Oscctrl *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_oscctrl_intenset_reg_t hri_oscctrl_get_INTEN_reg(const void *const          hw,
+                                                                   hri_oscctrl_intenset_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_oscctrl_intenset_reg_t hri_oscctrl_read_INTEN_reg(const void *const hw)
+{
+	return ((Oscctrl *)hw)->INTENSET.reg;
+}
+
+static inline void hri_oscctrl_write_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t data)
+{
+	((Oscctrl *)hw)->INTENSET.reg = data;
+	((Oscctrl *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_oscctrl_clear_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t mask)
+{
+	((Oscctrl *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_oscctrl_get_STATUS_XOSCRDY_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCRDY) >> OSCCTRL_STATUS_XOSCRDY_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_XOSCFAIL_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCFAIL) >> OSCCTRL_STATUS_XOSCFAIL_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_XOSCCKSW_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCCKSW) >> OSCCTRL_STATUS_XOSCCKSW_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_OSC16MRDY_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_OSC16MRDY) >> OSCCTRL_STATUS_OSC16MRDY_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DFLLRDY_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLRDY) >> OSCCTRL_STATUS_DFLLRDY_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DFLLOOB_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLOOB) >> OSCCTRL_STATUS_DFLLOOB_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DFLLLCKF_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLLCKF) >> OSCCTRL_STATUS_DFLLLCKF_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DFLLLCKC_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLLCKC) >> OSCCTRL_STATUS_DFLLLCKC_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DFLLRCS_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLRCS) >> OSCCTRL_STATUS_DFLLRCS_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DPLLLCKR_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLLLCKR) >> OSCCTRL_STATUS_DPLLLCKR_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DPLLLCKF_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLLLCKF) >> OSCCTRL_STATUS_DPLLLCKF_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DPLLTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLLTO) >> OSCCTRL_STATUS_DPLLTO_Pos;
+}
+
+static inline bool hri_oscctrl_get_STATUS_DPLLLDRTO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLLLDRTO) >> OSCCTRL_STATUS_DPLLLDRTO_Pos;
+}
+
+static inline hri_oscctrl_status_reg_t hri_oscctrl_get_STATUS_reg(const void *const hw, hri_oscctrl_status_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_oscctrl_status_reg_t hri_oscctrl_read_STATUS_reg(const void *const hw)
+{
+	return ((Oscctrl *)hw)->STATUS.reg;
+}
+
+static inline bool hri_oscctrl_get_DPLLSYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_ENABLE) >> OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_oscctrl_get_DPLLSYNCBUSY_DPLLRATIO_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_DPLLRATIO) >> OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos;
+}
+
+static inline bool hri_oscctrl_get_DPLLSYNCBUSY_DPLLPRESC_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_DPLLPRESC) >> OSCCTRL_DPLLSYNCBUSY_DPLLPRESC_Pos;
+}
+
+static inline hri_oscctrl_dpllsyncbusy_reg_t hri_oscctrl_get_DPLLSYNCBUSY_reg(const void *const              hw,
+                                                                              hri_oscctrl_dpllsyncbusy_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DPLLSYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_oscctrl_dpllsyncbusy_reg_t hri_oscctrl_read_DPLLSYNCBUSY_reg(const void *const hw)
+{
+	return ((Oscctrl *)hw)->DPLLSYNCBUSY.reg;
+}
+
+static inline bool hri_oscctrl_get_DPLLSTATUS_LOCK_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_LOCK) >> OSCCTRL_DPLLSTATUS_LOCK_Pos;
+}
+
+static inline bool hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(const void *const hw)
+{
+	return (((Oscctrl *)hw)->DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_CLKRDY) >> OSCCTRL_DPLLSTATUS_CLKRDY_Pos;
+}
+
+static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrl_get_DPLLSTATUS_reg(const void *const            hw,
+                                                                          hri_oscctrl_dpllstatus_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DPLLSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrl_read_DPLLSTATUS_reg(const void *const hw)
+{
+	return ((Oscctrl *)hw)->DPLLSTATUS.reg;
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_ENABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_ENABLE;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_XOSCCTRL_ENABLE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	tmp = ((Oscctrl *)hw)->XOSCCTRL.reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_ENABLE) >> OSCCTRL_XOSCCTRL_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_ENABLE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->XOSCCTRL.reg;
+	tmp &= ~OSCCTRL_XOSCCTRL_ENABLE;
+	tmp |= value << OSCCTRL_XOSCCTRL_ENABLE_Pos;
+	((Oscctrl *)hw)->XOSCCTRL.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_ENABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_ENABLE;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_ENABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_ENABLE;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_XTALEN_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_XTALEN;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_XOSCCTRL_XTALEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL.reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_XTALEN) >> OSCCTRL_XOSCCTRL_XTALEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_XTALEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->XOSCCTRL.reg;
+	tmp &= ~OSCCTRL_XOSCCTRL_XTALEN;
+	tmp |= value << OSCCTRL_XOSCCTRL_XTALEN_Pos;
+	((Oscctrl *)hw)->XOSCCTRL.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_XTALEN_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_XTALEN;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_XTALEN_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_XTALEN;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_CFDEN_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_CFDEN;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_XOSCCTRL_CFDEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL.reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_CFDEN) >> OSCCTRL_XOSCCTRL_CFDEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_CFDEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->XOSCCTRL.reg;
+	tmp &= ~OSCCTRL_XOSCCTRL_CFDEN;
+	tmp |= value << OSCCTRL_XOSCCTRL_CFDEN_Pos;
+	((Oscctrl *)hw)->XOSCCTRL.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_CFDEN_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_CFDEN;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_CFDEN_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_CFDEN;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_SWBEN_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_SWBEN;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_XOSCCTRL_SWBEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL.reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_SWBEN) >> OSCCTRL_XOSCCTRL_SWBEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_SWBEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->XOSCCTRL.reg;
+	tmp &= ~OSCCTRL_XOSCCTRL_SWBEN;
+	tmp |= value << OSCCTRL_XOSCCTRL_SWBEN_Pos;
+	((Oscctrl *)hw)->XOSCCTRL.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_SWBEN_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_SWBEN;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_SWBEN_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_SWBEN;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_RUNSTDBY_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_RUNSTDBY;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_XOSCCTRL_RUNSTDBY_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL.reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_RUNSTDBY) >> OSCCTRL_XOSCCTRL_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->XOSCCTRL.reg;
+	tmp &= ~OSCCTRL_XOSCCTRL_RUNSTDBY;
+	tmp |= value << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos;
+	((Oscctrl *)hw)->XOSCCTRL.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_RUNSTDBY_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_RUNSTDBY;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_RUNSTDBY_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_RUNSTDBY;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_ONDEMAND_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_ONDEMAND;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_XOSCCTRL_ONDEMAND_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL.reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_ONDEMAND) >> OSCCTRL_XOSCCTRL_ONDEMAND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_ONDEMAND_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->XOSCCTRL.reg;
+	tmp &= ~OSCCTRL_XOSCCTRL_ONDEMAND;
+	tmp |= value << OSCCTRL_XOSCCTRL_ONDEMAND_Pos;
+	((Oscctrl *)hw)->XOSCCTRL.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_ONDEMAND_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_ONDEMAND;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_ONDEMAND_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_ONDEMAND;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_AMPGC_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_AMPGC;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_XOSCCTRL_AMPGC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL.reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_AMPGC) >> OSCCTRL_XOSCCTRL_AMPGC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_AMPGC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->XOSCCTRL.reg;
+	tmp &= ~OSCCTRL_XOSCCTRL_AMPGC;
+	tmp |= value << OSCCTRL_XOSCCTRL_AMPGC_Pos;
+	((Oscctrl *)hw)->XOSCCTRL.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_AMPGC_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_AMPGC;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_AMPGC_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_AMPGC;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_GAIN_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_GAIN(mask);
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_GAIN_bf(const void *const          hw,
+                                                                          hri_oscctrl_xoscctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL.reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_GAIN(mask)) >> OSCCTRL_XOSCCTRL_GAIN_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_GAIN_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t data)
+{
+	uint16_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->XOSCCTRL.reg;
+	tmp &= ~OSCCTRL_XOSCCTRL_GAIN_Msk;
+	tmp |= OSCCTRL_XOSCCTRL_GAIN(data);
+	((Oscctrl *)hw)->XOSCCTRL.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_GAIN_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_GAIN(mask);
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_GAIN_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_GAIN(mask);
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_GAIN_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL.reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_GAIN_Msk) >> OSCCTRL_XOSCCTRL_GAIN_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_STARTUP_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_STARTUP(mask);
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_STARTUP_bf(const void *const          hw,
+                                                                             hri_oscctrl_xoscctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL.reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_STARTUP(mask)) >> OSCCTRL_XOSCCTRL_STARTUP_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_STARTUP_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t data)
+{
+	uint16_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->XOSCCTRL.reg;
+	tmp &= ~OSCCTRL_XOSCCTRL_STARTUP_Msk;
+	tmp |= OSCCTRL_XOSCCTRL_STARTUP(data);
+	((Oscctrl *)hw)->XOSCCTRL.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_STARTUP_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_STARTUP(mask);
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_STARTUP_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_STARTUP(mask);
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_STARTUP_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Oscctrl *)hw)->XOSCCTRL.reg;
+	tmp = (tmp & OSCCTRL_XOSCCTRL_STARTUP_Msk) >> OSCCTRL_XOSCCTRL_STARTUP_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_XOSCCTRL_reg(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg |= mask;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_reg(const void *const          hw,
+                                                                      hri_oscctrl_xoscctrl_reg_t mask)
+{
+	uint16_t tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	tmp = ((Oscctrl *)hw)->XOSCCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_XOSCCTRL_reg(const void *const hw, hri_oscctrl_xoscctrl_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg = data;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_XOSCCTRL_reg(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg &= ~mask;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_XOSCCTRL_reg(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->XOSCCTRL.reg ^= mask;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_reg(const void *const hw)
+{
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	return ((Oscctrl *)hw)->XOSCCTRL.reg;
+}
+
+static inline void hri_oscctrl_set_CFDPRESC_CFDPRESC_bf(const void *const hw, hri_oscctrl_cfdpresc_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->CFDPRESC.reg |= OSCCTRL_CFDPRESC_CFDPRESC(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_cfdpresc_reg_t hri_oscctrl_get_CFDPRESC_CFDPRESC_bf(const void *const          hw,
+                                                                              hri_oscctrl_cfdpresc_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->CFDPRESC.reg;
+	tmp = (tmp & OSCCTRL_CFDPRESC_CFDPRESC(mask)) >> OSCCTRL_CFDPRESC_CFDPRESC_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_CFDPRESC_CFDPRESC_bf(const void *const hw, hri_oscctrl_cfdpresc_reg_t data)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->CFDPRESC.reg;
+	tmp &= ~OSCCTRL_CFDPRESC_CFDPRESC_Msk;
+	tmp |= OSCCTRL_CFDPRESC_CFDPRESC(data);
+	((Oscctrl *)hw)->CFDPRESC.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_CFDPRESC_CFDPRESC_bf(const void *const hw, hri_oscctrl_cfdpresc_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->CFDPRESC.reg &= ~OSCCTRL_CFDPRESC_CFDPRESC(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_CFDPRESC_CFDPRESC_bf(const void *const hw, hri_oscctrl_cfdpresc_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->CFDPRESC.reg ^= OSCCTRL_CFDPRESC_CFDPRESC(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_cfdpresc_reg_t hri_oscctrl_read_CFDPRESC_CFDPRESC_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->CFDPRESC.reg;
+	tmp = (tmp & OSCCTRL_CFDPRESC_CFDPRESC_Msk) >> OSCCTRL_CFDPRESC_CFDPRESC_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_CFDPRESC_reg(const void *const hw, hri_oscctrl_cfdpresc_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->CFDPRESC.reg |= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_cfdpresc_reg_t hri_oscctrl_get_CFDPRESC_reg(const void *const          hw,
+                                                                      hri_oscctrl_cfdpresc_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->CFDPRESC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_CFDPRESC_reg(const void *const hw, hri_oscctrl_cfdpresc_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->CFDPRESC.reg = data;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_CFDPRESC_reg(const void *const hw, hri_oscctrl_cfdpresc_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->CFDPRESC.reg &= ~mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_CFDPRESC_reg(const void *const hw, hri_oscctrl_cfdpresc_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->CFDPRESC.reg ^= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_cfdpresc_reg_t hri_oscctrl_read_CFDPRESC_reg(const void *const hw)
+{
+	return ((Oscctrl *)hw)->CFDPRESC.reg;
+}
+
+static inline void hri_oscctrl_set_EVCTRL_CFDEO_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->EVCTRL.reg |= OSCCTRL_EVCTRL_CFDEO;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_EVCTRL_CFDEO_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->EVCTRL.reg;
+	tmp = (tmp & OSCCTRL_EVCTRL_CFDEO) >> OSCCTRL_EVCTRL_CFDEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_EVCTRL_CFDEO_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->EVCTRL.reg;
+	tmp &= ~OSCCTRL_EVCTRL_CFDEO;
+	tmp |= value << OSCCTRL_EVCTRL_CFDEO_Pos;
+	((Oscctrl *)hw)->EVCTRL.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_EVCTRL_CFDEO_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->EVCTRL.reg &= ~OSCCTRL_EVCTRL_CFDEO;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_EVCTRL_CFDEO_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->EVCTRL.reg ^= OSCCTRL_EVCTRL_CFDEO;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->EVCTRL.reg |= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_evctrl_reg_t hri_oscctrl_get_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->EVCTRL.reg = data;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->EVCTRL.reg &= ~mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->EVCTRL.reg ^= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_evctrl_reg_t hri_oscctrl_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Oscctrl *)hw)->EVCTRL.reg;
+}
+
+static inline void hri_oscctrl_set_OSC16MCTRL_ENABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->OSC16MCTRL.reg |= OSCCTRL_OSC16MCTRL_ENABLE;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_OSC16MCTRL_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg;
+	tmp = (tmp & OSCCTRL_OSC16MCTRL_ENABLE) >> OSCCTRL_OSC16MCTRL_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_OSC16MCTRL_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg;
+	tmp &= ~OSCCTRL_OSC16MCTRL_ENABLE;
+	tmp |= value << OSCCTRL_OSC16MCTRL_ENABLE_Pos;
+	((Oscctrl *)hw)->OSC16MCTRL.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_OSC16MCTRL_ENABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->OSC16MCTRL.reg &= ~OSCCTRL_OSC16MCTRL_ENABLE;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_OSC16MCTRL_ENABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->OSC16MCTRL.reg ^= OSCCTRL_OSC16MCTRL_ENABLE;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_OSC16MCTRL_RUNSTDBY_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->OSC16MCTRL.reg |= OSCCTRL_OSC16MCTRL_RUNSTDBY;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_OSC16MCTRL_RUNSTDBY_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg;
+	tmp = (tmp & OSCCTRL_OSC16MCTRL_RUNSTDBY) >> OSCCTRL_OSC16MCTRL_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_OSC16MCTRL_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg;
+	tmp &= ~OSCCTRL_OSC16MCTRL_RUNSTDBY;
+	tmp |= value << OSCCTRL_OSC16MCTRL_RUNSTDBY_Pos;
+	((Oscctrl *)hw)->OSC16MCTRL.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_OSC16MCTRL_RUNSTDBY_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->OSC16MCTRL.reg &= ~OSCCTRL_OSC16MCTRL_RUNSTDBY;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_OSC16MCTRL_RUNSTDBY_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->OSC16MCTRL.reg ^= OSCCTRL_OSC16MCTRL_RUNSTDBY;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_OSC16MCTRL_ONDEMAND_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->OSC16MCTRL.reg |= OSCCTRL_OSC16MCTRL_ONDEMAND;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_OSC16MCTRL_ONDEMAND_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg;
+	tmp = (tmp & OSCCTRL_OSC16MCTRL_ONDEMAND) >> OSCCTRL_OSC16MCTRL_ONDEMAND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_OSC16MCTRL_ONDEMAND_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg;
+	tmp &= ~OSCCTRL_OSC16MCTRL_ONDEMAND;
+	tmp |= value << OSCCTRL_OSC16MCTRL_ONDEMAND_Pos;
+	((Oscctrl *)hw)->OSC16MCTRL.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_OSC16MCTRL_ONDEMAND_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->OSC16MCTRL.reg &= ~OSCCTRL_OSC16MCTRL_ONDEMAND;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_OSC16MCTRL_ONDEMAND_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->OSC16MCTRL.reg ^= OSCCTRL_OSC16MCTRL_ONDEMAND;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_OSC16MCTRL_FSEL_bf(const void *const hw, hri_oscctrl_osc16mctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->OSC16MCTRL.reg |= OSCCTRL_OSC16MCTRL_FSEL(mask);
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_osc16mctrl_reg_t hri_oscctrl_get_OSC16MCTRL_FSEL_bf(const void *const            hw,
+                                                                              hri_oscctrl_osc16mctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg;
+	tmp = (tmp & OSCCTRL_OSC16MCTRL_FSEL(mask)) >> OSCCTRL_OSC16MCTRL_FSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_OSC16MCTRL_FSEL_bf(const void *const hw, hri_oscctrl_osc16mctrl_reg_t data)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg;
+	tmp &= ~OSCCTRL_OSC16MCTRL_FSEL_Msk;
+	tmp |= OSCCTRL_OSC16MCTRL_FSEL(data);
+	((Oscctrl *)hw)->OSC16MCTRL.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_OSC16MCTRL_FSEL_bf(const void *const hw, hri_oscctrl_osc16mctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->OSC16MCTRL.reg &= ~OSCCTRL_OSC16MCTRL_FSEL(mask);
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_OSC16MCTRL_FSEL_bf(const void *const hw, hri_oscctrl_osc16mctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->OSC16MCTRL.reg ^= OSCCTRL_OSC16MCTRL_FSEL(mask);
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_osc16mctrl_reg_t hri_oscctrl_read_OSC16MCTRL_FSEL_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg;
+	tmp = (tmp & OSCCTRL_OSC16MCTRL_FSEL_Msk) >> OSCCTRL_OSC16MCTRL_FSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_OSC16MCTRL_reg(const void *const hw, hri_oscctrl_osc16mctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->OSC16MCTRL.reg |= mask;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_osc16mctrl_reg_t hri_oscctrl_get_OSC16MCTRL_reg(const void *const            hw,
+                                                                          hri_oscctrl_osc16mctrl_reg_t mask)
+{
+	uint8_t tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_OSC16MCTRL_reg(const void *const hw, hri_oscctrl_osc16mctrl_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->OSC16MCTRL.reg = data;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_OSC16MCTRL_reg(const void *const hw, hri_oscctrl_osc16mctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->OSC16MCTRL.reg &= ~mask;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_OSC16MCTRL_reg(const void *const hw, hri_oscctrl_osc16mctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->OSC16MCTRL.reg ^= mask;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_osc16mctrl_reg_t hri_oscctrl_read_OSC16MCTRL_reg(const void *const hw)
+{
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	return ((Oscctrl *)hw)->OSC16MCTRL.reg;
+}
+
+static inline void hri_oscctrl_set_DFLLCTRL_ENABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_ENABLE;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLCTRL_ENABLE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	tmp = ((Oscctrl *)hw)->DFLLCTRL.reg;
+	tmp = (tmp & OSCCTRL_DFLLCTRL_ENABLE) >> OSCCTRL_DFLLCTRL_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRL_ENABLE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLCTRL.reg;
+	tmp &= ~OSCCTRL_DFLLCTRL_ENABLE;
+	tmp |= value << OSCCTRL_DFLLCTRL_ENABLE_Pos;
+	((Oscctrl *)hw)->DFLLCTRL.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRL_ENABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_ENABLE;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRL_ENABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_ENABLE;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLCTRL_MODE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_MODE;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLCTRL_MODE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRL.reg;
+	tmp = (tmp & OSCCTRL_DFLLCTRL_MODE) >> OSCCTRL_DFLLCTRL_MODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRL_MODE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLCTRL.reg;
+	tmp &= ~OSCCTRL_DFLLCTRL_MODE;
+	tmp |= value << OSCCTRL_DFLLCTRL_MODE_Pos;
+	((Oscctrl *)hw)->DFLLCTRL.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRL_MODE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_MODE;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRL_MODE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_MODE;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLCTRL_STABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_STABLE;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLCTRL_STABLE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRL.reg;
+	tmp = (tmp & OSCCTRL_DFLLCTRL_STABLE) >> OSCCTRL_DFLLCTRL_STABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRL_STABLE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLCTRL.reg;
+	tmp &= ~OSCCTRL_DFLLCTRL_STABLE;
+	tmp |= value << OSCCTRL_DFLLCTRL_STABLE_Pos;
+	((Oscctrl *)hw)->DFLLCTRL.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRL_STABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_STABLE;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRL_STABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_STABLE;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLCTRL_LLAW_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_LLAW;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLCTRL_LLAW_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRL.reg;
+	tmp = (tmp & OSCCTRL_DFLLCTRL_LLAW) >> OSCCTRL_DFLLCTRL_LLAW_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRL_LLAW_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLCTRL.reg;
+	tmp &= ~OSCCTRL_DFLLCTRL_LLAW;
+	tmp |= value << OSCCTRL_DFLLCTRL_LLAW_Pos;
+	((Oscctrl *)hw)->DFLLCTRL.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRL_LLAW_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_LLAW;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRL_LLAW_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_LLAW;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLCTRL_USBCRM_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_USBCRM;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLCTRL_USBCRM_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRL.reg;
+	tmp = (tmp & OSCCTRL_DFLLCTRL_USBCRM) >> OSCCTRL_DFLLCTRL_USBCRM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRL_USBCRM_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLCTRL.reg;
+	tmp &= ~OSCCTRL_DFLLCTRL_USBCRM;
+	tmp |= value << OSCCTRL_DFLLCTRL_USBCRM_Pos;
+	((Oscctrl *)hw)->DFLLCTRL.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRL_USBCRM_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_USBCRM;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRL_USBCRM_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_USBCRM;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLCTRL_RUNSTDBY_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_RUNSTDBY;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLCTRL_RUNSTDBY_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRL.reg;
+	tmp = (tmp & OSCCTRL_DFLLCTRL_RUNSTDBY) >> OSCCTRL_DFLLCTRL_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRL_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLCTRL.reg;
+	tmp &= ~OSCCTRL_DFLLCTRL_RUNSTDBY;
+	tmp |= value << OSCCTRL_DFLLCTRL_RUNSTDBY_Pos;
+	((Oscctrl *)hw)->DFLLCTRL.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRL_RUNSTDBY_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_RUNSTDBY;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRL_RUNSTDBY_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_RUNSTDBY;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLCTRL_ONDEMAND_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_ONDEMAND;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLCTRL_ONDEMAND_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRL.reg;
+	tmp = (tmp & OSCCTRL_DFLLCTRL_ONDEMAND) >> OSCCTRL_DFLLCTRL_ONDEMAND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRL_ONDEMAND_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLCTRL.reg;
+	tmp &= ~OSCCTRL_DFLLCTRL_ONDEMAND;
+	tmp |= value << OSCCTRL_DFLLCTRL_ONDEMAND_Pos;
+	((Oscctrl *)hw)->DFLLCTRL.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRL_ONDEMAND_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_ONDEMAND;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRL_ONDEMAND_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_ONDEMAND;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLCTRL_CCDIS_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_CCDIS;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLCTRL_CCDIS_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRL.reg;
+	tmp = (tmp & OSCCTRL_DFLLCTRL_CCDIS) >> OSCCTRL_DFLLCTRL_CCDIS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRL_CCDIS_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLCTRL.reg;
+	tmp &= ~OSCCTRL_DFLLCTRL_CCDIS;
+	tmp |= value << OSCCTRL_DFLLCTRL_CCDIS_Pos;
+	((Oscctrl *)hw)->DFLLCTRL.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRL_CCDIS_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_CCDIS;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRL_CCDIS_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_CCDIS;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLCTRL_QLDIS_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_QLDIS;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLCTRL_QLDIS_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRL.reg;
+	tmp = (tmp & OSCCTRL_DFLLCTRL_QLDIS) >> OSCCTRL_DFLLCTRL_QLDIS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRL_QLDIS_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLCTRL.reg;
+	tmp &= ~OSCCTRL_DFLLCTRL_QLDIS;
+	tmp |= value << OSCCTRL_DFLLCTRL_QLDIS_Pos;
+	((Oscctrl *)hw)->DFLLCTRL.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRL_QLDIS_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_QLDIS;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRL_QLDIS_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_QLDIS;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLCTRL_BPLCKC_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_BPLCKC;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLCTRL_BPLCKC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRL.reg;
+	tmp = (tmp & OSCCTRL_DFLLCTRL_BPLCKC) >> OSCCTRL_DFLLCTRL_BPLCKC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRL_BPLCKC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLCTRL.reg;
+	tmp &= ~OSCCTRL_DFLLCTRL_BPLCKC;
+	tmp |= value << OSCCTRL_DFLLCTRL_BPLCKC_Pos;
+	((Oscctrl *)hw)->DFLLCTRL.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRL_BPLCKC_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_BPLCKC;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRL_BPLCKC_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_BPLCKC;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLCTRL_WAITLOCK_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_WAITLOCK;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLCTRL_WAITLOCK_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLCTRL.reg;
+	tmp = (tmp & OSCCTRL_DFLLCTRL_WAITLOCK) >> OSCCTRL_DFLLCTRL_WAITLOCK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRL_WAITLOCK_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLCTRL.reg;
+	tmp &= ~OSCCTRL_DFLLCTRL_WAITLOCK;
+	tmp |= value << OSCCTRL_DFLLCTRL_WAITLOCK_Pos;
+	((Oscctrl *)hw)->DFLLCTRL.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRL_WAITLOCK_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_WAITLOCK;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRL_WAITLOCK_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_WAITLOCK;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLCTRL_reg(const void *const hw, hri_oscctrl_dfllctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg |= mask;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllctrl_reg_t hri_oscctrl_get_DFLLCTRL_reg(const void *const          hw,
+                                                                      hri_oscctrl_dfllctrl_reg_t mask)
+{
+	uint16_t tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	tmp = ((Oscctrl *)hw)->DFLLCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLCTRL_reg(const void *const hw, hri_oscctrl_dfllctrl_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg = data;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLCTRL_reg(const void *const hw, hri_oscctrl_dfllctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg &= ~mask;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLCTRL_reg(const void *const hw, hri_oscctrl_dfllctrl_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLCTRL.reg ^= mask;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllctrl_reg_t hri_oscctrl_read_DFLLCTRL_reg(const void *const hw)
+{
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	return ((Oscctrl *)hw)->DFLLCTRL.reg;
+}
+
+static inline void hri_oscctrl_set_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg |= OSCCTRL_DFLLVAL_FINE(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_FINE_bf(const void *const         hw,
+                                                                        hri_oscctrl_dfllval_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLVAL.reg;
+	tmp = (tmp & OSCCTRL_DFLLVAL_FINE(mask)) >> OSCCTRL_DFLLVAL_FINE_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLVAL.reg;
+	tmp &= ~OSCCTRL_DFLLVAL_FINE_Msk;
+	tmp |= OSCCTRL_DFLLVAL_FINE(data);
+	((Oscctrl *)hw)->DFLLVAL.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg &= ~OSCCTRL_DFLLVAL_FINE(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg ^= OSCCTRL_DFLLVAL_FINE(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_FINE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLVAL.reg;
+	tmp = (tmp & OSCCTRL_DFLLVAL_FINE_Msk) >> OSCCTRL_DFLLVAL_FINE_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg |= OSCCTRL_DFLLVAL_COARSE(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_COARSE_bf(const void *const         hw,
+                                                                          hri_oscctrl_dfllval_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLVAL.reg;
+	tmp = (tmp & OSCCTRL_DFLLVAL_COARSE(mask)) >> OSCCTRL_DFLLVAL_COARSE_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLVAL.reg;
+	tmp &= ~OSCCTRL_DFLLVAL_COARSE_Msk;
+	tmp |= OSCCTRL_DFLLVAL_COARSE(data);
+	((Oscctrl *)hw)->DFLLVAL.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg &= ~OSCCTRL_DFLLVAL_COARSE(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg ^= OSCCTRL_DFLLVAL_COARSE(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_COARSE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLVAL.reg;
+	tmp = (tmp & OSCCTRL_DFLLVAL_COARSE_Msk) >> OSCCTRL_DFLLVAL_COARSE_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg |= OSCCTRL_DFLLVAL_DIFF(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_DIFF_bf(const void *const         hw,
+                                                                        hri_oscctrl_dfllval_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLVAL.reg;
+	tmp = (tmp & OSCCTRL_DFLLVAL_DIFF(mask)) >> OSCCTRL_DFLLVAL_DIFF_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLVAL.reg;
+	tmp &= ~OSCCTRL_DFLLVAL_DIFF_Msk;
+	tmp |= OSCCTRL_DFLLVAL_DIFF(data);
+	((Oscctrl *)hw)->DFLLVAL.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg &= ~OSCCTRL_DFLLVAL_DIFF(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg ^= OSCCTRL_DFLLVAL_DIFF(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_DIFF_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLVAL.reg;
+	tmp = (tmp & OSCCTRL_DFLLVAL_DIFF_Msk) >> OSCCTRL_DFLLVAL_DIFF_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg |= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_reg(const void *const         hw,
+                                                                    hri_oscctrl_dfllval_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLVAL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg = data;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg &= ~mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLVAL.reg ^= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_reg(const void *const hw)
+{
+	return ((Oscctrl *)hw)->DFLLVAL.reg;
+}
+
+static inline void hri_oscctrl_set_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg |= OSCCTRL_DFLLMUL_MUL(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_MUL_bf(const void *const         hw,
+                                                                       hri_oscctrl_dfllmul_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLMUL.reg;
+	tmp = (tmp & OSCCTRL_DFLLMUL_MUL(mask)) >> OSCCTRL_DFLLMUL_MUL_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLMUL.reg;
+	tmp &= ~OSCCTRL_DFLLMUL_MUL_Msk;
+	tmp |= OSCCTRL_DFLLMUL_MUL(data);
+	((Oscctrl *)hw)->DFLLMUL.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg &= ~OSCCTRL_DFLLMUL_MUL(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg ^= OSCCTRL_DFLLMUL_MUL(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_MUL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLMUL.reg;
+	tmp = (tmp & OSCCTRL_DFLLMUL_MUL_Msk) >> OSCCTRL_DFLLMUL_MUL_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg |= OSCCTRL_DFLLMUL_FSTEP(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_FSTEP_bf(const void *const         hw,
+                                                                         hri_oscctrl_dfllmul_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLMUL.reg;
+	tmp = (tmp & OSCCTRL_DFLLMUL_FSTEP(mask)) >> OSCCTRL_DFLLMUL_FSTEP_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLMUL.reg;
+	tmp &= ~OSCCTRL_DFLLMUL_FSTEP_Msk;
+	tmp |= OSCCTRL_DFLLMUL_FSTEP(data);
+	((Oscctrl *)hw)->DFLLMUL.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg &= ~OSCCTRL_DFLLMUL_FSTEP(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg ^= OSCCTRL_DFLLMUL_FSTEP(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_FSTEP_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLMUL.reg;
+	tmp = (tmp & OSCCTRL_DFLLMUL_FSTEP_Msk) >> OSCCTRL_DFLLMUL_FSTEP_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg |= OSCCTRL_DFLLMUL_CSTEP(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_CSTEP_bf(const void *const         hw,
+                                                                         hri_oscctrl_dfllmul_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLMUL.reg;
+	tmp = (tmp & OSCCTRL_DFLLMUL_CSTEP(mask)) >> OSCCTRL_DFLLMUL_CSTEP_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLMUL.reg;
+	tmp &= ~OSCCTRL_DFLLMUL_CSTEP_Msk;
+	tmp |= OSCCTRL_DFLLMUL_CSTEP(data);
+	((Oscctrl *)hw)->DFLLMUL.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg &= ~OSCCTRL_DFLLMUL_CSTEP(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg ^= OSCCTRL_DFLLMUL_CSTEP(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_CSTEP_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLMUL.reg;
+	tmp = (tmp & OSCCTRL_DFLLMUL_CSTEP_Msk) >> OSCCTRL_DFLLMUL_CSTEP_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg |= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_reg(const void *const         hw,
+                                                                    hri_oscctrl_dfllmul_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLMUL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg = data;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg &= ~mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLMUL.reg ^= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_reg(const void *const hw)
+{
+	return ((Oscctrl *)hw)->DFLLMUL.reg;
+}
+
+static inline void hri_oscctrl_set_DFLLSYNC_READREQ_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg |= OSCCTRL_DFLLSYNC_READREQ;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DFLLSYNC_READREQ_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLSYNC.reg;
+	tmp = (tmp & OSCCTRL_DFLLSYNC_READREQ) >> OSCCTRL_DFLLSYNC_READREQ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLSYNC_READREQ_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DFLLSYNC.reg;
+	tmp &= ~OSCCTRL_DFLLSYNC_READREQ;
+	tmp |= value << OSCCTRL_DFLLSYNC_READREQ_Pos;
+	((Oscctrl *)hw)->DFLLSYNC.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLSYNC_READREQ_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg &= ~OSCCTRL_DFLLSYNC_READREQ;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLSYNC_READREQ_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg ^= OSCCTRL_DFLLSYNC_READREQ;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg |= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllsync_reg_t hri_oscctrl_get_DFLLSYNC_reg(const void *const          hw,
+                                                                      hri_oscctrl_dfllsync_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DFLLSYNC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg = data;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg &= ~mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DFLLSYNC.reg ^= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dfllsync_reg_t hri_oscctrl_read_DFLLSYNC_reg(const void *const hw)
+{
+	return ((Oscctrl *)hw)->DFLLSYNC.reg;
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLA_ENABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ENABLE;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DPLLCTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLA_ENABLE) >> OSCCTRL_DPLLCTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLA_ENABLE;
+	tmp |= value << OSCCTRL_DPLLCTRLA_ENABLE_Pos;
+	((Oscctrl *)hw)->DPLLCTRLA.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLA_ENABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ENABLE;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLA_ENABLE_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ENABLE;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_RUNSTDBY;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DPLLCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLA_RUNSTDBY) >> OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY;
+	tmp |= value << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos;
+	((Oscctrl *)hw)->DPLLCTRLA.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_RUNSTDBY;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLA_ONDEMAND_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ONDEMAND;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DPLLCTRLA_ONDEMAND_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLA_ONDEMAND) >> OSCCTRL_DPLLCTRLA_ONDEMAND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLA_ONDEMAND_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLA_ONDEMAND;
+	tmp |= value << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos;
+	((Oscctrl *)hw)->DPLLCTRLA.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLA_ONDEMAND_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ONDEMAND;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLA_ONDEMAND_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ONDEMAND;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLA.reg |= mask;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrl_get_DPLLCTRLA_reg(const void *const           hw,
+                                                                        hri_oscctrl_dpllctrla_reg_t mask)
+{
+	uint8_t tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLA.reg = data;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLA.reg &= ~mask;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLA.reg ^= mask;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrl_read_DPLLCTRLA_reg(const void *const hw)
+{
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE);
+	return ((Oscctrl *)hw)->DPLLCTRLA.reg;
+}
+
+static inline void hri_oscctrl_set_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDR(mask);
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_get_DPLLRATIO_LDR_bf(const void *const           hw,
+                                                                           hri_oscctrl_dpllratio_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DPLLRATIO.reg;
+	tmp = (tmp & OSCCTRL_DPLLRATIO_LDR(mask)) >> OSCCTRL_DPLLRATIO_LDR_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DPLLRATIO.reg;
+	tmp &= ~OSCCTRL_DPLLRATIO_LDR_Msk;
+	tmp |= OSCCTRL_DPLLRATIO_LDR(data);
+	((Oscctrl *)hw)->DPLLRATIO.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDR(mask);
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDR(mask);
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_LDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DPLLRATIO.reg;
+	tmp = (tmp & OSCCTRL_DPLLRATIO_LDR_Msk) >> OSCCTRL_DPLLRATIO_LDR_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDRFRAC(mask);
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_get_DPLLRATIO_LDRFRAC_bf(const void *const           hw,
+                                                                               hri_oscctrl_dpllratio_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DPLLRATIO.reg;
+	tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC(mask)) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DPLLRATIO.reg;
+	tmp &= ~OSCCTRL_DPLLRATIO_LDRFRAC_Msk;
+	tmp |= OSCCTRL_DPLLRATIO_LDRFRAC(data);
+	((Oscctrl *)hw)->DPLLRATIO.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDRFRAC(mask);
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDRFRAC(mask);
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_LDRFRAC_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DPLLRATIO.reg;
+	tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC_Msk) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLRATIO.reg |= mask;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_get_DPLLRATIO_reg(const void *const           hw,
+                                                                        hri_oscctrl_dpllratio_reg_t mask)
+{
+	uint32_t tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	tmp = ((Oscctrl *)hw)->DPLLRATIO.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLRATIO.reg = data;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLRATIO.reg &= ~mask;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLRATIO.reg ^= mask;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_reg(const void *const hw)
+{
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	return ((Oscctrl *)hw)->DPLLRATIO.reg;
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLB_LPEN_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LPEN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DPLLCTRLB_LPEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_LPEN) >> OSCCTRL_DPLLCTRLB_LPEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLB_LPEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_LPEN;
+	tmp |= value << OSCCTRL_DPLLCTRLB_LPEN_Pos;
+	((Oscctrl *)hw)->DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLB_LPEN_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LPEN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLB_LPEN_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LPEN;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLB_WUF_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_WUF;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DPLLCTRLB_WUF_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_WUF) >> OSCCTRL_DPLLCTRLB_WUF_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLB_WUF_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_WUF;
+	tmp |= value << OSCCTRL_DPLLCTRLB_WUF_Pos;
+	((Oscctrl *)hw)->DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLB_WUF_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_WUF;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLB_WUF_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_WUF;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLB_LBYPASS_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LBYPASS;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_oscctrl_get_DPLLCTRLB_LBYPASS_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_LBYPASS) >> OSCCTRL_DPLLCTRLB_LBYPASS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLB_LBYPASS_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_LBYPASS;
+	tmp |= value << OSCCTRL_DPLLCTRLB_LBYPASS_Pos;
+	((Oscctrl *)hw)->DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLB_LBYPASS_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LBYPASS;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLB_LBYPASS_bit(const void *const hw)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LBYPASS;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_FILTER(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_get_DPLLCTRLB_FILTER_bf(const void *const           hw,
+                                                                              hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER(mask)) >> OSCCTRL_DPLLCTRLB_FILTER_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_FILTER_Msk;
+	tmp |= OSCCTRL_DPLLCTRLB_FILTER(data);
+	((Oscctrl *)hw)->DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_FILTER(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_FILTER(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_FILTER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER_Msk) >> OSCCTRL_DPLLCTRLB_FILTER_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_REFCLK(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_get_DPLLCTRLB_REFCLK_bf(const void *const           hw,
+                                                                              hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK(mask)) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_REFCLK_Msk;
+	tmp |= OSCCTRL_DPLLCTRLB_REFCLK(data);
+	((Oscctrl *)hw)->DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_REFCLK(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_REFCLK(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_REFCLK_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK_Msk) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LTIME(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_get_DPLLCTRLB_LTIME_bf(const void *const           hw,
+                                                                             hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME(mask)) >> OSCCTRL_DPLLCTRLB_LTIME_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_LTIME_Msk;
+	tmp |= OSCCTRL_DPLLCTRLB_LTIME(data);
+	((Oscctrl *)hw)->DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LTIME(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LTIME(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_LTIME_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME_Msk) >> OSCCTRL_DPLLCTRLB_LTIME_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DIV(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_get_DPLLCTRLB_DIV_bf(const void *const           hw,
+                                                                           hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV(mask)) >> OSCCTRL_DPLLCTRLB_DIV_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data)
+{
+	uint32_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg;
+	tmp &= ~OSCCTRL_DPLLCTRLB_DIV_Msk;
+	tmp |= OSCCTRL_DPLLCTRLB_DIV(data);
+	((Oscctrl *)hw)->DPLLCTRLB.reg = tmp;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DIV(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DIV(mask);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_DIV_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg;
+	tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV_Msk) >> OSCCTRL_DPLLCTRLB_DIV_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLB.reg |= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_get_DPLLCTRLB_reg(const void *const           hw,
+                                                                        hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLB.reg = data;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLB.reg &= ~mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLCTRLB.reg ^= mask;
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_reg(const void *const hw)
+{
+	return ((Oscctrl *)hw)->DPLLCTRLB.reg;
+}
+
+static inline void hri_oscctrl_set_DPLLPRESC_PRESC_bf(const void *const hw, hri_oscctrl_dpllpresc_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLPRESC.reg |= OSCCTRL_DPLLPRESC_PRESC(mask);
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllpresc_reg_t hri_oscctrl_get_DPLLPRESC_PRESC_bf(const void *const           hw,
+                                                                             hri_oscctrl_dpllpresc_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DPLLPRESC.reg;
+	tmp = (tmp & OSCCTRL_DPLLPRESC_PRESC(mask)) >> OSCCTRL_DPLLPRESC_PRESC_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLPRESC_PRESC_bf(const void *const hw, hri_oscctrl_dpllpresc_reg_t data)
+{
+	uint8_t tmp;
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	tmp = ((Oscctrl *)hw)->DPLLPRESC.reg;
+	tmp &= ~OSCCTRL_DPLLPRESC_PRESC_Msk;
+	tmp |= OSCCTRL_DPLLPRESC_PRESC(data);
+	((Oscctrl *)hw)->DPLLPRESC.reg = tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLPRESC_PRESC_bf(const void *const hw, hri_oscctrl_dpllpresc_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLPRESC.reg &= ~OSCCTRL_DPLLPRESC_PRESC(mask);
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLPRESC_PRESC_bf(const void *const hw, hri_oscctrl_dpllpresc_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLPRESC.reg ^= OSCCTRL_DPLLPRESC_PRESC(mask);
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllpresc_reg_t hri_oscctrl_read_DPLLPRESC_PRESC_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Oscctrl *)hw)->DPLLPRESC.reg;
+	tmp = (tmp & OSCCTRL_DPLLPRESC_PRESC_Msk) >> OSCCTRL_DPLLPRESC_PRESC_Pos;
+	return tmp;
+}
+
+static inline void hri_oscctrl_set_DPLLPRESC_reg(const void *const hw, hri_oscctrl_dpllpresc_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLPRESC.reg |= mask;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllpresc_reg_t hri_oscctrl_get_DPLLPRESC_reg(const void *const           hw,
+                                                                        hri_oscctrl_dpllpresc_reg_t mask)
+{
+	uint8_t tmp;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	tmp = ((Oscctrl *)hw)->DPLLPRESC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_oscctrl_write_DPLLPRESC_reg(const void *const hw, hri_oscctrl_dpllpresc_reg_t data)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLPRESC.reg = data;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_clear_DPLLPRESC_reg(const void *const hw, hri_oscctrl_dpllpresc_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLPRESC.reg &= ~mask;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_oscctrl_toggle_DPLLPRESC_reg(const void *const hw, hri_oscctrl_dpllpresc_reg_t mask)
+{
+	OSCCTRL_CRITICAL_SECTION_ENTER();
+	((Oscctrl *)hw)->DPLLPRESC.reg ^= mask;
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	OSCCTRL_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_oscctrl_dpllpresc_reg_t hri_oscctrl_read_DPLLPRESC_reg(const void *const hw)
+{
+	hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK);
+	return ((Oscctrl *)hw)->DPLLPRESC.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_OSCCTRL_L22_H_INCLUDED */
+#endif /* _SAML22_OSCCTRL_COMPONENT_ */
diff --git a/watch-library/hardware/hri/hri_pac_l22.h b/watch-library/hardware/hri/hri_pac_l22.h
new file mode 100644
index 00000000..488c7079
--- /dev/null
+++ b/watch-library/hardware/hri/hri_pac_l22.h
@@ -0,0 +1,1076 @@
+/**
+ * \file
+ *
+ * \brief SAM PAC
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_PAC_COMPONENT_
+#ifndef _HRI_PAC_L22_H_INCLUDED_
+#define _HRI_PAC_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_PAC_CRITICAL_SECTIONS)
+#define PAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define PAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define PAC_CRITICAL_SECTION_ENTER()
+#define PAC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_pac_intflaga_reg_t;
+typedef uint32_t hri_pac_intflagahb_reg_t;
+typedef uint32_t hri_pac_intflagb_reg_t;
+typedef uint32_t hri_pac_intflagc_reg_t;
+typedef uint32_t hri_pac_statusa_reg_t;
+typedef uint32_t hri_pac_statusb_reg_t;
+typedef uint32_t hri_pac_statusc_reg_t;
+typedef uint32_t hri_pac_wrctrl_reg_t;
+typedef uint8_t  hri_pac_evctrl_reg_t;
+typedef uint8_t  hri_pac_intenset_reg_t;
+
+static inline bool hri_pac_get_INTFLAGAHB_FLASH_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_FLASH) >> PAC_INTFLAGAHB_FLASH_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_FLASH_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_FLASH;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_HSRAMCM0P_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HSRAMCM0P) >> PAC_INTFLAGAHB_HSRAMCM0P_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_HSRAMCM0P_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HSRAMCM0P;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_HSRAMDSU_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HSRAMDSU) >> PAC_INTFLAGAHB_HSRAMDSU_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_HSRAMDSU_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HSRAMDSU;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_HPB1_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB1) >> PAC_INTFLAGAHB_HPB1_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_HPB1_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB1;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_HPB0_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB0) >> PAC_INTFLAGAHB_HPB0_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_HPB0_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB0;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_HPB2_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB2) >> PAC_INTFLAGAHB_HPB2_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_HPB2_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB2;
+}
+
+static inline bool hri_pac_get_INTFLAGAHB_HSRAMDMAC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HSRAMDMAC) >> PAC_INTFLAGAHB_HSRAMDMAC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_HSRAMDMAC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HSRAMDMAC;
+}
+
+static inline hri_pac_intflagahb_reg_t hri_pac_get_INTFLAGAHB_reg(const void *const hw, hri_pac_intflagahb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->INTFLAGAHB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pac_intflagahb_reg_t hri_pac_read_INTFLAGAHB_reg(const void *const hw)
+{
+	return ((Pac *)hw)->INTFLAGAHB.reg;
+}
+
+static inline void hri_pac_clear_INTFLAGAHB_reg(const void *const hw, hri_pac_intflagahb_reg_t mask)
+{
+	((Pac *)hw)->INTFLAGAHB.reg = mask;
+}
+
+static inline bool hri_pac_get_INTFLAGA_PAC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_PAC) >> PAC_INTFLAGA_PAC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_PAC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_PAC;
+}
+
+static inline bool hri_pac_get_INTFLAGA_PM_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_PM) >> PAC_INTFLAGA_PM_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_PM_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_PM;
+}
+
+static inline bool hri_pac_get_INTFLAGA_MCLK_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_MCLK) >> PAC_INTFLAGA_MCLK_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_MCLK_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_MCLK;
+}
+
+static inline bool hri_pac_get_INTFLAGA_RSTC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_RSTC) >> PAC_INTFLAGA_RSTC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_RSTC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_RSTC;
+}
+
+static inline bool hri_pac_get_INTFLAGA_OSCCTRL_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_OSCCTRL) >> PAC_INTFLAGA_OSCCTRL_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_OSCCTRL_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_OSCCTRL;
+}
+
+static inline bool hri_pac_get_INTFLAGA_OSC32KCTRL_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_OSC32KCTRL) >> PAC_INTFLAGA_OSC32KCTRL_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_OSC32KCTRL_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_OSC32KCTRL;
+}
+
+static inline bool hri_pac_get_INTFLAGA_SUPC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_SUPC) >> PAC_INTFLAGA_SUPC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_SUPC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_SUPC;
+}
+
+static inline bool hri_pac_get_INTFLAGA_GCLK_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_GCLK) >> PAC_INTFLAGA_GCLK_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_GCLK_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_GCLK;
+}
+
+static inline bool hri_pac_get_INTFLAGA_WDT_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_WDT) >> PAC_INTFLAGA_WDT_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_WDT_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_WDT;
+}
+
+static inline bool hri_pac_get_INTFLAGA_RTC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_RTC) >> PAC_INTFLAGA_RTC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_RTC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_RTC;
+}
+
+static inline bool hri_pac_get_INTFLAGA_EIC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_EIC) >> PAC_INTFLAGA_EIC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_EIC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_EIC;
+}
+
+static inline bool hri_pac_get_INTFLAGA_FREQM_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_FREQM) >> PAC_INTFLAGA_FREQM_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGA_FREQM_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_FREQM;
+}
+
+static inline hri_pac_intflaga_reg_t hri_pac_get_INTFLAGA_reg(const void *const hw, hri_pac_intflaga_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->INTFLAGA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pac_intflaga_reg_t hri_pac_read_INTFLAGA_reg(const void *const hw)
+{
+	return ((Pac *)hw)->INTFLAGA.reg;
+}
+
+static inline void hri_pac_clear_INTFLAGA_reg(const void *const hw, hri_pac_intflaga_reg_t mask)
+{
+	((Pac *)hw)->INTFLAGA.reg = mask;
+}
+
+static inline bool hri_pac_get_INTFLAGB_USB_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_USB) >> PAC_INTFLAGB_USB_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_USB_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_USB;
+}
+
+static inline bool hri_pac_get_INTFLAGB_DSU_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_DSU) >> PAC_INTFLAGB_DSU_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_DSU_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_DSU;
+}
+
+static inline bool hri_pac_get_INTFLAGB_NVMCTRL_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_NVMCTRL) >> PAC_INTFLAGB_NVMCTRL_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_NVMCTRL_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_NVMCTRL;
+}
+
+static inline bool hri_pac_get_INTFLAGB_PORT_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_PORT) >> PAC_INTFLAGB_PORT_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_PORT_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_PORT;
+}
+
+static inline bool hri_pac_get_INTFLAGB_DMAC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_DMAC) >> PAC_INTFLAGB_DMAC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_DMAC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_DMAC;
+}
+
+static inline bool hri_pac_get_INTFLAGB_MTB_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_MTB) >> PAC_INTFLAGB_MTB_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGB_MTB_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_MTB;
+}
+
+static inline hri_pac_intflagb_reg_t hri_pac_get_INTFLAGB_reg(const void *const hw, hri_pac_intflagb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->INTFLAGB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pac_intflagb_reg_t hri_pac_read_INTFLAGB_reg(const void *const hw)
+{
+	return ((Pac *)hw)->INTFLAGB.reg;
+}
+
+static inline void hri_pac_clear_INTFLAGB_reg(const void *const hw, hri_pac_intflagb_reg_t mask)
+{
+	((Pac *)hw)->INTFLAGB.reg = mask;
+}
+
+static inline bool hri_pac_get_INTFLAGC_EVSYS_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_EVSYS) >> PAC_INTFLAGC_EVSYS_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_EVSYS_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_EVSYS;
+}
+
+static inline bool hri_pac_get_INTFLAGC_SERCOM0_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_SERCOM0) >> PAC_INTFLAGC_SERCOM0_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_SERCOM0_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_SERCOM0;
+}
+
+static inline bool hri_pac_get_INTFLAGC_SERCOM1_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_SERCOM1) >> PAC_INTFLAGC_SERCOM1_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_SERCOM1_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_SERCOM1;
+}
+
+static inline bool hri_pac_get_INTFLAGC_SERCOM2_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_SERCOM2) >> PAC_INTFLAGC_SERCOM2_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_SERCOM2_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_SERCOM2;
+}
+
+static inline bool hri_pac_get_INTFLAGC_SERCOM3_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_SERCOM3) >> PAC_INTFLAGC_SERCOM3_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_SERCOM3_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_SERCOM3;
+}
+
+static inline bool hri_pac_get_INTFLAGC_SERCOM4_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_SERCOM4) >> PAC_INTFLAGC_SERCOM4_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_SERCOM4_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_SERCOM4;
+}
+
+static inline bool hri_pac_get_INTFLAGC_SERCOM5_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_SERCOM5) >> PAC_INTFLAGC_SERCOM5_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_SERCOM5_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_SERCOM5;
+}
+
+static inline bool hri_pac_get_INTFLAGC_TCC0_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TCC0) >> PAC_INTFLAGC_TCC0_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_TCC0_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TCC0;
+}
+
+static inline bool hri_pac_get_INTFLAGC_TC0_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC0) >> PAC_INTFLAGC_TC0_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_TC0_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC0;
+}
+
+static inline bool hri_pac_get_INTFLAGC_TC1_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC1) >> PAC_INTFLAGC_TC1_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_TC1_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC1;
+}
+
+static inline bool hri_pac_get_INTFLAGC_TC2_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC2) >> PAC_INTFLAGC_TC2_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_TC2_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC2;
+}
+
+static inline bool hri_pac_get_INTFLAGC_TC3_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC3) >> PAC_INTFLAGC_TC3_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_TC3_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC3;
+}
+
+static inline bool hri_pac_get_INTFLAGC_ADC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_ADC) >> PAC_INTFLAGC_ADC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_ADC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_ADC;
+}
+
+static inline bool hri_pac_get_INTFLAGC_AC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_AC) >> PAC_INTFLAGC_AC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_AC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_AC;
+}
+
+static inline bool hri_pac_get_INTFLAGC_PTC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_PTC) >> PAC_INTFLAGC_PTC_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_PTC_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_PTC;
+}
+
+static inline bool hri_pac_get_INTFLAGC_SLCD_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_SLCD) >> PAC_INTFLAGC_SLCD_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_SLCD_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_SLCD;
+}
+
+static inline bool hri_pac_get_INTFLAGC_AES_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_AES) >> PAC_INTFLAGC_AES_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_AES_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_AES;
+}
+
+static inline bool hri_pac_get_INTFLAGC_TRNG_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TRNG) >> PAC_INTFLAGC_TRNG_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_TRNG_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TRNG;
+}
+
+static inline bool hri_pac_get_INTFLAGC_CCL_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_CCL) >> PAC_INTFLAGC_CCL_Pos;
+}
+
+static inline void hri_pac_clear_INTFLAGC_CCL_bit(const void *const hw)
+{
+	((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_CCL;
+}
+
+static inline hri_pac_intflagc_reg_t hri_pac_get_INTFLAGC_reg(const void *const hw, hri_pac_intflagc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->INTFLAGC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pac_intflagc_reg_t hri_pac_read_INTFLAGC_reg(const void *const hw)
+{
+	return ((Pac *)hw)->INTFLAGC.reg;
+}
+
+static inline void hri_pac_clear_INTFLAGC_reg(const void *const hw, hri_pac_intflagc_reg_t mask)
+{
+	((Pac *)hw)->INTFLAGC.reg = mask;
+}
+
+static inline void hri_pac_set_INTEN_ERR_bit(const void *const hw)
+{
+	((Pac *)hw)->INTENSET.reg = PAC_INTENSET_ERR;
+}
+
+static inline bool hri_pac_get_INTEN_ERR_bit(const void *const hw)
+{
+	return (((Pac *)hw)->INTENSET.reg & PAC_INTENSET_ERR) >> PAC_INTENSET_ERR_Pos;
+}
+
+static inline void hri_pac_write_INTEN_ERR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Pac *)hw)->INTENCLR.reg = PAC_INTENSET_ERR;
+	} else {
+		((Pac *)hw)->INTENSET.reg = PAC_INTENSET_ERR;
+	}
+}
+
+static inline void hri_pac_clear_INTEN_ERR_bit(const void *const hw)
+{
+	((Pac *)hw)->INTENCLR.reg = PAC_INTENSET_ERR;
+}
+
+static inline void hri_pac_set_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask)
+{
+	((Pac *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_pac_intenset_reg_t hri_pac_get_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pac *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pac_intenset_reg_t hri_pac_read_INTEN_reg(const void *const hw)
+{
+	return ((Pac *)hw)->INTENSET.reg;
+}
+
+static inline void hri_pac_write_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t data)
+{
+	((Pac *)hw)->INTENSET.reg = data;
+	((Pac *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_pac_clear_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask)
+{
+	((Pac *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_pac_get_STATUSA_PAC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_PAC) >> PAC_STATUSA_PAC_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_PM_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_PM) >> PAC_STATUSA_PM_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_MCLK_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_MCLK) >> PAC_STATUSA_MCLK_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_RSTC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_RSTC) >> PAC_STATUSA_RSTC_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_OSCCTRL_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_OSCCTRL) >> PAC_STATUSA_OSCCTRL_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_OSC32KCTRL_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_OSC32KCTRL) >> PAC_STATUSA_OSC32KCTRL_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_SUPC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_SUPC) >> PAC_STATUSA_SUPC_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_GCLK_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_GCLK) >> PAC_STATUSA_GCLK_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_WDT_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_WDT) >> PAC_STATUSA_WDT_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_RTC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_RTC) >> PAC_STATUSA_RTC_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_EIC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_EIC) >> PAC_STATUSA_EIC_Pos;
+}
+
+static inline bool hri_pac_get_STATUSA_FREQM_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_FREQM) >> PAC_STATUSA_FREQM_Pos;
+}
+
+static inline hri_pac_statusa_reg_t hri_pac_get_STATUSA_reg(const void *const hw, hri_pac_statusa_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->STATUSA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pac_statusa_reg_t hri_pac_read_STATUSA_reg(const void *const hw)
+{
+	return ((Pac *)hw)->STATUSA.reg;
+}
+
+static inline bool hri_pac_get_STATUSB_USB_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_USB) >> PAC_STATUSB_USB_Pos;
+}
+
+static inline bool hri_pac_get_STATUSB_DSU_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_DSU) >> PAC_STATUSB_DSU_Pos;
+}
+
+static inline bool hri_pac_get_STATUSB_NVMCTRL_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_NVMCTRL) >> PAC_STATUSB_NVMCTRL_Pos;
+}
+
+static inline bool hri_pac_get_STATUSB_PORT_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_PORT) >> PAC_STATUSB_PORT_Pos;
+}
+
+static inline bool hri_pac_get_STATUSB_DMAC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_DMAC) >> PAC_STATUSB_DMAC_Pos;
+}
+
+static inline bool hri_pac_get_STATUSB_MTB_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_MTB) >> PAC_STATUSB_MTB_Pos;
+}
+
+static inline hri_pac_statusb_reg_t hri_pac_get_STATUSB_reg(const void *const hw, hri_pac_statusb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->STATUSB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pac_statusb_reg_t hri_pac_read_STATUSB_reg(const void *const hw)
+{
+	return ((Pac *)hw)->STATUSB.reg;
+}
+
+static inline bool hri_pac_get_STATUSC_EVSYS_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_EVSYS) >> PAC_STATUSC_EVSYS_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_SERCOM0_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_SERCOM0) >> PAC_STATUSC_SERCOM0_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_SERCOM1_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_SERCOM1) >> PAC_STATUSC_SERCOM1_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_SERCOM2_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_SERCOM2) >> PAC_STATUSC_SERCOM2_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_SERCOM3_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_SERCOM3) >> PAC_STATUSC_SERCOM3_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_SERCOM4_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_SERCOM4) >> PAC_STATUSC_SERCOM4_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_SERCOM5_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_SERCOM5) >> PAC_STATUSC_SERCOM5_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_TCC0_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TCC0) >> PAC_STATUSC_TCC0_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_TC0_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC0) >> PAC_STATUSC_TC0_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_TC1_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC1) >> PAC_STATUSC_TC1_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_TC2_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC2) >> PAC_STATUSC_TC2_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_TC3_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC3) >> PAC_STATUSC_TC3_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_ADC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_ADC) >> PAC_STATUSC_ADC_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_AC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_AC) >> PAC_STATUSC_AC_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_PTC_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_PTC) >> PAC_STATUSC_PTC_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_SLCD_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_SLCD) >> PAC_STATUSC_SLCD_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_AES_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_AES) >> PAC_STATUSC_AES_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_TRNG_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TRNG) >> PAC_STATUSC_TRNG_Pos;
+}
+
+static inline bool hri_pac_get_STATUSC_CCL_bit(const void *const hw)
+{
+	return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_CCL) >> PAC_STATUSC_CCL_Pos;
+}
+
+static inline hri_pac_statusc_reg_t hri_pac_get_STATUSC_reg(const void *const hw, hri_pac_statusc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->STATUSC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pac_statusc_reg_t hri_pac_read_STATUSC_reg(const void *const hw)
+{
+	return ((Pac *)hw)->STATUSC.reg;
+}
+
+static inline void hri_pac_set_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->WRCTRL.reg |= PAC_WRCTRL_PERID(mask);
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->WRCTRL.reg;
+	tmp = (tmp & PAC_WRCTRL_PERID(mask)) >> PAC_WRCTRL_PERID_Pos;
+	return tmp;
+}
+
+static inline void hri_pac_write_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t data)
+{
+	uint32_t tmp;
+	PAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pac *)hw)->WRCTRL.reg;
+	tmp &= ~PAC_WRCTRL_PERID_Msk;
+	tmp |= PAC_WRCTRL_PERID(data);
+	((Pac *)hw)->WRCTRL.reg = tmp;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pac_clear_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->WRCTRL.reg &= ~PAC_WRCTRL_PERID(mask);
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pac_toggle_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->WRCTRL.reg ^= PAC_WRCTRL_PERID(mask);
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_PERID_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->WRCTRL.reg;
+	tmp = (tmp & PAC_WRCTRL_PERID_Msk) >> PAC_WRCTRL_PERID_Pos;
+	return tmp;
+}
+
+static inline void hri_pac_set_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->WRCTRL.reg |= PAC_WRCTRL_KEY(mask);
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->WRCTRL.reg;
+	tmp = (tmp & PAC_WRCTRL_KEY(mask)) >> PAC_WRCTRL_KEY_Pos;
+	return tmp;
+}
+
+static inline void hri_pac_write_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t data)
+{
+	uint32_t tmp;
+	PAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pac *)hw)->WRCTRL.reg;
+	tmp &= ~PAC_WRCTRL_KEY_Msk;
+	tmp |= PAC_WRCTRL_KEY(data);
+	((Pac *)hw)->WRCTRL.reg = tmp;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pac_clear_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->WRCTRL.reg &= ~PAC_WRCTRL_KEY(mask);
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pac_toggle_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->WRCTRL.reg ^= PAC_WRCTRL_KEY(mask);
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_KEY_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->WRCTRL.reg;
+	tmp = (tmp & PAC_WRCTRL_KEY_Msk) >> PAC_WRCTRL_KEY_Pos;
+	return tmp;
+}
+
+static inline void hri_pac_set_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->WRCTRL.reg |= mask;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Pac *)hw)->WRCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pac_write_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t data)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->WRCTRL.reg = data;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pac_clear_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->WRCTRL.reg &= ~mask;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pac_toggle_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->WRCTRL.reg ^= mask;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_reg(const void *const hw)
+{
+	return ((Pac *)hw)->WRCTRL.reg;
+}
+
+static inline void hri_pac_set_EVCTRL_ERREO_bit(const void *const hw)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->EVCTRL.reg |= PAC_EVCTRL_ERREO;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pac_get_EVCTRL_ERREO_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pac *)hw)->EVCTRL.reg;
+	tmp = (tmp & PAC_EVCTRL_ERREO) >> PAC_EVCTRL_ERREO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pac_write_EVCTRL_ERREO_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	PAC_CRITICAL_SECTION_ENTER();
+	tmp = ((Pac *)hw)->EVCTRL.reg;
+	tmp &= ~PAC_EVCTRL_ERREO;
+	tmp |= value << PAC_EVCTRL_ERREO_Pos;
+	((Pac *)hw)->EVCTRL.reg = tmp;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pac_clear_EVCTRL_ERREO_bit(const void *const hw)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->EVCTRL.reg &= ~PAC_EVCTRL_ERREO;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pac_toggle_EVCTRL_ERREO_bit(const void *const hw)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->EVCTRL.reg ^= PAC_EVCTRL_ERREO;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pac_set_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->EVCTRL.reg |= mask;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pac_evctrl_reg_t hri_pac_get_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pac *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pac_write_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t data)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->EVCTRL.reg = data;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pac_clear_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->EVCTRL.reg &= ~mask;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pac_toggle_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask)
+{
+	PAC_CRITICAL_SECTION_ENTER();
+	((Pac *)hw)->EVCTRL.reg ^= mask;
+	PAC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pac_evctrl_reg_t hri_pac_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Pac *)hw)->EVCTRL.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_PAC_L22_H_INCLUDED */
+#endif /* _SAML22_PAC_COMPONENT_ */
diff --git a/watch-library/hardware/hri/hri_pm_l22.h b/watch-library/hardware/hri/hri_pm_l22.h
new file mode 100644
index 00000000..d56d3cf7
--- /dev/null
+++ b/watch-library/hardware/hri/hri_pm_l22.h
@@ -0,0 +1,592 @@
+/**
+ * \file
+ *
+ * \brief SAM PM
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_PM_COMPONENT_
+#ifndef _HRI_PM_L22_H_INCLUDED_
+#define _HRI_PM_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_PM_CRITICAL_SECTIONS)
+#define PM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define PM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define PM_CRITICAL_SECTION_ENTER()
+#define PM_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_pm_stdbycfg_reg_t;
+typedef uint8_t  hri_pm_ctrla_reg_t;
+typedef uint8_t  hri_pm_intenset_reg_t;
+typedef uint8_t  hri_pm_intflag_reg_t;
+typedef uint8_t  hri_pm_plcfg_reg_t;
+typedef uint8_t  hri_pm_sleepcfg_reg_t;
+
+static inline bool hri_pm_get_INTFLAG_PLRDY_bit(const void *const hw)
+{
+	return (((Pm *)hw)->INTFLAG.reg & PM_INTFLAG_PLRDY) >> PM_INTFLAG_PLRDY_Pos;
+}
+
+static inline void hri_pm_clear_INTFLAG_PLRDY_bit(const void *const hw)
+{
+	((Pm *)hw)->INTFLAG.reg = PM_INTFLAG_PLRDY;
+}
+
+static inline bool hri_pm_get_interrupt_PLRDY_bit(const void *const hw)
+{
+	return (((Pm *)hw)->INTFLAG.reg & PM_INTFLAG_PLRDY) >> PM_INTFLAG_PLRDY_Pos;
+}
+
+static inline void hri_pm_clear_interrupt_PLRDY_bit(const void *const hw)
+{
+	((Pm *)hw)->INTFLAG.reg = PM_INTFLAG_PLRDY;
+}
+
+static inline hri_pm_intflag_reg_t hri_pm_get_INTFLAG_reg(const void *const hw, hri_pm_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pm_intflag_reg_t hri_pm_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Pm *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_pm_clear_INTFLAG_reg(const void *const hw, hri_pm_intflag_reg_t mask)
+{
+	((Pm *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_pm_set_INTEN_PLRDY_bit(const void *const hw)
+{
+	((Pm *)hw)->INTENSET.reg = PM_INTENSET_PLRDY;
+}
+
+static inline bool hri_pm_get_INTEN_PLRDY_bit(const void *const hw)
+{
+	return (((Pm *)hw)->INTENSET.reg & PM_INTENSET_PLRDY) >> PM_INTENSET_PLRDY_Pos;
+}
+
+static inline void hri_pm_write_INTEN_PLRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Pm *)hw)->INTENCLR.reg = PM_INTENSET_PLRDY;
+	} else {
+		((Pm *)hw)->INTENSET.reg = PM_INTENSET_PLRDY;
+	}
+}
+
+static inline void hri_pm_clear_INTEN_PLRDY_bit(const void *const hw)
+{
+	((Pm *)hw)->INTENCLR.reg = PM_INTENSET_PLRDY;
+}
+
+static inline void hri_pm_set_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask)
+{
+	((Pm *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_pm_intenset_reg_t hri_pm_get_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_pm_intenset_reg_t hri_pm_read_INTEN_reg(const void *const hw)
+{
+	return ((Pm *)hw)->INTENSET.reg;
+}
+
+static inline void hri_pm_write_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t data)
+{
+	((Pm *)hw)->INTENSET.reg = data;
+	((Pm *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_pm_clear_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask)
+{
+	((Pm *)hw)->INTENCLR.reg = mask;
+}
+
+static inline void hri_pm_set_CTRLA_IORET_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->CTRLA.reg |= PM_CTRLA_IORET;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pm_get_CTRLA_IORET_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->CTRLA.reg;
+	tmp = (tmp & PM_CTRLA_IORET) >> PM_CTRLA_IORET_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pm_write_CTRLA_IORET_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->CTRLA.reg;
+	tmp &= ~PM_CTRLA_IORET;
+	tmp |= value << PM_CTRLA_IORET_Pos;
+	((Pm *)hw)->CTRLA.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_CTRLA_IORET_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->CTRLA.reg &= ~PM_CTRLA_IORET;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_CTRLA_IORET_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->CTRLA.reg ^= PM_CTRLA_IORET;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_set_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->CTRLA.reg |= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_ctrla_reg_t hri_pm_get_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pm_write_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t data)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->CTRLA.reg = data;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->CTRLA.reg &= ~mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->CTRLA.reg ^= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_ctrla_reg_t hri_pm_read_CTRLA_reg(const void *const hw)
+{
+	return ((Pm *)hw)->CTRLA.reg;
+}
+
+static inline void hri_pm_set_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->SLEEPCFG.reg |= PM_SLEEPCFG_SLEEPMODE(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_sleepcfg_reg_t hri_pm_get_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->SLEEPCFG.reg;
+	tmp = (tmp & PM_SLEEPCFG_SLEEPMODE(mask)) >> PM_SLEEPCFG_SLEEPMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_write_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t data)
+{
+	uint8_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->SLEEPCFG.reg;
+	tmp &= ~PM_SLEEPCFG_SLEEPMODE_Msk;
+	tmp |= PM_SLEEPCFG_SLEEPMODE(data);
+	((Pm *)hw)->SLEEPCFG.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->SLEEPCFG.reg &= ~PM_SLEEPCFG_SLEEPMODE(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->SLEEPCFG.reg ^= PM_SLEEPCFG_SLEEPMODE(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_sleepcfg_reg_t hri_pm_read_SLEEPCFG_SLEEPMODE_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->SLEEPCFG.reg;
+	tmp = (tmp & PM_SLEEPCFG_SLEEPMODE_Msk) >> PM_SLEEPCFG_SLEEPMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_set_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->SLEEPCFG.reg |= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_sleepcfg_reg_t hri_pm_get_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->SLEEPCFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pm_write_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t data)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->SLEEPCFG.reg = data;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->SLEEPCFG.reg &= ~mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->SLEEPCFG.reg ^= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_sleepcfg_reg_t hri_pm_read_SLEEPCFG_reg(const void *const hw)
+{
+	return ((Pm *)hw)->SLEEPCFG.reg;
+}
+
+static inline void hri_pm_set_PLCFG_PLDIS_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->PLCFG.reg |= PM_PLCFG_PLDIS;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_pm_get_PLCFG_PLDIS_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->PLCFG.reg;
+	tmp = (tmp & PM_PLCFG_PLDIS) >> PM_PLCFG_PLDIS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_pm_write_PLCFG_PLDIS_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->PLCFG.reg;
+	tmp &= ~PM_PLCFG_PLDIS;
+	tmp |= value << PM_PLCFG_PLDIS_Pos;
+	((Pm *)hw)->PLCFG.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_PLCFG_PLDIS_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->PLCFG.reg &= ~PM_PLCFG_PLDIS;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_PLCFG_PLDIS_bit(const void *const hw)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->PLCFG.reg ^= PM_PLCFG_PLDIS;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_set_PLCFG_PLSEL_bf(const void *const hw, hri_pm_plcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->PLCFG.reg |= PM_PLCFG_PLSEL(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_plcfg_reg_t hri_pm_get_PLCFG_PLSEL_bf(const void *const hw, hri_pm_plcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->PLCFG.reg;
+	tmp = (tmp & PM_PLCFG_PLSEL(mask)) >> PM_PLCFG_PLSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_write_PLCFG_PLSEL_bf(const void *const hw, hri_pm_plcfg_reg_t data)
+{
+	uint8_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->PLCFG.reg;
+	tmp &= ~PM_PLCFG_PLSEL_Msk;
+	tmp |= PM_PLCFG_PLSEL(data);
+	((Pm *)hw)->PLCFG.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_PLCFG_PLSEL_bf(const void *const hw, hri_pm_plcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->PLCFG.reg &= ~PM_PLCFG_PLSEL(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_PLCFG_PLSEL_bf(const void *const hw, hri_pm_plcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->PLCFG.reg ^= PM_PLCFG_PLSEL(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_plcfg_reg_t hri_pm_read_PLCFG_PLSEL_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->PLCFG.reg;
+	tmp = (tmp & PM_PLCFG_PLSEL_Msk) >> PM_PLCFG_PLSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_set_PLCFG_reg(const void *const hw, hri_pm_plcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->PLCFG.reg |= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_plcfg_reg_t hri_pm_get_PLCFG_reg(const void *const hw, hri_pm_plcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Pm *)hw)->PLCFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pm_write_PLCFG_reg(const void *const hw, hri_pm_plcfg_reg_t data)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->PLCFG.reg = data;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_PLCFG_reg(const void *const hw, hri_pm_plcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->PLCFG.reg &= ~mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_PLCFG_reg(const void *const hw, hri_pm_plcfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->PLCFG.reg ^= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_plcfg_reg_t hri_pm_read_PLCFG_reg(const void *const hw)
+{
+	return ((Pm *)hw)->PLCFG.reg;
+}
+
+static inline void hri_pm_set_STDBYCFG_VREGSMOD_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_VREGSMOD(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_VREGSMOD_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Pm *)hw)->STDBYCFG.reg;
+	tmp = (tmp & PM_STDBYCFG_VREGSMOD(mask)) >> PM_STDBYCFG_VREGSMOD_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_write_STDBYCFG_VREGSMOD_bf(const void *const hw, hri_pm_stdbycfg_reg_t data)
+{
+	uint16_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->STDBYCFG.reg;
+	tmp &= ~PM_STDBYCFG_VREGSMOD_Msk;
+	tmp |= PM_STDBYCFG_VREGSMOD(data);
+	((Pm *)hw)->STDBYCFG.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_STDBYCFG_VREGSMOD_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_VREGSMOD(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_STDBYCFG_VREGSMOD_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_VREGSMOD(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_VREGSMOD_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Pm *)hw)->STDBYCFG.reg;
+	tmp = (tmp & PM_STDBYCFG_VREGSMOD_Msk) >> PM_STDBYCFG_VREGSMOD_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_set_STDBYCFG_BBIASHS_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_BBIASHS(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_BBIASHS_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Pm *)hw)->STDBYCFG.reg;
+	tmp = (tmp & PM_STDBYCFG_BBIASHS(mask)) >> PM_STDBYCFG_BBIASHS_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_write_STDBYCFG_BBIASHS_bf(const void *const hw, hri_pm_stdbycfg_reg_t data)
+{
+	uint16_t tmp;
+	PM_CRITICAL_SECTION_ENTER();
+	tmp = ((Pm *)hw)->STDBYCFG.reg;
+	tmp &= ~PM_STDBYCFG_BBIASHS_Msk;
+	tmp |= PM_STDBYCFG_BBIASHS(data);
+	((Pm *)hw)->STDBYCFG.reg = tmp;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_STDBYCFG_BBIASHS_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_BBIASHS(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_STDBYCFG_BBIASHS_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_BBIASHS(mask);
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_BBIASHS_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Pm *)hw)->STDBYCFG.reg;
+	tmp = (tmp & PM_STDBYCFG_BBIASHS_Msk) >> PM_STDBYCFG_BBIASHS_Pos;
+	return tmp;
+}
+
+static inline void hri_pm_set_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->STDBYCFG.reg |= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Pm *)hw)->STDBYCFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_pm_write_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t data)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->STDBYCFG.reg = data;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_clear_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->STDBYCFG.reg &= ~mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_pm_toggle_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask)
+{
+	PM_CRITICAL_SECTION_ENTER();
+	((Pm *)hw)->STDBYCFG.reg ^= mask;
+	PM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_reg(const void *const hw)
+{
+	return ((Pm *)hw)->STDBYCFG.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_PM_L22_H_INCLUDED */
+#endif /* _SAML22_PM_COMPONENT_ */
diff --git a/watch-library/hardware/hri/hri_port_l22.h b/watch-library/hardware/hri/hri_port_l22.h
new file mode 100644
index 00000000..ee99c2e8
--- /dev/null
+++ b/watch-library/hardware/hri/hri_port_l22.h
@@ -0,0 +1,2357 @@
+/**
+ * \file
+ *
+ * \brief SAM PORT
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_PORT_COMPONENT_
+#ifndef _HRI_PORT_L22_H_INCLUDED_
+#define _HRI_PORT_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_PORT_CRITICAL_SECTIONS)
+#define PORT_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define PORT_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define PORT_CRITICAL_SECTION_ENTER()
+#define PORT_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_port_ctrl_reg_t;
+typedef uint32_t hri_port_dir_reg_t;
+typedef uint32_t hri_port_evctrl_reg_t;
+typedef uint32_t hri_port_in_reg_t;
+typedef uint32_t hri_port_out_reg_t;
+typedef uint32_t hri_port_wrconfig_reg_t;
+typedef uint32_t hri_portgroup_ctrl_reg_t;
+typedef uint32_t hri_portgroup_dir_reg_t;
+typedef uint32_t hri_portgroup_evctrl_reg_t;
+typedef uint32_t hri_portgroup_in_reg_t;
+typedef uint32_t hri_portgroup_out_reg_t;
+typedef uint32_t hri_portgroup_wrconfig_reg_t;
+typedef uint8_t  hri_port_pincfg_reg_t;
+typedef uint8_t  hri_port_pmux_reg_t;
+typedef uint8_t  hri_portgroup_pincfg_reg_t;
+typedef uint8_t  hri_portgroup_pmux_reg_t;
+
+static inline void hri_portgroup_set_DIR_reg(const void *const hw, hri_port_dir_reg_t mask)
+{
+	((PortGroup *)hw)->DIRSET.reg = mask;
+}
+
+static inline hri_port_dir_reg_t hri_portgroup_get_DIR_reg(const void *const hw, hri_port_dir_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->DIR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_port_dir_reg_t hri_portgroup_read_DIR_reg(const void *const hw)
+{
+	return ((PortGroup *)hw)->DIR.reg;
+}
+
+static inline void hri_portgroup_write_DIR_reg(const void *const hw, hri_port_dir_reg_t data)
+{
+	((PortGroup *)hw)->DIRSET.reg = data;
+	((PortGroup *)hw)->DIRCLR.reg = ~data;
+}
+
+static inline void hri_portgroup_clear_DIR_reg(const void *const hw, hri_port_dir_reg_t mask)
+{
+	((PortGroup *)hw)->DIRCLR.reg = mask;
+}
+
+static inline void hri_portgroup_toggle_DIR_reg(const void *const hw, hri_port_dir_reg_t mask)
+{
+	((PortGroup *)hw)->DIRTGL.reg = mask;
+}
+
+static inline void hri_portgroup_set_OUT_reg(const void *const hw, hri_port_out_reg_t mask)
+{
+	((PortGroup *)hw)->OUTSET.reg = mask;
+}
+
+static inline hri_port_out_reg_t hri_portgroup_get_OUT_reg(const void *const hw, hri_port_out_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->OUT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_port_out_reg_t hri_portgroup_read_OUT_reg(const void *const hw)
+{
+	return ((PortGroup *)hw)->OUT.reg;
+}
+
+static inline void hri_portgroup_write_OUT_reg(const void *const hw, hri_port_out_reg_t data)
+{
+	((PortGroup *)hw)->OUTSET.reg = data;
+	((PortGroup *)hw)->OUTCLR.reg = ~data;
+}
+
+static inline void hri_portgroup_clear_OUT_reg(const void *const hw, hri_port_out_reg_t mask)
+{
+	((PortGroup *)hw)->OUTCLR.reg = mask;
+}
+
+static inline void hri_portgroup_toggle_OUT_reg(const void *const hw, hri_port_out_reg_t mask)
+{
+	((PortGroup *)hw)->OUTTGL.reg = mask;
+}
+
+static inline hri_port_in_reg_t hri_portgroup_get_IN_reg(const void *const hw, hri_port_in_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->IN.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_port_in_reg_t hri_portgroup_read_IN_reg(const void *const hw)
+{
+	return ((PortGroup *)hw)->IN.reg;
+}
+
+static inline void hri_portgroup_set_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->CTRL.reg |= PORT_CTRL_SAMPLING(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_ctrl_reg_t hri_portgroup_get_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->CTRL.reg;
+	tmp = (tmp & PORT_CTRL_SAMPLING(mask)) >> PORT_CTRL_SAMPLING_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->CTRL.reg;
+	tmp &= ~PORT_CTRL_SAMPLING_Msk;
+	tmp |= PORT_CTRL_SAMPLING(data);
+	((PortGroup *)hw)->CTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->CTRL.reg &= ~PORT_CTRL_SAMPLING(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->CTRL.reg ^= PORT_CTRL_SAMPLING(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_ctrl_reg_t hri_portgroup_read_CTRL_SAMPLING_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->CTRL.reg;
+	tmp = (tmp & PORT_CTRL_SAMPLING_Msk) >> PORT_CTRL_SAMPLING_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->CTRL.reg |= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_ctrl_reg_t hri_portgroup_get_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->CTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->CTRL.reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->CTRL.reg &= ~mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->CTRL.reg ^= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_ctrl_reg_t hri_portgroup_read_CTRL_reg(const void *const hw)
+{
+	return ((PortGroup *)hw)->CTRL.reg;
+}
+
+static inline void hri_portgroup_set_EVCTRL_PORTEI0_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI0;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_portgroup_get_EVCTRL_PORTEI0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PORTEI0) >> PORT_EVCTRL_PORTEI0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_PORTEI0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PORTEI0;
+	tmp |= value << PORT_EVCTRL_PORTEI0_Pos;
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_PORTEI0_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_PORTEI0_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI0;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_set_EVCTRL_PORTEI1_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI1;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_portgroup_get_EVCTRL_PORTEI1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PORTEI1) >> PORT_EVCTRL_PORTEI1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_PORTEI1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PORTEI1;
+	tmp |= value << PORT_EVCTRL_PORTEI1_Pos;
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_PORTEI1_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_PORTEI1_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI1;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_set_EVCTRL_PORTEI2_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI2;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_portgroup_get_EVCTRL_PORTEI2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PORTEI2) >> PORT_EVCTRL_PORTEI2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_PORTEI2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PORTEI2;
+	tmp |= value << PORT_EVCTRL_PORTEI2_Pos;
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_PORTEI2_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_PORTEI2_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI2;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_set_EVCTRL_PORTEI3_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI3;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_portgroup_get_EVCTRL_PORTEI3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PORTEI3) >> PORT_EVCTRL_PORTEI3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_PORTEI3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PORTEI3;
+	tmp |= value << PORT_EVCTRL_PORTEI3_Pos;
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_PORTEI3_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_PORTEI3_bit(const void *const hw)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI3;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_set_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID0(mask)) >> PORT_EVCTRL_PID0_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PID0_Msk;
+	tmp |= PORT_EVCTRL_PID0(data);
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID0_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID0_Msk) >> PORT_EVCTRL_PID0_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT0(mask)) >> PORT_EVCTRL_EVACT0_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_EVACT0_Msk;
+	tmp |= PORT_EVCTRL_EVACT0(data);
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT0_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT0_Msk) >> PORT_EVCTRL_EVACT0_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID1(mask)) >> PORT_EVCTRL_PID1_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PID1_Msk;
+	tmp |= PORT_EVCTRL_PID1(data);
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID1_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID1_Msk) >> PORT_EVCTRL_PID1_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT1(mask)) >> PORT_EVCTRL_EVACT1_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_EVACT1_Msk;
+	tmp |= PORT_EVCTRL_EVACT1(data);
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT1_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT1_Msk) >> PORT_EVCTRL_EVACT1_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID2(mask)) >> PORT_EVCTRL_PID2_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PID2_Msk;
+	tmp |= PORT_EVCTRL_PID2(data);
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID2_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID2_Msk) >> PORT_EVCTRL_PID2_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT2(mask)) >> PORT_EVCTRL_EVACT2_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_EVACT2_Msk;
+	tmp |= PORT_EVCTRL_EVACT2(data);
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT2_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT2_Msk) >> PORT_EVCTRL_EVACT2_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID3(mask)) >> PORT_EVCTRL_PID3_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PID3_Msk;
+	tmp |= PORT_EVCTRL_PID3(data);
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID3_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID3_Msk) >> PORT_EVCTRL_PID3_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT3(mask)) >> PORT_EVCTRL_EVACT3_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_EVACT3_Msk;
+	tmp |= PORT_EVCTRL_EVACT3(data);
+	((PortGroup *)hw)->EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT3_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT3_Msk) >> PORT_EVCTRL_EVACT3_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg |= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((PortGroup *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg &= ~mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->EVCTRL.reg ^= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_reg(const void *const hw)
+{
+	return ((PortGroup *)hw)->EVCTRL.reg;
+}
+
+static inline void hri_portgroup_set_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg |= PORT_PMUX_PMUXE(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_PMUXE_bf(const void *const hw, uint8_t index,
+                                                                  hri_port_pmux_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PMUX[index].reg;
+	tmp = (tmp & PORT_PMUX_PMUXE(mask)) >> PORT_PMUX_PMUXE_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t data)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->PMUX[index].reg;
+	tmp &= ~PORT_PMUX_PMUXE_Msk;
+	tmp |= PORT_PMUX_PMUXE(data);
+	((PortGroup *)hw)->PMUX[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg &= ~PORT_PMUX_PMUXE(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg ^= PORT_PMUX_PMUXE(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_PMUXE_bf(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PMUX[index].reg;
+	tmp = (tmp & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg |= PORT_PMUX_PMUXO(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_PMUXO_bf(const void *const hw, uint8_t index,
+                                                                  hri_port_pmux_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PMUX[index].reg;
+	tmp = (tmp & PORT_PMUX_PMUXO(mask)) >> PORT_PMUX_PMUXO_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t data)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->PMUX[index].reg;
+	tmp &= ~PORT_PMUX_PMUXO_Msk;
+	tmp |= PORT_PMUX_PMUXO(data);
+	((PortGroup *)hw)->PMUX[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg &= ~PORT_PMUX_PMUXO(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg ^= PORT_PMUX_PMUXO(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_PMUXO_bf(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PMUX[index].reg;
+	tmp = (tmp & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos;
+	return tmp;
+}
+
+static inline void hri_portgroup_set_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg |= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_reg(const void *const hw, uint8_t index,
+                                                             hri_port_pmux_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PMUX[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg &= ~mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PMUX[index].reg ^= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_reg(const void *const hw, uint8_t index)
+{
+	return ((PortGroup *)hw)->PMUX[index].reg;
+}
+
+static inline void hri_portgroup_set_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_PMUXEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_portgroup_get_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PINCFG[index].reg;
+	tmp = (tmp & PORT_PINCFG_PMUXEN) >> PORT_PINCFG_PMUXEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_portgroup_write_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->PINCFG[index].reg;
+	tmp &= ~PORT_PINCFG_PMUXEN;
+	tmp |= value << PORT_PINCFG_PMUXEN_Pos;
+	((PortGroup *)hw)->PINCFG[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_PMUXEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_PMUXEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_set_PINCFG_INEN_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_INEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_portgroup_get_PINCFG_INEN_bit(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PINCFG[index].reg;
+	tmp = (tmp & PORT_PINCFG_INEN) >> PORT_PINCFG_INEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_portgroup_write_PINCFG_INEN_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->PINCFG[index].reg;
+	tmp &= ~PORT_PINCFG_INEN;
+	tmp |= value << PORT_PINCFG_INEN_Pos;
+	((PortGroup *)hw)->PINCFG[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_PINCFG_INEN_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_INEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_PINCFG_INEN_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_INEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_set_PINCFG_PULLEN_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_PULLEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_portgroup_get_PINCFG_PULLEN_bit(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PINCFG[index].reg;
+	tmp = (tmp & PORT_PINCFG_PULLEN) >> PORT_PINCFG_PULLEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_portgroup_write_PINCFG_PULLEN_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->PINCFG[index].reg;
+	tmp &= ~PORT_PINCFG_PULLEN;
+	tmp |= value << PORT_PINCFG_PULLEN_Pos;
+	((PortGroup *)hw)->PINCFG[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_PINCFG_PULLEN_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_PULLEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_PINCFG_PULLEN_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_PULLEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_set_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_DRVSTR;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_portgroup_get_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PINCFG[index].reg;
+	tmp = (tmp & PORT_PINCFG_DRVSTR) >> PORT_PINCFG_DRVSTR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_portgroup_write_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index, bool value)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((PortGroup *)hw)->PINCFG[index].reg;
+	tmp &= ~PORT_PINCFG_DRVSTR;
+	tmp |= value << PORT_PINCFG_DRVSTR_Pos;
+	((PortGroup *)hw)->PINCFG[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_DRVSTR;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_DRVSTR;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_set_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg |= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pincfg_reg_t hri_portgroup_get_PINCFG_reg(const void *const hw, uint8_t index,
+                                                                 hri_port_pincfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((PortGroup *)hw)->PINCFG[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_portgroup_write_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_clear_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg &= ~mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_portgroup_toggle_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->PINCFG[index].reg ^= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pincfg_reg_t hri_portgroup_read_PINCFG_reg(const void *const hw, uint8_t index)
+{
+	return ((PortGroup *)hw)->PINCFG[index].reg;
+}
+
+static inline void hri_portgroup_write_WRCONFIG_reg(const void *const hw, hri_port_wrconfig_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((PortGroup *)hw)->WRCONFIG.reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_set_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].DIRSET.reg = mask;
+}
+
+static inline hri_port_dir_reg_t hri_port_get_DIR_reg(const void *const hw, uint8_t submodule_index,
+                                                      hri_port_dir_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].DIR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_port_dir_reg_t hri_port_read_DIR_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Port *)hw)->Group[submodule_index].DIR.reg;
+}
+
+static inline void hri_port_write_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t data)
+{
+	((Port *)hw)->Group[submodule_index].DIRSET.reg = data;
+	((Port *)hw)->Group[submodule_index].DIRCLR.reg = ~data;
+}
+
+static inline void hri_port_clear_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask;
+}
+
+static inline void hri_port_toggle_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].DIRTGL.reg = mask;
+}
+
+static inline void hri_port_set_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].OUTSET.reg = mask;
+}
+
+static inline hri_port_out_reg_t hri_port_get_OUT_reg(const void *const hw, uint8_t submodule_index,
+                                                      hri_port_out_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].OUT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_port_out_reg_t hri_port_read_OUT_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Port *)hw)->Group[submodule_index].OUT.reg;
+}
+
+static inline void hri_port_write_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t data)
+{
+	((Port *)hw)->Group[submodule_index].OUTSET.reg = data;
+	((Port *)hw)->Group[submodule_index].OUTCLR.reg = ~data;
+}
+
+static inline void hri_port_clear_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask;
+}
+
+static inline void hri_port_toggle_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask)
+{
+	((Port *)hw)->Group[submodule_index].OUTTGL.reg = mask;
+}
+
+static inline hri_port_in_reg_t hri_port_get_IN_reg(const void *const hw, uint8_t submodule_index,
+                                                    hri_port_in_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].IN.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_port_in_reg_t hri_port_read_IN_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Port *)hw)->Group[submodule_index].IN.reg;
+}
+
+static inline void hri_port_set_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].CTRL.reg |= PORT_CTRL_SAMPLING(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_ctrl_reg_t hri_port_get_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index,
+                                                                hri_port_ctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg;
+	tmp = (tmp & PORT_CTRL_SAMPLING(mask)) >> PORT_CTRL_SAMPLING_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_port_ctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg;
+	tmp &= ~PORT_CTRL_SAMPLING_Msk;
+	tmp |= PORT_CTRL_SAMPLING(data);
+	((Port *)hw)->Group[submodule_index].CTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].CTRL.reg &= ~PORT_CTRL_SAMPLING(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].CTRL.reg ^= PORT_CTRL_SAMPLING(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_ctrl_reg_t hri_port_read_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg;
+	tmp = (tmp & PORT_CTRL_SAMPLING_Msk) >> PORT_CTRL_SAMPLING_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].CTRL.reg |= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_ctrl_reg_t hri_port_get_CTRL_reg(const void *const hw, uint8_t submodule_index,
+                                                        hri_port_ctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_port_write_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].CTRL.reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].CTRL.reg &= ~mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].CTRL.reg ^= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_ctrl_reg_t hri_port_read_CTRL_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Port *)hw)->Group[submodule_index].CTRL.reg;
+}
+
+static inline void hri_port_set_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI0;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_port_get_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PORTEI0) >> PORT_EVCTRL_PORTEI0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_port_write_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PORTEI0;
+	tmp |= value << PORT_EVCTRL_PORTEI0_Pos;
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI0;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_set_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI1;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_port_get_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PORTEI1) >> PORT_EVCTRL_PORTEI1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_port_write_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PORTEI1;
+	tmp |= value << PORT_EVCTRL_PORTEI1_Pos;
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI1;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_set_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI2;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_port_get_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PORTEI2) >> PORT_EVCTRL_PORTEI2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_port_write_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PORTEI2;
+	tmp |= value << PORT_EVCTRL_PORTEI2_Pos;
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI2;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_set_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI3;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_port_get_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PORTEI3) >> PORT_EVCTRL_PORTEI3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_port_write_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PORTEI3;
+	tmp |= value << PORT_EVCTRL_PORTEI3_Pos;
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI3;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_set_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index,
+                                               hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index,
+                                                                hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID0(mask)) >> PORT_EVCTRL_PID0_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PID0_Msk;
+	tmp |= PORT_EVCTRL_PID0(data);
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID0_Msk) >> PORT_EVCTRL_PID0_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index,
+                                                                  hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT0(mask)) >> PORT_EVCTRL_EVACT0_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_EVACT0_Msk;
+	tmp |= PORT_EVCTRL_EVACT0(data);
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT0(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT0_Msk) >> PORT_EVCTRL_EVACT0_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index,
+                                               hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index,
+                                                                hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID1(mask)) >> PORT_EVCTRL_PID1_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PID1_Msk;
+	tmp |= PORT_EVCTRL_PID1(data);
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID1_Msk) >> PORT_EVCTRL_PID1_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index,
+                                                                  hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT1(mask)) >> PORT_EVCTRL_EVACT1_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_EVACT1_Msk;
+	tmp |= PORT_EVCTRL_EVACT1(data);
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT1(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT1_Msk) >> PORT_EVCTRL_EVACT1_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index,
+                                               hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index,
+                                                                hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID2(mask)) >> PORT_EVCTRL_PID2_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PID2_Msk;
+	tmp |= PORT_EVCTRL_PID2(data);
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID2_Msk) >> PORT_EVCTRL_PID2_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index,
+                                                                  hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT2(mask)) >> PORT_EVCTRL_EVACT2_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_EVACT2_Msk;
+	tmp |= PORT_EVCTRL_EVACT2(data);
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT2(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT2_Msk) >> PORT_EVCTRL_EVACT2_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index,
+                                               hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index,
+                                                                hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID3(mask)) >> PORT_EVCTRL_PID3_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_PID3_Msk;
+	tmp |= PORT_EVCTRL_PID3(data);
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_PID3_Msk) >> PORT_EVCTRL_PID3_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index,
+                                                                  hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT3(mask)) >> PORT_EVCTRL_EVACT3_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_port_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= ~PORT_EVCTRL_EVACT3_Msk;
+	tmp |= PORT_EVCTRL_EVACT3(data);
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT3(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp = (tmp & PORT_EVCTRL_EVACT3_Msk) >> PORT_EVCTRL_EVACT3_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg |= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_reg(const void *const hw, uint8_t submodule_index,
+                                                            hri_port_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_port_write_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
+}
+
+static inline void hri_port_set_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                              hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg |= PORT_PMUX_PMUXE(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_port_get_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index,
+                                                             uint8_t index, hri_port_pmux_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+	tmp = (tmp & PORT_PMUX_PMUXE(mask)) >> PORT_PMUX_PMUXE_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                hri_port_pmux_reg_t data)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+	tmp &= ~PORT_PMUX_PMUXE_Msk;
+	tmp |= PORT_PMUX_PMUXE(data);
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~PORT_PMUX_PMUXE(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                 hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= PORT_PMUX_PMUXE(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_port_read_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index,
+                                                              uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+	tmp = (tmp & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                              hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg |= PORT_PMUX_PMUXO(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_port_get_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index,
+                                                             uint8_t index, hri_port_pmux_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+	tmp = (tmp & PORT_PMUX_PMUXO(mask)) >> PORT_PMUX_PMUXO_Pos;
+	return tmp;
+}
+
+static inline void hri_port_write_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                hri_port_pmux_reg_t data)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+	tmp &= ~PORT_PMUX_PMUXO_Msk;
+	tmp |= PORT_PMUX_PMUXO(data);
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~PORT_PMUX_PMUXO(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                 hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= PORT_PMUX_PMUXO(mask);
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_port_read_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index,
+                                                              uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+	tmp = (tmp & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos;
+	return tmp;
+}
+
+static inline void hri_port_set_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                         hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg |= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_port_get_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                        hri_port_pmux_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_port_write_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                           hri_port_pmux_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                           hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                            hri_port_pmux_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pmux_reg_t hri_port_read_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	return ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
+}
+
+static inline void hri_port_set_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PMUXEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_port_get_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+	tmp = (tmp & PORT_PINCFG_PMUXEN) >> PORT_PINCFG_PMUXEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_port_write_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                    bool value)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+	tmp &= ~PORT_PINCFG_PMUXEN;
+	tmp |= value << PORT_PINCFG_PMUXEN_Pos;
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PMUXEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_PMUXEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_set_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_INEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_port_get_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+	tmp = (tmp & PORT_PINCFG_INEN) >> PORT_PINCFG_INEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_port_write_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                  bool value)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+	tmp &= ~PORT_PINCFG_INEN;
+	tmp |= value << PORT_PINCFG_INEN_Pos;
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_INEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_INEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_set_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PULLEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_port_get_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+	tmp = (tmp & PORT_PINCFG_PULLEN) >> PORT_PINCFG_PULLEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_port_write_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                    bool value)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+	tmp &= ~PORT_PINCFG_PULLEN;
+	tmp |= value << PORT_PINCFG_PULLEN_Pos;
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PULLEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_PULLEN;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_set_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_DRVSTR;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_port_get_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+	tmp = (tmp & PORT_PINCFG_DRVSTR) >> PORT_PINCFG_DRVSTR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_port_write_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                                    bool value)
+{
+	uint8_t tmp;
+	PORT_CRITICAL_SECTION_ENTER();
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+	tmp &= ~PORT_PINCFG_DRVSTR;
+	tmp |= value << PORT_PINCFG_DRVSTR_Pos;
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_DRVSTR;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_DRVSTR;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_set_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                           hri_port_pincfg_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pincfg_reg_t hri_port_get_PINCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                            uint8_t index, hri_port_pincfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_port_write_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                             hri_port_pincfg_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_clear_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                             hri_port_pincfg_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_port_toggle_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
+                                              hri_port_pincfg_reg_t mask)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= mask;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_port_pincfg_reg_t hri_port_read_PINCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                             uint8_t index)
+{
+	return ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
+}
+
+static inline void hri_port_write_WRCONFIG_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_port_wrconfig_reg_t data)
+{
+	PORT_CRITICAL_SECTION_ENTER();
+	((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data;
+	PORT_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_PORT_L22_H_INCLUDED */
+#endif /* _SAML22_PORT_COMPONENT_ */
diff --git a/watch-library/hardware/hri/hri_rstc_l22.h b/watch-library/hardware/hri/hri_rstc_l22.h
new file mode 100644
index 00000000..853744e2
--- /dev/null
+++ b/watch-library/hardware/hri/hri_rstc_l22.h
@@ -0,0 +1,132 @@
+/**
+ * \file
+ *
+ * \brief SAM RSTC
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_RSTC_COMPONENT_
+#ifndef _HRI_RSTC_L22_H_INCLUDED_
+#define _HRI_RSTC_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_RSTC_CRITICAL_SECTIONS)
+#define RSTC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define RSTC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define RSTC_CRITICAL_SECTION_ENTER()
+#define RSTC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint8_t hri_rstc_bkupexit_reg_t;
+typedef uint8_t hri_rstc_rcause_reg_t;
+
+static inline bool hri_rstc_get_RCAUSE_POR_bit(const void *const hw)
+{
+	return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_POR) >> RSTC_RCAUSE_POR_Pos;
+}
+
+static inline bool hri_rstc_get_RCAUSE_BODCORE_bit(const void *const hw)
+{
+	return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BODCORE) >> RSTC_RCAUSE_BODCORE_Pos;
+}
+
+static inline bool hri_rstc_get_RCAUSE_BODVDD_bit(const void *const hw)
+{
+	return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BODVDD) >> RSTC_RCAUSE_BODVDD_Pos;
+}
+
+static inline bool hri_rstc_get_RCAUSE_EXT_bit(const void *const hw)
+{
+	return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_EXT) >> RSTC_RCAUSE_EXT_Pos;
+}
+
+static inline bool hri_rstc_get_RCAUSE_WDT_bit(const void *const hw)
+{
+	return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_WDT) >> RSTC_RCAUSE_WDT_Pos;
+}
+
+static inline bool hri_rstc_get_RCAUSE_SYST_bit(const void *const hw)
+{
+	return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_SYST) >> RSTC_RCAUSE_SYST_Pos;
+}
+
+static inline bool hri_rstc_get_RCAUSE_BACKUP_bit(const void *const hw)
+{
+	return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BACKUP) >> RSTC_RCAUSE_BACKUP_Pos;
+}
+
+static inline hri_rstc_rcause_reg_t hri_rstc_get_RCAUSE_reg(const void *const hw, hri_rstc_rcause_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Rstc *)hw)->RCAUSE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rstc_rcause_reg_t hri_rstc_read_RCAUSE_reg(const void *const hw)
+{
+	return ((Rstc *)hw)->RCAUSE.reg;
+}
+
+static inline bool hri_rstc_get_BKUPEXIT_RTC_bit(const void *const hw)
+{
+	return (((Rstc *)hw)->BKUPEXIT.reg & RSTC_BKUPEXIT_RTC) >> RSTC_BKUPEXIT_RTC_Pos;
+}
+
+static inline bool hri_rstc_get_BKUPEXIT_BBPS_bit(const void *const hw)
+{
+	return (((Rstc *)hw)->BKUPEXIT.reg & RSTC_BKUPEXIT_BBPS) >> RSTC_BKUPEXIT_BBPS_Pos;
+}
+
+static inline hri_rstc_bkupexit_reg_t hri_rstc_get_BKUPEXIT_reg(const void *const hw, hri_rstc_bkupexit_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Rstc *)hw)->BKUPEXIT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rstc_bkupexit_reg_t hri_rstc_read_BKUPEXIT_reg(const void *const hw)
+{
+	return ((Rstc *)hw)->BKUPEXIT.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_RSTC_L22_H_INCLUDED */
+#endif /* _SAML22_RSTC_COMPONENT_ */
diff --git a/watch-library/hardware/hri/hri_rtc_l22.h b/watch-library/hardware/hri/hri_rtc_l22.h
new file mode 100644
index 00000000..0b46f010
--- /dev/null
+++ b/watch-library/hardware/hri/hri_rtc_l22.h
@@ -0,0 +1,9084 @@
+/**
+ * \file
+ *
+ * \brief SAM RTC
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_RTC_COMPONENT_
+#ifndef _HRI_RTC_L22_H_INCLUDED_
+#define _HRI_RTC_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_RTC_CRITICAL_SECTIONS)
+#define RTC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define RTC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define RTC_CRITICAL_SECTION_ENTER()
+#define RTC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_rtcmode0_ctrla_reg_t;
+typedef uint16_t hri_rtcmode0_ctrlb_reg_t;
+typedef uint16_t hri_rtcmode0_intenset_reg_t;
+typedef uint16_t hri_rtcmode0_intflag_reg_t;
+typedef uint16_t hri_rtcmode1_comp_reg_t;
+typedef uint16_t hri_rtcmode1_count_reg_t;
+typedef uint16_t hri_rtcmode1_ctrla_reg_t;
+typedef uint16_t hri_rtcmode1_ctrlb_reg_t;
+typedef uint16_t hri_rtcmode1_intenset_reg_t;
+typedef uint16_t hri_rtcmode1_intflag_reg_t;
+typedef uint16_t hri_rtcmode1_per_reg_t;
+typedef uint16_t hri_rtcmode2_ctrla_reg_t;
+typedef uint16_t hri_rtcmode2_ctrlb_reg_t;
+typedef uint16_t hri_rtcmode2_intenset_reg_t;
+typedef uint16_t hri_rtcmode2_intflag_reg_t;
+typedef uint32_t hri_rtc_bkup_reg_t;
+typedef uint32_t hri_rtc_gp_reg_t;
+typedef uint32_t hri_rtc_tampctrl_reg_t;
+typedef uint32_t hri_rtc_tampid_reg_t;
+typedef uint32_t hri_rtcalarm_alarm_reg_t;
+typedef uint32_t hri_rtcmode0_comp_reg_t;
+typedef uint32_t hri_rtcmode0_count_reg_t;
+typedef uint32_t hri_rtcmode0_evctrl_reg_t;
+typedef uint32_t hri_rtcmode0_syncbusy_reg_t;
+typedef uint32_t hri_rtcmode0_timestamp_reg_t;
+typedef uint32_t hri_rtcmode1_evctrl_reg_t;
+typedef uint32_t hri_rtcmode1_syncbusy_reg_t;
+typedef uint32_t hri_rtcmode1_timestamp_reg_t;
+typedef uint32_t hri_rtcmode2_alarm_reg_t;
+typedef uint32_t hri_rtcmode2_clock_reg_t;
+typedef uint32_t hri_rtcmode2_evctrl_reg_t;
+typedef uint32_t hri_rtcmode2_syncbusy_reg_t;
+typedef uint32_t hri_rtcmode2_timestamp_reg_t;
+typedef uint8_t  hri_rtc_dbgctrl_reg_t;
+typedef uint8_t  hri_rtc_freqcorr_reg_t;
+typedef uint8_t  hri_rtcalarm_mask_reg_t;
+typedef uint8_t  hri_rtcmode2_mask_reg_t;
+
+static inline void hri_rtcmode0_wait_for_sync(const void *const hw, hri_rtcmode0_syncbusy_reg_t reg)
+{
+	while (((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_rtcmode0_is_syncing(const void *const hw, hri_rtcmode0_syncbusy_reg_t reg)
+{
+	return ((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg;
+}
+
+static inline void hri_rtcmode1_wait_for_sync(const void *const hw, hri_rtcmode1_syncbusy_reg_t reg)
+{
+	while (((Rtc *)hw)->MODE1.SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_rtcmode1_is_syncing(const void *const hw, hri_rtcmode1_syncbusy_reg_t reg)
+{
+	return ((Rtc *)hw)->MODE1.SYNCBUSY.reg & reg;
+}
+
+static inline void hri_rtcmode2_wait_for_sync(const void *const hw, hri_rtcmode2_syncbusy_reg_t reg)
+{
+	while (((Rtc *)hw)->MODE2.SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_rtcmode2_is_syncing(const void *const hw, hri_rtcmode2_syncbusy_reg_t reg)
+{
+	return ((Rtc *)hw)->MODE2.SYNCBUSY.reg & reg;
+}
+
+static inline void hri_rtcalarm_set_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_SECOND(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                                        hri_rtcalarm_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_SECOND(mask)) >> RTC_MODE2_ALARM_SECOND_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_write_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcalarm_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_SECOND_Msk;
+	tmp |= RTC_MODE2_ALARM_SECOND(data);
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_clear_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_SECOND(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_toggle_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                       hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_SECOND(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_SECOND_Msk) >> RTC_MODE2_ALARM_SECOND_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_set_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MINUTE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                                        hri_rtcalarm_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_MINUTE(mask)) >> RTC_MODE2_ALARM_MINUTE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_write_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcalarm_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_MINUTE_Msk;
+	tmp |= RTC_MODE2_ALARM_MINUTE(data);
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_clear_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MINUTE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_toggle_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                       hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MINUTE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_MINUTE_Msk) >> RTC_MODE2_ALARM_MINUTE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_set_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_HOUR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                                      hri_rtcalarm_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_HOUR(mask)) >> RTC_MODE2_ALARM_HOUR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_write_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcalarm_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_HOUR_Msk;
+	tmp |= RTC_MODE2_ALARM_HOUR(data);
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_clear_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_HOUR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_toggle_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_HOUR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_HOUR_Msk) >> RTC_MODE2_ALARM_HOUR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_set_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_DAY(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                                     hri_rtcalarm_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_DAY(mask)) >> RTC_MODE2_ALARM_DAY_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_write_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_rtcalarm_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_DAY_Msk;
+	tmp |= RTC_MODE2_ALARM_DAY(data);
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_clear_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_DAY(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_toggle_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_DAY(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_DAY_Msk) >> RTC_MODE2_ALARM_DAY_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_set_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MONTH(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                                       hri_rtcalarm_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_MONTH(mask)) >> RTC_MODE2_ALARM_MONTH_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_write_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_rtcalarm_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_MONTH_Msk;
+	tmp |= RTC_MODE2_ALARM_MONTH(data);
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_clear_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MONTH(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_toggle_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MONTH(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_MONTH_Msk) >> RTC_MODE2_ALARM_MONTH_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_set_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_YEAR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                                      hri_rtcalarm_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_YEAR(mask)) >> RTC_MODE2_ALARM_YEAR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_write_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcalarm_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_YEAR_Msk;
+	tmp |= RTC_MODE2_ALARM_YEAR(data);
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_clear_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_YEAR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_toggle_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_YEAR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_YEAR_Msk) >> RTC_MODE2_ALARM_YEAR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_set_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                              hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                                                  hri_rtcalarm_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_write_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_rtcalarm_alarm_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_clear_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_toggle_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_rtcalarm_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg;
+}
+
+static inline void hri_rtcalarm_set_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                hri_rtcalarm_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg |= RTC_MODE2_MASK_SEL(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_get_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_rtcalarm_mask_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg;
+	tmp = (tmp & RTC_MODE2_MASK_SEL(mask)) >> RTC_MODE2_MASK_SEL_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_write_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_rtcalarm_mask_reg_t data)
+{
+	uint8_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg;
+	tmp &= ~RTC_MODE2_MASK_SEL_Msk;
+	tmp |= RTC_MODE2_MASK_SEL(data);
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_clear_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_rtcalarm_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg &= ~RTC_MODE2_MASK_SEL(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_toggle_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_rtcalarm_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg ^= RTC_MODE2_MASK_SEL(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_read_MASK_SEL_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg;
+	tmp = (tmp & RTC_MODE2_MASK_SEL_Msk) >> RTC_MODE2_MASK_SEL_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_set_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                             hri_rtcalarm_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_get_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                                                hri_rtcalarm_mask_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcalarm_write_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_rtcalarm_mask_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_clear_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_rtcalarm_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcalarm_toggle_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_rtcalarm_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_read_MASK_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg;
+}
+
+static inline void hri_rtcmode2_set_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_SECOND(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                                        hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_SECOND(mask)) >> RTC_MODE2_ALARM_SECOND_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcmode2_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_SECOND_Msk;
+	tmp |= RTC_MODE2_ALARM_SECOND(data);
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_SECOND(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index,
+                                                       hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_SECOND(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_SECOND_Msk) >> RTC_MODE2_ALARM_SECOND_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MINUTE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                                        hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_MINUTE(mask)) >> RTC_MODE2_ALARM_MINUTE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcmode2_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_MINUTE_Msk;
+	tmp |= RTC_MODE2_ALARM_MINUTE(data);
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MINUTE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index,
+                                                       hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MINUTE(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_MINUTE_Msk) >> RTC_MODE2_ALARM_MINUTE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_HOUR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                                      hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_HOUR(mask)) >> RTC_MODE2_ALARM_HOUR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_HOUR_Msk;
+	tmp |= RTC_MODE2_ALARM_HOUR(data);
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_HOUR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_HOUR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_HOUR_Msk) >> RTC_MODE2_ALARM_HOUR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                 hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_DAY(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                                     hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_DAY(mask)) >> RTC_MODE2_ALARM_DAY_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_rtcmode2_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_DAY_Msk;
+	tmp |= RTC_MODE2_ALARM_DAY(data);
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_DAY(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_DAY(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_DAY_Msk) >> RTC_MODE2_ALARM_DAY_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MONTH(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                                       hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_MONTH(mask)) >> RTC_MODE2_ALARM_MONTH_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_rtcmode2_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_MONTH_Msk;
+	tmp |= RTC_MODE2_ALARM_MONTH(data);
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MONTH(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MONTH(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_MONTH_Msk) >> RTC_MODE2_ALARM_MONTH_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_YEAR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                                      hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_YEAR(mask)) >> RTC_MODE2_ALARM_YEAR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= ~RTC_MODE2_ALARM_YEAR_Msk;
+	tmp |= RTC_MODE2_ALARM_YEAR(data);
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                    hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_YEAR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index,
+                                                     hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_YEAR(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp = (tmp & RTC_MODE2_ALARM_YEAR_Msk) >> RTC_MODE2_ALARM_YEAR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                              hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                                                  hri_rtcmode2_alarm_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_rtcmode2_alarm_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_ALARM_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_rtcmode2_alarm_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg;
+}
+
+static inline void hri_rtcmode2_set_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                hri_rtcmode2_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg |= RTC_MODE2_MASK_SEL(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_get_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_rtcmode2_mask_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg;
+	tmp = (tmp & RTC_MODE2_MASK_SEL(mask)) >> RTC_MODE2_MASK_SEL_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_rtcmode2_mask_reg_t data)
+{
+	uint8_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg;
+	tmp &= ~RTC_MODE2_MASK_SEL_Msk;
+	tmp |= RTC_MODE2_MASK_SEL(data);
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_rtcmode2_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg &= ~RTC_MODE2_MASK_SEL(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_MASK_SEL_bf(const void *const hw, uint8_t submodule_index,
+                                                   hri_rtcmode2_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg ^= RTC_MODE2_MASK_SEL(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_read_MASK_SEL_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg;
+	tmp = (tmp & RTC_MODE2_MASK_SEL_Msk) >> RTC_MODE2_MASK_SEL_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                             hri_rtcmode2_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_get_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                                                hri_rtcmode2_mask_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_rtcmode2_mask_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_rtcmode2_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_MASK_reg(const void *const hw, uint8_t submodule_index,
+                                                hri_rtcmode2_mask_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_read_MASK_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_PER0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER0) >> RTC_MODE0_INTFLAG_PER0_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER0;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_PER1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER1) >> RTC_MODE0_INTFLAG_PER1_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER1;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_PER2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER2) >> RTC_MODE0_INTFLAG_PER2_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER2;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_PER3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER3) >> RTC_MODE0_INTFLAG_PER3_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER3;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_PER4_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER4) >> RTC_MODE0_INTFLAG_PER4_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER4;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_PER5_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER5) >> RTC_MODE0_INTFLAG_PER5_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER5;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_PER6_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER6) >> RTC_MODE0_INTFLAG_PER6_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER6;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_PER7_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER7) >> RTC_MODE0_INTFLAG_PER7_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER7;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_CMP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP0) >> RTC_MODE0_INTFLAG_CMP0_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_CMP0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_TAMPER_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_TAMPER) >> RTC_MODE0_INTFLAG_TAMPER_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_TAMPER;
+}
+
+static inline bool hri_rtcmode0_get_INTFLAG_OVF_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_OVF) >> RTC_MODE0_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_PER0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER0) >> RTC_MODE0_INTFLAG_PER0_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER0;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_PER1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER1) >> RTC_MODE0_INTFLAG_PER1_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER1;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_PER2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER2) >> RTC_MODE0_INTFLAG_PER2_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER2;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_PER3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER3) >> RTC_MODE0_INTFLAG_PER3_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER3;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_PER4_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER4) >> RTC_MODE0_INTFLAG_PER4_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER4;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_PER5_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER5) >> RTC_MODE0_INTFLAG_PER5_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER5;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_PER6_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER6) >> RTC_MODE0_INTFLAG_PER6_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER6;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_PER7_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER7) >> RTC_MODE0_INTFLAG_PER7_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER7;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_CMP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP0) >> RTC_MODE0_INTFLAG_CMP0_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_CMP0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_TAMPER_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_TAMPER) >> RTC_MODE0_INTFLAG_TAMPER_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_TAMPER;
+}
+
+static inline bool hri_rtcmode0_get_interrupt_OVF_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_OVF) >> RTC_MODE0_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_rtcmode0_clear_interrupt_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF;
+}
+
+static inline hri_rtcmode0_intflag_reg_t hri_rtcmode0_get_INTFLAG_reg(const void *const          hw,
+                                                                      hri_rtcmode0_intflag_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode0_intflag_reg_t hri_rtcmode0_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE0.INTFLAG.reg;
+}
+
+static inline void hri_rtcmode0_clear_INTFLAG_reg(const void *const hw, hri_rtcmode0_intflag_reg_t mask)
+{
+	((Rtc *)hw)->MODE0.INTFLAG.reg = mask;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_PER0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER0) >> RTC_MODE1_INTFLAG_PER0_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER0;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_PER1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER1) >> RTC_MODE1_INTFLAG_PER1_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER1;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_PER2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER2) >> RTC_MODE1_INTFLAG_PER2_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER2;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_PER3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER3) >> RTC_MODE1_INTFLAG_PER3_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER3;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_PER4_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER4) >> RTC_MODE1_INTFLAG_PER4_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER4;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_PER5_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER5) >> RTC_MODE1_INTFLAG_PER5_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER5;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_PER6_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER6) >> RTC_MODE1_INTFLAG_PER6_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER6;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_PER7_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER7) >> RTC_MODE1_INTFLAG_PER7_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER7;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_CMP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP0) >> RTC_MODE1_INTFLAG_CMP0_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_CMP0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP0;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_CMP1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP1) >> RTC_MODE1_INTFLAG_CMP1_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_CMP1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP1;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_TAMPER_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_TAMPER) >> RTC_MODE1_INTFLAG_TAMPER_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_TAMPER;
+}
+
+static inline bool hri_rtcmode1_get_INTFLAG_OVF_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_OVF) >> RTC_MODE1_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_OVF;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_PER0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER0) >> RTC_MODE1_INTFLAG_PER0_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER0;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_PER1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER1) >> RTC_MODE1_INTFLAG_PER1_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER1;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_PER2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER2) >> RTC_MODE1_INTFLAG_PER2_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER2;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_PER3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER3) >> RTC_MODE1_INTFLAG_PER3_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER3;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_PER4_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER4) >> RTC_MODE1_INTFLAG_PER4_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER4;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_PER5_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER5) >> RTC_MODE1_INTFLAG_PER5_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER5;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_PER6_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER6) >> RTC_MODE1_INTFLAG_PER6_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER6;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_PER7_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER7) >> RTC_MODE1_INTFLAG_PER7_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER7;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_CMP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP0) >> RTC_MODE1_INTFLAG_CMP0_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_CMP0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP0;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_CMP1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP1) >> RTC_MODE1_INTFLAG_CMP1_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_CMP1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP1;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_TAMPER_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_TAMPER) >> RTC_MODE1_INTFLAG_TAMPER_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_TAMPER;
+}
+
+static inline bool hri_rtcmode1_get_interrupt_OVF_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_OVF) >> RTC_MODE1_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_rtcmode1_clear_interrupt_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_OVF;
+}
+
+static inline hri_rtcmode1_intflag_reg_t hri_rtcmode1_get_INTFLAG_reg(const void *const          hw,
+                                                                      hri_rtcmode1_intflag_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode1_intflag_reg_t hri_rtcmode1_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE1.INTFLAG.reg;
+}
+
+static inline void hri_rtcmode1_clear_INTFLAG_reg(const void *const hw, hri_rtcmode1_intflag_reg_t mask)
+{
+	((Rtc *)hw)->MODE1.INTFLAG.reg = mask;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_PER0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER0) >> RTC_MODE2_INTFLAG_PER0_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER0;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_PER1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER1) >> RTC_MODE2_INTFLAG_PER1_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER1;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_PER2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER2) >> RTC_MODE2_INTFLAG_PER2_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER2;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_PER3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER3) >> RTC_MODE2_INTFLAG_PER3_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER3;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_PER4_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER4) >> RTC_MODE2_INTFLAG_PER4_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER4;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_PER5_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER5) >> RTC_MODE2_INTFLAG_PER5_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER5;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_PER6_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER6) >> RTC_MODE2_INTFLAG_PER6_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER6;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_PER7_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER7) >> RTC_MODE2_INTFLAG_PER7_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER7;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_ALARM0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM0) >> RTC_MODE2_INTFLAG_ALARM0_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_ALARM0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM0;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_TAMPER_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_TAMPER) >> RTC_MODE2_INTFLAG_TAMPER_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_TAMPER;
+}
+
+static inline bool hri_rtcmode2_get_INTFLAG_OVF_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_OVF) >> RTC_MODE2_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_PER0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER0) >> RTC_MODE2_INTFLAG_PER0_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER0;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_PER1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER1) >> RTC_MODE2_INTFLAG_PER1_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER1;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_PER2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER2) >> RTC_MODE2_INTFLAG_PER2_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER2;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_PER3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER3) >> RTC_MODE2_INTFLAG_PER3_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER3;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_PER4_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER4) >> RTC_MODE2_INTFLAG_PER4_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER4;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_PER5_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER5) >> RTC_MODE2_INTFLAG_PER5_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER5;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_PER6_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER6) >> RTC_MODE2_INTFLAG_PER6_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER6;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_PER7_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER7) >> RTC_MODE2_INTFLAG_PER7_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER7;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_ALARM0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM0) >> RTC_MODE2_INTFLAG_ALARM0_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_ALARM0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM0;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_TAMPER_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_TAMPER) >> RTC_MODE2_INTFLAG_TAMPER_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_TAMPER;
+}
+
+static inline bool hri_rtcmode2_get_interrupt_OVF_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_OVF) >> RTC_MODE2_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_rtcmode2_clear_interrupt_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF;
+}
+
+static inline hri_rtcmode2_intflag_reg_t hri_rtcmode2_get_INTFLAG_reg(const void *const          hw,
+                                                                      hri_rtcmode2_intflag_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode2_intflag_reg_t hri_rtcmode2_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE2.INTFLAG.reg;
+}
+
+static inline void hri_rtcmode2_clear_INTFLAG_reg(const void *const hw, hri_rtcmode2_intflag_reg_t mask)
+{
+	((Rtc *)hw)->MODE2.INTFLAG.reg = mask;
+}
+
+static inline void hri_rtcmode0_set_INTEN_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER0;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_PER0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER0) >> RTC_MODE0_INTENSET_PER0_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_PER0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER0;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER0;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER0;
+}
+
+static inline void hri_rtcmode0_set_INTEN_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER1;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_PER1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER1) >> RTC_MODE0_INTENSET_PER1_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_PER1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER1;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER1;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER1;
+}
+
+static inline void hri_rtcmode0_set_INTEN_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER2;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_PER2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER2) >> RTC_MODE0_INTENSET_PER2_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_PER2_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER2;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER2;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER2;
+}
+
+static inline void hri_rtcmode0_set_INTEN_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER3;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_PER3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER3) >> RTC_MODE0_INTENSET_PER3_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_PER3_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER3;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER3;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER3;
+}
+
+static inline void hri_rtcmode0_set_INTEN_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER4;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_PER4_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER4) >> RTC_MODE0_INTENSET_PER4_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_PER4_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER4;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER4;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER4;
+}
+
+static inline void hri_rtcmode0_set_INTEN_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER5;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_PER5_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER5) >> RTC_MODE0_INTENSET_PER5_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_PER5_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER5;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER5;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER5;
+}
+
+static inline void hri_rtcmode0_set_INTEN_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER6;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_PER6_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER6) >> RTC_MODE0_INTENSET_PER6_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_PER6_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER6;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER6;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER6;
+}
+
+static inline void hri_rtcmode0_set_INTEN_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER7;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_PER7_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER7) >> RTC_MODE0_INTENSET_PER7_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_PER7_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER7;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER7;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER7;
+}
+
+static inline void hri_rtcmode0_set_INTEN_CMP0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_CMP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_CMP0) >> RTC_MODE0_INTENSET_CMP0_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_CMP0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP0;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_CMP0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP0;
+}
+
+static inline void hri_rtcmode0_set_INTEN_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_TAMPER;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_TAMPER_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_TAMPER) >> RTC_MODE0_INTENSET_TAMPER_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_TAMPER_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_TAMPER;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_TAMPER;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_TAMPER;
+}
+
+static inline void hri_rtcmode0_set_INTEN_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_OVF;
+}
+
+static inline bool hri_rtcmode0_get_INTEN_OVF_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_OVF) >> RTC_MODE0_INTENSET_OVF_Pos;
+}
+
+static inline void hri_rtcmode0_write_INTEN_OVF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_OVF;
+	} else {
+		((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_OVF;
+	}
+}
+
+static inline void hri_rtcmode0_clear_INTEN_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_OVF;
+}
+
+static inline void hri_rtcmode0_set_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t mask)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = mask;
+}
+
+static inline hri_rtcmode0_intenset_reg_t hri_rtcmode0_get_INTEN_reg(const void *const           hw,
+                                                                     hri_rtcmode0_intenset_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode0_intenset_reg_t hri_rtcmode0_read_INTEN_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE0.INTENSET.reg;
+}
+
+static inline void hri_rtcmode0_write_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t data)
+{
+	((Rtc *)hw)->MODE0.INTENSET.reg = data;
+	((Rtc *)hw)->MODE0.INTENCLR.reg = ~data;
+}
+
+static inline void hri_rtcmode0_clear_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t mask)
+{
+	((Rtc *)hw)->MODE0.INTENCLR.reg = mask;
+}
+
+static inline void hri_rtcmode1_set_INTEN_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER0;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_PER0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER0) >> RTC_MODE1_INTENSET_PER0_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_PER0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER0;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER0;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER0;
+}
+
+static inline void hri_rtcmode1_set_INTEN_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER1;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_PER1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER1) >> RTC_MODE1_INTENSET_PER1_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_PER1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER1;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER1;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER1;
+}
+
+static inline void hri_rtcmode1_set_INTEN_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER2;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_PER2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER2) >> RTC_MODE1_INTENSET_PER2_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_PER2_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER2;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER2;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER2;
+}
+
+static inline void hri_rtcmode1_set_INTEN_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER3;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_PER3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER3) >> RTC_MODE1_INTENSET_PER3_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_PER3_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER3;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER3;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER3;
+}
+
+static inline void hri_rtcmode1_set_INTEN_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER4;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_PER4_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER4) >> RTC_MODE1_INTENSET_PER4_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_PER4_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER4;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER4;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER4;
+}
+
+static inline void hri_rtcmode1_set_INTEN_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER5;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_PER5_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER5) >> RTC_MODE1_INTENSET_PER5_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_PER5_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER5;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER5;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER5;
+}
+
+static inline void hri_rtcmode1_set_INTEN_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER6;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_PER6_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER6) >> RTC_MODE1_INTENSET_PER6_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_PER6_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER6;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER6;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER6;
+}
+
+static inline void hri_rtcmode1_set_INTEN_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER7;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_PER7_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER7) >> RTC_MODE1_INTENSET_PER7_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_PER7_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER7;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER7;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER7;
+}
+
+static inline void hri_rtcmode1_set_INTEN_CMP0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP0;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_CMP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP0) >> RTC_MODE1_INTENSET_CMP0_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_CMP0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP0;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP0;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_CMP0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP0;
+}
+
+static inline void hri_rtcmode1_set_INTEN_CMP1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP1;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_CMP1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP1) >> RTC_MODE1_INTENSET_CMP1_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_CMP1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP1;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP1;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_CMP1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP1;
+}
+
+static inline void hri_rtcmode1_set_INTEN_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_TAMPER;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_TAMPER_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_TAMPER) >> RTC_MODE1_INTENSET_TAMPER_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_TAMPER_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_TAMPER;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_TAMPER;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_TAMPER;
+}
+
+static inline void hri_rtcmode1_set_INTEN_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_OVF;
+}
+
+static inline bool hri_rtcmode1_get_INTEN_OVF_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_OVF) >> RTC_MODE1_INTENSET_OVF_Pos;
+}
+
+static inline void hri_rtcmode1_write_INTEN_OVF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_OVF;
+	} else {
+		((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_OVF;
+	}
+}
+
+static inline void hri_rtcmode1_clear_INTEN_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_OVF;
+}
+
+static inline void hri_rtcmode1_set_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t mask)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = mask;
+}
+
+static inline hri_rtcmode1_intenset_reg_t hri_rtcmode1_get_INTEN_reg(const void *const           hw,
+                                                                     hri_rtcmode1_intenset_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode1_intenset_reg_t hri_rtcmode1_read_INTEN_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE1.INTENSET.reg;
+}
+
+static inline void hri_rtcmode1_write_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t data)
+{
+	((Rtc *)hw)->MODE1.INTENSET.reg = data;
+	((Rtc *)hw)->MODE1.INTENCLR.reg = ~data;
+}
+
+static inline void hri_rtcmode1_clear_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t mask)
+{
+	((Rtc *)hw)->MODE1.INTENCLR.reg = mask;
+}
+
+static inline void hri_rtcmode2_set_INTEN_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER0;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_PER0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER0) >> RTC_MODE2_INTENSET_PER0_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_PER0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER0;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER0;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_PER0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER0;
+}
+
+static inline void hri_rtcmode2_set_INTEN_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER1;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_PER1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER1) >> RTC_MODE2_INTENSET_PER1_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_PER1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER1;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER1;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_PER1_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER1;
+}
+
+static inline void hri_rtcmode2_set_INTEN_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER2;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_PER2_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER2) >> RTC_MODE2_INTENSET_PER2_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_PER2_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER2;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER2;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_PER2_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER2;
+}
+
+static inline void hri_rtcmode2_set_INTEN_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER3;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_PER3_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER3) >> RTC_MODE2_INTENSET_PER3_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_PER3_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER3;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER3;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_PER3_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER3;
+}
+
+static inline void hri_rtcmode2_set_INTEN_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER4;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_PER4_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER4) >> RTC_MODE2_INTENSET_PER4_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_PER4_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER4;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER4;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_PER4_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER4;
+}
+
+static inline void hri_rtcmode2_set_INTEN_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER5;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_PER5_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER5) >> RTC_MODE2_INTENSET_PER5_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_PER5_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER5;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER5;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_PER5_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER5;
+}
+
+static inline void hri_rtcmode2_set_INTEN_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER6;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_PER6_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER6) >> RTC_MODE2_INTENSET_PER6_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_PER6_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER6;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER6;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_PER6_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER6;
+}
+
+static inline void hri_rtcmode2_set_INTEN_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER7;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_PER7_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER7) >> RTC_MODE2_INTENSET_PER7_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_PER7_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER7;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER7;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_PER7_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER7;
+}
+
+static inline void hri_rtcmode2_set_INTEN_ALARM0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM0;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_ALARM0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_ALARM0) >> RTC_MODE2_INTENSET_ALARM0_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_ALARM0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM0;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM0;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_ALARM0_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM0;
+}
+
+static inline void hri_rtcmode2_set_INTEN_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_TAMPER;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_TAMPER_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_TAMPER) >> RTC_MODE2_INTENSET_TAMPER_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_TAMPER_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_TAMPER;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_TAMPER;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_TAMPER_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_TAMPER;
+}
+
+static inline void hri_rtcmode2_set_INTEN_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_OVF;
+}
+
+static inline bool hri_rtcmode2_get_INTEN_OVF_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_OVF) >> RTC_MODE2_INTENSET_OVF_Pos;
+}
+
+static inline void hri_rtcmode2_write_INTEN_OVF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_OVF;
+	} else {
+		((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_OVF;
+	}
+}
+
+static inline void hri_rtcmode2_clear_INTEN_OVF_bit(const void *const hw)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_OVF;
+}
+
+static inline void hri_rtcmode2_set_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t mask)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = mask;
+}
+
+static inline hri_rtcmode2_intenset_reg_t hri_rtcmode2_get_INTEN_reg(const void *const           hw,
+                                                                     hri_rtcmode2_intenset_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode2_intenset_reg_t hri_rtcmode2_read_INTEN_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE2.INTENSET.reg;
+}
+
+static inline void hri_rtcmode2_write_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t data)
+{
+	((Rtc *)hw)->MODE2.INTENSET.reg = data;
+	((Rtc *)hw)->MODE2.INTENCLR.reg = ~data;
+}
+
+static inline void hri_rtcmode2_clear_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t mask)
+{
+	((Rtc *)hw)->MODE2.INTENCLR.reg = mask;
+}
+
+static inline bool hri_rtcmode0_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_SWRST) >> RTC_MODE0_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_rtcmode0_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_ENABLE) >> RTC_MODE0_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_rtcmode0_get_SYNCBUSY_FREQCORR_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_FREQCORR) >> RTC_MODE0_SYNCBUSY_FREQCORR_Pos;
+}
+
+static inline bool hri_rtcmode0_get_SYNCBUSY_COUNT_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COUNT) >> RTC_MODE0_SYNCBUSY_COUNT_Pos;
+}
+
+static inline bool hri_rtcmode0_get_SYNCBUSY_COMP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COMP0) >> RTC_MODE0_SYNCBUSY_COMP0_Pos;
+}
+
+static inline bool hri_rtcmode0_get_SYNCBUSY_COUNTSYNC_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COUNTSYNC) >> RTC_MODE0_SYNCBUSY_COUNTSYNC_Pos;
+}
+
+static inline bool hri_rtcmode0_get_SYNCBUSY_GP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP0) >> RTC_MODE0_SYNCBUSY_GP0_Pos;
+}
+
+static inline bool hri_rtcmode0_get_SYNCBUSY_GP1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP1) >> RTC_MODE0_SYNCBUSY_GP1_Pos;
+}
+
+static inline hri_rtcmode0_syncbusy_reg_t hri_rtcmode0_get_SYNCBUSY_reg(const void *const           hw,
+                                                                        hri_rtcmode0_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode0_syncbusy_reg_t hri_rtcmode0_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE0.SYNCBUSY.reg;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_SWRST) >> RTC_MODE1_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_ENABLE) >> RTC_MODE1_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_FREQCORR_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_FREQCORR) >> RTC_MODE1_SYNCBUSY_FREQCORR_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_COUNT_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COUNT) >> RTC_MODE1_SYNCBUSY_COUNT_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_PER_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_PER) >> RTC_MODE1_SYNCBUSY_PER_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_COMP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP0) >> RTC_MODE1_SYNCBUSY_COMP0_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_COMP1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP1) >> RTC_MODE1_SYNCBUSY_COMP1_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_COUNTSYNC_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COUNTSYNC) >> RTC_MODE1_SYNCBUSY_COUNTSYNC_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_GP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP0) >> RTC_MODE1_SYNCBUSY_GP0_Pos;
+}
+
+static inline bool hri_rtcmode1_get_SYNCBUSY_GP1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP1) >> RTC_MODE1_SYNCBUSY_GP1_Pos;
+}
+
+static inline hri_rtcmode1_syncbusy_reg_t hri_rtcmode1_get_SYNCBUSY_reg(const void *const           hw,
+                                                                        hri_rtcmode1_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode1_syncbusy_reg_t hri_rtcmode1_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE1.SYNCBUSY.reg;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_SWRST) >> RTC_MODE2_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_ENABLE) >> RTC_MODE2_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_FREQCORR_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_FREQCORR) >> RTC_MODE2_SYNCBUSY_FREQCORR_Pos;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_CLOCK_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_CLOCK) >> RTC_MODE2_SYNCBUSY_CLOCK_Pos;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_ALARM0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_ALARM0) >> RTC_MODE2_SYNCBUSY_ALARM0_Pos;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_MASK0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_MASK0) >> RTC_MODE2_SYNCBUSY_MASK0_Pos;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_CLOCKSYNC_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_CLOCKSYNC) >> RTC_MODE2_SYNCBUSY_CLOCKSYNC_Pos;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_GP0_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP0) >> RTC_MODE2_SYNCBUSY_GP0_Pos;
+}
+
+static inline bool hri_rtcmode2_get_SYNCBUSY_GP1_bit(const void *const hw)
+{
+	return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP1) >> RTC_MODE2_SYNCBUSY_GP1_Pos;
+}
+
+static inline hri_rtcmode2_syncbusy_reg_t hri_rtcmode2_get_SYNCBUSY_reg(const void *const           hw,
+                                                                        hri_rtcmode2_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode2_syncbusy_reg_t hri_rtcmode2_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE2.SYNCBUSY.reg;
+}
+
+static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_get_TIMESTAMP_COUNT_bf(const void *const            hw,
+                                                                               hri_rtcmode0_timestamp_reg_t mask)
+{
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	return (((Rtc *)hw)->MODE0.TIMESTAMP.reg & RTC_MODE0_TIMESTAMP_COUNT(mask)) >> RTC_MODE0_TIMESTAMP_COUNT_Pos;
+}
+
+static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_read_TIMESTAMP_COUNT_bf(const void *const hw)
+{
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	return (((Rtc *)hw)->MODE0.TIMESTAMP.reg & RTC_MODE0_TIMESTAMP_COUNT_Msk) >> RTC_MODE0_TIMESTAMP_COUNT_Pos;
+}
+
+static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_get_TIMESTAMP_reg(const void *const            hw,
+                                                                          hri_rtcmode0_timestamp_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	tmp = ((Rtc *)hw)->MODE0.TIMESTAMP.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_read_TIMESTAMP_reg(const void *const hw)
+{
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	return ((Rtc *)hw)->MODE0.TIMESTAMP.reg;
+}
+
+static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_get_TIMESTAMP_COUNT_bf(const void *const            hw,
+                                                                               hri_rtcmode1_timestamp_reg_t mask)
+{
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	return (((Rtc *)hw)->MODE1.TIMESTAMP.reg & RTC_MODE1_TIMESTAMP_COUNT(mask)) >> RTC_MODE1_TIMESTAMP_COUNT_Pos;
+}
+
+static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_read_TIMESTAMP_COUNT_bf(const void *const hw)
+{
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	return (((Rtc *)hw)->MODE1.TIMESTAMP.reg & RTC_MODE1_TIMESTAMP_COUNT_Msk) >> RTC_MODE1_TIMESTAMP_COUNT_Pos;
+}
+
+static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_get_TIMESTAMP_reg(const void *const            hw,
+                                                                          hri_rtcmode1_timestamp_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	tmp = ((Rtc *)hw)->MODE1.TIMESTAMP.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_read_TIMESTAMP_reg(const void *const hw)
+{
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	return ((Rtc *)hw)->MODE1.TIMESTAMP.reg;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_SECOND_bf(const void *const            hw,
+                                                                                hri_rtcmode2_timestamp_reg_t mask)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_SECOND(mask)) >> RTC_MODE2_TIMESTAMP_SECOND_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_SECOND_bf(const void *const hw)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_SECOND_Msk) >> RTC_MODE2_TIMESTAMP_SECOND_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_MINUTE_bf(const void *const            hw,
+                                                                                hri_rtcmode2_timestamp_reg_t mask)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MINUTE(mask)) >> RTC_MODE2_TIMESTAMP_MINUTE_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_MINUTE_bf(const void *const hw)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MINUTE_Msk) >> RTC_MODE2_TIMESTAMP_MINUTE_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_HOUR_bf(const void *const            hw,
+                                                                              hri_rtcmode2_timestamp_reg_t mask)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_HOUR(mask)) >> RTC_MODE2_TIMESTAMP_HOUR_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_HOUR_bf(const void *const hw)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_HOUR_Msk) >> RTC_MODE2_TIMESTAMP_HOUR_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_DAY_bf(const void *const            hw,
+                                                                             hri_rtcmode2_timestamp_reg_t mask)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_DAY(mask)) >> RTC_MODE2_TIMESTAMP_DAY_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_DAY_bf(const void *const hw)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_DAY_Msk) >> RTC_MODE2_TIMESTAMP_DAY_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_MONTH_bf(const void *const            hw,
+                                                                               hri_rtcmode2_timestamp_reg_t mask)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MONTH(mask)) >> RTC_MODE2_TIMESTAMP_MONTH_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_MONTH_bf(const void *const hw)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MONTH_Msk) >> RTC_MODE2_TIMESTAMP_MONTH_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_YEAR_bf(const void *const            hw,
+                                                                              hri_rtcmode2_timestamp_reg_t mask)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_YEAR(mask)) >> RTC_MODE2_TIMESTAMP_YEAR_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_YEAR_bf(const void *const hw)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_YEAR_Msk) >> RTC_MODE2_TIMESTAMP_YEAR_Pos;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_reg(const void *const            hw,
+                                                                          hri_rtcmode2_timestamp_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.TIMESTAMP.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_reg(const void *const hw)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return ((Rtc *)hw)->MODE2.TIMESTAMP.reg;
+}
+
+static inline void hri_rtcmode0_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_SWRST;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST);
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp = (tmp & RTC_MODE0_CTRLA_SWRST) >> RTC_MODE0_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_ENABLE;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp = (tmp & RTC_MODE0_CTRLA_ENABLE) >> RTC_MODE0_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp &= ~RTC_MODE0_CTRLA_ENABLE;
+	tmp |= value << RTC_MODE0_CTRLA_ENABLE_Pos;
+	((Rtc *)hw)->MODE0.CTRLA.reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_ENABLE;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_ENABLE;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_CTRLA_MATCHCLR_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_MATCHCLR;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLA_MATCHCLR_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp = (tmp & RTC_MODE0_CTRLA_MATCHCLR) >> RTC_MODE0_CTRLA_MATCHCLR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLA_MATCHCLR_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp &= ~RTC_MODE0_CTRLA_MATCHCLR;
+	tmp |= value << RTC_MODE0_CTRLA_MATCHCLR_Pos;
+	((Rtc *)hw)->MODE0.CTRLA.reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLA_MATCHCLR_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_MATCHCLR;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLA_MATCHCLR_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_MATCHCLR;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_CTRLA_BKTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_BKTRST;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLA_BKTRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp = (tmp & RTC_MODE0_CTRLA_BKTRST) >> RTC_MODE0_CTRLA_BKTRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLA_BKTRST_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp &= ~RTC_MODE0_CTRLA_BKTRST;
+	tmp |= value << RTC_MODE0_CTRLA_BKTRST_Pos;
+	((Rtc *)hw)->MODE0.CTRLA.reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLA_BKTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_BKTRST;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLA_BKTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_BKTRST;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_CTRLA_GPTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_GPTRST;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLA_GPTRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp = (tmp & RTC_MODE0_CTRLA_GPTRST) >> RTC_MODE0_CTRLA_GPTRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLA_GPTRST_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp &= ~RTC_MODE0_CTRLA_GPTRST;
+	tmp |= value << RTC_MODE0_CTRLA_GPTRST_Pos;
+	((Rtc *)hw)->MODE0.CTRLA.reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLA_GPTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_GPTRST;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLA_GPTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_GPTRST;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_CTRLA_COUNTSYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_COUNTSYNC;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLA_COUNTSYNC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp = (tmp & RTC_MODE0_CTRLA_COUNTSYNC) >> RTC_MODE0_CTRLA_COUNTSYNC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLA_COUNTSYNC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp &= ~RTC_MODE0_CTRLA_COUNTSYNC;
+	tmp |= value << RTC_MODE0_CTRLA_COUNTSYNC_Pos;
+	((Rtc *)hw)->MODE0.CTRLA.reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLA_COUNTSYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_COUNTSYNC;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLA_COUNTSYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_COUNTSYNC;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_MODE(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_MODE_bf(const void *const        hw,
+                                                                      hri_rtcmode0_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp = (tmp & RTC_MODE0_CTRLA_MODE(mask)) >> RTC_MODE0_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp &= ~RTC_MODE0_CTRLA_MODE_Msk;
+	tmp |= RTC_MODE0_CTRLA_MODE(data);
+	((Rtc *)hw)->MODE0.CTRLA.reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_MODE(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_MODE(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_MODE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp = (tmp & RTC_MODE0_CTRLA_MODE_Msk) >> RTC_MODE0_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_PRESCALER(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_PRESCALER_bf(const void *const        hw,
+                                                                           hri_rtcmode0_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp = (tmp & RTC_MODE0_CTRLA_PRESCALER(mask)) >> RTC_MODE0_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp &= ~RTC_MODE0_CTRLA_PRESCALER_Msk;
+	tmp |= RTC_MODE0_CTRLA_PRESCALER(data);
+	((Rtc *)hw)->MODE0.CTRLA.reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_PRESCALER(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_PRESCALER(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_PRESCALER_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp = (tmp & RTC_MODE0_CTRLA_PRESCALER_Msk) >> RTC_MODE0_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_set_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg |= mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg = data;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg &= ~mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLA.reg ^= mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_reg(const void *const hw)
+{
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
+	return ((Rtc *)hw)->MODE0.CTRLA.reg;
+}
+
+static inline void hri_rtcmode1_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_SWRST;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST);
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp = (tmp & RTC_MODE1_CTRLA_SWRST) >> RTC_MODE1_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_ENABLE;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp = (tmp & RTC_MODE1_CTRLA_ENABLE) >> RTC_MODE1_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp &= ~RTC_MODE1_CTRLA_ENABLE;
+	tmp |= value << RTC_MODE1_CTRLA_ENABLE_Pos;
+	((Rtc *)hw)->MODE1.CTRLA.reg = tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_ENABLE;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_ENABLE;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_CTRLA_BKTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_BKTRST;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_CTRLA_BKTRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp = (tmp & RTC_MODE1_CTRLA_BKTRST) >> RTC_MODE1_CTRLA_BKTRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLA_BKTRST_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp &= ~RTC_MODE1_CTRLA_BKTRST;
+	tmp |= value << RTC_MODE1_CTRLA_BKTRST_Pos;
+	((Rtc *)hw)->MODE1.CTRLA.reg = tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLA_BKTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_BKTRST;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLA_BKTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_BKTRST;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_CTRLA_GPTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_GPTRST;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_CTRLA_GPTRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp = (tmp & RTC_MODE1_CTRLA_GPTRST) >> RTC_MODE1_CTRLA_GPTRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLA_GPTRST_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp &= ~RTC_MODE1_CTRLA_GPTRST;
+	tmp |= value << RTC_MODE1_CTRLA_GPTRST_Pos;
+	((Rtc *)hw)->MODE1.CTRLA.reg = tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLA_GPTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_GPTRST;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLA_GPTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_GPTRST;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_CTRLA_COUNTSYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_COUNTSYNC;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_CTRLA_COUNTSYNC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp = (tmp & RTC_MODE1_CTRLA_COUNTSYNC) >> RTC_MODE1_CTRLA_COUNTSYNC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLA_COUNTSYNC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp &= ~RTC_MODE1_CTRLA_COUNTSYNC;
+	tmp |= value << RTC_MODE1_CTRLA_COUNTSYNC_Pos;
+	((Rtc *)hw)->MODE1.CTRLA.reg = tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLA_COUNTSYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_COUNTSYNC;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLA_COUNTSYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_COUNTSYNC;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_MODE(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_MODE_bf(const void *const        hw,
+                                                                      hri_rtcmode1_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp = (tmp & RTC_MODE1_CTRLA_MODE(mask)) >> RTC_MODE1_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp &= ~RTC_MODE1_CTRLA_MODE_Msk;
+	tmp |= RTC_MODE1_CTRLA_MODE(data);
+	((Rtc *)hw)->MODE1.CTRLA.reg = tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_MODE(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_MODE(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_MODE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp = (tmp & RTC_MODE1_CTRLA_MODE_Msk) >> RTC_MODE1_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_PRESCALER(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_PRESCALER_bf(const void *const        hw,
+                                                                           hri_rtcmode1_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp = (tmp & RTC_MODE1_CTRLA_PRESCALER(mask)) >> RTC_MODE1_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp &= ~RTC_MODE1_CTRLA_PRESCALER_Msk;
+	tmp |= RTC_MODE1_CTRLA_PRESCALER(data);
+	((Rtc *)hw)->MODE1.CTRLA.reg = tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_PRESCALER(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_PRESCALER(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_PRESCALER_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp = (tmp & RTC_MODE1_CTRLA_PRESCALER_Msk) >> RTC_MODE1_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_set_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg |= mask;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	tmp = ((Rtc *)hw)->MODE1.CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg = data;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg &= ~mask;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLA.reg ^= mask;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_reg(const void *const hw)
+{
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC);
+	return ((Rtc *)hw)->MODE1.CTRLA.reg;
+}
+
+static inline void hri_rtcmode2_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_SWRST;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST);
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp = (tmp & RTC_MODE2_CTRLA_SWRST) >> RTC_MODE2_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_ENABLE;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp = (tmp & RTC_MODE2_CTRLA_ENABLE) >> RTC_MODE2_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp &= ~RTC_MODE2_CTRLA_ENABLE;
+	tmp |= value << RTC_MODE2_CTRLA_ENABLE_Pos;
+	((Rtc *)hw)->MODE2.CTRLA.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_ENABLE;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_ENABLE;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLA_CLKREP_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_CLKREP;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLA_CLKREP_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp = (tmp & RTC_MODE2_CTRLA_CLKREP) >> RTC_MODE2_CTRLA_CLKREP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLA_CLKREP_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp &= ~RTC_MODE2_CTRLA_CLKREP;
+	tmp |= value << RTC_MODE2_CTRLA_CLKREP_Pos;
+	((Rtc *)hw)->MODE2.CTRLA.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLA_CLKREP_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_CLKREP;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLA_CLKREP_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_CLKREP;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLA_MATCHCLR_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_MATCHCLR;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLA_MATCHCLR_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp = (tmp & RTC_MODE2_CTRLA_MATCHCLR) >> RTC_MODE2_CTRLA_MATCHCLR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLA_MATCHCLR_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp &= ~RTC_MODE2_CTRLA_MATCHCLR;
+	tmp |= value << RTC_MODE2_CTRLA_MATCHCLR_Pos;
+	((Rtc *)hw)->MODE2.CTRLA.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLA_MATCHCLR_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_MATCHCLR;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLA_MATCHCLR_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_MATCHCLR;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLA_BKTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_BKTRST;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLA_BKTRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp = (tmp & RTC_MODE2_CTRLA_BKTRST) >> RTC_MODE2_CTRLA_BKTRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLA_BKTRST_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp &= ~RTC_MODE2_CTRLA_BKTRST;
+	tmp |= value << RTC_MODE2_CTRLA_BKTRST_Pos;
+	((Rtc *)hw)->MODE2.CTRLA.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLA_BKTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_BKTRST;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLA_BKTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_BKTRST;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLA_GPTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_GPTRST;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLA_GPTRST_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp = (tmp & RTC_MODE2_CTRLA_GPTRST) >> RTC_MODE2_CTRLA_GPTRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLA_GPTRST_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp &= ~RTC_MODE2_CTRLA_GPTRST;
+	tmp |= value << RTC_MODE2_CTRLA_GPTRST_Pos;
+	((Rtc *)hw)->MODE2.CTRLA.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLA_GPTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_GPTRST;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLA_GPTRST_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_GPTRST;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLA_CLOCKSYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_CLOCKSYNC;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLA_CLOCKSYNC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp = (tmp & RTC_MODE2_CTRLA_CLOCKSYNC) >> RTC_MODE2_CTRLA_CLOCKSYNC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLA_CLOCKSYNC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp &= ~RTC_MODE2_CTRLA_CLOCKSYNC;
+	tmp |= value << RTC_MODE2_CTRLA_CLOCKSYNC_Pos;
+	((Rtc *)hw)->MODE2.CTRLA.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLA_CLOCKSYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_CLOCKSYNC;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLA_CLOCKSYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_CLOCKSYNC;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_MODE(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_MODE_bf(const void *const        hw,
+                                                                      hri_rtcmode2_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp = (tmp & RTC_MODE2_CTRLA_MODE(mask)) >> RTC_MODE2_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp &= ~RTC_MODE2_CTRLA_MODE_Msk;
+	tmp |= RTC_MODE2_CTRLA_MODE(data);
+	((Rtc *)hw)->MODE2.CTRLA.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_MODE(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_MODE(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_MODE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp = (tmp & RTC_MODE2_CTRLA_MODE_Msk) >> RTC_MODE2_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_PRESCALER(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_PRESCALER_bf(const void *const        hw,
+                                                                           hri_rtcmode2_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp = (tmp & RTC_MODE2_CTRLA_PRESCALER(mask)) >> RTC_MODE2_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp &= ~RTC_MODE2_CTRLA_PRESCALER_Msk;
+	tmp |= RTC_MODE2_CTRLA_PRESCALER(data);
+	((Rtc *)hw)->MODE2.CTRLA.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_PRESCALER(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_PRESCALER(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_PRESCALER_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp = (tmp & RTC_MODE2_CTRLA_PRESCALER_Msk) >> RTC_MODE2_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg |= mask;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
+{
+	uint16_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	tmp = ((Rtc *)hw)->MODE2.CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg = data;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg &= ~mask;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLA.reg ^= mask;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_reg(const void *const hw)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC);
+	return ((Rtc *)hw)->MODE2.CTRLA.reg;
+}
+
+static inline void hri_rtcmode0_set_CTRLB_GP0EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_GP0EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLB_GP0EN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp = (tmp & RTC_MODE0_CTRLB_GP0EN) >> RTC_MODE0_CTRLB_GP0EN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLB_GP0EN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp &= ~RTC_MODE0_CTRLB_GP0EN;
+	tmp |= value << RTC_MODE0_CTRLB_GP0EN_Pos;
+	((Rtc *)hw)->MODE0.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLB_GP0EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_GP0EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLB_GP0EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_GP0EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DEBMAJ;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp = (tmp & RTC_MODE0_CTRLB_DEBMAJ) >> RTC_MODE0_CTRLB_DEBMAJ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLB_DEBMAJ_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp &= ~RTC_MODE0_CTRLB_DEBMAJ;
+	tmp |= value << RTC_MODE0_CTRLB_DEBMAJ_Pos;
+	((Rtc *)hw)->MODE0.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DEBMAJ;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DEBMAJ;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DEBASYNC;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp = (tmp & RTC_MODE0_CTRLB_DEBASYNC) >> RTC_MODE0_CTRLB_DEBASYNC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLB_DEBASYNC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp &= ~RTC_MODE0_CTRLB_DEBASYNC;
+	tmp |= value << RTC_MODE0_CTRLB_DEBASYNC_Pos;
+	((Rtc *)hw)->MODE0.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DEBASYNC;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DEBASYNC;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_RTCOUT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp = (tmp & RTC_MODE0_CTRLB_RTCOUT) >> RTC_MODE0_CTRLB_RTCOUT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLB_RTCOUT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp &= ~RTC_MODE0_CTRLB_RTCOUT;
+	tmp |= value << RTC_MODE0_CTRLB_RTCOUT_Pos;
+	((Rtc *)hw)->MODE0.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_RTCOUT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_RTCOUT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_CTRLB_DMAEN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DMAEN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_CTRLB_DMAEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp = (tmp & RTC_MODE0_CTRLB_DMAEN) >> RTC_MODE0_CTRLB_DMAEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLB_DMAEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp &= ~RTC_MODE0_CTRLB_DMAEN;
+	tmp |= value << RTC_MODE0_CTRLB_DMAEN_Pos;
+	((Rtc *)hw)->MODE0.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLB_DMAEN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DMAEN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLB_DMAEN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DMAEN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DEBF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_get_CTRLB_DEBF_bf(const void *const        hw,
+                                                                      hri_rtcmode0_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp = (tmp & RTC_MODE0_CTRLB_DEBF(mask)) >> RTC_MODE0_CTRLB_DEBF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp &= ~RTC_MODE0_CTRLB_DEBF_Msk;
+	tmp |= RTC_MODE0_CTRLB_DEBF(data);
+	((Rtc *)hw)->MODE0.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DEBF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DEBF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_read_CTRLB_DEBF_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp = (tmp & RTC_MODE0_CTRLB_DEBF_Msk) >> RTC_MODE0_CTRLB_DEBF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_set_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_ACTF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_get_CTRLB_ACTF_bf(const void *const        hw,
+                                                                      hri_rtcmode0_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp = (tmp & RTC_MODE0_CTRLB_ACTF(mask)) >> RTC_MODE0_CTRLB_ACTF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp &= ~RTC_MODE0_CTRLB_ACTF_Msk;
+	tmp |= RTC_MODE0_CTRLB_ACTF(data);
+	((Rtc *)hw)->MODE0.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_ACTF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_ACTF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_read_CTRLB_ACTF_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp = (tmp & RTC_MODE0_CTRLB_ACTF_Msk) >> RTC_MODE0_CTRLB_ACTF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_set_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_get_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.CTRLB.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_read_CTRLB_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE0.CTRLB.reg;
+}
+
+static inline void hri_rtcmode1_set_CTRLB_GP0EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_GP0EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_CTRLB_GP0EN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp = (tmp & RTC_MODE1_CTRLB_GP0EN) >> RTC_MODE1_CTRLB_GP0EN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLB_GP0EN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp &= ~RTC_MODE1_CTRLB_GP0EN;
+	tmp |= value << RTC_MODE1_CTRLB_GP0EN_Pos;
+	((Rtc *)hw)->MODE1.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLB_GP0EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_GP0EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLB_GP0EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_GP0EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DEBMAJ;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp = (tmp & RTC_MODE1_CTRLB_DEBMAJ) >> RTC_MODE1_CTRLB_DEBMAJ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLB_DEBMAJ_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp &= ~RTC_MODE1_CTRLB_DEBMAJ;
+	tmp |= value << RTC_MODE1_CTRLB_DEBMAJ_Pos;
+	((Rtc *)hw)->MODE1.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DEBMAJ;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DEBMAJ;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DEBASYNC;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp = (tmp & RTC_MODE1_CTRLB_DEBASYNC) >> RTC_MODE1_CTRLB_DEBASYNC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLB_DEBASYNC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp &= ~RTC_MODE1_CTRLB_DEBASYNC;
+	tmp |= value << RTC_MODE1_CTRLB_DEBASYNC_Pos;
+	((Rtc *)hw)->MODE1.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DEBASYNC;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DEBASYNC;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_RTCOUT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp = (tmp & RTC_MODE1_CTRLB_RTCOUT) >> RTC_MODE1_CTRLB_RTCOUT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLB_RTCOUT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp &= ~RTC_MODE1_CTRLB_RTCOUT;
+	tmp |= value << RTC_MODE1_CTRLB_RTCOUT_Pos;
+	((Rtc *)hw)->MODE1.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_RTCOUT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_RTCOUT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_CTRLB_DMAEN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DMAEN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_CTRLB_DMAEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp = (tmp & RTC_MODE1_CTRLB_DMAEN) >> RTC_MODE1_CTRLB_DMAEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLB_DMAEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp &= ~RTC_MODE1_CTRLB_DMAEN;
+	tmp |= value << RTC_MODE1_CTRLB_DMAEN_Pos;
+	((Rtc *)hw)->MODE1.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLB_DMAEN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DMAEN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLB_DMAEN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DMAEN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DEBF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_get_CTRLB_DEBF_bf(const void *const        hw,
+                                                                      hri_rtcmode1_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp = (tmp & RTC_MODE1_CTRLB_DEBF(mask)) >> RTC_MODE1_CTRLB_DEBF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp &= ~RTC_MODE1_CTRLB_DEBF_Msk;
+	tmp |= RTC_MODE1_CTRLB_DEBF(data);
+	((Rtc *)hw)->MODE1.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DEBF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DEBF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_read_CTRLB_DEBF_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp = (tmp & RTC_MODE1_CTRLB_DEBF_Msk) >> RTC_MODE1_CTRLB_DEBF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_set_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_ACTF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_get_CTRLB_ACTF_bf(const void *const        hw,
+                                                                      hri_rtcmode1_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp = (tmp & RTC_MODE1_CTRLB_ACTF(mask)) >> RTC_MODE1_CTRLB_ACTF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp &= ~RTC_MODE1_CTRLB_ACTF_Msk;
+	tmp |= RTC_MODE1_CTRLB_ACTF(data);
+	((Rtc *)hw)->MODE1.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_ACTF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_ACTF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_read_CTRLB_ACTF_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp = (tmp & RTC_MODE1_CTRLB_ACTF_Msk) >> RTC_MODE1_CTRLB_ACTF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_set_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_get_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.CTRLB.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_read_CTRLB_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE1.CTRLB.reg;
+}
+
+static inline void hri_rtcmode2_set_CTRLB_GP0EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_GP0EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLB_GP0EN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp = (tmp & RTC_MODE2_CTRLB_GP0EN) >> RTC_MODE2_CTRLB_GP0EN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLB_GP0EN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp &= ~RTC_MODE2_CTRLB_GP0EN;
+	tmp |= value << RTC_MODE2_CTRLB_GP0EN_Pos;
+	((Rtc *)hw)->MODE2.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLB_GP0EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_GP0EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLB_GP0EN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_GP0EN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DEBMAJ;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp = (tmp & RTC_MODE2_CTRLB_DEBMAJ) >> RTC_MODE2_CTRLB_DEBMAJ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLB_DEBMAJ_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp &= ~RTC_MODE2_CTRLB_DEBMAJ;
+	tmp |= value << RTC_MODE2_CTRLB_DEBMAJ_Pos;
+	((Rtc *)hw)->MODE2.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DEBMAJ;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLB_DEBMAJ_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DEBMAJ;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DEBASYNC;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp = (tmp & RTC_MODE2_CTRLB_DEBASYNC) >> RTC_MODE2_CTRLB_DEBASYNC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLB_DEBASYNC_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp &= ~RTC_MODE2_CTRLB_DEBASYNC;
+	tmp |= value << RTC_MODE2_CTRLB_DEBASYNC_Pos;
+	((Rtc *)hw)->MODE2.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DEBASYNC;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLB_DEBASYNC_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DEBASYNC;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_RTCOUT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp = (tmp & RTC_MODE2_CTRLB_RTCOUT) >> RTC_MODE2_CTRLB_RTCOUT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLB_RTCOUT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp &= ~RTC_MODE2_CTRLB_RTCOUT;
+	tmp |= value << RTC_MODE2_CTRLB_RTCOUT_Pos;
+	((Rtc *)hw)->MODE2.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_RTCOUT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLB_RTCOUT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_RTCOUT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLB_DMAEN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DMAEN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_CTRLB_DMAEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp = (tmp & RTC_MODE2_CTRLB_DMAEN) >> RTC_MODE2_CTRLB_DMAEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLB_DMAEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp &= ~RTC_MODE2_CTRLB_DMAEN;
+	tmp |= value << RTC_MODE2_CTRLB_DMAEN_Pos;
+	((Rtc *)hw)->MODE2.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLB_DMAEN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DMAEN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLB_DMAEN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DMAEN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DEBF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_get_CTRLB_DEBF_bf(const void *const        hw,
+                                                                      hri_rtcmode2_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp = (tmp & RTC_MODE2_CTRLB_DEBF(mask)) >> RTC_MODE2_CTRLB_DEBF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp &= ~RTC_MODE2_CTRLB_DEBF_Msk;
+	tmp |= RTC_MODE2_CTRLB_DEBF(data);
+	((Rtc *)hw)->MODE2.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DEBF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DEBF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_read_CTRLB_DEBF_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp = (tmp & RTC_MODE2_CTRLB_DEBF_Msk) >> RTC_MODE2_CTRLB_DEBF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_ACTF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_get_CTRLB_ACTF_bf(const void *const        hw,
+                                                                      hri_rtcmode2_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp = (tmp & RTC_MODE2_CTRLB_ACTF(mask)) >> RTC_MODE2_CTRLB_ACTF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp &= ~RTC_MODE2_CTRLB_ACTF_Msk;
+	tmp |= RTC_MODE2_CTRLB_ACTF(data);
+	((Rtc *)hw)->MODE2.CTRLB.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_ACTF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_ACTF(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_read_CTRLB_ACTF_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp = (tmp & RTC_MODE2_CTRLB_ACTF_Msk) >> RTC_MODE2_CTRLB_ACTF_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_get_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CTRLB.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_read_CTRLB_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE2.CTRLB.reg;
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_PEREO0) >> RTC_MODE0_EVCTRL_PEREO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_PEREO0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_PEREO0;
+	tmp |= value << RTC_MODE0_EVCTRL_PEREO0_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_PEREO1) >> RTC_MODE0_EVCTRL_PEREO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_PEREO1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_PEREO1;
+	tmp |= value << RTC_MODE0_EVCTRL_PEREO1_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_PEREO2) >> RTC_MODE0_EVCTRL_PEREO2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_PEREO2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_PEREO2;
+	tmp |= value << RTC_MODE0_EVCTRL_PEREO2_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_PEREO3) >> RTC_MODE0_EVCTRL_PEREO3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_PEREO3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_PEREO3;
+	tmp |= value << RTC_MODE0_EVCTRL_PEREO3_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_PEREO4) >> RTC_MODE0_EVCTRL_PEREO4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_PEREO4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_PEREO4;
+	tmp |= value << RTC_MODE0_EVCTRL_PEREO4_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO5;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_PEREO5) >> RTC_MODE0_EVCTRL_PEREO5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_PEREO5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_PEREO5;
+	tmp |= value << RTC_MODE0_EVCTRL_PEREO5_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO5;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO5;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO6;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_PEREO6) >> RTC_MODE0_EVCTRL_PEREO6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_PEREO6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_PEREO6;
+	tmp |= value << RTC_MODE0_EVCTRL_PEREO6_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO6;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO6;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO7;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_PEREO7) >> RTC_MODE0_EVCTRL_PEREO7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_PEREO7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_PEREO7;
+	tmp |= value << RTC_MODE0_EVCTRL_PEREO7_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO7;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO7;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_CMPEO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_CMPEO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_CMPEO0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_CMPEO0) >> RTC_MODE0_EVCTRL_CMPEO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_CMPEO0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_CMPEO0;
+	tmp |= value << RTC_MODE0_EVCTRL_CMPEO0_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_CMPEO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_CMPEO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_CMPEO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_CMPEO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_TAMPEREO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_TAMPEREO) >> RTC_MODE0_EVCTRL_TAMPEREO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_TAMPEREO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_TAMPEREO;
+	tmp |= value << RTC_MODE0_EVCTRL_TAMPEREO_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_TAMPEREO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_TAMPEREO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_OVFEO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_OVFEO) >> RTC_MODE0_EVCTRL_OVFEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_OVFEO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_OVFEO;
+	tmp |= value << RTC_MODE0_EVCTRL_OVFEO_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_OVFEO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_OVFEO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_TAMPEVEI;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode0_get_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE0_EVCTRL_TAMPEVEI) >> RTC_MODE0_EVCTRL_TAMPEVEI_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_TAMPEVEI_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= ~RTC_MODE0_EVCTRL_TAMPEVEI;
+	tmp |= value << RTC_MODE0_EVCTRL_TAMPEVEI_Pos;
+	((Rtc *)hw)->MODE0.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_TAMPEVEI;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_TAMPEVEI;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_set_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_evctrl_reg_t hri_rtcmode0_get_EVCTRL_reg(const void *const         hw,
+                                                                    hri_rtcmode0_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.EVCTRL.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_evctrl_reg_t hri_rtcmode0_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE0.EVCTRL.reg;
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_PEREO0) >> RTC_MODE1_EVCTRL_PEREO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_PEREO0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_PEREO0;
+	tmp |= value << RTC_MODE1_EVCTRL_PEREO0_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_PEREO1) >> RTC_MODE1_EVCTRL_PEREO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_PEREO1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_PEREO1;
+	tmp |= value << RTC_MODE1_EVCTRL_PEREO1_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_PEREO2) >> RTC_MODE1_EVCTRL_PEREO2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_PEREO2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_PEREO2;
+	tmp |= value << RTC_MODE1_EVCTRL_PEREO2_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_PEREO3) >> RTC_MODE1_EVCTRL_PEREO3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_PEREO3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_PEREO3;
+	tmp |= value << RTC_MODE1_EVCTRL_PEREO3_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_PEREO4) >> RTC_MODE1_EVCTRL_PEREO4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_PEREO4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_PEREO4;
+	tmp |= value << RTC_MODE1_EVCTRL_PEREO4_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO5;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_PEREO5) >> RTC_MODE1_EVCTRL_PEREO5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_PEREO5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_PEREO5;
+	tmp |= value << RTC_MODE1_EVCTRL_PEREO5_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO5;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO5;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO6;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_PEREO6) >> RTC_MODE1_EVCTRL_PEREO6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_PEREO6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_PEREO6;
+	tmp |= value << RTC_MODE1_EVCTRL_PEREO6_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO6;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO6;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO7;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_PEREO7) >> RTC_MODE1_EVCTRL_PEREO7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_PEREO7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_PEREO7;
+	tmp |= value << RTC_MODE1_EVCTRL_PEREO7_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO7;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO7;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_CMPEO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_CMPEO0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO0) >> RTC_MODE1_EVCTRL_CMPEO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_CMPEO0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_CMPEO0;
+	tmp |= value << RTC_MODE1_EVCTRL_CMPEO0_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_CMPEO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_CMPEO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_CMPEO1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO1) >> RTC_MODE1_EVCTRL_CMPEO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_CMPEO1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_CMPEO1;
+	tmp |= value << RTC_MODE1_EVCTRL_CMPEO1_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_CMPEO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_TAMPEREO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_TAMPEREO) >> RTC_MODE1_EVCTRL_TAMPEREO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_TAMPEREO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_TAMPEREO;
+	tmp |= value << RTC_MODE1_EVCTRL_TAMPEREO_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_TAMPEREO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_TAMPEREO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_OVFEO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_OVFEO) >> RTC_MODE1_EVCTRL_OVFEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_OVFEO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_OVFEO;
+	tmp |= value << RTC_MODE1_EVCTRL_OVFEO_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_OVFEO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_OVFEO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_TAMPEVEI;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode1_get_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE1_EVCTRL_TAMPEVEI) >> RTC_MODE1_EVCTRL_TAMPEVEI_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_TAMPEVEI_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= ~RTC_MODE1_EVCTRL_TAMPEVEI;
+	tmp |= value << RTC_MODE1_EVCTRL_TAMPEVEI_Pos;
+	((Rtc *)hw)->MODE1.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_TAMPEVEI;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_TAMPEVEI;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_set_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_evctrl_reg_t hri_rtcmode1_get_EVCTRL_reg(const void *const         hw,
+                                                                    hri_rtcmode1_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.EVCTRL.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_evctrl_reg_t hri_rtcmode1_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE1.EVCTRL.reg;
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_PEREO0) >> RTC_MODE2_EVCTRL_PEREO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_PEREO0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_PEREO0;
+	tmp |= value << RTC_MODE2_EVCTRL_PEREO0_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_PEREO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_PEREO1) >> RTC_MODE2_EVCTRL_PEREO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_PEREO1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_PEREO1;
+	tmp |= value << RTC_MODE2_EVCTRL_PEREO1_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_PEREO1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_PEREO2) >> RTC_MODE2_EVCTRL_PEREO2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_PEREO2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_PEREO2;
+	tmp |= value << RTC_MODE2_EVCTRL_PEREO2_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_PEREO2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_PEREO3) >> RTC_MODE2_EVCTRL_PEREO3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_PEREO3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_PEREO3;
+	tmp |= value << RTC_MODE2_EVCTRL_PEREO3_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_PEREO3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_PEREO4) >> RTC_MODE2_EVCTRL_PEREO4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_PEREO4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_PEREO4;
+	tmp |= value << RTC_MODE2_EVCTRL_PEREO4_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_PEREO4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO5;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_PEREO5) >> RTC_MODE2_EVCTRL_PEREO5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_PEREO5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_PEREO5;
+	tmp |= value << RTC_MODE2_EVCTRL_PEREO5_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO5;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_PEREO5_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO5;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO6;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_PEREO6) >> RTC_MODE2_EVCTRL_PEREO6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_PEREO6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_PEREO6;
+	tmp |= value << RTC_MODE2_EVCTRL_PEREO6_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO6;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_PEREO6_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO6;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO7;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_PEREO7) >> RTC_MODE2_EVCTRL_PEREO7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_PEREO7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_PEREO7;
+	tmp |= value << RTC_MODE2_EVCTRL_PEREO7_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO7;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_PEREO7_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO7;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_ALARMEO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_ALARMEO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_ALARMEO0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_ALARMEO0) >> RTC_MODE2_EVCTRL_ALARMEO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_ALARMEO0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_ALARMEO0;
+	tmp |= value << RTC_MODE2_EVCTRL_ALARMEO0_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_ALARMEO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_ALARMEO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_ALARMEO0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_ALARMEO0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_TAMPEREO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_TAMPEREO) >> RTC_MODE2_EVCTRL_TAMPEREO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_TAMPEREO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_TAMPEREO;
+	tmp |= value << RTC_MODE2_EVCTRL_TAMPEREO_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_TAMPEREO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_TAMPEREO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_TAMPEREO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_OVFEO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_OVFEO) >> RTC_MODE2_EVCTRL_OVFEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_OVFEO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_OVFEO;
+	tmp |= value << RTC_MODE2_EVCTRL_OVFEO_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_OVFEO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_OVFEO;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_TAMPEVEI;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtcmode2_get_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp = (tmp & RTC_MODE2_EVCTRL_TAMPEVEI) >> RTC_MODE2_EVCTRL_TAMPEVEI_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_TAMPEVEI_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= ~RTC_MODE2_EVCTRL_TAMPEVEI;
+	tmp |= value << RTC_MODE2_EVCTRL_TAMPEVEI_Pos;
+	((Rtc *)hw)->MODE2.EVCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_TAMPEVEI;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_TAMPEVEI_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_TAMPEVEI;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_set_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_evctrl_reg_t hri_rtcmode2_get_EVCTRL_reg(const void *const         hw,
+                                                                    hri_rtcmode2_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.EVCTRL.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_evctrl_reg_t hri_rtcmode2_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE2.EVCTRL.reg;
+}
+
+static inline void hri_rtc_set_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.DBGCTRL.reg |= RTC_DBGCTRL_DBGRUN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg;
+	tmp = (tmp & RTC_DBGCTRL_DBGRUN) >> RTC_DBGCTRL_DBGRUN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg;
+	tmp &= ~RTC_DBGCTRL_DBGRUN;
+	tmp |= value << RTC_DBGCTRL_DBGRUN_Pos;
+	((Rtc *)hw)->MODE0.DBGCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.DBGCTRL.reg &= ~RTC_DBGCTRL_DBGRUN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.DBGCTRL.reg ^= RTC_DBGCTRL_DBGRUN;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.DBGCTRL.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_dbgctrl_reg_t hri_rtc_get_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtc_write_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.DBGCTRL.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.DBGCTRL.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.DBGCTRL.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_dbgctrl_reg_t hri_rtc_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE0.DBGCTRL.reg;
+}
+
+static inline void hri_rtc_set_FREQCORR_SIGN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.FREQCORR.reg |= RTC_FREQCORR_SIGN;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_FREQCORR_SIGN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg;
+	tmp = (tmp & RTC_FREQCORR_SIGN) >> RTC_FREQCORR_SIGN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_FREQCORR_SIGN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg;
+	tmp &= ~RTC_FREQCORR_SIGN;
+	tmp |= value << RTC_FREQCORR_SIGN_Pos;
+	((Rtc *)hw)->MODE0.FREQCORR.reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_FREQCORR_SIGN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.FREQCORR.reg &= ~RTC_FREQCORR_SIGN;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_FREQCORR_SIGN_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.FREQCORR.reg ^= RTC_FREQCORR_SIGN;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.FREQCORR.reg |= RTC_FREQCORR_VALUE(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_freqcorr_reg_t hri_rtc_get_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg;
+	tmp = (tmp & RTC_FREQCORR_VALUE(mask)) >> RTC_FREQCORR_VALUE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_write_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t data)
+{
+	uint8_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg;
+	tmp &= ~RTC_FREQCORR_VALUE_Msk;
+	tmp |= RTC_FREQCORR_VALUE(data);
+	((Rtc *)hw)->MODE0.FREQCORR.reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.FREQCORR.reg &= ~RTC_FREQCORR_VALUE(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.FREQCORR.reg ^= RTC_FREQCORR_VALUE(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_freqcorr_reg_t hri_rtc_read_FREQCORR_VALUE_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg;
+	tmp = (tmp & RTC_FREQCORR_VALUE_Msk) >> RTC_FREQCORR_VALUE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_set_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.FREQCORR.reg |= mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_freqcorr_reg_t hri_rtc_get_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask)
+{
+	uint8_t tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtc_write_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.FREQCORR.reg = data;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.FREQCORR.reg &= ~mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.FREQCORR.reg ^= mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_freqcorr_reg_t hri_rtc_read_FREQCORR_reg(const void *const hw)
+{
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK);
+	return ((Rtc *)hw)->MODE0.FREQCORR.reg;
+}
+
+static inline void hri_rtcmode0_set_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COUNT.reg |= RTC_MODE0_COUNT_COUNT(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_count_reg_t hri_rtcmode0_get_COUNT_COUNT_bf(const void *const        hw,
+                                                                       hri_rtcmode0_count_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	tmp = ((Rtc *)hw)->MODE0.COUNT.reg;
+	tmp = (tmp & RTC_MODE0_COUNT_COUNT(mask)) >> RTC_MODE0_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.COUNT.reg;
+	tmp &= ~RTC_MODE0_COUNT_COUNT_Msk;
+	tmp |= RTC_MODE0_COUNT_COUNT(data);
+	((Rtc *)hw)->MODE0.COUNT.reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COUNT.reg &= ~RTC_MODE0_COUNT_COUNT(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COUNT.reg ^= RTC_MODE0_COUNT_COUNT(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_count_reg_t hri_rtcmode0_read_COUNT_COUNT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	tmp = ((Rtc *)hw)->MODE0.COUNT.reg;
+	tmp = (tmp & RTC_MODE0_COUNT_COUNT_Msk) >> RTC_MODE0_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_set_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COUNT.reg |= mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_count_reg_t hri_rtcmode0_get_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	tmp = ((Rtc *)hw)->MODE0.COUNT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COUNT.reg = data;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COUNT.reg &= ~mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COUNT.reg ^= mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_count_reg_t hri_rtcmode0_read_COUNT_reg(const void *const hw)
+{
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT);
+	return ((Rtc *)hw)->MODE0.COUNT.reg;
+}
+
+static inline void hri_rtcmode1_set_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COUNT.reg |= RTC_MODE1_COUNT_COUNT(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_count_reg_t hri_rtcmode1_get_COUNT_COUNT_bf(const void *const        hw,
+                                                                       hri_rtcmode1_count_reg_t mask)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	tmp = ((Rtc *)hw)->MODE1.COUNT.reg;
+	tmp = (tmp & RTC_MODE1_COUNT_COUNT(mask)) >> RTC_MODE1_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.COUNT.reg;
+	tmp &= ~RTC_MODE1_COUNT_COUNT_Msk;
+	tmp |= RTC_MODE1_COUNT_COUNT(data);
+	((Rtc *)hw)->MODE1.COUNT.reg = tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COUNT.reg &= ~RTC_MODE1_COUNT_COUNT(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COUNT.reg ^= RTC_MODE1_COUNT_COUNT(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_count_reg_t hri_rtcmode1_read_COUNT_COUNT_bf(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	tmp = ((Rtc *)hw)->MODE1.COUNT.reg;
+	tmp = (tmp & RTC_MODE1_COUNT_COUNT_Msk) >> RTC_MODE1_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_set_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COUNT.reg |= mask;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_count_reg_t hri_rtcmode1_get_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	tmp = ((Rtc *)hw)->MODE1.COUNT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COUNT.reg = data;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COUNT.reg &= ~mask;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COUNT.reg ^= mask;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_count_reg_t hri_rtcmode1_read_COUNT_reg(const void *const hw)
+{
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT);
+	return ((Rtc *)hw)->MODE1.COUNT.reg;
+}
+
+static inline void hri_rtcmode2_set_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_SECOND(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_SECOND_bf(const void *const        hw,
+                                                                        hri_rtcmode2_clock_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_SECOND(mask)) >> RTC_MODE2_CLOCK_SECOND_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp &= ~RTC_MODE2_CLOCK_SECOND_Msk;
+	tmp |= RTC_MODE2_CLOCK_SECOND(data);
+	((Rtc *)hw)->MODE2.CLOCK.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_SECOND(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_SECOND(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_SECOND_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_SECOND_Msk) >> RTC_MODE2_CLOCK_SECOND_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_MINUTE(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_MINUTE_bf(const void *const        hw,
+                                                                        hri_rtcmode2_clock_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_MINUTE(mask)) >> RTC_MODE2_CLOCK_MINUTE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp &= ~RTC_MODE2_CLOCK_MINUTE_Msk;
+	tmp |= RTC_MODE2_CLOCK_MINUTE(data);
+	((Rtc *)hw)->MODE2.CLOCK.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_MINUTE(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_MINUTE(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_MINUTE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_MINUTE_Msk) >> RTC_MODE2_CLOCK_MINUTE_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_HOUR(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_HOUR_bf(const void *const        hw,
+                                                                      hri_rtcmode2_clock_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_HOUR(mask)) >> RTC_MODE2_CLOCK_HOUR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp &= ~RTC_MODE2_CLOCK_HOUR_Msk;
+	tmp |= RTC_MODE2_CLOCK_HOUR(data);
+	((Rtc *)hw)->MODE2.CLOCK.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_HOUR(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_HOUR(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_HOUR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_HOUR_Msk) >> RTC_MODE2_CLOCK_HOUR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_DAY(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_DAY_bf(const void *const        hw,
+                                                                     hri_rtcmode2_clock_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_DAY(mask)) >> RTC_MODE2_CLOCK_DAY_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp &= ~RTC_MODE2_CLOCK_DAY_Msk;
+	tmp |= RTC_MODE2_CLOCK_DAY(data);
+	((Rtc *)hw)->MODE2.CLOCK.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_DAY(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_DAY(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_DAY_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_DAY_Msk) >> RTC_MODE2_CLOCK_DAY_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_MONTH(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_MONTH_bf(const void *const        hw,
+                                                                       hri_rtcmode2_clock_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_MONTH(mask)) >> RTC_MODE2_CLOCK_MONTH_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp &= ~RTC_MODE2_CLOCK_MONTH_Msk;
+	tmp |= RTC_MODE2_CLOCK_MONTH(data);
+	((Rtc *)hw)->MODE2.CLOCK.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_MONTH(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_MONTH(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_MONTH_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_MONTH_Msk) >> RTC_MODE2_CLOCK_MONTH_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_YEAR(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_YEAR_bf(const void *const        hw,
+                                                                      hri_rtcmode2_clock_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_YEAR(mask)) >> RTC_MODE2_CLOCK_YEAR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp &= ~RTC_MODE2_CLOCK_YEAR_Msk;
+	tmp |= RTC_MODE2_CLOCK_YEAR(data);
+	((Rtc *)hw)->MODE2.CLOCK.reg = tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_YEAR(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_YEAR(mask);
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_YEAR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp = (tmp & RTC_MODE2_CLOCK_YEAR_Msk) >> RTC_MODE2_CLOCK_YEAR_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_set_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg |= mask;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	tmp = ((Rtc *)hw)->MODE2.CLOCK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode2_write_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg = data;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_clear_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg &= ~mask;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode2_toggle_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE2.CLOCK.reg ^= mask;
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_reg(const void *const hw)
+{
+	hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_);
+	return ((Rtc *)hw)->MODE2.CLOCK.reg;
+}
+
+static inline void hri_rtcmode1_set_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.PER.reg |= RTC_MODE1_PER_PER(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_per_reg_t hri_rtcmode1_get_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	tmp = ((Rtc *)hw)->MODE1.PER.reg;
+	tmp = (tmp & RTC_MODE1_PER_PER(mask)) >> RTC_MODE1_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.PER.reg;
+	tmp &= ~RTC_MODE1_PER_PER_Msk;
+	tmp |= RTC_MODE1_PER_PER(data);
+	((Rtc *)hw)->MODE1.PER.reg = tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.PER.reg &= ~RTC_MODE1_PER_PER(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.PER.reg ^= RTC_MODE1_PER_PER(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_per_reg_t hri_rtcmode1_read_PER_PER_bf(const void *const hw)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	tmp = ((Rtc *)hw)->MODE1.PER.reg;
+	tmp = (tmp & RTC_MODE1_PER_PER_Msk) >> RTC_MODE1_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_set_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.PER.reg |= mask;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_per_reg_t hri_rtcmode1_get_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	tmp = ((Rtc *)hw)->MODE1.PER.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.PER.reg = data;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.PER.reg &= ~mask;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.PER.reg ^= mask;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_per_reg_t hri_rtcmode1_read_PER_reg(const void *const hw)
+{
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER);
+	return ((Rtc *)hw)->MODE1.PER.reg;
+}
+
+static inline void hri_rtcmode0_set_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COMP[index].reg |= RTC_MODE0_COMP_COMP(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_get_COMP_COMP_bf(const void *const hw, uint8_t index,
+                                                                    hri_rtcmode0_comp_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.COMP[index].reg;
+	tmp = (tmp & RTC_MODE0_COMP_COMP(mask)) >> RTC_MODE0_COMP_COMP_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.COMP[index].reg;
+	tmp &= ~RTC_MODE0_COMP_COMP_Msk;
+	tmp |= RTC_MODE0_COMP_COMP(data);
+	((Rtc *)hw)->MODE0.COMP[index].reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COMP[index].reg &= ~RTC_MODE0_COMP_COMP(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COMP[index].reg ^= RTC_MODE0_COMP_COMP(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_read_COMP_COMP_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.COMP[index].reg;
+	tmp = (tmp & RTC_MODE0_COMP_COMP_Msk) >> RTC_MODE0_COMP_COMP_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_set_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COMP[index].reg |= mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_get_COMP_reg(const void *const hw, uint8_t index,
+                                                                hri_rtcmode0_comp_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0);
+	tmp = ((Rtc *)hw)->MODE0.COMP[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode0_write_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COMP[index].reg = data;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_clear_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COMP[index].reg &= ~mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode0_toggle_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.COMP[index].reg ^= mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_read_COMP_reg(const void *const hw, uint8_t index)
+{
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0);
+	return ((Rtc *)hw)->MODE0.COMP[index].reg;
+}
+
+static inline void hri_rtcmode1_set_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COMP[index].reg |= RTC_MODE1_COMP_COMP(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_get_COMP_COMP_bf(const void *const hw, uint8_t index,
+                                                                    hri_rtcmode1_comp_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.COMP[index].reg;
+	tmp = (tmp & RTC_MODE1_COMP_COMP(mask)) >> RTC_MODE1_COMP_COMP_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t data)
+{
+	uint16_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE1.COMP[index].reg;
+	tmp &= ~RTC_MODE1_COMP_COMP_Msk;
+	tmp |= RTC_MODE1_COMP_COMP(data);
+	((Rtc *)hw)->MODE1.COMP[index].reg = tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COMP[index].reg &= ~RTC_MODE1_COMP_COMP(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COMP[index].reg ^= RTC_MODE1_COMP_COMP(mask);
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_read_COMP_COMP_bf(const void *const hw, uint8_t index)
+{
+	uint16_t tmp;
+	tmp = ((Rtc *)hw)->MODE1.COMP[index].reg;
+	tmp = (tmp & RTC_MODE1_COMP_COMP_Msk) >> RTC_MODE1_COMP_COMP_Pos;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_set_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COMP[index].reg |= mask;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_get_COMP_reg(const void *const hw, uint8_t index,
+                                                                hri_rtcmode1_comp_reg_t mask)
+{
+	uint16_t tmp;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1);
+	tmp = ((Rtc *)hw)->MODE1.COMP[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtcmode1_write_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COMP[index].reg = data;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_clear_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COMP[index].reg &= ~mask;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtcmode1_toggle_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE1.COMP[index].reg ^= mask;
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_read_COMP_reg(const void *const hw, uint8_t index)
+{
+	hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1);
+	return ((Rtc *)hw)->MODE1.COMP[index].reg;
+}
+
+static inline void hri_rtc_set_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.GP[index].reg |= RTC_GP_GP(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_gp_reg_t hri_rtc_get_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.GP[index].reg;
+	tmp = (tmp & RTC_GP_GP(mask)) >> RTC_GP_GP_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_write_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.GP[index].reg;
+	tmp &= ~RTC_GP_GP_Msk;
+	tmp |= RTC_GP_GP(data);
+	((Rtc *)hw)->MODE0.GP[index].reg = tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.GP[index].reg &= ~RTC_GP_GP(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.GP[index].reg ^= RTC_GP_GP(mask);
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_gp_reg_t hri_rtc_read_GP_GP_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.GP[index].reg;
+	tmp = (tmp & RTC_GP_GP_Msk) >> RTC_GP_GP_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_set_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.GP[index].reg |= mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_gp_reg_t hri_rtc_get_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask)
+{
+	uint32_t tmp;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1);
+	tmp = ((Rtc *)hw)->MODE0.GP[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtc_write_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.GP[index].reg = data;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.GP[index].reg &= ~mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.GP[index].reg ^= mask;
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_gp_reg_t hri_rtc_read_GP_reg(const void *const hw, uint8_t index)
+{
+	hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1);
+	return ((Rtc *)hw)->MODE0.GP[index].reg;
+}
+
+static inline void hri_rtc_set_TAMPCTRL_TAMLVL0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPCTRL_TAMLVL0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_TAMLVL0) >> RTC_TAMPCTRL_TAMLVL0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_TAMLVL0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_TAMLVL0;
+	tmp |= value << RTC_TAMPCTRL_TAMLVL0_Pos;
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_TAMLVL0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPCTRL_TAMLVL1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPCTRL_TAMLVL1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_TAMLVL1) >> RTC_TAMPCTRL_TAMLVL1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_TAMLVL1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_TAMLVL1;
+	tmp |= value << RTC_TAMPCTRL_TAMLVL1_Pos;
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_TAMLVL1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPCTRL_TAMLVL2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPCTRL_TAMLVL2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_TAMLVL2) >> RTC_TAMPCTRL_TAMLVL2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_TAMLVL2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_TAMLVL2;
+	tmp |= value << RTC_TAMPCTRL_TAMLVL2_Pos;
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_TAMLVL2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPCTRL_TAMLVL3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPCTRL_TAMLVL3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_TAMLVL3) >> RTC_TAMPCTRL_TAMLVL3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_TAMLVL3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_TAMLVL3;
+	tmp |= value << RTC_TAMPCTRL_TAMLVL3_Pos;
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_TAMLVL3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPCTRL_TAMLVL4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPCTRL_TAMLVL4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_TAMLVL4) >> RTC_TAMPCTRL_TAMLVL4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_TAMLVL4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_TAMLVL4;
+	tmp |= value << RTC_TAMPCTRL_TAMLVL4_Pos;
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_TAMLVL4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPCTRL_DEBNC0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPCTRL_DEBNC0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_DEBNC0) >> RTC_TAMPCTRL_DEBNC0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_DEBNC0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_DEBNC0;
+	tmp |= value << RTC_TAMPCTRL_DEBNC0_Pos;
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_DEBNC0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_DEBNC0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPCTRL_DEBNC1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPCTRL_DEBNC1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_DEBNC1) >> RTC_TAMPCTRL_DEBNC1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_DEBNC1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_DEBNC1;
+	tmp |= value << RTC_TAMPCTRL_DEBNC1_Pos;
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_DEBNC1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_DEBNC1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPCTRL_DEBNC2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPCTRL_DEBNC2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_DEBNC2) >> RTC_TAMPCTRL_DEBNC2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_DEBNC2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_DEBNC2;
+	tmp |= value << RTC_TAMPCTRL_DEBNC2_Pos;
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_DEBNC2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_DEBNC2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPCTRL_DEBNC3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPCTRL_DEBNC3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_DEBNC3) >> RTC_TAMPCTRL_DEBNC3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_DEBNC3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_DEBNC3;
+	tmp |= value << RTC_TAMPCTRL_DEBNC3_Pos;
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_DEBNC3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_DEBNC3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPCTRL_DEBNC4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPCTRL_DEBNC4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_DEBNC4) >> RTC_TAMPCTRL_DEBNC4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_DEBNC4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_DEBNC4;
+	tmp |= value << RTC_TAMPCTRL_DEBNC4_Pos;
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_DEBNC4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_DEBNC4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN0ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_IN0ACT(mask)) >> RTC_TAMPCTRL_IN0ACT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_IN0ACT_Msk;
+	tmp |= RTC_TAMPCTRL_IN0ACT(data);
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN0ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN0ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN0ACT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_IN0ACT_Msk) >> RTC_TAMPCTRL_IN0ACT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_set_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN1ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_IN1ACT(mask)) >> RTC_TAMPCTRL_IN1ACT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_IN1ACT_Msk;
+	tmp |= RTC_TAMPCTRL_IN1ACT(data);
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN1ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN1ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN1ACT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_IN1ACT_Msk) >> RTC_TAMPCTRL_IN1ACT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_set_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN2ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_IN2ACT(mask)) >> RTC_TAMPCTRL_IN2ACT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_IN2ACT_Msk;
+	tmp |= RTC_TAMPCTRL_IN2ACT(data);
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN2ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN2ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN2ACT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_IN2ACT_Msk) >> RTC_TAMPCTRL_IN2ACT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_set_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN3ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_IN3ACT(mask)) >> RTC_TAMPCTRL_IN3ACT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_IN3ACT_Msk;
+	tmp |= RTC_TAMPCTRL_IN3ACT(data);
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN3ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN3ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN3ACT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_IN3ACT_Msk) >> RTC_TAMPCTRL_IN3ACT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_set_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN4ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_IN4ACT(mask)) >> RTC_TAMPCTRL_IN4ACT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= ~RTC_TAMPCTRL_IN4ACT_Msk;
+	tmp |= RTC_TAMPCTRL_IN4ACT(data);
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN4ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN4ACT(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN4ACT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp = (tmp & RTC_TAMPCTRL_IN4ACT_Msk) >> RTC_TAMPCTRL_IN4ACT_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_set_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtc_write_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE0.TAMPCTRL.reg;
+}
+
+static inline void hri_rtc_set_TAMPID_TAMPID0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPID_TAMPID0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp = (tmp & RTC_TAMPID_TAMPID0) >> RTC_TAMPID_TAMPID0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPID_TAMPID0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp &= ~RTC_TAMPID_TAMPID0;
+	tmp |= value << RTC_TAMPID_TAMPID0_Pos;
+	((Rtc *)hw)->MODE0.TAMPID.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPID_TAMPID0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPID_TAMPID0_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID0;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPID_TAMPID1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPID_TAMPID1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp = (tmp & RTC_TAMPID_TAMPID1) >> RTC_TAMPID_TAMPID1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPID_TAMPID1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp &= ~RTC_TAMPID_TAMPID1;
+	tmp |= value << RTC_TAMPID_TAMPID1_Pos;
+	((Rtc *)hw)->MODE0.TAMPID.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPID_TAMPID1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPID_TAMPID1_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID1;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPID_TAMPID2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPID_TAMPID2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp = (tmp & RTC_TAMPID_TAMPID2) >> RTC_TAMPID_TAMPID2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPID_TAMPID2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp &= ~RTC_TAMPID_TAMPID2;
+	tmp |= value << RTC_TAMPID_TAMPID2_Pos;
+	((Rtc *)hw)->MODE0.TAMPID.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPID_TAMPID2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPID_TAMPID2_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID2;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPID_TAMPID3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPID_TAMPID3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp = (tmp & RTC_TAMPID_TAMPID3) >> RTC_TAMPID_TAMPID3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPID_TAMPID3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp &= ~RTC_TAMPID_TAMPID3;
+	tmp |= value << RTC_TAMPID_TAMPID3_Pos;
+	((Rtc *)hw)->MODE0.TAMPID.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPID_TAMPID3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPID_TAMPID3_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID3;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPID_TAMPID4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPID_TAMPID4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp = (tmp & RTC_TAMPID_TAMPID4) >> RTC_TAMPID_TAMPID4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPID_TAMPID4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp &= ~RTC_TAMPID_TAMPID4;
+	tmp |= value << RTC_TAMPID_TAMPID4_Pos;
+	((Rtc *)hw)->MODE0.TAMPID.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPID_TAMPID4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPID_TAMPID4_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID4;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPID_TAMPEVT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPEVT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_rtc_get_TAMPID_TAMPEVT_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp = (tmp & RTC_TAMPID_TAMPEVT) >> RTC_TAMPID_TAMPEVT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_rtc_write_TAMPID_TAMPEVT_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp &= ~RTC_TAMPID_TAMPEVT;
+	tmp |= value << RTC_TAMPID_TAMPEVT_Pos;
+	((Rtc *)hw)->MODE0.TAMPID.reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPID_TAMPEVT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPEVT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPID_TAMPEVT_bit(const void *const hw)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPEVT;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_set_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampid_reg_t hri_rtc_get_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.TAMPID.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtc_write_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.TAMPID.reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_tampid_reg_t hri_rtc_read_TAMPID_reg(const void *const hw)
+{
+	return ((Rtc *)hw)->MODE0.TAMPID.reg;
+}
+
+static inline void hri_rtc_set_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.BKUP[index].reg |= RTC_BKUP_BKUP(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_bkup_reg_t hri_rtc_get_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg;
+	tmp = (tmp & RTC_BKUP_BKUP(mask)) >> RTC_BKUP_BKUP_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_write_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t data)
+{
+	uint32_t tmp;
+	RTC_CRITICAL_SECTION_ENTER();
+	tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg;
+	tmp &= ~RTC_BKUP_BKUP_Msk;
+	tmp |= RTC_BKUP_BKUP(data);
+	((Rtc *)hw)->MODE0.BKUP[index].reg = tmp;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.BKUP[index].reg &= ~RTC_BKUP_BKUP(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.BKUP[index].reg ^= RTC_BKUP_BKUP(mask);
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_bkup_reg_t hri_rtc_read_BKUP_BKUP_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg;
+	tmp = (tmp & RTC_BKUP_BKUP_Msk) >> RTC_BKUP_BKUP_Pos;
+	return tmp;
+}
+
+static inline void hri_rtc_set_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.BKUP[index].reg |= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_bkup_reg_t hri_rtc_get_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_rtc_write_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t data)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.BKUP[index].reg = data;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_clear_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.BKUP[index].reg &= ~mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_rtc_toggle_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask)
+{
+	RTC_CRITICAL_SECTION_ENTER();
+	((Rtc *)hw)->MODE0.BKUP[index].reg ^= mask;
+	RTC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_rtc_bkup_reg_t hri_rtc_read_BKUP_reg(const void *const hw, uint8_t index)
+{
+	return ((Rtc *)hw)->MODE0.BKUP[index].reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_RTC_L22_H_INCLUDED */
+#endif /* _SAML22_RTC_COMPONENT_ */
diff --git a/watch-library/hardware/hri/hri_sercom_l22.h b/watch-library/hardware/hri/hri_sercom_l22.h
new file mode 100644
index 00000000..6d97ca8a
--- /dev/null
+++ b/watch-library/hardware/hri/hri_sercom_l22.h
@@ -0,0 +1,7827 @@
+/**
+ * \file
+ *
+ * \brief SAM SERCOM
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_SERCOM_COMPONENT_
+#ifndef _HRI_SERCOM_L22_H_INCLUDED_
+#define _HRI_SERCOM_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_SERCOM_CRITICAL_SECTIONS)
+#define SERCOM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define SERCOM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define SERCOM_CRITICAL_SECTION_ENTER()
+#define SERCOM_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_sercomi2cm_status_reg_t;
+typedef uint16_t hri_sercomi2cs_status_reg_t;
+typedef uint16_t hri_sercomspi_status_reg_t;
+typedef uint16_t hri_sercomusart_baud_reg_t;
+typedef uint16_t hri_sercomusart_data_reg_t;
+typedef uint16_t hri_sercomusart_status_reg_t;
+typedef uint32_t hri_sercomi2cm_addr_reg_t;
+typedef uint32_t hri_sercomi2cm_baud_reg_t;
+typedef uint32_t hri_sercomi2cm_ctrla_reg_t;
+typedef uint32_t hri_sercomi2cm_ctrlb_reg_t;
+typedef uint32_t hri_sercomi2cm_syncbusy_reg_t;
+typedef uint32_t hri_sercomi2cs_addr_reg_t;
+typedef uint32_t hri_sercomi2cs_ctrla_reg_t;
+typedef uint32_t hri_sercomi2cs_ctrlb_reg_t;
+typedef uint32_t hri_sercomi2cs_syncbusy_reg_t;
+typedef uint32_t hri_sercomspi_addr_reg_t;
+typedef uint32_t hri_sercomspi_ctrla_reg_t;
+typedef uint32_t hri_sercomspi_ctrlb_reg_t;
+typedef uint32_t hri_sercomspi_data_reg_t;
+typedef uint32_t hri_sercomspi_syncbusy_reg_t;
+typedef uint32_t hri_sercomusart_ctrla_reg_t;
+typedef uint32_t hri_sercomusart_ctrlb_reg_t;
+typedef uint32_t hri_sercomusart_ctrlc_reg_t;
+typedef uint32_t hri_sercomusart_syncbusy_reg_t;
+typedef uint8_t  hri_sercomi2cm_data_reg_t;
+typedef uint8_t  hri_sercomi2cm_dbgctrl_reg_t;
+typedef uint8_t  hri_sercomi2cm_intenset_reg_t;
+typedef uint8_t  hri_sercomi2cm_intflag_reg_t;
+typedef uint8_t  hri_sercomi2cs_data_reg_t;
+typedef uint8_t  hri_sercomi2cs_intenset_reg_t;
+typedef uint8_t  hri_sercomi2cs_intflag_reg_t;
+typedef uint8_t  hri_sercomspi_baud_reg_t;
+typedef uint8_t  hri_sercomspi_dbgctrl_reg_t;
+typedef uint8_t  hri_sercomspi_intenset_reg_t;
+typedef uint8_t  hri_sercomspi_intflag_reg_t;
+typedef uint8_t  hri_sercomusart_dbgctrl_reg_t;
+typedef uint8_t  hri_sercomusart_intenset_reg_t;
+typedef uint8_t  hri_sercomusart_intflag_reg_t;
+typedef uint8_t  hri_sercomusart_rxerrcnt_reg_t;
+typedef uint8_t  hri_sercomusart_rxpl_reg_t;
+
+static inline void hri_sercomi2cm_wait_for_sync(const void *const hw, hri_sercomi2cm_syncbusy_reg_t reg)
+{
+	while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_sercomi2cm_is_syncing(const void *const hw, hri_sercomi2cm_syncbusy_reg_t reg)
+{
+	return ((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg;
+}
+
+static inline void hri_sercomi2cs_wait_for_sync(const void *const hw, hri_sercomi2cs_syncbusy_reg_t reg)
+{
+	while (((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_sercomi2cs_is_syncing(const void *const hw, hri_sercomi2cs_syncbusy_reg_t reg)
+{
+	return ((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg;
+}
+
+static inline void hri_sercomspi_wait_for_sync(const void *const hw, hri_sercomspi_syncbusy_reg_t reg)
+{
+	while (((Sercom *)hw)->SPI.SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_sercomspi_is_syncing(const void *const hw, hri_sercomspi_syncbusy_reg_t reg)
+{
+	return ((Sercom *)hw)->SPI.SYNCBUSY.reg & reg;
+}
+
+static inline void hri_sercomusart_wait_for_sync(const void *const hw, hri_sercomusart_syncbusy_reg_t reg)
+{
+	while (((Sercom *)hw)->USART.SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_sercomusart_is_syncing(const void *const hw, hri_sercomusart_syncbusy_reg_t reg)
+{
+	return ((Sercom *)hw)->USART.SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_sercomi2cm_get_INTFLAG_MB_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) >> SERCOM_I2CM_INTFLAG_MB_Pos;
+}
+
+static inline void hri_sercomi2cm_clear_INTFLAG_MB_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB;
+}
+
+static inline bool hri_sercomi2cm_get_INTFLAG_SB_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) >> SERCOM_I2CM_INTFLAG_SB_Pos;
+}
+
+static inline void hri_sercomi2cm_clear_INTFLAG_SB_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB;
+}
+
+static inline bool hri_sercomi2cm_get_INTFLAG_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_ERROR) >> SERCOM_I2CM_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_sercomi2cm_clear_INTFLAG_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_ERROR;
+}
+
+static inline bool hri_sercomi2cm_get_interrupt_MB_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) >> SERCOM_I2CM_INTFLAG_MB_Pos;
+}
+
+static inline void hri_sercomi2cm_clear_interrupt_MB_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB;
+}
+
+static inline bool hri_sercomi2cm_get_interrupt_SB_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) >> SERCOM_I2CM_INTFLAG_SB_Pos;
+}
+
+static inline void hri_sercomi2cm_clear_interrupt_SB_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB;
+}
+
+static inline bool hri_sercomi2cm_get_interrupt_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_ERROR) >> SERCOM_I2CM_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_sercomi2cm_clear_interrupt_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_ERROR;
+}
+
+static inline hri_sercomi2cm_intflag_reg_t hri_sercomi2cm_get_INTFLAG_reg(const void *const            hw,
+                                                                          hri_sercomi2cm_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomi2cm_intflag_reg_t hri_sercomi2cm_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CM.INTFLAG.reg;
+}
+
+static inline void hri_sercomi2cm_clear_INTFLAG_reg(const void *const hw, hri_sercomi2cm_intflag_reg_t mask)
+{
+	((Sercom *)hw)->I2CM.INTFLAG.reg = mask;
+}
+
+static inline bool hri_sercomi2cs_get_INTFLAG_PREC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) >> SERCOM_I2CS_INTFLAG_PREC_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_INTFLAG_PREC_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC;
+}
+
+static inline bool hri_sercomi2cs_get_INTFLAG_AMATCH_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) >> SERCOM_I2CS_INTFLAG_AMATCH_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_INTFLAG_AMATCH_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH;
+}
+
+static inline bool hri_sercomi2cs_get_INTFLAG_DRDY_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) >> SERCOM_I2CS_INTFLAG_DRDY_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_INTFLAG_DRDY_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY;
+}
+
+static inline bool hri_sercomi2cs_get_INTFLAG_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_ERROR) >> SERCOM_I2CS_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_INTFLAG_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_ERROR;
+}
+
+static inline bool hri_sercomi2cs_get_interrupt_PREC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) >> SERCOM_I2CS_INTFLAG_PREC_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_interrupt_PREC_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC;
+}
+
+static inline bool hri_sercomi2cs_get_interrupt_AMATCH_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) >> SERCOM_I2CS_INTFLAG_AMATCH_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_interrupt_AMATCH_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH;
+}
+
+static inline bool hri_sercomi2cs_get_interrupt_DRDY_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) >> SERCOM_I2CS_INTFLAG_DRDY_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_interrupt_DRDY_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY;
+}
+
+static inline bool hri_sercomi2cs_get_interrupt_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_ERROR) >> SERCOM_I2CS_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_interrupt_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_ERROR;
+}
+
+static inline hri_sercomi2cs_intflag_reg_t hri_sercomi2cs_get_INTFLAG_reg(const void *const            hw,
+                                                                          hri_sercomi2cs_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomi2cs_intflag_reg_t hri_sercomi2cs_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CS.INTFLAG.reg;
+}
+
+static inline void hri_sercomi2cs_clear_INTFLAG_reg(const void *const hw, hri_sercomi2cs_intflag_reg_t mask)
+{
+	((Sercom *)hw)->I2CS.INTFLAG.reg = mask;
+}
+
+static inline bool hri_sercomspi_get_INTFLAG_DRE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE) >> SERCOM_SPI_INTFLAG_DRE_Pos;
+}
+
+static inline void hri_sercomspi_clear_INTFLAG_DRE_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_DRE;
+}
+
+static inline bool hri_sercomspi_get_INTFLAG_TXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) >> SERCOM_SPI_INTFLAG_TXC_Pos;
+}
+
+static inline void hri_sercomspi_clear_INTFLAG_TXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC;
+}
+
+static inline bool hri_sercomspi_get_INTFLAG_RXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC) >> SERCOM_SPI_INTFLAG_RXC_Pos;
+}
+
+static inline void hri_sercomspi_clear_INTFLAG_RXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_RXC;
+}
+
+static inline bool hri_sercomspi_get_INTFLAG_SSL_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_SSL) >> SERCOM_SPI_INTFLAG_SSL_Pos;
+}
+
+static inline void hri_sercomspi_clear_INTFLAG_SSL_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_SSL;
+}
+
+static inline bool hri_sercomspi_get_INTFLAG_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) >> SERCOM_SPI_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_sercomspi_clear_INTFLAG_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_ERROR;
+}
+
+static inline bool hri_sercomspi_get_interrupt_DRE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE) >> SERCOM_SPI_INTFLAG_DRE_Pos;
+}
+
+static inline void hri_sercomspi_clear_interrupt_DRE_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_DRE;
+}
+
+static inline bool hri_sercomspi_get_interrupt_TXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) >> SERCOM_SPI_INTFLAG_TXC_Pos;
+}
+
+static inline void hri_sercomspi_clear_interrupt_TXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC;
+}
+
+static inline bool hri_sercomspi_get_interrupt_RXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC) >> SERCOM_SPI_INTFLAG_RXC_Pos;
+}
+
+static inline void hri_sercomspi_clear_interrupt_RXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_RXC;
+}
+
+static inline bool hri_sercomspi_get_interrupt_SSL_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_SSL) >> SERCOM_SPI_INTFLAG_SSL_Pos;
+}
+
+static inline void hri_sercomspi_clear_interrupt_SSL_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_SSL;
+}
+
+static inline bool hri_sercomspi_get_interrupt_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) >> SERCOM_SPI_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_sercomspi_clear_interrupt_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_ERROR;
+}
+
+static inline hri_sercomspi_intflag_reg_t hri_sercomspi_get_INTFLAG_reg(const void *const           hw,
+                                                                        hri_sercomspi_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->SPI.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomspi_intflag_reg_t hri_sercomspi_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->SPI.INTFLAG.reg;
+}
+
+static inline void hri_sercomspi_clear_INTFLAG_reg(const void *const hw, hri_sercomspi_intflag_reg_t mask)
+{
+	((Sercom *)hw)->SPI.INTFLAG.reg = mask;
+}
+
+static inline bool hri_sercomusart_get_INTFLAG_DRE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos;
+}
+
+static inline void hri_sercomusart_clear_INTFLAG_DRE_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_DRE;
+}
+
+static inline bool hri_sercomusart_get_INTFLAG_TXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos;
+}
+
+static inline void hri_sercomusart_clear_INTFLAG_TXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_TXC;
+}
+
+static inline bool hri_sercomusart_get_INTFLAG_RXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos;
+}
+
+static inline void hri_sercomusart_clear_INTFLAG_RXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXC;
+}
+
+static inline bool hri_sercomusart_get_INTFLAG_RXS_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXS) >> SERCOM_USART_INTFLAG_RXS_Pos;
+}
+
+static inline void hri_sercomusart_clear_INTFLAG_RXS_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXS;
+}
+
+static inline bool hri_sercomusart_get_INTFLAG_CTSIC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_CTSIC) >> SERCOM_USART_INTFLAG_CTSIC_Pos;
+}
+
+static inline void hri_sercomusart_clear_INTFLAG_CTSIC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC;
+}
+
+static inline bool hri_sercomusart_get_INTFLAG_RXBRK_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXBRK) >> SERCOM_USART_INTFLAG_RXBRK_Pos;
+}
+
+static inline void hri_sercomusart_clear_INTFLAG_RXBRK_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK;
+}
+
+static inline bool hri_sercomusart_get_INTFLAG_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) >> SERCOM_USART_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_sercomusart_clear_INTFLAG_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR;
+}
+
+static inline bool hri_sercomusart_get_interrupt_DRE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos;
+}
+
+static inline void hri_sercomusart_clear_interrupt_DRE_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_DRE;
+}
+
+static inline bool hri_sercomusart_get_interrupt_TXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos;
+}
+
+static inline void hri_sercomusart_clear_interrupt_TXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_TXC;
+}
+
+static inline bool hri_sercomusart_get_interrupt_RXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos;
+}
+
+static inline void hri_sercomusart_clear_interrupt_RXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXC;
+}
+
+static inline bool hri_sercomusart_get_interrupt_RXS_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXS) >> SERCOM_USART_INTFLAG_RXS_Pos;
+}
+
+static inline void hri_sercomusart_clear_interrupt_RXS_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXS;
+}
+
+static inline bool hri_sercomusart_get_interrupt_CTSIC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_CTSIC) >> SERCOM_USART_INTFLAG_CTSIC_Pos;
+}
+
+static inline void hri_sercomusart_clear_interrupt_CTSIC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC;
+}
+
+static inline bool hri_sercomusart_get_interrupt_RXBRK_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXBRK) >> SERCOM_USART_INTFLAG_RXBRK_Pos;
+}
+
+static inline void hri_sercomusart_clear_interrupt_RXBRK_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK;
+}
+
+static inline bool hri_sercomusart_get_interrupt_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) >> SERCOM_USART_INTFLAG_ERROR_Pos;
+}
+
+static inline void hri_sercomusart_clear_interrupt_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR;
+}
+
+static inline hri_sercomusart_intflag_reg_t hri_sercomusart_get_INTFLAG_reg(const void *const             hw,
+                                                                            hri_sercomusart_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->USART.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomusart_intflag_reg_t hri_sercomusart_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.INTFLAG.reg;
+}
+
+static inline void hri_sercomusart_clear_INTFLAG_reg(const void *const hw, hri_sercomusart_intflag_reg_t mask)
+{
+	((Sercom *)hw)->USART.INTFLAG.reg = mask;
+}
+
+static inline void hri_sercomi2cm_set_INTEN_MB_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_MB;
+}
+
+static inline bool hri_sercomi2cm_get_INTEN_MB_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_MB) >> SERCOM_I2CM_INTENSET_MB_Pos;
+}
+
+static inline void hri_sercomi2cm_write_INTEN_MB_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_MB;
+	} else {
+		((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_MB;
+	}
+}
+
+static inline void hri_sercomi2cm_clear_INTEN_MB_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_MB;
+}
+
+static inline void hri_sercomi2cm_set_INTEN_SB_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_SB;
+}
+
+static inline bool hri_sercomi2cm_get_INTEN_SB_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_SB) >> SERCOM_I2CM_INTENSET_SB_Pos;
+}
+
+static inline void hri_sercomi2cm_write_INTEN_SB_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_SB;
+	} else {
+		((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_SB;
+	}
+}
+
+static inline void hri_sercomi2cm_clear_INTEN_SB_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_SB;
+}
+
+static inline void hri_sercomi2cm_set_INTEN_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_ERROR;
+}
+
+static inline bool hri_sercomi2cm_get_INTEN_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_ERROR) >> SERCOM_I2CM_INTENSET_ERROR_Pos;
+}
+
+static inline void hri_sercomi2cm_write_INTEN_ERROR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_ERROR;
+	} else {
+		((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_ERROR;
+	}
+}
+
+static inline void hri_sercomi2cm_clear_INTEN_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_ERROR;
+}
+
+static inline void hri_sercomi2cm_set_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t mask)
+{
+	((Sercom *)hw)->I2CM.INTENSET.reg = mask;
+}
+
+static inline hri_sercomi2cm_intenset_reg_t hri_sercomi2cm_get_INTEN_reg(const void *const             hw,
+                                                                         hri_sercomi2cm_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomi2cm_intenset_reg_t hri_sercomi2cm_read_INTEN_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CM.INTENSET.reg;
+}
+
+static inline void hri_sercomi2cm_write_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t data)
+{
+	((Sercom *)hw)->I2CM.INTENSET.reg = data;
+	((Sercom *)hw)->I2CM.INTENCLR.reg = ~data;
+}
+
+static inline void hri_sercomi2cm_clear_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t mask)
+{
+	((Sercom *)hw)->I2CM.INTENCLR.reg = mask;
+}
+
+static inline void hri_sercomi2cs_set_INTEN_PREC_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_PREC;
+}
+
+static inline bool hri_sercomi2cs_get_INTEN_PREC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_PREC) >> SERCOM_I2CS_INTENSET_PREC_Pos;
+}
+
+static inline void hri_sercomi2cs_write_INTEN_PREC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC;
+	} else {
+		((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_PREC;
+	}
+}
+
+static inline void hri_sercomi2cs_clear_INTEN_PREC_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC;
+}
+
+static inline void hri_sercomi2cs_set_INTEN_AMATCH_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_AMATCH;
+}
+
+static inline bool hri_sercomi2cs_get_INTEN_AMATCH_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_AMATCH) >> SERCOM_I2CS_INTENSET_AMATCH_Pos;
+}
+
+static inline void hri_sercomi2cs_write_INTEN_AMATCH_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_AMATCH;
+	} else {
+		((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_AMATCH;
+	}
+}
+
+static inline void hri_sercomi2cs_clear_INTEN_AMATCH_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_AMATCH;
+}
+
+static inline void hri_sercomi2cs_set_INTEN_DRDY_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_DRDY;
+}
+
+static inline bool hri_sercomi2cs_get_INTEN_DRDY_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_DRDY) >> SERCOM_I2CS_INTENSET_DRDY_Pos;
+}
+
+static inline void hri_sercomi2cs_write_INTEN_DRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_DRDY;
+	} else {
+		((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_DRDY;
+	}
+}
+
+static inline void hri_sercomi2cs_clear_INTEN_DRDY_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_DRDY;
+}
+
+static inline void hri_sercomi2cs_set_INTEN_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_ERROR;
+}
+
+static inline bool hri_sercomi2cs_get_INTEN_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_ERROR) >> SERCOM_I2CS_INTENSET_ERROR_Pos;
+}
+
+static inline void hri_sercomi2cs_write_INTEN_ERROR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_ERROR;
+	} else {
+		((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_ERROR;
+	}
+}
+
+static inline void hri_sercomi2cs_clear_INTEN_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_ERROR;
+}
+
+static inline void hri_sercomi2cs_set_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t mask)
+{
+	((Sercom *)hw)->I2CS.INTENSET.reg = mask;
+}
+
+static inline hri_sercomi2cs_intenset_reg_t hri_sercomi2cs_get_INTEN_reg(const void *const             hw,
+                                                                         hri_sercomi2cs_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomi2cs_intenset_reg_t hri_sercomi2cs_read_INTEN_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CS.INTENSET.reg;
+}
+
+static inline void hri_sercomi2cs_write_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t data)
+{
+	((Sercom *)hw)->I2CS.INTENSET.reg = data;
+	((Sercom *)hw)->I2CS.INTENCLR.reg = ~data;
+}
+
+static inline void hri_sercomi2cs_clear_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t mask)
+{
+	((Sercom *)hw)->I2CS.INTENCLR.reg = mask;
+}
+
+static inline void hri_sercomspi_set_INTEN_DRE_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_DRE;
+}
+
+static inline bool hri_sercomspi_get_INTEN_DRE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_DRE) >> SERCOM_SPI_INTENSET_DRE_Pos;
+}
+
+static inline void hri_sercomspi_write_INTEN_DRE_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_DRE;
+	} else {
+		((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_DRE;
+	}
+}
+
+static inline void hri_sercomspi_clear_INTEN_DRE_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_DRE;
+}
+
+static inline void hri_sercomspi_set_INTEN_TXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_TXC;
+}
+
+static inline bool hri_sercomspi_get_INTEN_TXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_TXC) >> SERCOM_SPI_INTENSET_TXC_Pos;
+}
+
+static inline void hri_sercomspi_write_INTEN_TXC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_TXC;
+	} else {
+		((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_TXC;
+	}
+}
+
+static inline void hri_sercomspi_clear_INTEN_TXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_TXC;
+}
+
+static inline void hri_sercomspi_set_INTEN_RXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_RXC;
+}
+
+static inline bool hri_sercomspi_get_INTEN_RXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_RXC) >> SERCOM_SPI_INTENSET_RXC_Pos;
+}
+
+static inline void hri_sercomspi_write_INTEN_RXC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_RXC;
+	} else {
+		((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_RXC;
+	}
+}
+
+static inline void hri_sercomspi_clear_INTEN_RXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_RXC;
+}
+
+static inline void hri_sercomspi_set_INTEN_SSL_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_SSL;
+}
+
+static inline bool hri_sercomspi_get_INTEN_SSL_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_SSL) >> SERCOM_SPI_INTENSET_SSL_Pos;
+}
+
+static inline void hri_sercomspi_write_INTEN_SSL_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_SSL;
+	} else {
+		((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_SSL;
+	}
+}
+
+static inline void hri_sercomspi_clear_INTEN_SSL_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_SSL;
+}
+
+static inline void hri_sercomspi_set_INTEN_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_ERROR;
+}
+
+static inline bool hri_sercomspi_get_INTEN_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_ERROR) >> SERCOM_SPI_INTENSET_ERROR_Pos;
+}
+
+static inline void hri_sercomspi_write_INTEN_ERROR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_ERROR;
+	} else {
+		((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_ERROR;
+	}
+}
+
+static inline void hri_sercomspi_clear_INTEN_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_ERROR;
+}
+
+static inline void hri_sercomspi_set_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t mask)
+{
+	((Sercom *)hw)->SPI.INTENSET.reg = mask;
+}
+
+static inline hri_sercomspi_intenset_reg_t hri_sercomspi_get_INTEN_reg(const void *const            hw,
+                                                                       hri_sercomspi_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->SPI.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomspi_intenset_reg_t hri_sercomspi_read_INTEN_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->SPI.INTENSET.reg;
+}
+
+static inline void hri_sercomspi_write_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t data)
+{
+	((Sercom *)hw)->SPI.INTENSET.reg = data;
+	((Sercom *)hw)->SPI.INTENCLR.reg = ~data;
+}
+
+static inline void hri_sercomspi_clear_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t mask)
+{
+	((Sercom *)hw)->SPI.INTENCLR.reg = mask;
+}
+
+static inline void hri_sercomusart_set_INTEN_DRE_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE;
+}
+
+static inline bool hri_sercomusart_get_INTEN_DRE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_DRE) >> SERCOM_USART_INTENSET_DRE_Pos;
+}
+
+static inline void hri_sercomusart_write_INTEN_DRE_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_DRE;
+	} else {
+		((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE;
+	}
+}
+
+static inline void hri_sercomusart_clear_INTEN_DRE_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_DRE;
+}
+
+static inline void hri_sercomusart_set_INTEN_TXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC;
+}
+
+static inline bool hri_sercomusart_get_INTEN_TXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_TXC) >> SERCOM_USART_INTENSET_TXC_Pos;
+}
+
+static inline void hri_sercomusart_write_INTEN_TXC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_TXC;
+	} else {
+		((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC;
+	}
+}
+
+static inline void hri_sercomusart_clear_INTEN_TXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_TXC;
+}
+
+static inline void hri_sercomusart_set_INTEN_RXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXC;
+}
+
+static inline bool hri_sercomusart_get_INTEN_RXC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXC) >> SERCOM_USART_INTENSET_RXC_Pos;
+}
+
+static inline void hri_sercomusart_write_INTEN_RXC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXC;
+	} else {
+		((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXC;
+	}
+}
+
+static inline void hri_sercomusart_clear_INTEN_RXC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXC;
+}
+
+static inline void hri_sercomusart_set_INTEN_RXS_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXS;
+}
+
+static inline bool hri_sercomusart_get_INTEN_RXS_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXS) >> SERCOM_USART_INTENSET_RXS_Pos;
+}
+
+static inline void hri_sercomusart_write_INTEN_RXS_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXS;
+	} else {
+		((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXS;
+	}
+}
+
+static inline void hri_sercomusart_clear_INTEN_RXS_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXS;
+}
+
+static inline void hri_sercomusart_set_INTEN_CTSIC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_CTSIC;
+}
+
+static inline bool hri_sercomusart_get_INTEN_CTSIC_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_CTSIC) >> SERCOM_USART_INTENSET_CTSIC_Pos;
+}
+
+static inline void hri_sercomusart_write_INTEN_CTSIC_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_CTSIC;
+	} else {
+		((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_CTSIC;
+	}
+}
+
+static inline void hri_sercomusart_clear_INTEN_CTSIC_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_CTSIC;
+}
+
+static inline void hri_sercomusart_set_INTEN_RXBRK_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXBRK;
+}
+
+static inline bool hri_sercomusart_get_INTEN_RXBRK_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXBRK) >> SERCOM_USART_INTENSET_RXBRK_Pos;
+}
+
+static inline void hri_sercomusart_write_INTEN_RXBRK_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXBRK;
+	} else {
+		((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXBRK;
+	}
+}
+
+static inline void hri_sercomusart_clear_INTEN_RXBRK_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXBRK;
+}
+
+static inline void hri_sercomusart_set_INTEN_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_ERROR;
+}
+
+static inline bool hri_sercomusart_get_INTEN_ERROR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_ERROR) >> SERCOM_USART_INTENSET_ERROR_Pos;
+}
+
+static inline void hri_sercomusart_write_INTEN_ERROR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_ERROR;
+	} else {
+		((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_ERROR;
+	}
+}
+
+static inline void hri_sercomusart_clear_INTEN_ERROR_bit(const void *const hw)
+{
+	((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_ERROR;
+}
+
+static inline void hri_sercomusart_set_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t mask)
+{
+	((Sercom *)hw)->USART.INTENSET.reg = mask;
+}
+
+static inline hri_sercomusart_intenset_reg_t hri_sercomusart_get_INTEN_reg(const void *const              hw,
+                                                                           hri_sercomusart_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->USART.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomusart_intenset_reg_t hri_sercomusart_read_INTEN_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.INTENSET.reg;
+}
+
+static inline void hri_sercomusart_write_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t data)
+{
+	((Sercom *)hw)->USART.INTENSET.reg = data;
+	((Sercom *)hw)->USART.INTENCLR.reg = ~data;
+}
+
+static inline void hri_sercomusart_clear_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t mask)
+{
+	((Sercom *)hw)->USART.INTENCLR.reg = mask;
+}
+
+static inline bool hri_sercomi2cm_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_SWRST) >> SERCOM_I2CM_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_sercomi2cm_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_ENABLE) >> SERCOM_I2CM_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_sercomi2cm_get_SYNCBUSY_SYSOP_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_SYSOP) >> SERCOM_I2CM_SYNCBUSY_SYSOP_Pos;
+}
+
+static inline hri_sercomi2cm_syncbusy_reg_t hri_sercomi2cm_get_SYNCBUSY_reg(const void *const             hw,
+                                                                            hri_sercomi2cm_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomi2cm_syncbusy_reg_t hri_sercomi2cm_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CM.SYNCBUSY.reg;
+}
+
+static inline bool hri_sercomi2cs_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_SWRST) >> SERCOM_I2CS_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_sercomi2cs_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_ENABLE) >> SERCOM_I2CS_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline hri_sercomi2cs_syncbusy_reg_t hri_sercomi2cs_get_SYNCBUSY_reg(const void *const             hw,
+                                                                            hri_sercomi2cs_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomi2cs_syncbusy_reg_t hri_sercomi2cs_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CS.SYNCBUSY.reg;
+}
+
+static inline bool hri_sercomspi_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_SWRST) >> SERCOM_SPI_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_sercomspi_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_ENABLE) >> SERCOM_SPI_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_sercomspi_get_SYNCBUSY_CTRLB_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_CTRLB) >> SERCOM_SPI_SYNCBUSY_CTRLB_Pos;
+}
+
+static inline hri_sercomspi_syncbusy_reg_t hri_sercomspi_get_SYNCBUSY_reg(const void *const            hw,
+                                                                          hri_sercomspi_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomspi_syncbusy_reg_t hri_sercomspi_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->SPI.SYNCBUSY.reg;
+}
+
+static inline bool hri_sercomusart_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_SWRST) >> SERCOM_USART_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_sercomusart_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_ENABLE) >> SERCOM_USART_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_sercomusart_get_SYNCBUSY_CTRLB_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_CTRLB) >> SERCOM_USART_SYNCBUSY_CTRLB_Pos;
+}
+
+static inline hri_sercomusart_syncbusy_reg_t hri_sercomusart_get_SYNCBUSY_reg(const void *const              hw,
+                                                                              hri_sercomusart_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomusart_syncbusy_reg_t hri_sercomusart_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.SYNCBUSY.reg;
+}
+
+static inline hri_sercomusart_rxerrcnt_reg_t hri_sercomusart_get_RXERRCNT_reg(const void *const              hw,
+                                                                              hri_sercomusart_rxerrcnt_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->USART.RXERRCNT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_sercomusart_rxerrcnt_reg_t hri_sercomusart_read_RXERRCNT_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.RXERRCNT.reg;
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SWRST;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST);
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_SWRST) >> SERCOM_I2CM_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_ENABLE;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_ENABLE) >> SERCOM_I2CM_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_ENABLE;
+	tmp |= value << SERCOM_I2CM_CTRLA_ENABLE_Pos;
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_ENABLE;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_ENABLE;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_RUNSTDBY;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_RUNSTDBY) >> SERCOM_I2CM_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_RUNSTDBY;
+	tmp |= value << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos;
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_RUNSTDBY;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_RUNSTDBY;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_PINOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_PINOUT;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLA_PINOUT_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_PINOUT) >> SERCOM_I2CM_CTRLA_PINOUT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_PINOUT_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_PINOUT;
+	tmp |= value << SERCOM_I2CM_CTRLA_PINOUT_Pos;
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_PINOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_PINOUT;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_PINOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_PINOUT;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_MEXTTOEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_MEXTTOEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLA_MEXTTOEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_MEXTTOEN) >> SERCOM_I2CM_CTRLA_MEXTTOEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_MEXTTOEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_MEXTTOEN;
+	tmp |= value << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos;
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_MEXTTOEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_MEXTTOEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_MEXTTOEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_MEXTTOEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_SEXTTOEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SEXTTOEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLA_SEXTTOEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_SEXTTOEN) >> SERCOM_I2CM_CTRLA_SEXTTOEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_SEXTTOEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_SEXTTOEN;
+	tmp |= value << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos;
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_SEXTTOEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SEXTTOEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_SEXTTOEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SEXTTOEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_SCLSM_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SCLSM;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLA_SCLSM_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_SCLSM) >> SERCOM_I2CM_CTRLA_SCLSM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_SCLSM_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_SCLSM;
+	tmp |= value << SERCOM_I2CM_CTRLA_SCLSM_Pos;
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_SCLSM_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SCLSM;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_SCLSM_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SCLSM;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_LOWTOUTEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_LOWTOUTEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLA_LOWTOUTEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_LOWTOUTEN) >> SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_LOWTOUTEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_LOWTOUTEN;
+	tmp |= value << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos;
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_LOWTOUTEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_LOWTOUTEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_LOWTOUTEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_LOWTOUTEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_MODE(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_MODE_bf(const void *const          hw,
+                                                                          hri_sercomi2cm_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_MODE(mask)) >> SERCOM_I2CM_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_MODE_Msk;
+	tmp |= SERCOM_I2CM_CTRLA_MODE(data);
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_MODE(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_MODE(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_MODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_MODE_Msk) >> SERCOM_I2CM_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SDAHOLD(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_SDAHOLD_bf(const void *const          hw,
+                                                                             hri_sercomi2cm_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_SDAHOLD(mask)) >> SERCOM_I2CM_CTRLA_SDAHOLD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_SDAHOLD_Msk;
+	tmp |= SERCOM_I2CM_CTRLA_SDAHOLD(data);
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SDAHOLD(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SDAHOLD(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_SDAHOLD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_SDAHOLD_Msk) >> SERCOM_I2CM_CTRLA_SDAHOLD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SPEED(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_SPEED_bf(const void *const          hw,
+                                                                           hri_sercomi2cm_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_SPEED(mask)) >> SERCOM_I2CM_CTRLA_SPEED_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_SPEED_Msk;
+	tmp |= SERCOM_I2CM_CTRLA_SPEED(data);
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SPEED(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SPEED(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_SPEED_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_SPEED_Msk) >> SERCOM_I2CM_CTRLA_SPEED_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_INACTOUT(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_INACTOUT_bf(const void *const          hw,
+                                                                              hri_sercomi2cm_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_INACTOUT(mask)) >> SERCOM_I2CM_CTRLA_INACTOUT_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= ~SERCOM_I2CM_CTRLA_INACTOUT_Msk;
+	tmp |= SERCOM_I2CM_CTRLA_INACTOUT(data);
+	((Sercom *)hw)->I2CM.CTRLA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_INACTOUT(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_INACTOUT(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_INACTOUT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLA_INACTOUT_Msk) >> SERCOM_I2CM_CTRLA_INACTOUT_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg |= mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_reg(const void *const          hw,
+                                                                      hri_sercomi2cm_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	tmp = ((Sercom *)hw)->I2CM.CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg = data;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg &= ~mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLA.reg ^= mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_reg(const void *const hw)
+{
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE);
+	return ((Sercom *)hw)->I2CM.CTRLA.reg;
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SWRST;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST);
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_SWRST) >> SERCOM_I2CS_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_ENABLE;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE);
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_ENABLE) >> SERCOM_I2CS_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= ~SERCOM_I2CS_CTRLA_ENABLE;
+	tmp |= value << SERCOM_I2CS_CTRLA_ENABLE_Pos;
+	((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_ENABLE;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_ENABLE;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_RUNSTDBY;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_RUNSTDBY) >> SERCOM_I2CS_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= ~SERCOM_I2CS_CTRLA_RUNSTDBY;
+	tmp |= value << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos;
+	((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_RUNSTDBY;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_RUNSTDBY;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_PINOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_PINOUT;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLA_PINOUT_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_PINOUT) >> SERCOM_I2CS_CTRLA_PINOUT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_PINOUT_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= ~SERCOM_I2CS_CTRLA_PINOUT;
+	tmp |= value << SERCOM_I2CS_CTRLA_PINOUT_Pos;
+	((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_PINOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_PINOUT;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_PINOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_PINOUT;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_SEXTTOEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SEXTTOEN;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLA_SEXTTOEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_SEXTTOEN) >> SERCOM_I2CS_CTRLA_SEXTTOEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_SEXTTOEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= ~SERCOM_I2CS_CTRLA_SEXTTOEN;
+	tmp |= value << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos;
+	((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_SEXTTOEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SEXTTOEN;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_SEXTTOEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SEXTTOEN;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_SCLSM_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SCLSM;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLA_SCLSM_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_SCLSM) >> SERCOM_I2CS_CTRLA_SCLSM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_SCLSM_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= ~SERCOM_I2CS_CTRLA_SCLSM;
+	tmp |= value << SERCOM_I2CS_CTRLA_SCLSM_Pos;
+	((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_SCLSM_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SCLSM;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_SCLSM_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SCLSM;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_LOWTOUTEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_LOWTOUTEN;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLA_LOWTOUTEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_LOWTOUTEN) >> SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_LOWTOUTEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= ~SERCOM_I2CS_CTRLA_LOWTOUTEN;
+	tmp |= value << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos;
+	((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_LOWTOUTEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_LOWTOUTEN;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_LOWTOUTEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_LOWTOUTEN;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_MODE(mask);
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_MODE_bf(const void *const          hw,
+                                                                          hri_sercomi2cs_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_MODE(mask)) >> SERCOM_I2CS_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= ~SERCOM_I2CS_CTRLA_MODE_Msk;
+	tmp |= SERCOM_I2CS_CTRLA_MODE(data);
+	((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_MODE(mask);
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_MODE(mask);
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_MODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_MODE_Msk) >> SERCOM_I2CS_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SDAHOLD(mask);
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_SDAHOLD_bf(const void *const          hw,
+                                                                             hri_sercomi2cs_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_SDAHOLD(mask)) >> SERCOM_I2CS_CTRLA_SDAHOLD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= ~SERCOM_I2CS_CTRLA_SDAHOLD_Msk;
+	tmp |= SERCOM_I2CS_CTRLA_SDAHOLD(data);
+	((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SDAHOLD(mask);
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SDAHOLD(mask);
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_SDAHOLD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_SDAHOLD_Msk) >> SERCOM_I2CS_CTRLA_SDAHOLD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SPEED(mask);
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_SPEED_bf(const void *const          hw,
+                                                                           hri_sercomi2cs_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_SPEED(mask)) >> SERCOM_I2CS_CTRLA_SPEED_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= ~SERCOM_I2CS_CTRLA_SPEED_Msk;
+	tmp |= SERCOM_I2CS_CTRLA_SPEED(data);
+	((Sercom *)hw)->I2CS.CTRLA.reg = tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SPEED(mask);
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SPEED(mask);
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_SPEED_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLA_SPEED_Msk) >> SERCOM_I2CS_CTRLA_SPEED_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_set_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg |= mask;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_reg(const void *const          hw,
+                                                                      hri_sercomi2cs_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->I2CS.CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg = data;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg &= ~mask;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLA.reg ^= mask;
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_reg(const void *const hw)
+{
+	hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK);
+	return ((Sercom *)hw)->I2CS.CTRLA.reg;
+}
+
+static inline void hri_sercomspi_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_SWRST;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST);
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_SWRST) >> SERCOM_SPI_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_ENABLE;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_ENABLE) >> SERCOM_SPI_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_ENABLE;
+	tmp |= value << SERCOM_SPI_CTRLA_ENABLE_Pos;
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_ENABLE;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_ENABLE;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_RUNSTDBY;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_RUNSTDBY) >> SERCOM_SPI_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_RUNSTDBY;
+	tmp |= value << SERCOM_SPI_CTRLA_RUNSTDBY_Pos;
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_RUNSTDBY;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_RUNSTDBY;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLA_IBON_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_IBON;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLA_IBON_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_IBON) >> SERCOM_SPI_CTRLA_IBON_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_IBON_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_IBON;
+	tmp |= value << SERCOM_SPI_CTRLA_IBON_Pos;
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_IBON_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_IBON;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_IBON_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_IBON;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLA_CPHA_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_CPHA;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLA_CPHA_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_CPHA) >> SERCOM_SPI_CTRLA_CPHA_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_CPHA_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_CPHA;
+	tmp |= value << SERCOM_SPI_CTRLA_CPHA_Pos;
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_CPHA_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_CPHA;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_CPHA_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_CPHA;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLA_CPOL_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_CPOL;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLA_CPOL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_CPOL) >> SERCOM_SPI_CTRLA_CPOL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_CPOL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_CPOL;
+	tmp |= value << SERCOM_SPI_CTRLA_CPOL_Pos;
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_CPOL_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_CPOL;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_CPOL_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_CPOL;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLA_DORD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DORD;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLA_DORD_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_DORD) >> SERCOM_SPI_CTRLA_DORD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_DORD_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_DORD;
+	tmp |= value << SERCOM_SPI_CTRLA_DORD_Pos;
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_DORD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DORD;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_DORD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DORD;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_MODE(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_MODE_bf(const void *const         hw,
+                                                                        hri_sercomspi_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_MODE(mask)) >> SERCOM_SPI_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_MODE_Msk;
+	tmp |= SERCOM_SPI_CTRLA_MODE(data);
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_MODE(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_MODE(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_MODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_MODE_Msk) >> SERCOM_SPI_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DOPO(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_DOPO_bf(const void *const         hw,
+                                                                        hri_sercomspi_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_DOPO(mask)) >> SERCOM_SPI_CTRLA_DOPO_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_DOPO_Msk;
+	tmp |= SERCOM_SPI_CTRLA_DOPO(data);
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DOPO(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DOPO(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_DOPO_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_DOPO_Msk) >> SERCOM_SPI_CTRLA_DOPO_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DIPO(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_DIPO_bf(const void *const         hw,
+                                                                        hri_sercomspi_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_DIPO(mask)) >> SERCOM_SPI_CTRLA_DIPO_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_DIPO_Msk;
+	tmp |= SERCOM_SPI_CTRLA_DIPO(data);
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DIPO(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DIPO(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_DIPO_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_DIPO_Msk) >> SERCOM_SPI_CTRLA_DIPO_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_FORM(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_FORM_bf(const void *const         hw,
+                                                                        hri_sercomspi_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_FORM(mask)) >> SERCOM_SPI_CTRLA_FORM_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= ~SERCOM_SPI_CTRLA_FORM_Msk;
+	tmp |= SERCOM_SPI_CTRLA_FORM(data);
+	((Sercom *)hw)->SPI.CTRLA.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_FORM(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_FORM(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_FORM_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLA_FORM_Msk) >> SERCOM_SPI_CTRLA_FORM_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg |= mask;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_reg(const void *const         hw,
+                                                                    hri_sercomspi_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg = data;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg &= ~mask;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLA.reg ^= mask;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_reg(const void *const hw)
+{
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
+	return ((Sercom *)hw)->SPI.CTRLA.reg;
+}
+
+static inline void hri_sercomusart_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SWRST;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST);
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_SWRST) >> SERCOM_USART_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_ENABLE) >> SERCOM_USART_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_ENABLE;
+	tmp |= value << SERCOM_USART_CTRLA_ENABLE_Pos;
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_ENABLE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RUNSTDBY;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_RUNSTDBY) >> SERCOM_USART_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_RUNSTDBY;
+	tmp |= value << SERCOM_USART_CTRLA_RUNSTDBY_Pos;
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RUNSTDBY;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RUNSTDBY;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLA_IBON_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_IBON;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLA_IBON_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_IBON) >> SERCOM_USART_CTRLA_IBON_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_IBON_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_IBON;
+	tmp |= value << SERCOM_USART_CTRLA_IBON_Pos;
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_IBON_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_IBON;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_IBON_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_IBON;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLA_TXINV_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_TXINV;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLA_TXINV_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_TXINV) >> SERCOM_USART_CTRLA_TXINV_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_TXINV_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_TXINV;
+	tmp |= value << SERCOM_USART_CTRLA_TXINV_Pos;
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_TXINV_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_TXINV;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_TXINV_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_TXINV;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLA_RXINV_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RXINV;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLA_RXINV_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_RXINV) >> SERCOM_USART_CTRLA_RXINV_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_RXINV_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_RXINV;
+	tmp |= value << SERCOM_USART_CTRLA_RXINV_Pos;
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_RXINV_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RXINV;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_RXINV_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RXINV;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLA_CMODE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_CMODE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLA_CMODE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_CMODE) >> SERCOM_USART_CTRLA_CMODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_CMODE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_CMODE;
+	tmp |= value << SERCOM_USART_CTRLA_CMODE_Pos;
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_CMODE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_CMODE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_CMODE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_CMODE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLA_CPOL_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_CPOL;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLA_CPOL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_CPOL) >> SERCOM_USART_CTRLA_CPOL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_CPOL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_CPOL;
+	tmp |= value << SERCOM_USART_CTRLA_CPOL_Pos;
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_CPOL_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_CPOL;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_CPOL_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_CPOL;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLA_DORD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_DORD;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLA_DORD_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_DORD) >> SERCOM_USART_CTRLA_DORD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_DORD_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_DORD;
+	tmp |= value << SERCOM_USART_CTRLA_DORD_Pos;
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_DORD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_DORD;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_DORD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_DORD;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_MODE(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_MODE_bf(const void *const           hw,
+                                                                            hri_sercomusart_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_MODE(mask)) >> SERCOM_USART_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_MODE_Msk;
+	tmp |= SERCOM_USART_CTRLA_MODE(data);
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_MODE(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_MODE(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_MODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_MODE_Msk) >> SERCOM_USART_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SAMPR(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_SAMPR_bf(const void *const           hw,
+                                                                             hri_sercomusart_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_SAMPR(mask)) >> SERCOM_USART_CTRLA_SAMPR_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_SAMPR_Msk;
+	tmp |= SERCOM_USART_CTRLA_SAMPR(data);
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_SAMPR(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_SAMPR(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_SAMPR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_SAMPR_Msk) >> SERCOM_USART_CTRLA_SAMPR_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_TXPO(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_TXPO_bf(const void *const           hw,
+                                                                            hri_sercomusart_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_TXPO(mask)) >> SERCOM_USART_CTRLA_TXPO_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_TXPO_Msk;
+	tmp |= SERCOM_USART_CTRLA_TXPO(data);
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_TXPO(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_TXPO(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_TXPO_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_TXPO_Msk) >> SERCOM_USART_CTRLA_TXPO_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RXPO(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_RXPO_bf(const void *const           hw,
+                                                                            hri_sercomusart_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_RXPO(mask)) >> SERCOM_USART_CTRLA_RXPO_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_RXPO_Msk;
+	tmp |= SERCOM_USART_CTRLA_RXPO(data);
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RXPO(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RXPO(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_RXPO_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_RXPO_Msk) >> SERCOM_USART_CTRLA_RXPO_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SAMPA(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_SAMPA_bf(const void *const           hw,
+                                                                             hri_sercomusart_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_SAMPA(mask)) >> SERCOM_USART_CTRLA_SAMPA_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_SAMPA_Msk;
+	tmp |= SERCOM_USART_CTRLA_SAMPA(data);
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_SAMPA(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_SAMPA(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_SAMPA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_SAMPA_Msk) >> SERCOM_USART_CTRLA_SAMPA_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_FORM(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_FORM_bf(const void *const           hw,
+                                                                            hri_sercomusart_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_FORM(mask)) >> SERCOM_USART_CTRLA_FORM_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= ~SERCOM_USART_CTRLA_FORM_Msk;
+	tmp |= SERCOM_USART_CTRLA_FORM(data);
+	((Sercom *)hw)->USART.CTRLA.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_FORM(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_FORM(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_FORM_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp = (tmp & SERCOM_USART_CTRLA_FORM_Msk) >> SERCOM_USART_CTRLA_FORM_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg |= mask;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_reg(const void *const           hw,
+                                                                        hri_sercomusart_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	tmp = ((Sercom *)hw)->USART.CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg = data;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg &= ~mask;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLA.reg ^= mask;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_reg(const void *const hw)
+{
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
+	return ((Sercom *)hw)->USART.CTRLA.reg;
+}
+
+static inline void hri_sercomi2cm_set_CTRLB_SMEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_SMEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLB_SMEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLB_SMEN) >> SERCOM_I2CM_CTRLB_SMEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLB_SMEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp &= ~SERCOM_I2CM_CTRLB_SMEN;
+	tmp |= value << SERCOM_I2CM_CTRLB_SMEN_Pos;
+	((Sercom *)hw)->I2CM.CTRLB.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLB_SMEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_SMEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLB_SMEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_SMEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLB_QCEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_QCEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLB_QCEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLB_QCEN) >> SERCOM_I2CM_CTRLB_QCEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLB_QCEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp &= ~SERCOM_I2CM_CTRLB_QCEN;
+	tmp |= value << SERCOM_I2CM_CTRLB_QCEN_Pos;
+	((Sercom *)hw)->I2CM.CTRLB.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLB_QCEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_QCEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLB_QCEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_QCEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLB_ACKACT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_CTRLB_ACKACT_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLB_ACKACT) >> SERCOM_I2CM_CTRLB_ACKACT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLB_ACKACT_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp &= ~SERCOM_I2CM_CTRLB_ACKACT;
+	tmp |= value << SERCOM_I2CM_CTRLB_ACKACT_Pos;
+	((Sercom *)hw)->I2CM.CTRLB.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLB_ACKACT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLB_ACKACT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_ACKACT;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_get_CTRLB_CMD_bf(const void *const          hw,
+                                                                         hri_sercomi2cm_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLB_CMD(mask)) >> SERCOM_I2CM_CTRLB_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp &= ~SERCOM_I2CM_CTRLB_CMD_Msk;
+	tmp |= SERCOM_I2CM_CTRLB_CMD(data);
+	((Sercom *)hw)->I2CM.CTRLB.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_CMD(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_CMD(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_read_CTRLB_CMD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CM_CTRLB_CMD_Msk) >> SERCOM_I2CM_CTRLB_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg |= mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_get_CTRLB_reg(const void *const          hw,
+                                                                      hri_sercomi2cm_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	tmp = ((Sercom *)hw)->I2CM.CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg = data;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg &= ~mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.CTRLB.reg ^= mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_read_CTRLB_reg(const void *const hw)
+{
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	return ((Sercom *)hw)->I2CM.CTRLB.reg;
+}
+
+static inline void hri_sercomi2cs_set_CTRLB_SMEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_SMEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLB_SMEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLB_SMEN) >> SERCOM_I2CS_CTRLB_SMEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLB_SMEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp &= ~SERCOM_I2CS_CTRLB_SMEN;
+	tmp |= value << SERCOM_I2CS_CTRLB_SMEN_Pos;
+	((Sercom *)hw)->I2CS.CTRLB.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLB_SMEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_SMEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLB_SMEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_SMEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLB_GCMD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_GCMD;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLB_GCMD_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLB_GCMD) >> SERCOM_I2CS_CTRLB_GCMD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLB_GCMD_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp &= ~SERCOM_I2CS_CTRLB_GCMD;
+	tmp |= value << SERCOM_I2CS_CTRLB_GCMD_Pos;
+	((Sercom *)hw)->I2CS.CTRLB.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLB_GCMD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_GCMD;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLB_GCMD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_GCMD;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLB_AACKEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_AACKEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLB_AACKEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLB_AACKEN) >> SERCOM_I2CS_CTRLB_AACKEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLB_AACKEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp &= ~SERCOM_I2CS_CTRLB_AACKEN;
+	tmp |= value << SERCOM_I2CS_CTRLB_AACKEN_Pos;
+	((Sercom *)hw)->I2CS.CTRLB.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLB_AACKEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_AACKEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLB_AACKEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_AACKEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLB_ACKACT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_CTRLB_ACKACT_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLB_ACKACT) >> SERCOM_I2CS_CTRLB_ACKACT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLB_ACKACT_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp &= ~SERCOM_I2CS_CTRLB_ACKACT;
+	tmp |= value << SERCOM_I2CS_CTRLB_ACKACT_Pos;
+	((Sercom *)hw)->I2CS.CTRLB.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLB_ACKACT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLB_ACKACT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_ACKACT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_AMODE(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_AMODE_bf(const void *const          hw,
+                                                                           hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLB_AMODE(mask)) >> SERCOM_I2CS_CTRLB_AMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp &= ~SERCOM_I2CS_CTRLB_AMODE_Msk;
+	tmp |= SERCOM_I2CS_CTRLB_AMODE(data);
+	((Sercom *)hw)->I2CS.CTRLB.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_AMODE(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_AMODE(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_AMODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLB_AMODE_Msk) >> SERCOM_I2CS_CTRLB_AMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_set_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_CMD_bf(const void *const          hw,
+                                                                         hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLB_CMD(mask)) >> SERCOM_I2CS_CTRLB_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp &= ~SERCOM_I2CS_CTRLB_CMD_Msk;
+	tmp |= SERCOM_I2CS_CTRLB_CMD(data);
+	((Sercom *)hw)->I2CS.CTRLB.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_CMD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_CMD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_CMD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp = (tmp & SERCOM_I2CS_CTRLB_CMD_Msk) >> SERCOM_I2CS_CTRLB_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_set_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_reg(const void *const          hw,
+                                                                      hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.CTRLB.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CS.CTRLB.reg;
+}
+
+static inline void hri_sercomspi_set_CTRLB_PLOADEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_PLOADEN;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLB_PLOADEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLB_PLOADEN) >> SERCOM_SPI_CTRLB_PLOADEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLB_PLOADEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp &= ~SERCOM_SPI_CTRLB_PLOADEN;
+	tmp |= value << SERCOM_SPI_CTRLB_PLOADEN_Pos;
+	((Sercom *)hw)->SPI.CTRLB.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLB_PLOADEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_PLOADEN;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLB_PLOADEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_PLOADEN;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLB_SSDE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_SSDE;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLB_SSDE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLB_SSDE) >> SERCOM_SPI_CTRLB_SSDE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLB_SSDE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp &= ~SERCOM_SPI_CTRLB_SSDE;
+	tmp |= value << SERCOM_SPI_CTRLB_SSDE_Pos;
+	((Sercom *)hw)->SPI.CTRLB.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLB_SSDE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_SSDE;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLB_SSDE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_SSDE;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLB_MSSEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_MSSEN;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLB_MSSEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLB_MSSEN) >> SERCOM_SPI_CTRLB_MSSEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLB_MSSEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp &= ~SERCOM_SPI_CTRLB_MSSEN;
+	tmp |= value << SERCOM_SPI_CTRLB_MSSEN_Pos;
+	((Sercom *)hw)->SPI.CTRLB.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLB_MSSEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_MSSEN;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLB_MSSEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_MSSEN;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLB_RXEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_RXEN;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_CTRLB_RXEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLB_RXEN) >> SERCOM_SPI_CTRLB_RXEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLB_RXEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp &= ~SERCOM_SPI_CTRLB_RXEN;
+	tmp |= value << SERCOM_SPI_CTRLB_RXEN_Pos;
+	((Sercom *)hw)->SPI.CTRLB.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLB_RXEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_RXEN;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLB_RXEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_RXEN;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_CHSIZE(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_CHSIZE_bf(const void *const         hw,
+                                                                          hri_sercomspi_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLB_CHSIZE(mask)) >> SERCOM_SPI_CTRLB_CHSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp &= ~SERCOM_SPI_CTRLB_CHSIZE_Msk;
+	tmp |= SERCOM_SPI_CTRLB_CHSIZE(data);
+	((Sercom *)hw)->SPI.CTRLB.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_CHSIZE(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_CHSIZE(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_CHSIZE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLB_CHSIZE_Msk) >> SERCOM_SPI_CTRLB_CHSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_AMODE(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_AMODE_bf(const void *const         hw,
+                                                                         hri_sercomspi_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLB_AMODE(mask)) >> SERCOM_SPI_CTRLB_AMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp &= ~SERCOM_SPI_CTRLB_AMODE_Msk;
+	tmp |= SERCOM_SPI_CTRLB_AMODE(data);
+	((Sercom *)hw)->SPI.CTRLB.reg = tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_AMODE(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_AMODE(mask);
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_AMODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp = (tmp & SERCOM_SPI_CTRLB_AMODE_Msk) >> SERCOM_SPI_CTRLB_AMODE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg |= mask;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_reg(const void *const         hw,
+                                                                    hri_sercomspi_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->SPI.CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg = data;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg &= ~mask;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.CTRLB.reg ^= mask;
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_reg(const void *const hw)
+{
+	hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
+	return ((Sercom *)hw)->SPI.CTRLB.reg;
+}
+
+static inline void hri_sercomusart_set_CTRLB_SBMODE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_SBMODE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLB_SBMODE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_SBMODE) >> SERCOM_USART_CTRLB_SBMODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_SBMODE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= ~SERCOM_USART_CTRLB_SBMODE;
+	tmp |= value << SERCOM_USART_CTRLB_SBMODE_Pos;
+	((Sercom *)hw)->USART.CTRLB.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_SBMODE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_SBMODE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_SBMODE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_SBMODE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLB_COLDEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_COLDEN;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLB_COLDEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_COLDEN) >> SERCOM_USART_CTRLB_COLDEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_COLDEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= ~SERCOM_USART_CTRLB_COLDEN;
+	tmp |= value << SERCOM_USART_CTRLB_COLDEN_Pos;
+	((Sercom *)hw)->USART.CTRLB.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_COLDEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_COLDEN;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_COLDEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_COLDEN;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLB_SFDE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_SFDE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLB_SFDE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_SFDE) >> SERCOM_USART_CTRLB_SFDE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_SFDE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= ~SERCOM_USART_CTRLB_SFDE;
+	tmp |= value << SERCOM_USART_CTRLB_SFDE_Pos;
+	((Sercom *)hw)->USART.CTRLB.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_SFDE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_SFDE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_SFDE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_SFDE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLB_ENC_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_ENC;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLB_ENC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_ENC) >> SERCOM_USART_CTRLB_ENC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_ENC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= ~SERCOM_USART_CTRLB_ENC;
+	tmp |= value << SERCOM_USART_CTRLB_ENC_Pos;
+	((Sercom *)hw)->USART.CTRLB.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_ENC_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_ENC;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_ENC_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_ENC;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLB_PMODE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_PMODE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLB_PMODE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_PMODE) >> SERCOM_USART_CTRLB_PMODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_PMODE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= ~SERCOM_USART_CTRLB_PMODE;
+	tmp |= value << SERCOM_USART_CTRLB_PMODE_Pos;
+	((Sercom *)hw)->USART.CTRLB.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_PMODE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_PMODE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_PMODE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_PMODE;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLB_TXEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_TXEN;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLB_TXEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_TXEN) >> SERCOM_USART_CTRLB_TXEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_TXEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= ~SERCOM_USART_CTRLB_TXEN;
+	tmp |= value << SERCOM_USART_CTRLB_TXEN_Pos;
+	((Sercom *)hw)->USART.CTRLB.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_TXEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_TXEN;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_TXEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_TXEN;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLB_RXEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_RXEN;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLB_RXEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_RXEN) >> SERCOM_USART_CTRLB_RXEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_RXEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= ~SERCOM_USART_CTRLB_RXEN;
+	tmp |= value << SERCOM_USART_CTRLB_RXEN_Pos;
+	((Sercom *)hw)->USART.CTRLB.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_RXEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_RXEN;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_RXEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_RXEN;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_CHSIZE(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_CHSIZE_bf(const void *const           hw,
+                                                                              hri_sercomusart_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_CHSIZE(mask)) >> SERCOM_USART_CTRLB_CHSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= ~SERCOM_USART_CTRLB_CHSIZE_Msk;
+	tmp |= SERCOM_USART_CTRLB_CHSIZE(data);
+	((Sercom *)hw)->USART.CTRLB.reg = tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_CHSIZE(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_CHSIZE(mask);
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_CHSIZE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp = (tmp & SERCOM_USART_CTRLB_CHSIZE_Msk) >> SERCOM_USART_CTRLB_CHSIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg |= mask;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_reg(const void *const           hw,
+                                                                        hri_sercomusart_ctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	tmp = ((Sercom *)hw)->USART.CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg = data;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg &= ~mask;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLB.reg ^= mask;
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_reg(const void *const hw)
+{
+	hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
+	return ((Sercom *)hw)->USART.CTRLB.reg;
+}
+
+static inline void hri_sercomusart_set_CTRLC_INACK_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_INACK;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLC_INACK_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp = (tmp & SERCOM_USART_CTRLC_INACK) >> SERCOM_USART_CTRLC_INACK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLC_INACK_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp &= ~SERCOM_USART_CTRLC_INACK;
+	tmp |= value << SERCOM_USART_CTRLC_INACK_Pos;
+	((Sercom *)hw)->USART.CTRLC.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLC_INACK_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_INACK;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLC_INACK_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_INACK;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLC_DSNACK_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_DSNACK;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_CTRLC_DSNACK_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp = (tmp & SERCOM_USART_CTRLC_DSNACK) >> SERCOM_USART_CTRLC_DSNACK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLC_DSNACK_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp &= ~SERCOM_USART_CTRLC_DSNACK;
+	tmp |= value << SERCOM_USART_CTRLC_DSNACK_Pos;
+	((Sercom *)hw)->USART.CTRLC.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLC_DSNACK_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_DSNACK;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLC_DSNACK_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_DSNACK;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_GTIME(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_GTIME_bf(const void *const           hw,
+                                                                             hri_sercomusart_ctrlc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp = (tmp & SERCOM_USART_CTRLC_GTIME(mask)) >> SERCOM_USART_CTRLC_GTIME_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp &= ~SERCOM_USART_CTRLC_GTIME_Msk;
+	tmp |= SERCOM_USART_CTRLC_GTIME(data);
+	((Sercom *)hw)->USART.CTRLC.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_GTIME(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_GTIME(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_GTIME_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp = (tmp & SERCOM_USART_CTRLC_GTIME_Msk) >> SERCOM_USART_CTRLC_GTIME_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_MAXITER(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_MAXITER_bf(const void *const           hw,
+                                                                               hri_sercomusart_ctrlc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp = (tmp & SERCOM_USART_CTRLC_MAXITER(mask)) >> SERCOM_USART_CTRLC_MAXITER_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp &= ~SERCOM_USART_CTRLC_MAXITER_Msk;
+	tmp |= SERCOM_USART_CTRLC_MAXITER(data);
+	((Sercom *)hw)->USART.CTRLC.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_MAXITER(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_MAXITER(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_MAXITER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp = (tmp & SERCOM_USART_CTRLC_MAXITER_Msk) >> SERCOM_USART_CTRLC_MAXITER_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_reg(const void *const           hw,
+                                                                        hri_sercomusart_ctrlc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->USART.CTRLC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.CTRLC.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.CTRLC.reg;
+}
+
+static inline void hri_sercomi2cm_set_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_BAUD_bf(const void *const         hw,
+                                                                        hri_sercomi2cm_baud_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp = (tmp & SERCOM_I2CM_BAUD_BAUD(mask)) >> SERCOM_I2CM_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp &= ~SERCOM_I2CM_BAUD_BAUD_Msk;
+	tmp |= SERCOM_I2CM_BAUD_BAUD(data);
+	((Sercom *)hw)->I2CM.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_BAUD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp = (tmp & SERCOM_I2CM_BAUD_BAUD_Msk) >> SERCOM_I2CM_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_BAUDLOW(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_BAUDLOW_bf(const void *const         hw,
+                                                                           hri_sercomi2cm_baud_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp = (tmp & SERCOM_I2CM_BAUD_BAUDLOW(mask)) >> SERCOM_I2CM_BAUD_BAUDLOW_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp &= ~SERCOM_I2CM_BAUD_BAUDLOW_Msk;
+	tmp |= SERCOM_I2CM_BAUD_BAUDLOW(data);
+	((Sercom *)hw)->I2CM.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_BAUDLOW(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_BAUDLOW(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_BAUDLOW_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp = (tmp & SERCOM_I2CM_BAUD_BAUDLOW_Msk) >> SERCOM_I2CM_BAUD_BAUDLOW_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_HSBAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_HSBAUD_bf(const void *const         hw,
+                                                                          hri_sercomi2cm_baud_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUD(mask)) >> SERCOM_I2CM_BAUD_HSBAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp &= ~SERCOM_I2CM_BAUD_HSBAUD_Msk;
+	tmp |= SERCOM_I2CM_BAUD_HSBAUD(data);
+	((Sercom *)hw)->I2CM.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_HSBAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_HSBAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_HSBAUD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUD_Msk) >> SERCOM_I2CM_BAUD_HSBAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_HSBAUDLOW(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_HSBAUDLOW_bf(const void *const         hw,
+                                                                             hri_sercomi2cm_baud_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUDLOW(mask)) >> SERCOM_I2CM_BAUD_HSBAUDLOW_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp &= ~SERCOM_I2CM_BAUD_HSBAUDLOW_Msk;
+	tmp |= SERCOM_I2CM_BAUD_HSBAUDLOW(data);
+	((Sercom *)hw)->I2CM.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_HSBAUDLOW(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_HSBAUDLOW(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_HSBAUDLOW_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUDLOW_Msk) >> SERCOM_I2CM_BAUD_HSBAUDLOW_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_reg(const void *const         hw,
+                                                                    hri_sercomi2cm_baud_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.BAUD.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.BAUD.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CM.BAUD.reg;
+}
+
+static inline void hri_sercomspi_set_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.BAUD.reg |= SERCOM_SPI_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_baud_reg_t hri_sercomspi_get_BAUD_BAUD_bf(const void *const        hw,
+                                                                      hri_sercomspi_baud_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->SPI.BAUD.reg;
+	tmp = (tmp & SERCOM_SPI_BAUD_BAUD(mask)) >> SERCOM_SPI_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t data)
+{
+	uint8_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.BAUD.reg;
+	tmp &= ~SERCOM_SPI_BAUD_BAUD_Msk;
+	tmp |= SERCOM_SPI_BAUD_BAUD(data);
+	((Sercom *)hw)->SPI.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.BAUD.reg &= ~SERCOM_SPI_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.BAUD.reg ^= SERCOM_SPI_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_baud_reg_t hri_sercomspi_read_BAUD_BAUD_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->SPI.BAUD.reg;
+	tmp = (tmp & SERCOM_SPI_BAUD_BAUD_Msk) >> SERCOM_SPI_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.BAUD.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_baud_reg_t hri_sercomspi_get_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->SPI.BAUD.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.BAUD.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.BAUD.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.BAUD.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_baud_reg_t hri_sercomspi_read_BAUD_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->SPI.BAUD.reg;
+}
+
+static inline void hri_sercomusart_set_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRAC_BAUD_bf(const void *const          hw,
+                                                                               hri_sercomusart_baud_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRACFP_BAUD_bf(const void *const          hw,
+                                                                                 hri_sercomusart_baud_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp &= ~SERCOM_USART_BAUD_BAUD_Msk;
+	tmp |= SERCOM_USART_BAUD_BAUD(data);
+	((Sercom *)hw)->USART.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_write_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp &= ~SERCOM_USART_BAUD_BAUD_Msk;
+	tmp |= SERCOM_USART_BAUD_BAUD(data);
+	((Sercom *)hw)->USART.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRAC_BAUD_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRACFP_BAUD_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRAC_FP(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRACFP_FP(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRAC_FP_bf(const void *const          hw,
+                                                                             hri_sercomusart_baud_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_FRAC_FP(mask)) >> SERCOM_USART_BAUD_FRAC_FP_Pos;
+	return tmp;
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRACFP_FP_bf(const void *const          hw,
+                                                                               hri_sercomusart_baud_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_FRACFP_FP(mask)) >> SERCOM_USART_BAUD_FRACFP_FP_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp &= ~SERCOM_USART_BAUD_FRAC_FP_Msk;
+	tmp |= SERCOM_USART_BAUD_FRAC_FP(data);
+	((Sercom *)hw)->USART.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_write_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp &= ~SERCOM_USART_BAUD_FRACFP_FP_Msk;
+	tmp |= SERCOM_USART_BAUD_FRACFP_FP(data);
+	((Sercom *)hw)->USART.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRAC_FP(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRACFP_FP(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRAC_FP(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRACFP_FP(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRAC_FP_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_FRAC_FP_Msk) >> SERCOM_USART_BAUD_FRAC_FP_Pos;
+	return tmp;
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRACFP_FP_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_FRACFP_FP_Msk) >> SERCOM_USART_BAUD_FRACFP_FP_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_BAUD_bf(const void *const          hw,
+                                                                          hri_sercomusart_baud_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_USARTFP_BAUD_bf(const void *const          hw,
+                                                                                  hri_sercomusart_baud_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp &= ~SERCOM_USART_BAUD_BAUD_Msk;
+	tmp |= SERCOM_USART_BAUD_BAUD(data);
+	((Sercom *)hw)->USART.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_write_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp &= ~SERCOM_USART_BAUD_BAUD_Msk;
+	tmp |= SERCOM_USART_BAUD_BAUD(data);
+	((Sercom *)hw)->USART.BAUD.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_BAUD_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_USARTFP_BAUD_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_reg(const void *const          hw,
+                                                                      hri_sercomusart_baud_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.BAUD.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.BAUD.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.BAUD.reg;
+}
+
+static inline void hri_sercomusart_set_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.RXPL.reg |= SERCOM_USART_RXPL_RXPL(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_get_RXPL_RXPL_bf(const void *const          hw,
+                                                                          hri_sercomusart_rxpl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->USART.RXPL.reg;
+	tmp = (tmp & SERCOM_USART_RXPL_RXPL(mask)) >> SERCOM_USART_RXPL_RXPL_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t data)
+{
+	uint8_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.RXPL.reg;
+	tmp &= ~SERCOM_USART_RXPL_RXPL_Msk;
+	tmp |= SERCOM_USART_RXPL_RXPL(data);
+	((Sercom *)hw)->USART.RXPL.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.RXPL.reg &= ~SERCOM_USART_RXPL_RXPL(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.RXPL.reg ^= SERCOM_USART_RXPL_RXPL(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_read_RXPL_RXPL_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->USART.RXPL.reg;
+	tmp = (tmp & SERCOM_USART_RXPL_RXPL_Msk) >> SERCOM_USART_RXPL_RXPL_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.RXPL.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_get_RXPL_reg(const void *const          hw,
+                                                                      hri_sercomusart_rxpl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->USART.RXPL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.RXPL.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.RXPL.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.RXPL.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_read_RXPL_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.RXPL.reg;
+}
+
+static inline void hri_sercomi2cm_set_ADDR_LENEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_LENEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_ADDR_LENEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CM_ADDR_LENEN) >> SERCOM_I2CM_ADDR_LENEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_ADDR_LENEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp &= ~SERCOM_I2CM_ADDR_LENEN;
+	tmp |= value << SERCOM_I2CM_ADDR_LENEN_Pos;
+	((Sercom *)hw)->I2CM.ADDR.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_ADDR_LENEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_LENEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_ADDR_LENEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_LENEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_ADDR_HS_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_HS;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_ADDR_HS_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CM_ADDR_HS) >> SERCOM_I2CM_ADDR_HS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_ADDR_HS_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp &= ~SERCOM_I2CM_ADDR_HS;
+	tmp |= value << SERCOM_I2CM_ADDR_HS_Pos;
+	((Sercom *)hw)->I2CM.ADDR.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_ADDR_HS_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_HS;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_ADDR_HS_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_HS;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_ADDR_TENBITEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_TENBITEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_ADDR_TENBITEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CM_ADDR_TENBITEN) >> SERCOM_I2CM_ADDR_TENBITEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_ADDR_TENBITEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp &= ~SERCOM_I2CM_ADDR_TENBITEN;
+	tmp |= value << SERCOM_I2CM_ADDR_TENBITEN_Pos;
+	((Sercom *)hw)->I2CM.ADDR.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_ADDR_TENBITEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_TENBITEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_ADDR_TENBITEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_TENBITEN;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_ADDR(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_ADDR_bf(const void *const         hw,
+                                                                        hri_sercomi2cm_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CM_ADDR_ADDR(mask)) >> SERCOM_I2CM_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp &= ~SERCOM_I2CM_ADDR_ADDR_Msk;
+	tmp |= SERCOM_I2CM_ADDR_ADDR(data);
+	((Sercom *)hw)->I2CM.ADDR.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_ADDR(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_ADDR(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_ADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CM_ADDR_ADDR_Msk) >> SERCOM_I2CM_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_LEN(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_LEN_bf(const void *const         hw,
+                                                                       hri_sercomi2cm_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CM_ADDR_LEN(mask)) >> SERCOM_I2CM_ADDR_LEN_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp &= ~SERCOM_I2CM_ADDR_LEN_Msk;
+	tmp |= SERCOM_I2CM_ADDR_LEN(data);
+	((Sercom *)hw)->I2CM.ADDR.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_LEN(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_LEN(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_LEN_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CM_ADDR_LEN_Msk) >> SERCOM_I2CM_ADDR_LEN_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg |= mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_reg(const void *const         hw,
+                                                                    hri_sercomi2cm_addr_reg_t mask)
+{
+	uint32_t tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	tmp = ((Sercom *)hw)->I2CM.ADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg = data;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg &= ~mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.ADDR.reg ^= mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_reg(const void *const hw)
+{
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	return ((Sercom *)hw)->I2CM.ADDR.reg;
+}
+
+static inline void hri_sercomi2cs_set_ADDR_GENCEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_GENCEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_ADDR_GENCEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CS_ADDR_GENCEN) >> SERCOM_I2CS_ADDR_GENCEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_ADDR_GENCEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp &= ~SERCOM_I2CS_ADDR_GENCEN;
+	tmp |= value << SERCOM_I2CS_ADDR_GENCEN_Pos;
+	((Sercom *)hw)->I2CS.ADDR.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_ADDR_GENCEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_GENCEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_ADDR_GENCEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_GENCEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_ADDR_TENBITEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_TENBITEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_ADDR_TENBITEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CS_ADDR_TENBITEN) >> SERCOM_I2CS_ADDR_TENBITEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cs_write_ADDR_TENBITEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp &= ~SERCOM_I2CS_ADDR_TENBITEN;
+	tmp |= value << SERCOM_I2CS_ADDR_TENBITEN_Pos;
+	((Sercom *)hw)->I2CS.ADDR.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_ADDR_TENBITEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_TENBITEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_ADDR_TENBITEN_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_TENBITEN;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_set_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_ADDR(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_ADDR_bf(const void *const         hw,
+                                                                        hri_sercomi2cs_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CS_ADDR_ADDR(mask)) >> SERCOM_I2CS_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp &= ~SERCOM_I2CS_ADDR_ADDR_Msk;
+	tmp |= SERCOM_I2CS_ADDR_ADDR(data);
+	((Sercom *)hw)->I2CS.ADDR.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_ADDR(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_ADDR(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_ADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CS_ADDR_ADDR_Msk) >> SERCOM_I2CS_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_set_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_ADDRMASK(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_ADDRMASK_bf(const void *const         hw,
+                                                                            hri_sercomi2cs_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CS_ADDR_ADDRMASK(mask)) >> SERCOM_I2CS_ADDR_ADDRMASK_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp &= ~SERCOM_I2CS_ADDR_ADDRMASK_Msk;
+	tmp |= SERCOM_I2CS_ADDR_ADDRMASK(data);
+	((Sercom *)hw)->I2CS.ADDR.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_ADDRMASK(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_ADDRMASK(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_ADDRMASK_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp = (tmp & SERCOM_I2CS_ADDR_ADDRMASK_Msk) >> SERCOM_I2CS_ADDR_ADDRMASK_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_set_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_reg(const void *const         hw,
+                                                                    hri_sercomi2cs_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.ADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.ADDR.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CS.ADDR.reg;
+}
+
+static inline void hri_sercomspi_set_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg |= SERCOM_SPI_ADDR_ADDR(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_ADDR_bf(const void *const        hw,
+                                                                      hri_sercomspi_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.ADDR.reg;
+	tmp = (tmp & SERCOM_SPI_ADDR_ADDR(mask)) >> SERCOM_SPI_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.ADDR.reg;
+	tmp &= ~SERCOM_SPI_ADDR_ADDR_Msk;
+	tmp |= SERCOM_SPI_ADDR_ADDR(data);
+	((Sercom *)hw)->SPI.ADDR.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg &= ~SERCOM_SPI_ADDR_ADDR(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg ^= SERCOM_SPI_ADDR_ADDR(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_ADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.ADDR.reg;
+	tmp = (tmp & SERCOM_SPI_ADDR_ADDR_Msk) >> SERCOM_SPI_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg |= SERCOM_SPI_ADDR_ADDRMASK(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_ADDRMASK_bf(const void *const        hw,
+                                                                          hri_sercomspi_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.ADDR.reg;
+	tmp = (tmp & SERCOM_SPI_ADDR_ADDRMASK(mask)) >> SERCOM_SPI_ADDR_ADDRMASK_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.ADDR.reg;
+	tmp &= ~SERCOM_SPI_ADDR_ADDRMASK_Msk;
+	tmp |= SERCOM_SPI_ADDR_ADDRMASK(data);
+	((Sercom *)hw)->SPI.ADDR.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg &= ~SERCOM_SPI_ADDR_ADDRMASK(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg ^= SERCOM_SPI_ADDR_ADDRMASK(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_ADDRMASK_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.ADDR.reg;
+	tmp = (tmp & SERCOM_SPI_ADDR_ADDRMASK_Msk) >> SERCOM_SPI_ADDR_ADDRMASK_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.ADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.ADDR.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->SPI.ADDR.reg;
+}
+
+static inline void hri_sercomi2cm_set_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DATA.reg |= SERCOM_I2CM_DATA_DATA(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_get_DATA_DATA_bf(const void *const         hw,
+                                                                        hri_sercomi2cm_data_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.DATA.reg;
+	tmp = (tmp & SERCOM_I2CM_DATA_DATA(mask)) >> SERCOM_I2CM_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t data)
+{
+	uint8_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.DATA.reg;
+	tmp &= ~SERCOM_I2CM_DATA_DATA_Msk;
+	tmp |= SERCOM_I2CM_DATA_DATA(data);
+	((Sercom *)hw)->I2CM.DATA.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DATA.reg &= ~SERCOM_I2CM_DATA_DATA(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DATA.reg ^= SERCOM_I2CM_DATA_DATA(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_read_DATA_DATA_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.DATA.reg;
+	tmp = (tmp & SERCOM_I2CM_DATA_DATA_Msk) >> SERCOM_I2CM_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DATA.reg |= mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_get_DATA_reg(const void *const         hw,
+                                                                    hri_sercomi2cm_data_reg_t mask)
+{
+	uint8_t tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	tmp = ((Sercom *)hw)->I2CM.DATA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DATA.reg = data;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DATA.reg &= ~mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DATA.reg ^= mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_read_DATA_reg(const void *const hw)
+{
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	return ((Sercom *)hw)->I2CM.DATA.reg;
+}
+
+static inline void hri_sercomi2cs_set_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.DATA.reg |= SERCOM_I2CS_DATA_DATA(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_get_DATA_DATA_bf(const void *const         hw,
+                                                                        hri_sercomi2cs_data_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.DATA.reg;
+	tmp = (tmp & SERCOM_I2CS_DATA_DATA(mask)) >> SERCOM_I2CS_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t data)
+{
+	uint8_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CS.DATA.reg;
+	tmp &= ~SERCOM_I2CS_DATA_DATA_Msk;
+	tmp |= SERCOM_I2CS_DATA_DATA(data);
+	((Sercom *)hw)->I2CS.DATA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.DATA.reg &= ~SERCOM_I2CS_DATA_DATA(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.DATA.reg ^= SERCOM_I2CS_DATA_DATA(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_read_DATA_DATA_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.DATA.reg;
+	tmp = (tmp & SERCOM_I2CS_DATA_DATA_Msk) >> SERCOM_I2CS_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_set_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.DATA.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_get_DATA_reg(const void *const         hw,
+                                                                    hri_sercomi2cs_data_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.DATA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_write_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.DATA.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_clear_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.DATA.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cs_toggle_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.DATA.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_read_DATA_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CS.DATA.reg;
+}
+
+static inline void hri_sercomspi_set_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DATA.reg |= SERCOM_SPI_DATA_DATA(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_data_reg_t hri_sercomspi_get_DATA_DATA_bf(const void *const        hw,
+                                                                      hri_sercomspi_data_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.DATA.reg;
+	tmp = (tmp & SERCOM_SPI_DATA_DATA(mask)) >> SERCOM_SPI_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t data)
+{
+	uint32_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.DATA.reg;
+	tmp &= ~SERCOM_SPI_DATA_DATA_Msk;
+	tmp |= SERCOM_SPI_DATA_DATA(data);
+	((Sercom *)hw)->SPI.DATA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DATA.reg &= ~SERCOM_SPI_DATA_DATA(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DATA.reg ^= SERCOM_SPI_DATA_DATA(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_data_reg_t hri_sercomspi_read_DATA_DATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.DATA.reg;
+	tmp = (tmp & SERCOM_SPI_DATA_DATA_Msk) >> SERCOM_SPI_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomspi_set_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DATA.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_data_reg_t hri_sercomspi_get_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Sercom *)hw)->SPI.DATA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DATA.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DATA.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DATA.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_data_reg_t hri_sercomspi_read_DATA_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->SPI.DATA.reg;
+}
+
+static inline void hri_sercomusart_set_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DATA.reg |= SERCOM_USART_DATA_DATA(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_data_reg_t hri_sercomusart_get_DATA_DATA_bf(const void *const          hw,
+                                                                          hri_sercomusart_data_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.DATA.reg;
+	tmp = (tmp & SERCOM_USART_DATA_DATA(mask)) >> SERCOM_USART_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.DATA.reg;
+	tmp &= ~SERCOM_USART_DATA_DATA_Msk;
+	tmp |= SERCOM_USART_DATA_DATA(data);
+	((Sercom *)hw)->USART.DATA.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DATA.reg &= ~SERCOM_USART_DATA_DATA(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DATA.reg ^= SERCOM_USART_DATA_DATA(mask);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_data_reg_t hri_sercomusart_read_DATA_DATA_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.DATA.reg;
+	tmp = (tmp & SERCOM_USART_DATA_DATA_Msk) >> SERCOM_USART_DATA_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_sercomusart_set_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DATA.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_data_reg_t hri_sercomusart_get_DATA_reg(const void *const          hw,
+                                                                      hri_sercomusart_data_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.DATA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DATA.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DATA.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DATA.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_data_reg_t hri_sercomusart_read_DATA_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.DATA.reg;
+}
+
+static inline void hri_sercomi2cm_set_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DBGCTRL.reg |= SERCOM_I2CM_DBGCTRL_DBGSTOP;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg;
+	tmp = (tmp & SERCOM_I2CM_DBGCTRL_DBGSTOP) >> SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomi2cm_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg;
+	tmp &= ~SERCOM_I2CM_DBGCTRL_DBGSTOP;
+	tmp |= value << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos;
+	((Sercom *)hw)->I2CM.DBGCTRL.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DBGCTRL.reg &= ~SERCOM_I2CM_DBGCTRL_DBGSTOP;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DBGCTRL.reg ^= SERCOM_I2CM_DBGCTRL_DBGSTOP;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DBGCTRL.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_dbgctrl_reg_t hri_sercomi2cm_get_DBGCTRL_reg(const void *const            hw,
+                                                                          hri_sercomi2cm_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_write_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DBGCTRL.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DBGCTRL.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.DBGCTRL.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_dbgctrl_reg_t hri_sercomi2cm_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CM.DBGCTRL.reg;
+}
+
+static inline void hri_sercomspi_set_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DBGCTRL.reg |= SERCOM_SPI_DBGCTRL_DBGSTOP;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomspi_get_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg;
+	tmp = (tmp & SERCOM_SPI_DBGCTRL_DBGSTOP) >> SERCOM_SPI_DBGCTRL_DBGSTOP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomspi_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg;
+	tmp &= ~SERCOM_SPI_DBGCTRL_DBGSTOP;
+	tmp |= value << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos;
+	((Sercom *)hw)->SPI.DBGCTRL.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DBGCTRL.reg &= ~SERCOM_SPI_DBGCTRL_DBGSTOP;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DBGCTRL.reg ^= SERCOM_SPI_DBGCTRL_DBGSTOP;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_set_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DBGCTRL.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_dbgctrl_reg_t hri_sercomspi_get_DBGCTRL_reg(const void *const           hw,
+                                                                        hri_sercomspi_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomspi_write_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DBGCTRL.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_clear_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DBGCTRL.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomspi_toggle_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.DBGCTRL.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_dbgctrl_reg_t hri_sercomspi_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->SPI.DBGCTRL.reg;
+}
+
+static inline void hri_sercomusart_set_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DBGCTRL.reg |= SERCOM_USART_DBGCTRL_DBGSTOP;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->USART.DBGCTRL.reg;
+	tmp = (tmp & SERCOM_USART_DBGCTRL_DBGSTOP) >> SERCOM_USART_DBGCTRL_DBGSTOP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_sercomusart_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->USART.DBGCTRL.reg;
+	tmp &= ~SERCOM_USART_DBGCTRL_DBGSTOP;
+	tmp |= value << SERCOM_USART_DBGCTRL_DBGSTOP_Pos;
+	((Sercom *)hw)->USART.DBGCTRL.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DBGCTRL.reg &= ~SERCOM_USART_DBGCTRL_DBGSTOP;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DBGCTRL.reg ^= SERCOM_USART_DBGCTRL_DBGSTOP;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_set_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DBGCTRL.reg |= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_dbgctrl_reg_t hri_sercomusart_get_DBGCTRL_reg(const void *const             hw,
+                                                                            hri_sercomusart_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Sercom *)hw)->USART.DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomusart_write_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t data)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DBGCTRL.reg = data;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_clear_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DBGCTRL.reg &= ~mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomusart_toggle_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.DBGCTRL.reg ^= mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_dbgctrl_reg_t hri_sercomusart_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.DBGCTRL.reg;
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_BUSERR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_BUSERR) >> SERCOM_I2CS_STATUS_BUSERR_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_BUSERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_BUSERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_COLL_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_COLL) >> SERCOM_I2CS_STATUS_COLL_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_COLL_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_COLL;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_RXNACK_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_RXNACK) >> SERCOM_I2CS_STATUS_RXNACK_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_RXNACK_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_RXNACK;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_DIR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_DIR) >> SERCOM_I2CS_STATUS_DIR_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_DIR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_DIR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_SR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_SR) >> SERCOM_I2CS_STATUS_SR_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_SR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_SR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_LOWTOUT_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_LOWTOUT) >> SERCOM_I2CS_STATUS_LOWTOUT_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_LOWTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_LOWTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_CLKHOLD_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_CLKHOLD) >> SERCOM_I2CS_STATUS_CLKHOLD_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_CLKHOLD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_CLKHOLD;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_SEXTTOUT_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_SEXTTOUT) >> SERCOM_I2CS_STATUS_SEXTTOUT_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_SEXTTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_SEXTTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cs_get_STATUS_HS_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_HS) >> SERCOM_I2CS_STATUS_HS_Pos;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_HS_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_HS;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_status_reg_t hri_sercomi2cs_get_STATUS_reg(const void *const           hw,
+                                                                        hri_sercomi2cs_status_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->I2CS.STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cs_clear_STATUS_reg(const void *const hw, hri_sercomi2cs_status_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CS.STATUS.reg = mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cs_status_reg_t hri_sercomi2cs_read_STATUS_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->I2CS.STATUS.reg;
+}
+
+static inline bool hri_sercomspi_get_STATUS_BUFOVF_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->SPI.STATUS.reg & SERCOM_SPI_STATUS_BUFOVF) >> SERCOM_SPI_STATUS_BUFOVF_Pos;
+}
+
+static inline void hri_sercomspi_clear_STATUS_BUFOVF_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.STATUS.reg = SERCOM_SPI_STATUS_BUFOVF;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_status_reg_t hri_sercomspi_get_STATUS_reg(const void *const          hw,
+                                                                      hri_sercomspi_status_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->SPI.STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomspi_clear_STATUS_reg(const void *const hw, hri_sercomspi_status_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->SPI.STATUS.reg = mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomspi_status_reg_t hri_sercomspi_read_STATUS_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->SPI.STATUS.reg;
+}
+
+static inline bool hri_sercomusart_get_STATUS_PERR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_PERR) >> SERCOM_USART_STATUS_PERR_Pos;
+}
+
+static inline void hri_sercomusart_clear_STATUS_PERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_PERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_STATUS_FERR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_FERR) >> SERCOM_USART_STATUS_FERR_Pos;
+}
+
+static inline void hri_sercomusart_clear_STATUS_FERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_FERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_STATUS_BUFOVF_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_BUFOVF) >> SERCOM_USART_STATUS_BUFOVF_Pos;
+}
+
+static inline void hri_sercomusart_clear_STATUS_BUFOVF_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_BUFOVF;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_STATUS_CTS_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_CTS) >> SERCOM_USART_STATUS_CTS_Pos;
+}
+
+static inline void hri_sercomusart_clear_STATUS_CTS_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_CTS;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_STATUS_ISF_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_ISF) >> SERCOM_USART_STATUS_ISF_Pos;
+}
+
+static inline void hri_sercomusart_clear_STATUS_ISF_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_ISF;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_STATUS_COLL_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_COLL) >> SERCOM_USART_STATUS_COLL_Pos;
+}
+
+static inline void hri_sercomusart_clear_STATUS_COLL_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_COLL;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_STATUS_TXE_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_TXE) >> SERCOM_USART_STATUS_TXE_Pos;
+}
+
+static inline void hri_sercomusart_clear_STATUS_TXE_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_TXE;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomusart_get_STATUS_ITER_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_ITER) >> SERCOM_USART_STATUS_ITER_Pos;
+}
+
+static inline void hri_sercomusart_clear_STATUS_ITER_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_ITER;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_status_reg_t hri_sercomusart_get_STATUS_reg(const void *const            hw,
+                                                                          hri_sercomusart_status_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Sercom *)hw)->USART.STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomusart_clear_STATUS_reg(const void *const hw, hri_sercomusart_status_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->USART.STATUS.reg = mask;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomusart_status_reg_t hri_sercomusart_read_STATUS_reg(const void *const hw)
+{
+	return ((Sercom *)hw)->USART.STATUS.reg;
+}
+
+static inline void hri_sercomi2cm_set_STATUS_BUSERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_BUSERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_STATUS_BUSERR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSERR) >> SERCOM_I2CM_STATUS_BUSERR_Pos;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_BUSERR_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= ~SERCOM_I2CM_STATUS_BUSERR;
+	tmp |= value << SERCOM_I2CM_STATUS_BUSERR_Pos;
+	((Sercom *)hw)->I2CM.STATUS.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_BUSERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_BUSERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_BUSERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_BUSERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_STATUS_ARBLOST_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_ARBLOST;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_STATUS_ARBLOST_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_ARBLOST) >> SERCOM_I2CM_STATUS_ARBLOST_Pos;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_ARBLOST_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= ~SERCOM_I2CM_STATUS_ARBLOST;
+	tmp |= value << SERCOM_I2CM_STATUS_ARBLOST_Pos;
+	((Sercom *)hw)->I2CM.STATUS.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_ARBLOST_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_ARBLOST;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_ARBLOST_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_ARBLOST;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_STATUS_RXNACK_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_RXNACK;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_STATUS_RXNACK_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) >> SERCOM_I2CM_STATUS_RXNACK_Pos;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_RXNACK_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= ~SERCOM_I2CM_STATUS_RXNACK;
+	tmp |= value << SERCOM_I2CM_STATUS_RXNACK_Pos;
+	((Sercom *)hw)->I2CM.STATUS.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_RXNACK_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_RXNACK;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_RXNACK_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_RXNACK;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_STATUS_LOWTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_LOWTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_STATUS_LOWTOUT_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_LOWTOUT) >> SERCOM_I2CM_STATUS_LOWTOUT_Pos;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_LOWTOUT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= ~SERCOM_I2CM_STATUS_LOWTOUT;
+	tmp |= value << SERCOM_I2CM_STATUS_LOWTOUT_Pos;
+	((Sercom *)hw)->I2CM.STATUS.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_LOWTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_LOWTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_LOWTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_LOWTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_STATUS_CLKHOLD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_CLKHOLD;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_STATUS_CLKHOLD_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_CLKHOLD) >> SERCOM_I2CM_STATUS_CLKHOLD_Pos;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_CLKHOLD_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= ~SERCOM_I2CM_STATUS_CLKHOLD;
+	tmp |= value << SERCOM_I2CM_STATUS_CLKHOLD_Pos;
+	((Sercom *)hw)->I2CM.STATUS.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_CLKHOLD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_CLKHOLD;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_CLKHOLD_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_CLKHOLD;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_STATUS_MEXTTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_MEXTTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_STATUS_MEXTTOUT_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_MEXTTOUT) >> SERCOM_I2CM_STATUS_MEXTTOUT_Pos;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_MEXTTOUT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= ~SERCOM_I2CM_STATUS_MEXTTOUT;
+	tmp |= value << SERCOM_I2CM_STATUS_MEXTTOUT_Pos;
+	((Sercom *)hw)->I2CM.STATUS.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_MEXTTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_MEXTTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_MEXTTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_MEXTTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_STATUS_SEXTTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_SEXTTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_STATUS_SEXTTOUT_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_SEXTTOUT) >> SERCOM_I2CM_STATUS_SEXTTOUT_Pos;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_SEXTTOUT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= ~SERCOM_I2CM_STATUS_SEXTTOUT;
+	tmp |= value << SERCOM_I2CM_STATUS_SEXTTOUT_Pos;
+	((Sercom *)hw)->I2CM.STATUS.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_SEXTTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_SEXTTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_SEXTTOUT_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_SEXTTOUT;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_set_STATUS_LENERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_LENERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_sercomi2cm_get_STATUS_LENERR_bit(const void *const hw)
+{
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_LENERR) >> SERCOM_I2CM_STATUS_LENERR_Pos;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_LENERR_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= ~SERCOM_I2CM_STATUS_LENERR;
+	tmp |= value << SERCOM_I2CM_STATUS_LENERR_Pos;
+	((Sercom *)hw)->I2CM.STATUS.reg = tmp;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_LENERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_LENERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_LENERR_bit(const void *const hw)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_LENERR;
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_get_STATUS_BUSSTATE_bf(const void *const           hw,
+                                                                                hri_sercomi2cm_status_reg_t mask)
+{
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(mask)) >> SERCOM_I2CM_STATUS_BUSSTATE_Pos;
+}
+
+static inline void hri_sercomi2cm_set_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_BUSSTATE(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_read_STATUS_BUSSTATE_bf(const void *const hw)
+{
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE_Msk) >> SERCOM_I2CM_STATUS_BUSSTATE_Pos;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t data)
+{
+	uint16_t tmp;
+	SERCOM_CRITICAL_SECTION_ENTER();
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= ~SERCOM_I2CM_STATUS_BUSSTATE_Msk;
+	tmp |= SERCOM_I2CM_STATUS_BUSSTATE(data);
+	((Sercom *)hw)->I2CM.STATUS.reg = tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_BUSSTATE(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_BUSSTATE(mask);
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_get_STATUS_reg(const void *const           hw,
+                                                                        hri_sercomi2cm_status_reg_t mask)
+{
+	uint16_t tmp;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	tmp = ((Sercom *)hw)->I2CM.STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_sercomi2cm_set_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask)
+{
+	((Sercom *)hw)->I2CM.STATUS.reg |= mask;
+}
+
+static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_read_STATUS_reg(const void *const hw)
+{
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	return ((Sercom *)hw)->I2CM.STATUS.reg;
+}
+
+static inline void hri_sercomi2cm_write_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t data)
+{
+	((Sercom *)hw)->I2CM.STATUS.reg = data;
+}
+
+static inline void hri_sercomi2cm_toggle_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask)
+{
+	((Sercom *)hw)->I2CM.STATUS.reg ^= mask;
+}
+
+static inline void hri_sercomi2cm_clear_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask)
+{
+	SERCOM_CRITICAL_SECTION_ENTER();
+	((Sercom *)hw)->I2CM.STATUS.reg = mask;
+	hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP);
+	SERCOM_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_SERCOM_L22_H_INCLUDED */
+#endif /* _SAML22_SERCOM_COMPONENT_ */
diff --git a/watch-library/hardware/hri/hri_slcd_l22.h b/watch-library/hardware/hri/hri_slcd_l22.h
new file mode 100644
index 00000000..89fde269
--- /dev/null
+++ b/watch-library/hardware/hri/hri_slcd_l22.h
@@ -0,0 +1,5440 @@
+/**
+ * \file
+ *
+ * \brief SAM SLCD
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_SLCD_COMPONENT_
+#ifndef _HRI_SLCD_L22_H_INCLUDED_
+#define _HRI_SLCD_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_SLCD_CRITICAL_SECTIONS)
+#define SLCD_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define SLCD_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define SLCD_CRITICAL_SECTION_ENTER()
+#define SLCD_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_slcd_cmindex_reg_t;
+typedef uint16_t hri_slcd_ctrlb_reg_t;
+typedef uint16_t hri_slcd_ctrlc_reg_t;
+typedef uint32_t hri_slcd_acmcfg_reg_t;
+typedef uint32_t hri_slcd_bcfg_reg_t;
+typedef uint32_t hri_slcd_cmdata_reg_t;
+typedef uint32_t hri_slcd_cmdmask_reg_t;
+typedef uint32_t hri_slcd_csrcfg_reg_t;
+typedef uint32_t hri_slcd_ctrla_reg_t;
+typedef uint32_t hri_slcd_isdata_reg_t;
+typedef uint32_t hri_slcd_lpenh_reg_t;
+typedef uint32_t hri_slcd_lpenl_reg_t;
+typedef uint32_t hri_slcd_sdatah0_reg_t;
+typedef uint32_t hri_slcd_sdatah1_reg_t;
+typedef uint32_t hri_slcd_sdatah2_reg_t;
+typedef uint32_t hri_slcd_sdatah3_reg_t;
+typedef uint32_t hri_slcd_sdatah4_reg_t;
+typedef uint32_t hri_slcd_sdatah5_reg_t;
+typedef uint32_t hri_slcd_sdatah6_reg_t;
+typedef uint32_t hri_slcd_sdatah7_reg_t;
+typedef uint32_t hri_slcd_sdatal0_reg_t;
+typedef uint32_t hri_slcd_sdatal1_reg_t;
+typedef uint32_t hri_slcd_sdatal2_reg_t;
+typedef uint32_t hri_slcd_sdatal3_reg_t;
+typedef uint32_t hri_slcd_sdatal4_reg_t;
+typedef uint32_t hri_slcd_sdatal5_reg_t;
+typedef uint32_t hri_slcd_sdatal6_reg_t;
+typedef uint32_t hri_slcd_sdatal7_reg_t;
+typedef uint32_t hri_slcd_syncbusy_reg_t;
+typedef uint8_t  hri_slcd_abmcfg_reg_t;
+typedef uint8_t  hri_slcd_cmcfg_reg_t;
+typedef uint8_t  hri_slcd_ctrld_reg_t;
+typedef uint8_t  hri_slcd_evctrl_reg_t;
+typedef uint8_t  hri_slcd_fc0_reg_t;
+typedef uint8_t  hri_slcd_fc1_reg_t;
+typedef uint8_t  hri_slcd_fc2_reg_t;
+typedef uint8_t  hri_slcd_intenset_reg_t;
+typedef uint8_t  hri_slcd_intflag_reg_t;
+typedef uint8_t  hri_slcd_status_reg_t;
+
+static inline void hri_slcd_wait_for_sync(const void *const hw, hri_slcd_syncbusy_reg_t reg)
+{
+	while (((Slcd *)hw)->SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_slcd_is_syncing(const void *const hw, hri_slcd_syncbusy_reg_t reg)
+{
+	return ((Slcd *)hw)->SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_slcd_get_INTFLAG_FC0O_bit(const void *const hw)
+{
+	return (((Slcd *)hw)->INTFLAG.reg & SLCD_INTFLAG_FC0O) >> SLCD_INTFLAG_FC0O_Pos;
+}
+
+static inline void hri_slcd_clear_INTFLAG_FC0O_bit(const void *const hw)
+{
+	((Slcd *)hw)->INTFLAG.reg = SLCD_INTFLAG_FC0O;
+}
+
+static inline bool hri_slcd_get_INTFLAG_FC1O_bit(const void *const hw)
+{
+	return (((Slcd *)hw)->INTFLAG.reg & SLCD_INTFLAG_FC1O) >> SLCD_INTFLAG_FC1O_Pos;
+}
+
+static inline void hri_slcd_clear_INTFLAG_FC1O_bit(const void *const hw)
+{
+	((Slcd *)hw)->INTFLAG.reg = SLCD_INTFLAG_FC1O;
+}
+
+static inline bool hri_slcd_get_INTFLAG_FC2O_bit(const void *const hw)
+{
+	return (((Slcd *)hw)->INTFLAG.reg & SLCD_INTFLAG_FC2O) >> SLCD_INTFLAG_FC2O_Pos;
+}
+
+static inline void hri_slcd_clear_INTFLAG_FC2O_bit(const void *const hw)
+{
+	((Slcd *)hw)->INTFLAG.reg = SLCD_INTFLAG_FC2O;
+}
+
+static inline bool hri_slcd_get_INTFLAG_VLCDRT_bit(const void *const hw)
+{
+	return (((Slcd *)hw)->INTFLAG.reg & SLCD_INTFLAG_VLCDRT) >> SLCD_INTFLAG_VLCDRT_Pos;
+}
+
+static inline void hri_slcd_clear_INTFLAG_VLCDRT_bit(const void *const hw)
+{
+	((Slcd *)hw)->INTFLAG.reg = SLCD_INTFLAG_VLCDRT;
+}
+
+static inline bool hri_slcd_get_INTFLAG_VLCDST_bit(const void *const hw)
+{
+	return (((Slcd *)hw)->INTFLAG.reg & SLCD_INTFLAG_VLCDST) >> SLCD_INTFLAG_VLCDST_Pos;
+}
+
+static inline void hri_slcd_clear_INTFLAG_VLCDST_bit(const void *const hw)
+{
+	((Slcd *)hw)->INTFLAG.reg = SLCD_INTFLAG_VLCDST;
+}
+
+static inline bool hri_slcd_get_INTFLAG_PRST_bit(const void *const hw)
+{
+	return (((Slcd *)hw)->INTFLAG.reg & SLCD_INTFLAG_PRST) >> SLCD_INTFLAG_PRST_Pos;
+}
+
+static inline void hri_slcd_clear_INTFLAG_PRST_bit(const void *const hw)
+{
+	((Slcd *)hw)->INTFLAG.reg = SLCD_INTFLAG_PRST;
+}
+
+static inline bool hri_slcd_get_interrupt_FC0O_bit(const void *const hw)
+{
+	return (((Slcd *)hw)->INTFLAG.reg & SLCD_INTFLAG_FC0O) >> SLCD_INTFLAG_FC0O_Pos;
+}
+
+static inline void hri_slcd_clear_interrupt_FC0O_bit(const void *const hw)
+{
+	((Slcd *)hw)->INTFLAG.reg = SLCD_INTFLAG_FC0O;
+}
+
+static inline bool hri_slcd_get_interrupt_FC1O_bit(const void *const hw)
+{
+	return (((Slcd *)hw)->INTFLAG.reg & SLCD_INTFLAG_FC1O) >> SLCD_INTFLAG_FC1O_Pos;
+}
+
+static inline void hri_slcd_clear_interrupt_FC1O_bit(const void *const hw)
+{
+	((Slcd *)hw)->INTFLAG.reg = SLCD_INTFLAG_FC1O;
+}
+
+static inline bool hri_slcd_get_interrupt_FC2O_bit(const void *const hw)
+{
+	return (((Slcd *)hw)->INTFLAG.reg & SLCD_INTFLAG_FC2O) >> SLCD_INTFLAG_FC2O_Pos;
+}
+
+static inline void hri_slcd_clear_interrupt_FC2O_bit(const void *const hw)
+{
+	((Slcd *)hw)->INTFLAG.reg = SLCD_INTFLAG_FC2O;
+}
+
+static inline bool hri_slcd_get_interrupt_VLCDRT_bit(const void *const hw)
+{
+	return (((Slcd *)hw)->INTFLAG.reg & SLCD_INTFLAG_VLCDRT) >> SLCD_INTFLAG_VLCDRT_Pos;
+}
+
+static inline void hri_slcd_clear_interrupt_VLCDRT_bit(const void *const hw)
+{
+	((Slcd *)hw)->INTFLAG.reg = SLCD_INTFLAG_VLCDRT;
+}
+
+static inline bool hri_slcd_get_interrupt_VLCDST_bit(const void *const hw)
+{
+	return (((Slcd *)hw)->INTFLAG.reg & SLCD_INTFLAG_VLCDST) >> SLCD_INTFLAG_VLCDST_Pos;
+}
+
+static inline void hri_slcd_clear_interrupt_VLCDST_bit(const void *const hw)
+{
+	((Slcd *)hw)->INTFLAG.reg = SLCD_INTFLAG_VLCDST;
+}
+
+static inline bool hri_slcd_get_interrupt_PRST_bit(const void *const hw)
+{
+	return (((Slcd *)hw)->INTFLAG.reg & SLCD_INTFLAG_PRST) >> SLCD_INTFLAG_PRST_Pos;
+}
+
+static inline void hri_slcd_clear_interrupt_PRST_bit(const void *const hw)
+{
+	((Slcd *)hw)->INTFLAG.reg = SLCD_INTFLAG_PRST;
+}
+
+static inline hri_slcd_intflag_reg_t hri_slcd_get_INTFLAG_reg(const void *const hw, hri_slcd_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_slcd_intflag_reg_t hri_slcd_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_slcd_clear_INTFLAG_reg(const void *const hw, hri_slcd_intflag_reg_t mask)
+{
+	((Slcd *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_slcd_set_INTEN_FC0O_bit(const void *const hw)
+{
+	((Slcd *)hw)->INTENSET.reg = SLCD_INTENSET_FC0O;
+}
+
+static inline bool hri_slcd_get_INTEN_FC0O_bit(const void *const hw)
+{
+	return (((Slcd *)hw)->INTENSET.reg & SLCD_INTENSET_FC0O) >> SLCD_INTENSET_FC0O_Pos;
+}
+
+static inline void hri_slcd_write_INTEN_FC0O_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Slcd *)hw)->INTENCLR.reg = SLCD_INTENSET_FC0O;
+	} else {
+		((Slcd *)hw)->INTENSET.reg = SLCD_INTENSET_FC0O;
+	}
+}
+
+static inline void hri_slcd_clear_INTEN_FC0O_bit(const void *const hw)
+{
+	((Slcd *)hw)->INTENCLR.reg = SLCD_INTENSET_FC0O;
+}
+
+static inline void hri_slcd_set_INTEN_FC1O_bit(const void *const hw)
+{
+	((Slcd *)hw)->INTENSET.reg = SLCD_INTENSET_FC1O;
+}
+
+static inline bool hri_slcd_get_INTEN_FC1O_bit(const void *const hw)
+{
+	return (((Slcd *)hw)->INTENSET.reg & SLCD_INTENSET_FC1O) >> SLCD_INTENSET_FC1O_Pos;
+}
+
+static inline void hri_slcd_write_INTEN_FC1O_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Slcd *)hw)->INTENCLR.reg = SLCD_INTENSET_FC1O;
+	} else {
+		((Slcd *)hw)->INTENSET.reg = SLCD_INTENSET_FC1O;
+	}
+}
+
+static inline void hri_slcd_clear_INTEN_FC1O_bit(const void *const hw)
+{
+	((Slcd *)hw)->INTENCLR.reg = SLCD_INTENSET_FC1O;
+}
+
+static inline void hri_slcd_set_INTEN_FC2O_bit(const void *const hw)
+{
+	((Slcd *)hw)->INTENSET.reg = SLCD_INTENSET_FC2O;
+}
+
+static inline bool hri_slcd_get_INTEN_FC2O_bit(const void *const hw)
+{
+	return (((Slcd *)hw)->INTENSET.reg & SLCD_INTENSET_FC2O) >> SLCD_INTENSET_FC2O_Pos;
+}
+
+static inline void hri_slcd_write_INTEN_FC2O_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Slcd *)hw)->INTENCLR.reg = SLCD_INTENSET_FC2O;
+	} else {
+		((Slcd *)hw)->INTENSET.reg = SLCD_INTENSET_FC2O;
+	}
+}
+
+static inline void hri_slcd_clear_INTEN_FC2O_bit(const void *const hw)
+{
+	((Slcd *)hw)->INTENCLR.reg = SLCD_INTENSET_FC2O;
+}
+
+static inline void hri_slcd_set_INTEN_VLCDRT_bit(const void *const hw)
+{
+	((Slcd *)hw)->INTENSET.reg = SLCD_INTENSET_VLCDRT;
+}
+
+static inline bool hri_slcd_get_INTEN_VLCDRT_bit(const void *const hw)
+{
+	return (((Slcd *)hw)->INTENSET.reg & SLCD_INTENSET_VLCDRT) >> SLCD_INTENSET_VLCDRT_Pos;
+}
+
+static inline void hri_slcd_write_INTEN_VLCDRT_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Slcd *)hw)->INTENCLR.reg = SLCD_INTENSET_VLCDRT;
+	} else {
+		((Slcd *)hw)->INTENSET.reg = SLCD_INTENSET_VLCDRT;
+	}
+}
+
+static inline void hri_slcd_clear_INTEN_VLCDRT_bit(const void *const hw)
+{
+	((Slcd *)hw)->INTENCLR.reg = SLCD_INTENSET_VLCDRT;
+}
+
+static inline void hri_slcd_set_INTEN_VLCDST_bit(const void *const hw)
+{
+	((Slcd *)hw)->INTENSET.reg = SLCD_INTENSET_VLCDST;
+}
+
+static inline bool hri_slcd_get_INTEN_VLCDST_bit(const void *const hw)
+{
+	return (((Slcd *)hw)->INTENSET.reg & SLCD_INTENSET_VLCDST) >> SLCD_INTENSET_VLCDST_Pos;
+}
+
+static inline void hri_slcd_write_INTEN_VLCDST_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Slcd *)hw)->INTENCLR.reg = SLCD_INTENSET_VLCDST;
+	} else {
+		((Slcd *)hw)->INTENSET.reg = SLCD_INTENSET_VLCDST;
+	}
+}
+
+static inline void hri_slcd_clear_INTEN_VLCDST_bit(const void *const hw)
+{
+	((Slcd *)hw)->INTENCLR.reg = SLCD_INTENSET_VLCDST;
+}
+
+static inline void hri_slcd_set_INTEN_PRST_bit(const void *const hw)
+{
+	((Slcd *)hw)->INTENSET.reg = SLCD_INTENSET_PRST;
+}
+
+static inline bool hri_slcd_get_INTEN_PRST_bit(const void *const hw)
+{
+	return (((Slcd *)hw)->INTENSET.reg & SLCD_INTENSET_PRST) >> SLCD_INTENSET_PRST_Pos;
+}
+
+static inline void hri_slcd_write_INTEN_PRST_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Slcd *)hw)->INTENCLR.reg = SLCD_INTENSET_PRST;
+	} else {
+		((Slcd *)hw)->INTENSET.reg = SLCD_INTENSET_PRST;
+	}
+}
+
+static inline void hri_slcd_clear_INTEN_PRST_bit(const void *const hw)
+{
+	((Slcd *)hw)->INTENCLR.reg = SLCD_INTENSET_PRST;
+}
+
+static inline void hri_slcd_set_INTEN_reg(const void *const hw, hri_slcd_intenset_reg_t mask)
+{
+	((Slcd *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_slcd_intenset_reg_t hri_slcd_get_INTEN_reg(const void *const hw, hri_slcd_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_slcd_intenset_reg_t hri_slcd_read_INTEN_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->INTENSET.reg;
+}
+
+static inline void hri_slcd_write_INTEN_reg(const void *const hw, hri_slcd_intenset_reg_t data)
+{
+	((Slcd *)hw)->INTENSET.reg = data;
+	((Slcd *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_slcd_clear_INTEN_reg(const void *const hw, hri_slcd_intenset_reg_t mask)
+{
+	((Slcd *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_slcd_get_STATUS_VLCDR_bit(const void *const hw)
+{
+	return (((Slcd *)hw)->STATUS.reg & SLCD_STATUS_VLCDR) >> SLCD_STATUS_VLCDR_Pos;
+}
+
+static inline bool hri_slcd_get_STATUS_PRUN_bit(const void *const hw)
+{
+	return (((Slcd *)hw)->STATUS.reg & SLCD_STATUS_PRUN) >> SLCD_STATUS_PRUN_Pos;
+}
+
+static inline bool hri_slcd_get_STATUS_VLCDS_bit(const void *const hw)
+{
+	return (((Slcd *)hw)->STATUS.reg & SLCD_STATUS_VLCDS) >> SLCD_STATUS_VLCDS_Pos;
+}
+
+static inline bool hri_slcd_get_STATUS_CMWRBUSY_bit(const void *const hw)
+{
+	return (((Slcd *)hw)->STATUS.reg & SLCD_STATUS_CMWRBUSY) >> SLCD_STATUS_CMWRBUSY_Pos;
+}
+
+static inline bool hri_slcd_get_STATUS_ACMBUSY_bit(const void *const hw)
+{
+	return (((Slcd *)hw)->STATUS.reg & SLCD_STATUS_ACMBUSY) >> SLCD_STATUS_ACMBUSY_Pos;
+}
+
+static inline bool hri_slcd_get_STATUS_ABMBUSY_bit(const void *const hw)
+{
+	return (((Slcd *)hw)->STATUS.reg & SLCD_STATUS_ABMBUSY) >> SLCD_STATUS_ABMBUSY_Pos;
+}
+
+static inline hri_slcd_status_reg_t hri_slcd_get_STATUS_reg(const void *const hw, hri_slcd_status_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_slcd_status_reg_t hri_slcd_read_STATUS_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->STATUS.reg;
+}
+
+static inline bool hri_slcd_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Slcd *)hw)->SYNCBUSY.reg & SLCD_SYNCBUSY_SWRST) >> SLCD_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_slcd_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Slcd *)hw)->SYNCBUSY.reg & SLCD_SYNCBUSY_ENABLE) >> SLCD_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_slcd_get_SYNCBUSY_CTRLD_bit(const void *const hw)
+{
+	return (((Slcd *)hw)->SYNCBUSY.reg & SLCD_SYNCBUSY_CTRLD) >> SLCD_SYNCBUSY_CTRLD_Pos;
+}
+
+static inline hri_slcd_syncbusy_reg_t hri_slcd_get_SYNCBUSY_reg(const void *const hw, hri_slcd_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_slcd_syncbusy_reg_t hri_slcd_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->SYNCBUSY.reg;
+}
+
+static inline void hri_slcd_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg |= SLCD_CTRLA_SWRST;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST);
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp = (tmp & SLCD_CTRLA_SWRST) >> SLCD_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg |= SLCD_CTRLA_ENABLE;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST | SLCD_SYNCBUSY_ENABLE);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST | SLCD_SYNCBUSY_ENABLE);
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp = (tmp & SLCD_CTRLA_ENABLE) >> SLCD_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp &= ~SLCD_CTRLA_ENABLE;
+	tmp |= value << SLCD_CTRLA_ENABLE_Pos;
+	((Slcd *)hw)->CTRLA.reg = tmp;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST | SLCD_SYNCBUSY_ENABLE);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg &= ~SLCD_CTRLA_ENABLE;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST | SLCD_SYNCBUSY_ENABLE);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg ^= SLCD_CTRLA_ENABLE;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST | SLCD_SYNCBUSY_ENABLE);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_set_CTRLA_WMOD_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg |= SLCD_CTRLA_WMOD;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_CTRLA_WMOD_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp = (tmp & SLCD_CTRLA_WMOD) >> SLCD_CTRLA_WMOD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_write_CTRLA_WMOD_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp &= ~SLCD_CTRLA_WMOD;
+	tmp |= value << SLCD_CTRLA_WMOD_Pos;
+	((Slcd *)hw)->CTRLA.reg = tmp;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLA_WMOD_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg &= ~SLCD_CTRLA_WMOD;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLA_WMOD_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg ^= SLCD_CTRLA_WMOD;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg |= SLCD_CTRLA_RUNSTDBY;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp = (tmp & SLCD_CTRLA_RUNSTDBY) >> SLCD_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp &= ~SLCD_CTRLA_RUNSTDBY;
+	tmp |= value << SLCD_CTRLA_RUNSTDBY_Pos;
+	((Slcd *)hw)->CTRLA.reg = tmp;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg &= ~SLCD_CTRLA_RUNSTDBY;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg ^= SLCD_CTRLA_RUNSTDBY;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_set_CTRLA_XVLCD_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg |= SLCD_CTRLA_XVLCD;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_CTRLA_XVLCD_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp = (tmp & SLCD_CTRLA_XVLCD) >> SLCD_CTRLA_XVLCD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_write_CTRLA_XVLCD_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp &= ~SLCD_CTRLA_XVLCD;
+	tmp |= value << SLCD_CTRLA_XVLCD_Pos;
+	((Slcd *)hw)->CTRLA.reg = tmp;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLA_XVLCD_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg &= ~SLCD_CTRLA_XVLCD;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLA_XVLCD_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg ^= SLCD_CTRLA_XVLCD;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_set_CTRLA_DUTY_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg |= SLCD_CTRLA_DUTY(mask);
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrla_reg_t hri_slcd_get_CTRLA_DUTY_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp = (tmp & SLCD_CTRLA_DUTY(mask)) >> SLCD_CTRLA_DUTY_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_CTRLA_DUTY_bf(const void *const hw, hri_slcd_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp &= ~SLCD_CTRLA_DUTY_Msk;
+	tmp |= SLCD_CTRLA_DUTY(data);
+	((Slcd *)hw)->CTRLA.reg = tmp;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLA_DUTY_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg &= ~SLCD_CTRLA_DUTY(mask);
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLA_DUTY_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg ^= SLCD_CTRLA_DUTY(mask);
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrla_reg_t hri_slcd_read_CTRLA_DUTY_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp = (tmp & SLCD_CTRLA_DUTY_Msk) >> SLCD_CTRLA_DUTY_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_CTRLA_PRESC_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg |= SLCD_CTRLA_PRESC(mask);
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrla_reg_t hri_slcd_get_CTRLA_PRESC_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp = (tmp & SLCD_CTRLA_PRESC(mask)) >> SLCD_CTRLA_PRESC_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_CTRLA_PRESC_bf(const void *const hw, hri_slcd_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp &= ~SLCD_CTRLA_PRESC_Msk;
+	tmp |= SLCD_CTRLA_PRESC(data);
+	((Slcd *)hw)->CTRLA.reg = tmp;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLA_PRESC_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg &= ~SLCD_CTRLA_PRESC(mask);
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLA_PRESC_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg ^= SLCD_CTRLA_PRESC(mask);
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrla_reg_t hri_slcd_read_CTRLA_PRESC_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp = (tmp & SLCD_CTRLA_PRESC_Msk) >> SLCD_CTRLA_PRESC_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_CTRLA_CKDIV_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg |= SLCD_CTRLA_CKDIV(mask);
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrla_reg_t hri_slcd_get_CTRLA_CKDIV_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp = (tmp & SLCD_CTRLA_CKDIV(mask)) >> SLCD_CTRLA_CKDIV_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_CTRLA_CKDIV_bf(const void *const hw, hri_slcd_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp &= ~SLCD_CTRLA_CKDIV_Msk;
+	tmp |= SLCD_CTRLA_CKDIV(data);
+	((Slcd *)hw)->CTRLA.reg = tmp;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLA_CKDIV_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg &= ~SLCD_CTRLA_CKDIV(mask);
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLA_CKDIV_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg ^= SLCD_CTRLA_CKDIV(mask);
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrla_reg_t hri_slcd_read_CTRLA_CKDIV_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp = (tmp & SLCD_CTRLA_CKDIV_Msk) >> SLCD_CTRLA_CKDIV_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_CTRLA_BIAS_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg |= SLCD_CTRLA_BIAS(mask);
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrla_reg_t hri_slcd_get_CTRLA_BIAS_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp = (tmp & SLCD_CTRLA_BIAS(mask)) >> SLCD_CTRLA_BIAS_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_CTRLA_BIAS_bf(const void *const hw, hri_slcd_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp &= ~SLCD_CTRLA_BIAS_Msk;
+	tmp |= SLCD_CTRLA_BIAS(data);
+	((Slcd *)hw)->CTRLA.reg = tmp;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLA_BIAS_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg &= ~SLCD_CTRLA_BIAS(mask);
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLA_BIAS_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg ^= SLCD_CTRLA_BIAS(mask);
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrla_reg_t hri_slcd_read_CTRLA_BIAS_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp = (tmp & SLCD_CTRLA_BIAS_Msk) >> SLCD_CTRLA_BIAS_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_CTRLA_PRF_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg |= SLCD_CTRLA_PRF(mask);
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrla_reg_t hri_slcd_get_CTRLA_PRF_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp = (tmp & SLCD_CTRLA_PRF(mask)) >> SLCD_CTRLA_PRF_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_CTRLA_PRF_bf(const void *const hw, hri_slcd_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp &= ~SLCD_CTRLA_PRF_Msk;
+	tmp |= SLCD_CTRLA_PRF(data);
+	((Slcd *)hw)->CTRLA.reg = tmp;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLA_PRF_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg &= ~SLCD_CTRLA_PRF(mask);
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLA_PRF_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg ^= SLCD_CTRLA_PRF(mask);
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrla_reg_t hri_slcd_read_CTRLA_PRF_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp = (tmp & SLCD_CTRLA_PRF_Msk) >> SLCD_CTRLA_PRF_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_CTRLA_DMFCS_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg |= SLCD_CTRLA_DMFCS(mask);
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrla_reg_t hri_slcd_get_CTRLA_DMFCS_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp = (tmp & SLCD_CTRLA_DMFCS(mask)) >> SLCD_CTRLA_DMFCS_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_CTRLA_DMFCS_bf(const void *const hw, hri_slcd_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp &= ~SLCD_CTRLA_DMFCS_Msk;
+	tmp |= SLCD_CTRLA_DMFCS(data);
+	((Slcd *)hw)->CTRLA.reg = tmp;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLA_DMFCS_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg &= ~SLCD_CTRLA_DMFCS(mask);
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLA_DMFCS_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg ^= SLCD_CTRLA_DMFCS(mask);
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrla_reg_t hri_slcd_read_CTRLA_DMFCS_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp = (tmp & SLCD_CTRLA_DMFCS_Msk) >> SLCD_CTRLA_DMFCS_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_CTRLA_RRF_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg |= SLCD_CTRLA_RRF(mask);
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrla_reg_t hri_slcd_get_CTRLA_RRF_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp = (tmp & SLCD_CTRLA_RRF(mask)) >> SLCD_CTRLA_RRF_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_CTRLA_RRF_bf(const void *const hw, hri_slcd_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp &= ~SLCD_CTRLA_RRF_Msk;
+	tmp |= SLCD_CTRLA_RRF(data);
+	((Slcd *)hw)->CTRLA.reg = tmp;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLA_RRF_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg &= ~SLCD_CTRLA_RRF(mask);
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLA_RRF_bf(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg ^= SLCD_CTRLA_RRF(mask);
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrla_reg_t hri_slcd_read_CTRLA_RRF_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp = (tmp & SLCD_CTRLA_RRF_Msk) >> SLCD_CTRLA_RRF_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_CTRLA_reg(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg |= mask;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST | SLCD_SYNCBUSY_ENABLE);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrla_reg_t hri_slcd_get_CTRLA_reg(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST | SLCD_SYNCBUSY_ENABLE);
+	tmp = ((Slcd *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_CTRLA_reg(const void *const hw, hri_slcd_ctrla_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg = data;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST | SLCD_SYNCBUSY_ENABLE);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLA_reg(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg &= ~mask;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST | SLCD_SYNCBUSY_ENABLE);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLA_reg(const void *const hw, hri_slcd_ctrla_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLA.reg ^= mask;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST | SLCD_SYNCBUSY_ENABLE);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrla_reg_t hri_slcd_read_CTRLA_reg(const void *const hw)
+{
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_SWRST | SLCD_SYNCBUSY_ENABLE);
+	return ((Slcd *)hw)->CTRLA.reg;
+}
+
+static inline void hri_slcd_set_CTRLB_BBEN_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLB.reg |= SLCD_CTRLB_BBEN;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_CTRLB_BBEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Slcd *)hw)->CTRLB.reg;
+	tmp = (tmp & SLCD_CTRLB_BBEN) >> SLCD_CTRLB_BBEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_write_CTRLB_BBEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLB.reg;
+	tmp &= ~SLCD_CTRLB_BBEN;
+	tmp |= value << SLCD_CTRLB_BBEN_Pos;
+	((Slcd *)hw)->CTRLB.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLB_BBEN_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLB.reg &= ~SLCD_CTRLB_BBEN;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLB_BBEN_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLB.reg ^= SLCD_CTRLB_BBEN;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_set_CTRLB_LREN_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLB.reg |= SLCD_CTRLB_LREN;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_CTRLB_LREN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Slcd *)hw)->CTRLB.reg;
+	tmp = (tmp & SLCD_CTRLB_LREN) >> SLCD_CTRLB_LREN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_write_CTRLB_LREN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLB.reg;
+	tmp &= ~SLCD_CTRLB_LREN;
+	tmp |= value << SLCD_CTRLB_LREN_Pos;
+	((Slcd *)hw)->CTRLB.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLB_LREN_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLB.reg &= ~SLCD_CTRLB_LREN;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLB_LREN_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLB.reg ^= SLCD_CTRLB_LREN;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_set_CTRLB_BBD_bf(const void *const hw, hri_slcd_ctrlb_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLB.reg |= SLCD_CTRLB_BBD(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrlb_reg_t hri_slcd_get_CTRLB_BBD_bf(const void *const hw, hri_slcd_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Slcd *)hw)->CTRLB.reg;
+	tmp = (tmp & SLCD_CTRLB_BBD(mask)) >> SLCD_CTRLB_BBD_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_CTRLB_BBD_bf(const void *const hw, hri_slcd_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLB.reg;
+	tmp &= ~SLCD_CTRLB_BBD_Msk;
+	tmp |= SLCD_CTRLB_BBD(data);
+	((Slcd *)hw)->CTRLB.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLB_BBD_bf(const void *const hw, hri_slcd_ctrlb_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLB.reg &= ~SLCD_CTRLB_BBD(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLB_BBD_bf(const void *const hw, hri_slcd_ctrlb_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLB.reg ^= SLCD_CTRLB_BBD(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrlb_reg_t hri_slcd_read_CTRLB_BBD_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Slcd *)hw)->CTRLB.reg;
+	tmp = (tmp & SLCD_CTRLB_BBD_Msk) >> SLCD_CTRLB_BBD_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_CTRLB_LRD_bf(const void *const hw, hri_slcd_ctrlb_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLB.reg |= SLCD_CTRLB_LRD(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrlb_reg_t hri_slcd_get_CTRLB_LRD_bf(const void *const hw, hri_slcd_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Slcd *)hw)->CTRLB.reg;
+	tmp = (tmp & SLCD_CTRLB_LRD(mask)) >> SLCD_CTRLB_LRD_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_CTRLB_LRD_bf(const void *const hw, hri_slcd_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLB.reg;
+	tmp &= ~SLCD_CTRLB_LRD_Msk;
+	tmp |= SLCD_CTRLB_LRD(data);
+	((Slcd *)hw)->CTRLB.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLB_LRD_bf(const void *const hw, hri_slcd_ctrlb_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLB.reg &= ~SLCD_CTRLB_LRD(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLB_LRD_bf(const void *const hw, hri_slcd_ctrlb_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLB.reg ^= SLCD_CTRLB_LRD(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrlb_reg_t hri_slcd_read_CTRLB_LRD_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Slcd *)hw)->CTRLB.reg;
+	tmp = (tmp & SLCD_CTRLB_LRD_Msk) >> SLCD_CTRLB_LRD_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_CTRLB_reg(const void *const hw, hri_slcd_ctrlb_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLB.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrlb_reg_t hri_slcd_get_CTRLB_reg(const void *const hw, hri_slcd_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Slcd *)hw)->CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_CTRLB_reg(const void *const hw, hri_slcd_ctrlb_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLB.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLB_reg(const void *const hw, hri_slcd_ctrlb_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLB.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLB_reg(const void *const hw, hri_slcd_ctrlb_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLB.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrlb_reg_t hri_slcd_read_CTRLB_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->CTRLB.reg;
+}
+
+static inline void hri_slcd_set_CTRLC_CLEAR_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLC.reg |= SLCD_CTRLC_CLEAR;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_CTRLC_CLEAR_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Slcd *)hw)->CTRLC.reg;
+	tmp = (tmp & SLCD_CTRLC_CLEAR) >> SLCD_CTRLC_CLEAR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_write_CTRLC_CLEAR_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLC.reg;
+	tmp &= ~SLCD_CTRLC_CLEAR;
+	tmp |= value << SLCD_CTRLC_CLEAR_Pos;
+	((Slcd *)hw)->CTRLC.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLC_CLEAR_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLC.reg &= ~SLCD_CTRLC_CLEAR;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLC_CLEAR_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLC.reg ^= SLCD_CTRLC_CLEAR;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_set_CTRLC_LOCK_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLC.reg |= SLCD_CTRLC_LOCK;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_CTRLC_LOCK_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Slcd *)hw)->CTRLC.reg;
+	tmp = (tmp & SLCD_CTRLC_LOCK) >> SLCD_CTRLC_LOCK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_write_CTRLC_LOCK_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLC.reg;
+	tmp &= ~SLCD_CTRLC_LOCK;
+	tmp |= value << SLCD_CTRLC_LOCK_Pos;
+	((Slcd *)hw)->CTRLC.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLC_LOCK_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLC.reg &= ~SLCD_CTRLC_LOCK;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLC_LOCK_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLC.reg ^= SLCD_CTRLC_LOCK;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_set_CTRLC_ABMEN_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLC.reg |= SLCD_CTRLC_ABMEN;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_CTRLC_ABMEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Slcd *)hw)->CTRLC.reg;
+	tmp = (tmp & SLCD_CTRLC_ABMEN) >> SLCD_CTRLC_ABMEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_write_CTRLC_ABMEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLC.reg;
+	tmp &= ~SLCD_CTRLC_ABMEN;
+	tmp |= value << SLCD_CTRLC_ABMEN_Pos;
+	((Slcd *)hw)->CTRLC.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLC_ABMEN_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLC.reg &= ~SLCD_CTRLC_ABMEN;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLC_ABMEN_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLC.reg ^= SLCD_CTRLC_ABMEN;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_set_CTRLC_ACMEN_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLC.reg |= SLCD_CTRLC_ACMEN;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_CTRLC_ACMEN_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Slcd *)hw)->CTRLC.reg;
+	tmp = (tmp & SLCD_CTRLC_ACMEN) >> SLCD_CTRLC_ACMEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_write_CTRLC_ACMEN_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLC.reg;
+	tmp &= ~SLCD_CTRLC_ACMEN;
+	tmp |= value << SLCD_CTRLC_ACMEN_Pos;
+	((Slcd *)hw)->CTRLC.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLC_ACMEN_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLC.reg &= ~SLCD_CTRLC_ACMEN;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLC_ACMEN_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLC.reg ^= SLCD_CTRLC_ACMEN;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_set_CTRLC_CTST_bf(const void *const hw, hri_slcd_ctrlc_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLC.reg |= SLCD_CTRLC_CTST(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrlc_reg_t hri_slcd_get_CTRLC_CTST_bf(const void *const hw, hri_slcd_ctrlc_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Slcd *)hw)->CTRLC.reg;
+	tmp = (tmp & SLCD_CTRLC_CTST(mask)) >> SLCD_CTRLC_CTST_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_CTRLC_CTST_bf(const void *const hw, hri_slcd_ctrlc_reg_t data)
+{
+	uint16_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLC.reg;
+	tmp &= ~SLCD_CTRLC_CTST_Msk;
+	tmp |= SLCD_CTRLC_CTST(data);
+	((Slcd *)hw)->CTRLC.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLC_CTST_bf(const void *const hw, hri_slcd_ctrlc_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLC.reg &= ~SLCD_CTRLC_CTST(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLC_CTST_bf(const void *const hw, hri_slcd_ctrlc_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLC.reg ^= SLCD_CTRLC_CTST(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrlc_reg_t hri_slcd_read_CTRLC_CTST_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Slcd *)hw)->CTRLC.reg;
+	tmp = (tmp & SLCD_CTRLC_CTST_Msk) >> SLCD_CTRLC_CTST_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_CTRLC_LPPM_bf(const void *const hw, hri_slcd_ctrlc_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLC.reg |= SLCD_CTRLC_LPPM(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrlc_reg_t hri_slcd_get_CTRLC_LPPM_bf(const void *const hw, hri_slcd_ctrlc_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Slcd *)hw)->CTRLC.reg;
+	tmp = (tmp & SLCD_CTRLC_LPPM(mask)) >> SLCD_CTRLC_LPPM_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_CTRLC_LPPM_bf(const void *const hw, hri_slcd_ctrlc_reg_t data)
+{
+	uint16_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLC.reg;
+	tmp &= ~SLCD_CTRLC_LPPM_Msk;
+	tmp |= SLCD_CTRLC_LPPM(data);
+	((Slcd *)hw)->CTRLC.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLC_LPPM_bf(const void *const hw, hri_slcd_ctrlc_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLC.reg &= ~SLCD_CTRLC_LPPM(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLC_LPPM_bf(const void *const hw, hri_slcd_ctrlc_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLC.reg ^= SLCD_CTRLC_LPPM(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrlc_reg_t hri_slcd_read_CTRLC_LPPM_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Slcd *)hw)->CTRLC.reg;
+	tmp = (tmp & SLCD_CTRLC_LPPM_Msk) >> SLCD_CTRLC_LPPM_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_CTRLC_reg(const void *const hw, hri_slcd_ctrlc_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLC.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrlc_reg_t hri_slcd_get_CTRLC_reg(const void *const hw, hri_slcd_ctrlc_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Slcd *)hw)->CTRLC.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_CTRLC_reg(const void *const hw, hri_slcd_ctrlc_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLC.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLC_reg(const void *const hw, hri_slcd_ctrlc_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLC.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLC_reg(const void *const hw, hri_slcd_ctrlc_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLC.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrlc_reg_t hri_slcd_read_CTRLC_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->CTRLC.reg;
+}
+
+static inline void hri_slcd_set_CTRLD_BLANK_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLD.reg |= SLCD_CTRLD_BLANK;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_CTRLD_BLANK_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->CTRLD.reg;
+	tmp = (tmp & SLCD_CTRLD_BLANK) >> SLCD_CTRLD_BLANK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_write_CTRLD_BLANK_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLD.reg;
+	tmp &= ~SLCD_CTRLD_BLANK;
+	tmp |= value << SLCD_CTRLD_BLANK_Pos;
+	((Slcd *)hw)->CTRLD.reg = tmp;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLD_BLANK_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLD.reg &= ~SLCD_CTRLD_BLANK;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLD_BLANK_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLD.reg ^= SLCD_CTRLD_BLANK;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_set_CTRLD_BLINK_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLD.reg |= SLCD_CTRLD_BLINK;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_CTRLD_BLINK_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->CTRLD.reg;
+	tmp = (tmp & SLCD_CTRLD_BLINK) >> SLCD_CTRLD_BLINK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_write_CTRLD_BLINK_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLD.reg;
+	tmp &= ~SLCD_CTRLD_BLINK;
+	tmp |= value << SLCD_CTRLD_BLINK_Pos;
+	((Slcd *)hw)->CTRLD.reg = tmp;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLD_BLINK_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLD.reg &= ~SLCD_CTRLD_BLINK;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLD_BLINK_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLD.reg ^= SLCD_CTRLD_BLINK;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_set_CTRLD_CSREN_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLD.reg |= SLCD_CTRLD_CSREN;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_CTRLD_CSREN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->CTRLD.reg;
+	tmp = (tmp & SLCD_CTRLD_CSREN) >> SLCD_CTRLD_CSREN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_write_CTRLD_CSREN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLD.reg;
+	tmp &= ~SLCD_CTRLD_CSREN;
+	tmp |= value << SLCD_CTRLD_CSREN_Pos;
+	((Slcd *)hw)->CTRLD.reg = tmp;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLD_CSREN_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLD.reg &= ~SLCD_CTRLD_CSREN;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLD_CSREN_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLD.reg ^= SLCD_CTRLD_CSREN;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_set_CTRLD_FC0EN_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLD.reg |= SLCD_CTRLD_FC0EN;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_CTRLD_FC0EN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->CTRLD.reg;
+	tmp = (tmp & SLCD_CTRLD_FC0EN) >> SLCD_CTRLD_FC0EN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_write_CTRLD_FC0EN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLD.reg;
+	tmp &= ~SLCD_CTRLD_FC0EN;
+	tmp |= value << SLCD_CTRLD_FC0EN_Pos;
+	((Slcd *)hw)->CTRLD.reg = tmp;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLD_FC0EN_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLD.reg &= ~SLCD_CTRLD_FC0EN;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLD_FC0EN_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLD.reg ^= SLCD_CTRLD_FC0EN;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_set_CTRLD_FC1EN_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLD.reg |= SLCD_CTRLD_FC1EN;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_CTRLD_FC1EN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->CTRLD.reg;
+	tmp = (tmp & SLCD_CTRLD_FC1EN) >> SLCD_CTRLD_FC1EN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_write_CTRLD_FC1EN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLD.reg;
+	tmp &= ~SLCD_CTRLD_FC1EN;
+	tmp |= value << SLCD_CTRLD_FC1EN_Pos;
+	((Slcd *)hw)->CTRLD.reg = tmp;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLD_FC1EN_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLD.reg &= ~SLCD_CTRLD_FC1EN;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLD_FC1EN_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLD.reg ^= SLCD_CTRLD_FC1EN;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_set_CTRLD_FC2EN_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLD.reg |= SLCD_CTRLD_FC2EN;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_CTRLD_FC2EN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->CTRLD.reg;
+	tmp = (tmp & SLCD_CTRLD_FC2EN) >> SLCD_CTRLD_FC2EN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_write_CTRLD_FC2EN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLD.reg;
+	tmp &= ~SLCD_CTRLD_FC2EN;
+	tmp |= value << SLCD_CTRLD_FC2EN_Pos;
+	((Slcd *)hw)->CTRLD.reg = tmp;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLD_FC2EN_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLD.reg &= ~SLCD_CTRLD_FC2EN;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLD_FC2EN_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLD.reg ^= SLCD_CTRLD_FC2EN;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_set_CTRLD_DISPEN_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLD.reg |= SLCD_CTRLD_DISPEN;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_CTRLD_DISPEN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->CTRLD.reg;
+	tmp = (tmp & SLCD_CTRLD_DISPEN) >> SLCD_CTRLD_DISPEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_write_CTRLD_DISPEN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CTRLD.reg;
+	tmp &= ~SLCD_CTRLD_DISPEN;
+	tmp |= value << SLCD_CTRLD_DISPEN_Pos;
+	((Slcd *)hw)->CTRLD.reg = tmp;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLD_DISPEN_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLD.reg &= ~SLCD_CTRLD_DISPEN;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLD_DISPEN_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLD.reg ^= SLCD_CTRLD_DISPEN;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_set_CTRLD_reg(const void *const hw, hri_slcd_ctrld_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLD.reg |= mask;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrld_reg_t hri_slcd_get_CTRLD_reg(const void *const hw, hri_slcd_ctrld_reg_t mask)
+{
+	uint8_t tmp;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	tmp = ((Slcd *)hw)->CTRLD.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_CTRLD_reg(const void *const hw, hri_slcd_ctrld_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLD.reg = data;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CTRLD_reg(const void *const hw, hri_slcd_ctrld_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLD.reg &= ~mask;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CTRLD_reg(const void *const hw, hri_slcd_ctrld_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CTRLD.reg ^= mask;
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_ctrld_reg_t hri_slcd_read_CTRLD_reg(const void *const hw)
+{
+	hri_slcd_wait_for_sync(hw, SLCD_SYNCBUSY_MASK);
+	return ((Slcd *)hw)->CTRLD.reg;
+}
+
+static inline void hri_slcd_set_EVCTRL_FC0OEO_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->EVCTRL.reg |= SLCD_EVCTRL_FC0OEO;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_EVCTRL_FC0OEO_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->EVCTRL.reg;
+	tmp = (tmp & SLCD_EVCTRL_FC0OEO) >> SLCD_EVCTRL_FC0OEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_write_EVCTRL_FC0OEO_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->EVCTRL.reg;
+	tmp &= ~SLCD_EVCTRL_FC0OEO;
+	tmp |= value << SLCD_EVCTRL_FC0OEO_Pos;
+	((Slcd *)hw)->EVCTRL.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_EVCTRL_FC0OEO_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->EVCTRL.reg &= ~SLCD_EVCTRL_FC0OEO;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_EVCTRL_FC0OEO_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->EVCTRL.reg ^= SLCD_EVCTRL_FC0OEO;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_set_EVCTRL_FC1OEO_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->EVCTRL.reg |= SLCD_EVCTRL_FC1OEO;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_EVCTRL_FC1OEO_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->EVCTRL.reg;
+	tmp = (tmp & SLCD_EVCTRL_FC1OEO) >> SLCD_EVCTRL_FC1OEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_write_EVCTRL_FC1OEO_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->EVCTRL.reg;
+	tmp &= ~SLCD_EVCTRL_FC1OEO;
+	tmp |= value << SLCD_EVCTRL_FC1OEO_Pos;
+	((Slcd *)hw)->EVCTRL.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_EVCTRL_FC1OEO_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->EVCTRL.reg &= ~SLCD_EVCTRL_FC1OEO;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_EVCTRL_FC1OEO_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->EVCTRL.reg ^= SLCD_EVCTRL_FC1OEO;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_set_EVCTRL_FC2OEO_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->EVCTRL.reg |= SLCD_EVCTRL_FC2OEO;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_EVCTRL_FC2OEO_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->EVCTRL.reg;
+	tmp = (tmp & SLCD_EVCTRL_FC2OEO) >> SLCD_EVCTRL_FC2OEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_write_EVCTRL_FC2OEO_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->EVCTRL.reg;
+	tmp &= ~SLCD_EVCTRL_FC2OEO;
+	tmp |= value << SLCD_EVCTRL_FC2OEO_Pos;
+	((Slcd *)hw)->EVCTRL.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_EVCTRL_FC2OEO_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->EVCTRL.reg &= ~SLCD_EVCTRL_FC2OEO;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_EVCTRL_FC2OEO_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->EVCTRL.reg ^= SLCD_EVCTRL_FC2OEO;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_set_EVCTRL_reg(const void *const hw, hri_slcd_evctrl_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->EVCTRL.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_evctrl_reg_t hri_slcd_get_EVCTRL_reg(const void *const hw, hri_slcd_evctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_EVCTRL_reg(const void *const hw, hri_slcd_evctrl_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->EVCTRL.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_EVCTRL_reg(const void *const hw, hri_slcd_evctrl_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->EVCTRL.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_EVCTRL_reg(const void *const hw, hri_slcd_evctrl_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->EVCTRL.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_evctrl_reg_t hri_slcd_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->EVCTRL.reg;
+}
+
+static inline void hri_slcd_set_FC0_PB_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC0.reg |= SLCD_FC0_PB;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_FC0_PB_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->FC0.reg;
+	tmp = (tmp & SLCD_FC0_PB) >> SLCD_FC0_PB_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_write_FC0_PB_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->FC0.reg;
+	tmp &= ~SLCD_FC0_PB;
+	tmp |= value << SLCD_FC0_PB_Pos;
+	((Slcd *)hw)->FC0.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_FC0_PB_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC0.reg &= ~SLCD_FC0_PB;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_FC0_PB_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC0.reg ^= SLCD_FC0_PB;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_set_FC0_OVF_bf(const void *const hw, hri_slcd_fc0_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC0.reg |= SLCD_FC0_OVF(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_fc0_reg_t hri_slcd_get_FC0_OVF_bf(const void *const hw, hri_slcd_fc0_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->FC0.reg;
+	tmp = (tmp & SLCD_FC0_OVF(mask)) >> SLCD_FC0_OVF_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_FC0_OVF_bf(const void *const hw, hri_slcd_fc0_reg_t data)
+{
+	uint8_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->FC0.reg;
+	tmp &= ~SLCD_FC0_OVF_Msk;
+	tmp |= SLCD_FC0_OVF(data);
+	((Slcd *)hw)->FC0.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_FC0_OVF_bf(const void *const hw, hri_slcd_fc0_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC0.reg &= ~SLCD_FC0_OVF(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_FC0_OVF_bf(const void *const hw, hri_slcd_fc0_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC0.reg ^= SLCD_FC0_OVF(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_fc0_reg_t hri_slcd_read_FC0_OVF_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->FC0.reg;
+	tmp = (tmp & SLCD_FC0_OVF_Msk) >> SLCD_FC0_OVF_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_FC0_reg(const void *const hw, hri_slcd_fc0_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC0.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_fc0_reg_t hri_slcd_get_FC0_reg(const void *const hw, hri_slcd_fc0_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->FC0.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_FC0_reg(const void *const hw, hri_slcd_fc0_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC0.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_FC0_reg(const void *const hw, hri_slcd_fc0_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC0.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_FC0_reg(const void *const hw, hri_slcd_fc0_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC0.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_fc0_reg_t hri_slcd_read_FC0_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->FC0.reg;
+}
+
+static inline void hri_slcd_set_FC1_PB_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC1.reg |= SLCD_FC1_PB;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_FC1_PB_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->FC1.reg;
+	tmp = (tmp & SLCD_FC1_PB) >> SLCD_FC1_PB_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_write_FC1_PB_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->FC1.reg;
+	tmp &= ~SLCD_FC1_PB;
+	tmp |= value << SLCD_FC1_PB_Pos;
+	((Slcd *)hw)->FC1.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_FC1_PB_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC1.reg &= ~SLCD_FC1_PB;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_FC1_PB_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC1.reg ^= SLCD_FC1_PB;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_set_FC1_OVF_bf(const void *const hw, hri_slcd_fc1_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC1.reg |= SLCD_FC1_OVF(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_fc1_reg_t hri_slcd_get_FC1_OVF_bf(const void *const hw, hri_slcd_fc1_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->FC1.reg;
+	tmp = (tmp & SLCD_FC1_OVF(mask)) >> SLCD_FC1_OVF_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_FC1_OVF_bf(const void *const hw, hri_slcd_fc1_reg_t data)
+{
+	uint8_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->FC1.reg;
+	tmp &= ~SLCD_FC1_OVF_Msk;
+	tmp |= SLCD_FC1_OVF(data);
+	((Slcd *)hw)->FC1.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_FC1_OVF_bf(const void *const hw, hri_slcd_fc1_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC1.reg &= ~SLCD_FC1_OVF(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_FC1_OVF_bf(const void *const hw, hri_slcd_fc1_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC1.reg ^= SLCD_FC1_OVF(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_fc1_reg_t hri_slcd_read_FC1_OVF_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->FC1.reg;
+	tmp = (tmp & SLCD_FC1_OVF_Msk) >> SLCD_FC1_OVF_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_FC1_reg(const void *const hw, hri_slcd_fc1_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC1.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_fc1_reg_t hri_slcd_get_FC1_reg(const void *const hw, hri_slcd_fc1_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->FC1.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_FC1_reg(const void *const hw, hri_slcd_fc1_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC1.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_FC1_reg(const void *const hw, hri_slcd_fc1_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC1.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_FC1_reg(const void *const hw, hri_slcd_fc1_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC1.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_fc1_reg_t hri_slcd_read_FC1_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->FC1.reg;
+}
+
+static inline void hri_slcd_set_FC2_PB_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC2.reg |= SLCD_FC2_PB;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_FC2_PB_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->FC2.reg;
+	tmp = (tmp & SLCD_FC2_PB) >> SLCD_FC2_PB_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_write_FC2_PB_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->FC2.reg;
+	tmp &= ~SLCD_FC2_PB;
+	tmp |= value << SLCD_FC2_PB_Pos;
+	((Slcd *)hw)->FC2.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_FC2_PB_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC2.reg &= ~SLCD_FC2_PB;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_FC2_PB_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC2.reg ^= SLCD_FC2_PB;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_set_FC2_OVF_bf(const void *const hw, hri_slcd_fc2_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC2.reg |= SLCD_FC2_OVF(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_fc2_reg_t hri_slcd_get_FC2_OVF_bf(const void *const hw, hri_slcd_fc2_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->FC2.reg;
+	tmp = (tmp & SLCD_FC2_OVF(mask)) >> SLCD_FC2_OVF_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_FC2_OVF_bf(const void *const hw, hri_slcd_fc2_reg_t data)
+{
+	uint8_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->FC2.reg;
+	tmp &= ~SLCD_FC2_OVF_Msk;
+	tmp |= SLCD_FC2_OVF(data);
+	((Slcd *)hw)->FC2.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_FC2_OVF_bf(const void *const hw, hri_slcd_fc2_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC2.reg &= ~SLCD_FC2_OVF(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_FC2_OVF_bf(const void *const hw, hri_slcd_fc2_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC2.reg ^= SLCD_FC2_OVF(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_fc2_reg_t hri_slcd_read_FC2_OVF_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->FC2.reg;
+	tmp = (tmp & SLCD_FC2_OVF_Msk) >> SLCD_FC2_OVF_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_FC2_reg(const void *const hw, hri_slcd_fc2_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC2.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_fc2_reg_t hri_slcd_get_FC2_reg(const void *const hw, hri_slcd_fc2_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->FC2.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_FC2_reg(const void *const hw, hri_slcd_fc2_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC2.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_FC2_reg(const void *const hw, hri_slcd_fc2_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC2.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_FC2_reg(const void *const hw, hri_slcd_fc2_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->FC2.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_fc2_reg_t hri_slcd_read_FC2_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->FC2.reg;
+}
+
+static inline void hri_slcd_set_LPENL_LPEN_bf(const void *const hw, hri_slcd_lpenl_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->LPENL.reg |= SLCD_LPENL_LPEN(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_lpenl_reg_t hri_slcd_get_LPENL_LPEN_bf(const void *const hw, hri_slcd_lpenl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->LPENL.reg;
+	tmp = (tmp & SLCD_LPENL_LPEN(mask)) >> SLCD_LPENL_LPEN_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_LPENL_LPEN_bf(const void *const hw, hri_slcd_lpenl_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->LPENL.reg;
+	tmp &= ~SLCD_LPENL_LPEN_Msk;
+	tmp |= SLCD_LPENL_LPEN(data);
+	((Slcd *)hw)->LPENL.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_LPENL_LPEN_bf(const void *const hw, hri_slcd_lpenl_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->LPENL.reg &= ~SLCD_LPENL_LPEN(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_LPENL_LPEN_bf(const void *const hw, hri_slcd_lpenl_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->LPENL.reg ^= SLCD_LPENL_LPEN(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_lpenl_reg_t hri_slcd_read_LPENL_LPEN_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->LPENL.reg;
+	tmp = (tmp & SLCD_LPENL_LPEN_Msk) >> SLCD_LPENL_LPEN_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_LPENL_reg(const void *const hw, hri_slcd_lpenl_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->LPENL.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_lpenl_reg_t hri_slcd_get_LPENL_reg(const void *const hw, hri_slcd_lpenl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->LPENL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_LPENL_reg(const void *const hw, hri_slcd_lpenl_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->LPENL.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_LPENL_reg(const void *const hw, hri_slcd_lpenl_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->LPENL.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_LPENL_reg(const void *const hw, hri_slcd_lpenl_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->LPENL.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_lpenl_reg_t hri_slcd_read_LPENL_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->LPENL.reg;
+}
+
+static inline void hri_slcd_set_LPENH_LPEN_bf(const void *const hw, hri_slcd_lpenh_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->LPENH.reg |= SLCD_LPENH_LPEN(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_lpenh_reg_t hri_slcd_get_LPENH_LPEN_bf(const void *const hw, hri_slcd_lpenh_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->LPENH.reg;
+	tmp = (tmp & SLCD_LPENH_LPEN(mask)) >> SLCD_LPENH_LPEN_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_LPENH_LPEN_bf(const void *const hw, hri_slcd_lpenh_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->LPENH.reg;
+	tmp &= ~SLCD_LPENH_LPEN_Msk;
+	tmp |= SLCD_LPENH_LPEN(data);
+	((Slcd *)hw)->LPENH.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_LPENH_LPEN_bf(const void *const hw, hri_slcd_lpenh_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->LPENH.reg &= ~SLCD_LPENH_LPEN(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_LPENH_LPEN_bf(const void *const hw, hri_slcd_lpenh_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->LPENH.reg ^= SLCD_LPENH_LPEN(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_lpenh_reg_t hri_slcd_read_LPENH_LPEN_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->LPENH.reg;
+	tmp = (tmp & SLCD_LPENH_LPEN_Msk) >> SLCD_LPENH_LPEN_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_LPENH_reg(const void *const hw, hri_slcd_lpenh_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->LPENH.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_lpenh_reg_t hri_slcd_get_LPENH_reg(const void *const hw, hri_slcd_lpenh_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->LPENH.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_LPENH_reg(const void *const hw, hri_slcd_lpenh_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->LPENH.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_LPENH_reg(const void *const hw, hri_slcd_lpenh_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->LPENH.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_LPENH_reg(const void *const hw, hri_slcd_lpenh_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->LPENH.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_lpenh_reg_t hri_slcd_read_LPENH_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->LPENH.reg;
+}
+
+static inline void hri_slcd_set_SDATAL0_SDATA_bf(const void *const hw, hri_slcd_sdatal0_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL0.reg |= SLCD_SDATAL0_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal0_reg_t hri_slcd_get_SDATAL0_SDATA_bf(const void *const hw, hri_slcd_sdatal0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAL0.reg;
+	tmp = (tmp & SLCD_SDATAL0_SDATA(mask)) >> SLCD_SDATAL0_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAL0_SDATA_bf(const void *const hw, hri_slcd_sdatal0_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->SDATAL0.reg;
+	tmp &= ~SLCD_SDATAL0_SDATA_Msk;
+	tmp |= SLCD_SDATAL0_SDATA(data);
+	((Slcd *)hw)->SDATAL0.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAL0_SDATA_bf(const void *const hw, hri_slcd_sdatal0_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL0.reg &= ~SLCD_SDATAL0_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAL0_SDATA_bf(const void *const hw, hri_slcd_sdatal0_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL0.reg ^= SLCD_SDATAL0_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal0_reg_t hri_slcd_read_SDATAL0_SDATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAL0.reg;
+	tmp = (tmp & SLCD_SDATAL0_SDATA_Msk) >> SLCD_SDATAL0_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_SDATAL0_reg(const void *const hw, hri_slcd_sdatal0_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL0.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal0_reg_t hri_slcd_get_SDATAL0_reg(const void *const hw, hri_slcd_sdatal0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAL0.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAL0_reg(const void *const hw, hri_slcd_sdatal0_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL0.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAL0_reg(const void *const hw, hri_slcd_sdatal0_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL0.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAL0_reg(const void *const hw, hri_slcd_sdatal0_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL0.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal0_reg_t hri_slcd_read_SDATAL0_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->SDATAL0.reg;
+}
+
+static inline void hri_slcd_set_SDATAH0_SDATA_bf(const void *const hw, hri_slcd_sdatah0_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH0.reg |= SLCD_SDATAH0_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah0_reg_t hri_slcd_get_SDATAH0_SDATA_bf(const void *const hw, hri_slcd_sdatah0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAH0.reg;
+	tmp = (tmp & SLCD_SDATAH0_SDATA(mask)) >> SLCD_SDATAH0_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAH0_SDATA_bf(const void *const hw, hri_slcd_sdatah0_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->SDATAH0.reg;
+	tmp &= ~SLCD_SDATAH0_SDATA_Msk;
+	tmp |= SLCD_SDATAH0_SDATA(data);
+	((Slcd *)hw)->SDATAH0.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAH0_SDATA_bf(const void *const hw, hri_slcd_sdatah0_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH0.reg &= ~SLCD_SDATAH0_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAH0_SDATA_bf(const void *const hw, hri_slcd_sdatah0_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH0.reg ^= SLCD_SDATAH0_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah0_reg_t hri_slcd_read_SDATAH0_SDATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAH0.reg;
+	tmp = (tmp & SLCD_SDATAH0_SDATA_Msk) >> SLCD_SDATAH0_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_SDATAH0_reg(const void *const hw, hri_slcd_sdatah0_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH0.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah0_reg_t hri_slcd_get_SDATAH0_reg(const void *const hw, hri_slcd_sdatah0_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAH0.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAH0_reg(const void *const hw, hri_slcd_sdatah0_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH0.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAH0_reg(const void *const hw, hri_slcd_sdatah0_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH0.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAH0_reg(const void *const hw, hri_slcd_sdatah0_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH0.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah0_reg_t hri_slcd_read_SDATAH0_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->SDATAH0.reg;
+}
+
+static inline void hri_slcd_set_SDATAL1_SDATA_bf(const void *const hw, hri_slcd_sdatal1_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL1.reg |= SLCD_SDATAL1_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal1_reg_t hri_slcd_get_SDATAL1_SDATA_bf(const void *const hw, hri_slcd_sdatal1_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAL1.reg;
+	tmp = (tmp & SLCD_SDATAL1_SDATA(mask)) >> SLCD_SDATAL1_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAL1_SDATA_bf(const void *const hw, hri_slcd_sdatal1_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->SDATAL1.reg;
+	tmp &= ~SLCD_SDATAL1_SDATA_Msk;
+	tmp |= SLCD_SDATAL1_SDATA(data);
+	((Slcd *)hw)->SDATAL1.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAL1_SDATA_bf(const void *const hw, hri_slcd_sdatal1_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL1.reg &= ~SLCD_SDATAL1_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAL1_SDATA_bf(const void *const hw, hri_slcd_sdatal1_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL1.reg ^= SLCD_SDATAL1_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal1_reg_t hri_slcd_read_SDATAL1_SDATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAL1.reg;
+	tmp = (tmp & SLCD_SDATAL1_SDATA_Msk) >> SLCD_SDATAL1_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_SDATAL1_reg(const void *const hw, hri_slcd_sdatal1_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL1.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal1_reg_t hri_slcd_get_SDATAL1_reg(const void *const hw, hri_slcd_sdatal1_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAL1.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAL1_reg(const void *const hw, hri_slcd_sdatal1_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL1.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAL1_reg(const void *const hw, hri_slcd_sdatal1_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL1.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAL1_reg(const void *const hw, hri_slcd_sdatal1_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL1.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal1_reg_t hri_slcd_read_SDATAL1_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->SDATAL1.reg;
+}
+
+static inline void hri_slcd_set_SDATAH1_SDATA_bf(const void *const hw, hri_slcd_sdatah1_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH1.reg |= SLCD_SDATAH1_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah1_reg_t hri_slcd_get_SDATAH1_SDATA_bf(const void *const hw, hri_slcd_sdatah1_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAH1.reg;
+	tmp = (tmp & SLCD_SDATAH1_SDATA(mask)) >> SLCD_SDATAH1_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAH1_SDATA_bf(const void *const hw, hri_slcd_sdatah1_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->SDATAH1.reg;
+	tmp &= ~SLCD_SDATAH1_SDATA_Msk;
+	tmp |= SLCD_SDATAH1_SDATA(data);
+	((Slcd *)hw)->SDATAH1.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAH1_SDATA_bf(const void *const hw, hri_slcd_sdatah1_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH1.reg &= ~SLCD_SDATAH1_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAH1_SDATA_bf(const void *const hw, hri_slcd_sdatah1_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH1.reg ^= SLCD_SDATAH1_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah1_reg_t hri_slcd_read_SDATAH1_SDATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAH1.reg;
+	tmp = (tmp & SLCD_SDATAH1_SDATA_Msk) >> SLCD_SDATAH1_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_SDATAH1_reg(const void *const hw, hri_slcd_sdatah1_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH1.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah1_reg_t hri_slcd_get_SDATAH1_reg(const void *const hw, hri_slcd_sdatah1_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAH1.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAH1_reg(const void *const hw, hri_slcd_sdatah1_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH1.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAH1_reg(const void *const hw, hri_slcd_sdatah1_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH1.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAH1_reg(const void *const hw, hri_slcd_sdatah1_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH1.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah1_reg_t hri_slcd_read_SDATAH1_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->SDATAH1.reg;
+}
+
+static inline void hri_slcd_set_SDATAL2_SDATA_bf(const void *const hw, hri_slcd_sdatal2_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL2.reg |= SLCD_SDATAL2_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal2_reg_t hri_slcd_get_SDATAL2_SDATA_bf(const void *const hw, hri_slcd_sdatal2_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAL2.reg;
+	tmp = (tmp & SLCD_SDATAL2_SDATA(mask)) >> SLCD_SDATAL2_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAL2_SDATA_bf(const void *const hw, hri_slcd_sdatal2_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->SDATAL2.reg;
+	tmp &= ~SLCD_SDATAL2_SDATA_Msk;
+	tmp |= SLCD_SDATAL2_SDATA(data);
+	((Slcd *)hw)->SDATAL2.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAL2_SDATA_bf(const void *const hw, hri_slcd_sdatal2_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL2.reg &= ~SLCD_SDATAL2_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAL2_SDATA_bf(const void *const hw, hri_slcd_sdatal2_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL2.reg ^= SLCD_SDATAL2_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal2_reg_t hri_slcd_read_SDATAL2_SDATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAL2.reg;
+	tmp = (tmp & SLCD_SDATAL2_SDATA_Msk) >> SLCD_SDATAL2_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_SDATAL2_reg(const void *const hw, hri_slcd_sdatal2_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL2.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal2_reg_t hri_slcd_get_SDATAL2_reg(const void *const hw, hri_slcd_sdatal2_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAL2.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAL2_reg(const void *const hw, hri_slcd_sdatal2_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL2.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAL2_reg(const void *const hw, hri_slcd_sdatal2_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL2.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAL2_reg(const void *const hw, hri_slcd_sdatal2_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL2.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal2_reg_t hri_slcd_read_SDATAL2_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->SDATAL2.reg;
+}
+
+static inline void hri_slcd_set_SDATAH2_SDATA_bf(const void *const hw, hri_slcd_sdatah2_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH2.reg |= SLCD_SDATAH2_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah2_reg_t hri_slcd_get_SDATAH2_SDATA_bf(const void *const hw, hri_slcd_sdatah2_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAH2.reg;
+	tmp = (tmp & SLCD_SDATAH2_SDATA(mask)) >> SLCD_SDATAH2_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAH2_SDATA_bf(const void *const hw, hri_slcd_sdatah2_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->SDATAH2.reg;
+	tmp &= ~SLCD_SDATAH2_SDATA_Msk;
+	tmp |= SLCD_SDATAH2_SDATA(data);
+	((Slcd *)hw)->SDATAH2.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAH2_SDATA_bf(const void *const hw, hri_slcd_sdatah2_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH2.reg &= ~SLCD_SDATAH2_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAH2_SDATA_bf(const void *const hw, hri_slcd_sdatah2_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH2.reg ^= SLCD_SDATAH2_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah2_reg_t hri_slcd_read_SDATAH2_SDATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAH2.reg;
+	tmp = (tmp & SLCD_SDATAH2_SDATA_Msk) >> SLCD_SDATAH2_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_SDATAH2_reg(const void *const hw, hri_slcd_sdatah2_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH2.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah2_reg_t hri_slcd_get_SDATAH2_reg(const void *const hw, hri_slcd_sdatah2_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAH2.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAH2_reg(const void *const hw, hri_slcd_sdatah2_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH2.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAH2_reg(const void *const hw, hri_slcd_sdatah2_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH2.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAH2_reg(const void *const hw, hri_slcd_sdatah2_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH2.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah2_reg_t hri_slcd_read_SDATAH2_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->SDATAH2.reg;
+}
+
+static inline void hri_slcd_set_SDATAL3_SDATA_bf(const void *const hw, hri_slcd_sdatal3_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL3.reg |= SLCD_SDATAL3_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal3_reg_t hri_slcd_get_SDATAL3_SDATA_bf(const void *const hw, hri_slcd_sdatal3_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAL3.reg;
+	tmp = (tmp & SLCD_SDATAL3_SDATA(mask)) >> SLCD_SDATAL3_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAL3_SDATA_bf(const void *const hw, hri_slcd_sdatal3_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->SDATAL3.reg;
+	tmp &= ~SLCD_SDATAL3_SDATA_Msk;
+	tmp |= SLCD_SDATAL3_SDATA(data);
+	((Slcd *)hw)->SDATAL3.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAL3_SDATA_bf(const void *const hw, hri_slcd_sdatal3_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL3.reg &= ~SLCD_SDATAL3_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAL3_SDATA_bf(const void *const hw, hri_slcd_sdatal3_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL3.reg ^= SLCD_SDATAL3_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal3_reg_t hri_slcd_read_SDATAL3_SDATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAL3.reg;
+	tmp = (tmp & SLCD_SDATAL3_SDATA_Msk) >> SLCD_SDATAL3_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_SDATAL3_reg(const void *const hw, hri_slcd_sdatal3_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL3.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal3_reg_t hri_slcd_get_SDATAL3_reg(const void *const hw, hri_slcd_sdatal3_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAL3.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAL3_reg(const void *const hw, hri_slcd_sdatal3_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL3.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAL3_reg(const void *const hw, hri_slcd_sdatal3_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL3.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAL3_reg(const void *const hw, hri_slcd_sdatal3_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL3.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal3_reg_t hri_slcd_read_SDATAL3_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->SDATAL3.reg;
+}
+
+static inline void hri_slcd_set_SDATAH3_SDATA_bf(const void *const hw, hri_slcd_sdatah3_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH3.reg |= SLCD_SDATAH3_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah3_reg_t hri_slcd_get_SDATAH3_SDATA_bf(const void *const hw, hri_slcd_sdatah3_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAH3.reg;
+	tmp = (tmp & SLCD_SDATAH3_SDATA(mask)) >> SLCD_SDATAH3_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAH3_SDATA_bf(const void *const hw, hri_slcd_sdatah3_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->SDATAH3.reg;
+	tmp &= ~SLCD_SDATAH3_SDATA_Msk;
+	tmp |= SLCD_SDATAH3_SDATA(data);
+	((Slcd *)hw)->SDATAH3.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAH3_SDATA_bf(const void *const hw, hri_slcd_sdatah3_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH3.reg &= ~SLCD_SDATAH3_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAH3_SDATA_bf(const void *const hw, hri_slcd_sdatah3_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH3.reg ^= SLCD_SDATAH3_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah3_reg_t hri_slcd_read_SDATAH3_SDATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAH3.reg;
+	tmp = (tmp & SLCD_SDATAH3_SDATA_Msk) >> SLCD_SDATAH3_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_SDATAH3_reg(const void *const hw, hri_slcd_sdatah3_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH3.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah3_reg_t hri_slcd_get_SDATAH3_reg(const void *const hw, hri_slcd_sdatah3_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAH3.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAH3_reg(const void *const hw, hri_slcd_sdatah3_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH3.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAH3_reg(const void *const hw, hri_slcd_sdatah3_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH3.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAH3_reg(const void *const hw, hri_slcd_sdatah3_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH3.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah3_reg_t hri_slcd_read_SDATAH3_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->SDATAH3.reg;
+}
+
+static inline void hri_slcd_set_SDATAL4_SDATA_bf(const void *const hw, hri_slcd_sdatal4_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL4.reg |= SLCD_SDATAL4_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal4_reg_t hri_slcd_get_SDATAL4_SDATA_bf(const void *const hw, hri_slcd_sdatal4_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAL4.reg;
+	tmp = (tmp & SLCD_SDATAL4_SDATA(mask)) >> SLCD_SDATAL4_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAL4_SDATA_bf(const void *const hw, hri_slcd_sdatal4_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->SDATAL4.reg;
+	tmp &= ~SLCD_SDATAL4_SDATA_Msk;
+	tmp |= SLCD_SDATAL4_SDATA(data);
+	((Slcd *)hw)->SDATAL4.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAL4_SDATA_bf(const void *const hw, hri_slcd_sdatal4_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL4.reg &= ~SLCD_SDATAL4_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAL4_SDATA_bf(const void *const hw, hri_slcd_sdatal4_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL4.reg ^= SLCD_SDATAL4_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal4_reg_t hri_slcd_read_SDATAL4_SDATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAL4.reg;
+	tmp = (tmp & SLCD_SDATAL4_SDATA_Msk) >> SLCD_SDATAL4_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_SDATAL4_reg(const void *const hw, hri_slcd_sdatal4_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL4.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal4_reg_t hri_slcd_get_SDATAL4_reg(const void *const hw, hri_slcd_sdatal4_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAL4.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAL4_reg(const void *const hw, hri_slcd_sdatal4_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL4.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAL4_reg(const void *const hw, hri_slcd_sdatal4_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL4.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAL4_reg(const void *const hw, hri_slcd_sdatal4_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL4.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal4_reg_t hri_slcd_read_SDATAL4_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->SDATAL4.reg;
+}
+
+static inline void hri_slcd_set_SDATAH4_SDATA_bf(const void *const hw, hri_slcd_sdatah4_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH4.reg |= SLCD_SDATAH4_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah4_reg_t hri_slcd_get_SDATAH4_SDATA_bf(const void *const hw, hri_slcd_sdatah4_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAH4.reg;
+	tmp = (tmp & SLCD_SDATAH4_SDATA(mask)) >> SLCD_SDATAH4_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAH4_SDATA_bf(const void *const hw, hri_slcd_sdatah4_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->SDATAH4.reg;
+	tmp &= ~SLCD_SDATAH4_SDATA_Msk;
+	tmp |= SLCD_SDATAH4_SDATA(data);
+	((Slcd *)hw)->SDATAH4.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAH4_SDATA_bf(const void *const hw, hri_slcd_sdatah4_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH4.reg &= ~SLCD_SDATAH4_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAH4_SDATA_bf(const void *const hw, hri_slcd_sdatah4_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH4.reg ^= SLCD_SDATAH4_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah4_reg_t hri_slcd_read_SDATAH4_SDATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAH4.reg;
+	tmp = (tmp & SLCD_SDATAH4_SDATA_Msk) >> SLCD_SDATAH4_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_SDATAH4_reg(const void *const hw, hri_slcd_sdatah4_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH4.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah4_reg_t hri_slcd_get_SDATAH4_reg(const void *const hw, hri_slcd_sdatah4_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAH4.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAH4_reg(const void *const hw, hri_slcd_sdatah4_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH4.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAH4_reg(const void *const hw, hri_slcd_sdatah4_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH4.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAH4_reg(const void *const hw, hri_slcd_sdatah4_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH4.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah4_reg_t hri_slcd_read_SDATAH4_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->SDATAH4.reg;
+}
+
+static inline void hri_slcd_set_SDATAL5_SDATA_bf(const void *const hw, hri_slcd_sdatal5_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL5.reg |= SLCD_SDATAL5_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal5_reg_t hri_slcd_get_SDATAL5_SDATA_bf(const void *const hw, hri_slcd_sdatal5_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAL5.reg;
+	tmp = (tmp & SLCD_SDATAL5_SDATA(mask)) >> SLCD_SDATAL5_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAL5_SDATA_bf(const void *const hw, hri_slcd_sdatal5_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->SDATAL5.reg;
+	tmp &= ~SLCD_SDATAL5_SDATA_Msk;
+	tmp |= SLCD_SDATAL5_SDATA(data);
+	((Slcd *)hw)->SDATAL5.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAL5_SDATA_bf(const void *const hw, hri_slcd_sdatal5_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL5.reg &= ~SLCD_SDATAL5_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAL5_SDATA_bf(const void *const hw, hri_slcd_sdatal5_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL5.reg ^= SLCD_SDATAL5_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal5_reg_t hri_slcd_read_SDATAL5_SDATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAL5.reg;
+	tmp = (tmp & SLCD_SDATAL5_SDATA_Msk) >> SLCD_SDATAL5_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_SDATAL5_reg(const void *const hw, hri_slcd_sdatal5_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL5.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal5_reg_t hri_slcd_get_SDATAL5_reg(const void *const hw, hri_slcd_sdatal5_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAL5.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAL5_reg(const void *const hw, hri_slcd_sdatal5_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL5.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAL5_reg(const void *const hw, hri_slcd_sdatal5_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL5.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAL5_reg(const void *const hw, hri_slcd_sdatal5_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL5.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal5_reg_t hri_slcd_read_SDATAL5_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->SDATAL5.reg;
+}
+
+static inline void hri_slcd_set_SDATAH5_SDATA_bf(const void *const hw, hri_slcd_sdatah5_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH5.reg |= SLCD_SDATAH5_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah5_reg_t hri_slcd_get_SDATAH5_SDATA_bf(const void *const hw, hri_slcd_sdatah5_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAH5.reg;
+	tmp = (tmp & SLCD_SDATAH5_SDATA(mask)) >> SLCD_SDATAH5_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAH5_SDATA_bf(const void *const hw, hri_slcd_sdatah5_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->SDATAH5.reg;
+	tmp &= ~SLCD_SDATAH5_SDATA_Msk;
+	tmp |= SLCD_SDATAH5_SDATA(data);
+	((Slcd *)hw)->SDATAH5.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAH5_SDATA_bf(const void *const hw, hri_slcd_sdatah5_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH5.reg &= ~SLCD_SDATAH5_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAH5_SDATA_bf(const void *const hw, hri_slcd_sdatah5_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH5.reg ^= SLCD_SDATAH5_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah5_reg_t hri_slcd_read_SDATAH5_SDATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAH5.reg;
+	tmp = (tmp & SLCD_SDATAH5_SDATA_Msk) >> SLCD_SDATAH5_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_SDATAH5_reg(const void *const hw, hri_slcd_sdatah5_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH5.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah5_reg_t hri_slcd_get_SDATAH5_reg(const void *const hw, hri_slcd_sdatah5_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAH5.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAH5_reg(const void *const hw, hri_slcd_sdatah5_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH5.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAH5_reg(const void *const hw, hri_slcd_sdatah5_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH5.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAH5_reg(const void *const hw, hri_slcd_sdatah5_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH5.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah5_reg_t hri_slcd_read_SDATAH5_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->SDATAH5.reg;
+}
+
+static inline void hri_slcd_set_SDATAL6_SDATA_bf(const void *const hw, hri_slcd_sdatal6_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL6.reg |= SLCD_SDATAL6_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal6_reg_t hri_slcd_get_SDATAL6_SDATA_bf(const void *const hw, hri_slcd_sdatal6_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAL6.reg;
+	tmp = (tmp & SLCD_SDATAL6_SDATA(mask)) >> SLCD_SDATAL6_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAL6_SDATA_bf(const void *const hw, hri_slcd_sdatal6_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->SDATAL6.reg;
+	tmp &= ~SLCD_SDATAL6_SDATA_Msk;
+	tmp |= SLCD_SDATAL6_SDATA(data);
+	((Slcd *)hw)->SDATAL6.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAL6_SDATA_bf(const void *const hw, hri_slcd_sdatal6_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL6.reg &= ~SLCD_SDATAL6_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAL6_SDATA_bf(const void *const hw, hri_slcd_sdatal6_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL6.reg ^= SLCD_SDATAL6_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal6_reg_t hri_slcd_read_SDATAL6_SDATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAL6.reg;
+	tmp = (tmp & SLCD_SDATAL6_SDATA_Msk) >> SLCD_SDATAL6_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_SDATAL6_reg(const void *const hw, hri_slcd_sdatal6_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL6.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal6_reg_t hri_slcd_get_SDATAL6_reg(const void *const hw, hri_slcd_sdatal6_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAL6.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAL6_reg(const void *const hw, hri_slcd_sdatal6_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL6.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAL6_reg(const void *const hw, hri_slcd_sdatal6_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL6.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAL6_reg(const void *const hw, hri_slcd_sdatal6_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL6.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal6_reg_t hri_slcd_read_SDATAL6_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->SDATAL6.reg;
+}
+
+static inline void hri_slcd_set_SDATAH6_SDATA_bf(const void *const hw, hri_slcd_sdatah6_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH6.reg |= SLCD_SDATAH6_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah6_reg_t hri_slcd_get_SDATAH6_SDATA_bf(const void *const hw, hri_slcd_sdatah6_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAH6.reg;
+	tmp = (tmp & SLCD_SDATAH6_SDATA(mask)) >> SLCD_SDATAH6_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAH6_SDATA_bf(const void *const hw, hri_slcd_sdatah6_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->SDATAH6.reg;
+	tmp &= ~SLCD_SDATAH6_SDATA_Msk;
+	tmp |= SLCD_SDATAH6_SDATA(data);
+	((Slcd *)hw)->SDATAH6.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAH6_SDATA_bf(const void *const hw, hri_slcd_sdatah6_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH6.reg &= ~SLCD_SDATAH6_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAH6_SDATA_bf(const void *const hw, hri_slcd_sdatah6_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH6.reg ^= SLCD_SDATAH6_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah6_reg_t hri_slcd_read_SDATAH6_SDATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAH6.reg;
+	tmp = (tmp & SLCD_SDATAH6_SDATA_Msk) >> SLCD_SDATAH6_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_SDATAH6_reg(const void *const hw, hri_slcd_sdatah6_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH6.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah6_reg_t hri_slcd_get_SDATAH6_reg(const void *const hw, hri_slcd_sdatah6_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAH6.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAH6_reg(const void *const hw, hri_slcd_sdatah6_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH6.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAH6_reg(const void *const hw, hri_slcd_sdatah6_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH6.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAH6_reg(const void *const hw, hri_slcd_sdatah6_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH6.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah6_reg_t hri_slcd_read_SDATAH6_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->SDATAH6.reg;
+}
+
+static inline void hri_slcd_set_SDATAL7_SDATA_bf(const void *const hw, hri_slcd_sdatal7_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL7.reg |= SLCD_SDATAL7_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal7_reg_t hri_slcd_get_SDATAL7_SDATA_bf(const void *const hw, hri_slcd_sdatal7_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAL7.reg;
+	tmp = (tmp & SLCD_SDATAL7_SDATA(mask)) >> SLCD_SDATAL7_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAL7_SDATA_bf(const void *const hw, hri_slcd_sdatal7_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->SDATAL7.reg;
+	tmp &= ~SLCD_SDATAL7_SDATA_Msk;
+	tmp |= SLCD_SDATAL7_SDATA(data);
+	((Slcd *)hw)->SDATAL7.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAL7_SDATA_bf(const void *const hw, hri_slcd_sdatal7_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL7.reg &= ~SLCD_SDATAL7_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAL7_SDATA_bf(const void *const hw, hri_slcd_sdatal7_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL7.reg ^= SLCD_SDATAL7_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal7_reg_t hri_slcd_read_SDATAL7_SDATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAL7.reg;
+	tmp = (tmp & SLCD_SDATAL7_SDATA_Msk) >> SLCD_SDATAL7_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_SDATAL7_reg(const void *const hw, hri_slcd_sdatal7_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL7.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal7_reg_t hri_slcd_get_SDATAL7_reg(const void *const hw, hri_slcd_sdatal7_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAL7.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAL7_reg(const void *const hw, hri_slcd_sdatal7_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL7.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAL7_reg(const void *const hw, hri_slcd_sdatal7_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL7.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAL7_reg(const void *const hw, hri_slcd_sdatal7_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAL7.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatal7_reg_t hri_slcd_read_SDATAL7_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->SDATAL7.reg;
+}
+
+static inline void hri_slcd_set_SDATAH7_SDATA_bf(const void *const hw, hri_slcd_sdatah7_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH7.reg |= SLCD_SDATAH7_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah7_reg_t hri_slcd_get_SDATAH7_SDATA_bf(const void *const hw, hri_slcd_sdatah7_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAH7.reg;
+	tmp = (tmp & SLCD_SDATAH7_SDATA(mask)) >> SLCD_SDATAH7_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAH7_SDATA_bf(const void *const hw, hri_slcd_sdatah7_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->SDATAH7.reg;
+	tmp &= ~SLCD_SDATAH7_SDATA_Msk;
+	tmp |= SLCD_SDATAH7_SDATA(data);
+	((Slcd *)hw)->SDATAH7.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAH7_SDATA_bf(const void *const hw, hri_slcd_sdatah7_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH7.reg &= ~SLCD_SDATAH7_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAH7_SDATA_bf(const void *const hw, hri_slcd_sdatah7_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH7.reg ^= SLCD_SDATAH7_SDATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah7_reg_t hri_slcd_read_SDATAH7_SDATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAH7.reg;
+	tmp = (tmp & SLCD_SDATAH7_SDATA_Msk) >> SLCD_SDATAH7_SDATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_SDATAH7_reg(const void *const hw, hri_slcd_sdatah7_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH7.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah7_reg_t hri_slcd_get_SDATAH7_reg(const void *const hw, hri_slcd_sdatah7_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->SDATAH7.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_SDATAH7_reg(const void *const hw, hri_slcd_sdatah7_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH7.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_SDATAH7_reg(const void *const hw, hri_slcd_sdatah7_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH7.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_SDATAH7_reg(const void *const hw, hri_slcd_sdatah7_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->SDATAH7.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_sdatah7_reg_t hri_slcd_read_SDATAH7_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->SDATAH7.reg;
+}
+
+static inline void hri_slcd_set_BCFG_MODE_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->BCFG.reg |= SLCD_BCFG_MODE;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_BCFG_MODE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->BCFG.reg;
+	tmp = (tmp & SLCD_BCFG_MODE) >> SLCD_BCFG_MODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_write_BCFG_MODE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->BCFG.reg;
+	tmp &= ~SLCD_BCFG_MODE;
+	tmp |= value << SLCD_BCFG_MODE_Pos;
+	((Slcd *)hw)->BCFG.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_BCFG_MODE_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->BCFG.reg &= ~SLCD_BCFG_MODE;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_BCFG_MODE_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->BCFG.reg ^= SLCD_BCFG_MODE;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_set_BCFG_FCS_bf(const void *const hw, hri_slcd_bcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->BCFG.reg |= SLCD_BCFG_FCS(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_bcfg_reg_t hri_slcd_get_BCFG_FCS_bf(const void *const hw, hri_slcd_bcfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->BCFG.reg;
+	tmp = (tmp & SLCD_BCFG_FCS(mask)) >> SLCD_BCFG_FCS_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_BCFG_FCS_bf(const void *const hw, hri_slcd_bcfg_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->BCFG.reg;
+	tmp &= ~SLCD_BCFG_FCS_Msk;
+	tmp |= SLCD_BCFG_FCS(data);
+	((Slcd *)hw)->BCFG.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_BCFG_FCS_bf(const void *const hw, hri_slcd_bcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->BCFG.reg &= ~SLCD_BCFG_FCS(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_BCFG_FCS_bf(const void *const hw, hri_slcd_bcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->BCFG.reg ^= SLCD_BCFG_FCS(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_bcfg_reg_t hri_slcd_read_BCFG_FCS_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->BCFG.reg;
+	tmp = (tmp & SLCD_BCFG_FCS_Msk) >> SLCD_BCFG_FCS_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_BCFG_BSS0_bf(const void *const hw, hri_slcd_bcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->BCFG.reg |= SLCD_BCFG_BSS0(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_bcfg_reg_t hri_slcd_get_BCFG_BSS0_bf(const void *const hw, hri_slcd_bcfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->BCFG.reg;
+	tmp = (tmp & SLCD_BCFG_BSS0(mask)) >> SLCD_BCFG_BSS0_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_BCFG_BSS0_bf(const void *const hw, hri_slcd_bcfg_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->BCFG.reg;
+	tmp &= ~SLCD_BCFG_BSS0_Msk;
+	tmp |= SLCD_BCFG_BSS0(data);
+	((Slcd *)hw)->BCFG.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_BCFG_BSS0_bf(const void *const hw, hri_slcd_bcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->BCFG.reg &= ~SLCD_BCFG_BSS0(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_BCFG_BSS0_bf(const void *const hw, hri_slcd_bcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->BCFG.reg ^= SLCD_BCFG_BSS0(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_bcfg_reg_t hri_slcd_read_BCFG_BSS0_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->BCFG.reg;
+	tmp = (tmp & SLCD_BCFG_BSS0_Msk) >> SLCD_BCFG_BSS0_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_BCFG_BSS1_bf(const void *const hw, hri_slcd_bcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->BCFG.reg |= SLCD_BCFG_BSS1(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_bcfg_reg_t hri_slcd_get_BCFG_BSS1_bf(const void *const hw, hri_slcd_bcfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->BCFG.reg;
+	tmp = (tmp & SLCD_BCFG_BSS1(mask)) >> SLCD_BCFG_BSS1_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_BCFG_BSS1_bf(const void *const hw, hri_slcd_bcfg_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->BCFG.reg;
+	tmp &= ~SLCD_BCFG_BSS1_Msk;
+	tmp |= SLCD_BCFG_BSS1(data);
+	((Slcd *)hw)->BCFG.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_BCFG_BSS1_bf(const void *const hw, hri_slcd_bcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->BCFG.reg &= ~SLCD_BCFG_BSS1(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_BCFG_BSS1_bf(const void *const hw, hri_slcd_bcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->BCFG.reg ^= SLCD_BCFG_BSS1(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_bcfg_reg_t hri_slcd_read_BCFG_BSS1_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->BCFG.reg;
+	tmp = (tmp & SLCD_BCFG_BSS1_Msk) >> SLCD_BCFG_BSS1_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_BCFG_reg(const void *const hw, hri_slcd_bcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->BCFG.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_bcfg_reg_t hri_slcd_get_BCFG_reg(const void *const hw, hri_slcd_bcfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->BCFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_BCFG_reg(const void *const hw, hri_slcd_bcfg_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->BCFG.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_BCFG_reg(const void *const hw, hri_slcd_bcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->BCFG.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_BCFG_reg(const void *const hw, hri_slcd_bcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->BCFG.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_bcfg_reg_t hri_slcd_read_BCFG_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->BCFG.reg;
+}
+
+static inline void hri_slcd_set_CSRCFG_DIR_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CSRCFG.reg |= SLCD_CSRCFG_DIR;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_CSRCFG_DIR_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CSRCFG.reg;
+	tmp = (tmp & SLCD_CSRCFG_DIR) >> SLCD_CSRCFG_DIR_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_write_CSRCFG_DIR_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CSRCFG.reg;
+	tmp &= ~SLCD_CSRCFG_DIR;
+	tmp |= value << SLCD_CSRCFG_DIR_Pos;
+	((Slcd *)hw)->CSRCFG.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CSRCFG_DIR_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CSRCFG.reg &= ~SLCD_CSRCFG_DIR;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CSRCFG_DIR_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CSRCFG.reg ^= SLCD_CSRCFG_DIR;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_set_CSRCFG_FCS_bf(const void *const hw, hri_slcd_csrcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CSRCFG.reg |= SLCD_CSRCFG_FCS(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_csrcfg_reg_t hri_slcd_get_CSRCFG_FCS_bf(const void *const hw, hri_slcd_csrcfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CSRCFG.reg;
+	tmp = (tmp & SLCD_CSRCFG_FCS(mask)) >> SLCD_CSRCFG_FCS_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_CSRCFG_FCS_bf(const void *const hw, hri_slcd_csrcfg_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CSRCFG.reg;
+	tmp &= ~SLCD_CSRCFG_FCS_Msk;
+	tmp |= SLCD_CSRCFG_FCS(data);
+	((Slcd *)hw)->CSRCFG.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CSRCFG_FCS_bf(const void *const hw, hri_slcd_csrcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CSRCFG.reg &= ~SLCD_CSRCFG_FCS(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CSRCFG_FCS_bf(const void *const hw, hri_slcd_csrcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CSRCFG.reg ^= SLCD_CSRCFG_FCS(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_csrcfg_reg_t hri_slcd_read_CSRCFG_FCS_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CSRCFG.reg;
+	tmp = (tmp & SLCD_CSRCFG_FCS_Msk) >> SLCD_CSRCFG_FCS_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_CSRCFG_SIZE_bf(const void *const hw, hri_slcd_csrcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CSRCFG.reg |= SLCD_CSRCFG_SIZE(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_csrcfg_reg_t hri_slcd_get_CSRCFG_SIZE_bf(const void *const hw, hri_slcd_csrcfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CSRCFG.reg;
+	tmp = (tmp & SLCD_CSRCFG_SIZE(mask)) >> SLCD_CSRCFG_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_CSRCFG_SIZE_bf(const void *const hw, hri_slcd_csrcfg_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CSRCFG.reg;
+	tmp &= ~SLCD_CSRCFG_SIZE_Msk;
+	tmp |= SLCD_CSRCFG_SIZE(data);
+	((Slcd *)hw)->CSRCFG.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CSRCFG_SIZE_bf(const void *const hw, hri_slcd_csrcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CSRCFG.reg &= ~SLCD_CSRCFG_SIZE(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CSRCFG_SIZE_bf(const void *const hw, hri_slcd_csrcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CSRCFG.reg ^= SLCD_CSRCFG_SIZE(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_csrcfg_reg_t hri_slcd_read_CSRCFG_SIZE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CSRCFG.reg;
+	tmp = (tmp & SLCD_CSRCFG_SIZE_Msk) >> SLCD_CSRCFG_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_CSRCFG_DATA_bf(const void *const hw, hri_slcd_csrcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CSRCFG.reg |= SLCD_CSRCFG_DATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_csrcfg_reg_t hri_slcd_get_CSRCFG_DATA_bf(const void *const hw, hri_slcd_csrcfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CSRCFG.reg;
+	tmp = (tmp & SLCD_CSRCFG_DATA(mask)) >> SLCD_CSRCFG_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_CSRCFG_DATA_bf(const void *const hw, hri_slcd_csrcfg_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CSRCFG.reg;
+	tmp &= ~SLCD_CSRCFG_DATA_Msk;
+	tmp |= SLCD_CSRCFG_DATA(data);
+	((Slcd *)hw)->CSRCFG.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CSRCFG_DATA_bf(const void *const hw, hri_slcd_csrcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CSRCFG.reg &= ~SLCD_CSRCFG_DATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CSRCFG_DATA_bf(const void *const hw, hri_slcd_csrcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CSRCFG.reg ^= SLCD_CSRCFG_DATA(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_csrcfg_reg_t hri_slcd_read_CSRCFG_DATA_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CSRCFG.reg;
+	tmp = (tmp & SLCD_CSRCFG_DATA_Msk) >> SLCD_CSRCFG_DATA_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_CSRCFG_reg(const void *const hw, hri_slcd_csrcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CSRCFG.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_csrcfg_reg_t hri_slcd_get_CSRCFG_reg(const void *const hw, hri_slcd_csrcfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CSRCFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_CSRCFG_reg(const void *const hw, hri_slcd_csrcfg_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CSRCFG.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CSRCFG_reg(const void *const hw, hri_slcd_csrcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CSRCFG.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CSRCFG_reg(const void *const hw, hri_slcd_csrcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CSRCFG.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_csrcfg_reg_t hri_slcd_read_CSRCFG_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->CSRCFG.reg;
+}
+
+static inline void hri_slcd_set_CMCFG_DEC_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMCFG.reg |= SLCD_CMCFG_DEC;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_CMCFG_DEC_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->CMCFG.reg;
+	tmp = (tmp & SLCD_CMCFG_DEC) >> SLCD_CMCFG_DEC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_write_CMCFG_DEC_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CMCFG.reg;
+	tmp &= ~SLCD_CMCFG_DEC;
+	tmp |= value << SLCD_CMCFG_DEC_Pos;
+	((Slcd *)hw)->CMCFG.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CMCFG_DEC_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMCFG.reg &= ~SLCD_CMCFG_DEC;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CMCFG_DEC_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMCFG.reg ^= SLCD_CMCFG_DEC;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_set_CMCFG_NSEG_bf(const void *const hw, hri_slcd_cmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMCFG.reg |= SLCD_CMCFG_NSEG(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_cmcfg_reg_t hri_slcd_get_CMCFG_NSEG_bf(const void *const hw, hri_slcd_cmcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->CMCFG.reg;
+	tmp = (tmp & SLCD_CMCFG_NSEG(mask)) >> SLCD_CMCFG_NSEG_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_CMCFG_NSEG_bf(const void *const hw, hri_slcd_cmcfg_reg_t data)
+{
+	uint8_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CMCFG.reg;
+	tmp &= ~SLCD_CMCFG_NSEG_Msk;
+	tmp |= SLCD_CMCFG_NSEG(data);
+	((Slcd *)hw)->CMCFG.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CMCFG_NSEG_bf(const void *const hw, hri_slcd_cmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMCFG.reg &= ~SLCD_CMCFG_NSEG(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CMCFG_NSEG_bf(const void *const hw, hri_slcd_cmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMCFG.reg ^= SLCD_CMCFG_NSEG(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_cmcfg_reg_t hri_slcd_read_CMCFG_NSEG_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->CMCFG.reg;
+	tmp = (tmp & SLCD_CMCFG_NSEG_Msk) >> SLCD_CMCFG_NSEG_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_CMCFG_reg(const void *const hw, hri_slcd_cmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMCFG.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_cmcfg_reg_t hri_slcd_get_CMCFG_reg(const void *const hw, hri_slcd_cmcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->CMCFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_CMCFG_reg(const void *const hw, hri_slcd_cmcfg_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMCFG.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CMCFG_reg(const void *const hw, hri_slcd_cmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMCFG.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CMCFG_reg(const void *const hw, hri_slcd_cmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMCFG.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_cmcfg_reg_t hri_slcd_read_CMCFG_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->CMCFG.reg;
+}
+
+static inline void hri_slcd_set_ACMCFG_MODE_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ACMCFG.reg |= SLCD_ACMCFG_MODE;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_slcd_get_ACMCFG_MODE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->ACMCFG.reg;
+	tmp = (tmp & SLCD_ACMCFG_MODE) >> SLCD_ACMCFG_MODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_slcd_write_ACMCFG_MODE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->ACMCFG.reg;
+	tmp &= ~SLCD_ACMCFG_MODE;
+	tmp |= value << SLCD_ACMCFG_MODE_Pos;
+	((Slcd *)hw)->ACMCFG.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_ACMCFG_MODE_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ACMCFG.reg &= ~SLCD_ACMCFG_MODE;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_ACMCFG_MODE_bit(const void *const hw)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ACMCFG.reg ^= SLCD_ACMCFG_MODE;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_set_ACMCFG_NCOM_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ACMCFG.reg |= SLCD_ACMCFG_NCOM(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_acmcfg_reg_t hri_slcd_get_ACMCFG_NCOM_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->ACMCFG.reg;
+	tmp = (tmp & SLCD_ACMCFG_NCOM(mask)) >> SLCD_ACMCFG_NCOM_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_ACMCFG_NCOM_bf(const void *const hw, hri_slcd_acmcfg_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->ACMCFG.reg;
+	tmp &= ~SLCD_ACMCFG_NCOM_Msk;
+	tmp |= SLCD_ACMCFG_NCOM(data);
+	((Slcd *)hw)->ACMCFG.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_ACMCFG_NCOM_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ACMCFG.reg &= ~SLCD_ACMCFG_NCOM(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_ACMCFG_NCOM_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ACMCFG.reg ^= SLCD_ACMCFG_NCOM(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_acmcfg_reg_t hri_slcd_read_ACMCFG_NCOM_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->ACMCFG.reg;
+	tmp = (tmp & SLCD_ACMCFG_NCOM_Msk) >> SLCD_ACMCFG_NCOM_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_ACMCFG_NDIG_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ACMCFG.reg |= SLCD_ACMCFG_NDIG(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_acmcfg_reg_t hri_slcd_get_ACMCFG_NDIG_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->ACMCFG.reg;
+	tmp = (tmp & SLCD_ACMCFG_NDIG(mask)) >> SLCD_ACMCFG_NDIG_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_ACMCFG_NDIG_bf(const void *const hw, hri_slcd_acmcfg_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->ACMCFG.reg;
+	tmp &= ~SLCD_ACMCFG_NDIG_Msk;
+	tmp |= SLCD_ACMCFG_NDIG(data);
+	((Slcd *)hw)->ACMCFG.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_ACMCFG_NDIG_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ACMCFG.reg &= ~SLCD_ACMCFG_NDIG(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_ACMCFG_NDIG_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ACMCFG.reg ^= SLCD_ACMCFG_NDIG(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_acmcfg_reg_t hri_slcd_read_ACMCFG_NDIG_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->ACMCFG.reg;
+	tmp = (tmp & SLCD_ACMCFG_NDIG_Msk) >> SLCD_ACMCFG_NDIG_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_ACMCFG_STEPS_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ACMCFG.reg |= SLCD_ACMCFG_STEPS(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_acmcfg_reg_t hri_slcd_get_ACMCFG_STEPS_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->ACMCFG.reg;
+	tmp = (tmp & SLCD_ACMCFG_STEPS(mask)) >> SLCD_ACMCFG_STEPS_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_ACMCFG_STEPS_bf(const void *const hw, hri_slcd_acmcfg_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->ACMCFG.reg;
+	tmp &= ~SLCD_ACMCFG_STEPS_Msk;
+	tmp |= SLCD_ACMCFG_STEPS(data);
+	((Slcd *)hw)->ACMCFG.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_ACMCFG_STEPS_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ACMCFG.reg &= ~SLCD_ACMCFG_STEPS(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_ACMCFG_STEPS_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ACMCFG.reg ^= SLCD_ACMCFG_STEPS(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_acmcfg_reg_t hri_slcd_read_ACMCFG_STEPS_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->ACMCFG.reg;
+	tmp = (tmp & SLCD_ACMCFG_STEPS_Msk) >> SLCD_ACMCFG_STEPS_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_ACMCFG_NDROW_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ACMCFG.reg |= SLCD_ACMCFG_NDROW(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_acmcfg_reg_t hri_slcd_get_ACMCFG_NDROW_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->ACMCFG.reg;
+	tmp = (tmp & SLCD_ACMCFG_NDROW(mask)) >> SLCD_ACMCFG_NDROW_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_ACMCFG_NDROW_bf(const void *const hw, hri_slcd_acmcfg_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->ACMCFG.reg;
+	tmp &= ~SLCD_ACMCFG_NDROW_Msk;
+	tmp |= SLCD_ACMCFG_NDROW(data);
+	((Slcd *)hw)->ACMCFG.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_ACMCFG_NDROW_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ACMCFG.reg &= ~SLCD_ACMCFG_NDROW(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_ACMCFG_NDROW_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ACMCFG.reg ^= SLCD_ACMCFG_NDROW(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_acmcfg_reg_t hri_slcd_read_ACMCFG_NDROW_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->ACMCFG.reg;
+	tmp = (tmp & SLCD_ACMCFG_NDROW_Msk) >> SLCD_ACMCFG_NDROW_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_ACMCFG_STSEG_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ACMCFG.reg |= SLCD_ACMCFG_STSEG(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_acmcfg_reg_t hri_slcd_get_ACMCFG_STSEG_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->ACMCFG.reg;
+	tmp = (tmp & SLCD_ACMCFG_STSEG(mask)) >> SLCD_ACMCFG_STSEG_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_ACMCFG_STSEG_bf(const void *const hw, hri_slcd_acmcfg_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->ACMCFG.reg;
+	tmp &= ~SLCD_ACMCFG_STSEG_Msk;
+	tmp |= SLCD_ACMCFG_STSEG(data);
+	((Slcd *)hw)->ACMCFG.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_ACMCFG_STSEG_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ACMCFG.reg &= ~SLCD_ACMCFG_STSEG(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_ACMCFG_STSEG_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ACMCFG.reg ^= SLCD_ACMCFG_STSEG(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_acmcfg_reg_t hri_slcd_read_ACMCFG_STSEG_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->ACMCFG.reg;
+	tmp = (tmp & SLCD_ACMCFG_STSEG_Msk) >> SLCD_ACMCFG_STSEG_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_ACMCFG_FCS_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ACMCFG.reg |= SLCD_ACMCFG_FCS(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_acmcfg_reg_t hri_slcd_get_ACMCFG_FCS_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->ACMCFG.reg;
+	tmp = (tmp & SLCD_ACMCFG_FCS(mask)) >> SLCD_ACMCFG_FCS_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_ACMCFG_FCS_bf(const void *const hw, hri_slcd_acmcfg_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->ACMCFG.reg;
+	tmp &= ~SLCD_ACMCFG_FCS_Msk;
+	tmp |= SLCD_ACMCFG_FCS(data);
+	((Slcd *)hw)->ACMCFG.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_ACMCFG_FCS_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ACMCFG.reg &= ~SLCD_ACMCFG_FCS(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_ACMCFG_FCS_bf(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ACMCFG.reg ^= SLCD_ACMCFG_FCS(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_acmcfg_reg_t hri_slcd_read_ACMCFG_FCS_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->ACMCFG.reg;
+	tmp = (tmp & SLCD_ACMCFG_FCS_Msk) >> SLCD_ACMCFG_FCS_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_ACMCFG_reg(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ACMCFG.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_acmcfg_reg_t hri_slcd_get_ACMCFG_reg(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->ACMCFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_ACMCFG_reg(const void *const hw, hri_slcd_acmcfg_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ACMCFG.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_ACMCFG_reg(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ACMCFG.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_ACMCFG_reg(const void *const hw, hri_slcd_acmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ACMCFG.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_acmcfg_reg_t hri_slcd_read_ACMCFG_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->ACMCFG.reg;
+}
+
+static inline void hri_slcd_set_ABMCFG_FCS_bf(const void *const hw, hri_slcd_abmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ABMCFG.reg |= SLCD_ABMCFG_FCS(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_abmcfg_reg_t hri_slcd_get_ABMCFG_FCS_bf(const void *const hw, hri_slcd_abmcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->ABMCFG.reg;
+	tmp = (tmp & SLCD_ABMCFG_FCS(mask)) >> SLCD_ABMCFG_FCS_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_ABMCFG_FCS_bf(const void *const hw, hri_slcd_abmcfg_reg_t data)
+{
+	uint8_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->ABMCFG.reg;
+	tmp &= ~SLCD_ABMCFG_FCS_Msk;
+	tmp |= SLCD_ABMCFG_FCS(data);
+	((Slcd *)hw)->ABMCFG.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_ABMCFG_FCS_bf(const void *const hw, hri_slcd_abmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ABMCFG.reg &= ~SLCD_ABMCFG_FCS(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_ABMCFG_FCS_bf(const void *const hw, hri_slcd_abmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ABMCFG.reg ^= SLCD_ABMCFG_FCS(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_abmcfg_reg_t hri_slcd_read_ABMCFG_FCS_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->ABMCFG.reg;
+	tmp = (tmp & SLCD_ABMCFG_FCS_Msk) >> SLCD_ABMCFG_FCS_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_ABMCFG_SIZE_bf(const void *const hw, hri_slcd_abmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ABMCFG.reg |= SLCD_ABMCFG_SIZE(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_abmcfg_reg_t hri_slcd_get_ABMCFG_SIZE_bf(const void *const hw, hri_slcd_abmcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->ABMCFG.reg;
+	tmp = (tmp & SLCD_ABMCFG_SIZE(mask)) >> SLCD_ABMCFG_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_ABMCFG_SIZE_bf(const void *const hw, hri_slcd_abmcfg_reg_t data)
+{
+	uint8_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->ABMCFG.reg;
+	tmp &= ~SLCD_ABMCFG_SIZE_Msk;
+	tmp |= SLCD_ABMCFG_SIZE(data);
+	((Slcd *)hw)->ABMCFG.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_ABMCFG_SIZE_bf(const void *const hw, hri_slcd_abmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ABMCFG.reg &= ~SLCD_ABMCFG_SIZE(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_ABMCFG_SIZE_bf(const void *const hw, hri_slcd_abmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ABMCFG.reg ^= SLCD_ABMCFG_SIZE(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_abmcfg_reg_t hri_slcd_read_ABMCFG_SIZE_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->ABMCFG.reg;
+	tmp = (tmp & SLCD_ABMCFG_SIZE_Msk) >> SLCD_ABMCFG_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_ABMCFG_reg(const void *const hw, hri_slcd_abmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ABMCFG.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_abmcfg_reg_t hri_slcd_get_ABMCFG_reg(const void *const hw, hri_slcd_abmcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Slcd *)hw)->ABMCFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_ABMCFG_reg(const void *const hw, hri_slcd_abmcfg_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ABMCFG.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_ABMCFG_reg(const void *const hw, hri_slcd_abmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ABMCFG.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_ABMCFG_reg(const void *const hw, hri_slcd_abmcfg_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ABMCFG.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_abmcfg_reg_t hri_slcd_read_ABMCFG_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->ABMCFG.reg;
+}
+
+static inline void hri_slcd_set_CMDMASK_SDMASK_bf(const void *const hw, hri_slcd_cmdmask_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMDMASK.reg |= SLCD_CMDMASK_SDMASK(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_cmdmask_reg_t hri_slcd_get_CMDMASK_SDMASK_bf(const void *const hw, hri_slcd_cmdmask_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CMDMASK.reg;
+	tmp = (tmp & SLCD_CMDMASK_SDMASK(mask)) >> SLCD_CMDMASK_SDMASK_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_CMDMASK_SDMASK_bf(const void *const hw, hri_slcd_cmdmask_reg_t data)
+{
+	uint32_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CMDMASK.reg;
+	tmp &= ~SLCD_CMDMASK_SDMASK_Msk;
+	tmp |= SLCD_CMDMASK_SDMASK(data);
+	((Slcd *)hw)->CMDMASK.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CMDMASK_SDMASK_bf(const void *const hw, hri_slcd_cmdmask_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMDMASK.reg &= ~SLCD_CMDMASK_SDMASK(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CMDMASK_SDMASK_bf(const void *const hw, hri_slcd_cmdmask_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMDMASK.reg ^= SLCD_CMDMASK_SDMASK(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_cmdmask_reg_t hri_slcd_read_CMDMASK_SDMASK_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CMDMASK.reg;
+	tmp = (tmp & SLCD_CMDMASK_SDMASK_Msk) >> SLCD_CMDMASK_SDMASK_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_CMDMASK_reg(const void *const hw, hri_slcd_cmdmask_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMDMASK.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_cmdmask_reg_t hri_slcd_get_CMDMASK_reg(const void *const hw, hri_slcd_cmdmask_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Slcd *)hw)->CMDMASK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_CMDMASK_reg(const void *const hw, hri_slcd_cmdmask_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMDMASK.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CMDMASK_reg(const void *const hw, hri_slcd_cmdmask_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMDMASK.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CMDMASK_reg(const void *const hw, hri_slcd_cmdmask_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMDMASK.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_cmdmask_reg_t hri_slcd_read_CMDMASK_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->CMDMASK.reg;
+}
+
+static inline void hri_slcd_set_CMINDEX_SINDEX_bf(const void *const hw, hri_slcd_cmindex_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMINDEX.reg |= SLCD_CMINDEX_SINDEX(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_cmindex_reg_t hri_slcd_get_CMINDEX_SINDEX_bf(const void *const hw, hri_slcd_cmindex_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Slcd *)hw)->CMINDEX.reg;
+	tmp = (tmp & SLCD_CMINDEX_SINDEX(mask)) >> SLCD_CMINDEX_SINDEX_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_CMINDEX_SINDEX_bf(const void *const hw, hri_slcd_cmindex_reg_t data)
+{
+	uint16_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CMINDEX.reg;
+	tmp &= ~SLCD_CMINDEX_SINDEX_Msk;
+	tmp |= SLCD_CMINDEX_SINDEX(data);
+	((Slcd *)hw)->CMINDEX.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CMINDEX_SINDEX_bf(const void *const hw, hri_slcd_cmindex_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMINDEX.reg &= ~SLCD_CMINDEX_SINDEX(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CMINDEX_SINDEX_bf(const void *const hw, hri_slcd_cmindex_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMINDEX.reg ^= SLCD_CMINDEX_SINDEX(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_cmindex_reg_t hri_slcd_read_CMINDEX_SINDEX_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Slcd *)hw)->CMINDEX.reg;
+	tmp = (tmp & SLCD_CMINDEX_SINDEX_Msk) >> SLCD_CMINDEX_SINDEX_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_CMINDEX_CINDEX_bf(const void *const hw, hri_slcd_cmindex_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMINDEX.reg |= SLCD_CMINDEX_CINDEX(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_cmindex_reg_t hri_slcd_get_CMINDEX_CINDEX_bf(const void *const hw, hri_slcd_cmindex_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Slcd *)hw)->CMINDEX.reg;
+	tmp = (tmp & SLCD_CMINDEX_CINDEX(mask)) >> SLCD_CMINDEX_CINDEX_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_write_CMINDEX_CINDEX_bf(const void *const hw, hri_slcd_cmindex_reg_t data)
+{
+	uint16_t tmp;
+	SLCD_CRITICAL_SECTION_ENTER();
+	tmp = ((Slcd *)hw)->CMINDEX.reg;
+	tmp &= ~SLCD_CMINDEX_CINDEX_Msk;
+	tmp |= SLCD_CMINDEX_CINDEX(data);
+	((Slcd *)hw)->CMINDEX.reg = tmp;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CMINDEX_CINDEX_bf(const void *const hw, hri_slcd_cmindex_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMINDEX.reg &= ~SLCD_CMINDEX_CINDEX(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CMINDEX_CINDEX_bf(const void *const hw, hri_slcd_cmindex_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMINDEX.reg ^= SLCD_CMINDEX_CINDEX(mask);
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_cmindex_reg_t hri_slcd_read_CMINDEX_CINDEX_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Slcd *)hw)->CMINDEX.reg;
+	tmp = (tmp & SLCD_CMINDEX_CINDEX_Msk) >> SLCD_CMINDEX_CINDEX_Pos;
+	return tmp;
+}
+
+static inline void hri_slcd_set_CMINDEX_reg(const void *const hw, hri_slcd_cmindex_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMINDEX.reg |= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_cmindex_reg_t hri_slcd_get_CMINDEX_reg(const void *const hw, hri_slcd_cmindex_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Slcd *)hw)->CMINDEX.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_slcd_write_CMINDEX_reg(const void *const hw, hri_slcd_cmindex_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMINDEX.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_clear_CMINDEX_reg(const void *const hw, hri_slcd_cmindex_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMINDEX.reg &= ~mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_toggle_CMINDEX_reg(const void *const hw, hri_slcd_cmindex_reg_t mask)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMINDEX.reg ^= mask;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_slcd_cmindex_reg_t hri_slcd_read_CMINDEX_reg(const void *const hw)
+{
+	return ((Slcd *)hw)->CMINDEX.reg;
+}
+
+static inline void hri_slcd_write_ISDATA_reg(const void *const hw, hri_slcd_isdata_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->ISDATA.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_slcd_write_CMDATA_reg(const void *const hw, hri_slcd_cmdata_reg_t data)
+{
+	SLCD_CRITICAL_SECTION_ENTER();
+	((Slcd *)hw)->CMDATA.reg = data;
+	SLCD_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_SLCD_L22_H_INCLUDED */
+#endif /* _SAML22_SLCD_COMPONENT_ */
diff --git a/watch-library/hardware/hri/hri_supc_l22.h b/watch-library/hardware/hri/hri_supc_l22.h
new file mode 100644
index 00000000..9488ef0b
--- /dev/null
+++ b/watch-library/hardware/hri/hri_supc_l22.h
@@ -0,0 +1,2532 @@
+/**
+ * \file
+ *
+ * \brief SAM SUPC
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_SUPC_COMPONENT_
+#ifndef _HRI_SUPC_L22_H_INCLUDED_
+#define _HRI_SUPC_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_SUPC_CRITICAL_SECTIONS)
+#define SUPC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define SUPC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define SUPC_CRITICAL_SECTION_ENTER()
+#define SUPC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_supc_bbps_reg_t;
+typedef uint32_t hri_supc_bkin_reg_t;
+typedef uint32_t hri_supc_bkout_reg_t;
+typedef uint32_t hri_supc_bod12_reg_t;
+typedef uint32_t hri_supc_bod33_reg_t;
+typedef uint32_t hri_supc_intenset_reg_t;
+typedef uint32_t hri_supc_intflag_reg_t;
+typedef uint32_t hri_supc_status_reg_t;
+typedef uint32_t hri_supc_vref_reg_t;
+typedef uint32_t hri_supc_vreg_reg_t;
+
+static inline bool hri_supc_get_INTFLAG_BOD33RDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33RDY) >> SUPC_INTFLAG_BOD33RDY_Pos;
+}
+
+static inline void hri_supc_clear_INTFLAG_BOD33RDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33RDY;
+}
+
+static inline bool hri_supc_get_INTFLAG_BOD33DET_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33DET) >> SUPC_INTFLAG_BOD33DET_Pos;
+}
+
+static inline void hri_supc_clear_INTFLAG_BOD33DET_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33DET;
+}
+
+static inline bool hri_supc_get_INTFLAG_B33SRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B33SRDY) >> SUPC_INTFLAG_B33SRDY_Pos;
+}
+
+static inline void hri_supc_clear_INTFLAG_B33SRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B33SRDY;
+}
+
+static inline bool hri_supc_get_INTFLAG_BOD12RDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD12RDY) >> SUPC_INTFLAG_BOD12RDY_Pos;
+}
+
+static inline void hri_supc_clear_INTFLAG_BOD12RDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD12RDY;
+}
+
+static inline bool hri_supc_get_INTFLAG_BOD12DET_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD12DET) >> SUPC_INTFLAG_BOD12DET_Pos;
+}
+
+static inline void hri_supc_clear_INTFLAG_BOD12DET_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD12DET;
+}
+
+static inline bool hri_supc_get_INTFLAG_B12SRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B12SRDY) >> SUPC_INTFLAG_B12SRDY_Pos;
+}
+
+static inline void hri_supc_clear_INTFLAG_B12SRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B12SRDY;
+}
+
+static inline bool hri_supc_get_INTFLAG_VREGRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VREGRDY) >> SUPC_INTFLAG_VREGRDY_Pos;
+}
+
+static inline void hri_supc_clear_INTFLAG_VREGRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VREGRDY;
+}
+
+static inline bool hri_supc_get_INTFLAG_APWSRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_APWSRDY) >> SUPC_INTFLAG_APWSRDY_Pos;
+}
+
+static inline void hri_supc_clear_INTFLAG_APWSRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_APWSRDY;
+}
+
+static inline bool hri_supc_get_INTFLAG_VCORERDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VCORERDY) >> SUPC_INTFLAG_VCORERDY_Pos;
+}
+
+static inline void hri_supc_clear_INTFLAG_VCORERDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VCORERDY;
+}
+
+static inline bool hri_supc_get_interrupt_BOD33RDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33RDY) >> SUPC_INTFLAG_BOD33RDY_Pos;
+}
+
+static inline void hri_supc_clear_interrupt_BOD33RDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33RDY;
+}
+
+static inline bool hri_supc_get_interrupt_BOD33DET_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33DET) >> SUPC_INTFLAG_BOD33DET_Pos;
+}
+
+static inline void hri_supc_clear_interrupt_BOD33DET_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33DET;
+}
+
+static inline bool hri_supc_get_interrupt_B33SRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B33SRDY) >> SUPC_INTFLAG_B33SRDY_Pos;
+}
+
+static inline void hri_supc_clear_interrupt_B33SRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B33SRDY;
+}
+
+static inline bool hri_supc_get_interrupt_BOD12RDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD12RDY) >> SUPC_INTFLAG_BOD12RDY_Pos;
+}
+
+static inline void hri_supc_clear_interrupt_BOD12RDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD12RDY;
+}
+
+static inline bool hri_supc_get_interrupt_BOD12DET_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD12DET) >> SUPC_INTFLAG_BOD12DET_Pos;
+}
+
+static inline void hri_supc_clear_interrupt_BOD12DET_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD12DET;
+}
+
+static inline bool hri_supc_get_interrupt_B12SRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B12SRDY) >> SUPC_INTFLAG_B12SRDY_Pos;
+}
+
+static inline void hri_supc_clear_interrupt_B12SRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B12SRDY;
+}
+
+static inline bool hri_supc_get_interrupt_VREGRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VREGRDY) >> SUPC_INTFLAG_VREGRDY_Pos;
+}
+
+static inline void hri_supc_clear_interrupt_VREGRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VREGRDY;
+}
+
+static inline bool hri_supc_get_interrupt_APWSRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_APWSRDY) >> SUPC_INTFLAG_APWSRDY_Pos;
+}
+
+static inline void hri_supc_clear_interrupt_APWSRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_APWSRDY;
+}
+
+static inline bool hri_supc_get_interrupt_VCORERDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VCORERDY) >> SUPC_INTFLAG_VCORERDY_Pos;
+}
+
+static inline void hri_supc_clear_interrupt_VCORERDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VCORERDY;
+}
+
+static inline hri_supc_intflag_reg_t hri_supc_get_INTFLAG_reg(const void *const hw, hri_supc_intflag_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_supc_intflag_reg_t hri_supc_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Supc *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_supc_clear_INTFLAG_reg(const void *const hw, hri_supc_intflag_reg_t mask)
+{
+	((Supc *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_supc_set_INTEN_BOD33RDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33RDY;
+}
+
+static inline bool hri_supc_get_INTEN_BOD33RDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD33RDY) >> SUPC_INTENSET_BOD33RDY_Pos;
+}
+
+static inline void hri_supc_write_INTEN_BOD33RDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33RDY;
+	} else {
+		((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33RDY;
+	}
+}
+
+static inline void hri_supc_clear_INTEN_BOD33RDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33RDY;
+}
+
+static inline void hri_supc_set_INTEN_BOD33DET_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33DET;
+}
+
+static inline bool hri_supc_get_INTEN_BOD33DET_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD33DET) >> SUPC_INTENSET_BOD33DET_Pos;
+}
+
+static inline void hri_supc_write_INTEN_BOD33DET_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33DET;
+	} else {
+		((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33DET;
+	}
+}
+
+static inline void hri_supc_clear_INTEN_BOD33DET_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33DET;
+}
+
+static inline void hri_supc_set_INTEN_B33SRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B33SRDY;
+}
+
+static inline bool hri_supc_get_INTEN_B33SRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_B33SRDY) >> SUPC_INTENSET_B33SRDY_Pos;
+}
+
+static inline void hri_supc_write_INTEN_B33SRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B33SRDY;
+	} else {
+		((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B33SRDY;
+	}
+}
+
+static inline void hri_supc_clear_INTEN_B33SRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B33SRDY;
+}
+
+static inline void hri_supc_set_INTEN_BOD12RDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD12RDY;
+}
+
+static inline bool hri_supc_get_INTEN_BOD12RDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD12RDY) >> SUPC_INTENSET_BOD12RDY_Pos;
+}
+
+static inline void hri_supc_write_INTEN_BOD12RDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD12RDY;
+	} else {
+		((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD12RDY;
+	}
+}
+
+static inline void hri_supc_clear_INTEN_BOD12RDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD12RDY;
+}
+
+static inline void hri_supc_set_INTEN_BOD12DET_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD12DET;
+}
+
+static inline bool hri_supc_get_INTEN_BOD12DET_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD12DET) >> SUPC_INTENSET_BOD12DET_Pos;
+}
+
+static inline void hri_supc_write_INTEN_BOD12DET_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD12DET;
+	} else {
+		((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD12DET;
+	}
+}
+
+static inline void hri_supc_clear_INTEN_BOD12DET_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD12DET;
+}
+
+static inline void hri_supc_set_INTEN_B12SRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B12SRDY;
+}
+
+static inline bool hri_supc_get_INTEN_B12SRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_B12SRDY) >> SUPC_INTENSET_B12SRDY_Pos;
+}
+
+static inline void hri_supc_write_INTEN_B12SRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B12SRDY;
+	} else {
+		((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B12SRDY;
+	}
+}
+
+static inline void hri_supc_clear_INTEN_B12SRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B12SRDY;
+}
+
+static inline void hri_supc_set_INTEN_VREGRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VREGRDY;
+}
+
+static inline bool hri_supc_get_INTEN_VREGRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_VREGRDY) >> SUPC_INTENSET_VREGRDY_Pos;
+}
+
+static inline void hri_supc_write_INTEN_VREGRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VREGRDY;
+	} else {
+		((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VREGRDY;
+	}
+}
+
+static inline void hri_supc_clear_INTEN_VREGRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VREGRDY;
+}
+
+static inline void hri_supc_set_INTEN_APWSRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_APWSRDY;
+}
+
+static inline bool hri_supc_get_INTEN_APWSRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_APWSRDY) >> SUPC_INTENSET_APWSRDY_Pos;
+}
+
+static inline void hri_supc_write_INTEN_APWSRDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_APWSRDY;
+	} else {
+		((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_APWSRDY;
+	}
+}
+
+static inline void hri_supc_clear_INTEN_APWSRDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_APWSRDY;
+}
+
+static inline void hri_supc_set_INTEN_VCORERDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VCORERDY;
+}
+
+static inline bool hri_supc_get_INTEN_VCORERDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_VCORERDY) >> SUPC_INTENSET_VCORERDY_Pos;
+}
+
+static inline void hri_supc_write_INTEN_VCORERDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VCORERDY;
+	} else {
+		((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VCORERDY;
+	}
+}
+
+static inline void hri_supc_clear_INTEN_VCORERDY_bit(const void *const hw)
+{
+	((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VCORERDY;
+}
+
+static inline void hri_supc_set_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask)
+{
+	((Supc *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_supc_intenset_reg_t hri_supc_get_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_supc_intenset_reg_t hri_supc_read_INTEN_reg(const void *const hw)
+{
+	return ((Supc *)hw)->INTENSET.reg;
+}
+
+static inline void hri_supc_write_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t data)
+{
+	((Supc *)hw)->INTENSET.reg = data;
+	((Supc *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_supc_clear_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask)
+{
+	((Supc *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_supc_get_STATUS_BOD33RDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD33RDY) >> SUPC_STATUS_BOD33RDY_Pos;
+}
+
+static inline bool hri_supc_get_STATUS_BOD33DET_bit(const void *const hw)
+{
+	return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD33DET) >> SUPC_STATUS_BOD33DET_Pos;
+}
+
+static inline bool hri_supc_get_STATUS_B33SRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_B33SRDY) >> SUPC_STATUS_B33SRDY_Pos;
+}
+
+static inline bool hri_supc_get_STATUS_BOD12RDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD12RDY) >> SUPC_STATUS_BOD12RDY_Pos;
+}
+
+static inline bool hri_supc_get_STATUS_BOD12DET_bit(const void *const hw)
+{
+	return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD12DET) >> SUPC_STATUS_BOD12DET_Pos;
+}
+
+static inline bool hri_supc_get_STATUS_B12SRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_B12SRDY) >> SUPC_STATUS_B12SRDY_Pos;
+}
+
+static inline bool hri_supc_get_STATUS_VREGRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_VREGRDY) >> SUPC_STATUS_VREGRDY_Pos;
+}
+
+static inline bool hri_supc_get_STATUS_APWSRDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_APWSRDY) >> SUPC_STATUS_APWSRDY_Pos;
+}
+
+static inline bool hri_supc_get_STATUS_VCORERDY_bit(const void *const hw)
+{
+	return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_VCORERDY) >> SUPC_STATUS_VCORERDY_Pos;
+}
+
+static inline bool hri_supc_get_STATUS_BBPS_bit(const void *const hw)
+{
+	return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BBPS) >> SUPC_STATUS_BBPS_Pos;
+}
+
+static inline hri_supc_status_reg_t hri_supc_get_STATUS_reg(const void *const hw, hri_supc_status_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_supc_status_reg_t hri_supc_read_STATUS_reg(const void *const hw)
+{
+	return ((Supc *)hw)->STATUS.reg;
+}
+
+static inline hri_supc_bkin_reg_t hri_supc_get_BKIN_BKIN_bf(const void *const hw, hri_supc_bkin_reg_t mask)
+{
+	return (((Supc *)hw)->BKIN.reg & SUPC_BKIN_BKIN(mask)) >> SUPC_BKIN_BKIN_Pos;
+}
+
+static inline hri_supc_bkin_reg_t hri_supc_read_BKIN_BKIN_bf(const void *const hw)
+{
+	return (((Supc *)hw)->BKIN.reg & SUPC_BKIN_BKIN_Msk) >> SUPC_BKIN_BKIN_Pos;
+}
+
+static inline hri_supc_bkin_reg_t hri_supc_get_BKIN_reg(const void *const hw, hri_supc_bkin_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BKIN.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_supc_bkin_reg_t hri_supc_read_BKIN_reg(const void *const hw)
+{
+	return ((Supc *)hw)->BKIN.reg;
+}
+
+static inline void hri_supc_set_BOD33_ENABLE_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_ENABLE;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_BOD33_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_ENABLE) >> SUPC_BOD33_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_BOD33_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= ~SUPC_BOD33_ENABLE;
+	tmp |= value << SUPC_BOD33_ENABLE_Pos;
+	((Supc *)hw)->BOD33.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_ENABLE_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_ENABLE;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_ENABLE_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_ENABLE;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_BOD33_HYST_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_HYST;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_BOD33_HYST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_HYST) >> SUPC_BOD33_HYST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_BOD33_HYST_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= ~SUPC_BOD33_HYST;
+	tmp |= value << SUPC_BOD33_HYST_Pos;
+	((Supc *)hw)->BOD33.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_HYST_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_HYST;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_HYST_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_HYST;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_BOD33_STDBYCFG_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_STDBYCFG;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_BOD33_STDBYCFG_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_STDBYCFG) >> SUPC_BOD33_STDBYCFG_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_BOD33_STDBYCFG_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= ~SUPC_BOD33_STDBYCFG;
+	tmp |= value << SUPC_BOD33_STDBYCFG_Pos;
+	((Supc *)hw)->BOD33.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_STDBYCFG_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_STDBYCFG;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_STDBYCFG_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_STDBYCFG;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_BOD33_RUNSTDBY_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_RUNSTDBY;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_BOD33_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_RUNSTDBY) >> SUPC_BOD33_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_BOD33_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= ~SUPC_BOD33_RUNSTDBY;
+	tmp |= value << SUPC_BOD33_RUNSTDBY_Pos;
+	((Supc *)hw)->BOD33.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_RUNSTDBY_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_RUNSTDBY;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_RUNSTDBY_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_RUNSTDBY;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_BOD33_RUNBKUP_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_RUNBKUP;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_BOD33_RUNBKUP_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_RUNBKUP) >> SUPC_BOD33_RUNBKUP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_BOD33_RUNBKUP_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= ~SUPC_BOD33_RUNBKUP;
+	tmp |= value << SUPC_BOD33_RUNBKUP_Pos;
+	((Supc *)hw)->BOD33.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_RUNBKUP_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_RUNBKUP;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_RUNBKUP_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_RUNBKUP;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_BOD33_ACTCFG_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_ACTCFG;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_BOD33_ACTCFG_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_ACTCFG) >> SUPC_BOD33_ACTCFG_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_BOD33_ACTCFG_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= ~SUPC_BOD33_ACTCFG;
+	tmp |= value << SUPC_BOD33_ACTCFG_Pos;
+	((Supc *)hw)->BOD33.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_ACTCFG_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_ACTCFG;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_ACTCFG_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_ACTCFG;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_BOD33_VMON_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_VMON;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_BOD33_VMON_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_VMON) >> SUPC_BOD33_VMON_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_BOD33_VMON_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= ~SUPC_BOD33_VMON;
+	tmp |= value << SUPC_BOD33_VMON_Pos;
+	((Supc *)hw)->BOD33.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_VMON_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_VMON;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_VMON_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_VMON;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_ACTION(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_ACTION(mask)) >> SUPC_BOD33_ACTION_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= ~SUPC_BOD33_ACTION_Msk;
+	tmp |= SUPC_BOD33_ACTION(data);
+	((Supc *)hw)->BOD33.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_ACTION(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_ACTION(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_ACTION_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_ACTION_Msk) >> SUPC_BOD33_ACTION_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_PSEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_PSEL(mask)) >> SUPC_BOD33_PSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= ~SUPC_BOD33_PSEL_Msk;
+	tmp |= SUPC_BOD33_PSEL(data);
+	((Supc *)hw)->BOD33.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_PSEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_PSEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_PSEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_PSEL_Msk) >> SUPC_BOD33_PSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_LEVEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_LEVEL(mask)) >> SUPC_BOD33_LEVEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= ~SUPC_BOD33_LEVEL_Msk;
+	tmp |= SUPC_BOD33_LEVEL(data);
+	((Supc *)hw)->BOD33.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_LEVEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_LEVEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_LEVEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_LEVEL_Msk) >> SUPC_BOD33_LEVEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_BOD33_BKUPLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= SUPC_BOD33_BKUPLEVEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_BKUPLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_BKUPLEVEL(mask)) >> SUPC_BOD33_BKUPLEVEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_BOD33_BKUPLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= ~SUPC_BOD33_BKUPLEVEL_Msk;
+	tmp |= SUPC_BOD33_BKUPLEVEL(data);
+	((Supc *)hw)->BOD33.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_BKUPLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_BKUPLEVEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_BKUPLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_BKUPLEVEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_BKUPLEVEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp = (tmp & SUPC_BOD33_BKUPLEVEL_Msk) >> SUPC_BOD33_BKUPLEVEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg |= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD33.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_supc_write_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t data)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg = data;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg &= ~mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD33.reg ^= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_reg(const void *const hw)
+{
+	return ((Supc *)hw)->BOD33.reg;
+}
+
+static inline void hri_supc_set_BOD12_ENABLE_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg |= SUPC_BOD12_ENABLE;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_BOD12_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp = (tmp & SUPC_BOD12_ENABLE) >> SUPC_BOD12_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_BOD12_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp &= ~SUPC_BOD12_ENABLE;
+	tmp |= value << SUPC_BOD12_ENABLE_Pos;
+	((Supc *)hw)->BOD12.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD12_ENABLE_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_ENABLE;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD12_ENABLE_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_ENABLE;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_BOD12_HYST_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg |= SUPC_BOD12_HYST;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_BOD12_HYST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp = (tmp & SUPC_BOD12_HYST) >> SUPC_BOD12_HYST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_BOD12_HYST_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp &= ~SUPC_BOD12_HYST;
+	tmp |= value << SUPC_BOD12_HYST_Pos;
+	((Supc *)hw)->BOD12.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD12_HYST_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_HYST;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD12_HYST_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_HYST;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_BOD12_STDBYCFG_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg |= SUPC_BOD12_STDBYCFG;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_BOD12_STDBYCFG_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp = (tmp & SUPC_BOD12_STDBYCFG) >> SUPC_BOD12_STDBYCFG_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_BOD12_STDBYCFG_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp &= ~SUPC_BOD12_STDBYCFG;
+	tmp |= value << SUPC_BOD12_STDBYCFG_Pos;
+	((Supc *)hw)->BOD12.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD12_STDBYCFG_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_STDBYCFG;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD12_STDBYCFG_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_STDBYCFG;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_BOD12_RUNSTDBY_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg |= SUPC_BOD12_RUNSTDBY;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_BOD12_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp = (tmp & SUPC_BOD12_RUNSTDBY) >> SUPC_BOD12_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_BOD12_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp &= ~SUPC_BOD12_RUNSTDBY;
+	tmp |= value << SUPC_BOD12_RUNSTDBY_Pos;
+	((Supc *)hw)->BOD12.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD12_RUNSTDBY_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_RUNSTDBY;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD12_RUNSTDBY_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_RUNSTDBY;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_BOD12_ACTCFG_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg |= SUPC_BOD12_ACTCFG;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_BOD12_ACTCFG_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp = (tmp & SUPC_BOD12_ACTCFG) >> SUPC_BOD12_ACTCFG_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_BOD12_ACTCFG_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp &= ~SUPC_BOD12_ACTCFG;
+	tmp |= value << SUPC_BOD12_ACTCFG_Pos;
+	((Supc *)hw)->BOD12.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD12_ACTCFG_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_ACTCFG;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD12_ACTCFG_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_ACTCFG;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg |= SUPC_BOD12_ACTION(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod12_reg_t hri_supc_get_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp = (tmp & SUPC_BOD12_ACTION(mask)) >> SUPC_BOD12_ACTION_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp &= ~SUPC_BOD12_ACTION_Msk;
+	tmp |= SUPC_BOD12_ACTION(data);
+	((Supc *)hw)->BOD12.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_ACTION(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_ACTION(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod12_reg_t hri_supc_read_BOD12_ACTION_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp = (tmp & SUPC_BOD12_ACTION_Msk) >> SUPC_BOD12_ACTION_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg |= SUPC_BOD12_PSEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod12_reg_t hri_supc_get_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp = (tmp & SUPC_BOD12_PSEL(mask)) >> SUPC_BOD12_PSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp &= ~SUPC_BOD12_PSEL_Msk;
+	tmp |= SUPC_BOD12_PSEL(data);
+	((Supc *)hw)->BOD12.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_PSEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_PSEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod12_reg_t hri_supc_read_BOD12_PSEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp = (tmp & SUPC_BOD12_PSEL_Msk) >> SUPC_BOD12_PSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg |= SUPC_BOD12_LEVEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod12_reg_t hri_supc_get_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp = (tmp & SUPC_BOD12_LEVEL(mask)) >> SUPC_BOD12_LEVEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp &= ~SUPC_BOD12_LEVEL_Msk;
+	tmp |= SUPC_BOD12_LEVEL(data);
+	((Supc *)hw)->BOD12.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_LEVEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_LEVEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod12_reg_t hri_supc_read_BOD12_LEVEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp = (tmp & SUPC_BOD12_LEVEL_Msk) >> SUPC_BOD12_LEVEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg |= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod12_reg_t hri_supc_get_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BOD12.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_supc_write_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t data)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg = data;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg &= ~mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BOD12.reg ^= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bod12_reg_t hri_supc_read_BOD12_reg(const void *const hw)
+{
+	return ((Supc *)hw)->BOD12.reg;
+}
+
+static inline void hri_supc_set_VREG_ENABLE_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg |= SUPC_VREG_ENABLE;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_VREG_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp = (tmp & SUPC_VREG_ENABLE) >> SUPC_VREG_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_VREG_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp &= ~SUPC_VREG_ENABLE;
+	tmp |= value << SUPC_VREG_ENABLE_Pos;
+	((Supc *)hw)->VREG.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREG_ENABLE_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg &= ~SUPC_VREG_ENABLE;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREG_ENABLE_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg ^= SUPC_VREG_ENABLE;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_VREG_STDBYPL0_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg |= SUPC_VREG_STDBYPL0;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_VREG_STDBYPL0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp = (tmp & SUPC_VREG_STDBYPL0) >> SUPC_VREG_STDBYPL0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_VREG_STDBYPL0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp &= ~SUPC_VREG_STDBYPL0;
+	tmp |= value << SUPC_VREG_STDBYPL0_Pos;
+	((Supc *)hw)->VREG.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREG_STDBYPL0_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg &= ~SUPC_VREG_STDBYPL0;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREG_STDBYPL0_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg ^= SUPC_VREG_STDBYPL0;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_VREG_RUNSTDBY_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg |= SUPC_VREG_RUNSTDBY;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_VREG_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp = (tmp & SUPC_VREG_RUNSTDBY) >> SUPC_VREG_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_VREG_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp &= ~SUPC_VREG_RUNSTDBY;
+	tmp |= value << SUPC_VREG_RUNSTDBY_Pos;
+	((Supc *)hw)->VREG.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREG_RUNSTDBY_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg &= ~SUPC_VREG_RUNSTDBY;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREG_RUNSTDBY_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg ^= SUPC_VREG_RUNSTDBY;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_VREG_LPEFF_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg |= SUPC_VREG_LPEFF;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_VREG_LPEFF_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp = (tmp & SUPC_VREG_LPEFF) >> SUPC_VREG_LPEFF_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_VREG_LPEFF_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp &= ~SUPC_VREG_LPEFF;
+	tmp |= value << SUPC_VREG_LPEFF_Pos;
+	((Supc *)hw)->VREG.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREG_LPEFF_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg &= ~SUPC_VREG_LPEFF;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREG_LPEFF_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg ^= SUPC_VREG_LPEFF;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_VREG_SEL_bf(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg |= SUPC_VREG_SEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_vreg_reg_t hri_supc_get_VREG_SEL_bf(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp = (tmp & SUPC_VREG_SEL(mask)) >> SUPC_VREG_SEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_VREG_SEL_bf(const void *const hw, hri_supc_vreg_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp &= ~SUPC_VREG_SEL_Msk;
+	tmp |= SUPC_VREG_SEL(data);
+	((Supc *)hw)->VREG.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREG_SEL_bf(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg &= ~SUPC_VREG_SEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREG_SEL_bf(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg ^= SUPC_VREG_SEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_vreg_reg_t hri_supc_read_VREG_SEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp = (tmp & SUPC_VREG_SEL_Msk) >> SUPC_VREG_SEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_VREG_VSVSTEP_bf(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg |= SUPC_VREG_VSVSTEP(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_vreg_reg_t hri_supc_get_VREG_VSVSTEP_bf(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp = (tmp & SUPC_VREG_VSVSTEP(mask)) >> SUPC_VREG_VSVSTEP_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_VREG_VSVSTEP_bf(const void *const hw, hri_supc_vreg_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp &= ~SUPC_VREG_VSVSTEP_Msk;
+	tmp |= SUPC_VREG_VSVSTEP(data);
+	((Supc *)hw)->VREG.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREG_VSVSTEP_bf(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg &= ~SUPC_VREG_VSVSTEP(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREG_VSVSTEP_bf(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg ^= SUPC_VREG_VSVSTEP(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_vreg_reg_t hri_supc_read_VREG_VSVSTEP_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp = (tmp & SUPC_VREG_VSVSTEP_Msk) >> SUPC_VREG_VSVSTEP_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg |= SUPC_VREG_VSPER(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_vreg_reg_t hri_supc_get_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp = (tmp & SUPC_VREG_VSPER(mask)) >> SUPC_VREG_VSPER_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp &= ~SUPC_VREG_VSPER_Msk;
+	tmp |= SUPC_VREG_VSPER(data);
+	((Supc *)hw)->VREG.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg &= ~SUPC_VREG_VSPER(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg ^= SUPC_VREG_VSPER(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_vreg_reg_t hri_supc_read_VREG_VSPER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp = (tmp & SUPC_VREG_VSPER_Msk) >> SUPC_VREG_VSPER_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg |= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_vreg_reg_t hri_supc_get_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_supc_write_VREG_reg(const void *const hw, hri_supc_vreg_reg_t data)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg = data;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg &= ~mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREG.reg ^= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_vreg_reg_t hri_supc_read_VREG_reg(const void *const hw)
+{
+	return ((Supc *)hw)->VREG.reg;
+}
+
+static inline void hri_supc_set_VREF_TSEN_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg |= SUPC_VREF_TSEN;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_VREF_TSEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp = (tmp & SUPC_VREF_TSEN) >> SUPC_VREF_TSEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_VREF_TSEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp &= ~SUPC_VREF_TSEN;
+	tmp |= value << SUPC_VREF_TSEN_Pos;
+	((Supc *)hw)->VREF.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREF_TSEN_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg &= ~SUPC_VREF_TSEN;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREF_TSEN_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg ^= SUPC_VREF_TSEN;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_VREF_VREFOE_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg |= SUPC_VREF_VREFOE;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_VREF_VREFOE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp = (tmp & SUPC_VREF_VREFOE) >> SUPC_VREF_VREFOE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_VREF_VREFOE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp &= ~SUPC_VREF_VREFOE;
+	tmp |= value << SUPC_VREF_VREFOE_Pos;
+	((Supc *)hw)->VREF.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREF_VREFOE_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg &= ~SUPC_VREF_VREFOE;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREF_VREFOE_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg ^= SUPC_VREF_VREFOE;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_VREF_TSSEL_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg |= SUPC_VREF_TSSEL;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_VREF_TSSEL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp = (tmp & SUPC_VREF_TSSEL) >> SUPC_VREF_TSSEL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_VREF_TSSEL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp &= ~SUPC_VREF_TSSEL;
+	tmp |= value << SUPC_VREF_TSSEL_Pos;
+	((Supc *)hw)->VREF.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREF_TSSEL_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg &= ~SUPC_VREF_TSSEL;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREF_TSSEL_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg ^= SUPC_VREF_TSSEL;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_VREF_RUNSTDBY_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg |= SUPC_VREF_RUNSTDBY;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_VREF_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp = (tmp & SUPC_VREF_RUNSTDBY) >> SUPC_VREF_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_VREF_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp &= ~SUPC_VREF_RUNSTDBY;
+	tmp |= value << SUPC_VREF_RUNSTDBY_Pos;
+	((Supc *)hw)->VREF.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREF_RUNSTDBY_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg &= ~SUPC_VREF_RUNSTDBY;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREF_RUNSTDBY_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg ^= SUPC_VREF_RUNSTDBY;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_VREF_ONDEMAND_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg |= SUPC_VREF_ONDEMAND;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_VREF_ONDEMAND_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp = (tmp & SUPC_VREF_ONDEMAND) >> SUPC_VREF_ONDEMAND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_VREF_ONDEMAND_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp &= ~SUPC_VREF_ONDEMAND;
+	tmp |= value << SUPC_VREF_ONDEMAND_Pos;
+	((Supc *)hw)->VREF.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREF_ONDEMAND_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg &= ~SUPC_VREF_ONDEMAND;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREF_ONDEMAND_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg ^= SUPC_VREF_ONDEMAND;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg |= SUPC_VREF_SEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_vref_reg_t hri_supc_get_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp = (tmp & SUPC_VREF_SEL(mask)) >> SUPC_VREF_SEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp &= ~SUPC_VREF_SEL_Msk;
+	tmp |= SUPC_VREF_SEL(data);
+	((Supc *)hw)->VREF.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg &= ~SUPC_VREF_SEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg ^= SUPC_VREF_SEL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_vref_reg_t hri_supc_read_VREF_SEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp = (tmp & SUPC_VREF_SEL_Msk) >> SUPC_VREF_SEL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg |= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_vref_reg_t hri_supc_get_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->VREF.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_supc_write_VREF_reg(const void *const hw, hri_supc_vref_reg_t data)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg = data;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg &= ~mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->VREF.reg ^= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_vref_reg_t hri_supc_read_VREF_reg(const void *const hw)
+{
+	return ((Supc *)hw)->VREF.reg;
+}
+
+static inline void hri_supc_set_BBPS_WAKEEN_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg |= SUPC_BBPS_WAKEEN;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_BBPS_WAKEEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BBPS.reg;
+	tmp = (tmp & SUPC_BBPS_WAKEEN) >> SUPC_BBPS_WAKEEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_BBPS_WAKEEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BBPS.reg;
+	tmp &= ~SUPC_BBPS_WAKEEN;
+	tmp |= value << SUPC_BBPS_WAKEEN_Pos;
+	((Supc *)hw)->BBPS.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BBPS_WAKEEN_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg &= ~SUPC_BBPS_WAKEEN;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BBPS_WAKEEN_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg ^= SUPC_BBPS_WAKEEN;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_BBPS_PSOKEN_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg |= SUPC_BBPS_PSOKEN;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_supc_get_BBPS_PSOKEN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BBPS.reg;
+	tmp = (tmp & SUPC_BBPS_PSOKEN) >> SUPC_BBPS_PSOKEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_supc_write_BBPS_PSOKEN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BBPS.reg;
+	tmp &= ~SUPC_BBPS_PSOKEN;
+	tmp |= value << SUPC_BBPS_PSOKEN_Pos;
+	((Supc *)hw)->BBPS.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BBPS_PSOKEN_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg &= ~SUPC_BBPS_PSOKEN;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BBPS_PSOKEN_bit(const void *const hw)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg ^= SUPC_BBPS_PSOKEN;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_set_BBPS_CONF_bf(const void *const hw, hri_supc_bbps_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg |= SUPC_BBPS_CONF(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bbps_reg_t hri_supc_get_BBPS_CONF_bf(const void *const hw, hri_supc_bbps_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BBPS.reg;
+	tmp = (tmp & SUPC_BBPS_CONF(mask)) >> SUPC_BBPS_CONF_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_BBPS_CONF_bf(const void *const hw, hri_supc_bbps_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BBPS.reg;
+	tmp &= ~SUPC_BBPS_CONF_Msk;
+	tmp |= SUPC_BBPS_CONF(data);
+	((Supc *)hw)->BBPS.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BBPS_CONF_bf(const void *const hw, hri_supc_bbps_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg &= ~SUPC_BBPS_CONF(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BBPS_CONF_bf(const void *const hw, hri_supc_bbps_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg ^= SUPC_BBPS_CONF(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bbps_reg_t hri_supc_read_BBPS_CONF_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BBPS.reg;
+	tmp = (tmp & SUPC_BBPS_CONF_Msk) >> SUPC_BBPS_CONF_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg |= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bbps_reg_t hri_supc_get_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BBPS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_supc_write_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t data)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg = data;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg &= ~mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BBPS.reg ^= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bbps_reg_t hri_supc_read_BBPS_reg(const void *const hw)
+{
+	return ((Supc *)hw)->BBPS.reg;
+}
+
+static inline void hri_supc_set_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_EN(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp = (tmp & SUPC_BKOUT_EN(mask)) >> SUPC_BKOUT_EN_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp &= ~SUPC_BKOUT_EN_Msk;
+	tmp |= SUPC_BKOUT_EN(data);
+	((Supc *)hw)->BKOUT.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_EN(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_EN(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_EN_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp = (tmp & SUPC_BKOUT_EN_Msk) >> SUPC_BKOUT_EN_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_CLR(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp = (tmp & SUPC_BKOUT_CLR(mask)) >> SUPC_BKOUT_CLR_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp &= ~SUPC_BKOUT_CLR_Msk;
+	tmp |= SUPC_BKOUT_CLR(data);
+	((Supc *)hw)->BKOUT.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_CLR(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_CLR(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_CLR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp = (tmp & SUPC_BKOUT_CLR_Msk) >> SUPC_BKOUT_CLR_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_SET(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp = (tmp & SUPC_BKOUT_SET(mask)) >> SUPC_BKOUT_SET_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp &= ~SUPC_BKOUT_SET_Msk;
+	tmp |= SUPC_BKOUT_SET(data);
+	((Supc *)hw)->BKOUT.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_SET(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_SET(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_SET_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp = (tmp & SUPC_BKOUT_SET_Msk) >> SUPC_BKOUT_SET_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_RTCTGL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp = (tmp & SUPC_BKOUT_RTCTGL(mask)) >> SUPC_BKOUT_RTCTGL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_write_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t data)
+{
+	uint32_t tmp;
+	SUPC_CRITICAL_SECTION_ENTER();
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp &= ~SUPC_BKOUT_RTCTGL_Msk;
+	tmp |= SUPC_BKOUT_RTCTGL(data);
+	((Supc *)hw)->BKOUT.reg = tmp;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_RTCTGL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_RTCTGL(mask);
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_RTCTGL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp = (tmp & SUPC_BKOUT_RTCTGL_Msk) >> SUPC_BKOUT_RTCTGL_Pos;
+	return tmp;
+}
+
+static inline void hri_supc_set_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg |= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Supc *)hw)->BKOUT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_supc_write_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t data)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg = data;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_clear_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg &= ~mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_supc_toggle_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask)
+{
+	SUPC_CRITICAL_SECTION_ENTER();
+	((Supc *)hw)->BKOUT.reg ^= mask;
+	SUPC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_reg(const void *const hw)
+{
+	return ((Supc *)hw)->BKOUT.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_SUPC_L22_H_INCLUDED */
+#endif /* _SAML22_SUPC_COMPONENT_ */
diff --git a/watch-library/hardware/hri/hri_systemcontrol_l22.h b/watch-library/hardware/hri/hri_systemcontrol_l22.h
new file mode 100644
index 00000000..9553d51a
--- /dev/null
+++ b/watch-library/hardware/hri/hri_systemcontrol_l22.h
@@ -0,0 +1,498 @@
+/**
+ * \file
+ *
+ * \brief SAM SystemControl
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_SystemControl_COMPONENT_
+#ifndef _HRI_SystemControl_L22_H_INCLUDED_
+#define _HRI_SystemControl_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_SystemControl_CRITICAL_SECTIONS)
+#define SystemControl_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define SystemControl_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define SystemControl_CRITICAL_SECTION_ENTER()
+#define SystemControl_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_systemcontrol_aircr_reg_t;
+typedef uint32_t hri_systemcontrol_ccr_reg_t;
+typedef uint32_t hri_systemcontrol_cpuid_reg_t;
+typedef uint32_t hri_systemcontrol_dfsr_reg_t;
+typedef uint32_t hri_systemcontrol_icsr_reg_t;
+typedef uint32_t hri_systemcontrol_scr_reg_t;
+typedef uint32_t hri_systemcontrol_shcsr_reg_t;
+typedef uint32_t hri_systemcontrol_shpr2_reg_t;
+typedef uint32_t hri_systemcontrol_shpr3_reg_t;
+typedef uint32_t hri_systemcontrol_vtor_reg_t;
+
+static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_REVISION_bf(const void *const             hw,
+                                                                                    hri_systemcontrol_cpuid_reg_t mask)
+{
+	return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_REVISION(mask)) >> 0;
+}
+
+static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_REVISION_bf(const void *const hw)
+{
+	return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_REVISION_Msk) >> 0;
+}
+
+static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_PARTNO_bf(const void *const             hw,
+                                                                                  hri_systemcontrol_cpuid_reg_t mask)
+{
+	return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_PARTNO(mask)) >> 4;
+}
+
+static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_PARTNO_bf(const void *const hw)
+{
+	return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_PARTNO_Msk) >> 4;
+}
+
+static inline hri_systemcontrol_cpuid_reg_t
+hri_systemcontrol_get_CPUID_ARCHITECTURE_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask)
+{
+	return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_ARCHITECTURE(mask)) >> 16;
+}
+
+static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_ARCHITECTURE_bf(const void *const hw)
+{
+	return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_ARCHITECTURE_Msk) >> 16;
+}
+
+static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_VARIANT_bf(const void *const             hw,
+                                                                                   hri_systemcontrol_cpuid_reg_t mask)
+{
+	return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_VARIANT(mask)) >> 20;
+}
+
+static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_VARIANT_bf(const void *const hw)
+{
+	return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_VARIANT_Msk) >> 20;
+}
+
+static inline hri_systemcontrol_cpuid_reg_t
+hri_systemcontrol_get_CPUID_IMPLEMENTER_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask)
+{
+	return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_IMPLEMENTER(mask)) >> 24;
+}
+
+static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_IMPLEMENTER_bf(const void *const hw)
+{
+	return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_IMPLEMENTER_Msk) >> 24;
+}
+
+static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_reg(const void *const             hw,
+                                                                            hri_systemcontrol_cpuid_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->CPUID.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_reg(const void *const hw)
+{
+	return ((Systemcontrol *)hw)->CPUID.reg;
+}
+
+static inline bool hri_systemcontrol_get_CCR_UNALIGN_TRP_bit(const void *const hw)
+{
+	return (((Systemcontrol *)hw)->CCR.reg & SystemControl_CCR_UNALIGN_TRP) >> 3;
+}
+
+static inline bool hri_systemcontrol_get_CCR_STKALIGN_bit(const void *const hw)
+{
+	return (((Systemcontrol *)hw)->CCR.reg & SystemControl_CCR_STKALIGN) >> 9;
+}
+
+static inline hri_systemcontrol_ccr_reg_t hri_systemcontrol_get_CCR_reg(const void *const           hw,
+                                                                        hri_systemcontrol_ccr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->CCR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_systemcontrol_ccr_reg_t hri_systemcontrol_read_CCR_reg(const void *const hw)
+{
+	return ((Systemcontrol *)hw)->CCR.reg;
+}
+
+static inline void hri_systemcontrol_set_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->ICSR.reg |= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_icsr_reg_t hri_systemcontrol_get_ICSR_reg(const void *const            hw,
+                                                                          hri_systemcontrol_icsr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->ICSR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_write_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t data)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->ICSR.reg = data;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->ICSR.reg &= ~mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->ICSR.reg ^= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_icsr_reg_t hri_systemcontrol_read_ICSR_reg(const void *const hw)
+{
+	return ((Systemcontrol *)hw)->ICSR.reg;
+}
+
+static inline void hri_systemcontrol_set_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->VTOR.reg |= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_vtor_reg_t hri_systemcontrol_get_VTOR_reg(const void *const            hw,
+                                                                          hri_systemcontrol_vtor_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->VTOR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_write_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t data)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->VTOR.reg = data;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->VTOR.reg &= ~mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->VTOR.reg ^= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_vtor_reg_t hri_systemcontrol_read_VTOR_reg(const void *const hw)
+{
+	return ((Systemcontrol *)hw)->VTOR.reg;
+}
+
+static inline void hri_systemcontrol_set_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->AIRCR.reg |= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_aircr_reg_t hri_systemcontrol_get_AIRCR_reg(const void *const             hw,
+                                                                            hri_systemcontrol_aircr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->AIRCR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_write_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t data)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->AIRCR.reg = data;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->AIRCR.reg &= ~mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->AIRCR.reg ^= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_aircr_reg_t hri_systemcontrol_read_AIRCR_reg(const void *const hw)
+{
+	return ((Systemcontrol *)hw)->AIRCR.reg;
+}
+
+static inline void hri_systemcontrol_set_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SCR.reg |= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_scr_reg_t hri_systemcontrol_get_SCR_reg(const void *const           hw,
+                                                                        hri_systemcontrol_scr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->SCR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_write_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t data)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SCR.reg = data;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SCR.reg &= ~mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SCR.reg ^= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_scr_reg_t hri_systemcontrol_read_SCR_reg(const void *const hw)
+{
+	return ((Systemcontrol *)hw)->SCR.reg;
+}
+
+static inline void hri_systemcontrol_set_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHPR2.reg |= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_shpr2_reg_t hri_systemcontrol_get_SHPR2_reg(const void *const             hw,
+                                                                            hri_systemcontrol_shpr2_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->SHPR2.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_write_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t data)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHPR2.reg = data;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHPR2.reg &= ~mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHPR2.reg ^= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_shpr2_reg_t hri_systemcontrol_read_SHPR2_reg(const void *const hw)
+{
+	return ((Systemcontrol *)hw)->SHPR2.reg;
+}
+
+static inline void hri_systemcontrol_set_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHPR3.reg |= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_shpr3_reg_t hri_systemcontrol_get_SHPR3_reg(const void *const             hw,
+                                                                            hri_systemcontrol_shpr3_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->SHPR3.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_write_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t data)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHPR3.reg = data;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHPR3.reg &= ~mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHPR3.reg ^= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_shpr3_reg_t hri_systemcontrol_read_SHPR3_reg(const void *const hw)
+{
+	return ((Systemcontrol *)hw)->SHPR3.reg;
+}
+
+static inline void hri_systemcontrol_set_SHCSR_reg(const void *const hw, hri_systemcontrol_shcsr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHCSR.reg |= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_shcsr_reg_t hri_systemcontrol_get_SHCSR_reg(const void *const             hw,
+                                                                            hri_systemcontrol_shcsr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->SHCSR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_write_SHCSR_reg(const void *const hw, hri_systemcontrol_shcsr_reg_t data)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHCSR.reg = data;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_SHCSR_reg(const void *const hw, hri_systemcontrol_shcsr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHCSR.reg &= ~mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_SHCSR_reg(const void *const hw, hri_systemcontrol_shcsr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->SHCSR.reg ^= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_shcsr_reg_t hri_systemcontrol_read_SHCSR_reg(const void *const hw)
+{
+	return ((Systemcontrol *)hw)->SHCSR.reg;
+}
+
+static inline void hri_systemcontrol_set_DFSR_reg(const void *const hw, hri_systemcontrol_dfsr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->DFSR.reg |= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_dfsr_reg_t hri_systemcontrol_get_DFSR_reg(const void *const            hw,
+                                                                          hri_systemcontrol_dfsr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systemcontrol *)hw)->DFSR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_systemcontrol_write_DFSR_reg(const void *const hw, hri_systemcontrol_dfsr_reg_t data)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->DFSR.reg = data;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_clear_DFSR_reg(const void *const hw, hri_systemcontrol_dfsr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->DFSR.reg &= ~mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systemcontrol_toggle_DFSR_reg(const void *const hw, hri_systemcontrol_dfsr_reg_t mask)
+{
+	SystemControl_CRITICAL_SECTION_ENTER();
+	((Systemcontrol *)hw)->DFSR.reg ^= mask;
+	SystemControl_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systemcontrol_dfsr_reg_t hri_systemcontrol_read_DFSR_reg(const void *const hw)
+{
+	return ((Systemcontrol *)hw)->DFSR.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_SystemControl_L22_H_INCLUDED */
+#endif /* _SAML22_SystemControl_COMPONENT_ */
diff --git a/watch-library/hardware/hri/hri_systick_l22.h b/watch-library/hardware/hri/hri_systick_l22.h
new file mode 100644
index 00000000..aa09233f
--- /dev/null
+++ b/watch-library/hardware/hri/hri_systick_l22.h
@@ -0,0 +1,219 @@
+/**
+ * \file
+ *
+ * \brief SAM SysTick
+ *
+ * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_SysTick_COMPONENT_
+#ifndef _HRI_SysTick_L22_H_INCLUDED_
+#define _HRI_SysTick_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_SysTick_CRITICAL_SECTIONS)
+#define SysTick_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define SysTick_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define SysTick_CRITICAL_SECTION_ENTER()
+#define SysTick_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_systick_calib_reg_t;
+typedef uint32_t hri_systick_csr_reg_t;
+typedef uint32_t hri_systick_cvr_reg_t;
+typedef uint32_t hri_systick_rvr_reg_t;
+
+static inline bool hri_systick_get_CALIB_SKEW_bit(const void *const hw)
+{
+	return (((Systick *)hw)->CALIB.reg & SysTick_CALIB_SKEW) >> 30;
+}
+
+static inline bool hri_systick_get_CALIB_NOREF_bit(const void *const hw)
+{
+	return (((Systick *)hw)->CALIB.reg & SysTick_CALIB_NOREF) >> 31;
+}
+
+static inline hri_systick_calib_reg_t hri_systick_get_CALIB_TENMS_bf(const void *const hw, hri_systick_calib_reg_t mask)
+{
+	return (((Systick *)hw)->CALIB.reg & SysTick_CALIB_TENMS(mask)) >> 0;
+}
+
+static inline hri_systick_calib_reg_t hri_systick_read_CALIB_TENMS_bf(const void *const hw)
+{
+	return (((Systick *)hw)->CALIB.reg & SysTick_CALIB_TENMS_Msk) >> 0;
+}
+
+static inline hri_systick_calib_reg_t hri_systick_get_CALIB_reg(const void *const hw, hri_systick_calib_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systick *)hw)->CALIB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_systick_calib_reg_t hri_systick_read_CALIB_reg(const void *const hw)
+{
+	return ((Systick *)hw)->CALIB.reg;
+}
+
+static inline void hri_systick_set_CSR_reg(const void *const hw, hri_systick_csr_reg_t mask)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CSR.reg |= mask;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systick_csr_reg_t hri_systick_get_CSR_reg(const void *const hw, hri_systick_csr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systick *)hw)->CSR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_systick_write_CSR_reg(const void *const hw, hri_systick_csr_reg_t data)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CSR.reg = data;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systick_clear_CSR_reg(const void *const hw, hri_systick_csr_reg_t mask)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CSR.reg &= ~mask;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systick_toggle_CSR_reg(const void *const hw, hri_systick_csr_reg_t mask)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CSR.reg ^= mask;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systick_csr_reg_t hri_systick_read_CSR_reg(const void *const hw)
+{
+	return ((Systick *)hw)->CSR.reg;
+}
+
+static inline void hri_systick_set_RVR_reg(const void *const hw, hri_systick_rvr_reg_t mask)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->RVR.reg |= mask;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systick_rvr_reg_t hri_systick_get_RVR_reg(const void *const hw, hri_systick_rvr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systick *)hw)->RVR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_systick_write_RVR_reg(const void *const hw, hri_systick_rvr_reg_t data)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->RVR.reg = data;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systick_clear_RVR_reg(const void *const hw, hri_systick_rvr_reg_t mask)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->RVR.reg &= ~mask;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systick_toggle_RVR_reg(const void *const hw, hri_systick_rvr_reg_t mask)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->RVR.reg ^= mask;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systick_rvr_reg_t hri_systick_read_RVR_reg(const void *const hw)
+{
+	return ((Systick *)hw)->RVR.reg;
+}
+
+static inline void hri_systick_set_CVR_reg(const void *const hw, hri_systick_cvr_reg_t mask)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CVR.reg |= mask;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systick_cvr_reg_t hri_systick_get_CVR_reg(const void *const hw, hri_systick_cvr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Systick *)hw)->CVR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_systick_write_CVR_reg(const void *const hw, hri_systick_cvr_reg_t data)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CVR.reg = data;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systick_clear_CVR_reg(const void *const hw, hri_systick_cvr_reg_t mask)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CVR.reg &= ~mask;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_systick_toggle_CVR_reg(const void *const hw, hri_systick_cvr_reg_t mask)
+{
+	SysTick_CRITICAL_SECTION_ENTER();
+	((Systick *)hw)->CVR.reg ^= mask;
+	SysTick_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_systick_cvr_reg_t hri_systick_read_CVR_reg(const void *const hw)
+{
+	return ((Systick *)hw)->CVR.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_SysTick_L22_H_INCLUDED */
+#endif /* _SAML22_SysTick_COMPONENT_ */
diff --git a/watch-library/hardware/hri/hri_tc_l22.h b/watch-library/hardware/hri/hri_tc_l22.h
new file mode 100644
index 00000000..8fab128c
--- /dev/null
+++ b/watch-library/hardware/hri/hri_tc_l22.h
@@ -0,0 +1,2899 @@
+/**
+ * \file
+ *
+ * \brief SAM TC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_TC_COMPONENT_
+#ifndef _HRI_TC_L22_H_INCLUDED_
+#define _HRI_TC_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_TC_CRITICAL_SECTIONS)
+#define TC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define TC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define TC_CRITICAL_SECTION_ENTER()
+#define TC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_tc_evctrl_reg_t;
+typedef uint16_t hri_tccount16_cc_reg_t;
+typedef uint16_t hri_tccount16_ccbuf_reg_t;
+typedef uint16_t hri_tccount16_count_reg_t;
+typedef uint32_t hri_tc_ctrla_reg_t;
+typedef uint32_t hri_tc_syncbusy_reg_t;
+typedef uint32_t hri_tccount32_cc_reg_t;
+typedef uint32_t hri_tccount32_ccbuf_reg_t;
+typedef uint32_t hri_tccount32_count_reg_t;
+typedef uint8_t  hri_tc_ctrlbset_reg_t;
+typedef uint8_t  hri_tc_dbgctrl_reg_t;
+typedef uint8_t  hri_tc_drvctrl_reg_t;
+typedef uint8_t  hri_tc_intenset_reg_t;
+typedef uint8_t  hri_tc_intflag_reg_t;
+typedef uint8_t  hri_tc_status_reg_t;
+typedef uint8_t  hri_tc_wave_reg_t;
+typedef uint8_t  hri_tccount8_cc_reg_t;
+typedef uint8_t  hri_tccount8_ccbuf_reg_t;
+typedef uint8_t  hri_tccount8_count_reg_t;
+typedef uint8_t  hri_tccount8_per_reg_t;
+typedef uint8_t  hri_tccount8_perbuf_reg_t;
+
+static inline void hri_tc_wait_for_sync(const void *const hw, hri_tc_syncbusy_reg_t reg)
+{
+	while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_tc_is_syncing(const void *const hw, hri_tc_syncbusy_reg_t reg)
+{
+	return ((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_tc_get_INTFLAG_OVF_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_OVF) >> TC_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_tc_clear_INTFLAG_OVF_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_OVF;
+}
+
+static inline bool hri_tc_get_INTFLAG_ERR_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_ERR) >> TC_INTFLAG_ERR_Pos;
+}
+
+static inline void hri_tc_clear_INTFLAG_ERR_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_ERR;
+}
+
+static inline bool hri_tc_get_INTFLAG_MC0_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC0) >> TC_INTFLAG_MC0_Pos;
+}
+
+static inline void hri_tc_clear_INTFLAG_MC0_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC0;
+}
+
+static inline bool hri_tc_get_INTFLAG_MC1_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC1) >> TC_INTFLAG_MC1_Pos;
+}
+
+static inline void hri_tc_clear_INTFLAG_MC1_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC1;
+}
+
+static inline bool hri_tc_get_interrupt_OVF_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_OVF) >> TC_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_tc_clear_interrupt_OVF_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_OVF;
+}
+
+static inline bool hri_tc_get_interrupt_ERR_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_ERR) >> TC_INTFLAG_ERR_Pos;
+}
+
+static inline void hri_tc_clear_interrupt_ERR_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_ERR;
+}
+
+static inline bool hri_tc_get_interrupt_MC0_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC0) >> TC_INTFLAG_MC0_Pos;
+}
+
+static inline void hri_tc_clear_interrupt_MC0_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC0;
+}
+
+static inline bool hri_tc_get_interrupt_MC1_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC1) >> TC_INTFLAG_MC1_Pos;
+}
+
+static inline void hri_tc_clear_interrupt_MC1_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC1;
+}
+
+static inline hri_tc_intflag_reg_t hri_tc_get_INTFLAG_reg(const void *const hw, hri_tc_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_tc_intflag_reg_t hri_tc_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Tc *)hw)->COUNT16.INTFLAG.reg;
+}
+
+static inline void hri_tc_clear_INTFLAG_reg(const void *const hw, hri_tc_intflag_reg_t mask)
+{
+	((Tc *)hw)->COUNT16.INTFLAG.reg = mask;
+}
+
+static inline void hri_tc_set_CTRLB_DIR_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_DIR;
+}
+
+static inline bool hri_tc_get_CTRLB_DIR_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.CTRLBSET.reg & TC_CTRLBSET_DIR) >> TC_CTRLBSET_DIR_Pos;
+}
+
+static inline void hri_tc_write_CTRLB_DIR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_DIR;
+	} else {
+		((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_DIR;
+	}
+}
+
+static inline void hri_tc_clear_CTRLB_DIR_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_DIR;
+}
+
+static inline void hri_tc_set_CTRLB_LUPD_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_LUPD;
+}
+
+static inline bool hri_tc_get_CTRLB_LUPD_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.CTRLBSET.reg & TC_CTRLBSET_LUPD) >> TC_CTRLBSET_LUPD_Pos;
+}
+
+static inline void hri_tc_write_CTRLB_LUPD_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_LUPD;
+	} else {
+		((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_LUPD;
+	}
+}
+
+static inline void hri_tc_clear_CTRLB_LUPD_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_LUPD;
+}
+
+static inline void hri_tc_set_CTRLB_ONESHOT_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_ONESHOT;
+}
+
+static inline bool hri_tc_get_CTRLB_ONESHOT_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.CTRLBSET.reg & TC_CTRLBSET_ONESHOT) >> TC_CTRLBSET_ONESHOT_Pos;
+}
+
+static inline void hri_tc_write_CTRLB_ONESHOT_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_ONESHOT;
+	} else {
+		((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_ONESHOT;
+	}
+}
+
+static inline void hri_tc_clear_CTRLB_ONESHOT_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_ONESHOT;
+}
+
+static inline void hri_tc_set_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask)
+{
+	((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_CMD(mask);
+}
+
+static inline hri_tc_ctrlbset_reg_t hri_tc_get_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLBSET.reg;
+	tmp = (tmp & TC_CTRLBSET_CMD(mask)) >> TC_CTRLBSET_CMD_Pos;
+	return tmp;
+}
+
+static inline hri_tc_ctrlbset_reg_t hri_tc_read_CTRLB_CMD_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLBSET.reg;
+	tmp = (tmp & TC_CTRLBSET_CMD_Msk) >> TC_CTRLBSET_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_write_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t data)
+{
+	((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_CMD(data);
+	((Tc *)hw)->COUNT16.CTRLBCLR.reg = ~TC_CTRLBSET_CMD(data);
+}
+
+static inline void hri_tc_clear_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask)
+{
+	((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_CMD(mask);
+}
+
+static inline void hri_tc_set_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask)
+{
+	((Tc *)hw)->COUNT16.CTRLBSET.reg = mask;
+}
+
+static inline hri_tc_ctrlbset_reg_t hri_tc_get_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLBSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_tc_ctrlbset_reg_t hri_tc_read_CTRLB_reg(const void *const hw)
+{
+	return ((Tc *)hw)->COUNT16.CTRLBSET.reg;
+}
+
+static inline void hri_tc_write_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t data)
+{
+	((Tc *)hw)->COUNT16.CTRLBSET.reg = data;
+	((Tc *)hw)->COUNT16.CTRLBCLR.reg = ~data;
+}
+
+static inline void hri_tc_clear_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask)
+{
+	((Tc *)hw)->COUNT16.CTRLBCLR.reg = mask;
+}
+
+static inline void hri_tc_set_INTEN_OVF_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_OVF;
+}
+
+static inline bool hri_tc_get_INTEN_OVF_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_OVF) >> TC_INTENSET_OVF_Pos;
+}
+
+static inline void hri_tc_write_INTEN_OVF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_OVF;
+	} else {
+		((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_OVF;
+	}
+}
+
+static inline void hri_tc_clear_INTEN_OVF_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_OVF;
+}
+
+static inline void hri_tc_set_INTEN_ERR_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_ERR;
+}
+
+static inline bool hri_tc_get_INTEN_ERR_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_ERR) >> TC_INTENSET_ERR_Pos;
+}
+
+static inline void hri_tc_write_INTEN_ERR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_ERR;
+	} else {
+		((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_ERR;
+	}
+}
+
+static inline void hri_tc_clear_INTEN_ERR_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_ERR;
+}
+
+static inline void hri_tc_set_INTEN_MC0_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC0;
+}
+
+static inline bool hri_tc_get_INTEN_MC0_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_MC0) >> TC_INTENSET_MC0_Pos;
+}
+
+static inline void hri_tc_write_INTEN_MC0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC0;
+	} else {
+		((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC0;
+	}
+}
+
+static inline void hri_tc_clear_INTEN_MC0_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC0;
+}
+
+static inline void hri_tc_set_INTEN_MC1_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC1;
+}
+
+static inline bool hri_tc_get_INTEN_MC1_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_MC1) >> TC_INTENSET_MC1_Pos;
+}
+
+static inline void hri_tc_write_INTEN_MC1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC1;
+	} else {
+		((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC1;
+	}
+}
+
+static inline void hri_tc_clear_INTEN_MC1_bit(const void *const hw)
+{
+	((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC1;
+}
+
+static inline void hri_tc_set_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask)
+{
+	((Tc *)hw)->COUNT16.INTENSET.reg = mask;
+}
+
+static inline hri_tc_intenset_reg_t hri_tc_get_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_tc_intenset_reg_t hri_tc_read_INTEN_reg(const void *const hw)
+{
+	return ((Tc *)hw)->COUNT16.INTENSET.reg;
+}
+
+static inline void hri_tc_write_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t data)
+{
+	((Tc *)hw)->COUNT16.INTENSET.reg = data;
+	((Tc *)hw)->COUNT16.INTENCLR.reg = ~data;
+}
+
+static inline void hri_tc_clear_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask)
+{
+	((Tc *)hw)->COUNT16.INTENCLR.reg = mask;
+}
+
+static inline bool hri_tc_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_SWRST) >> TC_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_tc_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_ENABLE) >> TC_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_tc_get_SYNCBUSY_CTRLB_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_CTRLB) >> TC_SYNCBUSY_CTRLB_Pos;
+}
+
+static inline bool hri_tc_get_SYNCBUSY_STATUS_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_STATUS) >> TC_SYNCBUSY_STATUS_Pos;
+}
+
+static inline bool hri_tc_get_SYNCBUSY_COUNT_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_COUNT) >> TC_SYNCBUSY_COUNT_Pos;
+}
+
+static inline bool hri_tc_get_SYNCBUSY_PER_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_PER) >> TC_SYNCBUSY_PER_Pos;
+}
+
+static inline bool hri_tc_get_SYNCBUSY_CC0_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_CC0) >> TC_SYNCBUSY_CC0_Pos;
+}
+
+static inline bool hri_tc_get_SYNCBUSY_CC1_bit(const void *const hw)
+{
+	return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_CC1) >> TC_SYNCBUSY_CC1_Pos;
+}
+
+static inline hri_tc_syncbusy_reg_t hri_tc_get_SYNCBUSY_reg(const void *const hw, hri_tc_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_tc_syncbusy_reg_t hri_tc_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Tc *)hw)->COUNT16.SYNCBUSY.reg;
+}
+
+static inline void hri_tc_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_SWRST;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST);
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_SWRST) >> TC_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ENABLE;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_ENABLE) >> TC_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_ENABLE;
+	tmp |= value << TC_CTRLA_ENABLE_Pos;
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ENABLE;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ENABLE;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_RUNSTDBY;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_RUNSTDBY) >> TC_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_RUNSTDBY;
+	tmp |= value << TC_CTRLA_RUNSTDBY_Pos;
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_RUNSTDBY;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_RUNSTDBY;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_CTRLA_ONDEMAND_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ONDEMAND;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_CTRLA_ONDEMAND_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_ONDEMAND) >> TC_CTRLA_ONDEMAND_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_CTRLA_ONDEMAND_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_ONDEMAND;
+	tmp |= value << TC_CTRLA_ONDEMAND_Pos;
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_ONDEMAND_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ONDEMAND;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_ONDEMAND_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ONDEMAND;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_CTRLA_ALOCK_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ALOCK;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_CTRLA_ALOCK_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_ALOCK) >> TC_CTRLA_ALOCK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_CTRLA_ALOCK_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_ALOCK;
+	tmp |= value << TC_CTRLA_ALOCK_Pos;
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_ALOCK_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ALOCK;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_ALOCK_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ALOCK;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_CTRLA_CAPTEN0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTEN0;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_CTRLA_CAPTEN0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_CAPTEN0) >> TC_CTRLA_CAPTEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_CTRLA_CAPTEN0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_CAPTEN0;
+	tmp |= value << TC_CTRLA_CAPTEN0_Pos;
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_CAPTEN0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTEN0;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_CAPTEN0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTEN0;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_CTRLA_CAPTEN1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTEN1;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_CTRLA_CAPTEN1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_CAPTEN1) >> TC_CTRLA_CAPTEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_CTRLA_CAPTEN1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_CAPTEN1;
+	tmp |= value << TC_CTRLA_CAPTEN1_Pos;
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_CAPTEN1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTEN1;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_CAPTEN1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTEN1;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_CTRLA_COPEN0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_COPEN0;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_CTRLA_COPEN0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_COPEN0) >> TC_CTRLA_COPEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_CTRLA_COPEN0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_COPEN0;
+	tmp |= value << TC_CTRLA_COPEN0_Pos;
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_COPEN0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_COPEN0;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_COPEN0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_COPEN0;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_CTRLA_COPEN1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_COPEN1;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_CTRLA_COPEN1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_COPEN1) >> TC_CTRLA_COPEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_CTRLA_COPEN1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_COPEN1;
+	tmp |= value << TC_CTRLA_COPEN1_Pos;
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_COPEN1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_COPEN1;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_COPEN1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_COPEN1;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_MODE(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_MODE(mask)) >> TC_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_write_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_MODE_Msk;
+	tmp |= TC_CTRLA_MODE(data);
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_MODE(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_MODE(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_MODE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_MODE_Msk) >> TC_CTRLA_MODE_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_set_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_PRESCSYNC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_PRESCSYNC(mask)) >> TC_CTRLA_PRESCSYNC_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_write_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_PRESCSYNC_Msk;
+	tmp |= TC_CTRLA_PRESCSYNC(data);
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_PRESCSYNC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_PRESCSYNC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_PRESCSYNC_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_PRESCSYNC_Msk) >> TC_CTRLA_PRESCSYNC_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_PRESCALER(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_PRESCALER(mask)) >> TC_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= ~TC_CTRLA_PRESCALER_Msk;
+	tmp |= TC_CTRLA_PRESCALER(data);
+	((Tc *)hw)->COUNT16.CTRLA.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_PRESCALER(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_PRESCALER(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_PRESCALER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp = (tmp & TC_CTRLA_PRESCALER_Msk) >> TC_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_set_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	tmp = ((Tc *)hw)->COUNT16.CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tc_write_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CTRLA.reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_reg(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE);
+	return ((Tc *)hw)->COUNT16.CTRLA.reg;
+}
+
+static inline void hri_tc_set_EVCTRL_TCINV_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_TCINV;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_EVCTRL_TCINV_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp = (tmp & TC_EVCTRL_TCINV) >> TC_EVCTRL_TCINV_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_EVCTRL_TCINV_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp &= ~TC_EVCTRL_TCINV;
+	tmp |= value << TC_EVCTRL_TCINV_Pos;
+	((Tc *)hw)->COUNT16.EVCTRL.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_EVCTRL_TCINV_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_TCINV;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_EVCTRL_TCINV_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_TCINV;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_EVCTRL_TCEI_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_TCEI;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_EVCTRL_TCEI_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp = (tmp & TC_EVCTRL_TCEI) >> TC_EVCTRL_TCEI_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_EVCTRL_TCEI_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp &= ~TC_EVCTRL_TCEI;
+	tmp |= value << TC_EVCTRL_TCEI_Pos;
+	((Tc *)hw)->COUNT16.EVCTRL.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_EVCTRL_TCEI_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_TCEI;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_EVCTRL_TCEI_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_TCEI;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_OVFEO;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp = (tmp & TC_EVCTRL_OVFEO) >> TC_EVCTRL_OVFEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_EVCTRL_OVFEO_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp &= ~TC_EVCTRL_OVFEO;
+	tmp |= value << TC_EVCTRL_OVFEO_Pos;
+	((Tc *)hw)->COUNT16.EVCTRL.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_OVFEO;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_OVFEO;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_MCEO0;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp = (tmp & TC_EVCTRL_MCEO0) >> TC_EVCTRL_MCEO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_EVCTRL_MCEO0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp &= ~TC_EVCTRL_MCEO0;
+	tmp |= value << TC_EVCTRL_MCEO0_Pos;
+	((Tc *)hw)->COUNT16.EVCTRL.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_MCEO0;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_MCEO0;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_MCEO1;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp = (tmp & TC_EVCTRL_MCEO1) >> TC_EVCTRL_MCEO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_EVCTRL_MCEO1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp &= ~TC_EVCTRL_MCEO1;
+	tmp |= value << TC_EVCTRL_MCEO1_Pos;
+	((Tc *)hw)->COUNT16.EVCTRL.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_MCEO1;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_MCEO1;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_EVACT(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_evctrl_reg_t hri_tc_get_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp = (tmp & TC_EVCTRL_EVACT(mask)) >> TC_EVCTRL_EVACT_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_write_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t data)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp &= ~TC_EVCTRL_EVACT_Msk;
+	tmp |= TC_EVCTRL_EVACT(data);
+	((Tc *)hw)->COUNT16.EVCTRL.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_EVACT(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_EVACT(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_evctrl_reg_t hri_tc_read_EVCTRL_EVACT_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp = (tmp & TC_EVCTRL_EVACT_Msk) >> TC_EVCTRL_EVACT_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_set_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg |= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_evctrl_reg_t hri_tc_get_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tc_write_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg = data;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg &= ~mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.EVCTRL.reg ^= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_evctrl_reg_t hri_tc_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Tc *)hw)->COUNT16.EVCTRL.reg;
+}
+
+static inline void hri_tc_set_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.WAVE.reg |= TC_WAVE_WAVEGEN(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_wave_reg_t hri_tc_get_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.WAVE.reg;
+	tmp = (tmp & TC_WAVE_WAVEGEN(mask)) >> TC_WAVE_WAVEGEN_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_write_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t data)
+{
+	uint8_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.WAVE.reg;
+	tmp &= ~TC_WAVE_WAVEGEN_Msk;
+	tmp |= TC_WAVE_WAVEGEN(data);
+	((Tc *)hw)->COUNT16.WAVE.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.WAVE.reg &= ~TC_WAVE_WAVEGEN(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.WAVE.reg ^= TC_WAVE_WAVEGEN(mask);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_wave_reg_t hri_tc_read_WAVE_WAVEGEN_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.WAVE.reg;
+	tmp = (tmp & TC_WAVE_WAVEGEN_Msk) >> TC_WAVE_WAVEGEN_Pos;
+	return tmp;
+}
+
+static inline void hri_tc_set_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.WAVE.reg |= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_wave_reg_t hri_tc_get_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.WAVE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tc_write_WAVE_reg(const void *const hw, hri_tc_wave_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.WAVE.reg = data;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.WAVE.reg &= ~mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.WAVE.reg ^= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_wave_reg_t hri_tc_read_WAVE_reg(const void *const hw)
+{
+	return ((Tc *)hw)->COUNT16.WAVE.reg;
+}
+
+static inline void hri_tc_set_DRVCTRL_INVEN0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DRVCTRL.reg |= TC_DRVCTRL_INVEN0;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_DRVCTRL_INVEN0_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg;
+	tmp = (tmp & TC_DRVCTRL_INVEN0) >> TC_DRVCTRL_INVEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_DRVCTRL_INVEN0_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg;
+	tmp &= ~TC_DRVCTRL_INVEN0;
+	tmp |= value << TC_DRVCTRL_INVEN0_Pos;
+	((Tc *)hw)->COUNT16.DRVCTRL.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_DRVCTRL_INVEN0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~TC_DRVCTRL_INVEN0;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_DRVCTRL_INVEN0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DRVCTRL.reg ^= TC_DRVCTRL_INVEN0;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_DRVCTRL_INVEN1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DRVCTRL.reg |= TC_DRVCTRL_INVEN1;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_DRVCTRL_INVEN1_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg;
+	tmp = (tmp & TC_DRVCTRL_INVEN1) >> TC_DRVCTRL_INVEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_DRVCTRL_INVEN1_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg;
+	tmp &= ~TC_DRVCTRL_INVEN1;
+	tmp |= value << TC_DRVCTRL_INVEN1_Pos;
+	((Tc *)hw)->COUNT16.DRVCTRL.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_DRVCTRL_INVEN1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~TC_DRVCTRL_INVEN1;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_DRVCTRL_INVEN1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DRVCTRL.reg ^= TC_DRVCTRL_INVEN1;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DRVCTRL.reg |= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_drvctrl_reg_t hri_tc_get_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tc_write_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DRVCTRL.reg = data;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DRVCTRL.reg ^= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_drvctrl_reg_t hri_tc_read_DRVCTRL_reg(const void *const hw)
+{
+	return ((Tc *)hw)->COUNT16.DRVCTRL.reg;
+}
+
+static inline void hri_tc_set_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DBGCTRL.reg |= TC_DBGCTRL_DBGRUN;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.DBGCTRL.reg;
+	tmp = (tmp & TC_DBGCTRL_DBGRUN) >> TC_DBGCTRL_DBGRUN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.DBGCTRL.reg;
+	tmp &= ~TC_DBGCTRL_DBGRUN;
+	tmp |= value << TC_DBGCTRL_DBGRUN_Pos;
+	((Tc *)hw)->COUNT16.DBGCTRL.reg = tmp;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DBGCTRL.reg &= ~TC_DBGCTRL_DBGRUN;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DBGCTRL.reg ^= TC_DBGCTRL_DBGRUN;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_set_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DBGCTRL.reg |= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_dbgctrl_reg_t hri_tc_get_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tc_write_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DBGCTRL.reg = data;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_clear_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DBGCTRL.reg &= ~mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tc_toggle_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.DBGCTRL.reg ^= mask;
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_dbgctrl_reg_t hri_tc_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Tc *)hw)->COUNT16.DBGCTRL.reg;
+}
+
+static inline void hri_tccount8_set_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.COUNT.reg |= TC_COUNT8_COUNT_COUNT(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_count_reg_t hri_tccount8_get_COUNT_COUNT_bf(const void *const        hw,
+                                                                       hri_tccount8_count_reg_t mask)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	tmp = ((Tc *)hw)->COUNT8.COUNT.reg;
+	tmp = (tmp & TC_COUNT8_COUNT_COUNT(mask)) >> TC_COUNT8_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount8_write_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t data)
+{
+	uint8_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT8.COUNT.reg;
+	tmp &= ~TC_COUNT8_COUNT_COUNT_Msk;
+	tmp |= TC_COUNT8_COUNT_COUNT(data);
+	((Tc *)hw)->COUNT8.COUNT.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_clear_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.COUNT.reg &= ~TC_COUNT8_COUNT_COUNT(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_toggle_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.COUNT.reg ^= TC_COUNT8_COUNT_COUNT(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_count_reg_t hri_tccount8_read_COUNT_COUNT_bf(const void *const hw)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	tmp = ((Tc *)hw)->COUNT8.COUNT.reg;
+	tmp = (tmp & TC_COUNT8_COUNT_COUNT_Msk) >> TC_COUNT8_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount8_set_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.COUNT.reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_count_reg_t hri_tccount8_get_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	tmp = ((Tc *)hw)->COUNT8.COUNT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount8_write_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.COUNT.reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_clear_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.COUNT.reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_toggle_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.COUNT.reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_count_reg_t hri_tccount8_read_COUNT_reg(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	return ((Tc *)hw)->COUNT8.COUNT.reg;
+}
+
+static inline void hri_tccount16_set_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.COUNT.reg |= TC_COUNT16_COUNT_COUNT(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_count_reg_t hri_tccount16_get_COUNT_COUNT_bf(const void *const         hw,
+                                                                         hri_tccount16_count_reg_t mask)
+{
+	uint16_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	tmp = ((Tc *)hw)->COUNT16.COUNT.reg;
+	tmp = (tmp & TC_COUNT16_COUNT_COUNT(mask)) >> TC_COUNT16_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount16_write_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t data)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.COUNT.reg;
+	tmp &= ~TC_COUNT16_COUNT_COUNT_Msk;
+	tmp |= TC_COUNT16_COUNT_COUNT(data);
+	((Tc *)hw)->COUNT16.COUNT.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_clear_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.COUNT.reg &= ~TC_COUNT16_COUNT_COUNT(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_toggle_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.COUNT.reg ^= TC_COUNT16_COUNT_COUNT(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_count_reg_t hri_tccount16_read_COUNT_COUNT_bf(const void *const hw)
+{
+	uint16_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	tmp = ((Tc *)hw)->COUNT16.COUNT.reg;
+	tmp = (tmp & TC_COUNT16_COUNT_COUNT_Msk) >> TC_COUNT16_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount16_set_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.COUNT.reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_count_reg_t hri_tccount16_get_COUNT_reg(const void *const         hw,
+                                                                    hri_tccount16_count_reg_t mask)
+{
+	uint16_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	tmp = ((Tc *)hw)->COUNT16.COUNT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount16_write_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.COUNT.reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_clear_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.COUNT.reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_toggle_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.COUNT.reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_count_reg_t hri_tccount16_read_COUNT_reg(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	return ((Tc *)hw)->COUNT16.COUNT.reg;
+}
+
+static inline void hri_tccount32_set_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.COUNT.reg |= TC_COUNT32_COUNT_COUNT(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_count_reg_t hri_tccount32_get_COUNT_COUNT_bf(const void *const         hw,
+                                                                         hri_tccount32_count_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	tmp = ((Tc *)hw)->COUNT32.COUNT.reg;
+	tmp = (tmp & TC_COUNT32_COUNT_COUNT(mask)) >> TC_COUNT32_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount32_write_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t data)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT32.COUNT.reg;
+	tmp &= ~TC_COUNT32_COUNT_COUNT_Msk;
+	tmp |= TC_COUNT32_COUNT_COUNT(data);
+	((Tc *)hw)->COUNT32.COUNT.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_clear_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.COUNT.reg &= ~TC_COUNT32_COUNT_COUNT(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_toggle_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.COUNT.reg ^= TC_COUNT32_COUNT_COUNT(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_count_reg_t hri_tccount32_read_COUNT_COUNT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	tmp = ((Tc *)hw)->COUNT32.COUNT.reg;
+	tmp = (tmp & TC_COUNT32_COUNT_COUNT_Msk) >> TC_COUNT32_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount32_set_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.COUNT.reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_count_reg_t hri_tccount32_get_COUNT_reg(const void *const         hw,
+                                                                    hri_tccount32_count_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	tmp = ((Tc *)hw)->COUNT32.COUNT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount32_write_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.COUNT.reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_clear_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.COUNT.reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_toggle_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.COUNT.reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_count_reg_t hri_tccount32_read_COUNT_reg(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT);
+	return ((Tc *)hw)->COUNT32.COUNT.reg;
+}
+
+static inline void hri_tccount8_set_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PER.reg |= TC_COUNT8_PER_PER(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_per_reg_t hri_tccount8_get_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	tmp = ((Tc *)hw)->COUNT8.PER.reg;
+	tmp = (tmp & TC_COUNT8_PER_PER(mask)) >> TC_COUNT8_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount8_write_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t data)
+{
+	uint8_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT8.PER.reg;
+	tmp &= ~TC_COUNT8_PER_PER_Msk;
+	tmp |= TC_COUNT8_PER_PER(data);
+	((Tc *)hw)->COUNT8.PER.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_clear_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PER.reg &= ~TC_COUNT8_PER_PER(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_toggle_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PER.reg ^= TC_COUNT8_PER_PER(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_per_reg_t hri_tccount8_read_PER_PER_bf(const void *const hw)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	tmp = ((Tc *)hw)->COUNT8.PER.reg;
+	tmp = (tmp & TC_COUNT8_PER_PER_Msk) >> TC_COUNT8_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount8_set_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PER.reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_per_reg_t hri_tccount8_get_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	tmp = ((Tc *)hw)->COUNT8.PER.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount8_write_PER_reg(const void *const hw, hri_tccount8_per_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PER.reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_clear_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PER.reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_toggle_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PER.reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_per_reg_t hri_tccount8_read_PER_reg(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER);
+	return ((Tc *)hw)->COUNT8.PER.reg;
+}
+
+static inline void hri_tccount8_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CC[index].reg |= TC_COUNT8_CC_CC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_cc_reg_t hri_tccount8_get_CC_CC_bf(const void *const hw, uint8_t index,
+                                                              hri_tccount8_cc_reg_t mask)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	tmp = ((Tc *)hw)->COUNT8.CC[index].reg;
+	tmp = (tmp & TC_COUNT8_CC_CC(mask)) >> TC_COUNT8_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount8_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t data)
+{
+	uint8_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT8.CC[index].reg;
+	tmp &= ~TC_COUNT8_CC_CC_Msk;
+	tmp |= TC_COUNT8_CC_CC(data);
+	((Tc *)hw)->COUNT8.CC[index].reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CC[index].reg &= ~TC_COUNT8_CC_CC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CC[index].reg ^= TC_COUNT8_CC_CC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_cc_reg_t hri_tccount8_read_CC_CC_bf(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	tmp = ((Tc *)hw)->COUNT8.CC[index].reg;
+	tmp = (tmp & TC_COUNT8_CC_CC_Msk) >> TC_COUNT8_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount8_set_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CC[index].reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_cc_reg_t hri_tccount8_get_CC_reg(const void *const hw, uint8_t index,
+                                                            hri_tccount8_cc_reg_t mask)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	tmp = ((Tc *)hw)->COUNT8.CC[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount8_write_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CC[index].reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_clear_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CC[index].reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_toggle_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CC[index].reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_cc_reg_t hri_tccount8_read_CC_reg(const void *const hw, uint8_t index)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	return ((Tc *)hw)->COUNT8.CC[index].reg;
+}
+
+static inline void hri_tccount16_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CC[index].reg |= TC_COUNT16_CC_CC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_cc_reg_t hri_tccount16_get_CC_CC_bf(const void *const hw, uint8_t index,
+                                                                hri_tccount16_cc_reg_t mask)
+{
+	uint16_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	tmp = ((Tc *)hw)->COUNT16.CC[index].reg;
+	tmp = (tmp & TC_COUNT16_CC_CC(mask)) >> TC_COUNT16_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount16_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t data)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CC[index].reg;
+	tmp &= ~TC_COUNT16_CC_CC_Msk;
+	tmp |= TC_COUNT16_CC_CC(data);
+	((Tc *)hw)->COUNT16.CC[index].reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CC[index].reg &= ~TC_COUNT16_CC_CC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CC[index].reg ^= TC_COUNT16_CC_CC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_cc_reg_t hri_tccount16_read_CC_CC_bf(const void *const hw, uint8_t index)
+{
+	uint16_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	tmp = ((Tc *)hw)->COUNT16.CC[index].reg;
+	tmp = (tmp & TC_COUNT16_CC_CC_Msk) >> TC_COUNT16_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount16_set_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CC[index].reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_cc_reg_t hri_tccount16_get_CC_reg(const void *const hw, uint8_t index,
+                                                              hri_tccount16_cc_reg_t mask)
+{
+	uint16_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	tmp = ((Tc *)hw)->COUNT16.CC[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount16_write_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CC[index].reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_clear_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CC[index].reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_toggle_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CC[index].reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_cc_reg_t hri_tccount16_read_CC_reg(const void *const hw, uint8_t index)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	return ((Tc *)hw)->COUNT16.CC[index].reg;
+}
+
+static inline void hri_tccount32_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CC[index].reg |= TC_COUNT32_CC_CC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_cc_reg_t hri_tccount32_get_CC_CC_bf(const void *const hw, uint8_t index,
+                                                                hri_tccount32_cc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT32.CC[index].reg;
+	tmp = (tmp & TC_COUNT32_CC_CC(mask)) >> TC_COUNT32_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount32_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t data)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT32.CC[index].reg;
+	tmp &= ~TC_COUNT32_CC_CC_Msk;
+	tmp |= TC_COUNT32_CC_CC(data);
+	((Tc *)hw)->COUNT32.CC[index].reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CC[index].reg &= ~TC_COUNT32_CC_CC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CC[index].reg ^= TC_COUNT32_CC_CC(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_cc_reg_t hri_tccount32_read_CC_CC_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT32.CC[index].reg;
+	tmp = (tmp & TC_COUNT32_CC_CC_Msk) >> TC_COUNT32_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount32_set_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CC[index].reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_cc_reg_t hri_tccount32_get_CC_reg(const void *const hw, uint8_t index,
+                                                              hri_tccount32_cc_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	tmp = ((Tc *)hw)->COUNT32.CC[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount32_write_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CC[index].reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_clear_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CC[index].reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_toggle_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CC[index].reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_cc_reg_t hri_tccount32_read_CC_reg(const void *const hw, uint8_t index)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1);
+	return ((Tc *)hw)->COUNT32.CC[index].reg;
+}
+
+static inline void hri_tccount8_set_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PERBUF.reg |= TC_COUNT8_PERBUF_PERBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_perbuf_reg_t hri_tccount8_get_PERBUF_PERBUF_bf(const void *const         hw,
+                                                                          hri_tccount8_perbuf_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.PERBUF.reg;
+	tmp = (tmp & TC_COUNT8_PERBUF_PERBUF(mask)) >> TC_COUNT8_PERBUF_PERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount8_write_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t data)
+{
+	uint8_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT8.PERBUF.reg;
+	tmp &= ~TC_COUNT8_PERBUF_PERBUF_Msk;
+	tmp |= TC_COUNT8_PERBUF_PERBUF(data);
+	((Tc *)hw)->COUNT8.PERBUF.reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_clear_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PERBUF.reg &= ~TC_COUNT8_PERBUF_PERBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_toggle_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PERBUF.reg ^= TC_COUNT8_PERBUF_PERBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_perbuf_reg_t hri_tccount8_read_PERBUF_PERBUF_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.PERBUF.reg;
+	tmp = (tmp & TC_COUNT8_PERBUF_PERBUF_Msk) >> TC_COUNT8_PERBUF_PERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount8_set_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PERBUF.reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_perbuf_reg_t hri_tccount8_get_PERBUF_reg(const void *const         hw,
+                                                                    hri_tccount8_perbuf_reg_t mask)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	tmp = ((Tc *)hw)->COUNT8.PERBUF.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount8_write_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PERBUF.reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_clear_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PERBUF.reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_toggle_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.PERBUF.reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_perbuf_reg_t hri_tccount8_read_PERBUF_reg(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	return ((Tc *)hw)->COUNT8.PERBUF.reg;
+}
+
+static inline void hri_tccount8_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CCBUF[index].reg |= TC_COUNT8_CCBUF_CCBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_ccbuf_reg_t hri_tccount8_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                                       hri_tccount8_ccbuf_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg;
+	tmp = (tmp & TC_COUNT8_CCBUF_CCBUF(mask)) >> TC_COUNT8_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount8_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t data)
+{
+	uint8_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg;
+	tmp &= ~TC_COUNT8_CCBUF_CCBUF_Msk;
+	tmp |= TC_COUNT8_CCBUF_CCBUF(data);
+	((Tc *)hw)->COUNT8.CCBUF[index].reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CCBUF[index].reg &= ~TC_COUNT8_CCBUF_CCBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                      hri_tccount8_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CCBUF[index].reg ^= TC_COUNT8_CCBUF_CCBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_ccbuf_reg_t hri_tccount8_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index)
+{
+	uint8_t tmp;
+	tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg;
+	tmp = (tmp & TC_COUNT8_CCBUF_CCBUF_Msk) >> TC_COUNT8_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount8_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CCBUF[index].reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_ccbuf_reg_t hri_tccount8_get_CCBUF_reg(const void *const hw, uint8_t index,
+                                                                  hri_tccount8_ccbuf_reg_t mask)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount8_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CCBUF[index].reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CCBUF[index].reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount8_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT8.CCBUF[index].reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount8_ccbuf_reg_t hri_tccount8_read_CCBUF_reg(const void *const hw, uint8_t index)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	return ((Tc *)hw)->COUNT8.CCBUF[index].reg;
+}
+
+static inline void hri_tccount16_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CCBUF[index].reg |= TC_COUNT16_CCBUF_CCBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_ccbuf_reg_t hri_tccount16_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                                         hri_tccount16_ccbuf_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg;
+	tmp = (tmp & TC_COUNT16_CCBUF_CCBUF(mask)) >> TC_COUNT16_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount16_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                      hri_tccount16_ccbuf_reg_t data)
+{
+	uint16_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg;
+	tmp &= ~TC_COUNT16_CCBUF_CCBUF_Msk;
+	tmp |= TC_COUNT16_CCBUF_CCBUF(data);
+	((Tc *)hw)->COUNT16.CCBUF[index].reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                      hri_tccount16_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CCBUF[index].reg &= ~TC_COUNT16_CCBUF_CCBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                       hri_tccount16_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CCBUF[index].reg ^= TC_COUNT16_CCBUF_CCBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_ccbuf_reg_t hri_tccount16_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index)
+{
+	uint16_t tmp;
+	tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg;
+	tmp = (tmp & TC_COUNT16_CCBUF_CCBUF_Msk) >> TC_COUNT16_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount16_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CCBUF[index].reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_ccbuf_reg_t hri_tccount16_get_CCBUF_reg(const void *const hw, uint8_t index,
+                                                                    hri_tccount16_ccbuf_reg_t mask)
+{
+	uint16_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount16_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CCBUF[index].reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CCBUF[index].reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount16_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.CCBUF[index].reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount16_ccbuf_reg_t hri_tccount16_read_CCBUF_reg(const void *const hw, uint8_t index)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	return ((Tc *)hw)->COUNT16.CCBUF[index].reg;
+}
+
+static inline void hri_tccount32_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CCBUF[index].reg |= TC_COUNT32_CCBUF_CCBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_ccbuf_reg_t hri_tccount32_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                                         hri_tccount32_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg;
+	tmp = (tmp & TC_COUNT32_CCBUF_CCBUF(mask)) >> TC_COUNT32_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount32_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                      hri_tccount32_ccbuf_reg_t data)
+{
+	uint32_t tmp;
+	TC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg;
+	tmp &= ~TC_COUNT32_CCBUF_CCBUF_Msk;
+	tmp |= TC_COUNT32_CCBUF_CCBUF(data);
+	((Tc *)hw)->COUNT32.CCBUF[index].reg = tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                      hri_tccount32_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CCBUF[index].reg &= ~TC_COUNT32_CCBUF_CCBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                       hri_tccount32_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CCBUF[index].reg ^= TC_COUNT32_CCBUF_CCBUF(mask);
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_ccbuf_reg_t hri_tccount32_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg;
+	tmp = (tmp & TC_COUNT32_CCBUF_CCBUF_Msk) >> TC_COUNT32_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tccount32_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CCBUF[index].reg |= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_ccbuf_reg_t hri_tccount32_get_CCBUF_reg(const void *const hw, uint8_t index,
+                                                                    hri_tccount32_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tccount32_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t data)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CCBUF[index].reg = data;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CCBUF[index].reg &= ~mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tccount32_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT32.CCBUF[index].reg ^= mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tccount32_ccbuf_reg_t hri_tccount32_read_CCBUF_reg(const void *const hw, uint8_t index)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	return ((Tc *)hw)->COUNT32.CCBUF[index].reg;
+}
+
+static inline bool hri_tc_get_STATUS_STOP_bit(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_STOP) >> TC_STATUS_STOP_Pos;
+}
+
+static inline void hri_tc_clear_STATUS_STOP_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_STOP;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_STATUS_SLAVE_bit(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_SLAVE) >> TC_STATUS_SLAVE_Pos;
+}
+
+static inline void hri_tc_clear_STATUS_SLAVE_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_SLAVE;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_STATUS_PERBUFV_bit(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_PERBUFV) >> TC_STATUS_PERBUFV_Pos;
+}
+
+static inline void hri_tc_clear_STATUS_PERBUFV_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_PERBUFV;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_STATUS_CCBUFV0_bit(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_CCBUFV0) >> TC_STATUS_CCBUFV0_Pos;
+}
+
+static inline void hri_tc_clear_STATUS_CCBUFV0_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_CCBUFV0;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tc_get_STATUS_CCBUFV1_bit(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_CCBUFV1) >> TC_STATUS_CCBUFV1_Pos;
+}
+
+static inline void hri_tc_clear_STATUS_CCBUFV1_bit(const void *const hw)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_CCBUFV1;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_status_reg_t hri_tc_get_STATUS_reg(const void *const hw, hri_tc_status_reg_t mask)
+{
+	uint8_t tmp;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	tmp = ((Tc *)hw)->COUNT16.STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tc_clear_STATUS_reg(const void *const hw, hri_tc_status_reg_t mask)
+{
+	TC_CRITICAL_SECTION_ENTER();
+	((Tc *)hw)->COUNT16.STATUS.reg = mask;
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	TC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tc_status_reg_t hri_tc_read_STATUS_reg(const void *const hw)
+{
+	hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK);
+	return ((Tc *)hw)->COUNT16.STATUS.reg;
+}
+
+/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */
+#define hri_tc_set_PER_PER_bf(a, b) hri_tccount8_set_PER_PER_bf(a, b)
+#define hri_tc_get_PER_PER_bf(a, b) hri_tccount8_get_PER_PER_bf(a, b)
+#define hri_tc_write_PER_PER_bf(a, b) hri_tccount8_write_PER_PER_bf(a, b)
+#define hri_tc_clear_PER_PER_bf(a, b) hri_tccount8_clear_PER_PER_bf(a, b)
+#define hri_tc_toggle_PER_PER_bf(a, b) hri_tccount8_toggle_PER_PER_bf(a, b)
+#define hri_tc_read_PER_PER_bf(a) hri_tccount8_read_PER_PER_bf(a)
+#define hri_tc_set_PER_reg(a, b) hri_tccount8_set_PER_reg(a, b)
+#define hri_tc_get_PER_reg(a, b) hri_tccount8_get_PER_reg(a, b)
+#define hri_tc_write_PER_reg(a, b) hri_tccount8_write_PER_reg(a, b)
+#define hri_tc_clear_PER_reg(a, b) hri_tccount8_clear_PER_reg(a, b)
+#define hri_tc_toggle_PER_reg(a, b) hri_tccount8_toggle_PER_reg(a, b)
+#define hri_tc_read_PER_reg(a) hri_tccount8_read_PER_reg(a)
+#define hri_tc_set_PERBUF_PERBUF_bf(a, b) hri_tccount8_set_PERBUF_PERBUF_bf(a, b)
+#define hri_tc_get_PERBUF_PERBUF_bf(a, b) hri_tccount8_get_PERBUF_PERBUF_bf(a, b)
+#define hri_tc_write_PERBUF_PERBUF_bf(a, b) hri_tccount8_write_PERBUF_PERBUF_bf(a, b)
+#define hri_tc_clear_PERBUF_PERBUF_bf(a, b) hri_tccount8_clear_PERBUF_PERBUF_bf(a, b)
+#define hri_tc_toggle_PERBUF_PERBUF_bf(a, b) hri_tccount8_toggle_PERBUF_PERBUF_bf(a, b)
+#define hri_tc_read_PERBUF_PERBUF_bf(a) hri_tccount8_read_PERBUF_PERBUF_bf(a)
+#define hri_tc_set_PERBUF_reg(a, b) hri_tccount8_set_PERBUF_reg(a, b)
+#define hri_tc_get_PERBUF_reg(a, b) hri_tccount8_get_PERBUF_reg(a, b)
+#define hri_tc_write_PERBUF_reg(a, b) hri_tccount8_write_PERBUF_reg(a, b)
+#define hri_tc_clear_PERBUF_reg(a, b) hri_tccount8_clear_PERBUF_reg(a, b)
+#define hri_tc_toggle_PERBUF_reg(a, b) hri_tccount8_toggle_PERBUF_reg(a, b)
+#define hri_tc_read_PERBUF_reg(a) hri_tccount8_read_PERBUF_reg(a)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_TC_L22_H_INCLUDED */
+#endif /* _SAML22_TC_COMPONENT_ */
diff --git a/watch-library/hardware/hri/hri_tcc_l22.h b/watch-library/hardware/hri/hri_tcc_l22.h
new file mode 100644
index 00000000..c10442af
--- /dev/null
+++ b/watch-library/hardware/hri/hri_tcc_l22.h
@@ -0,0 +1,9462 @@
+/**
+ * \file
+ *
+ * \brief SAM TCC
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_TCC_COMPONENT_
+#ifndef _HRI_TCC_L22_H_INCLUDED_
+#define _HRI_TCC_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_TCC_CRITICAL_SECTIONS)
+#define TCC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define TCC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define TCC_CRITICAL_SECTION_ENTER()
+#define TCC_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_tcc_patt_reg_t;
+typedef uint16_t hri_tcc_pattbuf_reg_t;
+typedef uint32_t hri_tcc_cc_reg_t;
+typedef uint32_t hri_tcc_ccbuf_reg_t;
+typedef uint32_t hri_tcc_count_reg_t;
+typedef uint32_t hri_tcc_ctrla_reg_t;
+typedef uint32_t hri_tcc_drvctrl_reg_t;
+typedef uint32_t hri_tcc_evctrl_reg_t;
+typedef uint32_t hri_tcc_fctrla_reg_t;
+typedef uint32_t hri_tcc_fctrlb_reg_t;
+typedef uint32_t hri_tcc_intenset_reg_t;
+typedef uint32_t hri_tcc_intflag_reg_t;
+typedef uint32_t hri_tcc_per_reg_t;
+typedef uint32_t hri_tcc_perbuf_reg_t;
+typedef uint32_t hri_tcc_status_reg_t;
+typedef uint32_t hri_tcc_syncbusy_reg_t;
+typedef uint32_t hri_tcc_wave_reg_t;
+typedef uint32_t hri_tcc_wexctrl_reg_t;
+typedef uint8_t  hri_tcc_ctrlbset_reg_t;
+typedef uint8_t  hri_tcc_dbgctrl_reg_t;
+
+static inline void hri_tcc_wait_for_sync(const void *const hw, hri_tcc_syncbusy_reg_t reg)
+{
+	while (((Tcc *)hw)->SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_tcc_is_syncing(const void *const hw, hri_tcc_syncbusy_reg_t reg)
+{
+	return ((Tcc *)hw)->SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_tcc_get_INTFLAG_OVF_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_OVF) >> TCC_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_OVF_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_OVF;
+}
+
+static inline bool hri_tcc_get_INTFLAG_TRG_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_TRG) >> TCC_INTFLAG_TRG_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_TRG_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_TRG;
+}
+
+static inline bool hri_tcc_get_INTFLAG_CNT_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_CNT) >> TCC_INTFLAG_CNT_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_CNT_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_CNT;
+}
+
+static inline bool hri_tcc_get_INTFLAG_ERR_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_ERR) >> TCC_INTFLAG_ERR_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_ERR_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_ERR;
+}
+
+static inline bool hri_tcc_get_INTFLAG_UFS_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_UFS) >> TCC_INTFLAG_UFS_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_UFS_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_UFS;
+}
+
+static inline bool hri_tcc_get_INTFLAG_DFS_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_DFS) >> TCC_INTFLAG_DFS_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_DFS_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_DFS;
+}
+
+static inline bool hri_tcc_get_INTFLAG_FAULTA_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTA) >> TCC_INTFLAG_FAULTA_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_FAULTA_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTA;
+}
+
+static inline bool hri_tcc_get_INTFLAG_FAULTB_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTB) >> TCC_INTFLAG_FAULTB_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_FAULTB_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTB;
+}
+
+static inline bool hri_tcc_get_INTFLAG_FAULT0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT0) >> TCC_INTFLAG_FAULT0_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_FAULT0_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT0;
+}
+
+static inline bool hri_tcc_get_INTFLAG_FAULT1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT1) >> TCC_INTFLAG_FAULT1_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_FAULT1_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT1;
+}
+
+static inline bool hri_tcc_get_INTFLAG_MC0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC0) >> TCC_INTFLAG_MC0_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_MC0_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC0;
+}
+
+static inline bool hri_tcc_get_INTFLAG_MC1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC1) >> TCC_INTFLAG_MC1_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_MC1_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC1;
+}
+
+static inline bool hri_tcc_get_INTFLAG_MC2_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC2) >> TCC_INTFLAG_MC2_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_MC2_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC2;
+}
+
+static inline bool hri_tcc_get_INTFLAG_MC3_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC3) >> TCC_INTFLAG_MC3_Pos;
+}
+
+static inline void hri_tcc_clear_INTFLAG_MC3_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC3;
+}
+
+static inline bool hri_tcc_get_interrupt_OVF_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_OVF) >> TCC_INTFLAG_OVF_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_OVF_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_OVF;
+}
+
+static inline bool hri_tcc_get_interrupt_TRG_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_TRG) >> TCC_INTFLAG_TRG_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_TRG_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_TRG;
+}
+
+static inline bool hri_tcc_get_interrupt_CNT_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_CNT) >> TCC_INTFLAG_CNT_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_CNT_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_CNT;
+}
+
+static inline bool hri_tcc_get_interrupt_ERR_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_ERR) >> TCC_INTFLAG_ERR_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_ERR_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_ERR;
+}
+
+static inline bool hri_tcc_get_interrupt_UFS_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_UFS) >> TCC_INTFLAG_UFS_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_UFS_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_UFS;
+}
+
+static inline bool hri_tcc_get_interrupt_DFS_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_DFS) >> TCC_INTFLAG_DFS_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_DFS_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_DFS;
+}
+
+static inline bool hri_tcc_get_interrupt_FAULTA_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTA) >> TCC_INTFLAG_FAULTA_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_FAULTA_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTA;
+}
+
+static inline bool hri_tcc_get_interrupt_FAULTB_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTB) >> TCC_INTFLAG_FAULTB_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_FAULTB_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTB;
+}
+
+static inline bool hri_tcc_get_interrupt_FAULT0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT0) >> TCC_INTFLAG_FAULT0_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_FAULT0_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT0;
+}
+
+static inline bool hri_tcc_get_interrupt_FAULT1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT1) >> TCC_INTFLAG_FAULT1_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_FAULT1_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT1;
+}
+
+static inline bool hri_tcc_get_interrupt_MC0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC0) >> TCC_INTFLAG_MC0_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_MC0_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC0;
+}
+
+static inline bool hri_tcc_get_interrupt_MC1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC1) >> TCC_INTFLAG_MC1_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_MC1_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC1;
+}
+
+static inline bool hri_tcc_get_interrupt_MC2_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC2) >> TCC_INTFLAG_MC2_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_MC2_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC2;
+}
+
+static inline bool hri_tcc_get_interrupt_MC3_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC3) >> TCC_INTFLAG_MC3_Pos;
+}
+
+static inline void hri_tcc_clear_interrupt_MC3_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC3;
+}
+
+static inline hri_tcc_intflag_reg_t hri_tcc_get_INTFLAG_reg(const void *const hw, hri_tcc_intflag_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_tcc_intflag_reg_t hri_tcc_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_tcc_clear_INTFLAG_reg(const void *const hw, hri_tcc_intflag_reg_t mask)
+{
+	((Tcc *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_tcc_set_CTRLB_DIR_bit(const void *const hw)
+{
+	((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_DIR;
+}
+
+static inline bool hri_tcc_get_CTRLB_DIR_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_DIR) >> TCC_CTRLBSET_DIR_Pos;
+}
+
+static inline void hri_tcc_write_CTRLB_DIR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_DIR;
+	} else {
+		((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_DIR;
+	}
+}
+
+static inline void hri_tcc_clear_CTRLB_DIR_bit(const void *const hw)
+{
+	((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_DIR;
+}
+
+static inline void hri_tcc_set_CTRLB_LUPD_bit(const void *const hw)
+{
+	((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_LUPD;
+}
+
+static inline bool hri_tcc_get_CTRLB_LUPD_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_LUPD) >> TCC_CTRLBSET_LUPD_Pos;
+}
+
+static inline void hri_tcc_write_CTRLB_LUPD_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_LUPD;
+	} else {
+		((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_LUPD;
+	}
+}
+
+static inline void hri_tcc_clear_CTRLB_LUPD_bit(const void *const hw)
+{
+	((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_LUPD;
+}
+
+static inline void hri_tcc_set_CTRLB_ONESHOT_bit(const void *const hw)
+{
+	((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_ONESHOT;
+}
+
+static inline bool hri_tcc_get_CTRLB_ONESHOT_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_ONESHOT) >> TCC_CTRLBSET_ONESHOT_Pos;
+}
+
+static inline void hri_tcc_write_CTRLB_ONESHOT_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_ONESHOT;
+	} else {
+		((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_ONESHOT;
+	}
+}
+
+static inline void hri_tcc_clear_CTRLB_ONESHOT_bit(const void *const hw)
+{
+	((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_ONESHOT;
+}
+
+static inline void hri_tcc_set_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
+{
+	((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_IDXCMD(mask);
+}
+
+static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tcc *)hw)->CTRLBSET.reg;
+	tmp = (tmp & TCC_CTRLBSET_IDXCMD(mask)) >> TCC_CTRLBSET_IDXCMD_Pos;
+	return tmp;
+}
+
+static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_IDXCMD_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tcc *)hw)->CTRLBSET.reg;
+	tmp = (tmp & TCC_CTRLBSET_IDXCMD_Msk) >> TCC_CTRLBSET_IDXCMD_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t data)
+{
+	((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_IDXCMD(data);
+	((Tcc *)hw)->CTRLBCLR.reg = ~TCC_CTRLBSET_IDXCMD(data);
+}
+
+static inline void hri_tcc_clear_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
+{
+	((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_IDXCMD(mask);
+}
+
+static inline void hri_tcc_set_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
+{
+	((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_CMD(mask);
+}
+
+static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tcc *)hw)->CTRLBSET.reg;
+	tmp = (tmp & TCC_CTRLBSET_CMD(mask)) >> TCC_CTRLBSET_CMD_Pos;
+	return tmp;
+}
+
+static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_CMD_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tcc *)hw)->CTRLBSET.reg;
+	tmp = (tmp & TCC_CTRLBSET_CMD_Msk) >> TCC_CTRLBSET_CMD_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t data)
+{
+	((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_CMD(data);
+	((Tcc *)hw)->CTRLBCLR.reg = ~TCC_CTRLBSET_CMD(data);
+}
+
+static inline void hri_tcc_clear_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
+{
+	((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_CMD(mask);
+}
+
+static inline void hri_tcc_set_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
+{
+	((Tcc *)hw)->CTRLBSET.reg = mask;
+}
+
+static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tcc *)hw)->CTRLBSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->CTRLBSET.reg;
+}
+
+static inline void hri_tcc_write_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t data)
+{
+	((Tcc *)hw)->CTRLBSET.reg = data;
+	((Tcc *)hw)->CTRLBCLR.reg = ~data;
+}
+
+static inline void hri_tcc_clear_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
+{
+	((Tcc *)hw)->CTRLBCLR.reg = mask;
+}
+
+static inline void hri_tcc_set_INTEN_OVF_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_OVF;
+}
+
+static inline bool hri_tcc_get_INTEN_OVF_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_OVF) >> TCC_INTENSET_OVF_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_OVF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_OVF;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_OVF;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_OVF_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_OVF;
+}
+
+static inline void hri_tcc_set_INTEN_TRG_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_TRG;
+}
+
+static inline bool hri_tcc_get_INTEN_TRG_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_TRG) >> TCC_INTENSET_TRG_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_TRG_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_TRG;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_TRG;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_TRG_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_TRG;
+}
+
+static inline void hri_tcc_set_INTEN_CNT_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_CNT;
+}
+
+static inline bool hri_tcc_get_INTEN_CNT_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_CNT) >> TCC_INTENSET_CNT_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_CNT_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_CNT;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_CNT;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_CNT_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_CNT;
+}
+
+static inline void hri_tcc_set_INTEN_ERR_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_ERR;
+}
+
+static inline bool hri_tcc_get_INTEN_ERR_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_ERR) >> TCC_INTENSET_ERR_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_ERR_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_ERR;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_ERR;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_ERR_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_ERR;
+}
+
+static inline void hri_tcc_set_INTEN_UFS_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_UFS;
+}
+
+static inline bool hri_tcc_get_INTEN_UFS_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_UFS) >> TCC_INTENSET_UFS_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_UFS_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_UFS;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_UFS;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_UFS_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_UFS;
+}
+
+static inline void hri_tcc_set_INTEN_DFS_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_DFS;
+}
+
+static inline bool hri_tcc_get_INTEN_DFS_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_DFS) >> TCC_INTENSET_DFS_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_DFS_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_DFS;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_DFS;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_DFS_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_DFS;
+}
+
+static inline void hri_tcc_set_INTEN_FAULTA_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTA;
+}
+
+static inline bool hri_tcc_get_INTEN_FAULTA_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULTA) >> TCC_INTENSET_FAULTA_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_FAULTA_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTA;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTA;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_FAULTA_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTA;
+}
+
+static inline void hri_tcc_set_INTEN_FAULTB_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTB;
+}
+
+static inline bool hri_tcc_get_INTEN_FAULTB_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULTB) >> TCC_INTENSET_FAULTB_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_FAULTB_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTB;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTB;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_FAULTB_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTB;
+}
+
+static inline void hri_tcc_set_INTEN_FAULT0_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT0;
+}
+
+static inline bool hri_tcc_get_INTEN_FAULT0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULT0) >> TCC_INTENSET_FAULT0_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_FAULT0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT0;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT0;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_FAULT0_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT0;
+}
+
+static inline void hri_tcc_set_INTEN_FAULT1_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT1;
+}
+
+static inline bool hri_tcc_get_INTEN_FAULT1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULT1) >> TCC_INTENSET_FAULT1_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_FAULT1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT1;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT1;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_FAULT1_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT1;
+}
+
+static inline void hri_tcc_set_INTEN_MC0_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC0;
+}
+
+static inline bool hri_tcc_get_INTEN_MC0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC0) >> TCC_INTENSET_MC0_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_MC0_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC0;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC0;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_MC0_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC0;
+}
+
+static inline void hri_tcc_set_INTEN_MC1_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC1;
+}
+
+static inline bool hri_tcc_get_INTEN_MC1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC1) >> TCC_INTENSET_MC1_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_MC1_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC1;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC1;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_MC1_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC1;
+}
+
+static inline void hri_tcc_set_INTEN_MC2_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC2;
+}
+
+static inline bool hri_tcc_get_INTEN_MC2_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC2) >> TCC_INTENSET_MC2_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_MC2_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC2;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC2;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_MC2_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC2;
+}
+
+static inline void hri_tcc_set_INTEN_MC3_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC3;
+}
+
+static inline bool hri_tcc_get_INTEN_MC3_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC3) >> TCC_INTENSET_MC3_Pos;
+}
+
+static inline void hri_tcc_write_INTEN_MC3_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC3;
+	} else {
+		((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC3;
+	}
+}
+
+static inline void hri_tcc_clear_INTEN_MC3_bit(const void *const hw)
+{
+	((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC3;
+}
+
+static inline void hri_tcc_set_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask)
+{
+	((Tcc *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_tcc_intenset_reg_t hri_tcc_get_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_tcc_intenset_reg_t hri_tcc_read_INTEN_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->INTENSET.reg;
+}
+
+static inline void hri_tcc_write_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t data)
+{
+	((Tcc *)hw)->INTENSET.reg = data;
+	((Tcc *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_tcc_clear_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask)
+{
+	((Tcc *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_SWRST) >> TCC_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_ENABLE) >> TCC_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_CTRLB_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) >> TCC_SYNCBUSY_CTRLB_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_STATUS_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_STATUS) >> TCC_SYNCBUSY_STATUS_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_COUNT_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_COUNT) >> TCC_SYNCBUSY_COUNT_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_PATT_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_PATT) >> TCC_SYNCBUSY_PATT_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_WAVE_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_WAVE) >> TCC_SYNCBUSY_WAVE_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_PER_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_PER) >> TCC_SYNCBUSY_PER_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_CC0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC0) >> TCC_SYNCBUSY_CC0_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_CC1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC1) >> TCC_SYNCBUSY_CC1_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_CC2_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC2) >> TCC_SYNCBUSY_CC2_Pos;
+}
+
+static inline bool hri_tcc_get_SYNCBUSY_CC3_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC3) >> TCC_SYNCBUSY_CC3_Pos;
+}
+
+static inline hri_tcc_syncbusy_reg_t hri_tcc_get_SYNCBUSY_reg(const void *const hw, hri_tcc_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_tcc_syncbusy_reg_t hri_tcc_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->SYNCBUSY.reg;
+}
+
+static inline void hri_tcc_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_SWRST;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST);
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_SWRST) >> TCC_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_ENABLE;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_ENABLE) >> TCC_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_ENABLE;
+	tmp |= value << TCC_CTRLA_ENABLE_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_ENABLE;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_ENABLE;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_RUNSTDBY;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_RUNSTDBY) >> TCC_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_RUNSTDBY;
+	tmp |= value << TCC_CTRLA_RUNSTDBY_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_RUNSTDBY;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_RUNSTDBY;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_ALOCK_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_ALOCK;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_ALOCK_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_ALOCK) >> TCC_CTRLA_ALOCK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_ALOCK_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_ALOCK;
+	tmp |= value << TCC_CTRLA_ALOCK_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_ALOCK_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_ALOCK;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_ALOCK_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_ALOCK;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_MSYNC_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_MSYNC;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_MSYNC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_MSYNC) >> TCC_CTRLA_MSYNC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_MSYNC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_MSYNC;
+	tmp |= value << TCC_CTRLA_MSYNC_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_MSYNC_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_MSYNC;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_MSYNC_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_MSYNC;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_DMAOS_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_DMAOS;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_DMAOS_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_DMAOS) >> TCC_CTRLA_DMAOS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_DMAOS_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_DMAOS;
+	tmp |= value << TCC_CTRLA_DMAOS_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_DMAOS_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_DMAOS;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_DMAOS_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_DMAOS;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_CPTEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_CPTEN0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_CPTEN0) >> TCC_CTRLA_CPTEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_CPTEN0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_CPTEN0;
+	tmp |= value << TCC_CTRLA_CPTEN0_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_CPTEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_CPTEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_CPTEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_CPTEN1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_CPTEN1) >> TCC_CTRLA_CPTEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_CPTEN1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_CPTEN1;
+	tmp |= value << TCC_CTRLA_CPTEN1_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_CPTEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_CPTEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_CPTEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_CPTEN2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_CPTEN2) >> TCC_CTRLA_CPTEN2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_CPTEN2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_CPTEN2;
+	tmp |= value << TCC_CTRLA_CPTEN2_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_CPTEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_CPTEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_CPTEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_CTRLA_CPTEN3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_CPTEN3) >> TCC_CTRLA_CPTEN3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_CPTEN3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_CPTEN3;
+	tmp |= value << TCC_CTRLA_CPTEN3_Pos;
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_CPTEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_CPTEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_RESOLUTION(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_RESOLUTION(mask)) >> TCC_CTRLA_RESOLUTION_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_RESOLUTION_Msk;
+	tmp |= TCC_CTRLA_RESOLUTION(data);
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_RESOLUTION(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_RESOLUTION(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_RESOLUTION_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_RESOLUTION_Msk) >> TCC_CTRLA_RESOLUTION_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_PRESCALER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_PRESCALER(mask)) >> TCC_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_PRESCALER_Msk;
+	tmp |= TCC_CTRLA_PRESCALER(data);
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_PRESCALER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_PRESCALER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_PRESCALER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_PRESCALER_Msk) >> TCC_CTRLA_PRESCALER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_PRESCSYNC(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_PRESCSYNC(mask)) >> TCC_CTRLA_PRESCSYNC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= ~TCC_CTRLA_PRESCSYNC_Msk;
+	tmp |= TCC_CTRLA_PRESCSYNC(data);
+	((Tcc *)hw)->CTRLA.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_PRESCSYNC(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_PRESCSYNC(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_PRESCSYNC_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp = (tmp & TCC_CTRLA_PRESCSYNC_Msk) >> TCC_CTRLA_PRESCSYNC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg |= mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	tmp = ((Tcc *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg = data;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg &= ~mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CTRLA.reg ^= mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_reg(const void *const hw)
+{
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
+	return ((Tcc *)hw)->CTRLA.reg;
+}
+
+static inline void hri_tcc_set_FCTRLA_KEEP_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_KEEP;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_FCTRLA_KEEP_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_KEEP) >> TCC_FCTRLA_KEEP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_KEEP_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_KEEP;
+	tmp |= value << TCC_FCTRLA_KEEP_Pos;
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_KEEP_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_KEEP;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_KEEP_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_KEEP;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_FCTRLA_QUAL_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_QUAL;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_FCTRLA_QUAL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_QUAL) >> TCC_FCTRLA_QUAL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_QUAL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_QUAL;
+	tmp |= value << TCC_FCTRLA_QUAL_Pos;
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_QUAL_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_QUAL;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_QUAL_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_QUAL;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_FCTRLA_RESTART_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_RESTART;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_FCTRLA_RESTART_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_RESTART) >> TCC_FCTRLA_RESTART_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_RESTART_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_RESTART;
+	tmp |= value << TCC_FCTRLA_RESTART_Pos;
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_RESTART_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_RESTART;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_RESTART_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_RESTART;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_FCTRLA_BLANKPRESC_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANKPRESC;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_FCTRLA_BLANKPRESC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_BLANKPRESC) >> TCC_FCTRLA_BLANKPRESC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_BLANKPRESC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_BLANKPRESC;
+	tmp |= value << TCC_FCTRLA_BLANKPRESC_Pos;
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_BLANKPRESC_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANKPRESC;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_BLANKPRESC_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANKPRESC;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_SRC(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_SRC(mask)) >> TCC_FCTRLA_SRC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_SRC_Msk;
+	tmp |= TCC_FCTRLA_SRC(data);
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_SRC(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_SRC(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_SRC_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_SRC_Msk) >> TCC_FCTRLA_SRC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANK(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_BLANK(mask)) >> TCC_FCTRLA_BLANK_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_BLANK_Msk;
+	tmp |= TCC_FCTRLA_BLANK(data);
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANK(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANK(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_BLANK_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_BLANK_Msk) >> TCC_FCTRLA_BLANK_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_HALT(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_HALT(mask)) >> TCC_FCTRLA_HALT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_HALT_Msk;
+	tmp |= TCC_FCTRLA_HALT(data);
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_HALT(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_HALT(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_HALT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_HALT_Msk) >> TCC_FCTRLA_HALT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_CHSEL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_CHSEL(mask)) >> TCC_FCTRLA_CHSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_CHSEL_Msk;
+	tmp |= TCC_FCTRLA_CHSEL(data);
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_CHSEL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_CHSEL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_CHSEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_CHSEL_Msk) >> TCC_FCTRLA_CHSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_CAPTURE(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_CAPTURE(mask)) >> TCC_FCTRLA_CAPTURE_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_CAPTURE_Msk;
+	tmp |= TCC_FCTRLA_CAPTURE(data);
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_CAPTURE(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_CAPTURE(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_CAPTURE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_CAPTURE_Msk) >> TCC_FCTRLA_CAPTURE_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANKVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_BLANKVAL(mask)) >> TCC_FCTRLA_BLANKVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_BLANKVAL_Msk;
+	tmp |= TCC_FCTRLA_BLANKVAL(data);
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANKVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANKVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_BLANKVAL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_BLANKVAL_Msk) >> TCC_FCTRLA_BLANKVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_FILTERVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_FILTERVAL(mask)) >> TCC_FCTRLA_FILTERVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= ~TCC_FCTRLA_FILTERVAL_Msk;
+	tmp |= TCC_FCTRLA_FILTERVAL(data);
+	((Tcc *)hw)->FCTRLA.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_FILTERVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_FILTERVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_FILTERVAL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp = (tmp & TCC_FCTRLA_FILTERVAL_Msk) >> TCC_FCTRLA_FILTERVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLA.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->FCTRLA.reg;
+}
+
+static inline void hri_tcc_set_FCTRLB_KEEP_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_KEEP;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_FCTRLB_KEEP_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_KEEP) >> TCC_FCTRLB_KEEP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_KEEP_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_KEEP;
+	tmp |= value << TCC_FCTRLB_KEEP_Pos;
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_KEEP_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_KEEP;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_KEEP_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_KEEP;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_FCTRLB_QUAL_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_QUAL;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_FCTRLB_QUAL_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_QUAL) >> TCC_FCTRLB_QUAL_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_QUAL_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_QUAL;
+	tmp |= value << TCC_FCTRLB_QUAL_Pos;
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_QUAL_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_QUAL;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_QUAL_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_QUAL;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_FCTRLB_RESTART_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_RESTART;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_FCTRLB_RESTART_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_RESTART) >> TCC_FCTRLB_RESTART_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_RESTART_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_RESTART;
+	tmp |= value << TCC_FCTRLB_RESTART_Pos;
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_RESTART_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_RESTART;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_RESTART_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_RESTART;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_FCTRLB_BLANKPRESC_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANKPRESC;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_FCTRLB_BLANKPRESC_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_BLANKPRESC) >> TCC_FCTRLB_BLANKPRESC_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_BLANKPRESC_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_BLANKPRESC;
+	tmp |= value << TCC_FCTRLB_BLANKPRESC_Pos;
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_BLANKPRESC_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANKPRESC;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_BLANKPRESC_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANKPRESC;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_SRC(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_SRC(mask)) >> TCC_FCTRLB_SRC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_SRC_Msk;
+	tmp |= TCC_FCTRLB_SRC(data);
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_SRC(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_SRC(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_SRC_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_SRC_Msk) >> TCC_FCTRLB_SRC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANK(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_BLANK(mask)) >> TCC_FCTRLB_BLANK_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_BLANK_Msk;
+	tmp |= TCC_FCTRLB_BLANK(data);
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANK(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANK(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_BLANK_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_BLANK_Msk) >> TCC_FCTRLB_BLANK_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_HALT(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_HALT(mask)) >> TCC_FCTRLB_HALT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_HALT_Msk;
+	tmp |= TCC_FCTRLB_HALT(data);
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_HALT(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_HALT(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_HALT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_HALT_Msk) >> TCC_FCTRLB_HALT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_CHSEL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_CHSEL(mask)) >> TCC_FCTRLB_CHSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_CHSEL_Msk;
+	tmp |= TCC_FCTRLB_CHSEL(data);
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_CHSEL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_CHSEL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_CHSEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_CHSEL_Msk) >> TCC_FCTRLB_CHSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_CAPTURE(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_CAPTURE(mask)) >> TCC_FCTRLB_CAPTURE_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_CAPTURE_Msk;
+	tmp |= TCC_FCTRLB_CAPTURE(data);
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_CAPTURE(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_CAPTURE(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_CAPTURE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_CAPTURE_Msk) >> TCC_FCTRLB_CAPTURE_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANKVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_BLANKVAL(mask)) >> TCC_FCTRLB_BLANKVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_BLANKVAL_Msk;
+	tmp |= TCC_FCTRLB_BLANKVAL(data);
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANKVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANKVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_BLANKVAL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_BLANKVAL_Msk) >> TCC_FCTRLB_BLANKVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_FILTERVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_FILTERVAL(mask)) >> TCC_FCTRLB_FILTERVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= ~TCC_FCTRLB_FILTERVAL_Msk;
+	tmp |= TCC_FCTRLB_FILTERVAL(data);
+	((Tcc *)hw)->FCTRLB.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_FILTERVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_FILTERVAL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_FILTERVAL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp = (tmp & TCC_FCTRLB_FILTERVAL_Msk) >> TCC_FCTRLB_FILTERVAL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->FCTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->FCTRLB.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->FCTRLB.reg;
+}
+
+static inline void hri_tcc_set_WEXCTRL_DTIEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WEXCTRL_DTIEN0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_DTIEN0) >> TCC_WEXCTRL_DTIEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WEXCTRL_DTIEN0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp &= ~TCC_WEXCTRL_DTIEN0;
+	tmp |= value << TCC_WEXCTRL_DTIEN0_Pos;
+	((Tcc *)hw)->WEXCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WEXCTRL_DTIEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WEXCTRL_DTIEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WEXCTRL_DTIEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WEXCTRL_DTIEN1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_DTIEN1) >> TCC_WEXCTRL_DTIEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WEXCTRL_DTIEN1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp &= ~TCC_WEXCTRL_DTIEN1;
+	tmp |= value << TCC_WEXCTRL_DTIEN1_Pos;
+	((Tcc *)hw)->WEXCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WEXCTRL_DTIEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WEXCTRL_DTIEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WEXCTRL_DTIEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WEXCTRL_DTIEN2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_DTIEN2) >> TCC_WEXCTRL_DTIEN2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WEXCTRL_DTIEN2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp &= ~TCC_WEXCTRL_DTIEN2;
+	tmp |= value << TCC_WEXCTRL_DTIEN2_Pos;
+	((Tcc *)hw)->WEXCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WEXCTRL_DTIEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WEXCTRL_DTIEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WEXCTRL_DTIEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WEXCTRL_DTIEN3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_DTIEN3) >> TCC_WEXCTRL_DTIEN3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WEXCTRL_DTIEN3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp &= ~TCC_WEXCTRL_DTIEN3;
+	tmp |= value << TCC_WEXCTRL_DTIEN3_Pos;
+	((Tcc *)hw)->WEXCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WEXCTRL_DTIEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WEXCTRL_DTIEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_OTMX(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_OTMX(mask)) >> TCC_WEXCTRL_OTMX_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp &= ~TCC_WEXCTRL_OTMX_Msk;
+	tmp |= TCC_WEXCTRL_OTMX(data);
+	((Tcc *)hw)->WEXCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_OTMX(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_OTMX(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_OTMX_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_OTMX_Msk) >> TCC_WEXCTRL_OTMX_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTLS(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_DTLS(mask)) >> TCC_WEXCTRL_DTLS_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp &= ~TCC_WEXCTRL_DTLS_Msk;
+	tmp |= TCC_WEXCTRL_DTLS(data);
+	((Tcc *)hw)->WEXCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTLS(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTLS(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_DTLS_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_DTLS_Msk) >> TCC_WEXCTRL_DTLS_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTHS(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_DTHS(mask)) >> TCC_WEXCTRL_DTHS_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp &= ~TCC_WEXCTRL_DTHS_Msk;
+	tmp |= TCC_WEXCTRL_DTHS(data);
+	((Tcc *)hw)->WEXCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTHS(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTHS(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_DTHS_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp = (tmp & TCC_WEXCTRL_DTHS_Msk) >> TCC_WEXCTRL_DTHS_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WEXCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WEXCTRL.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->WEXCTRL.reg;
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRE0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRE0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRE0) >> TCC_DRVCTRL_NRE0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRE0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRE0;
+	tmp |= value << TCC_DRVCTRL_NRE0_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRE0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRE0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRE1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRE1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRE1) >> TCC_DRVCTRL_NRE1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRE1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRE1;
+	tmp |= value << TCC_DRVCTRL_NRE1_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRE1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRE1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRE2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRE2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRE2) >> TCC_DRVCTRL_NRE2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRE2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRE2;
+	tmp |= value << TCC_DRVCTRL_NRE2_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRE2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRE2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRE3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRE3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRE3) >> TCC_DRVCTRL_NRE3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRE3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRE3;
+	tmp |= value << TCC_DRVCTRL_NRE3_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRE3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRE3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRE4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRE4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRE4) >> TCC_DRVCTRL_NRE4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRE4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRE4;
+	tmp |= value << TCC_DRVCTRL_NRE4_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRE4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRE4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRE5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRE5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRE5) >> TCC_DRVCTRL_NRE5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRE5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRE5;
+	tmp |= value << TCC_DRVCTRL_NRE5_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRE5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRE5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRE6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRE6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRE6) >> TCC_DRVCTRL_NRE6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRE6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRE6;
+	tmp |= value << TCC_DRVCTRL_NRE6_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRE6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRE6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRE7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRE7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRE7) >> TCC_DRVCTRL_NRE7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRE7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRE7;
+	tmp |= value << TCC_DRVCTRL_NRE7_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRE7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRE7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRV0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRV0) >> TCC_DRVCTRL_NRV0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRV0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRV0;
+	tmp |= value << TCC_DRVCTRL_NRV0_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRV1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRV1) >> TCC_DRVCTRL_NRV1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRV1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRV1;
+	tmp |= value << TCC_DRVCTRL_NRV1_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRV2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRV2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRV2) >> TCC_DRVCTRL_NRV2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRV2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRV2;
+	tmp |= value << TCC_DRVCTRL_NRV2_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRV2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRV2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRV3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRV3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRV3) >> TCC_DRVCTRL_NRV3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRV3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRV3;
+	tmp |= value << TCC_DRVCTRL_NRV3_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRV3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRV3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRV4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRV4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRV4) >> TCC_DRVCTRL_NRV4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRV4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRV4;
+	tmp |= value << TCC_DRVCTRL_NRV4_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRV4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRV4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRV5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRV5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRV5) >> TCC_DRVCTRL_NRV5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRV5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRV5;
+	tmp |= value << TCC_DRVCTRL_NRV5_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRV5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRV5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRV6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRV6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRV6) >> TCC_DRVCTRL_NRV6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRV6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRV6;
+	tmp |= value << TCC_DRVCTRL_NRV6_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRV6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRV6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_NRV7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_NRV7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_NRV7) >> TCC_DRVCTRL_NRV7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_NRV7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_NRV7;
+	tmp |= value << TCC_DRVCTRL_NRV7_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_NRV7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_NRV7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_INVEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_INVEN0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_INVEN0) >> TCC_DRVCTRL_INVEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_INVEN0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_INVEN0;
+	tmp |= value << TCC_DRVCTRL_INVEN0_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_INVEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_INVEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_INVEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_INVEN1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_INVEN1) >> TCC_DRVCTRL_INVEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_INVEN1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_INVEN1;
+	tmp |= value << TCC_DRVCTRL_INVEN1_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_INVEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_INVEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_INVEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_INVEN2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_INVEN2) >> TCC_DRVCTRL_INVEN2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_INVEN2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_INVEN2;
+	tmp |= value << TCC_DRVCTRL_INVEN2_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_INVEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_INVEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_INVEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_INVEN3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_INVEN3) >> TCC_DRVCTRL_INVEN3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_INVEN3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_INVEN3;
+	tmp |= value << TCC_DRVCTRL_INVEN3_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_INVEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_INVEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_INVEN4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_INVEN4_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_INVEN4) >> TCC_DRVCTRL_INVEN4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_INVEN4_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_INVEN4;
+	tmp |= value << TCC_DRVCTRL_INVEN4_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_INVEN4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_INVEN4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_INVEN5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_INVEN5_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_INVEN5) >> TCC_DRVCTRL_INVEN5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_INVEN5_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_INVEN5;
+	tmp |= value << TCC_DRVCTRL_INVEN5_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_INVEN5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_INVEN5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_INVEN6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_INVEN6_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_INVEN6) >> TCC_DRVCTRL_INVEN6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_INVEN6_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_INVEN6;
+	tmp |= value << TCC_DRVCTRL_INVEN6_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_INVEN6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_INVEN6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_INVEN7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DRVCTRL_INVEN7_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_INVEN7) >> TCC_DRVCTRL_INVEN7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_INVEN7_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_INVEN7;
+	tmp |= value << TCC_DRVCTRL_INVEN7_Pos;
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_INVEN7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_INVEN7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_FILTERVAL0(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_FILTERVAL0(mask)) >> TCC_DRVCTRL_FILTERVAL0_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_FILTERVAL0_Msk;
+	tmp |= TCC_DRVCTRL_FILTERVAL0(data);
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_FILTERVAL0(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_FILTERVAL0(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_FILTERVAL0_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_FILTERVAL0_Msk) >> TCC_DRVCTRL_FILTERVAL0_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_FILTERVAL1(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_FILTERVAL1(mask)) >> TCC_DRVCTRL_FILTERVAL1_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= ~TCC_DRVCTRL_FILTERVAL1_Msk;
+	tmp |= TCC_DRVCTRL_FILTERVAL1(data);
+	((Tcc *)hw)->DRVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_FILTERVAL1(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_FILTERVAL1(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_FILTERVAL1_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp = (tmp & TCC_DRVCTRL_FILTERVAL1_Msk) >> TCC_DRVCTRL_FILTERVAL1_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->DRVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DRVCTRL.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->DRVCTRL.reg;
+}
+
+static inline void hri_tcc_set_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg |= TCC_DBGCTRL_DBGRUN;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tcc *)hw)->DBGCTRL.reg;
+	tmp = (tmp & TCC_DBGCTRL_DBGRUN) >> TCC_DBGCTRL_DBGRUN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DBGCTRL.reg;
+	tmp &= ~TCC_DBGCTRL_DBGRUN;
+	tmp |= value << TCC_DBGCTRL_DBGRUN_Pos;
+	((Tcc *)hw)->DBGCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg &= ~TCC_DBGCTRL_DBGRUN;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg ^= TCC_DBGCTRL_DBGRUN;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DBGCTRL_FDDBD_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg |= TCC_DBGCTRL_FDDBD;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_DBGCTRL_FDDBD_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Tcc *)hw)->DBGCTRL.reg;
+	tmp = (tmp & TCC_DBGCTRL_FDDBD) >> TCC_DBGCTRL_FDDBD_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_DBGCTRL_FDDBD_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->DBGCTRL.reg;
+	tmp &= ~TCC_DBGCTRL_FDDBD;
+	tmp |= value << TCC_DBGCTRL_FDDBD_Pos;
+	((Tcc *)hw)->DBGCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DBGCTRL_FDDBD_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg &= ~TCC_DBGCTRL_FDDBD;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DBGCTRL_FDDBD_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg ^= TCC_DBGCTRL_FDDBD;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_dbgctrl_reg_t hri_tcc_get_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Tcc *)hw)->DBGCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->DBGCTRL.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_dbgctrl_reg_t hri_tcc_read_DBGCTRL_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->DBGCTRL.reg;
+}
+
+static inline void hri_tcc_set_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_OVFEO;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_OVFEO) >> TCC_EVCTRL_OVFEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_OVFEO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_OVFEO;
+	tmp |= value << TCC_EVCTRL_OVFEO_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_OVFEO;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_OVFEO_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_OVFEO;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_TRGEO_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TRGEO;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_TRGEO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_TRGEO) >> TCC_EVCTRL_TRGEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_TRGEO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_TRGEO;
+	tmp |= value << TCC_EVCTRL_TRGEO_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_TRGEO_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TRGEO;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_TRGEO_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TRGEO;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_CNTEO_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_CNTEO;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_CNTEO_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_CNTEO) >> TCC_EVCTRL_CNTEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_CNTEO_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_CNTEO;
+	tmp |= value << TCC_EVCTRL_CNTEO_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_CNTEO_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_CNTEO;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_CNTEO_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_CNTEO;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_TCINV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCINV0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_TCINV0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_TCINV0) >> TCC_EVCTRL_TCINV0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_TCINV0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_TCINV0;
+	tmp |= value << TCC_EVCTRL_TCINV0_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_TCINV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCINV0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_TCINV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCINV0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_TCINV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCINV1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_TCINV1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_TCINV1) >> TCC_EVCTRL_TCINV1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_TCINV1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_TCINV1;
+	tmp |= value << TCC_EVCTRL_TCINV1_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_TCINV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCINV1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_TCINV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCINV1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_TCEI0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCEI0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_TCEI0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_TCEI0) >> TCC_EVCTRL_TCEI0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_TCEI0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_TCEI0;
+	tmp |= value << TCC_EVCTRL_TCEI0_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_TCEI0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCEI0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_TCEI0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCEI0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_TCEI1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCEI1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_TCEI1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_TCEI1) >> TCC_EVCTRL_TCEI1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_TCEI1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_TCEI1;
+	tmp |= value << TCC_EVCTRL_TCEI1_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_TCEI1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCEI1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_TCEI1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCEI1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEI0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEI0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEI0) >> TCC_EVCTRL_MCEI0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEI0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEI0;
+	tmp |= value << TCC_EVCTRL_MCEI0_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEI0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEI0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEI1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEI1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEI1) >> TCC_EVCTRL_MCEI1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEI1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEI1;
+	tmp |= value << TCC_EVCTRL_MCEI1_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEI1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEI1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEI2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEI2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEI2) >> TCC_EVCTRL_MCEI2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEI2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEI2;
+	tmp |= value << TCC_EVCTRL_MCEI2_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEI2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEI2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEI3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEI3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEI3) >> TCC_EVCTRL_MCEI3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEI3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEI3;
+	tmp |= value << TCC_EVCTRL_MCEI3_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEI3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEI3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEO0) >> TCC_EVCTRL_MCEO0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEO0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEO0;
+	tmp |= value << TCC_EVCTRL_MCEO0_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEO0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEO1) >> TCC_EVCTRL_MCEO1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEO1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEO1;
+	tmp |= value << TCC_EVCTRL_MCEO1_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEO1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEO2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEO2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEO2) >> TCC_EVCTRL_MCEO2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEO2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEO2;
+	tmp |= value << TCC_EVCTRL_MCEO2_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEO2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEO2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_MCEO3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_EVCTRL_MCEO3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_MCEO3) >> TCC_EVCTRL_MCEO3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_MCEO3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_MCEO3;
+	tmp |= value << TCC_EVCTRL_MCEO3_Pos;
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_MCEO3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_MCEO3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_EVACT0(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_EVACT0(mask)) >> TCC_EVCTRL_EVACT0_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_EVACT0_Msk;
+	tmp |= TCC_EVCTRL_EVACT0(data);
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_EVACT0(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_EVACT0(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_EVACT0_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_EVACT0_Msk) >> TCC_EVCTRL_EVACT0_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_EVACT1(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_EVACT1(mask)) >> TCC_EVCTRL_EVACT1_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_EVACT1_Msk;
+	tmp |= TCC_EVCTRL_EVACT1(data);
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_EVACT1(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_EVACT1(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_EVACT1_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_EVACT1_Msk) >> TCC_EVCTRL_EVACT1_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_CNTSEL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_CNTSEL(mask)) >> TCC_EVCTRL_CNTSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= ~TCC_EVCTRL_CNTSEL_Msk;
+	tmp |= TCC_EVCTRL_CNTSEL(data);
+	((Tcc *)hw)->EVCTRL.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_CNTSEL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_CNTSEL(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_CNTSEL_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp = (tmp & TCC_EVCTRL_CNTSEL_Msk) >> TCC_EVCTRL_CNTSEL_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->EVCTRL.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->EVCTRL.reg;
+}
+
+static inline void hri_tcc_set_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp &= ~TCC_COUNT_COUNT_Msk;
+	tmp |= TCC_COUNT_COUNT(data);
+	((Tcc *)hw)->COUNT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH6_COUNT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp &= ~TCC_COUNT_COUNT_Msk;
+	tmp |= TCC_COUNT_COUNT(data);
+	((Tcc *)hw)->COUNT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH5_COUNT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp &= ~TCC_COUNT_COUNT_Msk;
+	tmp |= TCC_COUNT_COUNT(data);
+	((Tcc *)hw)->COUNT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH4_COUNT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp &= ~TCC_COUNT_COUNT_Msk;
+	tmp |= TCC_COUNT_COUNT(data);
+	((Tcc *)hw)->COUNT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_COUNT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg |= mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	tmp = ((Tcc *)hw)->COUNT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_COUNT_reg(const void *const hw, hri_tcc_count_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg = data;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg &= ~mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->COUNT.reg ^= mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_reg(const void *const hw)
+{
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT);
+	return ((Tcc *)hw)->COUNT.reg;
+}
+
+static inline void hri_tcc_set_PATT_PGE0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGE0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGE0) >> TCC_PATT_PGE0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGE0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGE0;
+	tmp |= value << TCC_PATT_PGE0_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGE0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGE0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGE1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGE1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGE1) >> TCC_PATT_PGE1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGE1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGE1;
+	tmp |= value << TCC_PATT_PGE1_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGE1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGE1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGE2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGE2_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGE2) >> TCC_PATT_PGE2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGE2_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGE2;
+	tmp |= value << TCC_PATT_PGE2_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGE2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGE2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGE3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGE3_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGE3) >> TCC_PATT_PGE3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGE3_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGE3;
+	tmp |= value << TCC_PATT_PGE3_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGE3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGE3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGE4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE4;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGE4_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGE4) >> TCC_PATT_PGE4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGE4_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGE4;
+	tmp |= value << TCC_PATT_PGE4_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGE4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE4;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGE4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE4;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGE5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE5;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGE5_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGE5) >> TCC_PATT_PGE5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGE5_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGE5;
+	tmp |= value << TCC_PATT_PGE5_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGE5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE5;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGE5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE5;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGE6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE6;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGE6_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGE6) >> TCC_PATT_PGE6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGE6_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGE6;
+	tmp |= value << TCC_PATT_PGE6_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGE6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE6;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGE6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE6;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGE7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE7;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGE7_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGE7) >> TCC_PATT_PGE7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGE7_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGE7;
+	tmp |= value << TCC_PATT_PGE7_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGE7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE7;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGE7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE7;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGV0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGV0) >> TCC_PATT_PGV0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGV0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGV0;
+	tmp |= value << TCC_PATT_PGV0_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGV1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGV1) >> TCC_PATT_PGV1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGV1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGV1;
+	tmp |= value << TCC_PATT_PGV1_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGV2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGV2_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGV2) >> TCC_PATT_PGV2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGV2_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGV2;
+	tmp |= value << TCC_PATT_PGV2_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGV2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGV2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGV3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGV3_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGV3) >> TCC_PATT_PGV3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGV3_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGV3;
+	tmp |= value << TCC_PATT_PGV3_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGV3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGV3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGV4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV4;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGV4_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGV4) >> TCC_PATT_PGV4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGV4_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGV4;
+	tmp |= value << TCC_PATT_PGV4_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGV4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV4;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGV4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV4;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGV5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV5;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGV5_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGV5) >> TCC_PATT_PGV5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGV5_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGV5;
+	tmp |= value << TCC_PATT_PGV5_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGV5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV5;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGV5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV5;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGV6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV6;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGV6_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGV6) >> TCC_PATT_PGV6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGV6_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGV6;
+	tmp |= value << TCC_PATT_PGV6_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGV6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV6;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGV6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV6;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_PGV7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV7;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATT_PGV7_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp = (tmp & TCC_PATT_PGV7) >> TCC_PATT_PGV7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATT_PGV7_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= ~TCC_PATT_PGV7;
+	tmp |= value << TCC_PATT_PGV7_Pos;
+	((Tcc *)hw)->PATT.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_PGV7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV7;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_PGV7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV7;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg |= mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_patt_reg_t hri_tcc_get_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask)
+{
+	uint16_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	tmp = ((Tcc *)hw)->PATT.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PATT_reg(const void *const hw, hri_tcc_patt_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg = data;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg &= ~mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATT.reg ^= mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_patt_reg_t hri_tcc_read_PATT_reg(const void *const hw)
+{
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	return ((Tcc *)hw)->PATT.reg;
+}
+
+static inline void hri_tcc_set_WAVE_CIPEREN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CIPEREN;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_CIPEREN_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_CIPEREN) >> TCC_WAVE_CIPEREN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_CIPEREN_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_CIPEREN;
+	tmp |= value << TCC_WAVE_CIPEREN_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_CIPEREN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CIPEREN;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_CIPEREN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CIPEREN;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_CICCEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_CICCEN0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_CICCEN0) >> TCC_WAVE_CICCEN0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_CICCEN0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_CICCEN0;
+	tmp |= value << TCC_WAVE_CICCEN0_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_CICCEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_CICCEN0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_CICCEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_CICCEN1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_CICCEN1) >> TCC_WAVE_CICCEN1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_CICCEN1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_CICCEN1;
+	tmp |= value << TCC_WAVE_CICCEN1_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_CICCEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_CICCEN1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_CICCEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_CICCEN2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_CICCEN2) >> TCC_WAVE_CICCEN2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_CICCEN2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_CICCEN2;
+	tmp |= value << TCC_WAVE_CICCEN2_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_CICCEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_CICCEN2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_CICCEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_CICCEN3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_CICCEN3) >> TCC_WAVE_CICCEN3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_CICCEN3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_CICCEN3;
+	tmp |= value << TCC_WAVE_CICCEN3_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_CICCEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_CICCEN3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_POL0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_POL0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_POL0) >> TCC_WAVE_POL0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_POL0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_POL0;
+	tmp |= value << TCC_WAVE_POL0_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_POL0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_POL0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_POL1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_POL1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_POL1) >> TCC_WAVE_POL1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_POL1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_POL1;
+	tmp |= value << TCC_WAVE_POL1_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_POL1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_POL1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_POL2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_POL2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_POL2) >> TCC_WAVE_POL2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_POL2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_POL2;
+	tmp |= value << TCC_WAVE_POL2_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_POL2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_POL2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_POL3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_POL3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_POL3) >> TCC_WAVE_POL3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_POL3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_POL3;
+	tmp |= value << TCC_WAVE_POL3_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_POL3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_POL3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_SWAP0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_SWAP0_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_SWAP0) >> TCC_WAVE_SWAP0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_SWAP0_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_SWAP0;
+	tmp |= value << TCC_WAVE_SWAP0_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_SWAP0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_SWAP0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_SWAP1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_SWAP1_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_SWAP1) >> TCC_WAVE_SWAP1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_SWAP1_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_SWAP1;
+	tmp |= value << TCC_WAVE_SWAP1_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_SWAP1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_SWAP1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_SWAP2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_SWAP2_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_SWAP2) >> TCC_WAVE_SWAP2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_SWAP2_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_SWAP2;
+	tmp |= value << TCC_WAVE_SWAP2_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_SWAP2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_SWAP2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_SWAP3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_WAVE_SWAP3_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_SWAP3) >> TCC_WAVE_SWAP3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_WAVE_SWAP3_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_SWAP3;
+	tmp |= value << TCC_WAVE_SWAP3_Pos;
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_SWAP3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_SWAP3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_WAVEGEN(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_WAVEGEN(mask)) >> TCC_WAVE_WAVEGEN_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_WAVEGEN_Msk;
+	tmp |= TCC_WAVE_WAVEGEN(data);
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_WAVEGEN(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_WAVEGEN(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_WAVEGEN_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_WAVEGEN_Msk) >> TCC_WAVE_WAVEGEN_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= TCC_WAVE_RAMP(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_RAMP(mask)) >> TCC_WAVE_RAMP_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= ~TCC_WAVE_RAMP_Msk;
+	tmp |= TCC_WAVE_RAMP(data);
+	((Tcc *)hw)->WAVE.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_RAMP(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_RAMP(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_RAMP_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp = (tmp & TCC_WAVE_RAMP_Msk) >> TCC_WAVE_RAMP_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg |= mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	tmp = ((Tcc *)hw)->WAVE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg = data;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg &= ~mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->WAVE.reg ^= mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_reg(const void *const hw)
+{
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	return ((Tcc *)hw)->WAVE.reg;
+}
+
+static inline void hri_tcc_set_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg |= TCC_PER_DITH4_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_DITH4_DITHER(mask)) >> TCC_PER_DITH4_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp &= ~TCC_PER_DITH4_DITHER_Msk;
+	tmp |= TCC_PER_DITH4_DITHER(data);
+	((Tcc *)hw)->PER.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH4_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg ^= TCC_PER_DITH4_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH4_DITHER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_DITH4_DITHER_Msk) >> TCC_PER_DITH4_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg |= TCC_PER_DITH5_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_DITH5_DITHER(mask)) >> TCC_PER_DITH5_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp &= ~TCC_PER_DITH5_DITHER_Msk;
+	tmp |= TCC_PER_DITH5_DITHER(data);
+	((Tcc *)hw)->PER.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH5_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg ^= TCC_PER_DITH5_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH5_DITHER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_DITH5_DITHER_Msk) >> TCC_PER_DITH5_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg |= TCC_PER_DITH6_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_DITH6_DITHER(mask)) >> TCC_PER_DITH6_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp &= ~TCC_PER_DITH6_DITHER_Msk;
+	tmp |= TCC_PER_DITH6_DITHER(data);
+	((Tcc *)hw)->PER.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH6_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg ^= TCC_PER_DITH6_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH6_DITHER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_DITH6_DITHER_Msk) >> TCC_PER_DITH6_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp &= ~TCC_PER_PER_Msk;
+	tmp |= TCC_PER_PER(data);
+	((Tcc *)hw)->PER.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH6_PER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp &= ~TCC_PER_PER_Msk;
+	tmp |= TCC_PER_PER(data);
+	((Tcc *)hw)->PER.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH5_PER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp &= ~TCC_PER_PER_Msk;
+	tmp |= TCC_PER_PER(data);
+	((Tcc *)hw)->PER.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH4_PER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_get_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp &= ~TCC_PER_PER_Msk;
+	tmp |= TCC_PER_PER(data);
+	((Tcc *)hw)->PER.reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_read_PER_PER_bf(const void *const hw)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PER_reg(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg |= mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_get_PER_reg(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	tmp = ((Tcc *)hw)->PER.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PER_reg(const void *const hw, hri_tcc_per_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg = data;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PER_reg(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg &= ~mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PER_reg(const void *const hw, hri_tcc_per_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PER.reg ^= mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_per_reg_t hri_tcc_read_PER_reg(const void *const hw)
+{
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER);
+	return ((Tcc *)hw)->PER.reg;
+}
+
+static inline void hri_tcc_set_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH4_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index,
+                                                              hri_tcc_cc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_DITH4_DITHER(mask)) >> TCC_CC_DITH4_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp &= ~TCC_CC_DITH4_DITHER_Msk;
+	tmp |= TCC_CC_DITH4_DITHER(data);
+	((Tcc *)hw)->CC[index].reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH4_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH4_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_DITH4_DITHER_Msk) >> TCC_CC_DITH4_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH5_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index,
+                                                              hri_tcc_cc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_DITH5_DITHER(mask)) >> TCC_CC_DITH5_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp &= ~TCC_CC_DITH5_DITHER_Msk;
+	tmp |= TCC_CC_DITH5_DITHER(data);
+	((Tcc *)hw)->CC[index].reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH5_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH5_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_DITH5_DITHER_Msk) >> TCC_CC_DITH5_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH6_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index,
+                                                              hri_tcc_cc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_DITH6_DITHER(mask)) >> TCC_CC_DITH6_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp &= ~TCC_CC_DITH6_DITHER_Msk;
+	tmp |= TCC_CC_DITH6_DITHER(data);
+	((Tcc *)hw)->CC[index].reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH6_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH6_DITHER(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_DITH6_DITHER_Msk) >> TCC_CC_DITH6_DITHER_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp &= ~TCC_CC_CC_Msk;
+	tmp |= TCC_CC_CC(data);
+	((Tcc *)hw)->CC[index].reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH6_CC_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp &= ~TCC_CC_CC_Msk;
+	tmp |= TCC_CC_CC(data);
+	((Tcc *)hw)->CC[index].reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH5_CC_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp &= ~TCC_CC_CC_Msk;
+	tmp |= TCC_CC_CC(data);
+	((Tcc *)hw)->CC[index].reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH4_CC_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_get_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp &= ~TCC_CC_CC_Msk;
+	tmp |= TCC_CC_CC(data);
+	((Tcc *)hw)->CC[index].reg = tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask);
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_read_CC_CC_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg |= mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_get_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3);
+	tmp = ((Tcc *)hw)->CC[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg = data;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg &= ~mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CC[index].reg ^= mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_cc_reg_t hri_tcc_read_CC_reg(const void *const hw, uint8_t index)
+{
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3);
+	return ((Tcc *)hw)->CC[index].reg;
+}
+
+static inline void hri_tcc_set_PATTBUF_PGEB0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGEB0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGEB0) >> TCC_PATTBUF_PGEB0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGEB0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGEB0;
+	tmp |= value << TCC_PATTBUF_PGEB0_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGEB0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGEB0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGEB1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGEB1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGEB1) >> TCC_PATTBUF_PGEB1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGEB1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGEB1;
+	tmp |= value << TCC_PATTBUF_PGEB1_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGEB1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGEB1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGEB2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGEB2_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGEB2) >> TCC_PATTBUF_PGEB2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGEB2_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGEB2;
+	tmp |= value << TCC_PATTBUF_PGEB2_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGEB2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGEB2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGEB3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGEB3_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGEB3) >> TCC_PATTBUF_PGEB3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGEB3_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGEB3;
+	tmp |= value << TCC_PATTBUF_PGEB3_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGEB3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGEB3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGEB4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGEB4_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGEB4) >> TCC_PATTBUF_PGEB4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGEB4_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGEB4;
+	tmp |= value << TCC_PATTBUF_PGEB4_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGEB4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGEB4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGEB5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGEB5_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGEB5) >> TCC_PATTBUF_PGEB5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGEB5_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGEB5;
+	tmp |= value << TCC_PATTBUF_PGEB5_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGEB5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGEB5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGEB6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGEB6_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGEB6) >> TCC_PATTBUF_PGEB6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGEB6_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGEB6;
+	tmp |= value << TCC_PATTBUF_PGEB6_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGEB6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGEB6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGEB7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGEB7_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGEB7) >> TCC_PATTBUF_PGEB7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGEB7_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGEB7;
+	tmp |= value << TCC_PATTBUF_PGEB7_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGEB7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGEB7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGVB0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGVB0_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGVB0) >> TCC_PATTBUF_PGVB0_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGVB0_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGVB0;
+	tmp |= value << TCC_PATTBUF_PGVB0_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGVB0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGVB0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB0;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGVB1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGVB1_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGVB1) >> TCC_PATTBUF_PGVB1_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGVB1_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGVB1;
+	tmp |= value << TCC_PATTBUF_PGVB1_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGVB1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGVB1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB1;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGVB2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGVB2_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGVB2) >> TCC_PATTBUF_PGVB2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGVB2_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGVB2;
+	tmp |= value << TCC_PATTBUF_PGVB2_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGVB2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGVB2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB2;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGVB3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGVB3_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGVB3) >> TCC_PATTBUF_PGVB3_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGVB3_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGVB3;
+	tmp |= value << TCC_PATTBUF_PGVB3_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGVB3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGVB3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB3;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGVB4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGVB4_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGVB4) >> TCC_PATTBUF_PGVB4_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGVB4_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGVB4;
+	tmp |= value << TCC_PATTBUF_PGVB4_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGVB4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGVB4_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB4;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGVB5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGVB5_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGVB5) >> TCC_PATTBUF_PGVB5_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGVB5_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGVB5;
+	tmp |= value << TCC_PATTBUF_PGVB5_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGVB5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGVB5_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB5;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGVB6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGVB6_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGVB6) >> TCC_PATTBUF_PGVB6_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGVB6_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGVB6;
+	tmp |= value << TCC_PATTBUF_PGVB6_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGVB6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGVB6_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB6;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_PGVB7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_PATTBUF_PGVB7_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp = (tmp & TCC_PATTBUF_PGVB7) >> TCC_PATTBUF_PGVB7_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_PGVB7_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= ~TCC_PATTBUF_PGVB7;
+	tmp |= value << TCC_PATTBUF_PGVB7_Pos;
+	((Tcc *)hw)->PATTBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_PGVB7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_PGVB7_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB7;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_set_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_pattbuf_reg_t hri_tcc_get_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Tcc *)hw)->PATTBUF.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PATTBUF.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_pattbuf_reg_t hri_tcc_read_PATTBUF_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->PATTBUF.reg;
+}
+
+static inline void hri_tcc_set_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH4_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH4_DITHERBUF_bf(const void *const    hw,
+                                                                         hri_tcc_perbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_DITH4_DITHERBUF(mask)) >> TCC_PERBUF_DITH4_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp &= ~TCC_PERBUF_DITH4_DITHERBUF_Msk;
+	tmp |= TCC_PERBUF_DITH4_DITHERBUF(data);
+	((Tcc *)hw)->PERBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH4_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH4_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH4_DITHERBUF_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_DITH4_DITHERBUF_Msk) >> TCC_PERBUF_DITH4_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH5_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH5_DITHERBUF_bf(const void *const    hw,
+                                                                         hri_tcc_perbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_DITH5_DITHERBUF(mask)) >> TCC_PERBUF_DITH5_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp &= ~TCC_PERBUF_DITH5_DITHERBUF_Msk;
+	tmp |= TCC_PERBUF_DITH5_DITHERBUF(data);
+	((Tcc *)hw)->PERBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH5_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH5_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH5_DITHERBUF_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_DITH5_DITHERBUF_Msk) >> TCC_PERBUF_DITH5_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH6_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH6_DITHERBUF_bf(const void *const    hw,
+                                                                         hri_tcc_perbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_DITH6_DITHERBUF(mask)) >> TCC_PERBUF_DITH6_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp &= ~TCC_PERBUF_DITH6_DITHERBUF_Msk;
+	tmp |= TCC_PERBUF_DITH6_DITHERBUF(data);
+	((Tcc *)hw)->PERBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH6_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH6_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH6_DITHERBUF_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_DITH6_DITHERBUF_Msk) >> TCC_PERBUF_DITH6_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp &= ~TCC_PERBUF_PERBUF_Msk;
+	tmp |= TCC_PERBUF_PERBUF(data);
+	((Tcc *)hw)->PERBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH6_PERBUF_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp &= ~TCC_PERBUF_PERBUF_Msk;
+	tmp |= TCC_PERBUF_PERBUF(data);
+	((Tcc *)hw)->PERBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH5_PERBUF_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp &= ~TCC_PERBUF_PERBUF_Msk;
+	tmp |= TCC_PERBUF_PERBUF(data);
+	((Tcc *)hw)->PERBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH4_PERBUF_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp &= ~TCC_PERBUF_PERBUF_Msk;
+	tmp |= TCC_PERBUF_PERBUF(data);
+	((Tcc *)hw)->PERBUF.reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_PERBUF_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->PERBUF.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->PERBUF.reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_reg(const void *const hw)
+{
+	return ((Tcc *)hw)->PERBUF.reg;
+}
+
+static inline void hri_tcc_set_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index,
+                                                                   hri_tcc_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp &= ~TCC_CCBUF_CCBUF_Msk;
+	tmp |= TCC_CCBUF_CCBUF(data);
+	((Tcc *)hw)->CCBUF[index].reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH5_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index,
+                                                                       hri_tcc_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_DITH5_DITHERBUF(mask)) >> TCC_CCBUF_DITH5_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp &= ~TCC_CCBUF_DITH5_DITHERBUF_Msk;
+	tmp |= TCC_CCBUF_DITH5_DITHERBUF(data);
+	((Tcc *)hw)->CCBUF[index].reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH5_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index,
+                                                           hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH5_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_DITH5_DITHERBUF_Msk) >> TCC_CCBUF_DITH5_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH6_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index,
+                                                                       hri_tcc_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_DITH6_DITHERBUF(mask)) >> TCC_CCBUF_DITH6_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp &= ~TCC_CCBUF_DITH6_DITHERBUF_Msk;
+	tmp |= TCC_CCBUF_DITH6_DITHERBUF(data);
+	((Tcc *)hw)->CCBUF[index].reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH6_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index,
+                                                           hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH6_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_DITH6_DITHERBUF_Msk) >> TCC_CCBUF_DITH6_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index,
+                                                                   hri_tcc_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp &= ~TCC_CCBUF_CCBUF_Msk;
+	tmp |= TCC_CCBUF_CCBUF(data);
+	((Tcc *)hw)->CCBUF[index].reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index,
+                                                                   hri_tcc_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp &= ~TCC_CCBUF_CCBUF_Msk;
+	tmp |= TCC_CCBUF_CCBUF(data);
+	((Tcc *)hw)->CCBUF[index].reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH4_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index,
+                                                                       hri_tcc_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_DITH4_DITHERBUF(mask)) >> TCC_CCBUF_DITH4_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp &= ~TCC_CCBUF_DITH4_DITHERBUF_Msk;
+	tmp |= TCC_CCBUF_DITH4_DITHERBUF(data);
+	((Tcc *)hw)->CCBUF[index].reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH4_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index,
+                                                           hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH4_DITHERBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_DITH4_DITHERBUF_Msk) >> TCC_CCBUF_DITH4_DITHERBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
+                                                             hri_tcc_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data)
+{
+	uint32_t tmp;
+	TCC_CRITICAL_SECTION_ENTER();
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp &= ~TCC_CCBUF_CCBUF_Msk;
+	tmp |= TCC_CCBUF_CCBUF(data);
+	((Tcc *)hw)->CCBUF[index].reg = tmp;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos;
+	return tmp;
+}
+
+static inline void hri_tcc_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg |= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Tcc *)hw)->CCBUF[index].reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg = data;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg &= ~mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_tcc_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->CCBUF[index].reg ^= mask;
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_reg(const void *const hw, uint8_t index)
+{
+	return ((Tcc *)hw)->CCBUF[index].reg;
+}
+
+static inline bool hri_tcc_get_STATUS_STOP_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_STOP) >> TCC_STATUS_STOP_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_STOP_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_STOP;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_IDX_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_IDX) >> TCC_STATUS_IDX_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_IDX_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_IDX;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_UFS_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_UFS) >> TCC_STATUS_UFS_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_UFS_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_UFS;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_DFS_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_DFS) >> TCC_STATUS_DFS_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_DFS_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_DFS;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_SLAVE_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_SLAVE) >> TCC_STATUS_SLAVE_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_SLAVE_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_SLAVE;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_PATTBUFV_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_PATTBUFV) >> TCC_STATUS_PATTBUFV_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_PATTBUFV_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_PATTBUFV;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_PERBUFV_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_PERBUFV) >> TCC_STATUS_PERBUFV_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_PERBUFV_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_PERBUFV;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_FAULTAIN_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTAIN) >> TCC_STATUS_FAULTAIN_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_FAULTAIN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTAIN;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_FAULTBIN_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTBIN) >> TCC_STATUS_FAULTBIN_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_FAULTBIN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTBIN;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_FAULT0IN_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT0IN) >> TCC_STATUS_FAULT0IN_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_FAULT0IN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT0IN;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_FAULT1IN_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT1IN) >> TCC_STATUS_FAULT1IN_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_FAULT1IN_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT1IN;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_FAULTA_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTA) >> TCC_STATUS_FAULTA_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_FAULTA_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTA;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_FAULTB_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTB) >> TCC_STATUS_FAULTB_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_FAULTB_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTB;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_FAULT0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT0) >> TCC_STATUS_FAULT0_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_FAULT0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_FAULT1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT1) >> TCC_STATUS_FAULT1_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_FAULT1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CCBUFV0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV0) >> TCC_STATUS_CCBUFV0_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CCBUFV0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CCBUFV1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV1) >> TCC_STATUS_CCBUFV1_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CCBUFV1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CCBUFV2_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV2) >> TCC_STATUS_CCBUFV2_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CCBUFV2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CCBUFV3_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV3) >> TCC_STATUS_CCBUFV3_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CCBUFV3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CMP0_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP0) >> TCC_STATUS_CMP0_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CMP0_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP0;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CMP1_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP1) >> TCC_STATUS_CMP1_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CMP1_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP1;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CMP2_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP2) >> TCC_STATUS_CMP2_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CMP2_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP2;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_tcc_get_STATUS_CMP3_bit(const void *const hw)
+{
+	return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP3) >> TCC_STATUS_CMP3_Pos;
+}
+
+static inline void hri_tcc_clear_STATUS_CMP3_bit(const void *const hw)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP3;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_status_reg_t hri_tcc_get_STATUS_reg(const void *const hw, hri_tcc_status_reg_t mask)
+{
+	uint32_t tmp;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	tmp = ((Tcc *)hw)->STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_tcc_clear_STATUS_reg(const void *const hw, hri_tcc_status_reg_t mask)
+{
+	TCC_CRITICAL_SECTION_ENTER();
+	((Tcc *)hw)->STATUS.reg = mask;
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	TCC_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_tcc_status_reg_t hri_tcc_read_STATUS_reg(const void *const hw)
+{
+	hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
+	return ((Tcc *)hw)->STATUS.reg;
+}
+
+/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */
+#define hri_tcc_set_COUNT_DITH4_reg(a, b) hri_tcc_set_COUNT_reg(a, b)
+#define hri_tcc_get_COUNT_DITH4_reg(a, b) hri_tcc_get_COUNT_reg(a, b)
+#define hri_tcc_write_COUNT_DITH4_reg(a, b) hri_tcc_write_COUNT_reg(a, b)
+#define hri_tcc_clear_COUNT_DITH4_reg(a, b) hri_tcc_clear_COUNT_reg(a, b)
+#define hri_tcc_toggle_COUNT_DITH4_reg(a, b) hri_tcc_toggle_COUNT_reg(a, b)
+#define hri_tcc_read_COUNT_DITH4_reg(a) hri_tcc_read_COUNT_reg(a)
+#define hri_tcc_set_COUNT_DITH5_reg(a, b) hri_tcc_set_COUNT_reg(a, b)
+#define hri_tcc_get_COUNT_DITH5_reg(a, b) hri_tcc_get_COUNT_reg(a, b)
+#define hri_tcc_write_COUNT_DITH5_reg(a, b) hri_tcc_write_COUNT_reg(a, b)
+#define hri_tcc_clear_COUNT_DITH5_reg(a, b) hri_tcc_clear_COUNT_reg(a, b)
+#define hri_tcc_toggle_COUNT_DITH5_reg(a, b) hri_tcc_toggle_COUNT_reg(a, b)
+#define hri_tcc_read_COUNT_DITH5_reg(a) hri_tcc_read_COUNT_reg(a)
+#define hri_tcc_set_COUNT_DITH6_reg(a, b) hri_tcc_set_COUNT_reg(a, b)
+#define hri_tcc_get_COUNT_DITH6_reg(a, b) hri_tcc_get_COUNT_reg(a, b)
+#define hri_tcc_write_COUNT_DITH6_reg(a, b) hri_tcc_write_COUNT_reg(a, b)
+#define hri_tcc_clear_COUNT_DITH6_reg(a, b) hri_tcc_clear_COUNT_reg(a, b)
+#define hri_tcc_toggle_COUNT_DITH6_reg(a, b) hri_tcc_toggle_COUNT_reg(a, b)
+#define hri_tcc_read_COUNT_DITH6_reg(a) hri_tcc_read_COUNT_reg(a)
+#define hri_tcc_set_PER_DITH4_reg(a, b) hri_tcc_set_PER_reg(a, b)
+#define hri_tcc_get_PER_DITH4_reg(a, b) hri_tcc_get_PER_reg(a, b)
+#define hri_tcc_write_PER_DITH4_reg(a, b) hri_tcc_write_PER_reg(a, b)
+#define hri_tcc_clear_PER_DITH4_reg(a, b) hri_tcc_clear_PER_reg(a, b)
+#define hri_tcc_toggle_PER_DITH4_reg(a, b) hri_tcc_toggle_PER_reg(a, b)
+#define hri_tcc_read_PER_DITH4_reg(a) hri_tcc_read_PER_reg(a)
+#define hri_tcc_set_PER_DITH5_reg(a, b) hri_tcc_set_PER_reg(a, b)
+#define hri_tcc_get_PER_DITH5_reg(a, b) hri_tcc_get_PER_reg(a, b)
+#define hri_tcc_write_PER_DITH5_reg(a, b) hri_tcc_write_PER_reg(a, b)
+#define hri_tcc_clear_PER_DITH5_reg(a, b) hri_tcc_clear_PER_reg(a, b)
+#define hri_tcc_toggle_PER_DITH5_reg(a, b) hri_tcc_toggle_PER_reg(a, b)
+#define hri_tcc_read_PER_DITH5_reg(a) hri_tcc_read_PER_reg(a)
+#define hri_tcc_set_PER_DITH6_reg(a, b) hri_tcc_set_PER_reg(a, b)
+#define hri_tcc_get_PER_DITH6_reg(a, b) hri_tcc_get_PER_reg(a, b)
+#define hri_tcc_write_PER_DITH6_reg(a, b) hri_tcc_write_PER_reg(a, b)
+#define hri_tcc_clear_PER_DITH6_reg(a, b) hri_tcc_clear_PER_reg(a, b)
+#define hri_tcc_toggle_PER_DITH6_reg(a, b) hri_tcc_toggle_PER_reg(a, b)
+#define hri_tcc_read_PER_DITH6_reg(a) hri_tcc_read_PER_reg(a)
+#define hri_tcc_set_CC_DITH4_reg(a, b, c) hri_tcc_set_CC_reg(a, b, c)
+#define hri_tcc_get_CC_DITH4_reg(a, b, c) hri_tcc_get_CC_reg(a, b, c)
+#define hri_tcc_write_CC_DITH4_reg(a, b, c) hri_tcc_write_CC_reg(a, b, c)
+#define hri_tcc_clear_CC_DITH4_reg(a, b, c) hri_tcc_clear_CC_reg(a, b, c)
+#define hri_tcc_toggle_CC_DITH4_reg(a, b, c) hri_tcc_toggle_CC_reg(a, b, c)
+#define hri_tcc_read_CC_DITH4_reg(a, b) hri_tcc_read_CC_reg(a, b)
+#define hri_tcc_set_CC_DITH5_reg(a, b, c) hri_tcc_set_CC_reg(a, b, c)
+#define hri_tcc_get_CC_DITH5_reg(a, b, c) hri_tcc_get_CC_reg(a, b, c)
+#define hri_tcc_write_CC_DITH5_reg(a, b, c) hri_tcc_write_CC_reg(a, b, c)
+#define hri_tcc_clear_CC_DITH5_reg(a, b, c) hri_tcc_clear_CC_reg(a, b, c)
+#define hri_tcc_toggle_CC_DITH5_reg(a, b, c) hri_tcc_toggle_CC_reg(a, b, c)
+#define hri_tcc_read_CC_DITH5_reg(a, b) hri_tcc_read_CC_reg(a, b)
+#define hri_tcc_set_CC_DITH6_reg(a, b, c) hri_tcc_set_CC_reg(a, b, c)
+#define hri_tcc_get_CC_DITH6_reg(a, b, c) hri_tcc_get_CC_reg(a, b, c)
+#define hri_tcc_write_CC_DITH6_reg(a, b, c) hri_tcc_write_CC_reg(a, b, c)
+#define hri_tcc_clear_CC_DITH6_reg(a, b, c) hri_tcc_clear_CC_reg(a, b, c)
+#define hri_tcc_toggle_CC_DITH6_reg(a, b, c) hri_tcc_toggle_CC_reg(a, b, c)
+#define hri_tcc_read_CC_DITH6_reg(a, b) hri_tcc_read_CC_reg(a, b)
+#define hri_tcc_set_PERBUF_DITH4_reg(a, b) hri_tcc_set_PERBUF_reg(a, b)
+#define hri_tcc_get_PERBUF_DITH4_reg(a, b) hri_tcc_get_PERBUF_reg(a, b)
+#define hri_tcc_write_PERBUF_DITH4_reg(a, b) hri_tcc_write_PERBUF_reg(a, b)
+#define hri_tcc_clear_PERBUF_DITH4_reg(a, b) hri_tcc_clear_PERBUF_reg(a, b)
+#define hri_tcc_toggle_PERBUF_DITH4_reg(a, b) hri_tcc_toggle_PERBUF_reg(a, b)
+#define hri_tcc_read_PERBUF_DITH4_reg(a) hri_tcc_read_PERBUF_reg(a)
+#define hri_tcc_set_PERBUF_DITH5_reg(a, b) hri_tcc_set_PERBUF_reg(a, b)
+#define hri_tcc_get_PERBUF_DITH5_reg(a, b) hri_tcc_get_PERBUF_reg(a, b)
+#define hri_tcc_write_PERBUF_DITH5_reg(a, b) hri_tcc_write_PERBUF_reg(a, b)
+#define hri_tcc_clear_PERBUF_DITH5_reg(a, b) hri_tcc_clear_PERBUF_reg(a, b)
+#define hri_tcc_toggle_PERBUF_DITH5_reg(a, b) hri_tcc_toggle_PERBUF_reg(a, b)
+#define hri_tcc_read_PERBUF_DITH5_reg(a) hri_tcc_read_PERBUF_reg(a)
+#define hri_tcc_set_PERBUF_DITH6_reg(a, b) hri_tcc_set_PERBUF_reg(a, b)
+#define hri_tcc_get_PERBUF_DITH6_reg(a, b) hri_tcc_get_PERBUF_reg(a, b)
+#define hri_tcc_write_PERBUF_DITH6_reg(a, b) hri_tcc_write_PERBUF_reg(a, b)
+#define hri_tcc_clear_PERBUF_DITH6_reg(a, b) hri_tcc_clear_PERBUF_reg(a, b)
+#define hri_tcc_toggle_PERBUF_DITH6_reg(a, b) hri_tcc_toggle_PERBUF_reg(a, b)
+#define hri_tcc_read_PERBUF_DITH6_reg(a) hri_tcc_read_PERBUF_reg(a)
+#define hri_tcc_set_CCBUF_DITH4_reg(a, b, c) hri_tcc_set_CCBUF_reg(a, b, c)
+#define hri_tcc_get_CCBUF_DITH4_reg(a, b, c) hri_tcc_get_CCBUF_reg(a, b, c)
+#define hri_tcc_write_CCBUF_DITH4_reg(a, b, c) hri_tcc_write_CCBUF_reg(a, b, c)
+#define hri_tcc_clear_CCBUF_DITH4_reg(a, b, c) hri_tcc_clear_CCBUF_reg(a, b, c)
+#define hri_tcc_toggle_CCBUF_DITH4_reg(a, b, c) hri_tcc_toggle_CCBUF_reg(a, b, c)
+#define hri_tcc_read_CCBUF_DITH4_reg(a, b) hri_tcc_read_CCBUF_reg(a, b)
+#define hri_tcc_set_CCBUF_DITH5_reg(a, b, c) hri_tcc_set_CCBUF_reg(a, b, c)
+#define hri_tcc_get_CCBUF_DITH5_reg(a, b, c) hri_tcc_get_CCBUF_reg(a, b, c)
+#define hri_tcc_write_CCBUF_DITH5_reg(a, b, c) hri_tcc_write_CCBUF_reg(a, b, c)
+#define hri_tcc_clear_CCBUF_DITH5_reg(a, b, c) hri_tcc_clear_CCBUF_reg(a, b, c)
+#define hri_tcc_toggle_CCBUF_DITH5_reg(a, b, c) hri_tcc_toggle_CCBUF_reg(a, b, c)
+#define hri_tcc_read_CCBUF_DITH5_reg(a, b) hri_tcc_read_CCBUF_reg(a, b)
+#define hri_tcc_set_CCBUF_DITH6_reg(a, b, c) hri_tcc_set_CCBUF_reg(a, b, c)
+#define hri_tcc_get_CCBUF_DITH6_reg(a, b, c) hri_tcc_get_CCBUF_reg(a, b, c)
+#define hri_tcc_write_CCBUF_DITH6_reg(a, b, c) hri_tcc_write_CCBUF_reg(a, b, c)
+#define hri_tcc_clear_CCBUF_DITH6_reg(a, b, c) hri_tcc_clear_CCBUF_reg(a, b, c)
+#define hri_tcc_toggle_CCBUF_DITH6_reg(a, b, c) hri_tcc_toggle_CCBUF_reg(a, b, c)
+#define hri_tcc_read_CCBUF_DITH6_reg(a, b) hri_tcc_read_CCBUF_reg(a, b)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_TCC_L22_H_INCLUDED */
+#endif /* _SAML22_TCC_COMPONENT_ */
diff --git a/watch-library/hardware/hri/hri_trng_l22.h b/watch-library/hardware/hri/hri_trng_l22.h
new file mode 100644
index 00000000..8aad3aca
--- /dev/null
+++ b/watch-library/hardware/hri/hri_trng_l22.h
@@ -0,0 +1,380 @@
+/**
+ * \file
+ *
+ * \brief SAM TRNG
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_TRNG_COMPONENT_
+#ifndef _HRI_TRNG_L22_H_INCLUDED_
+#define _HRI_TRNG_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_TRNG_CRITICAL_SECTIONS)
+#define TRNG_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define TRNG_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define TRNG_CRITICAL_SECTION_ENTER()
+#define TRNG_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_trng_data_reg_t;
+typedef uint8_t  hri_trng_ctrla_reg_t;
+typedef uint8_t  hri_trng_evctrl_reg_t;
+typedef uint8_t  hri_trng_intenset_reg_t;
+typedef uint8_t  hri_trng_intflag_reg_t;
+
+static inline bool hri_trng_get_INTFLAG_DATARDY_bit(const void *const hw)
+{
+	return (((Trng *)hw)->INTFLAG.reg & TRNG_INTFLAG_DATARDY) >> TRNG_INTFLAG_DATARDY_Pos;
+}
+
+static inline void hri_trng_clear_INTFLAG_DATARDY_bit(const void *const hw)
+{
+	((Trng *)hw)->INTFLAG.reg = TRNG_INTFLAG_DATARDY;
+}
+
+static inline bool hri_trng_get_interrupt_DATARDY_bit(const void *const hw)
+{
+	return (((Trng *)hw)->INTFLAG.reg & TRNG_INTFLAG_DATARDY) >> TRNG_INTFLAG_DATARDY_Pos;
+}
+
+static inline void hri_trng_clear_interrupt_DATARDY_bit(const void *const hw)
+{
+	((Trng *)hw)->INTFLAG.reg = TRNG_INTFLAG_DATARDY;
+}
+
+static inline hri_trng_intflag_reg_t hri_trng_get_INTFLAG_reg(const void *const hw, hri_trng_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Trng *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_trng_intflag_reg_t hri_trng_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Trng *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_trng_clear_INTFLAG_reg(const void *const hw, hri_trng_intflag_reg_t mask)
+{
+	((Trng *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_trng_set_INTEN_DATARDY_bit(const void *const hw)
+{
+	((Trng *)hw)->INTENSET.reg = TRNG_INTENSET_DATARDY;
+}
+
+static inline bool hri_trng_get_INTEN_DATARDY_bit(const void *const hw)
+{
+	return (((Trng *)hw)->INTENSET.reg & TRNG_INTENSET_DATARDY) >> TRNG_INTENSET_DATARDY_Pos;
+}
+
+static inline void hri_trng_write_INTEN_DATARDY_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Trng *)hw)->INTENCLR.reg = TRNG_INTENSET_DATARDY;
+	} else {
+		((Trng *)hw)->INTENSET.reg = TRNG_INTENSET_DATARDY;
+	}
+}
+
+static inline void hri_trng_clear_INTEN_DATARDY_bit(const void *const hw)
+{
+	((Trng *)hw)->INTENCLR.reg = TRNG_INTENSET_DATARDY;
+}
+
+static inline void hri_trng_set_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t mask)
+{
+	((Trng *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_trng_intenset_reg_t hri_trng_get_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Trng *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_trng_intenset_reg_t hri_trng_read_INTEN_reg(const void *const hw)
+{
+	return ((Trng *)hw)->INTENSET.reg;
+}
+
+static inline void hri_trng_write_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t data)
+{
+	((Trng *)hw)->INTENSET.reg = data;
+	((Trng *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_trng_clear_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t mask)
+{
+	((Trng *)hw)->INTENCLR.reg = mask;
+}
+
+static inline hri_trng_data_reg_t hri_trng_get_DATA_DATA_bf(const void *const hw, hri_trng_data_reg_t mask)
+{
+	return (((Trng *)hw)->DATA.reg & TRNG_DATA_DATA(mask)) >> TRNG_DATA_DATA_Pos;
+}
+
+static inline hri_trng_data_reg_t hri_trng_read_DATA_DATA_bf(const void *const hw)
+{
+	return (((Trng *)hw)->DATA.reg & TRNG_DATA_DATA_Msk) >> TRNG_DATA_DATA_Pos;
+}
+
+static inline hri_trng_data_reg_t hri_trng_get_DATA_reg(const void *const hw, hri_trng_data_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Trng *)hw)->DATA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_trng_data_reg_t hri_trng_read_DATA_reg(const void *const hw)
+{
+	return ((Trng *)hw)->DATA.reg;
+}
+
+static inline void hri_trng_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->CTRLA.reg |= TRNG_CTRLA_ENABLE;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_trng_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Trng *)hw)->CTRLA.reg;
+	tmp = (tmp & TRNG_CTRLA_ENABLE) >> TRNG_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_trng_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	TRNG_CRITICAL_SECTION_ENTER();
+	tmp = ((Trng *)hw)->CTRLA.reg;
+	tmp &= ~TRNG_CTRLA_ENABLE;
+	tmp |= value << TRNG_CTRLA_ENABLE_Pos;
+	((Trng *)hw)->CTRLA.reg = tmp;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->CTRLA.reg &= ~TRNG_CTRLA_ENABLE;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->CTRLA.reg ^= TRNG_CTRLA_ENABLE;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->CTRLA.reg |= TRNG_CTRLA_RUNSTDBY;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_trng_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Trng *)hw)->CTRLA.reg;
+	tmp = (tmp & TRNG_CTRLA_RUNSTDBY) >> TRNG_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_trng_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	TRNG_CRITICAL_SECTION_ENTER();
+	tmp = ((Trng *)hw)->CTRLA.reg;
+	tmp &= ~TRNG_CTRLA_RUNSTDBY;
+	tmp |= value << TRNG_CTRLA_RUNSTDBY_Pos;
+	((Trng *)hw)->CTRLA.reg = tmp;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->CTRLA.reg &= ~TRNG_CTRLA_RUNSTDBY;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->CTRLA.reg ^= TRNG_CTRLA_RUNSTDBY;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_set_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->CTRLA.reg |= mask;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_trng_ctrla_reg_t hri_trng_get_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Trng *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_trng_write_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t data)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->CTRLA.reg = data;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_clear_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->CTRLA.reg &= ~mask;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_toggle_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->CTRLA.reg ^= mask;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_trng_ctrla_reg_t hri_trng_read_CTRLA_reg(const void *const hw)
+{
+	return ((Trng *)hw)->CTRLA.reg;
+}
+
+static inline void hri_trng_set_EVCTRL_DATARDYEO_bit(const void *const hw)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->EVCTRL.reg |= TRNG_EVCTRL_DATARDYEO;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_trng_get_EVCTRL_DATARDYEO_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Trng *)hw)->EVCTRL.reg;
+	tmp = (tmp & TRNG_EVCTRL_DATARDYEO) >> TRNG_EVCTRL_DATARDYEO_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_trng_write_EVCTRL_DATARDYEO_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	TRNG_CRITICAL_SECTION_ENTER();
+	tmp = ((Trng *)hw)->EVCTRL.reg;
+	tmp &= ~TRNG_EVCTRL_DATARDYEO;
+	tmp |= value << TRNG_EVCTRL_DATARDYEO_Pos;
+	((Trng *)hw)->EVCTRL.reg = tmp;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_clear_EVCTRL_DATARDYEO_bit(const void *const hw)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->EVCTRL.reg &= ~TRNG_EVCTRL_DATARDYEO;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_toggle_EVCTRL_DATARDYEO_bit(const void *const hw)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->EVCTRL.reg ^= TRNG_EVCTRL_DATARDYEO;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_set_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->EVCTRL.reg |= mask;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_trng_evctrl_reg_t hri_trng_get_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Trng *)hw)->EVCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_trng_write_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t data)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->EVCTRL.reg = data;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_clear_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->EVCTRL.reg &= ~mask;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_trng_toggle_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask)
+{
+	TRNG_CRITICAL_SECTION_ENTER();
+	((Trng *)hw)->EVCTRL.reg ^= mask;
+	TRNG_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_trng_evctrl_reg_t hri_trng_read_EVCTRL_reg(const void *const hw)
+{
+	return ((Trng *)hw)->EVCTRL.reg;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_TRNG_L22_H_INCLUDED */
+#endif /* _SAML22_TRNG_COMPONENT_ */
diff --git a/watch-library/hardware/hri/hri_usb_l22.h b/watch-library/hardware/hri/hri_usb_l22.h
new file mode 100644
index 00000000..57a9419d
--- /dev/null
+++ b/watch-library/hardware/hri/hri_usb_l22.h
@@ -0,0 +1,4713 @@
+/**
+ * \file
+ *
+ * \brief SAM USB
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_USB_COMPONENT_
+#ifndef _HRI_USB_L22_H_INCLUDED_
+#define _HRI_USB_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_USB_CRITICAL_SECTIONS)
+#define USB_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define USB_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define USB_CRITICAL_SECTION_ENTER()
+#define USB_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint16_t hri_usb_padcal_reg_t;
+typedef uint16_t hri_usbdesc_bank_extreg_reg_t;
+typedef uint16_t hri_usbdescriptordevice_extreg_reg_t;
+typedef uint16_t hri_usbdevice_ctrlb_reg_t;
+typedef uint16_t hri_usbdevice_epintsmry_reg_t;
+typedef uint16_t hri_usbdevice_fnum_reg_t;
+typedef uint16_t hri_usbdevice_intenset_reg_t;
+typedef uint16_t hri_usbdevice_intflag_reg_t;
+typedef uint32_t hri_usb_descadd_reg_t;
+typedef uint32_t hri_usbdesc_bank_addr_reg_t;
+typedef uint32_t hri_usbdesc_bank_pcksize_reg_t;
+typedef uint32_t hri_usbdescriptordevice_addr_reg_t;
+typedef uint32_t hri_usbdescriptordevice_pcksize_reg_t;
+typedef uint8_t  hri_usb_ctrla_reg_t;
+typedef uint8_t  hri_usb_fsmstatus_reg_t;
+typedef uint8_t  hri_usb_qosctrl_reg_t;
+typedef uint8_t  hri_usb_syncbusy_reg_t;
+typedef uint8_t  hri_usbdesc_bank_status_bk_reg_t;
+typedef uint8_t  hri_usbdescriptordevice_status_bk_reg_t;
+typedef uint8_t  hri_usbdevice_dadd_reg_t;
+typedef uint8_t  hri_usbdevice_epcfg_reg_t;
+typedef uint8_t  hri_usbdevice_epintenset_reg_t;
+typedef uint8_t  hri_usbdevice_epintflag_reg_t;
+typedef uint8_t  hri_usbdevice_epstatus_reg_t;
+typedef uint8_t  hri_usbdevice_status_reg_t;
+typedef uint8_t  hri_usbendpoint_epcfg_reg_t;
+typedef uint8_t  hri_usbendpoint_epintenset_reg_t;
+typedef uint8_t  hri_usbendpoint_epintflag_reg_t;
+typedef uint8_t  hri_usbendpoint_epstatus_reg_t;
+
+static inline void hri_usb_wait_for_sync(const void *const hw, hri_usb_syncbusy_reg_t reg)
+{
+	while (((Usb *)hw)->DEVICE.SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_usb_is_syncing(const void *const hw, hri_usb_syncbusy_reg_t reg)
+{
+	return ((Usb *)hw)->DEVICE.SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_usbendpoint_get_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0)
+	       >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos;
+}
+
+static inline void hri_usbendpoint_clear_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0;
+}
+
+static inline bool hri_usbendpoint_get_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1)
+	       >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos;
+}
+
+static inline void hri_usbendpoint_clear_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1;
+}
+
+static inline bool hri_usbendpoint_get_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0)
+	       >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos;
+}
+
+static inline void hri_usbendpoint_clear_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0;
+}
+
+static inline bool hri_usbendpoint_get_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1)
+	       >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos;
+}
+
+static inline void hri_usbendpoint_clear_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1;
+}
+
+static inline bool hri_usbendpoint_get_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP)
+	       >> USB_DEVICE_EPINTFLAG_RXSTP_Pos;
+}
+
+static inline void hri_usbendpoint_clear_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP;
+}
+
+static inline bool hri_usbendpoint_get_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0)
+	       >> USB_DEVICE_EPINTFLAG_STALL0_Pos;
+}
+
+static inline void hri_usbendpoint_clear_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0;
+}
+
+static inline bool hri_usbendpoint_get_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1)
+	       >> USB_DEVICE_EPINTFLAG_STALL1_Pos;
+}
+
+static inline void hri_usbendpoint_clear_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1;
+}
+
+static inline bool hri_usbendpoint_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0)
+	       >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos;
+}
+
+static inline void hri_usbendpoint_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0;
+}
+
+static inline bool hri_usbendpoint_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1)
+	       >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos;
+}
+
+static inline void hri_usbendpoint_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1;
+}
+
+static inline bool hri_usbendpoint_get_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0)
+	       >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos;
+}
+
+static inline void hri_usbendpoint_clear_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0;
+}
+
+static inline bool hri_usbendpoint_get_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1)
+	       >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos;
+}
+
+static inline void hri_usbendpoint_clear_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1;
+}
+
+static inline bool hri_usbendpoint_get_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP)
+	       >> USB_DEVICE_EPINTFLAG_RXSTP_Pos;
+}
+
+static inline void hri_usbendpoint_clear_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP;
+}
+
+static inline bool hri_usbendpoint_get_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0)
+	       >> USB_DEVICE_EPINTFLAG_STALL0_Pos;
+}
+
+static inline void hri_usbendpoint_clear_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0;
+}
+
+static inline bool hri_usbendpoint_get_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1)
+	       >> USB_DEVICE_EPINTFLAG_STALL1_Pos;
+}
+
+static inline void hri_usbendpoint_clear_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1;
+}
+
+static inline hri_usbendpoint_epintflag_reg_t
+hri_usbendpoint_get_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epintflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbendpoint_epintflag_reg_t hri_usbendpoint_read_EPINTFLAG_reg(const void *const hw,
+                                                                                 uint8_t           submodule_index)
+{
+	return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg;
+}
+
+static inline void hri_usbendpoint_clear_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index,
+                                                       hri_usbendpoint_epintflag_reg_t mask)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = mask;
+}
+
+static inline void hri_usbendpoint_set_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT;
+}
+
+static inline bool hri_usbendpoint_get_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLOUT)
+	       >> USB_DEVICE_EPSTATUS_DTGLOUT_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT;
+}
+
+static inline void hri_usbendpoint_set_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN;
+}
+
+static inline bool hri_usbendpoint_get_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLIN)
+	       >> USB_DEVICE_EPSTATUS_DTGLIN_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN;
+}
+
+static inline void hri_usbendpoint_set_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK;
+}
+
+static inline bool hri_usbendpoint_get_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_CURBK)
+	       >> USB_DEVICE_EPSTATUS_CURBK_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK;
+}
+
+static inline void hri_usbendpoint_set_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0;
+}
+
+static inline bool hri_usbendpoint_get_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ0)
+	       >> USB_DEVICE_EPSTATUS_STALLRQ0_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index,
+                                                               bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0;
+}
+
+static inline void hri_usbendpoint_set_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1;
+}
+
+static inline bool hri_usbendpoint_get_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ1)
+	       >> USB_DEVICE_EPSTATUS_STALLRQ1_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index,
+                                                               bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1;
+}
+
+static inline void hri_usbendpoint_set_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY;
+}
+
+static inline bool hri_usbendpoint_get_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK0RDY)
+	       >> USB_DEVICE_EPSTATUS_BK0RDY_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY;
+}
+
+static inline void hri_usbendpoint_set_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY;
+}
+
+static inline bool hri_usbendpoint_get_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK1RDY)
+	       >> USB_DEVICE_EPSTATUS_BK1RDY_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY;
+}
+
+static inline void hri_usbendpoint_set_EPSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbendpoint_epstatus_reg_t mask)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = mask;
+}
+
+static inline hri_usbendpoint_epstatus_reg_t
+hri_usbendpoint_get_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epstatus_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbendpoint_epstatus_reg_t hri_usbendpoint_read_EPSTATUS_reg(const void *const hw,
+                                                                               uint8_t           submodule_index)
+{
+	return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg;
+}
+
+static inline void hri_usbendpoint_write_EPSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                      hri_usbendpoint_epstatus_reg_t data)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = data;
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = ~data;
+}
+
+static inline void hri_usbendpoint_clear_EPSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                      hri_usbendpoint_epstatus_reg_t mask)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = mask;
+}
+
+static inline void hri_usbendpoint_set_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0;
+}
+
+static inline bool hri_usbendpoint_get_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT0)
+	       >> USB_DEVICE_EPINTENSET_TRCPT0_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0;
+}
+
+static inline void hri_usbendpoint_set_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1;
+}
+
+static inline bool hri_usbendpoint_get_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT1)
+	       >> USB_DEVICE_EPINTENSET_TRCPT1_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1;
+}
+
+static inline void hri_usbendpoint_set_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
+}
+
+static inline bool hri_usbendpoint_get_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL0)
+	       >> USB_DEVICE_EPINTENSET_TRFAIL0_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
+}
+
+static inline void hri_usbendpoint_set_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
+}
+
+static inline bool hri_usbendpoint_get_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL1)
+	       >> USB_DEVICE_EPINTENSET_TRFAIL1_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
+}
+
+static inline void hri_usbendpoint_set_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP;
+}
+
+static inline bool hri_usbendpoint_get_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_RXSTP)
+	       >> USB_DEVICE_EPINTENSET_RXSTP_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP;
+}
+
+static inline void hri_usbendpoint_set_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0;
+}
+
+static inline bool hri_usbendpoint_get_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL0)
+	       >> USB_DEVICE_EPINTENSET_STALL0_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0;
+}
+
+static inline void hri_usbendpoint_set_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1;
+}
+
+static inline bool hri_usbendpoint_get_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL1)
+	       >> USB_DEVICE_EPINTENSET_STALL1_Pos;
+}
+
+static inline void hri_usbendpoint_write_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1;
+	} else {
+		((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1;
+	}
+}
+
+static inline void hri_usbendpoint_clear_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1;
+}
+
+static inline void hri_usbendpoint_set_EPINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbendpoint_epintenset_reg_t mask)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = mask;
+}
+
+static inline hri_usbendpoint_epintenset_reg_t
+hri_usbendpoint_get_EPINTEN_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epintenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbendpoint_epintenset_reg_t hri_usbendpoint_read_EPINTEN_reg(const void *const hw,
+                                                                                uint8_t           submodule_index)
+{
+	return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg;
+}
+
+static inline void hri_usbendpoint_write_EPINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                     hri_usbendpoint_epintenset_reg_t data)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = data;
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = ~data;
+}
+
+static inline void hri_usbendpoint_clear_EPINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                     hri_usbendpoint_epintenset_reg_t mask)
+{
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = mask;
+}
+
+static inline void hri_usbendpoint_set_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_NYETDIS;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbendpoint_get_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_NYETDIS) >> USB_DEVICE_EPCFG_NYETDIS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbendpoint_write_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp &= ~USB_DEVICE_EPCFG_NYETDIS;
+	tmp |= value << USB_DEVICE_EPCFG_NYETDIS_Pos;
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbendpoint_clear_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_NYETDIS;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbendpoint_toggle_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_NYETDIS;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbendpoint_set_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index,
+                                                        hri_usbendpoint_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbendpoint_epcfg_reg_t
+hri_usbendpoint_get_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0(mask)) >> USB_DEVICE_EPCFG_EPTYPE0_Pos;
+	return tmp;
+}
+
+static inline void hri_usbendpoint_write_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index,
+                                                          hri_usbendpoint_epcfg_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp &= ~USB_DEVICE_EPCFG_EPTYPE0_Msk;
+	tmp |= USB_DEVICE_EPCFG_EPTYPE0(data);
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbendpoint_clear_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index,
+                                                          hri_usbendpoint_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE0(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbendpoint_toggle_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index,
+                                                           hri_usbendpoint_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE0(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_EPTYPE0_bf(const void *const hw,
+                                                                                uint8_t           submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0_Msk) >> USB_DEVICE_EPCFG_EPTYPE0_Pos;
+	return tmp;
+}
+
+static inline void hri_usbendpoint_set_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index,
+                                                        hri_usbendpoint_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbendpoint_epcfg_reg_t
+hri_usbendpoint_get_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1(mask)) >> USB_DEVICE_EPCFG_EPTYPE1_Pos;
+	return tmp;
+}
+
+static inline void hri_usbendpoint_write_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index,
+                                                          hri_usbendpoint_epcfg_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp &= ~USB_DEVICE_EPCFG_EPTYPE1_Msk;
+	tmp |= USB_DEVICE_EPCFG_EPTYPE1(data);
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbendpoint_clear_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index,
+                                                          hri_usbendpoint_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE1(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbendpoint_toggle_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index,
+                                                           hri_usbendpoint_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE1(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_EPTYPE1_bf(const void *const hw,
+                                                                                uint8_t           submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1_Msk) >> USB_DEVICE_EPCFG_EPTYPE1_Pos;
+	return tmp;
+}
+
+static inline void hri_usbendpoint_set_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbendpoint_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_get_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                                        hri_usbendpoint_epcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbendpoint_write_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbendpoint_epcfg_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbendpoint_clear_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbendpoint_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbendpoint_toggle_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbendpoint_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg;
+}
+
+static inline bool hri_usbdevice_get_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0)
+	       >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos;
+}
+
+static inline void hri_usbdevice_clear_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0;
+}
+
+static inline bool hri_usbdevice_get_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1)
+	       >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos;
+}
+
+static inline void hri_usbdevice_clear_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1;
+}
+
+static inline bool hri_usbdevice_get_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0)
+	       >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos;
+}
+
+static inline void hri_usbdevice_clear_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0;
+}
+
+static inline bool hri_usbdevice_get_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1)
+	       >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos;
+}
+
+static inline void hri_usbdevice_clear_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1;
+}
+
+static inline bool hri_usbdevice_get_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP)
+	       >> USB_DEVICE_EPINTFLAG_RXSTP_Pos;
+}
+
+static inline void hri_usbdevice_clear_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP;
+}
+
+static inline bool hri_usbdevice_get_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0)
+	       >> USB_DEVICE_EPINTFLAG_STALL0_Pos;
+}
+
+static inline void hri_usbdevice_clear_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0;
+}
+
+static inline bool hri_usbdevice_get_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1)
+	       >> USB_DEVICE_EPINTFLAG_STALL1_Pos;
+}
+
+static inline void hri_usbdevice_clear_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1;
+}
+
+static inline bool hri_usbdevice_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0)
+	       >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0;
+}
+
+static inline bool hri_usbdevice_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1)
+	       >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1;
+}
+
+static inline bool hri_usbdevice_get_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0)
+	       >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0;
+}
+
+static inline bool hri_usbdevice_get_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1)
+	       >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1;
+}
+
+static inline bool hri_usbdevice_get_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP)
+	       >> USB_DEVICE_EPINTFLAG_RXSTP_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP;
+}
+
+static inline bool hri_usbdevice_get_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0)
+	       >> USB_DEVICE_EPINTFLAG_STALL0_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0;
+}
+
+static inline bool hri_usbdevice_get_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1)
+	       >> USB_DEVICE_EPINTFLAG_STALL1_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1;
+}
+
+static inline hri_usbdevice_epintflag_reg_t
+hri_usbdevice_get_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, hri_usbdevice_epintflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbdevice_epintflag_reg_t hri_usbdevice_read_EPINTFLAG_reg(const void *const hw,
+                                                                             uint8_t           submodule_index)
+{
+	return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg;
+}
+
+static inline void hri_usbdevice_clear_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index,
+                                                     hri_usbdevice_epintflag_reg_t mask)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = mask;
+}
+
+static inline void hri_usbdevice_set_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT;
+}
+
+static inline bool hri_usbdevice_get_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLOUT)
+	       >> USB_DEVICE_EPSTATUS_DTGLOUT_Pos;
+}
+
+static inline void hri_usbdevice_write_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT;
+}
+
+static inline void hri_usbdevice_set_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN;
+}
+
+static inline bool hri_usbdevice_get_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLIN)
+	       >> USB_DEVICE_EPSTATUS_DTGLIN_Pos;
+}
+
+static inline void hri_usbdevice_write_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN;
+}
+
+static inline void hri_usbdevice_set_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK;
+}
+
+static inline bool hri_usbdevice_get_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_CURBK)
+	       >> USB_DEVICE_EPSTATUS_CURBK_Pos;
+}
+
+static inline void hri_usbdevice_write_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK;
+}
+
+static inline void hri_usbdevice_set_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0;
+}
+
+static inline bool hri_usbdevice_get_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ0)
+	       >> USB_DEVICE_EPSTATUS_STALLRQ0_Pos;
+}
+
+static inline void hri_usbdevice_write_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0;
+}
+
+static inline void hri_usbdevice_set_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1;
+}
+
+static inline bool hri_usbdevice_get_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ1)
+	       >> USB_DEVICE_EPSTATUS_STALLRQ1_Pos;
+}
+
+static inline void hri_usbdevice_write_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1;
+}
+
+static inline void hri_usbdevice_set_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY;
+}
+
+static inline bool hri_usbdevice_get_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK0RDY)
+	       >> USB_DEVICE_EPSTATUS_BK0RDY_Pos;
+}
+
+static inline void hri_usbdevice_write_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY;
+}
+
+static inline void hri_usbdevice_set_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY;
+}
+
+static inline bool hri_usbdevice_get_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK1RDY)
+	       >> USB_DEVICE_EPSTATUS_BK1RDY_Pos;
+}
+
+static inline void hri_usbdevice_write_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY;
+}
+
+static inline void hri_usbdevice_set_EPSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                  hri_usbdevice_epstatus_reg_t mask)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = mask;
+}
+
+static inline hri_usbdevice_epstatus_reg_t hri_usbdevice_get_EPSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                                          hri_usbdevice_epstatus_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbdevice_epstatus_reg_t hri_usbdevice_read_EPSTATUS_reg(const void *const hw,
+                                                                           uint8_t           submodule_index)
+{
+	return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg;
+}
+
+static inline void hri_usbdevice_write_EPSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbdevice_epstatus_reg_t data)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = data;
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = ~data;
+}
+
+static inline void hri_usbdevice_clear_EPSTATUS_reg(const void *const hw, uint8_t submodule_index,
+                                                    hri_usbdevice_epstatus_reg_t mask)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = mask;
+}
+
+static inline void hri_usbdevice_set_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0;
+}
+
+static inline bool hri_usbdevice_get_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT0)
+	       >> USB_DEVICE_EPINTENSET_TRCPT0_Pos;
+}
+
+static inline void hri_usbdevice_write_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0;
+}
+
+static inline void hri_usbdevice_set_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1;
+}
+
+static inline bool hri_usbdevice_get_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT1)
+	       >> USB_DEVICE_EPINTENSET_TRCPT1_Pos;
+}
+
+static inline void hri_usbdevice_write_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1;
+}
+
+static inline void hri_usbdevice_set_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
+}
+
+static inline bool hri_usbdevice_get_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL0)
+	       >> USB_DEVICE_EPINTENSET_TRFAIL0_Pos;
+}
+
+static inline void hri_usbdevice_write_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
+}
+
+static inline void hri_usbdevice_set_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
+}
+
+static inline bool hri_usbdevice_get_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL1)
+	       >> USB_DEVICE_EPINTENSET_TRFAIL1_Pos;
+}
+
+static inline void hri_usbdevice_write_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
+}
+
+static inline void hri_usbdevice_set_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP;
+}
+
+static inline bool hri_usbdevice_get_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_RXSTP)
+	       >> USB_DEVICE_EPINTENSET_RXSTP_Pos;
+}
+
+static inline void hri_usbdevice_write_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP;
+}
+
+static inline void hri_usbdevice_set_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0;
+}
+
+static inline bool hri_usbdevice_get_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL0)
+	       >> USB_DEVICE_EPINTENSET_STALL0_Pos;
+}
+
+static inline void hri_usbdevice_write_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0;
+}
+
+static inline void hri_usbdevice_set_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1;
+}
+
+static inline bool hri_usbdevice_get_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL1)
+	       >> USB_DEVICE_EPINTENSET_STALL1_Pos;
+}
+
+static inline void hri_usbdevice_write_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1;
+	} else {
+		((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1;
+	}
+}
+
+static inline void hri_usbdevice_clear_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1;
+}
+
+static inline void hri_usbdevice_set_EPINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbdevice_epintenset_reg_t mask)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = mask;
+}
+
+static inline hri_usbdevice_epintenset_reg_t
+hri_usbdevice_get_EPINTEN_reg(const void *const hw, uint8_t submodule_index, hri_usbdevice_epintenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbdevice_epintenset_reg_t hri_usbdevice_read_EPINTEN_reg(const void *const hw,
+                                                                            uint8_t           submodule_index)
+{
+	return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg;
+}
+
+static inline void hri_usbdevice_write_EPINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbdevice_epintenset_reg_t data)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = data;
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = ~data;
+}
+
+static inline void hri_usbdevice_clear_EPINTEN_reg(const void *const hw, uint8_t submodule_index,
+                                                   hri_usbdevice_epintenset_reg_t mask)
+{
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = mask;
+}
+
+static inline void hri_usbdevice_set_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_NYETDIS;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_NYETDIS) >> USB_DEVICE_EPCFG_NYETDIS_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index, bool value)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp &= ~USB_DEVICE_EPCFG_NYETDIS;
+	tmp |= value << USB_DEVICE_EPCFG_NYETDIS_Pos;
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_NYETDIS;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_NYETDIS;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_usbdevice_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_epcfg_reg_t
+hri_usbdevice_get_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, hri_usbdevice_epcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0(mask)) >> USB_DEVICE_EPCFG_EPTYPE0_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index,
+                                                        hri_usbdevice_epcfg_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp &= ~USB_DEVICE_EPCFG_EPTYPE0_Msk;
+	tmp |= USB_DEVICE_EPCFG_EPTYPE0(data);
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index,
+                                                        hri_usbdevice_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE0(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index,
+                                                         hri_usbdevice_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE0(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_EPTYPE0_bf(const void *const hw,
+                                                                            uint8_t           submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0_Msk) >> USB_DEVICE_EPCFG_EPTYPE0_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_set_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index,
+                                                      hri_usbdevice_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_epcfg_reg_t
+hri_usbdevice_get_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, hri_usbdevice_epcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1(mask)) >> USB_DEVICE_EPCFG_EPTYPE1_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index,
+                                                        hri_usbdevice_epcfg_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp &= ~USB_DEVICE_EPCFG_EPTYPE1_Msk;
+	tmp |= USB_DEVICE_EPCFG_EPTYPE1(data);
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index,
+                                                        hri_usbdevice_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE1(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index,
+                                                         hri_usbdevice_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE1(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_EPTYPE1_bf(const void *const hw,
+                                                                            uint8_t           submodule_index)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1_Msk) >> USB_DEVICE_EPCFG_EPTYPE1_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_set_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                               hri_usbdevice_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_get_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                                    hri_usbdevice_epcfg_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbdevice_epcfg_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                 hri_usbdevice_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_EPCFG_reg(const void *const hw, uint8_t submodule_index,
+                                                  hri_usbdevice_epcfg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_SUSPEND_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SUSPEND) >> USB_DEVICE_INTFLAG_SUSPEND_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_SUSPEND_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SUSPEND;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_MSOF_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_MSOF) >> USB_DEVICE_INTFLAG_MSOF_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_MSOF_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_MSOF;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_SOF_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SOF) >> USB_DEVICE_INTFLAG_SOF_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_SOF_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SOF;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_EORST_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORST) >> USB_DEVICE_INTFLAG_EORST_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_EORST_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORST;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_WAKEUP_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_WAKEUP) >> USB_DEVICE_INTFLAG_WAKEUP_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_WAKEUP_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_WAKEUP;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_EORSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORSM) >> USB_DEVICE_INTFLAG_EORSM_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_EORSM_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORSM;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_UPRSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_UPRSM) >> USB_DEVICE_INTFLAG_UPRSM_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_UPRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_UPRSM;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_RAMACER_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_RAMACER) >> USB_DEVICE_INTFLAG_RAMACER_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_RAMACER_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_RAMACER;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_LPMNYET_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMNYET) >> USB_DEVICE_INTFLAG_LPMNYET_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_LPMNYET_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMNYET;
+}
+
+static inline bool hri_usbdevice_get_INTFLAG_LPMSUSP_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMSUSP) >> USB_DEVICE_INTFLAG_LPMSUSP_Pos;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_LPMSUSP_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMSUSP;
+}
+
+static inline bool hri_usbdevice_get_interrupt_SUSPEND_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SUSPEND) >> USB_DEVICE_INTFLAG_SUSPEND_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_SUSPEND_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SUSPEND;
+}
+
+static inline bool hri_usbdevice_get_interrupt_MSOF_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_MSOF) >> USB_DEVICE_INTFLAG_MSOF_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_MSOF_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_MSOF;
+}
+
+static inline bool hri_usbdevice_get_interrupt_SOF_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SOF) >> USB_DEVICE_INTFLAG_SOF_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_SOF_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SOF;
+}
+
+static inline bool hri_usbdevice_get_interrupt_EORST_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORST) >> USB_DEVICE_INTFLAG_EORST_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_EORST_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORST;
+}
+
+static inline bool hri_usbdevice_get_interrupt_WAKEUP_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_WAKEUP) >> USB_DEVICE_INTFLAG_WAKEUP_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_WAKEUP_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_WAKEUP;
+}
+
+static inline bool hri_usbdevice_get_interrupt_EORSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORSM) >> USB_DEVICE_INTFLAG_EORSM_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_EORSM_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORSM;
+}
+
+static inline bool hri_usbdevice_get_interrupt_UPRSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_UPRSM) >> USB_DEVICE_INTFLAG_UPRSM_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_UPRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_UPRSM;
+}
+
+static inline bool hri_usbdevice_get_interrupt_RAMACER_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_RAMACER) >> USB_DEVICE_INTFLAG_RAMACER_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_RAMACER_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_RAMACER;
+}
+
+static inline bool hri_usbdevice_get_interrupt_LPMNYET_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMNYET) >> USB_DEVICE_INTFLAG_LPMNYET_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_LPMNYET_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMNYET;
+}
+
+static inline bool hri_usbdevice_get_interrupt_LPMSUSP_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMSUSP) >> USB_DEVICE_INTFLAG_LPMSUSP_Pos;
+}
+
+static inline void hri_usbdevice_clear_interrupt_LPMSUSP_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMSUSP;
+}
+
+static inline hri_usbdevice_intflag_reg_t hri_usbdevice_get_INTFLAG_reg(const void *const           hw,
+                                                                        hri_usbdevice_intflag_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbdevice_intflag_reg_t hri_usbdevice_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.INTFLAG.reg;
+}
+
+static inline void hri_usbdevice_clear_INTFLAG_reg(const void *const hw, hri_usbdevice_intflag_reg_t mask)
+{
+	((Usb *)hw)->DEVICE.INTFLAG.reg = mask;
+}
+
+static inline void hri_usbdevice_set_INTEN_SUSPEND_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SUSPEND;
+}
+
+static inline bool hri_usbdevice_get_INTEN_SUSPEND_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_SUSPEND) >> USB_DEVICE_INTENSET_SUSPEND_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_SUSPEND_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SUSPEND;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SUSPEND;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_SUSPEND_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SUSPEND;
+}
+
+static inline void hri_usbdevice_set_INTEN_MSOF_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_MSOF;
+}
+
+static inline bool hri_usbdevice_get_INTEN_MSOF_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_MSOF) >> USB_DEVICE_INTENSET_MSOF_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_MSOF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_MSOF;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_MSOF;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_MSOF_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_MSOF;
+}
+
+static inline void hri_usbdevice_set_INTEN_SOF_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SOF;
+}
+
+static inline bool hri_usbdevice_get_INTEN_SOF_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_SOF) >> USB_DEVICE_INTENSET_SOF_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_SOF_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SOF;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SOF;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_SOF_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SOF;
+}
+
+static inline void hri_usbdevice_set_INTEN_EORST_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORST;
+}
+
+static inline bool hri_usbdevice_get_INTEN_EORST_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_EORST) >> USB_DEVICE_INTENSET_EORST_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_EORST_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORST;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORST;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_EORST_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORST;
+}
+
+static inline void hri_usbdevice_set_INTEN_WAKEUP_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_WAKEUP;
+}
+
+static inline bool hri_usbdevice_get_INTEN_WAKEUP_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_WAKEUP) >> USB_DEVICE_INTENSET_WAKEUP_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_WAKEUP_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_WAKEUP;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_WAKEUP;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_WAKEUP_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_WAKEUP;
+}
+
+static inline void hri_usbdevice_set_INTEN_EORSM_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORSM;
+}
+
+static inline bool hri_usbdevice_get_INTEN_EORSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_EORSM) >> USB_DEVICE_INTENSET_EORSM_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_EORSM_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORSM;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORSM;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_EORSM_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORSM;
+}
+
+static inline void hri_usbdevice_set_INTEN_UPRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_UPRSM;
+}
+
+static inline bool hri_usbdevice_get_INTEN_UPRSM_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_UPRSM) >> USB_DEVICE_INTENSET_UPRSM_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_UPRSM_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_UPRSM;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_UPRSM;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_UPRSM_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_UPRSM;
+}
+
+static inline void hri_usbdevice_set_INTEN_RAMACER_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_RAMACER;
+}
+
+static inline bool hri_usbdevice_get_INTEN_RAMACER_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_RAMACER) >> USB_DEVICE_INTENSET_RAMACER_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_RAMACER_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_RAMACER;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_RAMACER;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_RAMACER_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_RAMACER;
+}
+
+static inline void hri_usbdevice_set_INTEN_LPMNYET_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMNYET;
+}
+
+static inline bool hri_usbdevice_get_INTEN_LPMNYET_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_LPMNYET) >> USB_DEVICE_INTENSET_LPMNYET_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_LPMNYET_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMNYET;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMNYET;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_LPMNYET_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMNYET;
+}
+
+static inline void hri_usbdevice_set_INTEN_LPMSUSP_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMSUSP;
+}
+
+static inline bool hri_usbdevice_get_INTEN_LPMSUSP_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_LPMSUSP) >> USB_DEVICE_INTENSET_LPMSUSP_Pos;
+}
+
+static inline void hri_usbdevice_write_INTEN_LPMSUSP_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMSUSP;
+	} else {
+		((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMSUSP;
+	}
+}
+
+static inline void hri_usbdevice_clear_INTEN_LPMSUSP_bit(const void *const hw)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMSUSP;
+}
+
+static inline void hri_usbdevice_set_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t mask)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = mask;
+}
+
+static inline hri_usbdevice_intenset_reg_t hri_usbdevice_get_INTEN_reg(const void *const            hw,
+                                                                       hri_usbdevice_intenset_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbdevice_intenset_reg_t hri_usbdevice_read_INTEN_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.INTENSET.reg;
+}
+
+static inline void hri_usbdevice_write_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t data)
+{
+	((Usb *)hw)->DEVICE.INTENSET.reg = data;
+	((Usb *)hw)->DEVICE.INTENCLR.reg = ~data;
+}
+
+static inline void hri_usbdevice_clear_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t mask)
+{
+	((Usb *)hw)->DEVICE.INTENCLR.reg = mask;
+}
+
+static inline bool hri_usb_get_SYNCBUSY_SWRST_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.SYNCBUSY.reg & USB_SYNCBUSY_SWRST) >> USB_SYNCBUSY_SWRST_Pos;
+}
+
+static inline bool hri_usb_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.SYNCBUSY.reg & USB_SYNCBUSY_ENABLE) >> USB_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline hri_usb_syncbusy_reg_t hri_usb_get_SYNCBUSY_reg(const void *const hw, hri_usb_syncbusy_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usb_syncbusy_reg_t hri_usb_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.SYNCBUSY.reg;
+}
+
+static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_SPEED_bf(const void *const          hw,
+                                                                           hri_usbdevice_status_reg_t mask)
+{
+	return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_SPEED(mask)) >> USB_DEVICE_STATUS_SPEED_Pos;
+}
+
+static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_SPEED_bf(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_SPEED_Msk) >> USB_DEVICE_STATUS_SPEED_Pos;
+}
+
+static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_LINESTATE_bf(const void *const          hw,
+                                                                               hri_usbdevice_status_reg_t mask)
+{
+	return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_LINESTATE(mask)) >> USB_DEVICE_STATUS_LINESTATE_Pos;
+}
+
+static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_LINESTATE_bf(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_LINESTATE_Msk) >> USB_DEVICE_STATUS_LINESTATE_Pos;
+}
+
+static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_reg(const void *const          hw,
+                                                                      hri_usbdevice_status_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.STATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.STATUS.reg;
+}
+
+static inline hri_usb_fsmstatus_reg_t hri_usb_get_FSMSTATUS_FSMSTATE_bf(const void *const       hw,
+                                                                        hri_usb_fsmstatus_reg_t mask)
+{
+	return (((Usb *)hw)->DEVICE.FSMSTATUS.reg & USB_FSMSTATUS_FSMSTATE(mask)) >> USB_FSMSTATUS_FSMSTATE_Pos;
+}
+
+static inline hri_usb_fsmstatus_reg_t hri_usb_read_FSMSTATUS_FSMSTATE_bf(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.FSMSTATUS.reg & USB_FSMSTATUS_FSMSTATE_Msk) >> USB_FSMSTATUS_FSMSTATE_Pos;
+}
+
+static inline hri_usb_fsmstatus_reg_t hri_usb_get_FSMSTATUS_reg(const void *const hw, hri_usb_fsmstatus_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.FSMSTATUS.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usb_fsmstatus_reg_t hri_usb_read_FSMSTATUS_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.FSMSTATUS.reg;
+}
+
+static inline bool hri_usbdevice_get_FNUM_FNCERR_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNCERR) >> USB_DEVICE_FNUM_FNCERR_Pos;
+}
+
+static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_MFNUM_bf(const void *const        hw,
+                                                                       hri_usbdevice_fnum_reg_t mask)
+{
+	return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_MFNUM(mask)) >> USB_DEVICE_FNUM_MFNUM_Pos;
+}
+
+static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_MFNUM_bf(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_MFNUM_Msk) >> USB_DEVICE_FNUM_MFNUM_Pos;
+}
+
+static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_FNUM_bf(const void *const        hw,
+                                                                      hri_usbdevice_fnum_reg_t mask)
+{
+	return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNUM(mask)) >> USB_DEVICE_FNUM_FNUM_Pos;
+}
+
+static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_FNUM_bf(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNUM_Msk) >> USB_DEVICE_FNUM_FNUM_Pos;
+}
+
+static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_reg(const void *const hw, hri_usbdevice_fnum_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.FNUM.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.FNUM.reg;
+}
+
+static inline bool hri_usbdevice_get_EPINTSMRY_EPINT0_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT0) >> USB_DEVICE_EPINTSMRY_EPINT0_Pos;
+}
+
+static inline bool hri_usbdevice_get_EPINTSMRY_EPINT1_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT1) >> USB_DEVICE_EPINTSMRY_EPINT1_Pos;
+}
+
+static inline bool hri_usbdevice_get_EPINTSMRY_EPINT2_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT2) >> USB_DEVICE_EPINTSMRY_EPINT2_Pos;
+}
+
+static inline bool hri_usbdevice_get_EPINTSMRY_EPINT3_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT3) >> USB_DEVICE_EPINTSMRY_EPINT3_Pos;
+}
+
+static inline bool hri_usbdevice_get_EPINTSMRY_EPINT4_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT4) >> USB_DEVICE_EPINTSMRY_EPINT4_Pos;
+}
+
+static inline bool hri_usbdevice_get_EPINTSMRY_EPINT5_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT5) >> USB_DEVICE_EPINTSMRY_EPINT5_Pos;
+}
+
+static inline bool hri_usbdevice_get_EPINTSMRY_EPINT6_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT6) >> USB_DEVICE_EPINTSMRY_EPINT6_Pos;
+}
+
+static inline bool hri_usbdevice_get_EPINTSMRY_EPINT7_bit(const void *const hw)
+{
+	return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT7) >> USB_DEVICE_EPINTSMRY_EPINT7_Pos;
+}
+
+static inline hri_usbdevice_epintsmry_reg_t hri_usbdevice_get_EPINTSMRY_reg(const void *const             hw,
+                                                                            hri_usbdevice_epintsmry_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.EPINTSMRY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_usbdevice_epintsmry_reg_t hri_usbdevice_read_EPINTSMRY_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.EPINTSMRY.reg;
+}
+
+static inline void hri_usb_set_CTRLA_SWRST_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLA.reg |= USB_CTRLA_SWRST;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usb_get_CTRLA_SWRST_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST);
+	tmp = ((Usb *)hw)->DEVICE.CTRLA.reg;
+	tmp = (tmp & USB_CTRLA_SWRST) >> USB_CTRLA_SWRST_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usb_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLA.reg |= USB_CTRLA_ENABLE;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usb_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE);
+	tmp = ((Usb *)hw)->DEVICE.CTRLA.reg;
+	tmp = (tmp & USB_CTRLA_ENABLE) >> USB_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usb_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLA.reg;
+	tmp &= ~USB_CTRLA_ENABLE;
+	tmp |= value << USB_CTRLA_ENABLE_Pos;
+	((Usb *)hw)->DEVICE.CTRLA.reg = tmp;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLA.reg &= ~USB_CTRLA_ENABLE;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLA.reg ^= USB_CTRLA_ENABLE;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_set_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLA.reg |= USB_CTRLA_RUNSTDBY;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usb_get_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLA.reg;
+	tmp = (tmp & USB_CTRLA_RUNSTDBY) >> USB_CTRLA_RUNSTDBY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usb_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLA.reg;
+	tmp &= ~USB_CTRLA_RUNSTDBY;
+	tmp |= value << USB_CTRLA_RUNSTDBY_Pos;
+	((Usb *)hw)->DEVICE.CTRLA.reg = tmp;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLA.reg &= ~USB_CTRLA_RUNSTDBY;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLA.reg ^= USB_CTRLA_RUNSTDBY;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_set_CTRLA_MODE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLA.reg |= USB_CTRLA_MODE;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usb_get_CTRLA_MODE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLA.reg;
+	tmp = (tmp & USB_CTRLA_MODE) >> USB_CTRLA_MODE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usb_write_CTRLA_MODE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLA.reg;
+	tmp &= ~USB_CTRLA_MODE;
+	tmp |= value << USB_CTRLA_MODE_Pos;
+	((Usb *)hw)->DEVICE.CTRLA.reg = tmp;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_CTRLA_MODE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLA.reg &= ~USB_CTRLA_MODE;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_CTRLA_MODE_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLA.reg ^= USB_CTRLA_MODE;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_set_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLA.reg |= mask;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_ctrla_reg_t hri_usb_get_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	tmp = ((Usb *)hw)->DEVICE.CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usb_write_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLA.reg = data;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLA.reg &= ~mask;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLA.reg ^= mask;
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_ctrla_reg_t hri_usb_read_CTRLA_reg(const void *const hw)
+{
+	hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK);
+	return ((Usb *)hw)->DEVICE.CTRLA.reg;
+}
+
+static inline void hri_usb_set_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.QOSCTRL.reg |= USB_QOSCTRL_CQOS(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_qosctrl_reg_t hri_usb_get_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg;
+	tmp = (tmp & USB_QOSCTRL_CQOS(mask)) >> USB_QOSCTRL_CQOS_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_write_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg;
+	tmp &= ~USB_QOSCTRL_CQOS_Msk;
+	tmp |= USB_QOSCTRL_CQOS(data);
+	((Usb *)hw)->DEVICE.QOSCTRL.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.QOSCTRL.reg &= ~USB_QOSCTRL_CQOS(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.QOSCTRL.reg ^= USB_QOSCTRL_CQOS(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_qosctrl_reg_t hri_usb_read_QOSCTRL_CQOS_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg;
+	tmp = (tmp & USB_QOSCTRL_CQOS_Msk) >> USB_QOSCTRL_CQOS_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_set_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.QOSCTRL.reg |= USB_QOSCTRL_DQOS(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_qosctrl_reg_t hri_usb_get_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg;
+	tmp = (tmp & USB_QOSCTRL_DQOS(mask)) >> USB_QOSCTRL_DQOS_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_write_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg;
+	tmp &= ~USB_QOSCTRL_DQOS_Msk;
+	tmp |= USB_QOSCTRL_DQOS(data);
+	((Usb *)hw)->DEVICE.QOSCTRL.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.QOSCTRL.reg &= ~USB_QOSCTRL_DQOS(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.QOSCTRL.reg ^= USB_QOSCTRL_DQOS(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_qosctrl_reg_t hri_usb_read_QOSCTRL_DQOS_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg;
+	tmp = (tmp & USB_QOSCTRL_DQOS_Msk) >> USB_QOSCTRL_DQOS_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_set_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.QOSCTRL.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_qosctrl_reg_t hri_usb_get_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usb_write_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.QOSCTRL.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.QOSCTRL.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.QOSCTRL.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_qosctrl_reg_t hri_usb_read_QOSCTRL_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.QOSCTRL.reg;
+}
+
+static inline void hri_usbdevice_set_CTRLB_DETACH_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_DETACH;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_CTRLB_DETACH_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_DETACH) >> USB_DEVICE_CTRLB_DETACH_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_DETACH_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_DETACH;
+	tmp |= value << USB_DEVICE_CTRLB_DETACH_Pos;
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_DETACH_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_DETACH;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_DETACH_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_DETACH;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_CTRLB_UPRSM_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_UPRSM;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_CTRLB_UPRSM_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_UPRSM) >> USB_DEVICE_CTRLB_UPRSM_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_UPRSM_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_UPRSM;
+	tmp |= value << USB_DEVICE_CTRLB_UPRSM_Pos;
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_UPRSM_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_UPRSM;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_UPRSM_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_UPRSM;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_CTRLB_NREPLY_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_NREPLY;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_CTRLB_NREPLY_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_NREPLY) >> USB_DEVICE_CTRLB_NREPLY_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_NREPLY_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_NREPLY;
+	tmp |= value << USB_DEVICE_CTRLB_NREPLY_Pos;
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_NREPLY_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_NREPLY;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_NREPLY_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_NREPLY;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_CTRLB_TSTJ_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTJ;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_CTRLB_TSTJ_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_TSTJ) >> USB_DEVICE_CTRLB_TSTJ_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_TSTJ_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_TSTJ;
+	tmp |= value << USB_DEVICE_CTRLB_TSTJ_Pos;
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_TSTJ_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTJ;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_TSTJ_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTJ;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_CTRLB_TSTK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_CTRLB_TSTK_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_TSTK) >> USB_DEVICE_CTRLB_TSTK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_TSTK_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_TSTK;
+	tmp |= value << USB_DEVICE_CTRLB_TSTK_Pos;
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_TSTK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_TSTK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_CTRLB_TSTPCKT_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTPCKT;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_CTRLB_TSTPCKT_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_TSTPCKT) >> USB_DEVICE_CTRLB_TSTPCKT_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_TSTPCKT_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_TSTPCKT;
+	tmp |= value << USB_DEVICE_CTRLB_TSTPCKT_Pos;
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_TSTPCKT_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTPCKT;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_TSTPCKT_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTPCKT;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_CTRLB_OPMODE2_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_OPMODE2;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_CTRLB_OPMODE2_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_OPMODE2) >> USB_DEVICE_CTRLB_OPMODE2_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_OPMODE2_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_OPMODE2;
+	tmp |= value << USB_DEVICE_CTRLB_OPMODE2_Pos;
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_OPMODE2_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_OPMODE2;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_OPMODE2_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_OPMODE2;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_CTRLB_GNAK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_GNAK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_CTRLB_GNAK_bit(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_GNAK) >> USB_DEVICE_CTRLB_GNAK_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_GNAK_bit(const void *const hw, bool value)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_GNAK;
+	tmp |= value << USB_DEVICE_CTRLB_GNAK_Pos;
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_GNAK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_GNAK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_GNAK_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_GNAK;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_SPDCONF(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_SPDCONF_bf(const void *const         hw,
+                                                                           hri_usbdevice_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_SPDCONF(mask)) >> USB_DEVICE_CTRLB_SPDCONF_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_SPDCONF_Msk;
+	tmp |= USB_DEVICE_CTRLB_SPDCONF(data);
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_SPDCONF(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_SPDCONF(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_SPDCONF_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_SPDCONF_Msk) >> USB_DEVICE_CTRLB_SPDCONF_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_set_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_LPMHDSK(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_LPMHDSK_bf(const void *const         hw,
+                                                                           hri_usbdevice_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_LPMHDSK(mask)) >> USB_DEVICE_CTRLB_LPMHDSK_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= ~USB_DEVICE_CTRLB_LPMHDSK_Msk;
+	tmp |= USB_DEVICE_CTRLB_LPMHDSK(data);
+	((Usb *)hw)->DEVICE.CTRLB.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_LPMHDSK(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_LPMHDSK(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_LPMHDSK_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp = (tmp & USB_DEVICE_CTRLB_LPMHDSK_Msk) >> USB_DEVICE_CTRLB_LPMHDSK_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_set_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_reg(const void *const         hw,
+                                                                    hri_usbdevice_ctrlb_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.CTRLB.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.CTRLB.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.CTRLB.reg;
+}
+
+static inline void hri_usbdevice_set_DADD_ADDEN_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg |= USB_DEVICE_DADD_ADDEN;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevice_get_DADD_ADDEN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DADD.reg;
+	tmp = (tmp & USB_DEVICE_DADD_ADDEN) >> USB_DEVICE_DADD_ADDEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevice_write_DADD_ADDEN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.DADD.reg;
+	tmp &= ~USB_DEVICE_DADD_ADDEN;
+	tmp |= value << USB_DEVICE_DADD_ADDEN_Pos;
+	((Usb *)hw)->DEVICE.DADD.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_DADD_ADDEN_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg &= ~USB_DEVICE_DADD_ADDEN;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_DADD_ADDEN_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg ^= USB_DEVICE_DADD_ADDEN;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_set_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg |= USB_DEVICE_DADD_DADD(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_dadd_reg_t hri_usbdevice_get_DADD_DADD_bf(const void *const        hw,
+                                                                      hri_usbdevice_dadd_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DADD.reg;
+	tmp = (tmp & USB_DEVICE_DADD_DADD(mask)) >> USB_DEVICE_DADD_DADD_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t data)
+{
+	uint8_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.DADD.reg;
+	tmp &= ~USB_DEVICE_DADD_DADD_Msk;
+	tmp |= USB_DEVICE_DADD_DADD(data);
+	((Usb *)hw)->DEVICE.DADD.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg &= ~USB_DEVICE_DADD_DADD(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg ^= USB_DEVICE_DADD_DADD(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_dadd_reg_t hri_usbdevice_read_DADD_DADD_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DADD.reg;
+	tmp = (tmp & USB_DEVICE_DADD_DADD_Msk) >> USB_DEVICE_DADD_DADD_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevice_set_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_dadd_reg_t hri_usbdevice_get_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DADD.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevice_write_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_clear_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevice_toggle_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DADD.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdevice_dadd_reg_t hri_usbdevice_read_DADD_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.DADD.reg;
+}
+
+static inline void hri_usb_set_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DESCADD.reg |= USB_DESCADD_DESCADD(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_descadd_reg_t hri_usb_get_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DESCADD.reg;
+	tmp = (tmp & USB_DESCADD_DESCADD(mask)) >> USB_DESCADD_DESCADD_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_write_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.DESCADD.reg;
+	tmp &= ~USB_DESCADD_DESCADD_Msk;
+	tmp |= USB_DESCADD_DESCADD(data);
+	((Usb *)hw)->DEVICE.DESCADD.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DESCADD.reg &= ~USB_DESCADD_DESCADD(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DESCADD.reg ^= USB_DESCADD_DESCADD(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_descadd_reg_t hri_usb_read_DESCADD_DESCADD_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DESCADD.reg;
+	tmp = (tmp & USB_DESCADD_DESCADD_Msk) >> USB_DESCADD_DESCADD_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_set_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DESCADD.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_descadd_reg_t hri_usb_get_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.DESCADD.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usb_write_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DESCADD.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DESCADD.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.DESCADD.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_descadd_reg_t hri_usb_read_DESCADD_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.DESCADD.reg;
+}
+
+static inline void hri_usb_set_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.PADCAL.reg |= USB_PADCAL_TRANSP(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.PADCAL.reg;
+	tmp = (tmp & USB_PADCAL_TRANSP(mask)) >> USB_PADCAL_TRANSP_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_write_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.PADCAL.reg;
+	tmp &= ~USB_PADCAL_TRANSP_Msk;
+	tmp |= USB_PADCAL_TRANSP(data);
+	((Usb *)hw)->DEVICE.PADCAL.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.PADCAL.reg &= ~USB_PADCAL_TRANSP(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.PADCAL.reg ^= USB_PADCAL_TRANSP(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_TRANSP_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.PADCAL.reg;
+	tmp = (tmp & USB_PADCAL_TRANSP_Msk) >> USB_PADCAL_TRANSP_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_set_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.PADCAL.reg |= USB_PADCAL_TRANSN(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.PADCAL.reg;
+	tmp = (tmp & USB_PADCAL_TRANSN(mask)) >> USB_PADCAL_TRANSN_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_write_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.PADCAL.reg;
+	tmp &= ~USB_PADCAL_TRANSN_Msk;
+	tmp |= USB_PADCAL_TRANSN(data);
+	((Usb *)hw)->DEVICE.PADCAL.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.PADCAL.reg &= ~USB_PADCAL_TRANSN(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.PADCAL.reg ^= USB_PADCAL_TRANSN(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_TRANSN_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.PADCAL.reg;
+	tmp = (tmp & USB_PADCAL_TRANSN_Msk) >> USB_PADCAL_TRANSN_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_set_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.PADCAL.reg |= USB_PADCAL_TRIM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.PADCAL.reg;
+	tmp = (tmp & USB_PADCAL_TRIM(mask)) >> USB_PADCAL_TRIM_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_write_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((Usb *)hw)->DEVICE.PADCAL.reg;
+	tmp &= ~USB_PADCAL_TRIM_Msk;
+	tmp |= USB_PADCAL_TRIM(data);
+	((Usb *)hw)->DEVICE.PADCAL.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.PADCAL.reg &= ~USB_PADCAL_TRIM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.PADCAL.reg ^= USB_PADCAL_TRIM(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_TRIM_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.PADCAL.reg;
+	tmp = (tmp & USB_PADCAL_TRIM_Msk) >> USB_PADCAL_TRIM_Pos;
+	return tmp;
+}
+
+static inline void hri_usb_set_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.PADCAL.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((Usb *)hw)->DEVICE.PADCAL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usb_write_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.PADCAL.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_clear_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.PADCAL.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usb_toggle_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((Usb *)hw)->DEVICE.PADCAL.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_reg(const void *const hw)
+{
+	return ((Usb *)hw)->DEVICE.PADCAL.reg;
+}
+
+static inline void hri_usbdescbank_set_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->ADDR.reg |= USB_DEVICE_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_addr_reg_t hri_usbdescbank_get_ADDR_ADDR_bf(const void *const           hw,
+                                                                           hri_usbdesc_bank_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg;
+	tmp = (tmp & USB_DEVICE_ADDR_ADDR(mask)) >> USB_DEVICE_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdescbank_write_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg;
+	tmp &= ~USB_DEVICE_ADDR_ADDR_Msk;
+	tmp |= USB_DEVICE_ADDR_ADDR(data);
+	((UsbDeviceDescBank *)hw)->ADDR.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdescbank_clear_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->ADDR.reg &= ~USB_DEVICE_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdescbank_toggle_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->ADDR.reg ^= USB_DEVICE_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_addr_reg_t hri_usbdescbank_read_ADDR_ADDR_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg;
+	tmp = (tmp & USB_DEVICE_ADDR_ADDR_Msk) >> USB_DEVICE_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdescbank_set_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->ADDR.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_addr_reg_t hri_usbdescbank_get_ADDR_reg(const void *const           hw,
+                                                                       hri_usbdesc_bank_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdescbank_write_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->ADDR.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdescbank_clear_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->ADDR.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdescbank_toggle_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->ADDR.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_addr_reg_t hri_usbdescbank_read_ADDR_reg(const void *const hw)
+{
+	return ((UsbDeviceDescBank *)hw)->ADDR.reg;
+}
+
+static inline void hri_usbdescbank_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdescbank_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_AUTO_ZLP) >> USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdescbank_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, bool value)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP;
+	tmp |= value << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos;
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdescbank_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdescbank_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdescbank_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t
+hri_usbdescbank_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT(mask)) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdescbank_write_PCKSIZE_BYTE_COUNT_bf(const void *const              hw,
+                                                               hri_usbdesc_bank_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk;
+	tmp |= USB_DEVICE_PCKSIZE_BYTE_COUNT(data);
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdescbank_clear_PCKSIZE_BYTE_COUNT_bf(const void *const              hw,
+                                                               hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdescbank_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const              hw,
+                                                                hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdescbank_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdescbank_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const              hw,
+                                                                    hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t
+hri_usbdescbank_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdescbank_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const              hw,
+                                                                      hri_usbdesc_bank_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk;
+	tmp |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(data);
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdescbank_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const              hw,
+                                                                      hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdescbank_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const              hw,
+                                                                       hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdescbank_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdescbank_set_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdescbank_get_PCKSIZE_SIZE_bf(const void *const              hw,
+                                                                                 hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE(mask)) >> USB_DEVICE_PCKSIZE_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdescbank_write_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp &= ~USB_DEVICE_PCKSIZE_SIZE_Msk;
+	tmp |= USB_DEVICE_PCKSIZE_SIZE(data);
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdescbank_clear_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdescbank_toggle_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdescbank_read_PCKSIZE_SIZE_bf(const void *const hw)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE_Msk) >> USB_DEVICE_PCKSIZE_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdescbank_set_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdescbank_get_PCKSIZE_reg(const void *const              hw,
+                                                                             hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdescbank_write_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdescbank_clear_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdescbank_toggle_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdescbank_read_PCKSIZE_reg(const void *const hw)
+{
+	return ((UsbDeviceDescBank *)hw)->PCKSIZE.reg;
+}
+
+static inline void hri_usbdescbank_set_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg |= USB_DEVICE_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t hri_usbdescbank_get_EXTREG_SUBPID_bf(const void *const             hw,
+                                                                                 hri_usbdesc_bank_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg;
+	tmp = (tmp & USB_DEVICE_EXTREG_SUBPID(mask)) >> USB_DEVICE_EXTREG_SUBPID_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdescbank_write_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg;
+	tmp &= ~USB_DEVICE_EXTREG_SUBPID_Msk;
+	tmp |= USB_DEVICE_EXTREG_SUBPID(data);
+	((UsbDeviceDescBank *)hw)->EXTREG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdescbank_clear_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~USB_DEVICE_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdescbank_toggle_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg ^= USB_DEVICE_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t hri_usbdescbank_read_EXTREG_SUBPID_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg;
+	tmp = (tmp & USB_DEVICE_EXTREG_SUBPID_Msk) >> USB_DEVICE_EXTREG_SUBPID_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdescbank_set_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg |= USB_DEVICE_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t hri_usbdescbank_get_EXTREG_VARIABLE_bf(const void *const             hw,
+                                                                                   hri_usbdesc_bank_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg;
+	tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE(mask)) >> USB_DEVICE_EXTREG_VARIABLE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdescbank_write_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg;
+	tmp &= ~USB_DEVICE_EXTREG_VARIABLE_Msk;
+	tmp |= USB_DEVICE_EXTREG_VARIABLE(data);
+	((UsbDeviceDescBank *)hw)->EXTREG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdescbank_clear_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~USB_DEVICE_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdescbank_toggle_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg ^= USB_DEVICE_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t hri_usbdescbank_read_EXTREG_VARIABLE_bf(const void *const hw)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg;
+	tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE_Msk) >> USB_DEVICE_EXTREG_VARIABLE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdescbank_set_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t hri_usbdescbank_get_EXTREG_reg(const void *const             hw,
+                                                                           hri_usbdesc_bank_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdescbank_write_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdescbank_clear_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdescbank_toggle_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->EXTREG.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_extreg_reg_t hri_usbdescbank_read_EXTREG_reg(const void *const hw)
+{
+	return ((UsbDeviceDescBank *)hw)->EXTREG.reg;
+}
+
+static inline bool hri_usbdescbank_get_STATUS_BK_CRCERR_bit(const void *const hw)
+{
+	return (((UsbDeviceDescBank *)hw)->STATUS_BK.reg & USB_DEVICE_STATUS_BK_CRCERR) >> USB_DEVICE_STATUS_BK_CRCERR_Pos;
+}
+
+static inline void hri_usbdescbank_clear_STATUS_BK_CRCERR_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->STATUS_BK.reg = USB_DEVICE_STATUS_BK_CRCERR;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdescbank_get_STATUS_BK_ERRORFLOW_bit(const void *const hw)
+{
+	return (((UsbDeviceDescBank *)hw)->STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW)
+	       >> USB_DEVICE_STATUS_BK_ERRORFLOW_Pos;
+}
+
+static inline void hri_usbdescbank_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->STATUS_BK.reg = USB_DEVICE_STATUS_BK_ERRORFLOW;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_status_bk_reg_t hri_usbdescbank_get_STATUS_BK_reg(const void *const                hw,
+                                                                                 hri_usbdesc_bank_status_bk_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbDeviceDescBank *)hw)->STATUS_BK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdescbank_clear_STATUS_BK_reg(const void *const hw, hri_usbdesc_bank_status_bk_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescBank *)hw)->STATUS_BK.reg = mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdesc_bank_status_bk_reg_t hri_usbdescbank_read_STATUS_BK_reg(const void *const hw)
+{
+	return ((UsbDeviceDescBank *)hw)->STATUS_BK.reg;
+}
+
+static inline void hri_usbdevicedescriptor_set_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                            hri_usbdescriptordevice_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg |= USB_DEVICE_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_addr_reg_t
+hri_usbdevicedescriptor_get_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index,
+                                         hri_usbdescriptordevice_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg;
+	tmp = (tmp & USB_DEVICE_ADDR_ADDR(mask)) >> USB_DEVICE_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_write_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                              hri_usbdescriptordevice_addr_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg;
+	tmp &= ~USB_DEVICE_ADDR_ADDR_Msk;
+	tmp |= USB_DEVICE_ADDR_ADDR(data);
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_clear_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                              hri_usbdescriptordevice_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg &= ~USB_DEVICE_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_toggle_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index,
+                                                               hri_usbdescriptordevice_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg ^= USB_DEVICE_ADDR_ADDR(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_addr_reg_t hri_usbdevicedescriptor_read_ADDR_ADDR_bf(const void *const hw,
+                                                                                           uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg;
+	tmp = (tmp & USB_DEVICE_ADDR_ADDR_Msk) >> USB_DEVICE_ADDR_ADDR_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_set_ADDR_reg(const void *const hw, uint8_t submodule_index,
+                                                        hri_usbdescriptordevice_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_addr_reg_t
+hri_usbdevicedescriptor_get_ADDR_reg(const void *const hw, uint8_t submodule_index,
+                                     hri_usbdescriptordevice_addr_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_write_ADDR_reg(const void *const hw, uint8_t submodule_index,
+                                                          hri_usbdescriptordevice_addr_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_clear_ADDR_reg(const void *const hw, uint8_t submodule_index,
+                                                          hri_usbdescriptordevice_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_toggle_ADDR_reg(const void *const hw, uint8_t submodule_index,
+                                                           hri_usbdescriptordevice_addr_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_addr_reg_t hri_usbdevicedescriptor_read_ADDR_reg(const void *const hw,
+                                                                                       uint8_t submodule_index)
+{
+	return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg;
+}
+
+static inline void hri_usbdevicedescriptor_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevicedescriptor_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_AUTO_ZLP) >> USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_usbdevicedescriptor_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index,
+                                                                      bool value)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP;
+	tmp |= value << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos;
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_AUTO_ZLP;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index,
+                                                                     hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_pcksize_reg_t
+hri_usbdevicedescriptor_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index,
+                                                  hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT(mask)) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index,
+                                                                       hri_usbdescriptordevice_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk;
+	tmp |= USB_DEVICE_PCKSIZE_BYTE_COUNT(data);
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index,
+                                                                       hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index,
+                                                                        hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_pcksize_reg_t
+hri_usbdevicedescriptor_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw,
+                                                                            uint8_t           submodule_index,
+                                                                            hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg
+	    |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_pcksize_reg_t
+hri_usbdevicedescriptor_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                         hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos;
+	return tmp;
+}
+
+static inline void
+hri_usbdevicedescriptor_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                           hri_usbdescriptordevice_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk;
+	tmp |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(data);
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void
+hri_usbdevicedescriptor_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                           hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg
+	    &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void
+hri_usbdevicedescriptor_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                            hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg
+	    ^= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_pcksize_reg_t
+hri_usbdevicedescriptor_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_set_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                               hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_pcksize_reg_t
+hri_usbdevicedescriptor_get_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                            hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE(mask)) >> USB_DEVICE_PCKSIZE_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_write_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                                 hri_usbdescriptordevice_pcksize_reg_t data)
+{
+	uint32_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp &= ~USB_DEVICE_PCKSIZE_SIZE_Msk;
+	tmp |= USB_DEVICE_PCKSIZE_SIZE(data);
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_clear_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                                 hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index,
+                                                                  hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_SIZE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_pcksize_reg_t
+hri_usbdevicedescriptor_read_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE_Msk) >> USB_DEVICE_PCKSIZE_SIZE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_set_PCKSIZE_reg(const void *const hw, uint8_t submodule_index,
+                                                           hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_pcksize_reg_t
+hri_usbdevicedescriptor_get_PCKSIZE_reg(const void *const hw, uint8_t submodule_index,
+                                        hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_write_PCKSIZE_reg(const void *const hw, uint8_t submodule_index,
+                                                             hri_usbdescriptordevice_pcksize_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_clear_PCKSIZE_reg(const void *const hw, uint8_t submodule_index,
+                                                             hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_reg(const void *const hw, uint8_t submodule_index,
+                                                              hri_usbdescriptordevice_pcksize_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_pcksize_reg_t hri_usbdevicedescriptor_read_PCKSIZE_reg(const void *const hw,
+                                                                                             uint8_t submodule_index)
+{
+	return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg;
+}
+
+static inline void hri_usbdevicedescriptor_set_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index,
+                                                                hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= USB_DEVICE_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_extreg_reg_t
+hri_usbdevicedescriptor_get_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index,
+                                             hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg;
+	tmp = (tmp & USB_DEVICE_EXTREG_SUBPID(mask)) >> USB_DEVICE_EXTREG_SUBPID_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_write_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index,
+                                                                  hri_usbdescriptordevice_extreg_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg;
+	tmp &= ~USB_DEVICE_EXTREG_SUBPID_Msk;
+	tmp |= USB_DEVICE_EXTREG_SUBPID(data);
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_clear_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index,
+                                                                  hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~USB_DEVICE_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_toggle_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index,
+                                                                   hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= USB_DEVICE_EXTREG_SUBPID(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_extreg_reg_t
+hri_usbdevicedescriptor_read_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg;
+	tmp = (tmp & USB_DEVICE_EXTREG_SUBPID_Msk) >> USB_DEVICE_EXTREG_SUBPID_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_set_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index,
+                                                                  hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= USB_DEVICE_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_extreg_reg_t
+hri_usbdevicedescriptor_get_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index,
+                                               hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg;
+	tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE(mask)) >> USB_DEVICE_EXTREG_VARIABLE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_write_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index,
+                                                                    hri_usbdescriptordevice_extreg_reg_t data)
+{
+	uint16_t tmp;
+	USB_CRITICAL_SECTION_ENTER();
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg;
+	tmp &= ~USB_DEVICE_EXTREG_VARIABLE_Msk;
+	tmp |= USB_DEVICE_EXTREG_VARIABLE(data);
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = tmp;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_clear_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index,
+                                                                    hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~USB_DEVICE_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_toggle_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index,
+                                                                     hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= USB_DEVICE_EXTREG_VARIABLE(mask);
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_extreg_reg_t
+hri_usbdevicedescriptor_read_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg;
+	tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE_Msk) >> USB_DEVICE_EXTREG_VARIABLE_Pos;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_set_EXTREG_reg(const void *const hw, uint8_t submodule_index,
+                                                          hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_extreg_reg_t
+hri_usbdevicedescriptor_get_EXTREG_reg(const void *const hw, uint8_t submodule_index,
+                                       hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	uint16_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_write_EXTREG_reg(const void *const hw, uint8_t submodule_index,
+                                                            hri_usbdescriptordevice_extreg_reg_t data)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = data;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_clear_EXTREG_reg(const void *const hw, uint8_t submodule_index,
+                                                            hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_usbdevicedescriptor_toggle_EXTREG_reg(const void *const hw, uint8_t submodule_index,
+                                                             hri_usbdescriptordevice_extreg_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_extreg_reg_t hri_usbdevicedescriptor_read_EXTREG_reg(const void *const hw,
+                                                                                           uint8_t submodule_index)
+{
+	return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg;
+}
+
+static inline bool hri_usbdevicedescriptor_get_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg & USB_DEVICE_STATUS_BK_CRCERR)
+	       >> USB_DEVICE_STATUS_BK_CRCERR_Pos;
+}
+
+static inline void hri_usbdevicedescriptor_clear_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = USB_DEVICE_STATUS_BK_CRCERR;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_usbdevicedescriptor_get_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index)
+{
+	return (((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW)
+	       >> USB_DEVICE_STATUS_BK_ERRORFLOW_Pos;
+}
+
+static inline void hri_usbdevicedescriptor_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = USB_DEVICE_STATUS_BK_ERRORFLOW;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_status_bk_reg_t
+hri_usbdevicedescriptor_get_STATUS_BK_reg(const void *const hw, uint8_t submodule_index,
+                                          hri_usbdescriptordevice_status_bk_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_usbdevicedescriptor_clear_STATUS_BK_reg(const void *const hw, uint8_t submodule_index,
+                                                               hri_usbdescriptordevice_status_bk_reg_t mask)
+{
+	USB_CRITICAL_SECTION_ENTER();
+	((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = mask;
+	USB_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_usbdescriptordevice_status_bk_reg_t
+hri_usbdevicedescriptor_read_STATUS_BK_reg(const void *const hw, uint8_t submodule_index)
+{
+	return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg;
+}
+
+/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */
+#define hri_usbdevice_wait_for_sync(a, b) hri_usb_wait_for_sync(a, b)
+#define hri_usbdevice_is_syncing(a, b) hri_usb_is_syncing(a, b)
+#define hri_usbdevice_set_CTRLA_SWRST_bit(a) hri_usb_set_CTRLA_SWRST_bit(a)
+#define hri_usbdevice_get_CTRLA_SWRST_bit(a) hri_usb_get_CTRLA_SWRST_bit(a)
+#define hri_usbdevice_set_CTRLA_ENABLE_bit(a) hri_usb_set_CTRLA_ENABLE_bit(a)
+#define hri_usbdevice_get_CTRLA_ENABLE_bit(a) hri_usb_get_CTRLA_ENABLE_bit(a)
+#define hri_usbdevice_write_CTRLA_ENABLE_bit(a, b) hri_usb_write_CTRLA_ENABLE_bit(a, b)
+#define hri_usbdevice_clear_CTRLA_ENABLE_bit(a) hri_usb_clear_CTRLA_ENABLE_bit(a)
+#define hri_usbdevice_toggle_CTRLA_ENABLE_bit(a) hri_usb_toggle_CTRLA_ENABLE_bit(a)
+#define hri_usbdevice_set_CTRLA_RUNSTDBY_bit(a) hri_usb_set_CTRLA_RUNSTDBY_bit(a)
+#define hri_usbdevice_get_CTRLA_RUNSTDBY_bit(a) hri_usb_get_CTRLA_RUNSTDBY_bit(a)
+#define hri_usbdevice_write_CTRLA_RUNSTDBY_bit(a, b) hri_usb_write_CTRLA_RUNSTDBY_bit(a, b)
+#define hri_usbdevice_clear_CTRLA_RUNSTDBY_bit(a) hri_usb_clear_CTRLA_RUNSTDBY_bit(a)
+#define hri_usbdevice_toggle_CTRLA_RUNSTDBY_bit(a) hri_usb_toggle_CTRLA_RUNSTDBY_bit(a)
+#define hri_usbdevice_set_CTRLA_MODE_bit(a) hri_usb_set_CTRLA_MODE_bit(a)
+#define hri_usbdevice_get_CTRLA_MODE_bit(a) hri_usb_get_CTRLA_MODE_bit(a)
+#define hri_usbdevice_write_CTRLA_MODE_bit(a, b) hri_usb_write_CTRLA_MODE_bit(a, b)
+#define hri_usbdevice_clear_CTRLA_MODE_bit(a) hri_usb_clear_CTRLA_MODE_bit(a)
+#define hri_usbdevice_toggle_CTRLA_MODE_bit(a) hri_usb_toggle_CTRLA_MODE_bit(a)
+#define hri_usbdevice_set_CTRLA_reg(a, b) hri_usb_set_CTRLA_reg(a, b)
+#define hri_usbdevice_get_CTRLA_reg(a, b) hri_usb_get_CTRLA_reg(a, b)
+#define hri_usbdevice_write_CTRLA_reg(a, b) hri_usb_write_CTRLA_reg(a, b)
+#define hri_usbdevice_clear_CTRLA_reg(a, b) hri_usb_clear_CTRLA_reg(a, b)
+#define hri_usbdevice_toggle_CTRLA_reg(a, b) hri_usb_toggle_CTRLA_reg(a, b)
+#define hri_usbdevice_read_CTRLA_reg(a) hri_usb_read_CTRLA_reg(a)
+#define hri_usbdevice_set_QOSCTRL_CQOS_bf(a, b) hri_usb_set_QOSCTRL_CQOS_bf(a, b)
+#define hri_usbdevice_get_QOSCTRL_CQOS_bf(a, b) hri_usb_get_QOSCTRL_CQOS_bf(a, b)
+#define hri_usbdevice_write_QOSCTRL_CQOS_bf(a, b) hri_usb_write_QOSCTRL_CQOS_bf(a, b)
+#define hri_usbdevice_clear_QOSCTRL_CQOS_bf(a, b) hri_usb_clear_QOSCTRL_CQOS_bf(a, b)
+#define hri_usbdevice_toggle_QOSCTRL_CQOS_bf(a, b) hri_usb_toggle_QOSCTRL_CQOS_bf(a, b)
+#define hri_usbdevice_read_QOSCTRL_CQOS_bf(a) hri_usb_read_QOSCTRL_CQOS_bf(a)
+#define hri_usbdevice_set_QOSCTRL_DQOS_bf(a, b) hri_usb_set_QOSCTRL_DQOS_bf(a, b)
+#define hri_usbdevice_get_QOSCTRL_DQOS_bf(a, b) hri_usb_get_QOSCTRL_DQOS_bf(a, b)
+#define hri_usbdevice_write_QOSCTRL_DQOS_bf(a, b) hri_usb_write_QOSCTRL_DQOS_bf(a, b)
+#define hri_usbdevice_clear_QOSCTRL_DQOS_bf(a, b) hri_usb_clear_QOSCTRL_DQOS_bf(a, b)
+#define hri_usbdevice_toggle_QOSCTRL_DQOS_bf(a, b) hri_usb_toggle_QOSCTRL_DQOS_bf(a, b)
+#define hri_usbdevice_read_QOSCTRL_DQOS_bf(a) hri_usb_read_QOSCTRL_DQOS_bf(a)
+#define hri_usbdevice_set_QOSCTRL_reg(a, b) hri_usb_set_QOSCTRL_reg(a, b)
+#define hri_usbdevice_get_QOSCTRL_reg(a, b) hri_usb_get_QOSCTRL_reg(a, b)
+#define hri_usbdevice_write_QOSCTRL_reg(a, b) hri_usb_write_QOSCTRL_reg(a, b)
+#define hri_usbdevice_clear_QOSCTRL_reg(a, b) hri_usb_clear_QOSCTRL_reg(a, b)
+#define hri_usbdevice_toggle_QOSCTRL_reg(a, b) hri_usb_toggle_QOSCTRL_reg(a, b)
+#define hri_usbdevice_read_QOSCTRL_reg(a) hri_usb_read_QOSCTRL_reg(a)
+#define hri_usbdevice_set_DESCADD_DESCADD_bf(a, b) hri_usb_set_DESCADD_DESCADD_bf(a, b)
+#define hri_usbdevice_get_DESCADD_DESCADD_bf(a, b) hri_usb_get_DESCADD_DESCADD_bf(a, b)
+#define hri_usbdevice_write_DESCADD_DESCADD_bf(a, b) hri_usb_write_DESCADD_DESCADD_bf(a, b)
+#define hri_usbdevice_clear_DESCADD_DESCADD_bf(a, b) hri_usb_clear_DESCADD_DESCADD_bf(a, b)
+#define hri_usbdevice_toggle_DESCADD_DESCADD_bf(a, b) hri_usb_toggle_DESCADD_DESCADD_bf(a, b)
+#define hri_usbdevice_read_DESCADD_DESCADD_bf(a) hri_usb_read_DESCADD_DESCADD_bf(a)
+#define hri_usbdevice_set_DESCADD_reg(a, b) hri_usb_set_DESCADD_reg(a, b)
+#define hri_usbdevice_get_DESCADD_reg(a, b) hri_usb_get_DESCADD_reg(a, b)
+#define hri_usbdevice_write_DESCADD_reg(a, b) hri_usb_write_DESCADD_reg(a, b)
+#define hri_usbdevice_clear_DESCADD_reg(a, b) hri_usb_clear_DESCADD_reg(a, b)
+#define hri_usbdevice_toggle_DESCADD_reg(a, b) hri_usb_toggle_DESCADD_reg(a, b)
+#define hri_usbdevice_read_DESCADD_reg(a) hri_usb_read_DESCADD_reg(a)
+#define hri_usbdevice_set_PADCAL_TRANSP_bf(a, b) hri_usb_set_PADCAL_TRANSP_bf(a, b)
+#define hri_usbdevice_get_PADCAL_TRANSP_bf(a, b) hri_usb_get_PADCAL_TRANSP_bf(a, b)
+#define hri_usbdevice_write_PADCAL_TRANSP_bf(a, b) hri_usb_write_PADCAL_TRANSP_bf(a, b)
+#define hri_usbdevice_clear_PADCAL_TRANSP_bf(a, b) hri_usb_clear_PADCAL_TRANSP_bf(a, b)
+#define hri_usbdevice_toggle_PADCAL_TRANSP_bf(a, b) hri_usb_toggle_PADCAL_TRANSP_bf(a, b)
+#define hri_usbdevice_read_PADCAL_TRANSP_bf(a) hri_usb_read_PADCAL_TRANSP_bf(a)
+#define hri_usbdevice_set_PADCAL_TRANSN_bf(a, b) hri_usb_set_PADCAL_TRANSN_bf(a, b)
+#define hri_usbdevice_get_PADCAL_TRANSN_bf(a, b) hri_usb_get_PADCAL_TRANSN_bf(a, b)
+#define hri_usbdevice_write_PADCAL_TRANSN_bf(a, b) hri_usb_write_PADCAL_TRANSN_bf(a, b)
+#define hri_usbdevice_clear_PADCAL_TRANSN_bf(a, b) hri_usb_clear_PADCAL_TRANSN_bf(a, b)
+#define hri_usbdevice_toggle_PADCAL_TRANSN_bf(a, b) hri_usb_toggle_PADCAL_TRANSN_bf(a, b)
+#define hri_usbdevice_read_PADCAL_TRANSN_bf(a) hri_usb_read_PADCAL_TRANSN_bf(a)
+#define hri_usbdevice_set_PADCAL_TRIM_bf(a, b) hri_usb_set_PADCAL_TRIM_bf(a, b)
+#define hri_usbdevice_get_PADCAL_TRIM_bf(a, b) hri_usb_get_PADCAL_TRIM_bf(a, b)
+#define hri_usbdevice_write_PADCAL_TRIM_bf(a, b) hri_usb_write_PADCAL_TRIM_bf(a, b)
+#define hri_usbdevice_clear_PADCAL_TRIM_bf(a, b) hri_usb_clear_PADCAL_TRIM_bf(a, b)
+#define hri_usbdevice_toggle_PADCAL_TRIM_bf(a, b) hri_usb_toggle_PADCAL_TRIM_bf(a, b)
+#define hri_usbdevice_read_PADCAL_TRIM_bf(a) hri_usb_read_PADCAL_TRIM_bf(a)
+#define hri_usbdevice_set_PADCAL_reg(a, b) hri_usb_set_PADCAL_reg(a, b)
+#define hri_usbdevice_get_PADCAL_reg(a, b) hri_usb_get_PADCAL_reg(a, b)
+#define hri_usbdevice_write_PADCAL_reg(a, b) hri_usb_write_PADCAL_reg(a, b)
+#define hri_usbdevice_clear_PADCAL_reg(a, b) hri_usb_clear_PADCAL_reg(a, b)
+#define hri_usbdevice_toggle_PADCAL_reg(a, b) hri_usb_toggle_PADCAL_reg(a, b)
+#define hri_usbdevice_read_PADCAL_reg(a) hri_usb_read_PADCAL_reg(a)
+#define hri_usbdevice_get_SYNCBUSY_SWRST_bit(a) hri_usb_get_SYNCBUSY_SWRST_bit(a)
+#define hri_usbdevice_get_SYNCBUSY_ENABLE_bit(a) hri_usb_get_SYNCBUSY_ENABLE_bit(a)
+#define hri_usbdevice_get_SYNCBUSY_reg(a, b) hri_usb_get_SYNCBUSY_reg(a, b)
+#define hri_usbdevice_read_SYNCBUSY_reg(a) hri_usb_read_SYNCBUSY_reg(a)
+#define hri_usbdevice_get_FSMSTATUS_FSMSTATE_bf(a, b) hri_usb_get_FSMSTATUS_FSMSTATE_bf(a, b)
+#define hri_usbdevice_read_FSMSTATUS_FSMSTATE_bf(a) hri_usb_read_FSMSTATUS_FSMSTATE_bf(a)
+#define hri_usbdevice_get_FSMSTATUS_reg(a, b) hri_usb_get_FSMSTATUS_reg(a, b)
+#define hri_usbdevice_read_FSMSTATUS_reg(a) hri_usb_read_FSMSTATUS_reg(a)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_USB_L22_H_INCLUDED */
+#endif /* _SAML22_USB_COMPONENT_ */
diff --git a/watch-library/hardware/hri/hri_wdt_l22.h b/watch-library/hardware/hri/hri_wdt_l22.h
new file mode 100644
index 00000000..4794b254
--- /dev/null
+++ b/watch-library/hardware/hri/hri_wdt_l22.h
@@ -0,0 +1,617 @@
+/**
+ * \file
+ *
+ * \brief SAM WDT
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifdef _SAML22_WDT_COMPONENT_
+#ifndef _HRI_WDT_L22_H_INCLUDED_
+#define _HRI_WDT_L22_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <hal_atomic.h>
+
+#if defined(ENABLE_WDT_CRITICAL_SECTIONS)
+#define WDT_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
+#define WDT_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
+#else
+#define WDT_CRITICAL_SECTION_ENTER()
+#define WDT_CRITICAL_SECTION_LEAVE()
+#endif
+
+typedef uint32_t hri_wdt_syncbusy_reg_t;
+typedef uint8_t  hri_wdt_clear_reg_t;
+typedef uint8_t  hri_wdt_config_reg_t;
+typedef uint8_t  hri_wdt_ctrla_reg_t;
+typedef uint8_t  hri_wdt_ewctrl_reg_t;
+typedef uint8_t  hri_wdt_intenset_reg_t;
+typedef uint8_t  hri_wdt_intflag_reg_t;
+
+static inline void hri_wdt_wait_for_sync(const void *const hw, hri_wdt_syncbusy_reg_t reg)
+{
+	while (((Wdt *)hw)->SYNCBUSY.reg & reg) {
+	};
+}
+
+static inline bool hri_wdt_is_syncing(const void *const hw, hri_wdt_syncbusy_reg_t reg)
+{
+	return ((Wdt *)hw)->SYNCBUSY.reg & reg;
+}
+
+static inline bool hri_wdt_get_INTFLAG_EW_bit(const void *const hw)
+{
+	return (((Wdt *)hw)->INTFLAG.reg & WDT_INTFLAG_EW) >> WDT_INTFLAG_EW_Pos;
+}
+
+static inline void hri_wdt_clear_INTFLAG_EW_bit(const void *const hw)
+{
+	((Wdt *)hw)->INTFLAG.reg = WDT_INTFLAG_EW;
+}
+
+static inline bool hri_wdt_get_interrupt_EW_bit(const void *const hw)
+{
+	return (((Wdt *)hw)->INTFLAG.reg & WDT_INTFLAG_EW) >> WDT_INTFLAG_EW_Pos;
+}
+
+static inline void hri_wdt_clear_interrupt_EW_bit(const void *const hw)
+{
+	((Wdt *)hw)->INTFLAG.reg = WDT_INTFLAG_EW;
+}
+
+static inline hri_wdt_intflag_reg_t hri_wdt_get_INTFLAG_reg(const void *const hw, hri_wdt_intflag_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->INTFLAG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_wdt_intflag_reg_t hri_wdt_read_INTFLAG_reg(const void *const hw)
+{
+	return ((Wdt *)hw)->INTFLAG.reg;
+}
+
+static inline void hri_wdt_clear_INTFLAG_reg(const void *const hw, hri_wdt_intflag_reg_t mask)
+{
+	((Wdt *)hw)->INTFLAG.reg = mask;
+}
+
+static inline void hri_wdt_set_INTEN_EW_bit(const void *const hw)
+{
+	((Wdt *)hw)->INTENSET.reg = WDT_INTENSET_EW;
+}
+
+static inline bool hri_wdt_get_INTEN_EW_bit(const void *const hw)
+{
+	return (((Wdt *)hw)->INTENSET.reg & WDT_INTENSET_EW) >> WDT_INTENSET_EW_Pos;
+}
+
+static inline void hri_wdt_write_INTEN_EW_bit(const void *const hw, bool value)
+{
+	if (value == 0x0) {
+		((Wdt *)hw)->INTENCLR.reg = WDT_INTENSET_EW;
+	} else {
+		((Wdt *)hw)->INTENSET.reg = WDT_INTENSET_EW;
+	}
+}
+
+static inline void hri_wdt_clear_INTEN_EW_bit(const void *const hw)
+{
+	((Wdt *)hw)->INTENCLR.reg = WDT_INTENSET_EW;
+}
+
+static inline void hri_wdt_set_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask)
+{
+	((Wdt *)hw)->INTENSET.reg = mask;
+}
+
+static inline hri_wdt_intenset_reg_t hri_wdt_get_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->INTENSET.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_wdt_intenset_reg_t hri_wdt_read_INTEN_reg(const void *const hw)
+{
+	return ((Wdt *)hw)->INTENSET.reg;
+}
+
+static inline void hri_wdt_write_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t data)
+{
+	((Wdt *)hw)->INTENSET.reg = data;
+	((Wdt *)hw)->INTENCLR.reg = ~data;
+}
+
+static inline void hri_wdt_clear_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask)
+{
+	((Wdt *)hw)->INTENCLR.reg = mask;
+}
+
+static inline bool hri_wdt_get_SYNCBUSY_ENABLE_bit(const void *const hw)
+{
+	return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_ENABLE) >> WDT_SYNCBUSY_ENABLE_Pos;
+}
+
+static inline bool hri_wdt_get_SYNCBUSY_WEN_bit(const void *const hw)
+{
+	return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_WEN) >> WDT_SYNCBUSY_WEN_Pos;
+}
+
+static inline bool hri_wdt_get_SYNCBUSY_ALWAYSON_bit(const void *const hw)
+{
+	return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_ALWAYSON) >> WDT_SYNCBUSY_ALWAYSON_Pos;
+}
+
+static inline bool hri_wdt_get_SYNCBUSY_CLEAR_bit(const void *const hw)
+{
+	return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_CLEAR) >> WDT_SYNCBUSY_CLEAR_Pos;
+}
+
+static inline hri_wdt_syncbusy_reg_t hri_wdt_get_SYNCBUSY_reg(const void *const hw, hri_wdt_syncbusy_reg_t mask)
+{
+	uint32_t tmp;
+	tmp = ((Wdt *)hw)->SYNCBUSY.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline hri_wdt_syncbusy_reg_t hri_wdt_read_SYNCBUSY_reg(const void *const hw)
+{
+	return ((Wdt *)hw)->SYNCBUSY.reg;
+}
+
+static inline void hri_wdt_set_CTRLA_ENABLE_bit(const void *const hw)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_ENABLE;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_wdt_get_CTRLA_ENABLE_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	tmp = ((Wdt *)hw)->CTRLA.reg;
+	tmp = (tmp & WDT_CTRLA_ENABLE) >> WDT_CTRLA_ENABLE_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_wdt_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	WDT_CRITICAL_SECTION_ENTER();
+	tmp = ((Wdt *)hw)->CTRLA.reg;
+	tmp &= ~WDT_CTRLA_ENABLE;
+	tmp |= value << WDT_CTRLA_ENABLE_Pos;
+	((Wdt *)hw)->CTRLA.reg = tmp;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_clear_CTRLA_ENABLE_bit(const void *const hw)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_ENABLE;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_toggle_CTRLA_ENABLE_bit(const void *const hw)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_ENABLE;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_set_CTRLA_WEN_bit(const void *const hw)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_WEN;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_wdt_get_CTRLA_WEN_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	tmp = ((Wdt *)hw)->CTRLA.reg;
+	tmp = (tmp & WDT_CTRLA_WEN) >> WDT_CTRLA_WEN_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_wdt_write_CTRLA_WEN_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	WDT_CRITICAL_SECTION_ENTER();
+	tmp = ((Wdt *)hw)->CTRLA.reg;
+	tmp &= ~WDT_CTRLA_WEN;
+	tmp |= value << WDT_CTRLA_WEN_Pos;
+	((Wdt *)hw)->CTRLA.reg = tmp;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_clear_CTRLA_WEN_bit(const void *const hw)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_WEN;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_toggle_CTRLA_WEN_bit(const void *const hw)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_WEN;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_set_CTRLA_ALWAYSON_bit(const void *const hw)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_ALWAYSON;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline bool hri_wdt_get_CTRLA_ALWAYSON_bit(const void *const hw)
+{
+	uint8_t tmp;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	tmp = ((Wdt *)hw)->CTRLA.reg;
+	tmp = (tmp & WDT_CTRLA_ALWAYSON) >> WDT_CTRLA_ALWAYSON_Pos;
+	return (bool)tmp;
+}
+
+static inline void hri_wdt_write_CTRLA_ALWAYSON_bit(const void *const hw, bool value)
+{
+	uint8_t tmp;
+	WDT_CRITICAL_SECTION_ENTER();
+	tmp = ((Wdt *)hw)->CTRLA.reg;
+	tmp &= ~WDT_CTRLA_ALWAYSON;
+	tmp |= value << WDT_CTRLA_ALWAYSON_Pos;
+	((Wdt *)hw)->CTRLA.reg = tmp;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_clear_CTRLA_ALWAYSON_bit(const void *const hw)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_ALWAYSON;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_toggle_CTRLA_ALWAYSON_bit(const void *const hw)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_ALWAYSON;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_set_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg |= mask;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_ctrla_reg_t hri_wdt_get_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask)
+{
+	uint8_t tmp;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	tmp = ((Wdt *)hw)->CTRLA.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_wdt_write_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t data)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg = data;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_clear_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg &= ~mask;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_toggle_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CTRLA.reg ^= mask;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_ctrla_reg_t hri_wdt_read_CTRLA_reg(const void *const hw)
+{
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
+	return ((Wdt *)hw)->CTRLA.reg;
+}
+
+static inline void hri_wdt_set_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CONFIG.reg |= WDT_CONFIG_PER(mask);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->CONFIG.reg;
+	tmp = (tmp & WDT_CONFIG_PER(mask)) >> WDT_CONFIG_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_wdt_write_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t data)
+{
+	uint8_t tmp;
+	WDT_CRITICAL_SECTION_ENTER();
+	tmp = ((Wdt *)hw)->CONFIG.reg;
+	tmp &= ~WDT_CONFIG_PER_Msk;
+	tmp |= WDT_CONFIG_PER(data);
+	((Wdt *)hw)->CONFIG.reg = tmp;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_clear_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CONFIG.reg &= ~WDT_CONFIG_PER(mask);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_toggle_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CONFIG.reg ^= WDT_CONFIG_PER(mask);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_PER_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->CONFIG.reg;
+	tmp = (tmp & WDT_CONFIG_PER_Msk) >> WDT_CONFIG_PER_Pos;
+	return tmp;
+}
+
+static inline void hri_wdt_set_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CONFIG.reg |= WDT_CONFIG_WINDOW(mask);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->CONFIG.reg;
+	tmp = (tmp & WDT_CONFIG_WINDOW(mask)) >> WDT_CONFIG_WINDOW_Pos;
+	return tmp;
+}
+
+static inline void hri_wdt_write_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t data)
+{
+	uint8_t tmp;
+	WDT_CRITICAL_SECTION_ENTER();
+	tmp = ((Wdt *)hw)->CONFIG.reg;
+	tmp &= ~WDT_CONFIG_WINDOW_Msk;
+	tmp |= WDT_CONFIG_WINDOW(data);
+	((Wdt *)hw)->CONFIG.reg = tmp;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_clear_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CONFIG.reg &= ~WDT_CONFIG_WINDOW(mask);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_toggle_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CONFIG.reg ^= WDT_CONFIG_WINDOW(mask);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_WINDOW_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->CONFIG.reg;
+	tmp = (tmp & WDT_CONFIG_WINDOW_Msk) >> WDT_CONFIG_WINDOW_Pos;
+	return tmp;
+}
+
+static inline void hri_wdt_set_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CONFIG.reg |= mask;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->CONFIG.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_wdt_write_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t data)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CONFIG.reg = data;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_clear_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CONFIG.reg &= ~mask;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_toggle_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CONFIG.reg ^= mask;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_reg(const void *const hw)
+{
+	return ((Wdt *)hw)->CONFIG.reg;
+}
+
+static inline void hri_wdt_set_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->EWCTRL.reg |= WDT_EWCTRL_EWOFFSET(mask);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_ewctrl_reg_t hri_wdt_get_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->EWCTRL.reg;
+	tmp = (tmp & WDT_EWCTRL_EWOFFSET(mask)) >> WDT_EWCTRL_EWOFFSET_Pos;
+	return tmp;
+}
+
+static inline void hri_wdt_write_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t data)
+{
+	uint8_t tmp;
+	WDT_CRITICAL_SECTION_ENTER();
+	tmp = ((Wdt *)hw)->EWCTRL.reg;
+	tmp &= ~WDT_EWCTRL_EWOFFSET_Msk;
+	tmp |= WDT_EWCTRL_EWOFFSET(data);
+	((Wdt *)hw)->EWCTRL.reg = tmp;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_clear_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->EWCTRL.reg &= ~WDT_EWCTRL_EWOFFSET(mask);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_toggle_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->EWCTRL.reg ^= WDT_EWCTRL_EWOFFSET(mask);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_ewctrl_reg_t hri_wdt_read_EWCTRL_EWOFFSET_bf(const void *const hw)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->EWCTRL.reg;
+	tmp = (tmp & WDT_EWCTRL_EWOFFSET_Msk) >> WDT_EWCTRL_EWOFFSET_Pos;
+	return tmp;
+}
+
+static inline void hri_wdt_set_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->EWCTRL.reg |= mask;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_ewctrl_reg_t hri_wdt_get_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask)
+{
+	uint8_t tmp;
+	tmp = ((Wdt *)hw)->EWCTRL.reg;
+	tmp &= mask;
+	return tmp;
+}
+
+static inline void hri_wdt_write_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t data)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->EWCTRL.reg = data;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_clear_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->EWCTRL.reg &= ~mask;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline void hri_wdt_toggle_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->EWCTRL.reg ^= mask;
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+static inline hri_wdt_ewctrl_reg_t hri_wdt_read_EWCTRL_reg(const void *const hw)
+{
+	return ((Wdt *)hw)->EWCTRL.reg;
+}
+
+static inline void hri_wdt_write_CLEAR_reg(const void *const hw, hri_wdt_clear_reg_t data)
+{
+	WDT_CRITICAL_SECTION_ENTER();
+	((Wdt *)hw)->CLEAR.reg = data;
+	hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_CLEAR);
+	WDT_CRITICAL_SECTION_LEAVE();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HRI_WDT_L22_H_INCLUDED */
+#endif /* _SAML22_WDT_COMPONENT_ */