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| author | Alexsander Akers <me@a2.io> | 2022-01-25 15:03:22 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-01-25 15:03:22 -0500 |
| commit | b8de35658ffd78ad8b22f91ccbbd3d63663afda9 (patch) | |
| tree | 1f265ddfcc8e5abf0316b81b15f80bf5c70fa7b7 /watch-library/include/instance | |
| parent | 9e24f6c336773c7404139ab4db0eaab2f99504e2 (diff) | |
| download | Sensor-Watch-b8de35658ffd78ad8b22f91ccbbd3d63663afda9.tar.gz Sensor-Watch-b8de35658ffd78ad8b22f91ccbbd3d63663afda9.tar.bz2 Sensor-Watch-b8de35658ffd78ad8b22f91ccbbd3d63663afda9.zip | |
Sensor Watch Simulator (#35)
* Put something on screen
* Use the 32bit watch_date_time repr to pass from JS
* Implement periodic callbacks
* Clear display on enabling
* Hook up watch_set_led_color() to SVG (green-only)
* Make debug output full-width
* Remove default Emscripten canvas
* Implement sleep and button clicks
* Fix time zone conversion bug in beats-time app
* Clean up warnings
* Fix pin levels
* Set time zone to browser value (if available)
* Add basic backup data saving
* Silence format specifier warnings in both targets
* Remove unnecessary, copied files
* Use RTC pointer to clear callbacks (if available)
* Use preprocessor define to avoid hardcoding MOVEMENT_NUM_FACES
* Change each face to const preprocessor definition
* Remove Intl.DateTimeFormat usage
* Update shell.html title, header
* Add touch start/end event handlers on SVG buttons
* Update shell.html
* Update folder structure (shared, simulator, hardware under watch-library)
* Tease out shared components from watch_slcd
* Clean up simulator watch_slcd.c inline JS calls
* Fix missing newlines at end of file
* Add simulator warnings (except format, unused-paremter)
* Implement remaining watch_rtc functions
* Fix button bug on mouse down then drag out
* Implement remaining watch_slcd functions
* Link keyboard events to buttons (for keys A, L, M)
* Rewrite event handling (mouse, touch, keyboard) in C
* Set explicit text UTF-8 charset in shell.html
* Address PR comments
* Remove unused directories from include paths
Diffstat (limited to 'watch-library/include/instance')
37 files changed, 0 insertions, 3793 deletions
diff --git a/watch-library/include/instance/ac.h b/watch-library/include/instance/ac.h deleted file mode 100644 index d2bf7fb9..00000000 --- a/watch-library/include/instance/ac.h +++ /dev/null @@ -1,74 +0,0 @@ -/** - * \file - * - * \brief Instance description for AC - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_AC_INSTANCE_ -#define _SAML22_AC_INSTANCE_ - -/* ========== Register definition for AC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_AC_CTRLA (0x42003400) /**< \brief (AC) Control A */ -#define REG_AC_CTRLB (0x42003401) /**< \brief (AC) Control B */ -#define REG_AC_EVCTRL (0x42003402) /**< \brief (AC) Event Control */ -#define REG_AC_INTENCLR (0x42003404) /**< \brief (AC) Interrupt Enable Clear */ -#define REG_AC_INTENSET (0x42003405) /**< \brief (AC) Interrupt Enable Set */ -#define REG_AC_INTFLAG (0x42003406) /**< \brief (AC) Interrupt Flag Status and Clear */ -#define REG_AC_STATUSA (0x42003407) /**< \brief (AC) Status A */ -#define REG_AC_STATUSB (0x42003408) /**< \brief (AC) Status B */ -#define REG_AC_DBGCTRL (0x42003409) /**< \brief (AC) Debug Control */ -#define REG_AC_WINCTRL (0x4200340A) /**< \brief (AC) Window Control */ -#define REG_AC_SCALER0 (0x4200340C) /**< \brief (AC) Scaler 0 */ -#define REG_AC_SCALER1 (0x4200340D) /**< \brief (AC) Scaler 1 */ -#define REG_AC_COMPCTRL0 (0x42003410) /**< \brief (AC) Comparator Control 0 */ -#define REG_AC_COMPCTRL1 (0x42003414) /**< \brief (AC) Comparator Control 1 */ -#define REG_AC_SYNCBUSY (0x42003420) /**< \brief (AC) Synchronization Busy */ -#else -#define REG_AC_CTRLA (*(RwReg8 *)0x42003400UL) /**< \brief (AC) Control A */ -#define REG_AC_CTRLB (*(WoReg8 *)0x42003401UL) /**< \brief (AC) Control B */ -#define REG_AC_EVCTRL (*(RwReg16*)0x42003402UL) /**< \brief (AC) Event Control */ -#define REG_AC_INTENCLR (*(RwReg8 *)0x42003404UL) /**< \brief (AC) Interrupt Enable Clear */ -#define REG_AC_INTENSET (*(RwReg8 *)0x42003405UL) /**< \brief (AC) Interrupt Enable Set */ -#define REG_AC_INTFLAG (*(RwReg8 *)0x42003406UL) /**< \brief (AC) Interrupt Flag Status and Clear */ -#define REG_AC_STATUSA (*(RoReg8 *)0x42003407UL) /**< \brief (AC) Status A */ -#define REG_AC_STATUSB (*(RoReg8 *)0x42003408UL) /**< \brief (AC) Status B */ -#define REG_AC_DBGCTRL (*(RwReg8 *)0x42003409UL) /**< \brief (AC) Debug Control */ -#define REG_AC_WINCTRL (*(RwReg8 *)0x4200340AUL) /**< \brief (AC) Window Control */ -#define REG_AC_SCALER0 (*(RwReg8 *)0x4200340CUL) /**< \brief (AC) Scaler 0 */ -#define REG_AC_SCALER1 (*(RwReg8 *)0x4200340DUL) /**< \brief (AC) Scaler 1 */ -#define REG_AC_COMPCTRL0 (*(RwReg *)0x42003410UL) /**< \brief (AC) Comparator Control 0 */ -#define REG_AC_COMPCTRL1 (*(RwReg *)0x42003414UL) /**< \brief (AC) Comparator Control 1 */ -#define REG_AC_SYNCBUSY (*(RoReg *)0x42003420UL) /**< \brief (AC) Synchronization Busy */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for AC peripheral ========== */ -#define AC_COMPCTRL_MUXNEG_OPAMP 7 // OPAMP selection for MUXNEG -#define AC_GCLK_ID 26 // Index of Generic Clock -#define AC_NUM_CMP 2 // Number of comparators -#define AC_PAIRS 1 // Number of pairs of comparators - -#endif /* _SAML22_AC_INSTANCE_ */ diff --git a/watch-library/include/instance/adc.h b/watch-library/include/instance/adc.h deleted file mode 100644 index 593cf070..00000000 --- a/watch-library/include/instance/adc.h +++ /dev/null @@ -1,89 +0,0 @@ -/** - * \file - * - * \brief Instance description for ADC - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_ADC_INSTANCE_ -#define _SAML22_ADC_INSTANCE_ - -/* ========== Register definition for ADC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_ADC_CTRLA (0x42003000) /**< \brief (ADC) Control A */ -#define REG_ADC_CTRLB (0x42003001) /**< \brief (ADC) Control B */ -#define REG_ADC_REFCTRL (0x42003002) /**< \brief (ADC) Reference Control */ -#define REG_ADC_EVCTRL (0x42003003) /**< \brief (ADC) Event Control */ -#define REG_ADC_INTENCLR (0x42003004) /**< \brief (ADC) Interrupt Enable Clear */ -#define REG_ADC_INTENSET (0x42003005) /**< \brief (ADC) Interrupt Enable Set */ -#define REG_ADC_INTFLAG (0x42003006) /**< \brief (ADC) Interrupt Flag Status and Clear */ -#define REG_ADC_SEQSTATUS (0x42003007) /**< \brief (ADC) Sequence Status */ -#define REG_ADC_INPUTCTRL (0x42003008) /**< \brief (ADC) Input Control */ -#define REG_ADC_CTRLC (0x4200300A) /**< \brief (ADC) Control C */ -#define REG_ADC_AVGCTRL (0x4200300C) /**< \brief (ADC) Average Control */ -#define REG_ADC_SAMPCTRL (0x4200300D) /**< \brief (ADC) Sample Time Control */ -#define REG_ADC_WINLT (0x4200300E) /**< \brief (ADC) Window Monitor Lower Threshold */ -#define REG_ADC_WINUT (0x42003010) /**< \brief (ADC) Window Monitor Upper Threshold */ -#define REG_ADC_GAINCORR (0x42003012) /**< \brief (ADC) Gain Correction */ -#define REG_ADC_OFFSETCORR (0x42003014) /**< \brief (ADC) Offset Correction */ -#define REG_ADC_SWTRIG (0x42003018) /**< \brief (ADC) Software Trigger */ -#define REG_ADC_DBGCTRL (0x4200301C) /**< \brief (ADC) Debug Control */ -#define REG_ADC_SYNCBUSY (0x42003020) /**< \brief (ADC) Synchronization Busy */ -#define REG_ADC_RESULT (0x42003024) /**< \brief (ADC) Result */ -#define REG_ADC_SEQCTRL (0x42003028) /**< \brief (ADC) Sequence Control */ -#define REG_ADC_CALIB (0x4200302C) /**< \brief (ADC) Calibration */ -#else -#define REG_ADC_CTRLA (*(RwReg8 *)0x42003000UL) /**< \brief (ADC) Control A */ -#define REG_ADC_CTRLB (*(RwReg8 *)0x42003001UL) /**< \brief (ADC) Control B */ -#define REG_ADC_REFCTRL (*(RwReg8 *)0x42003002UL) /**< \brief (ADC) Reference Control */ -#define REG_ADC_EVCTRL (*(RwReg8 *)0x42003003UL) /**< \brief (ADC) Event Control */ -#define REG_ADC_INTENCLR (*(RwReg8 *)0x42003004UL) /**< \brief (ADC) Interrupt Enable Clear */ -#define REG_ADC_INTENSET (*(RwReg8 *)0x42003005UL) /**< \brief (ADC) Interrupt Enable Set */ -#define REG_ADC_INTFLAG (*(RwReg8 *)0x42003006UL) /**< \brief (ADC) Interrupt Flag Status and Clear */ -#define REG_ADC_SEQSTATUS (*(RoReg8 *)0x42003007UL) /**< \brief (ADC) Sequence Status */ -#define REG_ADC_INPUTCTRL (*(RwReg16*)0x42003008UL) /**< \brief (ADC) Input Control */ -#define REG_ADC_CTRLC (*(RwReg16*)0x4200300AUL) /**< \brief (ADC) Control C */ -#define REG_ADC_AVGCTRL (*(RwReg8 *)0x4200300CUL) /**< \brief (ADC) Average Control */ -#define REG_ADC_SAMPCTRL (*(RwReg8 *)0x4200300DUL) /**< \brief (ADC) Sample Time Control */ -#define REG_ADC_WINLT (*(RwReg16*)0x4200300EUL) /**< \brief (ADC) Window Monitor Lower Threshold */ -#define REG_ADC_WINUT (*(RwReg16*)0x42003010UL) /**< \brief (ADC) Window Monitor Upper Threshold */ -#define REG_ADC_GAINCORR (*(RwReg16*)0x42003012UL) /**< \brief (ADC) Gain Correction */ -#define REG_ADC_OFFSETCORR (*(RwReg16*)0x42003014UL) /**< \brief (ADC) Offset Correction */ -#define REG_ADC_SWTRIG (*(RwReg8 *)0x42003018UL) /**< \brief (ADC) Software Trigger */ -#define REG_ADC_DBGCTRL (*(RwReg8 *)0x4200301CUL) /**< \brief (ADC) Debug Control */ -#define REG_ADC_SYNCBUSY (*(RoReg16*)0x42003020UL) /**< \brief (ADC) Synchronization Busy */ -#define REG_ADC_RESULT (*(RoReg16*)0x42003024UL) /**< \brief (ADC) Result */ -#define REG_ADC_SEQCTRL (*(RwReg *)0x42003028UL) /**< \brief (ADC) Sequence Control */ -#define REG_ADC_CALIB (*(RwReg16*)0x4200302CUL) /**< \brief (ADC) Calibration */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for ADC peripheral ========== */ -#define ADC_DMAC_ID_RESRDY 31 // index of DMA RESRDY trigger -#define ADC_EXTCHANNEL_MSB 19 // Number of external channels -#define ADC_GCLK_ID 25 // index of Generic Clock -#define ADC_INT_CH30 2 // Select OPAMP or CTAT on Channel 30 -#define ADC_MASTER_SLAVE_MODE 0 // ADC Master/Slave Mode - -#endif /* _SAML22_ADC_INSTANCE_ */ diff --git a/watch-library/include/instance/aes.h b/watch-library/include/instance/aes.h deleted file mode 100644 index 1d39e171..00000000 --- a/watch-library/include/instance/aes.h +++ /dev/null @@ -1,102 +0,0 @@ -/** - * \file - * - * \brief Instance description for AES - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_AES_INSTANCE_ -#define _SAML22_AES_INSTANCE_ - -/* ========== Register definition for AES peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_AES_CTRLA (0x42004000) /**< \brief (AES) Control A */ -#define REG_AES_CTRLB (0x42004004) /**< \brief (AES) Control B */ -#define REG_AES_INTENCLR (0x42004005) /**< \brief (AES) Interrupt Enable Clear */ -#define REG_AES_INTENSET (0x42004006) /**< \brief (AES) Interrupt Enable Set */ -#define REG_AES_INTFLAG (0x42004007) /**< \brief (AES) Interrupt Flag Status */ -#define REG_AES_DATABUFPTR (0x42004008) /**< \brief (AES) Data buffer pointer */ -#define REG_AES_DBGCTRL (0x42004009) /**< \brief (AES) Debug control */ -#define REG_AES_KEYWORD0 (0x4200400C) /**< \brief (AES) Keyword 0 */ -#define REG_AES_KEYWORD1 (0x42004010) /**< \brief (AES) Keyword 1 */ -#define REG_AES_KEYWORD2 (0x42004014) /**< \brief (AES) Keyword 2 */ -#define REG_AES_KEYWORD3 (0x42004018) /**< \brief (AES) Keyword 3 */ -#define REG_AES_KEYWORD4 (0x4200401C) /**< \brief (AES) Keyword 4 */ -#define REG_AES_KEYWORD5 (0x42004020) /**< \brief (AES) Keyword 5 */ -#define REG_AES_KEYWORD6 (0x42004024) /**< \brief (AES) Keyword 6 */ -#define REG_AES_KEYWORD7 (0x42004028) /**< \brief (AES) Keyword 7 */ -#define REG_AES_INDATA (0x42004038) /**< \brief (AES) Indata */ -#define REG_AES_INTVECTV0 (0x4200403C) /**< \brief (AES) Initialisation Vector 0 */ -#define REG_AES_INTVECTV1 (0x42004040) /**< \brief (AES) Initialisation Vector 1 */ -#define REG_AES_INTVECTV2 (0x42004044) /**< \brief (AES) Initialisation Vector 2 */ -#define REG_AES_INTVECTV3 (0x42004048) /**< \brief (AES) Initialisation Vector 3 */ -#define REG_AES_HASHKEY0 (0x4200405C) /**< \brief (AES) Hash key 0 */ -#define REG_AES_HASHKEY1 (0x42004060) /**< \brief (AES) Hash key 1 */ -#define REG_AES_HASHKEY2 (0x42004064) /**< \brief (AES) Hash key 2 */ -#define REG_AES_HASHKEY3 (0x42004068) /**< \brief (AES) Hash key 3 */ -#define REG_AES_GHASH0 (0x4200406C) /**< \brief (AES) Galois Hash 0 */ -#define REG_AES_GHASH1 (0x42004070) /**< \brief (AES) Galois Hash 1 */ -#define REG_AES_GHASH2 (0x42004074) /**< \brief (AES) Galois Hash 2 */ -#define REG_AES_GHASH3 (0x42004078) /**< \brief (AES) Galois Hash 3 */ -#define REG_AES_CIPLEN (0x42004080) /**< \brief (AES) Cipher Length */ -#define REG_AES_RANDSEED (0x42004084) /**< \brief (AES) Random Seed */ -#else -#define REG_AES_CTRLA (*(RwReg *)0x42004000UL) /**< \brief (AES) Control A */ -#define REG_AES_CTRLB (*(RwReg8 *)0x42004004UL) /**< \brief (AES) Control B */ -#define REG_AES_INTENCLR (*(RwReg8 *)0x42004005UL) /**< \brief (AES) Interrupt Enable Clear */ -#define REG_AES_INTENSET (*(RwReg8 *)0x42004006UL) /**< \brief (AES) Interrupt Enable Set */ -#define REG_AES_INTFLAG (*(RwReg8 *)0x42004007UL) /**< \brief (AES) Interrupt Flag Status */ -#define REG_AES_DATABUFPTR (*(RwReg8 *)0x42004008UL) /**< \brief (AES) Data buffer pointer */ -#define REG_AES_DBGCTRL (*(WoReg8 *)0x42004009UL) /**< \brief (AES) Debug control */ -#define REG_AES_KEYWORD0 (*(WoReg *)0x4200400CUL) /**< \brief (AES) Keyword 0 */ -#define REG_AES_KEYWORD1 (*(WoReg *)0x42004010UL) /**< \brief (AES) Keyword 1 */ -#define REG_AES_KEYWORD2 (*(WoReg *)0x42004014UL) /**< \brief (AES) Keyword 2 */ -#define REG_AES_KEYWORD3 (*(WoReg *)0x42004018UL) /**< \brief (AES) Keyword 3 */ -#define REG_AES_KEYWORD4 (*(WoReg *)0x4200401CUL) /**< \brief (AES) Keyword 4 */ -#define REG_AES_KEYWORD5 (*(WoReg *)0x42004020UL) /**< \brief (AES) Keyword 5 */ -#define REG_AES_KEYWORD6 (*(WoReg *)0x42004024UL) /**< \brief (AES) Keyword 6 */ -#define REG_AES_KEYWORD7 (*(WoReg *)0x42004028UL) /**< \brief (AES) Keyword 7 */ -#define REG_AES_INDATA (*(RwReg *)0x42004038UL) /**< \brief (AES) Indata */ -#define REG_AES_INTVECTV0 (*(WoReg *)0x4200403CUL) /**< \brief (AES) Initialisation Vector 0 */ -#define REG_AES_INTVECTV1 (*(WoReg *)0x42004040UL) /**< \brief (AES) Initialisation Vector 1 */ -#define REG_AES_INTVECTV2 (*(WoReg *)0x42004044UL) /**< \brief (AES) Initialisation Vector 2 */ -#define REG_AES_INTVECTV3 (*(WoReg *)0x42004048UL) /**< \brief (AES) Initialisation Vector 3 */ -#define REG_AES_HASHKEY0 (*(RwReg *)0x4200405CUL) /**< \brief (AES) Hash key 0 */ -#define REG_AES_HASHKEY1 (*(RwReg *)0x42004060UL) /**< \brief (AES) Hash key 1 */ -#define REG_AES_HASHKEY2 (*(RwReg *)0x42004064UL) /**< \brief (AES) Hash key 2 */ -#define REG_AES_HASHKEY3 (*(RwReg *)0x42004068UL) /**< \brief (AES) Hash key 3 */ -#define REG_AES_GHASH0 (*(RwReg *)0x4200406CUL) /**< \brief (AES) Galois Hash 0 */ -#define REG_AES_GHASH1 (*(RwReg *)0x42004070UL) /**< \brief (AES) Galois Hash 1 */ -#define REG_AES_GHASH2 (*(RwReg *)0x42004074UL) /**< \brief (AES) Galois Hash 2 */ -#define REG_AES_GHASH3 (*(RwReg *)0x42004078UL) /**< \brief (AES) Galois Hash 3 */ -#define REG_AES_CIPLEN (*(RwReg *)0x42004080UL) /**< \brief (AES) Cipher Length */ -#define REG_AES_RANDSEED (*(RwReg *)0x42004084UL) /**< \brief (AES) Random Seed */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for AES peripheral ========== */ -#define AES_DMAC_ID_RD 36 // DMA DATA Read trigger -#define AES_DMAC_ID_WR 35 // DMA DATA Write trigger - -#endif /* _SAML22_AES_INSTANCE_ */ diff --git a/watch-library/include/instance/ccl.h b/watch-library/include/instance/ccl.h deleted file mode 100644 index b1e6e8e5..00000000 --- a/watch-library/include/instance/ccl.h +++ /dev/null @@ -1,58 +0,0 @@ -/** - * \file - * - * \brief Instance description for CCL - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_CCL_INSTANCE_ -#define _SAML22_CCL_INSTANCE_ - -/* ========== Register definition for CCL peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_CCL_CTRL (0x42004800) /**< \brief (CCL) Control */ -#define REG_CCL_SEQCTRL0 (0x42004804) /**< \brief (CCL) SEQ Control x 0 */ -#define REG_CCL_SEQCTRL1 (0x42004805) /**< \brief (CCL) SEQ Control x 1 */ -#define REG_CCL_LUTCTRL0 (0x42004808) /**< \brief (CCL) LUT Control x 0 */ -#define REG_CCL_LUTCTRL1 (0x4200480C) /**< \brief (CCL) LUT Control x 1 */ -#define REG_CCL_LUTCTRL2 (0x42004810) /**< \brief (CCL) LUT Control x 2 */ -#define REG_CCL_LUTCTRL3 (0x42004814) /**< \brief (CCL) LUT Control x 3 */ -#else -#define REG_CCL_CTRL (*(RwReg8 *)0x42004800UL) /**< \brief (CCL) Control */ -#define REG_CCL_SEQCTRL0 (*(RwReg8 *)0x42004804UL) /**< \brief (CCL) SEQ Control x 0 */ -#define REG_CCL_SEQCTRL1 (*(RwReg8 *)0x42004805UL) /**< \brief (CCL) SEQ Control x 1 */ -#define REG_CCL_LUTCTRL0 (*(RwReg *)0x42004808UL) /**< \brief (CCL) LUT Control x 0 */ -#define REG_CCL_LUTCTRL1 (*(RwReg *)0x4200480CUL) /**< \brief (CCL) LUT Control x 1 */ -#define REG_CCL_LUTCTRL2 (*(RwReg *)0x42004810UL) /**< \brief (CCL) LUT Control x 2 */ -#define REG_CCL_LUTCTRL3 (*(RwReg *)0x42004814UL) /**< \brief (CCL) LUT Control x 3 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for CCL peripheral ========== */ -#define CCL_GCLK_ID 28 // GCLK index for CCL -#define CCL_IO_NUM 12 // Numer of input pins -#define CCL_LUT_NUM 4 // Number of LUT in a CCL -#define CCL_SEQ_NUM 2 // Number of SEQ in a CCL - -#endif /* _SAML22_CCL_INSTANCE_ */ diff --git a/watch-library/include/instance/dmac.h b/watch-library/include/instance/dmac.h deleted file mode 100644 index 2b7580d2..00000000 --- a/watch-library/include/instance/dmac.h +++ /dev/null @@ -1,98 +0,0 @@ -/** - * \file - * - * \brief Instance description for DMAC - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_DMAC_INSTANCE_ -#define _SAML22_DMAC_INSTANCE_ - -/* ========== Register definition for DMAC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_DMAC_CTRL (0x41008000) /**< \brief (DMAC) Control */ -#define REG_DMAC_CRCCTRL (0x41008002) /**< \brief (DMAC) CRC Control */ -#define REG_DMAC_CRCDATAIN (0x41008004) /**< \brief (DMAC) CRC Data Input */ -#define REG_DMAC_CRCCHKSUM (0x41008008) /**< \brief (DMAC) CRC Checksum */ -#define REG_DMAC_CRCSTATUS (0x4100800C) /**< \brief (DMAC) CRC Status */ -#define REG_DMAC_DBGCTRL (0x4100800D) /**< \brief (DMAC) Debug Control */ -#define REG_DMAC_QOSCTRL (0x4100800E) /**< \brief (DMAC) QOS Control */ -#define REG_DMAC_SWTRIGCTRL (0x41008010) /**< \brief (DMAC) Software Trigger Control */ -#define REG_DMAC_PRICTRL0 (0x41008014) /**< \brief (DMAC) Priority Control 0 */ -#define REG_DMAC_INTPEND (0x41008020) /**< \brief (DMAC) Interrupt Pending */ -#define REG_DMAC_INTSTATUS (0x41008024) /**< \brief (DMAC) Interrupt Status */ -#define REG_DMAC_BUSYCH (0x41008028) /**< \brief (DMAC) Busy Channels */ -#define REG_DMAC_PENDCH (0x4100802C) /**< \brief (DMAC) Pending Channels */ -#define REG_DMAC_ACTIVE (0x41008030) /**< \brief (DMAC) Active Channel and Levels */ -#define REG_DMAC_BASEADDR (0x41008034) /**< \brief (DMAC) Descriptor Memory Section Base Address */ -#define REG_DMAC_WRBADDR (0x41008038) /**< \brief (DMAC) Write-Back Memory Section Base Address */ -#define REG_DMAC_CHID (0x4100803F) /**< \brief (DMAC) Channel ID */ -#define REG_DMAC_CHCTRLA (0x41008040) /**< \brief (DMAC) Channel Control A */ -#define REG_DMAC_CHCTRLB (0x41008044) /**< \brief (DMAC) Channel Control B */ -#define REG_DMAC_CHINTENCLR (0x4100804C) /**< \brief (DMAC) Channel Interrupt Enable Clear */ -#define REG_DMAC_CHINTENSET (0x4100804D) /**< \brief (DMAC) Channel Interrupt Enable Set */ -#define REG_DMAC_CHINTFLAG (0x4100804E) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */ -#define REG_DMAC_CHSTATUS (0x4100804F) /**< \brief (DMAC) Channel Status */ -#else -#define REG_DMAC_CTRL (*(RwReg16*)0x41008000UL) /**< \brief (DMAC) Control */ -#define REG_DMAC_CRCCTRL (*(RwReg16*)0x41008002UL) /**< \brief (DMAC) CRC Control */ -#define REG_DMAC_CRCDATAIN (*(RwReg *)0x41008004UL) /**< \brief (DMAC) CRC Data Input */ -#define REG_DMAC_CRCCHKSUM (*(RwReg *)0x41008008UL) /**< \brief (DMAC) CRC Checksum */ -#define REG_DMAC_CRCSTATUS (*(RwReg8 *)0x4100800CUL) /**< \brief (DMAC) CRC Status */ -#define REG_DMAC_DBGCTRL (*(RwReg8 *)0x4100800DUL) /**< \brief (DMAC) Debug Control */ -#define REG_DMAC_QOSCTRL (*(RwReg8 *)0x4100800EUL) /**< \brief (DMAC) QOS Control */ -#define REG_DMAC_SWTRIGCTRL (*(RwReg *)0x41008010UL) /**< \brief (DMAC) Software Trigger Control */ -#define REG_DMAC_PRICTRL0 (*(RwReg *)0x41008014UL) /**< \brief (DMAC) Priority Control 0 */ -#define REG_DMAC_INTPEND (*(RwReg16*)0x41008020UL) /**< \brief (DMAC) Interrupt Pending */ -#define REG_DMAC_INTSTATUS (*(RoReg *)0x41008024UL) /**< \brief (DMAC) Interrupt Status */ -#define REG_DMAC_BUSYCH (*(RoReg *)0x41008028UL) /**< \brief (DMAC) Busy Channels */ -#define REG_DMAC_PENDCH (*(RoReg *)0x4100802CUL) /**< \brief (DMAC) Pending Channels */ -#define REG_DMAC_ACTIVE (*(RoReg *)0x41008030UL) /**< \brief (DMAC) Active Channel and Levels */ -#define REG_DMAC_BASEADDR (*(RwReg *)0x41008034UL) /**< \brief (DMAC) Descriptor Memory Section Base Address */ -#define REG_DMAC_WRBADDR (*(RwReg *)0x41008038UL) /**< \brief (DMAC) Write-Back Memory Section Base Address */ -#define REG_DMAC_CHID (*(RwReg8 *)0x4100803FUL) /**< \brief (DMAC) Channel ID */ -#define REG_DMAC_CHCTRLA (*(RwReg8 *)0x41008040UL) /**< \brief (DMAC) Channel Control A */ -#define REG_DMAC_CHCTRLB (*(RwReg *)0x41008044UL) /**< \brief (DMAC) Channel Control B */ -#define REG_DMAC_CHINTENCLR (*(RwReg8 *)0x4100804CUL) /**< \brief (DMAC) Channel Interrupt Enable Clear */ -#define REG_DMAC_CHINTENSET (*(RwReg8 *)0x4100804DUL) /**< \brief (DMAC) Channel Interrupt Enable Set */ -#define REG_DMAC_CHINTFLAG (*(RwReg8 *)0x4100804EUL) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */ -#define REG_DMAC_CHSTATUS (*(RoReg8 *)0x4100804FUL) /**< \brief (DMAC) Channel Status */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for DMAC peripheral ========== */ -#define DMAC_CH_BITS 4 // Number of bits to select channel -#define DMAC_CH_NUM 16 // Number of channels -#define DMAC_CLK_AHB_ID 3 // AHB clock index -#define DMAC_EVIN_NUM 4 // Number of input events -#define DMAC_EVOUT_NUM 4 // Number of output events -#define DMAC_LVL_BITS 2 // Number of bit to select level priority -#define DMAC_LVL_NUM 4 // Enable priority level number -#define DMAC_QOSCTRL_D_RESETVALUE 2 // QOS dmac ahb interface reset value -#define DMAC_QOSCTRL_F_RESETVALUE 2 // QOS dmac fetch interface reset value -#define DMAC_QOSCTRL_WRB_RESETVALUE 2 // QOS dmac write back interface reset value -#define DMAC_TRIG_BITS 6 // Number of bits to select trigger source -#define DMAC_TRIG_NUM 40 // Number of peripheral triggers - -#endif /* _SAML22_DMAC_INSTANCE_ */ diff --git a/watch-library/include/instance/dsu.h b/watch-library/include/instance/dsu.h deleted file mode 100644 index 8c13d4f1..00000000 --- a/watch-library/include/instance/dsu.h +++ /dev/null @@ -1,95 +0,0 @@ -/** - * \file - * - * \brief Instance description for DSU - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_DSU_INSTANCE_ -#define _SAML22_DSU_INSTANCE_ - -/* ========== Register definition for DSU peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_DSU_CTRL (0x41002000) /**< \brief (DSU) Control */ -#define REG_DSU_STATUSA (0x41002001) /**< \brief (DSU) Status A */ -#define REG_DSU_STATUSB (0x41002002) /**< \brief (DSU) Status B */ -#define REG_DSU_ADDR (0x41002004) /**< \brief (DSU) Address */ -#define REG_DSU_LENGTH (0x41002008) /**< \brief (DSU) Length */ -#define REG_DSU_DATA (0x4100200C) /**< \brief (DSU) Data */ -#define REG_DSU_DCC0 (0x41002010) /**< \brief (DSU) Debug Communication Channel 0 */ -#define REG_DSU_DCC1 (0x41002014) /**< \brief (DSU) Debug Communication Channel 1 */ -#define REG_DSU_DID (0x41002018) /**< \brief (DSU) Device Identification */ -#define REG_DSU_DCFG0 (0x410020F0) /**< \brief (DSU) Device Configuration 0 */ -#define REG_DSU_DCFG1 (0x410020F4) /**< \brief (DSU) Device Configuration 1 */ -#define REG_DSU_ENTRY0 (0x41003000) /**< \brief (DSU) CoreSight ROM Table Entry 0 */ -#define REG_DSU_ENTRY1 (0x41003004) /**< \brief (DSU) CoreSight ROM Table Entry 1 */ -#define REG_DSU_END (0x41003008) /**< \brief (DSU) CoreSight ROM Table End */ -#define REG_DSU_MEMTYPE (0x41003FCC) /**< \brief (DSU) CoreSight ROM Table Memory Type */ -#define REG_DSU_PID4 (0x41003FD0) /**< \brief (DSU) Peripheral Identification 4 */ -#define REG_DSU_PID5 (0x41003FD4) /**< \brief (DSU) Peripheral Identification 5 */ -#define REG_DSU_PID6 (0x41003FD8) /**< \brief (DSU) Peripheral Identification 6 */ -#define REG_DSU_PID7 (0x41003FDC) /**< \brief (DSU) Peripheral Identification 7 */ -#define REG_DSU_PID0 (0x41003FE0) /**< \brief (DSU) Peripheral Identification 0 */ -#define REG_DSU_PID1 (0x41003FE4) /**< \brief (DSU) Peripheral Identification 1 */ -#define REG_DSU_PID2 (0x41003FE8) /**< \brief (DSU) Peripheral Identification 2 */ -#define REG_DSU_PID3 (0x41003FEC) /**< \brief (DSU) Peripheral Identification 3 */ -#define REG_DSU_CID0 (0x41003FF0) /**< \brief (DSU) Component Identification 0 */ -#define REG_DSU_CID1 (0x41003FF4) /**< \brief (DSU) Component Identification 1 */ -#define REG_DSU_CID2 (0x41003FF8) /**< \brief (DSU) Component Identification 2 */ -#define REG_DSU_CID3 (0x41003FFC) /**< \brief (DSU) Component Identification 3 */ -#else -#define REG_DSU_CTRL (*(WoReg8 *)0x41002000UL) /**< \brief (DSU) Control */ -#define REG_DSU_STATUSA (*(RwReg8 *)0x41002001UL) /**< \brief (DSU) Status A */ -#define REG_DSU_STATUSB (*(RoReg8 *)0x41002002UL) /**< \brief (DSU) Status B */ -#define REG_DSU_ADDR (*(RwReg *)0x41002004UL) /**< \brief (DSU) Address */ -#define REG_DSU_LENGTH (*(RwReg *)0x41002008UL) /**< \brief (DSU) Length */ -#define REG_DSU_DATA (*(RwReg *)0x4100200CUL) /**< \brief (DSU) Data */ -#define REG_DSU_DCC0 (*(RwReg *)0x41002010UL) /**< \brief (DSU) Debug Communication Channel 0 */ -#define REG_DSU_DCC1 (*(RwReg *)0x41002014UL) /**< \brief (DSU) Debug Communication Channel 1 */ -#define REG_DSU_DID (*(RoReg *)0x41002018UL) /**< \brief (DSU) Device Identification */ -#define REG_DSU_DCFG0 (*(RwReg *)0x410020F0UL) /**< \brief (DSU) Device Configuration 0 */ -#define REG_DSU_DCFG1 (*(RwReg *)0x410020F4UL) /**< \brief (DSU) Device Configuration 1 */ -#define REG_DSU_ENTRY0 (*(RoReg *)0x41003000UL) /**< \brief (DSU) CoreSight ROM Table Entry 0 */ -#define REG_DSU_ENTRY1 (*(RoReg *)0x41003004UL) /**< \brief (DSU) CoreSight ROM Table Entry 1 */ -#define REG_DSU_END (*(RoReg *)0x41003008UL) /**< \brief (DSU) CoreSight ROM Table End */ -#define REG_DSU_MEMTYPE (*(RoReg *)0x41003FCCUL) /**< \brief (DSU) CoreSight ROM Table Memory Type */ -#define REG_DSU_PID4 (*(RoReg *)0x41003FD0UL) /**< \brief (DSU) Peripheral Identification 4 */ -#define REG_DSU_PID5 (*(RoReg *)0x41003FD4UL) /**< \brief (DSU) Peripheral Identification 5 */ -#define REG_DSU_PID6 (*(RoReg *)0x41003FD8UL) /**< \brief (DSU) Peripheral Identification 6 */ -#define REG_DSU_PID7 (*(RoReg *)0x41003FDCUL) /**< \brief (DSU) Peripheral Identification 7 */ -#define REG_DSU_PID0 (*(RoReg *)0x41003FE0UL) /**< \brief (DSU) Peripheral Identification 0 */ -#define REG_DSU_PID1 (*(RoReg *)0x41003FE4UL) /**< \brief (DSU) Peripheral Identification 1 */ -#define REG_DSU_PID2 (*(RoReg *)0x41003FE8UL) /**< \brief (DSU) Peripheral Identification 2 */ -#define REG_DSU_PID3 (*(RoReg *)0x41003FECUL) /**< \brief (DSU) Peripheral Identification 3 */ -#define REG_DSU_CID0 (*(RoReg *)0x41003FF0UL) /**< \brief (DSU) Component Identification 0 */ -#define REG_DSU_CID1 (*(RoReg *)0x41003FF4UL) /**< \brief (DSU) Component Identification 1 */ -#define REG_DSU_CID2 (*(RoReg *)0x41003FF8UL) /**< \brief (DSU) Component Identification 2 */ -#define REG_DSU_CID3 (*(RoReg *)0x41003FFCUL) /**< \brief (DSU) Component Identification 3 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for DSU peripheral ========== */ -#define DSU_CLK_AHB_ID 5 - -#endif /* _SAML22_DSU_INSTANCE_ */ diff --git a/watch-library/include/instance/eic.h b/watch-library/include/instance/eic.h deleted file mode 100644 index 31a5a31f..00000000 --- a/watch-library/include/instance/eic.h +++ /dev/null @@ -1,66 +0,0 @@ -/** - * \file - * - * \brief Instance description for EIC - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_EIC_INSTANCE_ -#define _SAML22_EIC_INSTANCE_ - -/* ========== Register definition for EIC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_EIC_CTRLA (0x40002800) /**< \brief (EIC) Control */ -#define REG_EIC_NMICTRL (0x40002801) /**< \brief (EIC) NMI Control */ -#define REG_EIC_NMIFLAG (0x40002802) /**< \brief (EIC) NMI Interrupt Flag */ -#define REG_EIC_SYNCBUSY (0x40002804) /**< \brief (EIC) Syncbusy register */ -#define REG_EIC_EVCTRL (0x40002808) /**< \brief (EIC) Event Control */ -#define REG_EIC_INTENCLR (0x4000280C) /**< \brief (EIC) Interrupt Enable Clear */ -#define REG_EIC_INTENSET (0x40002810) /**< \brief (EIC) Interrupt Enable Set */ -#define REG_EIC_INTFLAG (0x40002814) /**< \brief (EIC) Interrupt Flag Status and Clear */ -#define REG_EIC_ASYNCH (0x40002818) /**< \brief (EIC) EIC Asynchronous edge Detection Enable */ -#define REG_EIC_CONFIG0 (0x4000281C) /**< \brief (EIC) Configuration 0 */ -#define REG_EIC_CONFIG1 (0x40002820) /**< \brief (EIC) Configuration 1 */ -#else -#define REG_EIC_CTRLA (*(RwReg8 *)0x40002800UL) /**< \brief (EIC) Control */ -#define REG_EIC_NMICTRL (*(RwReg8 *)0x40002801UL) /**< \brief (EIC) NMI Control */ -#define REG_EIC_NMIFLAG (*(RwReg16*)0x40002802UL) /**< \brief (EIC) NMI Interrupt Flag */ -#define REG_EIC_SYNCBUSY (*(RoReg *)0x40002804UL) /**< \brief (EIC) Syncbusy register */ -#define REG_EIC_EVCTRL (*(RwReg *)0x40002808UL) /**< \brief (EIC) Event Control */ -#define REG_EIC_INTENCLR (*(RwReg *)0x4000280CUL) /**< \brief (EIC) Interrupt Enable Clear */ -#define REG_EIC_INTENSET (*(RwReg *)0x40002810UL) /**< \brief (EIC) Interrupt Enable Set */ -#define REG_EIC_INTFLAG (*(RwReg *)0x40002814UL) /**< \brief (EIC) Interrupt Flag Status and Clear */ -#define REG_EIC_ASYNCH (*(RwReg *)0x40002818UL) /**< \brief (EIC) EIC Asynchronous edge Detection Enable */ -#define REG_EIC_CONFIG0 (*(RwReg *)0x4000281CUL) /**< \brief (EIC) Configuration 0 */ -#define REG_EIC_CONFIG1 (*(RwReg *)0x40002820UL) /**< \brief (EIC) Configuration 1 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for EIC peripheral ========== */ -#define EIC_EXTINT_NUM 16 -#define EIC_GCLK_ID 3 -#define EIC_NUMBER_OF_CONFIG_REGS 2 -#define EIC_NUMBER_OF_INTERRUPTS 16 - -#endif /* _SAML22_EIC_INSTANCE_ */ diff --git a/watch-library/include/instance/evsys.h b/watch-library/include/instance/evsys.h deleted file mode 100644 index a78277ac..00000000 --- a/watch-library/include/instance/evsys.h +++ /dev/null @@ -1,250 +0,0 @@ -/** - * \file - * - * \brief Instance description for EVSYS - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_EVSYS_INSTANCE_ -#define _SAML22_EVSYS_INSTANCE_ - -/* ========== Register definition for EVSYS peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_EVSYS_CTRLA (0x42000000) /**< \brief (EVSYS) Control */ -#define REG_EVSYS_CHSTATUS (0x4200000C) /**< \brief (EVSYS) Channel Status */ -#define REG_EVSYS_INTENCLR (0x42000010) /**< \brief (EVSYS) Interrupt Enable Clear */ -#define REG_EVSYS_INTENSET (0x42000014) /**< \brief (EVSYS) Interrupt Enable Set */ -#define REG_EVSYS_INTFLAG (0x42000018) /**< \brief (EVSYS) Interrupt Flag Status and Clear */ -#define REG_EVSYS_SWEVT (0x4200001C) /**< \brief (EVSYS) Software Event */ -#define REG_EVSYS_CHANNEL0 (0x42000020) /**< \brief (EVSYS) Channel 0 */ -#define REG_EVSYS_CHANNEL1 (0x42000024) /**< \brief (EVSYS) Channel 1 */ -#define REG_EVSYS_CHANNEL2 (0x42000028) /**< \brief (EVSYS) Channel 2 */ -#define REG_EVSYS_CHANNEL3 (0x4200002C) /**< \brief (EVSYS) Channel 3 */ -#define REG_EVSYS_CHANNEL4 (0x42000030) /**< \brief (EVSYS) Channel 4 */ -#define REG_EVSYS_CHANNEL5 (0x42000034) /**< \brief (EVSYS) Channel 5 */ -#define REG_EVSYS_CHANNEL6 (0x42000038) /**< \brief (EVSYS) Channel 6 */ -#define REG_EVSYS_CHANNEL7 (0x4200003C) /**< \brief (EVSYS) Channel 7 */ -#define REG_EVSYS_USER0 (0x42000080) /**< \brief (EVSYS) User Multiplexer 0 */ -#define REG_EVSYS_USER1 (0x42000084) /**< \brief (EVSYS) User Multiplexer 1 */ -#define REG_EVSYS_USER2 (0x42000088) /**< \brief (EVSYS) User Multiplexer 2 */ -#define REG_EVSYS_USER3 (0x4200008C) /**< \brief (EVSYS) User Multiplexer 3 */ -#define REG_EVSYS_USER4 (0x42000090) /**< \brief (EVSYS) User Multiplexer 4 */ -#define REG_EVSYS_USER5 (0x42000094) /**< \brief (EVSYS) User Multiplexer 5 */ -#define REG_EVSYS_USER6 (0x42000098) /**< \brief (EVSYS) User Multiplexer 6 */ -#define REG_EVSYS_USER7 (0x4200009C) /**< \brief (EVSYS) User Multiplexer 7 */ -#define REG_EVSYS_USER8 (0x420000A0) /**< \brief (EVSYS) User Multiplexer 8 */ -#define REG_EVSYS_USER9 (0x420000A4) /**< \brief (EVSYS) User Multiplexer 9 */ -#define REG_EVSYS_USER10 (0x420000A8) /**< \brief (EVSYS) User Multiplexer 10 */ -#define REG_EVSYS_USER11 (0x420000AC) /**< \brief (EVSYS) User Multiplexer 11 */ -#define REG_EVSYS_USER12 (0x420000B0) /**< \brief (EVSYS) User Multiplexer 12 */ -#define REG_EVSYS_USER13 (0x420000B4) /**< \brief (EVSYS) User Multiplexer 13 */ -#define REG_EVSYS_USER14 (0x420000B8) /**< \brief (EVSYS) User Multiplexer 14 */ -#define REG_EVSYS_USER15 (0x420000BC) /**< \brief (EVSYS) User Multiplexer 15 */ -#define REG_EVSYS_USER16 (0x420000C0) /**< \brief (EVSYS) User Multiplexer 16 */ -#define REG_EVSYS_USER17 (0x420000C4) /**< \brief (EVSYS) User Multiplexer 17 */ -#define REG_EVSYS_USER18 (0x420000C8) /**< \brief (EVSYS) User Multiplexer 18 */ -#define REG_EVSYS_USER19 (0x420000CC) /**< \brief (EVSYS) User Multiplexer 19 */ -#define REG_EVSYS_USER20 (0x420000D0) /**< \brief (EVSYS) User Multiplexer 20 */ -#define REG_EVSYS_USER21 (0x420000D4) /**< \brief (EVSYS) User Multiplexer 21 */ -#define REG_EVSYS_USER22 (0x420000D8) /**< \brief (EVSYS) User Multiplexer 22 */ -#define REG_EVSYS_USER23 (0x420000DC) /**< \brief (EVSYS) User Multiplexer 23 */ -#define REG_EVSYS_USER24 (0x420000E0) /**< \brief (EVSYS) User Multiplexer 24 */ -#define REG_EVSYS_USER25 (0x420000E4) /**< \brief (EVSYS) User Multiplexer 25 */ -#define REG_EVSYS_USER26 (0x420000E8) /**< \brief (EVSYS) User Multiplexer 26 */ -#define REG_EVSYS_USER27 (0x420000EC) /**< \brief (EVSYS) User Multiplexer 27 */ -#define REG_EVSYS_USER28 (0x420000F0) /**< \brief (EVSYS) User Multiplexer 28 */ -#define REG_EVSYS_USER29 (0x420000F4) /**< \brief (EVSYS) User Multiplexer 29 */ -#define REG_EVSYS_USER30 (0x420000F8) /**< \brief (EVSYS) User Multiplexer 30 */ -#else -#define REG_EVSYS_CTRLA (*(RwReg8 *)0x42000000UL) /**< \brief (EVSYS) Control */ -#define REG_EVSYS_CHSTATUS (*(RoReg *)0x4200000CUL) /**< \brief (EVSYS) Channel Status */ -#define REG_EVSYS_INTENCLR (*(RwReg *)0x42000010UL) /**< \brief (EVSYS) Interrupt Enable Clear */ -#define REG_EVSYS_INTENSET (*(RwReg *)0x42000014UL) /**< \brief (EVSYS) Interrupt Enable Set */ -#define REG_EVSYS_INTFLAG (*(RwReg *)0x42000018UL) /**< \brief (EVSYS) Interrupt Flag Status and Clear */ -#define REG_EVSYS_SWEVT (*(WoReg *)0x4200001CUL) /**< \brief (EVSYS) Software Event */ -#define REG_EVSYS_CHANNEL0 (*(RwReg *)0x42000020UL) /**< \brief (EVSYS) Channel 0 */ -#define REG_EVSYS_CHANNEL1 (*(RwReg *)0x42000024UL) /**< \brief (EVSYS) Channel 1 */ -#define REG_EVSYS_CHANNEL2 (*(RwReg *)0x42000028UL) /**< \brief (EVSYS) Channel 2 */ -#define REG_EVSYS_CHANNEL3 (*(RwReg *)0x4200002CUL) /**< \brief (EVSYS) Channel 3 */ -#define REG_EVSYS_CHANNEL4 (*(RwReg *)0x42000030UL) /**< \brief (EVSYS) Channel 4 */ -#define REG_EVSYS_CHANNEL5 (*(RwReg *)0x42000034UL) /**< \brief (EVSYS) Channel 5 */ -#define REG_EVSYS_CHANNEL6 (*(RwReg *)0x42000038UL) /**< \brief (EVSYS) Channel 6 */ -#define REG_EVSYS_CHANNEL7 (*(RwReg *)0x4200003CUL) /**< \brief (EVSYS) Channel 7 */ -#define REG_EVSYS_USER0 (*(RwReg *)0x42000080UL) /**< \brief (EVSYS) User Multiplexer 0 */ -#define REG_EVSYS_USER1 (*(RwReg *)0x42000084UL) /**< \brief (EVSYS) User Multiplexer 1 */ -#define REG_EVSYS_USER2 (*(RwReg *)0x42000088UL) /**< \brief (EVSYS) User Multiplexer 2 */ -#define REG_EVSYS_USER3 (*(RwReg *)0x4200008CUL) /**< \brief (EVSYS) User Multiplexer 3 */ -#define REG_EVSYS_USER4 (*(RwReg *)0x42000090UL) /**< \brief (EVSYS) User Multiplexer 4 */ -#define REG_EVSYS_USER5 (*(RwReg *)0x42000094UL) /**< \brief (EVSYS) User Multiplexer 5 */ -#define REG_EVSYS_USER6 (*(RwReg *)0x42000098UL) /**< \brief (EVSYS) User Multiplexer 6 */ -#define REG_EVSYS_USER7 (*(RwReg *)0x4200009CUL) /**< \brief (EVSYS) User Multiplexer 7 */ -#define REG_EVSYS_USER8 (*(RwReg *)0x420000A0UL) /**< \brief (EVSYS) User Multiplexer 8 */ -#define REG_EVSYS_USER9 (*(RwReg *)0x420000A4UL) /**< \brief (EVSYS) User Multiplexer 9 */ -#define REG_EVSYS_USER10 (*(RwReg *)0x420000A8UL) /**< \brief (EVSYS) User Multiplexer 10 */ -#define REG_EVSYS_USER11 (*(RwReg *)0x420000ACUL) /**< \brief (EVSYS) User Multiplexer 11 */ -#define REG_EVSYS_USER12 (*(RwReg *)0x420000B0UL) /**< \brief (EVSYS) User Multiplexer 12 */ -#define REG_EVSYS_USER13 (*(RwReg *)0x420000B4UL) /**< \brief (EVSYS) User Multiplexer 13 */ -#define REG_EVSYS_USER14 (*(RwReg *)0x420000B8UL) /**< \brief (EVSYS) User Multiplexer 14 */ -#define REG_EVSYS_USER15 (*(RwReg *)0x420000BCUL) /**< \brief (EVSYS) User Multiplexer 15 */ -#define REG_EVSYS_USER16 (*(RwReg *)0x420000C0UL) /**< \brief (EVSYS) User Multiplexer 16 */ -#define REG_EVSYS_USER17 (*(RwReg *)0x420000C4UL) /**< \brief (EVSYS) User Multiplexer 17 */ -#define REG_EVSYS_USER18 (*(RwReg *)0x420000C8UL) /**< \brief (EVSYS) User Multiplexer 18 */ -#define REG_EVSYS_USER19 (*(RwReg *)0x420000CCUL) /**< \brief (EVSYS) User Multiplexer 19 */ -#define REG_EVSYS_USER20 (*(RwReg *)0x420000D0UL) /**< \brief (EVSYS) User Multiplexer 20 */ -#define REG_EVSYS_USER21 (*(RwReg *)0x420000D4UL) /**< \brief (EVSYS) User Multiplexer 21 */ -#define REG_EVSYS_USER22 (*(RwReg *)0x420000D8UL) /**< \brief (EVSYS) User Multiplexer 22 */ -#define REG_EVSYS_USER23 (*(RwReg *)0x420000DCUL) /**< \brief (EVSYS) User Multiplexer 23 */ -#define REG_EVSYS_USER24 (*(RwReg *)0x420000E0UL) /**< \brief (EVSYS) User Multiplexer 24 */ -#define REG_EVSYS_USER25 (*(RwReg *)0x420000E4UL) /**< \brief (EVSYS) User Multiplexer 25 */ -#define REG_EVSYS_USER26 (*(RwReg *)0x420000E8UL) /**< \brief (EVSYS) User Multiplexer 26 */ -#define REG_EVSYS_USER27 (*(RwReg *)0x420000ECUL) /**< \brief (EVSYS) User Multiplexer 27 */ -#define REG_EVSYS_USER28 (*(RwReg *)0x420000F0UL) /**< \brief (EVSYS) User Multiplexer 28 */ -#define REG_EVSYS_USER29 (*(RwReg *)0x420000F4UL) /**< \brief (EVSYS) User Multiplexer 29 */ -#define REG_EVSYS_USER30 (*(RwReg *)0x420000F8UL) /**< \brief (EVSYS) User Multiplexer 30 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for EVSYS peripheral ========== */ -#define EVSYS_CHANNELS 8 // Number of Channels -#define EVSYS_CHANNELS_BITS 3 // Number of bits to select Channel -#define EVSYS_CHANNELS_MSB 7 // Number of Channels - 1 -#define EVSYS_EXTEVT_NUM 0 // Number of External Event Generators -#define EVSYS_GCLK_ID_0 7 -#define EVSYS_GCLK_ID_1 8 -#define EVSYS_GCLK_ID_2 9 -#define EVSYS_GCLK_ID_3 10 -#define EVSYS_GCLK_ID_4 11 -#define EVSYS_GCLK_ID_5 12 -#define EVSYS_GCLK_ID_6 13 -#define EVSYS_GCLK_ID_7 14 -#define EVSYS_GCLK_ID_LSB 7 -#define EVSYS_GCLK_ID_MSB 14 -#define EVSYS_GCLK_ID_SIZE 8 -#define EVSYS_GENERATORS 71 // Total Number of Event Generators -#define EVSYS_GENERATORS_BITS 7 // Number of bits to select Event Generator -#define EVSYS_USERS 31 // Total Number of Event Users -#define EVSYS_USERS_BITS 5 // Number of bits to select Event User - -// GENERATORS -#define EVSYS_ID_GEN_OSCCTRL_XOSC_FAIL 1 -#define EVSYS_ID_GEN_OSC32KCTRL_XOSC32K_FAIL 2 -#define EVSYS_ID_GEN_RTC_CMP_0 3 -#define EVSYS_ID_GEN_RTC_CMP_1 4 -#define EVSYS_ID_GEN_RTC_TAMPER 5 -#define EVSYS_ID_GEN_RTC_OVF 6 -#define EVSYS_ID_GEN_RTC_PER_0 7 -#define EVSYS_ID_GEN_RTC_PER_1 8 -#define EVSYS_ID_GEN_RTC_PER_2 9 -#define EVSYS_ID_GEN_RTC_PER_3 10 -#define EVSYS_ID_GEN_RTC_PER_4 11 -#define EVSYS_ID_GEN_RTC_PER_5 12 -#define EVSYS_ID_GEN_RTC_PER_6 13 -#define EVSYS_ID_GEN_RTC_PER_7 14 -#define EVSYS_ID_GEN_EIC_EXTINT_0 15 -#define EVSYS_ID_GEN_EIC_EXTINT_1 16 -#define EVSYS_ID_GEN_EIC_EXTINT_2 17 -#define EVSYS_ID_GEN_EIC_EXTINT_3 18 -#define EVSYS_ID_GEN_EIC_EXTINT_4 19 -#define EVSYS_ID_GEN_EIC_EXTINT_5 20 -#define EVSYS_ID_GEN_EIC_EXTINT_6 21 -#define EVSYS_ID_GEN_EIC_EXTINT_7 22 -#define EVSYS_ID_GEN_EIC_EXTINT_8 23 -#define EVSYS_ID_GEN_EIC_EXTINT_9 24 -#define EVSYS_ID_GEN_EIC_EXTINT_10 25 -#define EVSYS_ID_GEN_EIC_EXTINT_11 26 -#define EVSYS_ID_GEN_EIC_EXTINT_12 27 -#define EVSYS_ID_GEN_EIC_EXTINT_13 28 -#define EVSYS_ID_GEN_EIC_EXTINT_14 29 -#define EVSYS_ID_GEN_EIC_EXTINT_15 30 -#define EVSYS_ID_GEN_DMAC_CH_0 31 -#define EVSYS_ID_GEN_DMAC_CH_1 32 -#define EVSYS_ID_GEN_DMAC_CH_2 33 -#define EVSYS_ID_GEN_DMAC_CH_3 34 -#define EVSYS_ID_GEN_TCC0_OVF 35 -#define EVSYS_ID_GEN_TCC0_TRG 36 -#define EVSYS_ID_GEN_TCC0_CNT 37 -#define EVSYS_ID_GEN_TCC0_MCX_0 38 -#define EVSYS_ID_GEN_TCC0_MCX_1 39 -#define EVSYS_ID_GEN_TCC0_MCX_2 40 -#define EVSYS_ID_GEN_TCC0_MCX_3 41 -#define EVSYS_ID_GEN_TC0_OVF 42 -#define EVSYS_ID_GEN_TC0_MCX_0 43 -#define EVSYS_ID_GEN_TC0_MCX_1 44 -#define EVSYS_ID_GEN_TC1_OVF 45 -#define EVSYS_ID_GEN_TC1_MCX_0 46 -#define EVSYS_ID_GEN_TC1_MCX_1 47 -#define EVSYS_ID_GEN_TC2_OVF 48 -#define EVSYS_ID_GEN_TC2_MCX_0 49 -#define EVSYS_ID_GEN_TC2_MCX_1 50 -#define EVSYS_ID_GEN_TC3_OVF 51 -#define EVSYS_ID_GEN_TC3_MCX_0 52 -#define EVSYS_ID_GEN_TC3_MCX_1 53 -#define EVSYS_ID_GEN_ADC_RESRDY 54 -#define EVSYS_ID_GEN_ADC_WINMON 55 -#define EVSYS_ID_GEN_AC_COMP_0 56 -#define EVSYS_ID_GEN_AC_COMP_1 57 -#define EVSYS_ID_GEN_AC_WIN_0 58 -#define EVSYS_ID_GEN_SLCD_FC0OVERFLOW 61 -#define EVSYS_ID_GEN_SLCD_FC1OVERFLOW 62 -#define EVSYS_ID_GEN_SLCD_FC2OVERFLOW 63 -#define EVSYS_ID_GEN_SLCD_DT 64 -#define EVSYS_ID_GEN_TRNG_READY 65 -#define EVSYS_ID_GEN_CCL_LUTOUT_0 66 -#define EVSYS_ID_GEN_CCL_LUTOUT_1 67 -#define EVSYS_ID_GEN_CCL_LUTOUT_2 68 -#define EVSYS_ID_GEN_CCL_LUTOUT_3 69 -#define EVSYS_ID_GEN_PAC_ACCERR 70 - -// USERS -#define EVSYS_ID_USER_RTC_TAMPER 0 -#define EVSYS_ID_USER_PORT_EV_0 1 -#define EVSYS_ID_USER_PORT_EV_1 2 -#define EVSYS_ID_USER_PORT_EV_2 3 -#define EVSYS_ID_USER_PORT_EV_3 4 -#define EVSYS_ID_USER_DMAC_CH_0 5 -#define EVSYS_ID_USER_DMAC_CH_1 6 -#define EVSYS_ID_USER_DMAC_CH_2 7 -#define EVSYS_ID_USER_DMAC_CH_3 8 -#define EVSYS_ID_USER_TCC0_EV_0 9 -#define EVSYS_ID_USER_TCC0_EV_1 10 -#define EVSYS_ID_USER_TCC0_MC_0 11 -#define EVSYS_ID_USER_TCC0_MC_1 12 -#define EVSYS_ID_USER_TCC0_MC_2 13 -#define EVSYS_ID_USER_TCC0_MC_3 14 -#define EVSYS_ID_USER_TC0_EVU 15 -#define EVSYS_ID_USER_TC1_EVU 16 -#define EVSYS_ID_USER_TC2_EVU 17 -#define EVSYS_ID_USER_TC3_EVU 18 -#define EVSYS_ID_USER_ADC_START 19 -#define EVSYS_ID_USER_ADC_SYNC 20 -#define EVSYS_ID_USER_AC_SOC_0 21 -#define EVSYS_ID_USER_AC_SOC_1 22 -#define EVSYS_ID_USER_CCL_LUTIN_0 24 -#define EVSYS_ID_USER_CCL_LUTIN_1 25 -#define EVSYS_ID_USER_CCL_LUTIN_2 26 -#define EVSYS_ID_USER_CCL_LUTIN_3 27 -#define EVSYS_ID_USER_MTB_START 29 -#define EVSYS_ID_USER_MTB_STOP 30 - -#endif /* _SAML22_EVSYS_INSTANCE_ */ diff --git a/watch-library/include/instance/freqm.h b/watch-library/include/instance/freqm.h deleted file mode 100644 index 4c2e2102..00000000 --- a/watch-library/include/instance/freqm.h +++ /dev/null @@ -1,60 +0,0 @@ -/** - * \file - * - * \brief Instance description for FREQM - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_FREQM_INSTANCE_ -#define _SAML22_FREQM_INSTANCE_ - -/* ========== Register definition for FREQM peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_FREQM_CTRLA (0x40002C00) /**< \brief (FREQM) Control A Register */ -#define REG_FREQM_CTRLB (0x40002C01) /**< \brief (FREQM) Control B Register */ -#define REG_FREQM_CFGA (0x40002C02) /**< \brief (FREQM) Config A register */ -#define REG_FREQM_INTENCLR (0x40002C08) /**< \brief (FREQM) Interrupt Enable Clear Register */ -#define REG_FREQM_INTENSET (0x40002C09) /**< \brief (FREQM) Interrupt Enable Set Register */ -#define REG_FREQM_INTFLAG (0x40002C0A) /**< \brief (FREQM) Interrupt Flag Register */ -#define REG_FREQM_STATUS (0x40002C0B) /**< \brief (FREQM) Status Register */ -#define REG_FREQM_SYNCBUSY (0x40002C0C) /**< \brief (FREQM) Synchronization Busy Register */ -#define REG_FREQM_VALUE (0x40002C10) /**< \brief (FREQM) Count Value Register */ -#else -#define REG_FREQM_CTRLA (*(RwReg8 *)0x40002C00UL) /**< \brief (FREQM) Control A Register */ -#define REG_FREQM_CTRLB (*(WoReg8 *)0x40002C01UL) /**< \brief (FREQM) Control B Register */ -#define REG_FREQM_CFGA (*(RwReg16*)0x40002C02UL) /**< \brief (FREQM) Config A register */ -#define REG_FREQM_INTENCLR (*(RwReg8 *)0x40002C08UL) /**< \brief (FREQM) Interrupt Enable Clear Register */ -#define REG_FREQM_INTENSET (*(RwReg8 *)0x40002C09UL) /**< \brief (FREQM) Interrupt Enable Set Register */ -#define REG_FREQM_INTFLAG (*(RwReg8 *)0x40002C0AUL) /**< \brief (FREQM) Interrupt Flag Register */ -#define REG_FREQM_STATUS (*(RwReg8 *)0x40002C0BUL) /**< \brief (FREQM) Status Register */ -#define REG_FREQM_SYNCBUSY (*(RoReg *)0x40002C0CUL) /**< \brief (FREQM) Synchronization Busy Register */ -#define REG_FREQM_VALUE (*(RoReg *)0x40002C10UL) /**< \brief (FREQM) Count Value Register */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for FREQM peripheral ========== */ -#define FREQM_GCLK_ID_MSR 4 // Index of measure generic clock -#define FREQM_GCLK_ID_REF 5 // Index of reference generic clock - -#endif /* _SAML22_FREQM_INSTANCE_ */ diff --git a/watch-library/include/instance/gclk.h b/watch-library/include/instance/gclk.h deleted file mode 100644 index 869d77c6..00000000 --- a/watch-library/include/instance/gclk.h +++ /dev/null @@ -1,130 +0,0 @@ -/** - * \file - * - * \brief Instance description for GCLK - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_GCLK_INSTANCE_ -#define _SAML22_GCLK_INSTANCE_ - -/* ========== Register definition for GCLK peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_GCLK_CTRLA (0x40001C00) /**< \brief (GCLK) Control */ -#define REG_GCLK_SYNCBUSY (0x40001C04) /**< \brief (GCLK) Synchronization Busy */ -#define REG_GCLK_GENCTRL0 (0x40001C20) /**< \brief (GCLK) Generic Clock Generator Control 0 */ -#define REG_GCLK_GENCTRL1 (0x40001C24) /**< \brief (GCLK) Generic Clock Generator Control 1 */ -#define REG_GCLK_GENCTRL2 (0x40001C28) /**< \brief (GCLK) Generic Clock Generator Control 2 */ -#define REG_GCLK_GENCTRL3 (0x40001C2C) /**< \brief (GCLK) Generic Clock Generator Control 3 */ -#define REG_GCLK_GENCTRL4 (0x40001C30) /**< \brief (GCLK) Generic Clock Generator Control 4 */ -#define REG_GCLK_PCHCTRL0 (0x40001C80) /**< \brief (GCLK) Peripheral Clock Control 0 */ -#define REG_GCLK_PCHCTRL1 (0x40001C84) /**< \brief (GCLK) Peripheral Clock Control 1 */ -#define REG_GCLK_PCHCTRL2 (0x40001C88) /**< \brief (GCLK) Peripheral Clock Control 2 */ -#define REG_GCLK_PCHCTRL3 (0x40001C8C) /**< \brief (GCLK) Peripheral Clock Control 3 */ -#define REG_GCLK_PCHCTRL4 (0x40001C90) /**< \brief (GCLK) Peripheral Clock Control 4 */ -#define REG_GCLK_PCHCTRL5 (0x40001C94) /**< \brief (GCLK) Peripheral Clock Control 5 */ -#define REG_GCLK_PCHCTRL6 (0x40001C98) /**< \brief (GCLK) Peripheral Clock Control 6 */ -#define REG_GCLK_PCHCTRL7 (0x40001C9C) /**< \brief (GCLK) Peripheral Clock Control 7 */ -#define REG_GCLK_PCHCTRL8 (0x40001CA0) /**< \brief (GCLK) Peripheral Clock Control 8 */ -#define REG_GCLK_PCHCTRL9 (0x40001CA4) /**< \brief (GCLK) Peripheral Clock Control 9 */ -#define REG_GCLK_PCHCTRL10 (0x40001CA8) /**< \brief (GCLK) Peripheral Clock Control 10 */ -#define REG_GCLK_PCHCTRL11 (0x40001CAC) /**< \brief (GCLK) Peripheral Clock Control 11 */ -#define REG_GCLK_PCHCTRL12 (0x40001CB0) /**< \brief (GCLK) Peripheral Clock Control 12 */ -#define REG_GCLK_PCHCTRL13 (0x40001CB4) /**< \brief (GCLK) Peripheral Clock Control 13 */ -#define REG_GCLK_PCHCTRL14 (0x40001CB8) /**< \brief (GCLK) Peripheral Clock Control 14 */ -#define REG_GCLK_PCHCTRL15 (0x40001CBC) /**< \brief (GCLK) Peripheral Clock Control 15 */ -#define REG_GCLK_PCHCTRL16 (0x40001CC0) /**< \brief (GCLK) Peripheral Clock Control 16 */ -#define REG_GCLK_PCHCTRL17 (0x40001CC4) /**< \brief (GCLK) Peripheral Clock Control 17 */ -#define REG_GCLK_PCHCTRL18 (0x40001CC8) /**< \brief (GCLK) Peripheral Clock Control 18 */ -#define REG_GCLK_PCHCTRL19 (0x40001CCC) /**< \brief (GCLK) Peripheral Clock Control 19 */ -#define REG_GCLK_PCHCTRL20 (0x40001CD0) /**< \brief (GCLK) Peripheral Clock Control 20 */ -#define REG_GCLK_PCHCTRL21 (0x40001CD4) /**< \brief (GCLK) Peripheral Clock Control 21 */ -#define REG_GCLK_PCHCTRL22 (0x40001CD8) /**< \brief (GCLK) Peripheral Clock Control 22 */ -#define REG_GCLK_PCHCTRL23 (0x40001CDC) /**< \brief (GCLK) Peripheral Clock Control 23 */ -#define REG_GCLK_PCHCTRL24 (0x40001CE0) /**< \brief (GCLK) Peripheral Clock Control 24 */ -#define REG_GCLK_PCHCTRL25 (0x40001CE4) /**< \brief (GCLK) Peripheral Clock Control 25 */ -#define REG_GCLK_PCHCTRL26 (0x40001CE8) /**< \brief (GCLK) Peripheral Clock Control 26 */ -#define REG_GCLK_PCHCTRL27 (0x40001CEC) /**< \brief (GCLK) Peripheral Clock Control 27 */ -#define REG_GCLK_PCHCTRL28 (0x40001CF0) /**< \brief (GCLK) Peripheral Clock Control 28 */ -#define REG_GCLK_PCHCTRL29 (0x40001CF4) /**< \brief (GCLK) Peripheral Clock Control 29 */ -#else -#define REG_GCLK_CTRLA (*(RwReg8 *)0x40001C00UL) /**< \brief (GCLK) Control */ -#define REG_GCLK_SYNCBUSY (*(RoReg *)0x40001C04UL) /**< \brief (GCLK) Synchronization Busy */ -#define REG_GCLK_GENCTRL0 (*(RwReg *)0x40001C20UL) /**< \brief (GCLK) Generic Clock Generator Control 0 */ -#define REG_GCLK_GENCTRL1 (*(RwReg *)0x40001C24UL) /**< \brief (GCLK) Generic Clock Generator Control 1 */ -#define REG_GCLK_GENCTRL2 (*(RwReg *)0x40001C28UL) /**< \brief (GCLK) Generic Clock Generator Control 2 */ -#define REG_GCLK_GENCTRL3 (*(RwReg *)0x40001C2CUL) /**< \brief (GCLK) Generic Clock Generator Control 3 */ -#define REG_GCLK_GENCTRL4 (*(RwReg *)0x40001C30UL) /**< \brief (GCLK) Generic Clock Generator Control 4 */ -#define REG_GCLK_PCHCTRL0 (*(RwReg *)0x40001C80UL) /**< \brief (GCLK) Peripheral Clock Control 0 */ -#define REG_GCLK_PCHCTRL1 (*(RwReg *)0x40001C84UL) /**< \brief (GCLK) Peripheral Clock Control 1 */ -#define REG_GCLK_PCHCTRL2 (*(RwReg *)0x40001C88UL) /**< \brief (GCLK) Peripheral Clock Control 2 */ -#define REG_GCLK_PCHCTRL3 (*(RwReg *)0x40001C8CUL) /**< \brief (GCLK) Peripheral Clock Control 3 */ -#define REG_GCLK_PCHCTRL4 (*(RwReg *)0x40001C90UL) /**< \brief (GCLK) Peripheral Clock Control 4 */ -#define REG_GCLK_PCHCTRL5 (*(RwReg *)0x40001C94UL) /**< \brief (GCLK) Peripheral Clock Control 5 */ -#define REG_GCLK_PCHCTRL6 (*(RwReg *)0x40001C98UL) /**< \brief (GCLK) Peripheral Clock Control 6 */ -#define REG_GCLK_PCHCTRL7 (*(RwReg *)0x40001C9CUL) /**< \brief (GCLK) Peripheral Clock Control 7 */ -#define REG_GCLK_PCHCTRL8 (*(RwReg *)0x40001CA0UL) /**< \brief (GCLK) Peripheral Clock Control 8 */ -#define REG_GCLK_PCHCTRL9 (*(RwReg *)0x40001CA4UL) /**< \brief (GCLK) Peripheral Clock Control 9 */ -#define REG_GCLK_PCHCTRL10 (*(RwReg *)0x40001CA8UL) /**< \brief (GCLK) Peripheral Clock Control 10 */ -#define REG_GCLK_PCHCTRL11 (*(RwReg *)0x40001CACUL) /**< \brief (GCLK) Peripheral Clock Control 11 */ -#define REG_GCLK_PCHCTRL12 (*(RwReg *)0x40001CB0UL) /**< \brief (GCLK) Peripheral Clock Control 12 */ -#define REG_GCLK_PCHCTRL13 (*(RwReg *)0x40001CB4UL) /**< \brief (GCLK) Peripheral Clock Control 13 */ -#define REG_GCLK_PCHCTRL14 (*(RwReg *)0x40001CB8UL) /**< \brief (GCLK) Peripheral Clock Control 14 */ -#define REG_GCLK_PCHCTRL15 (*(RwReg *)0x40001CBCUL) /**< \brief (GCLK) Peripheral Clock Control 15 */ -#define REG_GCLK_PCHCTRL16 (*(RwReg *)0x40001CC0UL) /**< \brief (GCLK) Peripheral Clock Control 16 */ -#define REG_GCLK_PCHCTRL17 (*(RwReg *)0x40001CC4UL) /**< \brief (GCLK) Peripheral Clock Control 17 */ -#define REG_GCLK_PCHCTRL18 (*(RwReg *)0x40001CC8UL) /**< \brief (GCLK) Peripheral Clock Control 18 */ -#define REG_GCLK_PCHCTRL19 (*(RwReg *)0x40001CCCUL) /**< \brief (GCLK) Peripheral Clock Control 19 */ -#define REG_GCLK_PCHCTRL20 (*(RwReg *)0x40001CD0UL) /**< \brief (GCLK) Peripheral Clock Control 20 */ -#define REG_GCLK_PCHCTRL21 (*(RwReg *)0x40001CD4UL) /**< \brief (GCLK) Peripheral Clock Control 21 */ -#define REG_GCLK_PCHCTRL22 (*(RwReg *)0x40001CD8UL) /**< \brief (GCLK) Peripheral Clock Control 22 */ -#define REG_GCLK_PCHCTRL23 (*(RwReg *)0x40001CDCUL) /**< \brief (GCLK) Peripheral Clock Control 23 */ -#define REG_GCLK_PCHCTRL24 (*(RwReg *)0x40001CE0UL) /**< \brief (GCLK) Peripheral Clock Control 24 */ -#define REG_GCLK_PCHCTRL25 (*(RwReg *)0x40001CE4UL) /**< \brief (GCLK) Peripheral Clock Control 25 */ -#define REG_GCLK_PCHCTRL26 (*(RwReg *)0x40001CE8UL) /**< \brief (GCLK) Peripheral Clock Control 26 */ -#define REG_GCLK_PCHCTRL27 (*(RwReg *)0x40001CECUL) /**< \brief (GCLK) Peripheral Clock Control 27 */ -#define REG_GCLK_PCHCTRL28 (*(RwReg *)0x40001CF0UL) /**< \brief (GCLK) Peripheral Clock Control 28 */ -#define REG_GCLK_PCHCTRL29 (*(RwReg *)0x40001CF4UL) /**< \brief (GCLK) Peripheral Clock Control 29 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for GCLK peripheral ========== */ -#define GCLK_GENDIV_BITS 16 -#define GCLK_GEN_BITS 3 -#define GCLK_GEN_NUM 5 // Number of Generic Clock Generators -#define GCLK_GEN_NUM_MSB 4 // Number of Generic Clock Generators - 1 -#define GCLK_GEN_SOURCE_NUM_MSB 7 // Number of Generic Clock Sources - 1 -#define GCLK_NUM 30 // Number of Generic Clock Users -#define GCLK_SOURCE_BITS 3 -#define GCLK_SOURCE_DFLL48M 6 -#define GCLK_SOURCE_DPLL96M 7 -#define GCLK_SOURCE_GCLKGEN1 2 -#define GCLK_SOURCE_GCLKIN 1 -#define GCLK_SOURCE_NUM 8 // Number of Generic Clock Sources -#define GCLK_SOURCE_OSCULP32K 3 -#define GCLK_SOURCE_OSC16M 5 -#define GCLK_SOURCE_XOSC 0 -#define GCLK_SOURCE_XOSC32K 4 - -#endif /* _SAML22_GCLK_INSTANCE_ */ diff --git a/watch-library/include/instance/mclk.h b/watch-library/include/instance/mclk.h deleted file mode 100644 index 32af4f13..00000000 --- a/watch-library/include/instance/mclk.h +++ /dev/null @@ -1,63 +0,0 @@ -/** - * \file - * - * \brief Instance description for MCLK - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_MCLK_INSTANCE_ -#define _SAML22_MCLK_INSTANCE_ - -/* ========== Register definition for MCLK peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_MCLK_INTENCLR (0x40000801) /**< \brief (MCLK) Interrupt Enable Clear */ -#define REG_MCLK_INTENSET (0x40000802) /**< \brief (MCLK) Interrupt Enable Set */ -#define REG_MCLK_INTFLAG (0x40000803) /**< \brief (MCLK) Interrupt Flag Status and Clear */ -#define REG_MCLK_CPUDIV (0x40000804) /**< \brief (MCLK) CPU Clock Division */ -#define REG_MCLK_BUPDIV (0x40000806) /**< \brief (MCLK) Backup Clock Division */ -#define REG_MCLK_AHBMASK (0x40000810) /**< \brief (MCLK) AHB Mask */ -#define REG_MCLK_APBAMASK (0x40000814) /**< \brief (MCLK) APBA Mask */ -#define REG_MCLK_APBBMASK (0x40000818) /**< \brief (MCLK) APBB Mask */ -#define REG_MCLK_APBCMASK (0x4000081C) /**< \brief (MCLK) APBC Mask */ -#else -#define REG_MCLK_INTENCLR (*(RwReg8 *)0x40000801UL) /**< \brief (MCLK) Interrupt Enable Clear */ -#define REG_MCLK_INTENSET (*(RwReg8 *)0x40000802UL) /**< \brief (MCLK) Interrupt Enable Set */ -#define REG_MCLK_INTFLAG (*(RwReg8 *)0x40000803UL) /**< \brief (MCLK) Interrupt Flag Status and Clear */ -#define REG_MCLK_CPUDIV (*(RwReg8 *)0x40000804UL) /**< \brief (MCLK) CPU Clock Division */ -#define REG_MCLK_BUPDIV (*(RwReg8 *)0x40000806UL) /**< \brief (MCLK) Backup Clock Division */ -#define REG_MCLK_AHBMASK (*(RwReg *)0x40000810UL) /**< \brief (MCLK) AHB Mask */ -#define REG_MCLK_APBAMASK (*(RwReg *)0x40000814UL) /**< \brief (MCLK) APBA Mask */ -#define REG_MCLK_APBBMASK (*(RwReg *)0x40000818UL) /**< \brief (MCLK) APBB Mask */ -#define REG_MCLK_APBCMASK (*(RwReg *)0x4000081CUL) /**< \brief (MCLK) APBC Mask */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for MCLK peripheral ========== */ -#define MCLK_BUPDIV_IMPLEMENTED 1 -#define MCLK_CTRLA_MCSEL_GCLK 1 -#define MCLK_CTRLA_MCSEL_OSC8M 0 -#define MCLK_MCLK_CLK_APB_NUM 3 -#define MCLK_SYSTEM_CLOCK 1000000 // System Clock Frequency at Reset - -#endif /* _SAML22_MCLK_INSTANCE_ */ diff --git a/watch-library/include/instance/mtb.h b/watch-library/include/instance/mtb.h deleted file mode 100644 index 02e67161..00000000 --- a/watch-library/include/instance/mtb.h +++ /dev/null @@ -1,89 +0,0 @@ -/** - * \file - * - * \brief Instance description for MTB - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_MTB_INSTANCE_ -#define _SAML22_MTB_INSTANCE_ - -/* ========== Register definition for MTB peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_MTB_POSITION (0x4100A000) /**< \brief (MTB) MTB Position */ -#define REG_MTB_MASTER (0x4100A004) /**< \brief (MTB) MTB Master */ -#define REG_MTB_FLOW (0x4100A008) /**< \brief (MTB) MTB Flow */ -#define REG_MTB_BASE (0x4100A00C) /**< \brief (MTB) MTB Base */ -#define REG_MTB_ITCTRL (0x4100AF00) /**< \brief (MTB) MTB Integration Mode Control */ -#define REG_MTB_CLAIMSET (0x4100AFA0) /**< \brief (MTB) MTB Claim Set */ -#define REG_MTB_CLAIMCLR (0x4100AFA4) /**< \brief (MTB) MTB Claim Clear */ -#define REG_MTB_LOCKACCESS (0x4100AFB0) /**< \brief (MTB) MTB Lock Access */ -#define REG_MTB_LOCKSTATUS (0x4100AFB4) /**< \brief (MTB) MTB Lock Status */ -#define REG_MTB_AUTHSTATUS (0x4100AFB8) /**< \brief (MTB) MTB Authentication Status */ -#define REG_MTB_DEVARCH (0x4100AFBC) /**< \brief (MTB) MTB Device Architecture */ -#define REG_MTB_DEVID (0x4100AFC8) /**< \brief (MTB) MTB Device Configuration */ -#define REG_MTB_DEVTYPE (0x4100AFCC) /**< \brief (MTB) MTB Device Type */ -#define REG_MTB_PID4 (0x4100AFD0) /**< \brief (MTB) Peripheral Identification 4 */ -#define REG_MTB_PID5 (0x4100AFD4) /**< \brief (MTB) Peripheral Identification 5 */ -#define REG_MTB_PID6 (0x4100AFD8) /**< \brief (MTB) Peripheral Identification 6 */ -#define REG_MTB_PID7 (0x4100AFDC) /**< \brief (MTB) Peripheral Identification 7 */ -#define REG_MTB_PID0 (0x4100AFE0) /**< \brief (MTB) Peripheral Identification 0 */ -#define REG_MTB_PID1 (0x4100AFE4) /**< \brief (MTB) Peripheral Identification 1 */ -#define REG_MTB_PID2 (0x4100AFE8) /**< \brief (MTB) Peripheral Identification 2 */ -#define REG_MTB_PID3 (0x4100AFEC) /**< \brief (MTB) Peripheral Identification 3 */ -#define REG_MTB_CID0 (0x4100AFF0) /**< \brief (MTB) Component Identification 0 */ -#define REG_MTB_CID1 (0x4100AFF4) /**< \brief (MTB) Component Identification 1 */ -#define REG_MTB_CID2 (0x4100AFF8) /**< \brief (MTB) Component Identification 2 */ -#define REG_MTB_CID3 (0x4100AFFC) /**< \brief (MTB) Component Identification 3 */ -#else -#define REG_MTB_POSITION (*(RwReg *)0x4100A000UL) /**< \brief (MTB) MTB Position */ -#define REG_MTB_MASTER (*(RwReg *)0x4100A004UL) /**< \brief (MTB) MTB Master */ -#define REG_MTB_FLOW (*(RwReg *)0x4100A008UL) /**< \brief (MTB) MTB Flow */ -#define REG_MTB_BASE (*(RoReg *)0x4100A00CUL) /**< \brief (MTB) MTB Base */ -#define REG_MTB_ITCTRL (*(RwReg *)0x4100AF00UL) /**< \brief (MTB) MTB Integration Mode Control */ -#define REG_MTB_CLAIMSET (*(RwReg *)0x4100AFA0UL) /**< \brief (MTB) MTB Claim Set */ -#define REG_MTB_CLAIMCLR (*(RwReg *)0x4100AFA4UL) /**< \brief (MTB) MTB Claim Clear */ -#define REG_MTB_LOCKACCESS (*(RwReg *)0x4100AFB0UL) /**< \brief (MTB) MTB Lock Access */ -#define REG_MTB_LOCKSTATUS (*(RoReg *)0x4100AFB4UL) /**< \brief (MTB) MTB Lock Status */ -#define REG_MTB_AUTHSTATUS (*(RoReg *)0x4100AFB8UL) /**< \brief (MTB) MTB Authentication Status */ -#define REG_MTB_DEVARCH (*(RoReg *)0x4100AFBCUL) /**< \brief (MTB) MTB Device Architecture */ -#define REG_MTB_DEVID (*(RoReg *)0x4100AFC8UL) /**< \brief (MTB) MTB Device Configuration */ -#define REG_MTB_DEVTYPE (*(RoReg *)0x4100AFCCUL) /**< \brief (MTB) MTB Device Type */ -#define REG_MTB_PID4 (*(RoReg *)0x4100AFD0UL) /**< \brief (MTB) Peripheral Identification 4 */ -#define REG_MTB_PID5 (*(RoReg *)0x4100AFD4UL) /**< \brief (MTB) Peripheral Identification 5 */ -#define REG_MTB_PID6 (*(RoReg *)0x4100AFD8UL) /**< \brief (MTB) Peripheral Identification 6 */ -#define REG_MTB_PID7 (*(RoReg *)0x4100AFDCUL) /**< \brief (MTB) Peripheral Identification 7 */ -#define REG_MTB_PID0 (*(RoReg *)0x4100AFE0UL) /**< \brief (MTB) Peripheral Identification 0 */ -#define REG_MTB_PID1 (*(RoReg *)0x4100AFE4UL) /**< \brief (MTB) Peripheral Identification 1 */ -#define REG_MTB_PID2 (*(RoReg *)0x4100AFE8UL) /**< \brief (MTB) Peripheral Identification 2 */ -#define REG_MTB_PID3 (*(RoReg *)0x4100AFECUL) /**< \brief (MTB) Peripheral Identification 3 */ -#define REG_MTB_CID0 (*(RoReg *)0x4100AFF0UL) /**< \brief (MTB) Component Identification 0 */ -#define REG_MTB_CID1 (*(RoReg *)0x4100AFF4UL) /**< \brief (MTB) Component Identification 1 */ -#define REG_MTB_CID2 (*(RoReg *)0x4100AFF8UL) /**< \brief (MTB) Component Identification 2 */ -#define REG_MTB_CID3 (*(RoReg *)0x4100AFFCUL) /**< \brief (MTB) Component Identification 3 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - - -#endif /* _SAML22_MTB_INSTANCE_ */ diff --git a/watch-library/include/instance/nvmctrl.h b/watch-library/include/instance/nvmctrl.h deleted file mode 100644 index 89adf7ee..00000000 --- a/watch-library/include/instance/nvmctrl.h +++ /dev/null @@ -1,80 +0,0 @@ -/** - * \file - * - * \brief Instance description for NVMCTRL - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_NVMCTRL_INSTANCE_ -#define _SAML22_NVMCTRL_INSTANCE_ - -/* ========== Register definition for NVMCTRL peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_NVMCTRL_CTRLA (0x41004000) /**< \brief (NVMCTRL) Control A */ -#define REG_NVMCTRL_CTRLB (0x41004004) /**< \brief (NVMCTRL) Control B */ -#define REG_NVMCTRL_PARAM (0x41004008) /**< \brief (NVMCTRL) NVM Parameter */ -#define REG_NVMCTRL_INTENCLR (0x4100400C) /**< \brief (NVMCTRL) Interrupt Enable Clear */ -#define REG_NVMCTRL_INTENSET (0x41004010) /**< \brief (NVMCTRL) Interrupt Enable Set */ -#define REG_NVMCTRL_INTFLAG (0x41004014) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */ -#define REG_NVMCTRL_STATUS (0x41004018) /**< \brief (NVMCTRL) Status */ -#define REG_NVMCTRL_ADDR (0x4100401C) /**< \brief (NVMCTRL) Address */ -#define REG_NVMCTRL_LOCK (0x41004020) /**< \brief (NVMCTRL) Lock Section */ -#else -#define REG_NVMCTRL_CTRLA (*(RwReg16*)0x41004000UL) /**< \brief (NVMCTRL) Control A */ -#define REG_NVMCTRL_CTRLB (*(RwReg *)0x41004004UL) /**< \brief (NVMCTRL) Control B */ -#define REG_NVMCTRL_PARAM (*(RwReg *)0x41004008UL) /**< \brief (NVMCTRL) NVM Parameter */ -#define REG_NVMCTRL_INTENCLR (*(RwReg8 *)0x4100400CUL) /**< \brief (NVMCTRL) Interrupt Enable Clear */ -#define REG_NVMCTRL_INTENSET (*(RwReg8 *)0x41004010UL) /**< \brief (NVMCTRL) Interrupt Enable Set */ -#define REG_NVMCTRL_INTFLAG (*(RwReg8 *)0x41004014UL) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */ -#define REG_NVMCTRL_STATUS (*(RwReg16*)0x41004018UL) /**< \brief (NVMCTRL) Status */ -#define REG_NVMCTRL_ADDR (*(RwReg *)0x4100401CUL) /**< \brief (NVMCTRL) Address */ -#define REG_NVMCTRL_LOCK (*(RwReg16*)0x41004020UL) /**< \brief (NVMCTRL) Lock Section */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for NVMCTRL peripheral ========== */ -#define NVMCTRL_AUX0_ADDRESS 0x00804000 -#define NVMCTRL_AUX1_ADDRESS 0x00806000 -#define NVMCTRL_AUX2_ADDRESS 0x00808000 -#define NVMCTRL_AUX3_ADDRESS 0x0080A000 -#define NVMCTRL_CLK_AHB_ID 8 // Index of AHB Clock in PM.AHBMASK register -#define NVMCTRL_CLK_AHB_ID_PICACHU 10 // Index of PICACHU AHB Clock -#define NVMCTRL_FACTORY_WORD_IMPLEMENTED_MASK 0XC0000007FFFFFFFF -#define NVMCTRL_FLASH_SIZE 262144 -#define NVMCTRL_GCLK_ID 29 // Index of Generic Clock for test -#define NVMCTRL_LOCKBIT_ADDRESS 0x00802000 -#define NVMCTRL_PAGE_HW 32 -#define NVMCTRL_PAGE_SIZE 64 -#define NVMCTRL_PAGE_W 16 -#define NVMCTRL_PMSB 3 -#define NVMCTRL_PSZ_BITS 6 -#define NVMCTRL_ROW_PAGES 4 -#define NVMCTRL_ROW_SIZE 256 -#define NVMCTRL_USER_PAGE_ADDRESS 0x00800000 -#define NVMCTRL_USER_PAGE_OFFSET 0x00800000 -#define NVMCTRL_USER_WORD_IMPLEMENTED_MASK 0XC01FFFFFFFFFFFFF -#define NVMCTRL_RWWEE_PAGES 128 -#define NVMCTRL_RWW_EEPROM_ADDR 0x00400000 // Start address of the RWW EEPROM area - -#endif /* _SAML22_NVMCTRL_INSTANCE_ */ diff --git a/watch-library/include/instance/osc32kctrl.h b/watch-library/include/instance/osc32kctrl.h deleted file mode 100644 index 6edc7597..00000000 --- a/watch-library/include/instance/osc32kctrl.h +++ /dev/null @@ -1,61 +0,0 @@ -/** - * \file - * - * \brief Instance description for OSC32KCTRL - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_OSC32KCTRL_INSTANCE_ -#define _SAML22_OSC32KCTRL_INSTANCE_ - -/* ========== Register definition for OSC32KCTRL peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_OSC32KCTRL_INTENCLR (0x40001400) /**< \brief (OSC32KCTRL) Interrupt Enable Clear */ -#define REG_OSC32KCTRL_INTENSET (0x40001404) /**< \brief (OSC32KCTRL) Interrupt Enable Set */ -#define REG_OSC32KCTRL_INTFLAG (0x40001408) /**< \brief (OSC32KCTRL) Interrupt Flag Status and Clear */ -#define REG_OSC32KCTRL_STATUS (0x4000140C) /**< \brief (OSC32KCTRL) Power and Clocks Status */ -#define REG_OSC32KCTRL_RTCCTRL (0x40001410) /**< \brief (OSC32KCTRL) RTC Clock Selection */ -#define REG_OSC32KCTRL_SLCDCTRL (0x40001411) /**< \brief (OSC32KCTRL) SLCD Clock Selection */ -#define REG_OSC32KCTRL_XOSC32K (0x40001414) /**< \brief (OSC32KCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */ -#define REG_OSC32KCTRL_CFDCTRL (0x40001416) /**< \brief (OSC32KCTRL) Clock Failure Detector Control */ -#define REG_OSC32KCTRL_EVCTRL (0x40001417) /**< \brief (OSC32KCTRL) Event Control */ -#define REG_OSC32KCTRL_OSCULP32K (0x4000141C) /**< \brief (OSC32KCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ -#else -#define REG_OSC32KCTRL_INTENCLR (*(RwReg *)0x40001400UL) /**< \brief (OSC32KCTRL) Interrupt Enable Clear */ -#define REG_OSC32KCTRL_INTENSET (*(RwReg *)0x40001404UL) /**< \brief (OSC32KCTRL) Interrupt Enable Set */ -#define REG_OSC32KCTRL_INTFLAG (*(RwReg *)0x40001408UL) /**< \brief (OSC32KCTRL) Interrupt Flag Status and Clear */ -#define REG_OSC32KCTRL_STATUS (*(RoReg *)0x4000140CUL) /**< \brief (OSC32KCTRL) Power and Clocks Status */ -#define REG_OSC32KCTRL_RTCCTRL (*(RwReg8 *)0x40001410UL) /**< \brief (OSC32KCTRL) RTC Clock Selection */ -#define REG_OSC32KCTRL_SLCDCTRL (*(RwReg8 *)0x40001411UL) /**< \brief (OSC32KCTRL) SLCD Clock Selection */ -#define REG_OSC32KCTRL_XOSC32K (*(RwReg16*)0x40001414UL) /**< \brief (OSC32KCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */ -#define REG_OSC32KCTRL_CFDCTRL (*(RwReg8 *)0x40001416UL) /**< \brief (OSC32KCTRL) Clock Failure Detector Control */ -#define REG_OSC32KCTRL_EVCTRL (*(RwReg8 *)0x40001417UL) /**< \brief (OSC32KCTRL) Event Control */ -#define REG_OSC32KCTRL_OSCULP32K (*(RwReg *)0x4000141CUL) /**< \brief (OSC32KCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for OSC32KCTRL peripheral ========== */ -#define OSC32KCTRL_OSC32K_COARSE_CALIB_MSB 6 - -#endif /* _SAML22_OSC32KCTRL_INSTANCE_ */ diff --git a/watch-library/include/instance/oscctrl.h b/watch-library/include/instance/oscctrl.h deleted file mode 100644 index bd390207..00000000 --- a/watch-library/include/instance/oscctrl.h +++ /dev/null @@ -1,86 +0,0 @@ -/** - * \file - * - * \brief Instance description for OSCCTRL - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_OSCCTRL_INSTANCE_ -#define _SAML22_OSCCTRL_INSTANCE_ - -/* ========== Register definition for OSCCTRL peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_OSCCTRL_INTENCLR (0x40001000) /**< \brief (OSCCTRL) Interrupt Enable Clear */ -#define REG_OSCCTRL_INTENSET (0x40001004) /**< \brief (OSCCTRL) Interrupt Enable Set */ -#define REG_OSCCTRL_INTFLAG (0x40001008) /**< \brief (OSCCTRL) Interrupt Flag Status and Clear */ -#define REG_OSCCTRL_STATUS (0x4000100C) /**< \brief (OSCCTRL) Power and Clocks Status */ -#define REG_OSCCTRL_XOSCCTRL (0x40001010) /**< \brief (OSCCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */ -#define REG_OSCCTRL_CFDPRESC (0x40001012) /**< \brief (OSCCTRL) Cloc Failure Detector Prescaler */ -#define REG_OSCCTRL_EVCTRL (0x40001013) /**< \brief (OSCCTRL) Event Control */ -#define REG_OSCCTRL_OSC16MCTRL (0x40001014) /**< \brief (OSCCTRL) 16MHz Internal Oscillator (OSC16M) Control */ -#define REG_OSCCTRL_DFLLCTRL (0x40001018) /**< \brief (OSCCTRL) DFLL48M Control */ -#define REG_OSCCTRL_DFLLVAL (0x4000101C) /**< \brief (OSCCTRL) DFLL48M Value */ -#define REG_OSCCTRL_DFLLMUL (0x40001020) /**< \brief (OSCCTRL) DFLL48M Multiplier */ -#define REG_OSCCTRL_DFLLSYNC (0x40001024) /**< \brief (OSCCTRL) DFLL48M Synchronization */ -#define REG_OSCCTRL_DPLLCTRLA (0x40001028) /**< \brief (OSCCTRL) DPLL Control */ -#define REG_OSCCTRL_DPLLRATIO (0x4000102C) /**< \brief (OSCCTRL) DPLL Ratio Control */ -#define REG_OSCCTRL_DPLLCTRLB (0x40001030) /**< \brief (OSCCTRL) Digital Core Configuration */ -#define REG_OSCCTRL_DPLLPRESC (0x40001034) /**< \brief (OSCCTRL) DPLL Prescaler */ -#define REG_OSCCTRL_DPLLSYNCBUSY (0x40001038) /**< \brief (OSCCTRL) DPLL Synchronization Busy */ -#define REG_OSCCTRL_DPLLSTATUS (0x4000103C) /**< \brief (OSCCTRL) DPLL Status */ -#else -#define REG_OSCCTRL_INTENCLR (*(RwReg *)0x40001000UL) /**< \brief (OSCCTRL) Interrupt Enable Clear */ -#define REG_OSCCTRL_INTENSET (*(RwReg *)0x40001004UL) /**< \brief (OSCCTRL) Interrupt Enable Set */ -#define REG_OSCCTRL_INTFLAG (*(RwReg *)0x40001008UL) /**< \brief (OSCCTRL) Interrupt Flag Status and Clear */ -#define REG_OSCCTRL_STATUS (*(RoReg *)0x4000100CUL) /**< \brief (OSCCTRL) Power and Clocks Status */ -#define REG_OSCCTRL_XOSCCTRL (*(RwReg16*)0x40001010UL) /**< \brief (OSCCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */ -#define REG_OSCCTRL_CFDPRESC (*(RwReg8 *)0x40001012UL) /**< \brief (OSCCTRL) Cloc Failure Detector Prescaler */ -#define REG_OSCCTRL_EVCTRL (*(RwReg8 *)0x40001013UL) /**< \brief (OSCCTRL) Event Control */ -#define REG_OSCCTRL_OSC16MCTRL (*(RwReg8 *)0x40001014UL) /**< \brief (OSCCTRL) 16MHz Internal Oscillator (OSC16M) Control */ -#define REG_OSCCTRL_DFLLCTRL (*(RwReg16*)0x40001018UL) /**< \brief (OSCCTRL) DFLL48M Control */ -#define REG_OSCCTRL_DFLLVAL (*(RwReg *)0x4000101CUL) /**< \brief (OSCCTRL) DFLL48M Value */ -#define REG_OSCCTRL_DFLLMUL (*(RwReg *)0x40001020UL) /**< \brief (OSCCTRL) DFLL48M Multiplier */ -#define REG_OSCCTRL_DFLLSYNC (*(RwReg8 *)0x40001024UL) /**< \brief (OSCCTRL) DFLL48M Synchronization */ -#define REG_OSCCTRL_DPLLCTRLA (*(RwReg8 *)0x40001028UL) /**< \brief (OSCCTRL) DPLL Control */ -#define REG_OSCCTRL_DPLLRATIO (*(RwReg *)0x4000102CUL) /**< \brief (OSCCTRL) DPLL Ratio Control */ -#define REG_OSCCTRL_DPLLCTRLB (*(RwReg *)0x40001030UL) /**< \brief (OSCCTRL) Digital Core Configuration */ -#define REG_OSCCTRL_DPLLPRESC (*(RwReg8 *)0x40001034UL) /**< \brief (OSCCTRL) DPLL Prescaler */ -#define REG_OSCCTRL_DPLLSYNCBUSY (*(RoReg8 *)0x40001038UL) /**< \brief (OSCCTRL) DPLL Synchronization Busy */ -#define REG_OSCCTRL_DPLLSTATUS (*(RoReg8 *)0x4000103CUL) /**< \brief (OSCCTRL) DPLL Status */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for OSCCTRL peripheral ========== */ -#define OSCCTRL_DFLL48M_COARSE_MSB 5 -#define OSCCTRL_DFLL48M_FINE_MSB 9 -#define OSCCTRL_GCLK_ID_DFLL48 0 // Index of Generic Clock for DFLL48 -#define OSCCTRL_GCLK_ID_FDPLL 1 // Index of Generic Clock for DPLL -#define OSCCTRL_GCLK_ID_FDPLL32K 2 // Index of Generic Clock for DPLL 32K -#define OSCCTRL_CFD_VERSION 0x100 -#define OSCCTRL_DFLL48M_VERSION 0x320 -#define OSCCTRL_FDPLL_VERSION 0x211 -#define OSCCTRL_OSC16M_VERSION 0x101 -#define OSCCTRL_XOSC_VERSION 0x201 - -#endif /* _SAML22_OSCCTRL_INSTANCE_ */ diff --git a/watch-library/include/instance/pac.h b/watch-library/include/instance/pac.h deleted file mode 100644 index cc3d94d5..00000000 --- a/watch-library/include/instance/pac.h +++ /dev/null @@ -1,66 +0,0 @@ -/** - * \file - * - * \brief Instance description for PAC - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_PAC_INSTANCE_ -#define _SAML22_PAC_INSTANCE_ - -/* ========== Register definition for PAC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_PAC_WRCTRL (0x40000000) /**< \brief (PAC) Write control */ -#define REG_PAC_EVCTRL (0x40000004) /**< \brief (PAC) Event control */ -#define REG_PAC_INTENCLR (0x40000008) /**< \brief (PAC) Interrupt enable clear */ -#define REG_PAC_INTENSET (0x40000009) /**< \brief (PAC) Interrupt enable set */ -#define REG_PAC_INTFLAGAHB (0x40000010) /**< \brief (PAC) Bridge interrupt flag status */ -#define REG_PAC_INTFLAGA (0x40000014) /**< \brief (PAC) Peripheral interrupt flag status - Bridge A */ -#define REG_PAC_INTFLAGB (0x40000018) /**< \brief (PAC) Peripheral interrupt flag status - Bridge B */ -#define REG_PAC_INTFLAGC (0x4000001C) /**< \brief (PAC) Peripheral interrupt flag status - Bridge C */ -#define REG_PAC_STATUSA (0x40000034) /**< \brief (PAC) Peripheral write protection status - Bridge A */ -#define REG_PAC_STATUSB (0x40000038) /**< \brief (PAC) Peripheral write protection status - Bridge B */ -#define REG_PAC_STATUSC (0x4000003C) /**< \brief (PAC) Peripheral write protection status - Bridge C */ -#else -#define REG_PAC_WRCTRL (*(RwReg *)0x40000000UL) /**< \brief (PAC) Write control */ -#define REG_PAC_EVCTRL (*(RwReg8 *)0x40000004UL) /**< \brief (PAC) Event control */ -#define REG_PAC_INTENCLR (*(RwReg8 *)0x40000008UL) /**< \brief (PAC) Interrupt enable clear */ -#define REG_PAC_INTENSET (*(RwReg8 *)0x40000009UL) /**< \brief (PAC) Interrupt enable set */ -#define REG_PAC_INTFLAGAHB (*(RwReg *)0x40000010UL) /**< \brief (PAC) Bridge interrupt flag status */ -#define REG_PAC_INTFLAGA (*(RwReg *)0x40000014UL) /**< \brief (PAC) Peripheral interrupt flag status - Bridge A */ -#define REG_PAC_INTFLAGB (*(RwReg *)0x40000018UL) /**< \brief (PAC) Peripheral interrupt flag status - Bridge B */ -#define REG_PAC_INTFLAGC (*(RwReg *)0x4000001CUL) /**< \brief (PAC) Peripheral interrupt flag status - Bridge C */ -#define REG_PAC_STATUSA (*(RoReg *)0x40000034UL) /**< \brief (PAC) Peripheral write protection status - Bridge A */ -#define REG_PAC_STATUSB (*(RoReg *)0x40000038UL) /**< \brief (PAC) Peripheral write protection status - Bridge B */ -#define REG_PAC_STATUSC (*(RoReg *)0x4000003CUL) /**< \brief (PAC) Peripheral write protection status - Bridge C */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for PAC peripheral ========== */ -#define PAC_CLK_AHB_DOMAIN // Clock domain of AHB clock -#define PAC_CLK_AHB_ID 7 // AHB clock index -#define PAC_HPB_NUM 3 // Number of bridges AHB/APB -#define PAC_INTFLAG_NUM 4 // Number of intflag registers - -#endif /* _SAML22_PAC_INSTANCE_ */ diff --git a/watch-library/include/instance/pm.h b/watch-library/include/instance/pm.h deleted file mode 100644 index 6ca464f2..00000000 --- a/watch-library/include/instance/pm.h +++ /dev/null @@ -1,56 +0,0 @@ -/** - * \file - * - * \brief Instance description for PM - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_PM_INSTANCE_ -#define _SAML22_PM_INSTANCE_ - -/* ========== Register definition for PM peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_PM_CTRLA (0x40000400) /**< \brief (PM) Control A */ -#define REG_PM_SLEEPCFG (0x40000401) /**< \brief (PM) Sleep Configuration */ -#define REG_PM_PLCFG (0x40000402) /**< \brief (PM) Performance Level Configuration */ -#define REG_PM_INTENCLR (0x40000404) /**< \brief (PM) Interrupt Enable Clear */ -#define REG_PM_INTENSET (0x40000405) /**< \brief (PM) Interrupt Enable Set */ -#define REG_PM_INTFLAG (0x40000406) /**< \brief (PM) Interrupt Flag Status and Clear */ -#define REG_PM_STDBYCFG (0x40000408) /**< \brief (PM) Standby Configuration */ -#else -#define REG_PM_CTRLA (*(RwReg8 *)0x40000400UL) /**< \brief (PM) Control A */ -#define REG_PM_SLEEPCFG (*(RwReg8 *)0x40000401UL) /**< \brief (PM) Sleep Configuration */ -#define REG_PM_PLCFG (*(RwReg8 *)0x40000402UL) /**< \brief (PM) Performance Level Configuration */ -#define REG_PM_INTENCLR (*(RwReg8 *)0x40000404UL) /**< \brief (PM) Interrupt Enable Clear */ -#define REG_PM_INTENSET (*(RwReg8 *)0x40000405UL) /**< \brief (PM) Interrupt Enable Set */ -#define REG_PM_INTFLAG (*(RwReg8 *)0x40000406UL) /**< \brief (PM) Interrupt Flag Status and Clear */ -#define REG_PM_STDBYCFG (*(RwReg16*)0x40000408UL) /**< \brief (PM) Standby Configuration */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for PM peripheral ========== */ -#define PM_BIAS_RAM_HS 1 // one if RAM HS can be back biased -#define PM_PD_NUM 0 // Number of switchable Power Domain - -#endif /* _SAML22_PM_INSTANCE_ */ diff --git a/watch-library/include/instance/port.h b/watch-library/include/instance/port.h deleted file mode 100644 index 6ec1564d..00000000 --- a/watch-library/include/instance/port.h +++ /dev/null @@ -1,155 +0,0 @@ -/** - * \file - * - * \brief Instance description for PORT - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_PORT_INSTANCE_ -#define _SAML22_PORT_INSTANCE_ - -/* ========== Register definition for PORT peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_PORT_DIR0 (0x41006000) /**< \brief (PORT) Data Direction 0 */ -#define REG_PORT_DIRCLR0 (0x41006004) /**< \brief (PORT) Data Direction Clear 0 */ -#define REG_PORT_DIRSET0 (0x41006008) /**< \brief (PORT) Data Direction Set 0 */ -#define REG_PORT_DIRTGL0 (0x4100600C) /**< \brief (PORT) Data Direction Toggle 0 */ -#define REG_PORT_OUT0 (0x41006010) /**< \brief (PORT) Data Output Value 0 */ -#define REG_PORT_OUTCLR0 (0x41006014) /**< \brief (PORT) Data Output Value Clear 0 */ -#define REG_PORT_OUTSET0 (0x41006018) /**< \brief (PORT) Data Output Value Set 0 */ -#define REG_PORT_OUTTGL0 (0x4100601C) /**< \brief (PORT) Data Output Value Toggle 0 */ -#define REG_PORT_IN0 (0x41006020) /**< \brief (PORT) Data Input Value 0 */ -#define REG_PORT_CTRL0 (0x41006024) /**< \brief (PORT) Control 0 */ -#define REG_PORT_WRCONFIG0 (0x41006028) /**< \brief (PORT) Write Configuration 0 */ -#define REG_PORT_EVCTRL0 (0x4100602C) /**< \brief (PORT) Event Input Control 0 */ -#define REG_PORT_PMUX0 (0x41006030) /**< \brief (PORT) Peripheral Multiplexing 0 */ -#define REG_PORT_PINCFG0 (0x41006040) /**< \brief (PORT) Pin Configuration 0 */ -#define REG_PORT_DIR1 (0x41006080) /**< \brief (PORT) Data Direction 1 */ -#define REG_PORT_DIRCLR1 (0x41006084) /**< \brief (PORT) Data Direction Clear 1 */ -#define REG_PORT_DIRSET1 (0x41006088) /**< \brief (PORT) Data Direction Set 1 */ -#define REG_PORT_DIRTGL1 (0x4100608C) /**< \brief (PORT) Data Direction Toggle 1 */ -#define REG_PORT_OUT1 (0x41006090) /**< \brief (PORT) Data Output Value 1 */ -#define REG_PORT_OUTCLR1 (0x41006094) /**< \brief (PORT) Data Output Value Clear 1 */ -#define REG_PORT_OUTSET1 (0x41006098) /**< \brief (PORT) Data Output Value Set 1 */ -#define REG_PORT_OUTTGL1 (0x4100609C) /**< \brief (PORT) Data Output Value Toggle 1 */ -#define REG_PORT_IN1 (0x410060A0) /**< \brief (PORT) Data Input Value 1 */ -#define REG_PORT_CTRL1 (0x410060A4) /**< \brief (PORT) Control 1 */ -#define REG_PORT_WRCONFIG1 (0x410060A8) /**< \brief (PORT) Write Configuration 1 */ -#define REG_PORT_EVCTRL1 (0x410060AC) /**< \brief (PORT) Event Input Control 1 */ -#define REG_PORT_PMUX1 (0x410060B0) /**< \brief (PORT) Peripheral Multiplexing 1 */ -#define REG_PORT_PINCFG1 (0x410060C0) /**< \brief (PORT) Pin Configuration 1 */ -#define REG_PORT_DIR2 (0x41006100) /**< \brief (PORT) Data Direction 2 */ -#define REG_PORT_DIRCLR2 (0x41006104) /**< \brief (PORT) Data Direction Clear 2 */ -#define REG_PORT_DIRSET2 (0x41006108) /**< \brief (PORT) Data Direction Set 2 */ -#define REG_PORT_DIRTGL2 (0x4100610C) /**< \brief (PORT) Data Direction Toggle 2 */ -#define REG_PORT_OUT2 (0x41006110) /**< \brief (PORT) Data Output Value 2 */ -#define REG_PORT_OUTCLR2 (0x41006114) /**< \brief (PORT) Data Output Value Clear 2 */ -#define REG_PORT_OUTSET2 (0x41006118) /**< \brief (PORT) Data Output Value Set 2 */ -#define REG_PORT_OUTTGL2 (0x4100611C) /**< \brief (PORT) Data Output Value Toggle 2 */ -#define REG_PORT_IN2 (0x41006120) /**< \brief (PORT) Data Input Value 2 */ -#define REG_PORT_CTRL2 (0x41006124) /**< \brief (PORT) Control 2 */ -#define REG_PORT_WRCONFIG2 (0x41006128) /**< \brief (PORT) Write Configuration 2 */ -#define REG_PORT_EVCTRL2 (0x4100612C) /**< \brief (PORT) Event Input Control 2 */ -#define REG_PORT_PMUX2 (0x41006130) /**< \brief (PORT) Peripheral Multiplexing 2 */ -#define REG_PORT_PINCFG2 (0x41006140) /**< \brief (PORT) Pin Configuration 2 */ -#else -#define REG_PORT_DIR0 (*(RwReg *)0x41006000UL) /**< \brief (PORT) Data Direction 0 */ -#define REG_PORT_DIRCLR0 (*(RwReg *)0x41006004UL) /**< \brief (PORT) Data Direction Clear 0 */ -#define REG_PORT_DIRSET0 (*(RwReg *)0x41006008UL) /**< \brief (PORT) Data Direction Set 0 */ -#define REG_PORT_DIRTGL0 (*(RwReg *)0x4100600CUL) /**< \brief (PORT) Data Direction Toggle 0 */ -#define REG_PORT_OUT0 (*(RwReg *)0x41006010UL) /**< \brief (PORT) Data Output Value 0 */ -#define REG_PORT_OUTCLR0 (*(RwReg *)0x41006014UL) /**< \brief (PORT) Data Output Value Clear 0 */ -#define REG_PORT_OUTSET0 (*(RwReg *)0x41006018UL) /**< \brief (PORT) Data Output Value Set 0 */ -#define REG_PORT_OUTTGL0 (*(RwReg *)0x4100601CUL) /**< \brief (PORT) Data Output Value Toggle 0 */ -#define REG_PORT_IN0 (*(RoReg *)0x41006020UL) /**< \brief (PORT) Data Input Value 0 */ -#define REG_PORT_CTRL0 (*(RwReg *)0x41006024UL) /**< \brief (PORT) Control 0 */ -#define REG_PORT_WRCONFIG0 (*(WoReg *)0x41006028UL) /**< \brief (PORT) Write Configuration 0 */ -#define REG_PORT_EVCTRL0 (*(RwReg *)0x4100602CUL) /**< \brief (PORT) Event Input Control 0 */ -#define REG_PORT_PMUX0 (*(RwReg8 *)0x41006030UL) /**< \brief (PORT) Peripheral Multiplexing 0 */ -#define REG_PORT_PINCFG0 (*(RwReg8 *)0x41006040UL) /**< \brief (PORT) Pin Configuration 0 */ -#define REG_PORT_DIR1 (*(RwReg *)0x41006080UL) /**< \brief (PORT) Data Direction 1 */ -#define REG_PORT_DIRCLR1 (*(RwReg *)0x41006084UL) /**< \brief (PORT) Data Direction Clear 1 */ -#define REG_PORT_DIRSET1 (*(RwReg *)0x41006088UL) /**< \brief (PORT) Data Direction Set 1 */ -#define REG_PORT_DIRTGL1 (*(RwReg *)0x4100608CUL) /**< \brief (PORT) Data Direction Toggle 1 */ -#define REG_PORT_OUT1 (*(RwReg *)0x41006090UL) /**< \brief (PORT) Data Output Value 1 */ -#define REG_PORT_OUTCLR1 (*(RwReg *)0x41006094UL) /**< \brief (PORT) Data Output Value Clear 1 */ -#define REG_PORT_OUTSET1 (*(RwReg *)0x41006098UL) /**< \brief (PORT) Data Output Value Set 1 */ -#define REG_PORT_OUTTGL1 (*(RwReg *)0x4100609CUL) /**< \brief (PORT) Data Output Value Toggle 1 */ -#define REG_PORT_IN1 (*(RoReg *)0x410060A0UL) /**< \brief (PORT) Data Input Value 1 */ -#define REG_PORT_CTRL1 (*(RwReg *)0x410060A4UL) /**< \brief (PORT) Control 1 */ -#define REG_PORT_WRCONFIG1 (*(WoReg *)0x410060A8UL) /**< \brief (PORT) Write Configuration 1 */ -#define REG_PORT_EVCTRL1 (*(RwReg *)0x410060ACUL) /**< \brief (PORT) Event Input Control 1 */ -#define REG_PORT_PMUX1 (*(RwReg8 *)0x410060B0UL) /**< \brief (PORT) Peripheral Multiplexing 1 */ -#define REG_PORT_PINCFG1 (*(RwReg8 *)0x410060C0UL) /**< \brief (PORT) Pin Configuration 1 */ -#define REG_PORT_DIR2 (*(RwReg *)0x41006100UL) /**< \brief (PORT) Data Direction 2 */ -#define REG_PORT_DIRCLR2 (*(RwReg *)0x41006104UL) /**< \brief (PORT) Data Direction Clear 2 */ -#define REG_PORT_DIRSET2 (*(RwReg *)0x41006108UL) /**< \brief (PORT) Data Direction Set 2 */ -#define REG_PORT_DIRTGL2 (*(RwReg *)0x4100610CUL) /**< \brief (PORT) Data Direction Toggle 2 */ -#define REG_PORT_OUT2 (*(RwReg *)0x41006110UL) /**< \brief (PORT) Data Output Value 2 */ -#define REG_PORT_OUTCLR2 (*(RwReg *)0x41006114UL) /**< \brief (PORT) Data Output Value Clear 2 */ -#define REG_PORT_OUTSET2 (*(RwReg *)0x41006118UL) /**< \brief (PORT) Data Output Value Set 2 */ -#define REG_PORT_OUTTGL2 (*(RwReg *)0x4100611CUL) /**< \brief (PORT) Data Output Value Toggle 2 */ -#define REG_PORT_IN2 (*(RoReg *)0x41006120UL) /**< \brief (PORT) Data Input Value 2 */ -#define REG_PORT_CTRL2 (*(RwReg *)0x41006124UL) /**< \brief (PORT) Control 2 */ -#define REG_PORT_WRCONFIG2 (*(WoReg *)0x41006128UL) /**< \brief (PORT) Write Configuration 2 */ -#define REG_PORT_EVCTRL2 (*(RwReg *)0x4100612CUL) /**< \brief (PORT) Event Input Control 2 */ -#define REG_PORT_PMUX2 (*(RwReg8 *)0x41006130UL) /**< \brief (PORT) Peripheral Multiplexing 2 */ -#define REG_PORT_PINCFG2 (*(RwReg8 *)0x41006140UL) /**< \brief (PORT) Pin Configuration 2 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for PORT peripheral ========== */ -#define PORT_BITS 93 -#define PORT_DIR_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } -#define PORT_DIR_IMPLEMENTED { 0xCBFFFFFF, 0xC3FFFBFF, 0x1F3FFFEF } -#define PORT_DRVSTR 1 // DRVSTR supported -#define PORT_DRVSTR_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } -#define PORT_DRVSTR_IMPLEMENTED { 0xC8FFFFFF, 0xC3FFFBFF, 0x1F3FF0EF } -#define PORT_EVENT_IMPLEMENTED { 0xCBFFFFFF, 0xC3FFFBFF, 0x1F03F0EF } -#define PORT_EV_NUM 4 -#define PORT_INEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } -#define PORT_INEN_IMPLEMENTED { 0xCBFFFFFF, 0xC3FFFBFF, 0x1F3FFFEF } -#define PORT_ODRAIN 0 // ODRAIN supported -#define PORT_ODRAIN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } -#define PORT_ODRAIN_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 } -#define PORT_OUT_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } -#define PORT_OUT_IMPLEMENTED { 0xCBFFFFFF, 0xC3FFFBFF, 0x1F3FFFEF } -#define PORT_PIN_IMPLEMENTED { 0xCBFFFFFF, 0xC3FFFBFF, 0x1F3FFFEF } -#define PORT_PMUXBIT0_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } -#define PORT_PMUXBIT0_IMPLEMENTED { 0xCBFFFFFF, 0xC3FFFBFF, 0x1F3FFFEF } -#define PORT_PMUXBIT1_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000 } -#define PORT_PMUXBIT1_IMPLEMENTED { 0xCBFFFFF7, 0xC3FFFB0F, 0x1B003C03 } -#define PORT_PMUXBIT2_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000 } -#define PORT_PMUXBIT2_IMPLEMENTED { 0x4BFFFF34, 0xC3FFFB0F, 0x1F000003 } -#define PORT_PMUXBIT3_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } -#define PORT_PMUXBIT3_IMPLEMENTED { 0xC3CF0FF0, 0x00C3CBC7, 0x18300000 } -#define PORT_PMUXEN_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000 } -#define PORT_PMUXEN_IMPLEMENTED { 0xCBFFFFFF, 0xC3FFFBFF, 0x1F3FFFEF } -#define PORT_PULLEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } -#define PORT_PULLEN_IMPLEMENTED { 0xCBFFFFFF, 0xC3FFFBFF, 0x1F3FFFEF } -#define PORT_SLEWLIM 0 // SLEWLIM supported -#define PORT_SLEWLIM_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } -#define PORT_SLEWLIM_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 } - -#endif /* _SAML22_PORT_INSTANCE_ */ diff --git a/watch-library/include/instance/ptc.h b/watch-library/include/instance/ptc.h deleted file mode 100644 index 03c6b30d..00000000 --- a/watch-library/include/instance/ptc.h +++ /dev/null @@ -1,43 +0,0 @@ -/** - * \file - * - * \brief Instance description for PTC - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_PTC_INSTANCE_ -#define _SAML22_PTC_INSTANCE_ - -/* ========== Instance parameters for PTC peripheral ========== */ -#define PTC_DMAC_ID_EOC 37 // Index of DMA EOC trigger -#define PTC_DMAC_ID_SEQ 38 // Index of DMA SEQ trigger -#define PTC_DMAC_ID_WCOMP 39 // Index of DMA WCOMP trigger -#define PTC_GCLK_ID 27 // Index of Generic Clock -#define PTC_LINES_MSB 31 -#define PTC_LINES_NUM 32 // Number of PTC lines -#define PTC_Y_LINES_MSB 23 -#define PTC_Y_LINES_NUM 24 // Number of Y lines - -#endif /* _SAML22_PTC_INSTANCE_ */ diff --git a/watch-library/include/instance/rstc.h b/watch-library/include/instance/rstc.h deleted file mode 100644 index e6186fd4..00000000 --- a/watch-library/include/instance/rstc.h +++ /dev/null @@ -1,46 +0,0 @@ -/** - * \file - * - * \brief Instance description for RSTC - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_RSTC_INSTANCE_ -#define _SAML22_RSTC_INSTANCE_ - -/* ========== Register definition for RSTC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_RSTC_RCAUSE (0x40000C00) /**< \brief (RSTC) Reset Cause */ -#define REG_RSTC_BKUPEXIT (0x40000C02) /**< \brief (RSTC) Backup Exit Source */ -#else -#define REG_RSTC_RCAUSE (*(RoReg8 *)0x40000C00UL) /**< \brief (RSTC) Reset Cause */ -#define REG_RSTC_BKUPEXIT (*(RoReg8 *)0x40000C02UL) /**< \brief (RSTC) Backup Exit Source */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for RSTC peripheral ========== */ -#define RSTC_BACKUP_IMPLEMENTED 1 -#define RSTC_NUMBER_OF_EXTWAKE 0 // number of external wakeup line - -#endif /* _SAML22_RSTC_INSTANCE_ */ diff --git a/watch-library/include/instance/rtc.h b/watch-library/include/instance/rtc.h deleted file mode 100644 index 5c6bf72d..00000000 --- a/watch-library/include/instance/rtc.h +++ /dev/null @@ -1,142 +0,0 @@ -/** - * \file - * - * \brief Instance description for RTC - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_RTC_INSTANCE_ -#define _SAML22_RTC_INSTANCE_ - -/* ========== Register definition for RTC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_RTC_DBGCTRL (0x4000240E) /**< \brief (RTC) Debug Control */ -#define REG_RTC_FREQCORR (0x40002414) /**< \brief (RTC) Frequency Correction */ -#define REG_RTC_GP0 (0x40002440) /**< \brief (RTC) General Purpose 0 */ -#define REG_RTC_GP1 (0x40002444) /**< \brief (RTC) General Purpose 1 */ -#define REG_RTC_TAMPCTRL (0x40002460) /**< \brief (RTC) Tamper Control */ -#define REG_RTC_TAMPID (0x40002468) /**< \brief (RTC) Tamper ID */ -#define REG_RTC_BKUP0 (0x40002480) /**< \brief (RTC) Backup 0 */ -#define REG_RTC_BKUP1 (0x40002484) /**< \brief (RTC) Backup 1 */ -#define REG_RTC_BKUP2 (0x40002488) /**< \brief (RTC) Backup 2 */ -#define REG_RTC_BKUP3 (0x4000248C) /**< \brief (RTC) Backup 3 */ -#define REG_RTC_BKUP4 (0x40002490) /**< \brief (RTC) Backup 4 */ -#define REG_RTC_BKUP5 (0x40002494) /**< \brief (RTC) Backup 5 */ -#define REG_RTC_BKUP6 (0x40002498) /**< \brief (RTC) Backup 6 */ -#define REG_RTC_BKUP7 (0x4000249C) /**< \brief (RTC) Backup 7 */ -#define REG_RTC_MODE0_CTRLA (0x40002400) /**< \brief (RTC) MODE0 Control A */ -#define REG_RTC_MODE0_CTRLB (0x40002402) /**< \brief (RTC) MODE0 Control B */ -#define REG_RTC_MODE0_EVCTRL (0x40002404) /**< \brief (RTC) MODE0 Event Control */ -#define REG_RTC_MODE0_INTENCLR (0x40002408) /**< \brief (RTC) MODE0 Interrupt Enable Clear */ -#define REG_RTC_MODE0_INTENSET (0x4000240A) /**< \brief (RTC) MODE0 Interrupt Enable Set */ -#define REG_RTC_MODE0_INTFLAG (0x4000240C) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */ -#define REG_RTC_MODE0_SYNCBUSY (0x40002410) /**< \brief (RTC) MODE0 Synchronization Busy Status */ -#define REG_RTC_MODE0_COUNT (0x40002418) /**< \brief (RTC) MODE0 Counter Value */ -#define REG_RTC_MODE0_COMP0 (0x40002420) /**< \brief (RTC) MODE0 Compare 0 Value */ -#define REG_RTC_MODE0_TIMESTAMP (0x40002464) /**< \brief (RTC) MODE0 Timestamp */ -#define REG_RTC_MODE1_CTRLA (0x40002400) /**< \brief (RTC) MODE1 Control A */ -#define REG_RTC_MODE1_CTRLB (0x40002402) /**< \brief (RTC) MODE1 Control B */ -#define REG_RTC_MODE1_EVCTRL (0x40002404) /**< \brief (RTC) MODE1 Event Control */ -#define REG_RTC_MODE1_INTENCLR (0x40002408) /**< \brief (RTC) MODE1 Interrupt Enable Clear */ -#define REG_RTC_MODE1_INTENSET (0x4000240A) /**< \brief (RTC) MODE1 Interrupt Enable Set */ -#define REG_RTC_MODE1_INTFLAG (0x4000240C) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */ -#define REG_RTC_MODE1_SYNCBUSY (0x40002410) /**< \brief (RTC) MODE1 Synchronization Busy Status */ -#define REG_RTC_MODE1_COUNT (0x40002418) /**< \brief (RTC) MODE1 Counter Value */ -#define REG_RTC_MODE1_PER (0x4000241C) /**< \brief (RTC) MODE1 Counter Period */ -#define REG_RTC_MODE1_COMP0 (0x40002420) /**< \brief (RTC) MODE1 Compare 0 Value */ -#define REG_RTC_MODE1_COMP1 (0x40002422) /**< \brief (RTC) MODE1 Compare 1 Value */ -#define REG_RTC_MODE1_TIMESTAMP (0x40002464) /**< \brief (RTC) MODE1 Timestamp */ -#define REG_RTC_MODE2_CTRLA (0x40002400) /**< \brief (RTC) MODE2 Control A */ -#define REG_RTC_MODE2_CTRLB (0x40002402) /**< \brief (RTC) MODE2 Control B */ -#define REG_RTC_MODE2_EVCTRL (0x40002404) /**< \brief (RTC) MODE2 Event Control */ -#define REG_RTC_MODE2_INTENCLR (0x40002408) /**< \brief (RTC) MODE2 Interrupt Enable Clear */ -#define REG_RTC_MODE2_INTENSET (0x4000240A) /**< \brief (RTC) MODE2 Interrupt Enable Set */ -#define REG_RTC_MODE2_INTFLAG (0x4000240C) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */ -#define REG_RTC_MODE2_SYNCBUSY (0x40002410) /**< \brief (RTC) MODE2 Synchronization Busy Status */ -#define REG_RTC_MODE2_CLOCK (0x40002418) /**< \brief (RTC) MODE2 Clock Value */ -#define REG_RTC_MODE2_TIMESTAMP (0x40002464) /**< \brief (RTC) MODE2 Timestamp */ -#define REG_RTC_MODE2_ALARM_ALARM0 (0x40002420) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */ -#define REG_RTC_MODE2_ALARM_MASK0 (0x40002424) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */ -#else -#define REG_RTC_DBGCTRL (*(RwReg8 *)0x4000240EUL) /**< \brief (RTC) Debug Control */ -#define REG_RTC_FREQCORR (*(RwReg8 *)0x40002414UL) /**< \brief (RTC) Frequency Correction */ -#define REG_RTC_GP0 (*(RwReg *)0x40002440UL) /**< \brief (RTC) General Purpose 0 */ -#define REG_RTC_GP1 (*(RwReg *)0x40002444UL) /**< \brief (RTC) General Purpose 1 */ -#define REG_RTC_TAMPCTRL (*(RwReg *)0x40002460UL) /**< \brief (RTC) Tamper Control */ -#define REG_RTC_TAMPID (*(RwReg *)0x40002468UL) /**< \brief (RTC) Tamper ID */ -#define REG_RTC_BKUP0 (*(RwReg *)0x40002480UL) /**< \brief (RTC) Backup 0 */ -#define REG_RTC_BKUP1 (*(RwReg *)0x40002484UL) /**< \brief (RTC) Backup 1 */ -#define REG_RTC_BKUP2 (*(RwReg *)0x40002488UL) /**< \brief (RTC) Backup 2 */ -#define REG_RTC_BKUP3 (*(RwReg *)0x4000248CUL) /**< \brief (RTC) Backup 3 */ -#define REG_RTC_BKUP4 (*(RwReg *)0x40002490UL) /**< \brief (RTC) Backup 4 */ -#define REG_RTC_BKUP5 (*(RwReg *)0x40002494UL) /**< \brief (RTC) Backup 5 */ -#define REG_RTC_BKUP6 (*(RwReg *)0x40002498UL) /**< \brief (RTC) Backup 6 */ -#define REG_RTC_BKUP7 (*(RwReg *)0x4000249CUL) /**< \brief (RTC) Backup 7 */ -#define REG_RTC_MODE0_CTRLA (*(RwReg16*)0x40002400UL) /**< \brief (RTC) MODE0 Control A */ -#define REG_RTC_MODE0_CTRLB (*(RwReg16*)0x40002402UL) /**< \brief (RTC) MODE0 Control B */ -#define REG_RTC_MODE0_EVCTRL (*(RwReg *)0x40002404UL) /**< \brief (RTC) MODE0 Event Control */ -#define REG_RTC_MODE0_INTENCLR (*(RwReg16*)0x40002408UL) /**< \brief (RTC) MODE0 Interrupt Enable Clear */ -#define REG_RTC_MODE0_INTENSET (*(RwReg16*)0x4000240AUL) /**< \brief (RTC) MODE0 Interrupt Enable Set */ -#define REG_RTC_MODE0_INTFLAG (*(RwReg16*)0x4000240CUL) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */ -#define REG_RTC_MODE0_SYNCBUSY (*(RoReg *)0x40002410UL) /**< \brief (RTC) MODE0 Synchronization Busy Status */ -#define REG_RTC_MODE0_COUNT (*(RwReg *)0x40002418UL) /**< \brief (RTC) MODE0 Counter Value */ -#define REG_RTC_MODE0_COMP0 (*(RwReg *)0x40002420UL) /**< \brief (RTC) MODE0 Compare 0 Value */ -#define REG_RTC_MODE0_TIMESTAMP (*(RoReg *)0x40002464UL) /**< \brief (RTC) MODE0 Timestamp */ -#define REG_RTC_MODE1_CTRLA (*(RwReg16*)0x40002400UL) /**< \brief (RTC) MODE1 Control A */ -#define REG_RTC_MODE1_CTRLB (*(RwReg16*)0x40002402UL) /**< \brief (RTC) MODE1 Control B */ -#define REG_RTC_MODE1_EVCTRL (*(RwReg *)0x40002404UL) /**< \brief (RTC) MODE1 Event Control */ -#define REG_RTC_MODE1_INTENCLR (*(RwReg16*)0x40002408UL) /**< \brief (RTC) MODE1 Interrupt Enable Clear */ -#define REG_RTC_MODE1_INTENSET (*(RwReg16*)0x4000240AUL) /**< \brief (RTC) MODE1 Interrupt Enable Set */ -#define REG_RTC_MODE1_INTFLAG (*(RwReg16*)0x4000240CUL) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */ -#define REG_RTC_MODE1_SYNCBUSY (*(RoReg *)0x40002410UL) /**< \brief (RTC) MODE1 Synchronization Busy Status */ -#define REG_RTC_MODE1_COUNT (*(RwReg16*)0x40002418UL) /**< \brief (RTC) MODE1 Counter Value */ -#define REG_RTC_MODE1_PER (*(RwReg16*)0x4000241CUL) /**< \brief (RTC) MODE1 Counter Period */ -#define REG_RTC_MODE1_COMP0 (*(RwReg16*)0x40002420UL) /**< \brief (RTC) MODE1 Compare 0 Value */ -#define REG_RTC_MODE1_COMP1 (*(RwReg16*)0x40002422UL) /**< \brief (RTC) MODE1 Compare 1 Value */ -#define REG_RTC_MODE1_TIMESTAMP (*(RoReg *)0x40002464UL) /**< \brief (RTC) MODE1 Timestamp */ -#define REG_RTC_MODE2_CTRLA (*(RwReg16*)0x40002400UL) /**< \brief (RTC) MODE2 Control A */ -#define REG_RTC_MODE2_CTRLB (*(RwReg16*)0x40002402UL) /**< \brief (RTC) MODE2 Control B */ -#define REG_RTC_MODE2_EVCTRL (*(RwReg *)0x40002404UL) /**< \brief (RTC) MODE2 Event Control */ -#define REG_RTC_MODE2_INTENCLR (*(RwReg16*)0x40002408UL) /**< \brief (RTC) MODE2 Interrupt Enable Clear */ -#define REG_RTC_MODE2_INTENSET (*(RwReg16*)0x4000240AUL) /**< \brief (RTC) MODE2 Interrupt Enable Set */ -#define REG_RTC_MODE2_INTFLAG (*(RwReg16*)0x4000240CUL) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */ -#define REG_RTC_MODE2_SYNCBUSY (*(RoReg *)0x40002410UL) /**< \brief (RTC) MODE2 Synchronization Busy Status */ -#define REG_RTC_MODE2_CLOCK (*(RwReg *)0x40002418UL) /**< \brief (RTC) MODE2 Clock Value */ -#define REG_RTC_MODE2_TIMESTAMP (*(RoReg *)0x40002464UL) /**< \brief (RTC) MODE2 Timestamp */ -#define REG_RTC_MODE2_ALARM_ALARM0 (*(RwReg *)0x40002420UL) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */ -#define REG_RTC_MODE2_ALARM_MASK0 (*(RwReg8 *)0x40002424UL) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for RTC peripheral ========== */ -#define RTC_ALARM_NUM 1 // Number of Alarms -#define RTC_BKUP_NUM 8 // Number of Backup Registers -#define RTC_COMP16_NUM 2 // Number of 16-bit Comparators -#define RTC_COMP32_NUM 1 // Number of 32-bit Comparators -#define RTC_DMAC_ID_TIMESTAMP 1 // DMA RTC timestamp trigger -#define RTC_GPR_NUM 2 // Number of General-Purpose Registers -#define RTC_PER_NUM 8 // Number of Periodic Intervals -#define RTC_TAMPER_NUM 5 // Number of Tamper Inputs - -#endif /* _SAML22_RTC_INSTANCE_ */ diff --git a/watch-library/include/instance/sercom0.h b/watch-library/include/instance/sercom0.h deleted file mode 100644 index 7160d497..00000000 --- a/watch-library/include/instance/sercom0.h +++ /dev/null @@ -1,142 +0,0 @@ -/** - * \file - * - * \brief Instance description for SERCOM0 - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_SERCOM0_INSTANCE_ -#define _SAML22_SERCOM0_INSTANCE_ - -/* ========== Register definition for SERCOM0 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_SERCOM0_I2CM_CTRLA (0x42000400) /**< \brief (SERCOM0) I2CM Control A */ -#define REG_SERCOM0_I2CM_CTRLB (0x42000404) /**< \brief (SERCOM0) I2CM Control B */ -#define REG_SERCOM0_I2CM_BAUD (0x4200040C) /**< \brief (SERCOM0) I2CM Baud Rate */ -#define REG_SERCOM0_I2CM_INTENCLR (0x42000414) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */ -#define REG_SERCOM0_I2CM_INTENSET (0x42000416) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */ -#define REG_SERCOM0_I2CM_INTFLAG (0x42000418) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM0_I2CM_STATUS (0x4200041A) /**< \brief (SERCOM0) I2CM Status */ -#define REG_SERCOM0_I2CM_SYNCBUSY (0x4200041C) /**< \brief (SERCOM0) I2CM Synchronization Busy */ -#define REG_SERCOM0_I2CM_ADDR (0x42000424) /**< \brief (SERCOM0) I2CM Address */ -#define REG_SERCOM0_I2CM_DATA (0x42000428) /**< \brief (SERCOM0) I2CM Data */ -#define REG_SERCOM0_I2CM_DBGCTRL (0x42000430) /**< \brief (SERCOM0) I2CM Debug Control */ -#define REG_SERCOM0_I2CS_CTRLA (0x42000400) /**< \brief (SERCOM0) I2CS Control A */ -#define REG_SERCOM0_I2CS_CTRLB (0x42000404) /**< \brief (SERCOM0) I2CS Control B */ -#define REG_SERCOM0_I2CS_INTENCLR (0x42000414) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */ -#define REG_SERCOM0_I2CS_INTENSET (0x42000416) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */ -#define REG_SERCOM0_I2CS_INTFLAG (0x42000418) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM0_I2CS_STATUS (0x4200041A) /**< \brief (SERCOM0) I2CS Status */ -#define REG_SERCOM0_I2CS_SYNCBUSY (0x4200041C) /**< \brief (SERCOM0) I2CS Synchronization Busy */ -#define REG_SERCOM0_I2CS_ADDR (0x42000424) /**< \brief (SERCOM0) I2CS Address */ -#define REG_SERCOM0_I2CS_DATA (0x42000428) /**< \brief (SERCOM0) I2CS Data */ -#define REG_SERCOM0_SPI_CTRLA (0x42000400) /**< \brief (SERCOM0) SPI Control A */ -#define REG_SERCOM0_SPI_CTRLB (0x42000404) /**< \brief (SERCOM0) SPI Control B */ -#define REG_SERCOM0_SPI_BAUD (0x4200040C) /**< \brief (SERCOM0) SPI Baud Rate */ -#define REG_SERCOM0_SPI_INTENCLR (0x42000414) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */ -#define REG_SERCOM0_SPI_INTENSET (0x42000416) /**< \brief (SERCOM0) SPI Interrupt Enable Set */ -#define REG_SERCOM0_SPI_INTFLAG (0x42000418) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM0_SPI_STATUS (0x4200041A) /**< \brief (SERCOM0) SPI Status */ -#define REG_SERCOM0_SPI_SYNCBUSY (0x4200041C) /**< \brief (SERCOM0) SPI Synchronization Busy */ -#define REG_SERCOM0_SPI_ADDR (0x42000424) /**< \brief (SERCOM0) SPI Address */ -#define REG_SERCOM0_SPI_DATA (0x42000428) /**< \brief (SERCOM0) SPI Data */ -#define REG_SERCOM0_SPI_DBGCTRL (0x42000430) /**< \brief (SERCOM0) SPI Debug Control */ -#define REG_SERCOM0_USART_CTRLA (0x42000400) /**< \brief (SERCOM0) USART Control A */ -#define REG_SERCOM0_USART_CTRLB (0x42000404) /**< \brief (SERCOM0) USART Control B */ -#define REG_SERCOM0_USART_CTRLC (0x42000408) /**< \brief (SERCOM0) USART Control C */ -#define REG_SERCOM0_USART_BAUD (0x4200040C) /**< \brief (SERCOM0) USART Baud Rate */ -#define REG_SERCOM0_USART_RXPL (0x4200040E) /**< \brief (SERCOM0) USART Receive Pulse Length */ -#define REG_SERCOM0_USART_INTENCLR (0x42000414) /**< \brief (SERCOM0) USART Interrupt Enable Clear */ -#define REG_SERCOM0_USART_INTENSET (0x42000416) /**< \brief (SERCOM0) USART Interrupt Enable Set */ -#define REG_SERCOM0_USART_INTFLAG (0x42000418) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM0_USART_STATUS (0x4200041A) /**< \brief (SERCOM0) USART Status */ -#define REG_SERCOM0_USART_SYNCBUSY (0x4200041C) /**< \brief (SERCOM0) USART Synchronization Busy */ -#define REG_SERCOM0_USART_RXERRCNT (0x42000420) /**< \brief (SERCOM0) USART Receive Error Count */ -#define REG_SERCOM0_USART_DATA (0x42000428) /**< \brief (SERCOM0) USART Data */ -#define REG_SERCOM0_USART_DBGCTRL (0x42000430) /**< \brief (SERCOM0) USART Debug Control */ -#else -#define REG_SERCOM0_I2CM_CTRLA (*(RwReg *)0x42000400UL) /**< \brief (SERCOM0) I2CM Control A */ -#define REG_SERCOM0_I2CM_CTRLB (*(RwReg *)0x42000404UL) /**< \brief (SERCOM0) I2CM Control B */ -#define REG_SERCOM0_I2CM_BAUD (*(RwReg *)0x4200040CUL) /**< \brief (SERCOM0) I2CM Baud Rate */ -#define REG_SERCOM0_I2CM_INTENCLR (*(RwReg8 *)0x42000414UL) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */ -#define REG_SERCOM0_I2CM_INTENSET (*(RwReg8 *)0x42000416UL) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */ -#define REG_SERCOM0_I2CM_INTFLAG (*(RwReg8 *)0x42000418UL) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM0_I2CM_STATUS (*(RwReg16*)0x4200041AUL) /**< \brief (SERCOM0) I2CM Status */ -#define REG_SERCOM0_I2CM_SYNCBUSY (*(RoReg *)0x4200041CUL) /**< \brief (SERCOM0) I2CM Synchronization Busy */ -#define REG_SERCOM0_I2CM_ADDR (*(RwReg *)0x42000424UL) /**< \brief (SERCOM0) I2CM Address */ -#define REG_SERCOM0_I2CM_DATA (*(RwReg8 *)0x42000428UL) /**< \brief (SERCOM0) I2CM Data */ -#define REG_SERCOM0_I2CM_DBGCTRL (*(RwReg8 *)0x42000430UL) /**< \brief (SERCOM0) I2CM Debug Control */ -#define REG_SERCOM0_I2CS_CTRLA (*(RwReg *)0x42000400UL) /**< \brief (SERCOM0) I2CS Control A */ -#define REG_SERCOM0_I2CS_CTRLB (*(RwReg *)0x42000404UL) /**< \brief (SERCOM0) I2CS Control B */ -#define REG_SERCOM0_I2CS_INTENCLR (*(RwReg8 *)0x42000414UL) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */ -#define REG_SERCOM0_I2CS_INTENSET (*(RwReg8 *)0x42000416UL) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */ -#define REG_SERCOM0_I2CS_INTFLAG (*(RwReg8 *)0x42000418UL) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM0_I2CS_STATUS (*(RwReg16*)0x4200041AUL) /**< \brief (SERCOM0) I2CS Status */ -#define REG_SERCOM0_I2CS_SYNCBUSY (*(RoReg *)0x4200041CUL) /**< \brief (SERCOM0) I2CS Synchronization Busy */ -#define REG_SERCOM0_I2CS_ADDR (*(RwReg *)0x42000424UL) /**< \brief (SERCOM0) I2CS Address */ -#define REG_SERCOM0_I2CS_DATA (*(RwReg8 *)0x42000428UL) /**< \brief (SERCOM0) I2CS Data */ -#define REG_SERCOM0_SPI_CTRLA (*(RwReg *)0x42000400UL) /**< \brief (SERCOM0) SPI Control A */ -#define REG_SERCOM0_SPI_CTRLB (*(RwReg *)0x42000404UL) /**< \brief (SERCOM0) SPI Control B */ -#define REG_SERCOM0_SPI_BAUD (*(RwReg8 *)0x4200040CUL) /**< \brief (SERCOM0) SPI Baud Rate */ -#define REG_SERCOM0_SPI_INTENCLR (*(RwReg8 *)0x42000414UL) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */ -#define REG_SERCOM0_SPI_INTENSET (*(RwReg8 *)0x42000416UL) /**< \brief (SERCOM0) SPI Interrupt Enable Set */ -#define REG_SERCOM0_SPI_INTFLAG (*(RwReg8 *)0x42000418UL) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM0_SPI_STATUS (*(RwReg16*)0x4200041AUL) /**< \brief (SERCOM0) SPI Status */ -#define REG_SERCOM0_SPI_SYNCBUSY (*(RoReg *)0x4200041CUL) /**< \brief (SERCOM0) SPI Synchronization Busy */ -#define REG_SERCOM0_SPI_ADDR (*(RwReg *)0x42000424UL) /**< \brief (SERCOM0) SPI Address */ -#define REG_SERCOM0_SPI_DATA (*(RwReg *)0x42000428UL) /**< \brief (SERCOM0) SPI Data */ -#define REG_SERCOM0_SPI_DBGCTRL (*(RwReg8 *)0x42000430UL) /**< \brief (SERCOM0) SPI Debug Control */ -#define REG_SERCOM0_USART_CTRLA (*(RwReg *)0x42000400UL) /**< \brief (SERCOM0) USART Control A */ -#define REG_SERCOM0_USART_CTRLB (*(RwReg *)0x42000404UL) /**< \brief (SERCOM0) USART Control B */ -#define REG_SERCOM0_USART_CTRLC (*(RwReg *)0x42000408UL) /**< \brief (SERCOM0) USART Control C */ -#define REG_SERCOM0_USART_BAUD (*(RwReg16*)0x4200040CUL) /**< \brief (SERCOM0) USART Baud Rate */ -#define REG_SERCOM0_USART_RXPL (*(RwReg8 *)0x4200040EUL) /**< \brief (SERCOM0) USART Receive Pulse Length */ -#define REG_SERCOM0_USART_INTENCLR (*(RwReg8 *)0x42000414UL) /**< \brief (SERCOM0) USART Interrupt Enable Clear */ -#define REG_SERCOM0_USART_INTENSET (*(RwReg8 *)0x42000416UL) /**< \brief (SERCOM0) USART Interrupt Enable Set */ -#define REG_SERCOM0_USART_INTFLAG (*(RwReg8 *)0x42000418UL) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM0_USART_STATUS (*(RwReg16*)0x4200041AUL) /**< \brief (SERCOM0) USART Status */ -#define REG_SERCOM0_USART_SYNCBUSY (*(RoReg *)0x4200041CUL) /**< \brief (SERCOM0) USART Synchronization Busy */ -#define REG_SERCOM0_USART_RXERRCNT (*(RoReg8 *)0x42000420UL) /**< \brief (SERCOM0) USART Receive Error Count */ -#define REG_SERCOM0_USART_DATA (*(RwReg16*)0x42000428UL) /**< \brief (SERCOM0) USART Data */ -#define REG_SERCOM0_USART_DBGCTRL (*(RwReg8 *)0x42000430UL) /**< \brief (SERCOM0) USART Debug Control */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for SERCOM0 peripheral ========== */ -#define SERCOM0_DMAC_ID_RX 2 // Index of DMA RX trigger -#define SERCOM0_DMAC_ID_TX 3 // Index of DMA TX trigger -#define SERCOM0_GCLK_ID_CORE 16 -#define SERCOM0_GCLK_ID_SLOW 15 -#define SERCOM0_INT_MSB 6 -#define SERCOM0_PMSB 3 -#define SERCOM0_SPI 1 // SPI mode implemented? -#define SERCOM0_TWIM 0 // TWI Master mode implemented? -#define SERCOM0_TWIS 0 // TWI Slave mode implemented? -#define SERCOM0_TWI_HSMODE 0 // TWI HighSpeed mode implemented? -#define SERCOM0_USART 1 // USART mode implemented? -#define SERCOM0_USART_ISO7816 1 // USART ISO7816 mode implemented? -#define SERCOM0_USART_LIN_MASTER 0 // USART LIN Master mode implemented? -#define SERCOM0_USART_RS485 1 // USART RS485 mode implemented? - -#endif /* _SAML22_SERCOM0_INSTANCE_ */ diff --git a/watch-library/include/instance/sercom1.h b/watch-library/include/instance/sercom1.h deleted file mode 100644 index 1c0176ef..00000000 --- a/watch-library/include/instance/sercom1.h +++ /dev/null @@ -1,142 +0,0 @@ -/** - * \file - * - * \brief Instance description for SERCOM1 - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_SERCOM1_INSTANCE_ -#define _SAML22_SERCOM1_INSTANCE_ - -/* ========== Register definition for SERCOM1 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_SERCOM1_I2CM_CTRLA (0x42000800) /**< \brief (SERCOM1) I2CM Control A */ -#define REG_SERCOM1_I2CM_CTRLB (0x42000804) /**< \brief (SERCOM1) I2CM Control B */ -#define REG_SERCOM1_I2CM_BAUD (0x4200080C) /**< \brief (SERCOM1) I2CM Baud Rate */ -#define REG_SERCOM1_I2CM_INTENCLR (0x42000814) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */ -#define REG_SERCOM1_I2CM_INTENSET (0x42000816) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */ -#define REG_SERCOM1_I2CM_INTFLAG (0x42000818) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM1_I2CM_STATUS (0x4200081A) /**< \brief (SERCOM1) I2CM Status */ -#define REG_SERCOM1_I2CM_SYNCBUSY (0x4200081C) /**< \brief (SERCOM1) I2CM Synchronization Busy */ -#define REG_SERCOM1_I2CM_ADDR (0x42000824) /**< \brief (SERCOM1) I2CM Address */ -#define REG_SERCOM1_I2CM_DATA (0x42000828) /**< \brief (SERCOM1) I2CM Data */ -#define REG_SERCOM1_I2CM_DBGCTRL (0x42000830) /**< \brief (SERCOM1) I2CM Debug Control */ -#define REG_SERCOM1_I2CS_CTRLA (0x42000800) /**< \brief (SERCOM1) I2CS Control A */ -#define REG_SERCOM1_I2CS_CTRLB (0x42000804) /**< \brief (SERCOM1) I2CS Control B */ -#define REG_SERCOM1_I2CS_INTENCLR (0x42000814) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */ -#define REG_SERCOM1_I2CS_INTENSET (0x42000816) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */ -#define REG_SERCOM1_I2CS_INTFLAG (0x42000818) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM1_I2CS_STATUS (0x4200081A) /**< \brief (SERCOM1) I2CS Status */ -#define REG_SERCOM1_I2CS_SYNCBUSY (0x4200081C) /**< \brief (SERCOM1) I2CS Synchronization Busy */ -#define REG_SERCOM1_I2CS_ADDR (0x42000824) /**< \brief (SERCOM1) I2CS Address */ -#define REG_SERCOM1_I2CS_DATA (0x42000828) /**< \brief (SERCOM1) I2CS Data */ -#define REG_SERCOM1_SPI_CTRLA (0x42000800) /**< \brief (SERCOM1) SPI Control A */ -#define REG_SERCOM1_SPI_CTRLB (0x42000804) /**< \brief (SERCOM1) SPI Control B */ -#define REG_SERCOM1_SPI_BAUD (0x4200080C) /**< \brief (SERCOM1) SPI Baud Rate */ -#define REG_SERCOM1_SPI_INTENCLR (0x42000814) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */ -#define REG_SERCOM1_SPI_INTENSET (0x42000816) /**< \brief (SERCOM1) SPI Interrupt Enable Set */ -#define REG_SERCOM1_SPI_INTFLAG (0x42000818) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM1_SPI_STATUS (0x4200081A) /**< \brief (SERCOM1) SPI Status */ -#define REG_SERCOM1_SPI_SYNCBUSY (0x4200081C) /**< \brief (SERCOM1) SPI Synchronization Busy */ -#define REG_SERCOM1_SPI_ADDR (0x42000824) /**< \brief (SERCOM1) SPI Address */ -#define REG_SERCOM1_SPI_DATA (0x42000828) /**< \brief (SERCOM1) SPI Data */ -#define REG_SERCOM1_SPI_DBGCTRL (0x42000830) /**< \brief (SERCOM1) SPI Debug Control */ -#define REG_SERCOM1_USART_CTRLA (0x42000800) /**< \brief (SERCOM1) USART Control A */ -#define REG_SERCOM1_USART_CTRLB (0x42000804) /**< \brief (SERCOM1) USART Control B */ -#define REG_SERCOM1_USART_CTRLC (0x42000808) /**< \brief (SERCOM1) USART Control C */ -#define REG_SERCOM1_USART_BAUD (0x4200080C) /**< \brief (SERCOM1) USART Baud Rate */ -#define REG_SERCOM1_USART_RXPL (0x4200080E) /**< \brief (SERCOM1) USART Receive Pulse Length */ -#define REG_SERCOM1_USART_INTENCLR (0x42000814) /**< \brief (SERCOM1) USART Interrupt Enable Clear */ -#define REG_SERCOM1_USART_INTENSET (0x42000816) /**< \brief (SERCOM1) USART Interrupt Enable Set */ -#define REG_SERCOM1_USART_INTFLAG (0x42000818) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM1_USART_STATUS (0x4200081A) /**< \brief (SERCOM1) USART Status */ -#define REG_SERCOM1_USART_SYNCBUSY (0x4200081C) /**< \brief (SERCOM1) USART Synchronization Busy */ -#define REG_SERCOM1_USART_RXERRCNT (0x42000820) /**< \brief (SERCOM1) USART Receive Error Count */ -#define REG_SERCOM1_USART_DATA (0x42000828) /**< \brief (SERCOM1) USART Data */ -#define REG_SERCOM1_USART_DBGCTRL (0x42000830) /**< \brief (SERCOM1) USART Debug Control */ -#else -#define REG_SERCOM1_I2CM_CTRLA (*(RwReg *)0x42000800UL) /**< \brief (SERCOM1) I2CM Control A */ -#define REG_SERCOM1_I2CM_CTRLB (*(RwReg *)0x42000804UL) /**< \brief (SERCOM1) I2CM Control B */ -#define REG_SERCOM1_I2CM_BAUD (*(RwReg *)0x4200080CUL) /**< \brief (SERCOM1) I2CM Baud Rate */ -#define REG_SERCOM1_I2CM_INTENCLR (*(RwReg8 *)0x42000814UL) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */ -#define REG_SERCOM1_I2CM_INTENSET (*(RwReg8 *)0x42000816UL) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */ -#define REG_SERCOM1_I2CM_INTFLAG (*(RwReg8 *)0x42000818UL) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM1_I2CM_STATUS (*(RwReg16*)0x4200081AUL) /**< \brief (SERCOM1) I2CM Status */ -#define REG_SERCOM1_I2CM_SYNCBUSY (*(RoReg *)0x4200081CUL) /**< \brief (SERCOM1) I2CM Synchronization Busy */ -#define REG_SERCOM1_I2CM_ADDR (*(RwReg *)0x42000824UL) /**< \brief (SERCOM1) I2CM Address */ -#define REG_SERCOM1_I2CM_DATA (*(RwReg8 *)0x42000828UL) /**< \brief (SERCOM1) I2CM Data */ -#define REG_SERCOM1_I2CM_DBGCTRL (*(RwReg8 *)0x42000830UL) /**< \brief (SERCOM1) I2CM Debug Control */ -#define REG_SERCOM1_I2CS_CTRLA (*(RwReg *)0x42000800UL) /**< \brief (SERCOM1) I2CS Control A */ -#define REG_SERCOM1_I2CS_CTRLB (*(RwReg *)0x42000804UL) /**< \brief (SERCOM1) I2CS Control B */ -#define REG_SERCOM1_I2CS_INTENCLR (*(RwReg8 *)0x42000814UL) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */ -#define REG_SERCOM1_I2CS_INTENSET (*(RwReg8 *)0x42000816UL) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */ -#define REG_SERCOM1_I2CS_INTFLAG (*(RwReg8 *)0x42000818UL) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM1_I2CS_STATUS (*(RwReg16*)0x4200081AUL) /**< \brief (SERCOM1) I2CS Status */ -#define REG_SERCOM1_I2CS_SYNCBUSY (*(RoReg *)0x4200081CUL) /**< \brief (SERCOM1) I2CS Synchronization Busy */ -#define REG_SERCOM1_I2CS_ADDR (*(RwReg *)0x42000824UL) /**< \brief (SERCOM1) I2CS Address */ -#define REG_SERCOM1_I2CS_DATA (*(RwReg8 *)0x42000828UL) /**< \brief (SERCOM1) I2CS Data */ -#define REG_SERCOM1_SPI_CTRLA (*(RwReg *)0x42000800UL) /**< \brief (SERCOM1) SPI Control A */ -#define REG_SERCOM1_SPI_CTRLB (*(RwReg *)0x42000804UL) /**< \brief (SERCOM1) SPI Control B */ -#define REG_SERCOM1_SPI_BAUD (*(RwReg8 *)0x4200080CUL) /**< \brief (SERCOM1) SPI Baud Rate */ -#define REG_SERCOM1_SPI_INTENCLR (*(RwReg8 *)0x42000814UL) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */ -#define REG_SERCOM1_SPI_INTENSET (*(RwReg8 *)0x42000816UL) /**< \brief (SERCOM1) SPI Interrupt Enable Set */ -#define REG_SERCOM1_SPI_INTFLAG (*(RwReg8 *)0x42000818UL) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM1_SPI_STATUS (*(RwReg16*)0x4200081AUL) /**< \brief (SERCOM1) SPI Status */ -#define REG_SERCOM1_SPI_SYNCBUSY (*(RoReg *)0x4200081CUL) /**< \brief (SERCOM1) SPI Synchronization Busy */ -#define REG_SERCOM1_SPI_ADDR (*(RwReg *)0x42000824UL) /**< \brief (SERCOM1) SPI Address */ -#define REG_SERCOM1_SPI_DATA (*(RwReg *)0x42000828UL) /**< \brief (SERCOM1) SPI Data */ -#define REG_SERCOM1_SPI_DBGCTRL (*(RwReg8 *)0x42000830UL) /**< \brief (SERCOM1) SPI Debug Control */ -#define REG_SERCOM1_USART_CTRLA (*(RwReg *)0x42000800UL) /**< \brief (SERCOM1) USART Control A */ -#define REG_SERCOM1_USART_CTRLB (*(RwReg *)0x42000804UL) /**< \brief (SERCOM1) USART Control B */ -#define REG_SERCOM1_USART_CTRLC (*(RwReg *)0x42000808UL) /**< \brief (SERCOM1) USART Control C */ -#define REG_SERCOM1_USART_BAUD (*(RwReg16*)0x4200080CUL) /**< \brief (SERCOM1) USART Baud Rate */ -#define REG_SERCOM1_USART_RXPL (*(RwReg8 *)0x4200080EUL) /**< \brief (SERCOM1) USART Receive Pulse Length */ -#define REG_SERCOM1_USART_INTENCLR (*(RwReg8 *)0x42000814UL) /**< \brief (SERCOM1) USART Interrupt Enable Clear */ -#define REG_SERCOM1_USART_INTENSET (*(RwReg8 *)0x42000816UL) /**< \brief (SERCOM1) USART Interrupt Enable Set */ -#define REG_SERCOM1_USART_INTFLAG (*(RwReg8 *)0x42000818UL) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM1_USART_STATUS (*(RwReg16*)0x4200081AUL) /**< \brief (SERCOM1) USART Status */ -#define REG_SERCOM1_USART_SYNCBUSY (*(RoReg *)0x4200081CUL) /**< \brief (SERCOM1) USART Synchronization Busy */ -#define REG_SERCOM1_USART_RXERRCNT (*(RoReg8 *)0x42000820UL) /**< \brief (SERCOM1) USART Receive Error Count */ -#define REG_SERCOM1_USART_DATA (*(RwReg16*)0x42000828UL) /**< \brief (SERCOM1) USART Data */ -#define REG_SERCOM1_USART_DBGCTRL (*(RwReg8 *)0x42000830UL) /**< \brief (SERCOM1) USART Debug Control */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for SERCOM1 peripheral ========== */ -#define SERCOM1_DMAC_ID_RX 4 // Index of DMA RX trigger -#define SERCOM1_DMAC_ID_TX 5 // Index of DMA TX trigger -#define SERCOM1_GCLK_ID_CORE 17 -#define SERCOM1_GCLK_ID_SLOW 15 -#define SERCOM1_INT_MSB 6 -#define SERCOM1_PMSB 3 -#define SERCOM1_SPI 1 // SPI mode implemented? -#define SERCOM1_TWIM 1 // TWI Master mode implemented? -#define SERCOM1_TWIS 1 // TWI Slave mode implemented? -#define SERCOM1_TWI_HSMODE 1 // TWI HighSpeed mode implemented? -#define SERCOM1_USART 1 // USART mode implemented? -#define SERCOM1_USART_ISO7816 1 // USART ISO7816 mode implemented? -#define SERCOM1_USART_LIN_MASTER 0 // USART LIN Master mode implemented? -#define SERCOM1_USART_RS485 1 // USART RS485 mode implemented? - -#endif /* _SAML22_SERCOM1_INSTANCE_ */ diff --git a/watch-library/include/instance/sercom2.h b/watch-library/include/instance/sercom2.h deleted file mode 100644 index 6c8458cc..00000000 --- a/watch-library/include/instance/sercom2.h +++ /dev/null @@ -1,142 +0,0 @@ -/** - * \file - * - * \brief Instance description for SERCOM2 - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_SERCOM2_INSTANCE_ -#define _SAML22_SERCOM2_INSTANCE_ - -/* ========== Register definition for SERCOM2 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_SERCOM2_I2CM_CTRLA (0x42000C00) /**< \brief (SERCOM2) I2CM Control A */ -#define REG_SERCOM2_I2CM_CTRLB (0x42000C04) /**< \brief (SERCOM2) I2CM Control B */ -#define REG_SERCOM2_I2CM_BAUD (0x42000C0C) /**< \brief (SERCOM2) I2CM Baud Rate */ -#define REG_SERCOM2_I2CM_INTENCLR (0x42000C14) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */ -#define REG_SERCOM2_I2CM_INTENSET (0x42000C16) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */ -#define REG_SERCOM2_I2CM_INTFLAG (0x42000C18) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM2_I2CM_STATUS (0x42000C1A) /**< \brief (SERCOM2) I2CM Status */ -#define REG_SERCOM2_I2CM_SYNCBUSY (0x42000C1C) /**< \brief (SERCOM2) I2CM Synchronization Busy */ -#define REG_SERCOM2_I2CM_ADDR (0x42000C24) /**< \brief (SERCOM2) I2CM Address */ -#define REG_SERCOM2_I2CM_DATA (0x42000C28) /**< \brief (SERCOM2) I2CM Data */ -#define REG_SERCOM2_I2CM_DBGCTRL (0x42000C30) /**< \brief (SERCOM2) I2CM Debug Control */ -#define REG_SERCOM2_I2CS_CTRLA (0x42000C00) /**< \brief (SERCOM2) I2CS Control A */ -#define REG_SERCOM2_I2CS_CTRLB (0x42000C04) /**< \brief (SERCOM2) I2CS Control B */ -#define REG_SERCOM2_I2CS_INTENCLR (0x42000C14) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */ -#define REG_SERCOM2_I2CS_INTENSET (0x42000C16) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */ -#define REG_SERCOM2_I2CS_INTFLAG (0x42000C18) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM2_I2CS_STATUS (0x42000C1A) /**< \brief (SERCOM2) I2CS Status */ -#define REG_SERCOM2_I2CS_SYNCBUSY (0x42000C1C) /**< \brief (SERCOM2) I2CS Synchronization Busy */ -#define REG_SERCOM2_I2CS_ADDR (0x42000C24) /**< \brief (SERCOM2) I2CS Address */ -#define REG_SERCOM2_I2CS_DATA (0x42000C28) /**< \brief (SERCOM2) I2CS Data */ -#define REG_SERCOM2_SPI_CTRLA (0x42000C00) /**< \brief (SERCOM2) SPI Control A */ -#define REG_SERCOM2_SPI_CTRLB (0x42000C04) /**< \brief (SERCOM2) SPI Control B */ -#define REG_SERCOM2_SPI_BAUD (0x42000C0C) /**< \brief (SERCOM2) SPI Baud Rate */ -#define REG_SERCOM2_SPI_INTENCLR (0x42000C14) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */ -#define REG_SERCOM2_SPI_INTENSET (0x42000C16) /**< \brief (SERCOM2) SPI Interrupt Enable Set */ -#define REG_SERCOM2_SPI_INTFLAG (0x42000C18) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM2_SPI_STATUS (0x42000C1A) /**< \brief (SERCOM2) SPI Status */ -#define REG_SERCOM2_SPI_SYNCBUSY (0x42000C1C) /**< \brief (SERCOM2) SPI Synchronization Busy */ -#define REG_SERCOM2_SPI_ADDR (0x42000C24) /**< \brief (SERCOM2) SPI Address */ -#define REG_SERCOM2_SPI_DATA (0x42000C28) /**< \brief (SERCOM2) SPI Data */ -#define REG_SERCOM2_SPI_DBGCTRL (0x42000C30) /**< \brief (SERCOM2) SPI Debug Control */ -#define REG_SERCOM2_USART_CTRLA (0x42000C00) /**< \brief (SERCOM2) USART Control A */ -#define REG_SERCOM2_USART_CTRLB (0x42000C04) /**< \brief (SERCOM2) USART Control B */ -#define REG_SERCOM2_USART_CTRLC (0x42000C08) /**< \brief (SERCOM2) USART Control C */ -#define REG_SERCOM2_USART_BAUD (0x42000C0C) /**< \brief (SERCOM2) USART Baud Rate */ -#define REG_SERCOM2_USART_RXPL (0x42000C0E) /**< \brief (SERCOM2) USART Receive Pulse Length */ -#define REG_SERCOM2_USART_INTENCLR (0x42000C14) /**< \brief (SERCOM2) USART Interrupt Enable Clear */ -#define REG_SERCOM2_USART_INTENSET (0x42000C16) /**< \brief (SERCOM2) USART Interrupt Enable Set */ -#define REG_SERCOM2_USART_INTFLAG (0x42000C18) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM2_USART_STATUS (0x42000C1A) /**< \brief (SERCOM2) USART Status */ -#define REG_SERCOM2_USART_SYNCBUSY (0x42000C1C) /**< \brief (SERCOM2) USART Synchronization Busy */ -#define REG_SERCOM2_USART_RXERRCNT (0x42000C20) /**< \brief (SERCOM2) USART Receive Error Count */ -#define REG_SERCOM2_USART_DATA (0x42000C28) /**< \brief (SERCOM2) USART Data */ -#define REG_SERCOM2_USART_DBGCTRL (0x42000C30) /**< \brief (SERCOM2) USART Debug Control */ -#else -#define REG_SERCOM2_I2CM_CTRLA (*(RwReg *)0x42000C00UL) /**< \brief (SERCOM2) I2CM Control A */ -#define REG_SERCOM2_I2CM_CTRLB (*(RwReg *)0x42000C04UL) /**< \brief (SERCOM2) I2CM Control B */ -#define REG_SERCOM2_I2CM_BAUD (*(RwReg *)0x42000C0CUL) /**< \brief (SERCOM2) I2CM Baud Rate */ -#define REG_SERCOM2_I2CM_INTENCLR (*(RwReg8 *)0x42000C14UL) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */ -#define REG_SERCOM2_I2CM_INTENSET (*(RwReg8 *)0x42000C16UL) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */ -#define REG_SERCOM2_I2CM_INTFLAG (*(RwReg8 *)0x42000C18UL) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM2_I2CM_STATUS (*(RwReg16*)0x42000C1AUL) /**< \brief (SERCOM2) I2CM Status */ -#define REG_SERCOM2_I2CM_SYNCBUSY (*(RoReg *)0x42000C1CUL) /**< \brief (SERCOM2) I2CM Synchronization Busy */ -#define REG_SERCOM2_I2CM_ADDR (*(RwReg *)0x42000C24UL) /**< \brief (SERCOM2) I2CM Address */ -#define REG_SERCOM2_I2CM_DATA (*(RwReg8 *)0x42000C28UL) /**< \brief (SERCOM2) I2CM Data */ -#define REG_SERCOM2_I2CM_DBGCTRL (*(RwReg8 *)0x42000C30UL) /**< \brief (SERCOM2) I2CM Debug Control */ -#define REG_SERCOM2_I2CS_CTRLA (*(RwReg *)0x42000C00UL) /**< \brief (SERCOM2) I2CS Control A */ -#define REG_SERCOM2_I2CS_CTRLB (*(RwReg *)0x42000C04UL) /**< \brief (SERCOM2) I2CS Control B */ -#define REG_SERCOM2_I2CS_INTENCLR (*(RwReg8 *)0x42000C14UL) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */ -#define REG_SERCOM2_I2CS_INTENSET (*(RwReg8 *)0x42000C16UL) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */ -#define REG_SERCOM2_I2CS_INTFLAG (*(RwReg8 *)0x42000C18UL) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM2_I2CS_STATUS (*(RwReg16*)0x42000C1AUL) /**< \brief (SERCOM2) I2CS Status */ -#define REG_SERCOM2_I2CS_SYNCBUSY (*(RoReg *)0x42000C1CUL) /**< \brief (SERCOM2) I2CS Synchronization Busy */ -#define REG_SERCOM2_I2CS_ADDR (*(RwReg *)0x42000C24UL) /**< \brief (SERCOM2) I2CS Address */ -#define REG_SERCOM2_I2CS_DATA (*(RwReg8 *)0x42000C28UL) /**< \brief (SERCOM2) I2CS Data */ -#define REG_SERCOM2_SPI_CTRLA (*(RwReg *)0x42000C00UL) /**< \brief (SERCOM2) SPI Control A */ -#define REG_SERCOM2_SPI_CTRLB (*(RwReg *)0x42000C04UL) /**< \brief (SERCOM2) SPI Control B */ -#define REG_SERCOM2_SPI_BAUD (*(RwReg8 *)0x42000C0CUL) /**< \brief (SERCOM2) SPI Baud Rate */ -#define REG_SERCOM2_SPI_INTENCLR (*(RwReg8 *)0x42000C14UL) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */ -#define REG_SERCOM2_SPI_INTENSET (*(RwReg8 *)0x42000C16UL) /**< \brief (SERCOM2) SPI Interrupt Enable Set */ -#define REG_SERCOM2_SPI_INTFLAG (*(RwReg8 *)0x42000C18UL) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM2_SPI_STATUS (*(RwReg16*)0x42000C1AUL) /**< \brief (SERCOM2) SPI Status */ -#define REG_SERCOM2_SPI_SYNCBUSY (*(RoReg *)0x42000C1CUL) /**< \brief (SERCOM2) SPI Synchronization Busy */ -#define REG_SERCOM2_SPI_ADDR (*(RwReg *)0x42000C24UL) /**< \brief (SERCOM2) SPI Address */ -#define REG_SERCOM2_SPI_DATA (*(RwReg *)0x42000C28UL) /**< \brief (SERCOM2) SPI Data */ -#define REG_SERCOM2_SPI_DBGCTRL (*(RwReg8 *)0x42000C30UL) /**< \brief (SERCOM2) SPI Debug Control */ -#define REG_SERCOM2_USART_CTRLA (*(RwReg *)0x42000C00UL) /**< \brief (SERCOM2) USART Control A */ -#define REG_SERCOM2_USART_CTRLB (*(RwReg *)0x42000C04UL) /**< \brief (SERCOM2) USART Control B */ -#define REG_SERCOM2_USART_CTRLC (*(RwReg *)0x42000C08UL) /**< \brief (SERCOM2) USART Control C */ -#define REG_SERCOM2_USART_BAUD (*(RwReg16*)0x42000C0CUL) /**< \brief (SERCOM2) USART Baud Rate */ -#define REG_SERCOM2_USART_RXPL (*(RwReg8 *)0x42000C0EUL) /**< \brief (SERCOM2) USART Receive Pulse Length */ -#define REG_SERCOM2_USART_INTENCLR (*(RwReg8 *)0x42000C14UL) /**< \brief (SERCOM2) USART Interrupt Enable Clear */ -#define REG_SERCOM2_USART_INTENSET (*(RwReg8 *)0x42000C16UL) /**< \brief (SERCOM2) USART Interrupt Enable Set */ -#define REG_SERCOM2_USART_INTFLAG (*(RwReg8 *)0x42000C18UL) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM2_USART_STATUS (*(RwReg16*)0x42000C1AUL) /**< \brief (SERCOM2) USART Status */ -#define REG_SERCOM2_USART_SYNCBUSY (*(RoReg *)0x42000C1CUL) /**< \brief (SERCOM2) USART Synchronization Busy */ -#define REG_SERCOM2_USART_RXERRCNT (*(RoReg8 *)0x42000C20UL) /**< \brief (SERCOM2) USART Receive Error Count */ -#define REG_SERCOM2_USART_DATA (*(RwReg16*)0x42000C28UL) /**< \brief (SERCOM2) USART Data */ -#define REG_SERCOM2_USART_DBGCTRL (*(RwReg8 *)0x42000C30UL) /**< \brief (SERCOM2) USART Debug Control */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for SERCOM2 peripheral ========== */ -#define SERCOM2_DMAC_ID_RX 6 // Index of DMA RX trigger -#define SERCOM2_DMAC_ID_TX 7 // Index of DMA TX trigger -#define SERCOM2_GCLK_ID_CORE 18 -#define SERCOM2_GCLK_ID_SLOW 15 -#define SERCOM2_INT_MSB 6 -#define SERCOM2_PMSB 3 -#define SERCOM2_SPI 1 // SPI mode implemented? -#define SERCOM2_TWIM 1 // TWI Master mode implemented? -#define SERCOM2_TWIS 1 // TWI Slave mode implemented? -#define SERCOM2_TWI_HSMODE 0 // TWI HighSpeed mode implemented? -#define SERCOM2_USART 1 // USART mode implemented? -#define SERCOM2_USART_ISO7816 1 // USART ISO7816 mode implemented? -#define SERCOM2_USART_LIN_MASTER 0 // USART LIN Master mode implemented? -#define SERCOM2_USART_RS485 1 // USART RS485 mode implemented? - -#endif /* _SAML22_SERCOM2_INSTANCE_ */ diff --git a/watch-library/include/instance/sercom3.h b/watch-library/include/instance/sercom3.h deleted file mode 100644 index f7256e22..00000000 --- a/watch-library/include/instance/sercom3.h +++ /dev/null @@ -1,142 +0,0 @@ -/** - * \file - * - * \brief Instance description for SERCOM3 - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_SERCOM3_INSTANCE_ -#define _SAML22_SERCOM3_INSTANCE_ - -/* ========== Register definition for SERCOM3 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_SERCOM3_I2CM_CTRLA (0x42001000) /**< \brief (SERCOM3) I2CM Control A */ -#define REG_SERCOM3_I2CM_CTRLB (0x42001004) /**< \brief (SERCOM3) I2CM Control B */ -#define REG_SERCOM3_I2CM_BAUD (0x4200100C) /**< \brief (SERCOM3) I2CM Baud Rate */ -#define REG_SERCOM3_I2CM_INTENCLR (0x42001014) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */ -#define REG_SERCOM3_I2CM_INTENSET (0x42001016) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */ -#define REG_SERCOM3_I2CM_INTFLAG (0x42001018) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM3_I2CM_STATUS (0x4200101A) /**< \brief (SERCOM3) I2CM Status */ -#define REG_SERCOM3_I2CM_SYNCBUSY (0x4200101C) /**< \brief (SERCOM3) I2CM Synchronization Busy */ -#define REG_SERCOM3_I2CM_ADDR (0x42001024) /**< \brief (SERCOM3) I2CM Address */ -#define REG_SERCOM3_I2CM_DATA (0x42001028) /**< \brief (SERCOM3) I2CM Data */ -#define REG_SERCOM3_I2CM_DBGCTRL (0x42001030) /**< \brief (SERCOM3) I2CM Debug Control */ -#define REG_SERCOM3_I2CS_CTRLA (0x42001000) /**< \brief (SERCOM3) I2CS Control A */ -#define REG_SERCOM3_I2CS_CTRLB (0x42001004) /**< \brief (SERCOM3) I2CS Control B */ -#define REG_SERCOM3_I2CS_INTENCLR (0x42001014) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */ -#define REG_SERCOM3_I2CS_INTENSET (0x42001016) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */ -#define REG_SERCOM3_I2CS_INTFLAG (0x42001018) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM3_I2CS_STATUS (0x4200101A) /**< \brief (SERCOM3) I2CS Status */ -#define REG_SERCOM3_I2CS_SYNCBUSY (0x4200101C) /**< \brief (SERCOM3) I2CS Synchronization Busy */ -#define REG_SERCOM3_I2CS_ADDR (0x42001024) /**< \brief (SERCOM3) I2CS Address */ -#define REG_SERCOM3_I2CS_DATA (0x42001028) /**< \brief (SERCOM3) I2CS Data */ -#define REG_SERCOM3_SPI_CTRLA (0x42001000) /**< \brief (SERCOM3) SPI Control A */ -#define REG_SERCOM3_SPI_CTRLB (0x42001004) /**< \brief (SERCOM3) SPI Control B */ -#define REG_SERCOM3_SPI_BAUD (0x4200100C) /**< \brief (SERCOM3) SPI Baud Rate */ -#define REG_SERCOM3_SPI_INTENCLR (0x42001014) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */ -#define REG_SERCOM3_SPI_INTENSET (0x42001016) /**< \brief (SERCOM3) SPI Interrupt Enable Set */ -#define REG_SERCOM3_SPI_INTFLAG (0x42001018) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM3_SPI_STATUS (0x4200101A) /**< \brief (SERCOM3) SPI Status */ -#define REG_SERCOM3_SPI_SYNCBUSY (0x4200101C) /**< \brief (SERCOM3) SPI Synchronization Busy */ -#define REG_SERCOM3_SPI_ADDR (0x42001024) /**< \brief (SERCOM3) SPI Address */ -#define REG_SERCOM3_SPI_DATA (0x42001028) /**< \brief (SERCOM3) SPI Data */ -#define REG_SERCOM3_SPI_DBGCTRL (0x42001030) /**< \brief (SERCOM3) SPI Debug Control */ -#define REG_SERCOM3_USART_CTRLA (0x42001000) /**< \brief (SERCOM3) USART Control A */ -#define REG_SERCOM3_USART_CTRLB (0x42001004) /**< \brief (SERCOM3) USART Control B */ -#define REG_SERCOM3_USART_CTRLC (0x42001008) /**< \brief (SERCOM3) USART Control C */ -#define REG_SERCOM3_USART_BAUD (0x4200100C) /**< \brief (SERCOM3) USART Baud Rate */ -#define REG_SERCOM3_USART_RXPL (0x4200100E) /**< \brief (SERCOM3) USART Receive Pulse Length */ -#define REG_SERCOM3_USART_INTENCLR (0x42001014) /**< \brief (SERCOM3) USART Interrupt Enable Clear */ -#define REG_SERCOM3_USART_INTENSET (0x42001016) /**< \brief (SERCOM3) USART Interrupt Enable Set */ -#define REG_SERCOM3_USART_INTFLAG (0x42001018) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM3_USART_STATUS (0x4200101A) /**< \brief (SERCOM3) USART Status */ -#define REG_SERCOM3_USART_SYNCBUSY (0x4200101C) /**< \brief (SERCOM3) USART Synchronization Busy */ -#define REG_SERCOM3_USART_RXERRCNT (0x42001020) /**< \brief (SERCOM3) USART Receive Error Count */ -#define REG_SERCOM3_USART_DATA (0x42001028) /**< \brief (SERCOM3) USART Data */ -#define REG_SERCOM3_USART_DBGCTRL (0x42001030) /**< \brief (SERCOM3) USART Debug Control */ -#else -#define REG_SERCOM3_I2CM_CTRLA (*(RwReg *)0x42001000UL) /**< \brief (SERCOM3) I2CM Control A */ -#define REG_SERCOM3_I2CM_CTRLB (*(RwReg *)0x42001004UL) /**< \brief (SERCOM3) I2CM Control B */ -#define REG_SERCOM3_I2CM_BAUD (*(RwReg *)0x4200100CUL) /**< \brief (SERCOM3) I2CM Baud Rate */ -#define REG_SERCOM3_I2CM_INTENCLR (*(RwReg8 *)0x42001014UL) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */ -#define REG_SERCOM3_I2CM_INTENSET (*(RwReg8 *)0x42001016UL) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */ -#define REG_SERCOM3_I2CM_INTFLAG (*(RwReg8 *)0x42001018UL) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM3_I2CM_STATUS (*(RwReg16*)0x4200101AUL) /**< \brief (SERCOM3) I2CM Status */ -#define REG_SERCOM3_I2CM_SYNCBUSY (*(RoReg *)0x4200101CUL) /**< \brief (SERCOM3) I2CM Synchronization Busy */ -#define REG_SERCOM3_I2CM_ADDR (*(RwReg *)0x42001024UL) /**< \brief (SERCOM3) I2CM Address */ -#define REG_SERCOM3_I2CM_DATA (*(RwReg8 *)0x42001028UL) /**< \brief (SERCOM3) I2CM Data */ -#define REG_SERCOM3_I2CM_DBGCTRL (*(RwReg8 *)0x42001030UL) /**< \brief (SERCOM3) I2CM Debug Control */ -#define REG_SERCOM3_I2CS_CTRLA (*(RwReg *)0x42001000UL) /**< \brief (SERCOM3) I2CS Control A */ -#define REG_SERCOM3_I2CS_CTRLB (*(RwReg *)0x42001004UL) /**< \brief (SERCOM3) I2CS Control B */ -#define REG_SERCOM3_I2CS_INTENCLR (*(RwReg8 *)0x42001014UL) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */ -#define REG_SERCOM3_I2CS_INTENSET (*(RwReg8 *)0x42001016UL) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */ -#define REG_SERCOM3_I2CS_INTFLAG (*(RwReg8 *)0x42001018UL) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM3_I2CS_STATUS (*(RwReg16*)0x4200101AUL) /**< \brief (SERCOM3) I2CS Status */ -#define REG_SERCOM3_I2CS_SYNCBUSY (*(RoReg *)0x4200101CUL) /**< \brief (SERCOM3) I2CS Synchronization Busy */ -#define REG_SERCOM3_I2CS_ADDR (*(RwReg *)0x42001024UL) /**< \brief (SERCOM3) I2CS Address */ -#define REG_SERCOM3_I2CS_DATA (*(RwReg8 *)0x42001028UL) /**< \brief (SERCOM3) I2CS Data */ -#define REG_SERCOM3_SPI_CTRLA (*(RwReg *)0x42001000UL) /**< \brief (SERCOM3) SPI Control A */ -#define REG_SERCOM3_SPI_CTRLB (*(RwReg *)0x42001004UL) /**< \brief (SERCOM3) SPI Control B */ -#define REG_SERCOM3_SPI_BAUD (*(RwReg8 *)0x4200100CUL) /**< \brief (SERCOM3) SPI Baud Rate */ -#define REG_SERCOM3_SPI_INTENCLR (*(RwReg8 *)0x42001014UL) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */ -#define REG_SERCOM3_SPI_INTENSET (*(RwReg8 *)0x42001016UL) /**< \brief (SERCOM3) SPI Interrupt Enable Set */ -#define REG_SERCOM3_SPI_INTFLAG (*(RwReg8 *)0x42001018UL) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM3_SPI_STATUS (*(RwReg16*)0x4200101AUL) /**< \brief (SERCOM3) SPI Status */ -#define REG_SERCOM3_SPI_SYNCBUSY (*(RoReg *)0x4200101CUL) /**< \brief (SERCOM3) SPI Synchronization Busy */ -#define REG_SERCOM3_SPI_ADDR (*(RwReg *)0x42001024UL) /**< \brief (SERCOM3) SPI Address */ -#define REG_SERCOM3_SPI_DATA (*(RwReg *)0x42001028UL) /**< \brief (SERCOM3) SPI Data */ -#define REG_SERCOM3_SPI_DBGCTRL (*(RwReg8 *)0x42001030UL) /**< \brief (SERCOM3) SPI Debug Control */ -#define REG_SERCOM3_USART_CTRLA (*(RwReg *)0x42001000UL) /**< \brief (SERCOM3) USART Control A */ -#define REG_SERCOM3_USART_CTRLB (*(RwReg *)0x42001004UL) /**< \brief (SERCOM3) USART Control B */ -#define REG_SERCOM3_USART_CTRLC (*(RwReg *)0x42001008UL) /**< \brief (SERCOM3) USART Control C */ -#define REG_SERCOM3_USART_BAUD (*(RwReg16*)0x4200100CUL) /**< \brief (SERCOM3) USART Baud Rate */ -#define REG_SERCOM3_USART_RXPL (*(RwReg8 *)0x4200100EUL) /**< \brief (SERCOM3) USART Receive Pulse Length */ -#define REG_SERCOM3_USART_INTENCLR (*(RwReg8 *)0x42001014UL) /**< \brief (SERCOM3) USART Interrupt Enable Clear */ -#define REG_SERCOM3_USART_INTENSET (*(RwReg8 *)0x42001016UL) /**< \brief (SERCOM3) USART Interrupt Enable Set */ -#define REG_SERCOM3_USART_INTFLAG (*(RwReg8 *)0x42001018UL) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM3_USART_STATUS (*(RwReg16*)0x4200101AUL) /**< \brief (SERCOM3) USART Status */ -#define REG_SERCOM3_USART_SYNCBUSY (*(RoReg *)0x4200101CUL) /**< \brief (SERCOM3) USART Synchronization Busy */ -#define REG_SERCOM3_USART_RXERRCNT (*(RoReg8 *)0x42001020UL) /**< \brief (SERCOM3) USART Receive Error Count */ -#define REG_SERCOM3_USART_DATA (*(RwReg16*)0x42001028UL) /**< \brief (SERCOM3) USART Data */ -#define REG_SERCOM3_USART_DBGCTRL (*(RwReg8 *)0x42001030UL) /**< \brief (SERCOM3) USART Debug Control */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for SERCOM3 peripheral ========== */ -#define SERCOM3_DMAC_ID_RX 8 // Index of DMA RX trigger -#define SERCOM3_DMAC_ID_TX 9 // Index of DMA TX trigger -#define SERCOM3_GCLK_ID_CORE 19 -#define SERCOM3_GCLK_ID_SLOW 15 -#define SERCOM3_INT_MSB 6 -#define SERCOM3_PMSB 3 -#define SERCOM3_SPI 1 // SPI mode implemented? -#define SERCOM3_TWIM 1 // TWI Master mode implemented? -#define SERCOM3_TWIS 1 // TWI Slave mode implemented? -#define SERCOM3_TWI_HSMODE 0 // TWI HighSpeed mode implemented? -#define SERCOM3_USART 1 // USART mode implemented? -#define SERCOM3_USART_ISO7816 1 // USART ISO7816 mode implemented? -#define SERCOM3_USART_LIN_MASTER 0 // USART LIN Master mode implemented? -#define SERCOM3_USART_RS485 1 // USART RS485 mode implemented? - -#endif /* _SAML22_SERCOM3_INSTANCE_ */ diff --git a/watch-library/include/instance/sercom4.h b/watch-library/include/instance/sercom4.h deleted file mode 100644 index d5f5d736..00000000 --- a/watch-library/include/instance/sercom4.h +++ /dev/null @@ -1,142 +0,0 @@ -/** - * \file - * - * \brief Instance description for SERCOM4 - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_SERCOM4_INSTANCE_ -#define _SAML22_SERCOM4_INSTANCE_ - -/* ========== Register definition for SERCOM4 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_SERCOM4_I2CM_CTRLA (0x42001400) /**< \brief (SERCOM4) I2CM Control A */ -#define REG_SERCOM4_I2CM_CTRLB (0x42001404) /**< \brief (SERCOM4) I2CM Control B */ -#define REG_SERCOM4_I2CM_BAUD (0x4200140C) /**< \brief (SERCOM4) I2CM Baud Rate */ -#define REG_SERCOM4_I2CM_INTENCLR (0x42001414) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */ -#define REG_SERCOM4_I2CM_INTENSET (0x42001416) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */ -#define REG_SERCOM4_I2CM_INTFLAG (0x42001418) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM4_I2CM_STATUS (0x4200141A) /**< \brief (SERCOM4) I2CM Status */ -#define REG_SERCOM4_I2CM_SYNCBUSY (0x4200141C) /**< \brief (SERCOM4) I2CM Synchronization Busy */ -#define REG_SERCOM4_I2CM_ADDR (0x42001424) /**< \brief (SERCOM4) I2CM Address */ -#define REG_SERCOM4_I2CM_DATA (0x42001428) /**< \brief (SERCOM4) I2CM Data */ -#define REG_SERCOM4_I2CM_DBGCTRL (0x42001430) /**< \brief (SERCOM4) I2CM Debug Control */ -#define REG_SERCOM4_I2CS_CTRLA (0x42001400) /**< \brief (SERCOM4) I2CS Control A */ -#define REG_SERCOM4_I2CS_CTRLB (0x42001404) /**< \brief (SERCOM4) I2CS Control B */ -#define REG_SERCOM4_I2CS_INTENCLR (0x42001414) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */ -#define REG_SERCOM4_I2CS_INTENSET (0x42001416) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */ -#define REG_SERCOM4_I2CS_INTFLAG (0x42001418) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM4_I2CS_STATUS (0x4200141A) /**< \brief (SERCOM4) I2CS Status */ -#define REG_SERCOM4_I2CS_SYNCBUSY (0x4200141C) /**< \brief (SERCOM4) I2CS Synchronization Busy */ -#define REG_SERCOM4_I2CS_ADDR (0x42001424) /**< \brief (SERCOM4) I2CS Address */ -#define REG_SERCOM4_I2CS_DATA (0x42001428) /**< \brief (SERCOM4) I2CS Data */ -#define REG_SERCOM4_SPI_CTRLA (0x42001400) /**< \brief (SERCOM4) SPI Control A */ -#define REG_SERCOM4_SPI_CTRLB (0x42001404) /**< \brief (SERCOM4) SPI Control B */ -#define REG_SERCOM4_SPI_BAUD (0x4200140C) /**< \brief (SERCOM4) SPI Baud Rate */ -#define REG_SERCOM4_SPI_INTENCLR (0x42001414) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */ -#define REG_SERCOM4_SPI_INTENSET (0x42001416) /**< \brief (SERCOM4) SPI Interrupt Enable Set */ -#define REG_SERCOM4_SPI_INTFLAG (0x42001418) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM4_SPI_STATUS (0x4200141A) /**< \brief (SERCOM4) SPI Status */ -#define REG_SERCOM4_SPI_SYNCBUSY (0x4200141C) /**< \brief (SERCOM4) SPI Synchronization Busy */ -#define REG_SERCOM4_SPI_ADDR (0x42001424) /**< \brief (SERCOM4) SPI Address */ -#define REG_SERCOM4_SPI_DATA (0x42001428) /**< \brief (SERCOM4) SPI Data */ -#define REG_SERCOM4_SPI_DBGCTRL (0x42001430) /**< \brief (SERCOM4) SPI Debug Control */ -#define REG_SERCOM4_USART_CTRLA (0x42001400) /**< \brief (SERCOM4) USART Control A */ -#define REG_SERCOM4_USART_CTRLB (0x42001404) /**< \brief (SERCOM4) USART Control B */ -#define REG_SERCOM4_USART_CTRLC (0x42001408) /**< \brief (SERCOM4) USART Control C */ -#define REG_SERCOM4_USART_BAUD (0x4200140C) /**< \brief (SERCOM4) USART Baud Rate */ -#define REG_SERCOM4_USART_RXPL (0x4200140E) /**< \brief (SERCOM4) USART Receive Pulse Length */ -#define REG_SERCOM4_USART_INTENCLR (0x42001414) /**< \brief (SERCOM4) USART Interrupt Enable Clear */ -#define REG_SERCOM4_USART_INTENSET (0x42001416) /**< \brief (SERCOM4) USART Interrupt Enable Set */ -#define REG_SERCOM4_USART_INTFLAG (0x42001418) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM4_USART_STATUS (0x4200141A) /**< \brief (SERCOM4) USART Status */ -#define REG_SERCOM4_USART_SYNCBUSY (0x4200141C) /**< \brief (SERCOM4) USART Synchronization Busy */ -#define REG_SERCOM4_USART_RXERRCNT (0x42001420) /**< \brief (SERCOM4) USART Receive Error Count */ -#define REG_SERCOM4_USART_DATA (0x42001428) /**< \brief (SERCOM4) USART Data */ -#define REG_SERCOM4_USART_DBGCTRL (0x42001430) /**< \brief (SERCOM4) USART Debug Control */ -#else -#define REG_SERCOM4_I2CM_CTRLA (*(RwReg *)0x42001400UL) /**< \brief (SERCOM4) I2CM Control A */ -#define REG_SERCOM4_I2CM_CTRLB (*(RwReg *)0x42001404UL) /**< \brief (SERCOM4) I2CM Control B */ -#define REG_SERCOM4_I2CM_BAUD (*(RwReg *)0x4200140CUL) /**< \brief (SERCOM4) I2CM Baud Rate */ -#define REG_SERCOM4_I2CM_INTENCLR (*(RwReg8 *)0x42001414UL) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */ -#define REG_SERCOM4_I2CM_INTENSET (*(RwReg8 *)0x42001416UL) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */ -#define REG_SERCOM4_I2CM_INTFLAG (*(RwReg8 *)0x42001418UL) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM4_I2CM_STATUS (*(RwReg16*)0x4200141AUL) /**< \brief (SERCOM4) I2CM Status */ -#define REG_SERCOM4_I2CM_SYNCBUSY (*(RoReg *)0x4200141CUL) /**< \brief (SERCOM4) I2CM Synchronization Busy */ -#define REG_SERCOM4_I2CM_ADDR (*(RwReg *)0x42001424UL) /**< \brief (SERCOM4) I2CM Address */ -#define REG_SERCOM4_I2CM_DATA (*(RwReg8 *)0x42001428UL) /**< \brief (SERCOM4) I2CM Data */ -#define REG_SERCOM4_I2CM_DBGCTRL (*(RwReg8 *)0x42001430UL) /**< \brief (SERCOM4) I2CM Debug Control */ -#define REG_SERCOM4_I2CS_CTRLA (*(RwReg *)0x42001400UL) /**< \brief (SERCOM4) I2CS Control A */ -#define REG_SERCOM4_I2CS_CTRLB (*(RwReg *)0x42001404UL) /**< \brief (SERCOM4) I2CS Control B */ -#define REG_SERCOM4_I2CS_INTENCLR (*(RwReg8 *)0x42001414UL) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */ -#define REG_SERCOM4_I2CS_INTENSET (*(RwReg8 *)0x42001416UL) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */ -#define REG_SERCOM4_I2CS_INTFLAG (*(RwReg8 *)0x42001418UL) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM4_I2CS_STATUS (*(RwReg16*)0x4200141AUL) /**< \brief (SERCOM4) I2CS Status */ -#define REG_SERCOM4_I2CS_SYNCBUSY (*(RoReg *)0x4200141CUL) /**< \brief (SERCOM4) I2CS Synchronization Busy */ -#define REG_SERCOM4_I2CS_ADDR (*(RwReg *)0x42001424UL) /**< \brief (SERCOM4) I2CS Address */ -#define REG_SERCOM4_I2CS_DATA (*(RwReg8 *)0x42001428UL) /**< \brief (SERCOM4) I2CS Data */ -#define REG_SERCOM4_SPI_CTRLA (*(RwReg *)0x42001400UL) /**< \brief (SERCOM4) SPI Control A */ -#define REG_SERCOM4_SPI_CTRLB (*(RwReg *)0x42001404UL) /**< \brief (SERCOM4) SPI Control B */ -#define REG_SERCOM4_SPI_BAUD (*(RwReg8 *)0x4200140CUL) /**< \brief (SERCOM4) SPI Baud Rate */ -#define REG_SERCOM4_SPI_INTENCLR (*(RwReg8 *)0x42001414UL) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */ -#define REG_SERCOM4_SPI_INTENSET (*(RwReg8 *)0x42001416UL) /**< \brief (SERCOM4) SPI Interrupt Enable Set */ -#define REG_SERCOM4_SPI_INTFLAG (*(RwReg8 *)0x42001418UL) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM4_SPI_STATUS (*(RwReg16*)0x4200141AUL) /**< \brief (SERCOM4) SPI Status */ -#define REG_SERCOM4_SPI_SYNCBUSY (*(RoReg *)0x4200141CUL) /**< \brief (SERCOM4) SPI Synchronization Busy */ -#define REG_SERCOM4_SPI_ADDR (*(RwReg *)0x42001424UL) /**< \brief (SERCOM4) SPI Address */ -#define REG_SERCOM4_SPI_DATA (*(RwReg *)0x42001428UL) /**< \brief (SERCOM4) SPI Data */ -#define REG_SERCOM4_SPI_DBGCTRL (*(RwReg8 *)0x42001430UL) /**< \brief (SERCOM4) SPI Debug Control */ -#define REG_SERCOM4_USART_CTRLA (*(RwReg *)0x42001400UL) /**< \brief (SERCOM4) USART Control A */ -#define REG_SERCOM4_USART_CTRLB (*(RwReg *)0x42001404UL) /**< \brief (SERCOM4) USART Control B */ -#define REG_SERCOM4_USART_CTRLC (*(RwReg *)0x42001408UL) /**< \brief (SERCOM4) USART Control C */ -#define REG_SERCOM4_USART_BAUD (*(RwReg16*)0x4200140CUL) /**< \brief (SERCOM4) USART Baud Rate */ -#define REG_SERCOM4_USART_RXPL (*(RwReg8 *)0x4200140EUL) /**< \brief (SERCOM4) USART Receive Pulse Length */ -#define REG_SERCOM4_USART_INTENCLR (*(RwReg8 *)0x42001414UL) /**< \brief (SERCOM4) USART Interrupt Enable Clear */ -#define REG_SERCOM4_USART_INTENSET (*(RwReg8 *)0x42001416UL) /**< \brief (SERCOM4) USART Interrupt Enable Set */ -#define REG_SERCOM4_USART_INTFLAG (*(RwReg8 *)0x42001418UL) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM4_USART_STATUS (*(RwReg16*)0x4200141AUL) /**< \brief (SERCOM4) USART Status */ -#define REG_SERCOM4_USART_SYNCBUSY (*(RoReg *)0x4200141CUL) /**< \brief (SERCOM4) USART Synchronization Busy */ -#define REG_SERCOM4_USART_RXERRCNT (*(RoReg8 *)0x42001420UL) /**< \brief (SERCOM4) USART Receive Error Count */ -#define REG_SERCOM4_USART_DATA (*(RwReg16*)0x42001428UL) /**< \brief (SERCOM4) USART Data */ -#define REG_SERCOM4_USART_DBGCTRL (*(RwReg8 *)0x42001430UL) /**< \brief (SERCOM4) USART Debug Control */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for SERCOM4 peripheral ========== */ -#define SERCOM4_DMAC_ID_RX 10 // Index of DMA RX trigger -#define SERCOM4_DMAC_ID_TX 11 // Index of DMA TX trigger -#define SERCOM4_GCLK_ID_CORE 20 -#define SERCOM4_GCLK_ID_SLOW 15 -#define SERCOM4_INT_MSB 6 -#define SERCOM4_PMSB 3 -#define SERCOM4_SPI 1 // SPI mode implemented? -#define SERCOM4_TWIM 1 // TWI Master mode implemented? -#define SERCOM4_TWIS 1 // TWI Slave mode implemented? -#define SERCOM4_TWI_HSMODE 0 // TWI HighSpeed mode implemented? -#define SERCOM4_USART 1 // USART mode implemented? -#define SERCOM4_USART_ISO7816 1 // USART ISO7816 mode implemented? -#define SERCOM4_USART_LIN_MASTER 0 // USART LIN Master mode implemented? -#define SERCOM4_USART_RS485 1 // USART RS485 mode implemented? - -#endif /* _SAML22_SERCOM4_INSTANCE_ */ diff --git a/watch-library/include/instance/sercom5.h b/watch-library/include/instance/sercom5.h deleted file mode 100644 index 93214cf3..00000000 --- a/watch-library/include/instance/sercom5.h +++ /dev/null @@ -1,142 +0,0 @@ -/** - * \file - * - * \brief Instance description for SERCOM5 - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_SERCOM5_INSTANCE_ -#define _SAML22_SERCOM5_INSTANCE_ - -/* ========== Register definition for SERCOM5 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_SERCOM5_I2CM_CTRLA (0x42001800) /**< \brief (SERCOM5) I2CM Control A */ -#define REG_SERCOM5_I2CM_CTRLB (0x42001804) /**< \brief (SERCOM5) I2CM Control B */ -#define REG_SERCOM5_I2CM_BAUD (0x4200180C) /**< \brief (SERCOM5) I2CM Baud Rate */ -#define REG_SERCOM5_I2CM_INTENCLR (0x42001814) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */ -#define REG_SERCOM5_I2CM_INTENSET (0x42001816) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */ -#define REG_SERCOM5_I2CM_INTFLAG (0x42001818) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM5_I2CM_STATUS (0x4200181A) /**< \brief (SERCOM5) I2CM Status */ -#define REG_SERCOM5_I2CM_SYNCBUSY (0x4200181C) /**< \brief (SERCOM5) I2CM Synchronization Busy */ -#define REG_SERCOM5_I2CM_ADDR (0x42001824) /**< \brief (SERCOM5) I2CM Address */ -#define REG_SERCOM5_I2CM_DATA (0x42001828) /**< \brief (SERCOM5) I2CM Data */ -#define REG_SERCOM5_I2CM_DBGCTRL (0x42001830) /**< \brief (SERCOM5) I2CM Debug Control */ -#define REG_SERCOM5_I2CS_CTRLA (0x42001800) /**< \brief (SERCOM5) I2CS Control A */ -#define REG_SERCOM5_I2CS_CTRLB (0x42001804) /**< \brief (SERCOM5) I2CS Control B */ -#define REG_SERCOM5_I2CS_INTENCLR (0x42001814) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */ -#define REG_SERCOM5_I2CS_INTENSET (0x42001816) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */ -#define REG_SERCOM5_I2CS_INTFLAG (0x42001818) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM5_I2CS_STATUS (0x4200181A) /**< \brief (SERCOM5) I2CS Status */ -#define REG_SERCOM5_I2CS_SYNCBUSY (0x4200181C) /**< \brief (SERCOM5) I2CS Synchronization Busy */ -#define REG_SERCOM5_I2CS_ADDR (0x42001824) /**< \brief (SERCOM5) I2CS Address */ -#define REG_SERCOM5_I2CS_DATA (0x42001828) /**< \brief (SERCOM5) I2CS Data */ -#define REG_SERCOM5_SPI_CTRLA (0x42001800) /**< \brief (SERCOM5) SPI Control A */ -#define REG_SERCOM5_SPI_CTRLB (0x42001804) /**< \brief (SERCOM5) SPI Control B */ -#define REG_SERCOM5_SPI_BAUD (0x4200180C) /**< \brief (SERCOM5) SPI Baud Rate */ -#define REG_SERCOM5_SPI_INTENCLR (0x42001814) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */ -#define REG_SERCOM5_SPI_INTENSET (0x42001816) /**< \brief (SERCOM5) SPI Interrupt Enable Set */ -#define REG_SERCOM5_SPI_INTFLAG (0x42001818) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM5_SPI_STATUS (0x4200181A) /**< \brief (SERCOM5) SPI Status */ -#define REG_SERCOM5_SPI_SYNCBUSY (0x4200181C) /**< \brief (SERCOM5) SPI Synchronization Busy */ -#define REG_SERCOM5_SPI_ADDR (0x42001824) /**< \brief (SERCOM5) SPI Address */ -#define REG_SERCOM5_SPI_DATA (0x42001828) /**< \brief (SERCOM5) SPI Data */ -#define REG_SERCOM5_SPI_DBGCTRL (0x42001830) /**< \brief (SERCOM5) SPI Debug Control */ -#define REG_SERCOM5_USART_CTRLA (0x42001800) /**< \brief (SERCOM5) USART Control A */ -#define REG_SERCOM5_USART_CTRLB (0x42001804) /**< \brief (SERCOM5) USART Control B */ -#define REG_SERCOM5_USART_CTRLC (0x42001808) /**< \brief (SERCOM5) USART Control C */ -#define REG_SERCOM5_USART_BAUD (0x4200180C) /**< \brief (SERCOM5) USART Baud Rate */ -#define REG_SERCOM5_USART_RXPL (0x4200180E) /**< \brief (SERCOM5) USART Receive Pulse Length */ -#define REG_SERCOM5_USART_INTENCLR (0x42001814) /**< \brief (SERCOM5) USART Interrupt Enable Clear */ -#define REG_SERCOM5_USART_INTENSET (0x42001816) /**< \brief (SERCOM5) USART Interrupt Enable Set */ -#define REG_SERCOM5_USART_INTFLAG (0x42001818) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM5_USART_STATUS (0x4200181A) /**< \brief (SERCOM5) USART Status */ -#define REG_SERCOM5_USART_SYNCBUSY (0x4200181C) /**< \brief (SERCOM5) USART Synchronization Busy */ -#define REG_SERCOM5_USART_RXERRCNT (0x42001820) /**< \brief (SERCOM5) USART Receive Error Count */ -#define REG_SERCOM5_USART_DATA (0x42001828) /**< \brief (SERCOM5) USART Data */ -#define REG_SERCOM5_USART_DBGCTRL (0x42001830) /**< \brief (SERCOM5) USART Debug Control */ -#else -#define REG_SERCOM5_I2CM_CTRLA (*(RwReg *)0x42001800UL) /**< \brief (SERCOM5) I2CM Control A */ -#define REG_SERCOM5_I2CM_CTRLB (*(RwReg *)0x42001804UL) /**< \brief (SERCOM5) I2CM Control B */ -#define REG_SERCOM5_I2CM_BAUD (*(RwReg *)0x4200180CUL) /**< \brief (SERCOM5) I2CM Baud Rate */ -#define REG_SERCOM5_I2CM_INTENCLR (*(RwReg8 *)0x42001814UL) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */ -#define REG_SERCOM5_I2CM_INTENSET (*(RwReg8 *)0x42001816UL) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */ -#define REG_SERCOM5_I2CM_INTFLAG (*(RwReg8 *)0x42001818UL) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */ -#define REG_SERCOM5_I2CM_STATUS (*(RwReg16*)0x4200181AUL) /**< \brief (SERCOM5) I2CM Status */ -#define REG_SERCOM5_I2CM_SYNCBUSY (*(RoReg *)0x4200181CUL) /**< \brief (SERCOM5) I2CM Synchronization Busy */ -#define REG_SERCOM5_I2CM_ADDR (*(RwReg *)0x42001824UL) /**< \brief (SERCOM5) I2CM Address */ -#define REG_SERCOM5_I2CM_DATA (*(RwReg8 *)0x42001828UL) /**< \brief (SERCOM5) I2CM Data */ -#define REG_SERCOM5_I2CM_DBGCTRL (*(RwReg8 *)0x42001830UL) /**< \brief (SERCOM5) I2CM Debug Control */ -#define REG_SERCOM5_I2CS_CTRLA (*(RwReg *)0x42001800UL) /**< \brief (SERCOM5) I2CS Control A */ -#define REG_SERCOM5_I2CS_CTRLB (*(RwReg *)0x42001804UL) /**< \brief (SERCOM5) I2CS Control B */ -#define REG_SERCOM5_I2CS_INTENCLR (*(RwReg8 *)0x42001814UL) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */ -#define REG_SERCOM5_I2CS_INTENSET (*(RwReg8 *)0x42001816UL) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */ -#define REG_SERCOM5_I2CS_INTFLAG (*(RwReg8 *)0x42001818UL) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */ -#define REG_SERCOM5_I2CS_STATUS (*(RwReg16*)0x4200181AUL) /**< \brief (SERCOM5) I2CS Status */ -#define REG_SERCOM5_I2CS_SYNCBUSY (*(RoReg *)0x4200181CUL) /**< \brief (SERCOM5) I2CS Synchronization Busy */ -#define REG_SERCOM5_I2CS_ADDR (*(RwReg *)0x42001824UL) /**< \brief (SERCOM5) I2CS Address */ -#define REG_SERCOM5_I2CS_DATA (*(RwReg8 *)0x42001828UL) /**< \brief (SERCOM5) I2CS Data */ -#define REG_SERCOM5_SPI_CTRLA (*(RwReg *)0x42001800UL) /**< \brief (SERCOM5) SPI Control A */ -#define REG_SERCOM5_SPI_CTRLB (*(RwReg *)0x42001804UL) /**< \brief (SERCOM5) SPI Control B */ -#define REG_SERCOM5_SPI_BAUD (*(RwReg8 *)0x4200180CUL) /**< \brief (SERCOM5) SPI Baud Rate */ -#define REG_SERCOM5_SPI_INTENCLR (*(RwReg8 *)0x42001814UL) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */ -#define REG_SERCOM5_SPI_INTENSET (*(RwReg8 *)0x42001816UL) /**< \brief (SERCOM5) SPI Interrupt Enable Set */ -#define REG_SERCOM5_SPI_INTFLAG (*(RwReg8 *)0x42001818UL) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */ -#define REG_SERCOM5_SPI_STATUS (*(RwReg16*)0x4200181AUL) /**< \brief (SERCOM5) SPI Status */ -#define REG_SERCOM5_SPI_SYNCBUSY (*(RoReg *)0x4200181CUL) /**< \brief (SERCOM5) SPI Synchronization Busy */ -#define REG_SERCOM5_SPI_ADDR (*(RwReg *)0x42001824UL) /**< \brief (SERCOM5) SPI Address */ -#define REG_SERCOM5_SPI_DATA (*(RwReg *)0x42001828UL) /**< \brief (SERCOM5) SPI Data */ -#define REG_SERCOM5_SPI_DBGCTRL (*(RwReg8 *)0x42001830UL) /**< \brief (SERCOM5) SPI Debug Control */ -#define REG_SERCOM5_USART_CTRLA (*(RwReg *)0x42001800UL) /**< \brief (SERCOM5) USART Control A */ -#define REG_SERCOM5_USART_CTRLB (*(RwReg *)0x42001804UL) /**< \brief (SERCOM5) USART Control B */ -#define REG_SERCOM5_USART_CTRLC (*(RwReg *)0x42001808UL) /**< \brief (SERCOM5) USART Control C */ -#define REG_SERCOM5_USART_BAUD (*(RwReg16*)0x4200180CUL) /**< \brief (SERCOM5) USART Baud Rate */ -#define REG_SERCOM5_USART_RXPL (*(RwReg8 *)0x4200180EUL) /**< \brief (SERCOM5) USART Receive Pulse Length */ -#define REG_SERCOM5_USART_INTENCLR (*(RwReg8 *)0x42001814UL) /**< \brief (SERCOM5) USART Interrupt Enable Clear */ -#define REG_SERCOM5_USART_INTENSET (*(RwReg8 *)0x42001816UL) /**< \brief (SERCOM5) USART Interrupt Enable Set */ -#define REG_SERCOM5_USART_INTFLAG (*(RwReg8 *)0x42001818UL) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */ -#define REG_SERCOM5_USART_STATUS (*(RwReg16*)0x4200181AUL) /**< \brief (SERCOM5) USART Status */ -#define REG_SERCOM5_USART_SYNCBUSY (*(RoReg *)0x4200181CUL) /**< \brief (SERCOM5) USART Synchronization Busy */ -#define REG_SERCOM5_USART_RXERRCNT (*(RoReg8 *)0x42001820UL) /**< \brief (SERCOM5) USART Receive Error Count */ -#define REG_SERCOM5_USART_DATA (*(RwReg16*)0x42001828UL) /**< \brief (SERCOM5) USART Data */ -#define REG_SERCOM5_USART_DBGCTRL (*(RwReg8 *)0x42001830UL) /**< \brief (SERCOM5) USART Debug Control */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for SERCOM5 peripheral ========== */ -#define SERCOM5_DMAC_ID_RX 12 // Index of DMA RX trigger -#define SERCOM5_DMAC_ID_TX 13 // Index of DMA TX trigger -#define SERCOM5_GCLK_ID_CORE 21 -#define SERCOM5_GCLK_ID_SLOW 15 -#define SERCOM5_INT_MSB 3 -#define SERCOM5_PMSB 3 -#define SERCOM5_SPI 1 // SPI mode implemented? -#define SERCOM5_TWIM 1 // TWI Master mode implemented? -#define SERCOM5_TWIS 1 // TWI Slave mode implemented? -#define SERCOM5_TWI_HSMODE 1 // TWI HighSpeed mode implemented? -#define SERCOM5_USART 1 // USART mode implemented? -#define SERCOM5_USART_ISO7816 1 // USART ISO7816 mode implemented? -#define SERCOM5_USART_LIN_MASTER 0 // USART LIN Master mode implemented? -#define SERCOM5_USART_RS485 1 // USART RS485 mode implemented? - -#endif /* _SAML22_SERCOM5_INSTANCE_ */ diff --git a/watch-library/include/instance/slcd.h b/watch-library/include/instance/slcd.h deleted file mode 100644 index c4785831..00000000 --- a/watch-library/include/instance/slcd.h +++ /dev/null @@ -1,126 +0,0 @@ -/** - * \file - * - * \brief Instance description for SLCD - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_SLCD_INSTANCE_ -#define _SAML22_SLCD_INSTANCE_ - -/* ========== Register definition for SLCD peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_SLCD_CTRLA (0x42003C00) /**< \brief (SLCD) Control A */ -#define REG_SLCD_CTRLB (0x42003C04) /**< \brief (SLCD) Control B */ -#define REG_SLCD_CTRLC (0x42003C06) /**< \brief (SLCD) Control C */ -#define REG_SLCD_CTRLD (0x42003C08) /**< \brief (SLCD) Control D */ -#define REG_SLCD_EVCTRL (0x42003C0C) /**< \brief (SLCD) Event Control */ -#define REG_SLCD_INTENCLR (0x42003C0D) /**< \brief (SLCD) Interrupt Enable Clear */ -#define REG_SLCD_INTENSET (0x42003C0E) /**< \brief (SLCD) Interrupt Enable Set */ -#define REG_SLCD_INTFLAG (0x42003C0F) /**< \brief (SLCD) Interrupt Flag Status and Clear */ -#define REG_SLCD_STATUS (0x42003C10) /**< \brief (SLCD) Status */ -#define REG_SLCD_SYNCBUSY (0x42003C14) /**< \brief (SLCD) Synchronization Busy */ -#define REG_SLCD_FC0 (0x42003C18) /**< \brief (SLCD) Frame Counter 0 Configuration */ -#define REG_SLCD_FC1 (0x42003C19) /**< \brief (SLCD) Frame Counter 1 Configuration */ -#define REG_SLCD_FC2 (0x42003C1A) /**< \brief (SLCD) Frame Counter 2 Configuration */ -#define REG_SLCD_LPENL (0x42003C1C) /**< \brief (SLCD) LCD Pin Enable Low */ -#define REG_SLCD_LPENH (0x42003C20) /**< \brief (SLCD) LCD Pin Enable High */ -#define REG_SLCD_SDATAL0 (0x42003C24) /**< \brief (SLCD) Segments Data Low for COM0 Line */ -#define REG_SLCD_SDATAH0 (0x42003C28) /**< \brief (SLCD) Segments Data High for COM0 Line */ -#define REG_SLCD_SDATAL1 (0x42003C2C) /**< \brief (SLCD) Segments Data Low for COM1 Line */ -#define REG_SLCD_SDATAH1 (0x42003C30) /**< \brief (SLCD) Segments Data High for COM1 Line */ -#define REG_SLCD_SDATAL2 (0x42003C34) /**< \brief (SLCD) Segments Data Low for COM2 Line */ -#define REG_SLCD_SDATAH2 (0x42003C38) /**< \brief (SLCD) Segments Data High for COM2 Line */ -#define REG_SLCD_SDATAL3 (0x42003C3C) /**< \brief (SLCD) Segments Data Low for COM3 Line */ -#define REG_SLCD_SDATAH3 (0x42003C40) /**< \brief (SLCD) Segments Data High for COM3 Line */ -#define REG_SLCD_SDATAL4 (0x42003C44) /**< \brief (SLCD) Segments Data Low for COM4 Line */ -#define REG_SLCD_SDATAH4 (0x42003C48) /**< \brief (SLCD) Segments Data High for COM4 Line */ -#define REG_SLCD_SDATAL5 (0x42003C4C) /**< \brief (SLCD) Segments Data Low for COM5 Line */ -#define REG_SLCD_SDATAH5 (0x42003C50) /**< \brief (SLCD) Segments Data High for COM5 Line */ -#define REG_SLCD_SDATAL6 (0x42003C54) /**< \brief (SLCD) Segments Data Low for COM6 Line */ -#define REG_SLCD_SDATAH6 (0x42003C58) /**< \brief (SLCD) Segments Data High for COM6 Line */ -#define REG_SLCD_SDATAL7 (0x42003C5C) /**< \brief (SLCD) Segments Data Low for COM7 Line */ -#define REG_SLCD_SDATAH7 (0x42003C60) /**< \brief (SLCD) Segments Data High for COM7 Line */ -#define REG_SLCD_ISDATA (0x42003C64) /**< \brief (SLCD) Indirect Segments Data Access */ -#define REG_SLCD_BCFG (0x42003C68) /**< \brief (SLCD) Blink Configuration */ -#define REG_SLCD_CSRCFG (0x42003C6C) /**< \brief (SLCD) Circular Shift Register Configuration */ -#define REG_SLCD_CMCFG (0x42003C70) /**< \brief (SLCD) Character Mapping Configuration */ -#define REG_SLCD_ACMCFG (0x42003C74) /**< \brief (SLCD) Automated Character Mapping Configuration */ -#define REG_SLCD_ABMCFG (0x42003C78) /**< \brief (SLCD) Automated Bit Mapping Configuration */ -#define REG_SLCD_CMDATA (0x42003C7C) /**< \brief (SLCD) Character Mapping Segments Data */ -#define REG_SLCD_CMDMASK (0x42003C80) /**< \brief (SLCD) Character Mapping Segments Data Mask */ -#define REG_SLCD_CMINDEX (0x42003C84) /**< \brief (SLCD) Character Mapping SEG/COM Index */ -#else -#define REG_SLCD_CTRLA (*(RwReg *)0x42003C00UL) /**< \brief (SLCD) Control A */ -#define REG_SLCD_CTRLB (*(RwReg16*)0x42003C04UL) /**< \brief (SLCD) Control B */ -#define REG_SLCD_CTRLC (*(RwReg16*)0x42003C06UL) /**< \brief (SLCD) Control C */ -#define REG_SLCD_CTRLD (*(RwReg8 *)0x42003C08UL) /**< \brief (SLCD) Control D */ -#define REG_SLCD_EVCTRL (*(RwReg8 *)0x42003C0CUL) /**< \brief (SLCD) Event Control */ -#define REG_SLCD_INTENCLR (*(RwReg8 *)0x42003C0DUL) /**< \brief (SLCD) Interrupt Enable Clear */ -#define REG_SLCD_INTENSET (*(RwReg8 *)0x42003C0EUL) /**< \brief (SLCD) Interrupt Enable Set */ -#define REG_SLCD_INTFLAG (*(RwReg8 *)0x42003C0FUL) /**< \brief (SLCD) Interrupt Flag Status and Clear */ -#define REG_SLCD_STATUS (*(RoReg8 *)0x42003C10UL) /**< \brief (SLCD) Status */ -#define REG_SLCD_SYNCBUSY (*(RoReg *)0x42003C14UL) /**< \brief (SLCD) Synchronization Busy */ -#define REG_SLCD_FC0 (*(RwReg8 *)0x42003C18UL) /**< \brief (SLCD) Frame Counter 0 Configuration */ -#define REG_SLCD_FC1 (*(RwReg8 *)0x42003C19UL) /**< \brief (SLCD) Frame Counter 1 Configuration */ -#define REG_SLCD_FC2 (*(RwReg8 *)0x42003C1AUL) /**< \brief (SLCD) Frame Counter 2 Configuration */ -#define REG_SLCD_LPENL (*(RwReg *)0x42003C1CUL) /**< \brief (SLCD) LCD Pin Enable Low */ -#define REG_SLCD_LPENH (*(RwReg *)0x42003C20UL) /**< \brief (SLCD) LCD Pin Enable High */ -#define REG_SLCD_SDATAL0 (*(RwReg *)0x42003C24UL) /**< \brief (SLCD) Segments Data Low for COM0 Line */ -#define REG_SLCD_SDATAH0 (*(RwReg *)0x42003C28UL) /**< \brief (SLCD) Segments Data High for COM0 Line */ -#define REG_SLCD_SDATAL1 (*(RwReg *)0x42003C2CUL) /**< \brief (SLCD) Segments Data Low for COM1 Line */ -#define REG_SLCD_SDATAH1 (*(RwReg *)0x42003C30UL) /**< \brief (SLCD) Segments Data High for COM1 Line */ -#define REG_SLCD_SDATAL2 (*(RwReg *)0x42003C34UL) /**< \brief (SLCD) Segments Data Low for COM2 Line */ -#define REG_SLCD_SDATAH2 (*(RwReg *)0x42003C38UL) /**< \brief (SLCD) Segments Data High for COM2 Line */ -#define REG_SLCD_SDATAL3 (*(RwReg *)0x42003C3CUL) /**< \brief (SLCD) Segments Data Low for COM3 Line */ -#define REG_SLCD_SDATAH3 (*(RwReg *)0x42003C40UL) /**< \brief (SLCD) Segments Data High for COM3 Line */ -#define REG_SLCD_SDATAL4 (*(RwReg *)0x42003C44UL) /**< \brief (SLCD) Segments Data Low for COM4 Line */ -#define REG_SLCD_SDATAH4 (*(RwReg *)0x42003C48UL) /**< \brief (SLCD) Segments Data High for COM4 Line */ -#define REG_SLCD_SDATAL5 (*(RwReg *)0x42003C4CUL) /**< \brief (SLCD) Segments Data Low for COM5 Line */ -#define REG_SLCD_SDATAH5 (*(RwReg *)0x42003C50UL) /**< \brief (SLCD) Segments Data High for COM5 Line */ -#define REG_SLCD_SDATAL6 (*(RwReg *)0x42003C54UL) /**< \brief (SLCD) Segments Data Low for COM6 Line */ -#define REG_SLCD_SDATAH6 (*(RwReg *)0x42003C58UL) /**< \brief (SLCD) Segments Data High for COM6 Line */ -#define REG_SLCD_SDATAL7 (*(RwReg *)0x42003C5CUL) /**< \brief (SLCD) Segments Data Low for COM7 Line */ -#define REG_SLCD_SDATAH7 (*(RwReg *)0x42003C60UL) /**< \brief (SLCD) Segments Data High for COM7 Line */ -#define REG_SLCD_ISDATA (*(WoReg *)0x42003C64UL) /**< \brief (SLCD) Indirect Segments Data Access */ -#define REG_SLCD_BCFG (*(RwReg *)0x42003C68UL) /**< \brief (SLCD) Blink Configuration */ -#define REG_SLCD_CSRCFG (*(RwReg *)0x42003C6CUL) /**< \brief (SLCD) Circular Shift Register Configuration */ -#define REG_SLCD_CMCFG (*(RwReg8 *)0x42003C70UL) /**< \brief (SLCD) Character Mapping Configuration */ -#define REG_SLCD_ACMCFG (*(RwReg *)0x42003C74UL) /**< \brief (SLCD) Automated Character Mapping Configuration */ -#define REG_SLCD_ABMCFG (*(RwReg8 *)0x42003C78UL) /**< \brief (SLCD) Automated Bit Mapping Configuration */ -#define REG_SLCD_CMDATA (*(WoReg *)0x42003C7CUL) /**< \brief (SLCD) Character Mapping Segments Data */ -#define REG_SLCD_CMDMASK (*(RwReg *)0x42003C80UL) /**< \brief (SLCD) Character Mapping Segments Data Mask */ -#define REG_SLCD_CMINDEX (*(RwReg16*)0x42003C84UL) /**< \brief (SLCD) Character Mapping SEG/COM Index */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for SLCD peripheral ========== */ -#define SLCD_DMAC_ID_ABMDRDY 34 -#define SLCD_DMAC_ID_ACMDRDY 33 -#define SLCD_DMAC_ID_DMU 32 -#define SLCD_MAX_COM 8 // Max number of COM lines (4 or 8) -#define SLCD_MAX_SEG 44 // Max number of SEG lines (24 or 44) -#define SLCD_NB_LP 52 // Number of LCD pins ([28..64] or [48..64]) - -#endif /* _SAML22_SLCD_INSTANCE_ */ diff --git a/watch-library/include/instance/supc.h b/watch-library/include/instance/supc.h deleted file mode 100644 index 0800c5f3..00000000 --- a/watch-library/include/instance/supc.h +++ /dev/null @@ -1,65 +0,0 @@ -/** - * \file - * - * \brief Instance description for SUPC - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_SUPC_INSTANCE_ -#define _SAML22_SUPC_INSTANCE_ - -/* ========== Register definition for SUPC peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_SUPC_INTENCLR (0x40001800) /**< \brief (SUPC) Interrupt Enable Clear */ -#define REG_SUPC_INTENSET (0x40001804) /**< \brief (SUPC) Interrupt Enable Set */ -#define REG_SUPC_INTFLAG (0x40001808) /**< \brief (SUPC) Interrupt Flag Status and Clear */ -#define REG_SUPC_STATUS (0x4000180C) /**< \brief (SUPC) Power and Clocks Status */ -#define REG_SUPC_BOD33 (0x40001810) /**< \brief (SUPC) BOD33 Control */ -#define REG_SUPC_BOD12 (0x40001814) /**< \brief (SUPC) BOD12 Control */ -#define REG_SUPC_VREG (0x40001818) /**< \brief (SUPC) VREG Control */ -#define REG_SUPC_VREF (0x4000181C) /**< \brief (SUPC) VREF Control */ -#define REG_SUPC_BBPS (0x40001820) /**< \brief (SUPC) Battery Backup Power Switch */ -#define REG_SUPC_BKOUT (0x40001824) /**< \brief (SUPC) Backup Output Control */ -#define REG_SUPC_BKIN (0x40001828) /**< \brief (SUPC) Backup Input Control */ -#else -#define REG_SUPC_INTENCLR (*(RwReg *)0x40001800UL) /**< \brief (SUPC) Interrupt Enable Clear */ -#define REG_SUPC_INTENSET (*(RwReg *)0x40001804UL) /**< \brief (SUPC) Interrupt Enable Set */ -#define REG_SUPC_INTFLAG (*(RwReg *)0x40001808UL) /**< \brief (SUPC) Interrupt Flag Status and Clear */ -#define REG_SUPC_STATUS (*(RoReg *)0x4000180CUL) /**< \brief (SUPC) Power and Clocks Status */ -#define REG_SUPC_BOD33 (*(RwReg *)0x40001810UL) /**< \brief (SUPC) BOD33 Control */ -#define REG_SUPC_BOD12 (*(RwReg *)0x40001814UL) /**< \brief (SUPC) BOD12 Control */ -#define REG_SUPC_VREG (*(RwReg *)0x40001818UL) /**< \brief (SUPC) VREG Control */ -#define REG_SUPC_VREF (*(RwReg *)0x4000181CUL) /**< \brief (SUPC) VREF Control */ -#define REG_SUPC_BBPS (*(RwReg *)0x40001820UL) /**< \brief (SUPC) Battery Backup Power Switch */ -#define REG_SUPC_BKOUT (*(RwReg *)0x40001824UL) /**< \brief (SUPC) Backup Output Control */ -#define REG_SUPC_BKIN (*(RoReg *)0x40001828UL) /**< \brief (SUPC) Backup Input Control */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for SUPC peripheral ========== */ -#define SUPC_BOD12_CALIB_MSB 5 -#define SUPC_BOD33_CALIB_MSB 5 -#define SUPC_OUT_NUM_MSB 1 // MSB of backup output pad Number - -#endif /* _SAML22_SUPC_INSTANCE_ */ diff --git a/watch-library/include/instance/tc0.h b/watch-library/include/instance/tc0.h deleted file mode 100644 index a50b87e9..00000000 --- a/watch-library/include/instance/tc0.h +++ /dev/null @@ -1,109 +0,0 @@ -/** - * \file - * - * \brief Instance description for TC0 - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_TC0_INSTANCE_ -#define _SAML22_TC0_INSTANCE_ - -/* ========== Register definition for TC0 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_TC0_CTRLA (0x42002000) /**< \brief (TC0) Control A */ -#define REG_TC0_CTRLBCLR (0x42002004) /**< \brief (TC0) Control B Clear */ -#define REG_TC0_CTRLBSET (0x42002005) /**< \brief (TC0) Control B Set */ -#define REG_TC0_EVCTRL (0x42002006) /**< \brief (TC0) Event Control */ -#define REG_TC0_INTENCLR (0x42002008) /**< \brief (TC0) Interrupt Enable Clear */ -#define REG_TC0_INTENSET (0x42002009) /**< \brief (TC0) Interrupt Enable Set */ -#define REG_TC0_INTFLAG (0x4200200A) /**< \brief (TC0) Interrupt Flag Status and Clear */ -#define REG_TC0_STATUS (0x4200200B) /**< \brief (TC0) Status */ -#define REG_TC0_WAVE (0x4200200C) /**< \brief (TC0) Waveform Generation Control */ -#define REG_TC0_DRVCTRL (0x4200200D) /**< \brief (TC0) Control C */ -#define REG_TC0_DBGCTRL (0x4200200F) /**< \brief (TC0) Debug Control */ -#define REG_TC0_SYNCBUSY (0x42002010) /**< \brief (TC0) Synchronization Status */ -#define REG_TC0_COUNT16_COUNT (0x42002014) /**< \brief (TC0) COUNT16 Count */ -#define REG_TC0_COUNT16_CC0 (0x4200201C) /**< \brief (TC0) COUNT16 Compare and Capture 0 */ -#define REG_TC0_COUNT16_CC1 (0x4200201E) /**< \brief (TC0) COUNT16 Compare and Capture 1 */ -#define REG_TC0_COUNT16_CCBUF0 (0x42002030) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 0 */ -#define REG_TC0_COUNT16_CCBUF1 (0x42002032) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 1 */ -#define REG_TC0_COUNT32_COUNT (0x42002014) /**< \brief (TC0) COUNT32 Count */ -#define REG_TC0_COUNT32_CC0 (0x4200201C) /**< \brief (TC0) COUNT32 Compare and Capture 0 */ -#define REG_TC0_COUNT32_CC1 (0x42002020) /**< \brief (TC0) COUNT32 Compare and Capture 1 */ -#define REG_TC0_COUNT32_CCBUF0 (0x42002030) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 0 */ -#define REG_TC0_COUNT32_CCBUF1 (0x42002034) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 1 */ -#define REG_TC0_COUNT8_COUNT (0x42002014) /**< \brief (TC0) COUNT8 Count */ -#define REG_TC0_COUNT8_PER (0x4200201B) /**< \brief (TC0) COUNT8 Period */ -#define REG_TC0_COUNT8_CC0 (0x4200201C) /**< \brief (TC0) COUNT8 Compare and Capture 0 */ -#define REG_TC0_COUNT8_CC1 (0x4200201D) /**< \brief (TC0) COUNT8 Compare and Capture 1 */ -#define REG_TC0_COUNT8_PERBUF (0x4200202F) /**< \brief (TC0) COUNT8 Period Buffer */ -#define REG_TC0_COUNT8_CCBUF0 (0x42002030) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 0 */ -#define REG_TC0_COUNT8_CCBUF1 (0x42002031) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 1 */ -#else -#define REG_TC0_CTRLA (*(RwReg *)0x42002000UL) /**< \brief (TC0) Control A */ -#define REG_TC0_CTRLBCLR (*(RwReg8 *)0x42002004UL) /**< \brief (TC0) Control B Clear */ -#define REG_TC0_CTRLBSET (*(RwReg8 *)0x42002005UL) /**< \brief (TC0) Control B Set */ -#define REG_TC0_EVCTRL (*(RwReg16*)0x42002006UL) /**< \brief (TC0) Event Control */ -#define REG_TC0_INTENCLR (*(RwReg8 *)0x42002008UL) /**< \brief (TC0) Interrupt Enable Clear */ -#define REG_TC0_INTENSET (*(RwReg8 *)0x42002009UL) /**< \brief (TC0) Interrupt Enable Set */ -#define REG_TC0_INTFLAG (*(RwReg8 *)0x4200200AUL) /**< \brief (TC0) Interrupt Flag Status and Clear */ -#define REG_TC0_STATUS (*(RwReg8 *)0x4200200BUL) /**< \brief (TC0) Status */ -#define REG_TC0_WAVE (*(RwReg8 *)0x4200200CUL) /**< \brief (TC0) Waveform Generation Control */ -#define REG_TC0_DRVCTRL (*(RwReg8 *)0x4200200DUL) /**< \brief (TC0) Control C */ -#define REG_TC0_DBGCTRL (*(RwReg8 *)0x4200200FUL) /**< \brief (TC0) Debug Control */ -#define REG_TC0_SYNCBUSY (*(RoReg *)0x42002010UL) /**< \brief (TC0) Synchronization Status */ -#define REG_TC0_COUNT16_COUNT (*(RwReg16*)0x42002014UL) /**< \brief (TC0) COUNT16 Count */ -#define REG_TC0_COUNT16_CC0 (*(RwReg16*)0x4200201CUL) /**< \brief (TC0) COUNT16 Compare and Capture 0 */ -#define REG_TC0_COUNT16_CC1 (*(RwReg16*)0x4200201EUL) /**< \brief (TC0) COUNT16 Compare and Capture 1 */ -#define REG_TC0_COUNT16_CCBUF0 (*(RwReg16*)0x42002030UL) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 0 */ -#define REG_TC0_COUNT16_CCBUF1 (*(RwReg16*)0x42002032UL) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 1 */ -#define REG_TC0_COUNT32_COUNT (*(RwReg *)0x42002014UL) /**< \brief (TC0) COUNT32 Count */ -#define REG_TC0_COUNT32_CC0 (*(RwReg *)0x4200201CUL) /**< \brief (TC0) COUNT32 Compare and Capture 0 */ -#define REG_TC0_COUNT32_CC1 (*(RwReg *)0x42002020UL) /**< \brief (TC0) COUNT32 Compare and Capture 1 */ -#define REG_TC0_COUNT32_CCBUF0 (*(RwReg *)0x42002030UL) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 0 */ -#define REG_TC0_COUNT32_CCBUF1 (*(RwReg *)0x42002034UL) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 1 */ -#define REG_TC0_COUNT8_COUNT (*(RwReg8 *)0x42002014UL) /**< \brief (TC0) COUNT8 Count */ -#define REG_TC0_COUNT8_PER (*(RwReg8 *)0x4200201BUL) /**< \brief (TC0) COUNT8 Period */ -#define REG_TC0_COUNT8_CC0 (*(RwReg8 *)0x4200201CUL) /**< \brief (TC0) COUNT8 Compare and Capture 0 */ -#define REG_TC0_COUNT8_CC1 (*(RwReg8 *)0x4200201DUL) /**< \brief (TC0) COUNT8 Compare and Capture 1 */ -#define REG_TC0_COUNT8_PERBUF (*(RwReg8 *)0x4200202FUL) /**< \brief (TC0) COUNT8 Period Buffer */ -#define REG_TC0_COUNT8_CCBUF0 (*(RwReg8 *)0x42002030UL) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 0 */ -#define REG_TC0_COUNT8_CCBUF1 (*(RwReg8 *)0x42002031UL) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 1 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for TC0 peripheral ========== */ -#define TC0_CC_NUM 2 -#define TC0_DMAC_ID_MC_0 20 -#define TC0_DMAC_ID_MC_1 21 -#define TC0_DMAC_ID_MC_LSB 20 -#define TC0_DMAC_ID_MC_MSB 21 -#define TC0_DMAC_ID_MC_SIZE 2 -#define TC0_DMAC_ID_OVF 19 // Indexes of DMA Overflow trigger -#define TC0_EXT 0 -#define TC0_GCLK_ID 23 -#define TC0_MASTER 1 -#define TC0_OW_NUM 2 - -#endif /* _SAML22_TC0_INSTANCE_ */ diff --git a/watch-library/include/instance/tc1.h b/watch-library/include/instance/tc1.h deleted file mode 100644 index 9acada8a..00000000 --- a/watch-library/include/instance/tc1.h +++ /dev/null @@ -1,109 +0,0 @@ -/** - * \file - * - * \brief Instance description for TC1 - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_TC1_INSTANCE_ -#define _SAML22_TC1_INSTANCE_ - -/* ========== Register definition for TC1 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_TC1_CTRLA (0x42002400) /**< \brief (TC1) Control A */ -#define REG_TC1_CTRLBCLR (0x42002404) /**< \brief (TC1) Control B Clear */ -#define REG_TC1_CTRLBSET (0x42002405) /**< \brief (TC1) Control B Set */ -#define REG_TC1_EVCTRL (0x42002406) /**< \brief (TC1) Event Control */ -#define REG_TC1_INTENCLR (0x42002408) /**< \brief (TC1) Interrupt Enable Clear */ -#define REG_TC1_INTENSET (0x42002409) /**< \brief (TC1) Interrupt Enable Set */ -#define REG_TC1_INTFLAG (0x4200240A) /**< \brief (TC1) Interrupt Flag Status and Clear */ -#define REG_TC1_STATUS (0x4200240B) /**< \brief (TC1) Status */ -#define REG_TC1_WAVE (0x4200240C) /**< \brief (TC1) Waveform Generation Control */ -#define REG_TC1_DRVCTRL (0x4200240D) /**< \brief (TC1) Control C */ -#define REG_TC1_DBGCTRL (0x4200240F) /**< \brief (TC1) Debug Control */ -#define REG_TC1_SYNCBUSY (0x42002410) /**< \brief (TC1) Synchronization Status */ -#define REG_TC1_COUNT16_COUNT (0x42002414) /**< \brief (TC1) COUNT16 Count */ -#define REG_TC1_COUNT16_CC0 (0x4200241C) /**< \brief (TC1) COUNT16 Compare and Capture 0 */ -#define REG_TC1_COUNT16_CC1 (0x4200241E) /**< \brief (TC1) COUNT16 Compare and Capture 1 */ -#define REG_TC1_COUNT16_CCBUF0 (0x42002430) /**< \brief (TC1) COUNT16 Compare and Capture Buffer 0 */ -#define REG_TC1_COUNT16_CCBUF1 (0x42002432) /**< \brief (TC1) COUNT16 Compare and Capture Buffer 1 */ -#define REG_TC1_COUNT32_COUNT (0x42002414) /**< \brief (TC1) COUNT32 Count */ -#define REG_TC1_COUNT32_CC0 (0x4200241C) /**< \brief (TC1) COUNT32 Compare and Capture 0 */ -#define REG_TC1_COUNT32_CC1 (0x42002420) /**< \brief (TC1) COUNT32 Compare and Capture 1 */ -#define REG_TC1_COUNT32_CCBUF0 (0x42002430) /**< \brief (TC1) COUNT32 Compare and Capture Buffer 0 */ -#define REG_TC1_COUNT32_CCBUF1 (0x42002434) /**< \brief (TC1) COUNT32 Compare and Capture Buffer 1 */ -#define REG_TC1_COUNT8_COUNT (0x42002414) /**< \brief (TC1) COUNT8 Count */ -#define REG_TC1_COUNT8_PER (0x4200241B) /**< \brief (TC1) COUNT8 Period */ -#define REG_TC1_COUNT8_CC0 (0x4200241C) /**< \brief (TC1) COUNT8 Compare and Capture 0 */ -#define REG_TC1_COUNT8_CC1 (0x4200241D) /**< \brief (TC1) COUNT8 Compare and Capture 1 */ -#define REG_TC1_COUNT8_PERBUF (0x4200242F) /**< \brief (TC1) COUNT8 Period Buffer */ -#define REG_TC1_COUNT8_CCBUF0 (0x42002430) /**< \brief (TC1) COUNT8 Compare and Capture Buffer 0 */ -#define REG_TC1_COUNT8_CCBUF1 (0x42002431) /**< \brief (TC1) COUNT8 Compare and Capture Buffer 1 */ -#else -#define REG_TC1_CTRLA (*(RwReg *)0x42002400UL) /**< \brief (TC1) Control A */ -#define REG_TC1_CTRLBCLR (*(RwReg8 *)0x42002404UL) /**< \brief (TC1) Control B Clear */ -#define REG_TC1_CTRLBSET (*(RwReg8 *)0x42002405UL) /**< \brief (TC1) Control B Set */ -#define REG_TC1_EVCTRL (*(RwReg16*)0x42002406UL) /**< \brief (TC1) Event Control */ -#define REG_TC1_INTENCLR (*(RwReg8 *)0x42002408UL) /**< \brief (TC1) Interrupt Enable Clear */ -#define REG_TC1_INTENSET (*(RwReg8 *)0x42002409UL) /**< \brief (TC1) Interrupt Enable Set */ -#define REG_TC1_INTFLAG (*(RwReg8 *)0x4200240AUL) /**< \brief (TC1) Interrupt Flag Status and Clear */ -#define REG_TC1_STATUS (*(RwReg8 *)0x4200240BUL) /**< \brief (TC1) Status */ -#define REG_TC1_WAVE (*(RwReg8 *)0x4200240CUL) /**< \brief (TC1) Waveform Generation Control */ -#define REG_TC1_DRVCTRL (*(RwReg8 *)0x4200240DUL) /**< \brief (TC1) Control C */ -#define REG_TC1_DBGCTRL (*(RwReg8 *)0x4200240FUL) /**< \brief (TC1) Debug Control */ -#define REG_TC1_SYNCBUSY (*(RoReg *)0x42002410UL) /**< \brief (TC1) Synchronization Status */ -#define REG_TC1_COUNT16_COUNT (*(RwReg16*)0x42002414UL) /**< \brief (TC1) COUNT16 Count */ -#define REG_TC1_COUNT16_CC0 (*(RwReg16*)0x4200241CUL) /**< \brief (TC1) COUNT16 Compare and Capture 0 */ -#define REG_TC1_COUNT16_CC1 (*(RwReg16*)0x4200241EUL) /**< \brief (TC1) COUNT16 Compare and Capture 1 */ -#define REG_TC1_COUNT16_CCBUF0 (*(RwReg16*)0x42002430UL) /**< \brief (TC1) COUNT16 Compare and Capture Buffer 0 */ -#define REG_TC1_COUNT16_CCBUF1 (*(RwReg16*)0x42002432UL) /**< \brief (TC1) COUNT16 Compare and Capture Buffer 1 */ -#define REG_TC1_COUNT32_COUNT (*(RwReg *)0x42002414UL) /**< \brief (TC1) COUNT32 Count */ -#define REG_TC1_COUNT32_CC0 (*(RwReg *)0x4200241CUL) /**< \brief (TC1) COUNT32 Compare and Capture 0 */ -#define REG_TC1_COUNT32_CC1 (*(RwReg *)0x42002420UL) /**< \brief (TC1) COUNT32 Compare and Capture 1 */ -#define REG_TC1_COUNT32_CCBUF0 (*(RwReg *)0x42002430UL) /**< \brief (TC1) COUNT32 Compare and Capture Buffer 0 */ -#define REG_TC1_COUNT32_CCBUF1 (*(RwReg *)0x42002434UL) /**< \brief (TC1) COUNT32 Compare and Capture Buffer 1 */ -#define REG_TC1_COUNT8_COUNT (*(RwReg8 *)0x42002414UL) /**< \brief (TC1) COUNT8 Count */ -#define REG_TC1_COUNT8_PER (*(RwReg8 *)0x4200241BUL) /**< \brief (TC1) COUNT8 Period */ -#define REG_TC1_COUNT8_CC0 (*(RwReg8 *)0x4200241CUL) /**< \brief (TC1) COUNT8 Compare and Capture 0 */ -#define REG_TC1_COUNT8_CC1 (*(RwReg8 *)0x4200241DUL) /**< \brief (TC1) COUNT8 Compare and Capture 1 */ -#define REG_TC1_COUNT8_PERBUF (*(RwReg8 *)0x4200242FUL) /**< \brief (TC1) COUNT8 Period Buffer */ -#define REG_TC1_COUNT8_CCBUF0 (*(RwReg8 *)0x42002430UL) /**< \brief (TC1) COUNT8 Compare and Capture Buffer 0 */ -#define REG_TC1_COUNT8_CCBUF1 (*(RwReg8 *)0x42002431UL) /**< \brief (TC1) COUNT8 Compare and Capture Buffer 1 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for TC1 peripheral ========== */ -#define TC1_CC_NUM 2 -#define TC1_DMAC_ID_MC_0 23 -#define TC1_DMAC_ID_MC_1 24 -#define TC1_DMAC_ID_MC_LSB 23 -#define TC1_DMAC_ID_MC_MSB 24 -#define TC1_DMAC_ID_MC_SIZE 2 -#define TC1_DMAC_ID_OVF 22 // Indexes of DMA Overflow trigger -#define TC1_EXT 0 -#define TC1_GCLK_ID 23 -#define TC1_MASTER 0 -#define TC1_OW_NUM 2 - -#endif /* _SAML22_TC1_INSTANCE_ */ diff --git a/watch-library/include/instance/tc2.h b/watch-library/include/instance/tc2.h deleted file mode 100644 index 13b8fb2a..00000000 --- a/watch-library/include/instance/tc2.h +++ /dev/null @@ -1,109 +0,0 @@ -/** - * \file - * - * \brief Instance description for TC2 - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_TC2_INSTANCE_ -#define _SAML22_TC2_INSTANCE_ - -/* ========== Register definition for TC2 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_TC2_CTRLA (0x42002800) /**< \brief (TC2) Control A */ -#define REG_TC2_CTRLBCLR (0x42002804) /**< \brief (TC2) Control B Clear */ -#define REG_TC2_CTRLBSET (0x42002805) /**< \brief (TC2) Control B Set */ -#define REG_TC2_EVCTRL (0x42002806) /**< \brief (TC2) Event Control */ -#define REG_TC2_INTENCLR (0x42002808) /**< \brief (TC2) Interrupt Enable Clear */ -#define REG_TC2_INTENSET (0x42002809) /**< \brief (TC2) Interrupt Enable Set */ -#define REG_TC2_INTFLAG (0x4200280A) /**< \brief (TC2) Interrupt Flag Status and Clear */ -#define REG_TC2_STATUS (0x4200280B) /**< \brief (TC2) Status */ -#define REG_TC2_WAVE (0x4200280C) /**< \brief (TC2) Waveform Generation Control */ -#define REG_TC2_DRVCTRL (0x4200280D) /**< \brief (TC2) Control C */ -#define REG_TC2_DBGCTRL (0x4200280F) /**< \brief (TC2) Debug Control */ -#define REG_TC2_SYNCBUSY (0x42002810) /**< \brief (TC2) Synchronization Status */ -#define REG_TC2_COUNT16_COUNT (0x42002814) /**< \brief (TC2) COUNT16 Count */ -#define REG_TC2_COUNT16_CC0 (0x4200281C) /**< \brief (TC2) COUNT16 Compare and Capture 0 */ -#define REG_TC2_COUNT16_CC1 (0x4200281E) /**< \brief (TC2) COUNT16 Compare and Capture 1 */ -#define REG_TC2_COUNT16_CCBUF0 (0x42002830) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 0 */ -#define REG_TC2_COUNT16_CCBUF1 (0x42002832) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 1 */ -#define REG_TC2_COUNT32_COUNT (0x42002814) /**< \brief (TC2) COUNT32 Count */ -#define REG_TC2_COUNT32_CC0 (0x4200281C) /**< \brief (TC2) COUNT32 Compare and Capture 0 */ -#define REG_TC2_COUNT32_CC1 (0x42002820) /**< \brief (TC2) COUNT32 Compare and Capture 1 */ -#define REG_TC2_COUNT32_CCBUF0 (0x42002830) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 0 */ -#define REG_TC2_COUNT32_CCBUF1 (0x42002834) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 1 */ -#define REG_TC2_COUNT8_COUNT (0x42002814) /**< \brief (TC2) COUNT8 Count */ -#define REG_TC2_COUNT8_PER (0x4200281B) /**< \brief (TC2) COUNT8 Period */ -#define REG_TC2_COUNT8_CC0 (0x4200281C) /**< \brief (TC2) COUNT8 Compare and Capture 0 */ -#define REG_TC2_COUNT8_CC1 (0x4200281D) /**< \brief (TC2) COUNT8 Compare and Capture 1 */ -#define REG_TC2_COUNT8_PERBUF (0x4200282F) /**< \brief (TC2) COUNT8 Period Buffer */ -#define REG_TC2_COUNT8_CCBUF0 (0x42002830) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 0 */ -#define REG_TC2_COUNT8_CCBUF1 (0x42002831) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 1 */ -#else -#define REG_TC2_CTRLA (*(RwReg *)0x42002800UL) /**< \brief (TC2) Control A */ -#define REG_TC2_CTRLBCLR (*(RwReg8 *)0x42002804UL) /**< \brief (TC2) Control B Clear */ -#define REG_TC2_CTRLBSET (*(RwReg8 *)0x42002805UL) /**< \brief (TC2) Control B Set */ -#define REG_TC2_EVCTRL (*(RwReg16*)0x42002806UL) /**< \brief (TC2) Event Control */ -#define REG_TC2_INTENCLR (*(RwReg8 *)0x42002808UL) /**< \brief (TC2) Interrupt Enable Clear */ -#define REG_TC2_INTENSET (*(RwReg8 *)0x42002809UL) /**< \brief (TC2) Interrupt Enable Set */ -#define REG_TC2_INTFLAG (*(RwReg8 *)0x4200280AUL) /**< \brief (TC2) Interrupt Flag Status and Clear */ -#define REG_TC2_STATUS (*(RwReg8 *)0x4200280BUL) /**< \brief (TC2) Status */ -#define REG_TC2_WAVE (*(RwReg8 *)0x4200280CUL) /**< \brief (TC2) Waveform Generation Control */ -#define REG_TC2_DRVCTRL (*(RwReg8 *)0x4200280DUL) /**< \brief (TC2) Control C */ -#define REG_TC2_DBGCTRL (*(RwReg8 *)0x4200280FUL) /**< \brief (TC2) Debug Control */ -#define REG_TC2_SYNCBUSY (*(RoReg *)0x42002810UL) /**< \brief (TC2) Synchronization Status */ -#define REG_TC2_COUNT16_COUNT (*(RwReg16*)0x42002814UL) /**< \brief (TC2) COUNT16 Count */ -#define REG_TC2_COUNT16_CC0 (*(RwReg16*)0x4200281CUL) /**< \brief (TC2) COUNT16 Compare and Capture 0 */ -#define REG_TC2_COUNT16_CC1 (*(RwReg16*)0x4200281EUL) /**< \brief (TC2) COUNT16 Compare and Capture 1 */ -#define REG_TC2_COUNT16_CCBUF0 (*(RwReg16*)0x42002830UL) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 0 */ -#define REG_TC2_COUNT16_CCBUF1 (*(RwReg16*)0x42002832UL) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 1 */ -#define REG_TC2_COUNT32_COUNT (*(RwReg *)0x42002814UL) /**< \brief (TC2) COUNT32 Count */ -#define REG_TC2_COUNT32_CC0 (*(RwReg *)0x4200281CUL) /**< \brief (TC2) COUNT32 Compare and Capture 0 */ -#define REG_TC2_COUNT32_CC1 (*(RwReg *)0x42002820UL) /**< \brief (TC2) COUNT32 Compare and Capture 1 */ -#define REG_TC2_COUNT32_CCBUF0 (*(RwReg *)0x42002830UL) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 0 */ -#define REG_TC2_COUNT32_CCBUF1 (*(RwReg *)0x42002834UL) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 1 */ -#define REG_TC2_COUNT8_COUNT (*(RwReg8 *)0x42002814UL) /**< \brief (TC2) COUNT8 Count */ -#define REG_TC2_COUNT8_PER (*(RwReg8 *)0x4200281BUL) /**< \brief (TC2) COUNT8 Period */ -#define REG_TC2_COUNT8_CC0 (*(RwReg8 *)0x4200281CUL) /**< \brief (TC2) COUNT8 Compare and Capture 0 */ -#define REG_TC2_COUNT8_CC1 (*(RwReg8 *)0x4200281DUL) /**< \brief (TC2) COUNT8 Compare and Capture 1 */ -#define REG_TC2_COUNT8_PERBUF (*(RwReg8 *)0x4200282FUL) /**< \brief (TC2) COUNT8 Period Buffer */ -#define REG_TC2_COUNT8_CCBUF0 (*(RwReg8 *)0x42002830UL) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 0 */ -#define REG_TC2_COUNT8_CCBUF1 (*(RwReg8 *)0x42002831UL) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 1 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for TC2 peripheral ========== */ -#define TC2_CC_NUM 2 -#define TC2_DMAC_ID_MC_0 26 -#define TC2_DMAC_ID_MC_1 27 -#define TC2_DMAC_ID_MC_LSB 26 -#define TC2_DMAC_ID_MC_MSB 27 -#define TC2_DMAC_ID_MC_SIZE 2 -#define TC2_DMAC_ID_OVF 25 // Indexes of DMA Overflow trigger -#define TC2_EXT 0 -#define TC2_GCLK_ID 24 -#define TC2_MASTER 1 -#define TC2_OW_NUM 2 - -#endif /* _SAML22_TC2_INSTANCE_ */ diff --git a/watch-library/include/instance/tc3.h b/watch-library/include/instance/tc3.h deleted file mode 100644 index 7555903a..00000000 --- a/watch-library/include/instance/tc3.h +++ /dev/null @@ -1,109 +0,0 @@ -/** - * \file - * - * \brief Instance description for TC3 - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_TC3_INSTANCE_ -#define _SAML22_TC3_INSTANCE_ - -/* ========== Register definition for TC3 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_TC3_CTRLA (0x42002C00) /**< \brief (TC3) Control A */ -#define REG_TC3_CTRLBCLR (0x42002C04) /**< \brief (TC3) Control B Clear */ -#define REG_TC3_CTRLBSET (0x42002C05) /**< \brief (TC3) Control B Set */ -#define REG_TC3_EVCTRL (0x42002C06) /**< \brief (TC3) Event Control */ -#define REG_TC3_INTENCLR (0x42002C08) /**< \brief (TC3) Interrupt Enable Clear */ -#define REG_TC3_INTENSET (0x42002C09) /**< \brief (TC3) Interrupt Enable Set */ -#define REG_TC3_INTFLAG (0x42002C0A) /**< \brief (TC3) Interrupt Flag Status and Clear */ -#define REG_TC3_STATUS (0x42002C0B) /**< \brief (TC3) Status */ -#define REG_TC3_WAVE (0x42002C0C) /**< \brief (TC3) Waveform Generation Control */ -#define REG_TC3_DRVCTRL (0x42002C0D) /**< \brief (TC3) Control C */ -#define REG_TC3_DBGCTRL (0x42002C0F) /**< \brief (TC3) Debug Control */ -#define REG_TC3_SYNCBUSY (0x42002C10) /**< \brief (TC3) Synchronization Status */ -#define REG_TC3_COUNT16_COUNT (0x42002C14) /**< \brief (TC3) COUNT16 Count */ -#define REG_TC3_COUNT16_CC0 (0x42002C1C) /**< \brief (TC3) COUNT16 Compare and Capture 0 */ -#define REG_TC3_COUNT16_CC1 (0x42002C1E) /**< \brief (TC3) COUNT16 Compare and Capture 1 */ -#define REG_TC3_COUNT16_CCBUF0 (0x42002C30) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 0 */ -#define REG_TC3_COUNT16_CCBUF1 (0x42002C32) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 1 */ -#define REG_TC3_COUNT32_COUNT (0x42002C14) /**< \brief (TC3) COUNT32 Count */ -#define REG_TC3_COUNT32_CC0 (0x42002C1C) /**< \brief (TC3) COUNT32 Compare and Capture 0 */ -#define REG_TC3_COUNT32_CC1 (0x42002C20) /**< \brief (TC3) COUNT32 Compare and Capture 1 */ -#define REG_TC3_COUNT32_CCBUF0 (0x42002C30) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 0 */ -#define REG_TC3_COUNT32_CCBUF1 (0x42002C34) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 1 */ -#define REG_TC3_COUNT8_COUNT (0x42002C14) /**< \brief (TC3) COUNT8 Count */ -#define REG_TC3_COUNT8_PER (0x42002C1B) /**< \brief (TC3) COUNT8 Period */ -#define REG_TC3_COUNT8_CC0 (0x42002C1C) /**< \brief (TC3) COUNT8 Compare and Capture 0 */ -#define REG_TC3_COUNT8_CC1 (0x42002C1D) /**< \brief (TC3) COUNT8 Compare and Capture 1 */ -#define REG_TC3_COUNT8_PERBUF (0x42002C2F) /**< \brief (TC3) COUNT8 Period Buffer */ -#define REG_TC3_COUNT8_CCBUF0 (0x42002C30) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 0 */ -#define REG_TC3_COUNT8_CCBUF1 (0x42002C31) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 1 */ -#else -#define REG_TC3_CTRLA (*(RwReg *)0x42002C00UL) /**< \brief (TC3) Control A */ -#define REG_TC3_CTRLBCLR (*(RwReg8 *)0x42002C04UL) /**< \brief (TC3) Control B Clear */ -#define REG_TC3_CTRLBSET (*(RwReg8 *)0x42002C05UL) /**< \brief (TC3) Control B Set */ -#define REG_TC3_EVCTRL (*(RwReg16*)0x42002C06UL) /**< \brief (TC3) Event Control */ -#define REG_TC3_INTENCLR (*(RwReg8 *)0x42002C08UL) /**< \brief (TC3) Interrupt Enable Clear */ -#define REG_TC3_INTENSET (*(RwReg8 *)0x42002C09UL) /**< \brief (TC3) Interrupt Enable Set */ -#define REG_TC3_INTFLAG (*(RwReg8 *)0x42002C0AUL) /**< \brief (TC3) Interrupt Flag Status and Clear */ -#define REG_TC3_STATUS (*(RwReg8 *)0x42002C0BUL) /**< \brief (TC3) Status */ -#define REG_TC3_WAVE (*(RwReg8 *)0x42002C0CUL) /**< \brief (TC3) Waveform Generation Control */ -#define REG_TC3_DRVCTRL (*(RwReg8 *)0x42002C0DUL) /**< \brief (TC3) Control C */ -#define REG_TC3_DBGCTRL (*(RwReg8 *)0x42002C0FUL) /**< \brief (TC3) Debug Control */ -#define REG_TC3_SYNCBUSY (*(RoReg *)0x42002C10UL) /**< \brief (TC3) Synchronization Status */ -#define REG_TC3_COUNT16_COUNT (*(RwReg16*)0x42002C14UL) /**< \brief (TC3) COUNT16 Count */ -#define REG_TC3_COUNT16_CC0 (*(RwReg16*)0x42002C1CUL) /**< \brief (TC3) COUNT16 Compare and Capture 0 */ -#define REG_TC3_COUNT16_CC1 (*(RwReg16*)0x42002C1EUL) /**< \brief (TC3) COUNT16 Compare and Capture 1 */ -#define REG_TC3_COUNT16_CCBUF0 (*(RwReg16*)0x42002C30UL) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 0 */ -#define REG_TC3_COUNT16_CCBUF1 (*(RwReg16*)0x42002C32UL) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 1 */ -#define REG_TC3_COUNT32_COUNT (*(RwReg *)0x42002C14UL) /**< \brief (TC3) COUNT32 Count */ -#define REG_TC3_COUNT32_CC0 (*(RwReg *)0x42002C1CUL) /**< \brief (TC3) COUNT32 Compare and Capture 0 */ -#define REG_TC3_COUNT32_CC1 (*(RwReg *)0x42002C20UL) /**< \brief (TC3) COUNT32 Compare and Capture 1 */ -#define REG_TC3_COUNT32_CCBUF0 (*(RwReg *)0x42002C30UL) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 0 */ -#define REG_TC3_COUNT32_CCBUF1 (*(RwReg *)0x42002C34UL) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 1 */ -#define REG_TC3_COUNT8_COUNT (*(RwReg8 *)0x42002C14UL) /**< \brief (TC3) COUNT8 Count */ -#define REG_TC3_COUNT8_PER (*(RwReg8 *)0x42002C1BUL) /**< \brief (TC3) COUNT8 Period */ -#define REG_TC3_COUNT8_CC0 (*(RwReg8 *)0x42002C1CUL) /**< \brief (TC3) COUNT8 Compare and Capture 0 */ -#define REG_TC3_COUNT8_CC1 (*(RwReg8 *)0x42002C1DUL) /**< \brief (TC3) COUNT8 Compare and Capture 1 */ -#define REG_TC3_COUNT8_PERBUF (*(RwReg8 *)0x42002C2FUL) /**< \brief (TC3) COUNT8 Period Buffer */ -#define REG_TC3_COUNT8_CCBUF0 (*(RwReg8 *)0x42002C30UL) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 0 */ -#define REG_TC3_COUNT8_CCBUF1 (*(RwReg8 *)0x42002C31UL) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 1 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for TC3 peripheral ========== */ -#define TC3_CC_NUM 2 -#define TC3_DMAC_ID_MC_0 29 -#define TC3_DMAC_ID_MC_1 30 -#define TC3_DMAC_ID_MC_LSB 29 -#define TC3_DMAC_ID_MC_MSB 30 -#define TC3_DMAC_ID_MC_SIZE 2 -#define TC3_DMAC_ID_OVF 28 // Indexes of DMA Overflow trigger -#define TC3_EXT 0 -#define TC3_GCLK_ID 24 -#define TC3_MASTER 0 -#define TC3_OW_NUM 2 - -#endif /* _SAML22_TC3_INSTANCE_ */ diff --git a/watch-library/include/instance/tcc0.h b/watch-library/include/instance/tcc0.h deleted file mode 100644 index e5567d45..00000000 --- a/watch-library/include/instance/tcc0.h +++ /dev/null @@ -1,115 +0,0 @@ -/** - * \file - * - * \brief Instance description for TCC0 - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_TCC0_INSTANCE_ -#define _SAML22_TCC0_INSTANCE_ - -/* ========== Register definition for TCC0 peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_TCC0_CTRLA (0x42001C00) /**< \brief (TCC0) Control A */ -#define REG_TCC0_CTRLBCLR (0x42001C04) /**< \brief (TCC0) Control B Clear */ -#define REG_TCC0_CTRLBSET (0x42001C05) /**< \brief (TCC0) Control B Set */ -#define REG_TCC0_SYNCBUSY (0x42001C08) /**< \brief (TCC0) Synchronization Busy */ -#define REG_TCC0_FCTRLA (0x42001C0C) /**< \brief (TCC0) Recoverable Fault A Configuration */ -#define REG_TCC0_FCTRLB (0x42001C10) /**< \brief (TCC0) Recoverable Fault B Configuration */ -#define REG_TCC0_WEXCTRL (0x42001C14) /**< \brief (TCC0) Waveform Extension Configuration */ -#define REG_TCC0_DRVCTRL (0x42001C18) /**< \brief (TCC0) Driver Control */ -#define REG_TCC0_DBGCTRL (0x42001C1E) /**< \brief (TCC0) Debug Control */ -#define REG_TCC0_EVCTRL (0x42001C20) /**< \brief (TCC0) Event Control */ -#define REG_TCC0_INTENCLR (0x42001C24) /**< \brief (TCC0) Interrupt Enable Clear */ -#define REG_TCC0_INTENSET (0x42001C28) /**< \brief (TCC0) Interrupt Enable Set */ -#define REG_TCC0_INTFLAG (0x42001C2C) /**< \brief (TCC0) Interrupt Flag Status and Clear */ -#define REG_TCC0_STATUS (0x42001C30) /**< \brief (TCC0) Status */ -#define REG_TCC0_COUNT (0x42001C34) /**< \brief (TCC0) Count */ -#define REG_TCC0_PATT (0x42001C38) /**< \brief (TCC0) Pattern */ -#define REG_TCC0_WAVE (0x42001C3C) /**< \brief (TCC0) Waveform Control */ -#define REG_TCC0_PER (0x42001C40) /**< \brief (TCC0) Period */ -#define REG_TCC0_CC0 (0x42001C44) /**< \brief (TCC0) Compare and Capture 0 */ -#define REG_TCC0_CC1 (0x42001C48) /**< \brief (TCC0) Compare and Capture 1 */ -#define REG_TCC0_CC2 (0x42001C4C) /**< \brief (TCC0) Compare and Capture 2 */ -#define REG_TCC0_CC3 (0x42001C50) /**< \brief (TCC0) Compare and Capture 3 */ -#define REG_TCC0_PATTBUF (0x42001C64) /**< \brief (TCC0) Pattern Buffer */ -#define REG_TCC0_PERBUF (0x42001C6C) /**< \brief (TCC0) Period Buffer */ -#define REG_TCC0_CCBUF0 (0x42001C70) /**< \brief (TCC0) Compare and Capture Buffer 0 */ -#define REG_TCC0_CCBUF1 (0x42001C74) /**< \brief (TCC0) Compare and Capture Buffer 1 */ -#define REG_TCC0_CCBUF2 (0x42001C78) /**< \brief (TCC0) Compare and Capture Buffer 2 */ -#define REG_TCC0_CCBUF3 (0x42001C7C) /**< \brief (TCC0) Compare and Capture Buffer 3 */ -#else -#define REG_TCC0_CTRLA (*(RwReg *)0x42001C00UL) /**< \brief (TCC0) Control A */ -#define REG_TCC0_CTRLBCLR (*(RwReg8 *)0x42001C04UL) /**< \brief (TCC0) Control B Clear */ -#define REG_TCC0_CTRLBSET (*(RwReg8 *)0x42001C05UL) /**< \brief (TCC0) Control B Set */ -#define REG_TCC0_SYNCBUSY (*(RoReg *)0x42001C08UL) /**< \brief (TCC0) Synchronization Busy */ -#define REG_TCC0_FCTRLA (*(RwReg *)0x42001C0CUL) /**< \brief (TCC0) Recoverable Fault A Configuration */ -#define REG_TCC0_FCTRLB (*(RwReg *)0x42001C10UL) /**< \brief (TCC0) Recoverable Fault B Configuration */ -#define REG_TCC0_WEXCTRL (*(RwReg *)0x42001C14UL) /**< \brief (TCC0) Waveform Extension Configuration */ -#define REG_TCC0_DRVCTRL (*(RwReg *)0x42001C18UL) /**< \brief (TCC0) Driver Control */ -#define REG_TCC0_DBGCTRL (*(RwReg8 *)0x42001C1EUL) /**< \brief (TCC0) Debug Control */ -#define REG_TCC0_EVCTRL (*(RwReg *)0x42001C20UL) /**< \brief (TCC0) Event Control */ -#define REG_TCC0_INTENCLR (*(RwReg *)0x42001C24UL) /**< \brief (TCC0) Interrupt Enable Clear */ -#define REG_TCC0_INTENSET (*(RwReg *)0x42001C28UL) /**< \brief (TCC0) Interrupt Enable Set */ -#define REG_TCC0_INTFLAG (*(RwReg *)0x42001C2CUL) /**< \brief (TCC0) Interrupt Flag Status and Clear */ -#define REG_TCC0_STATUS (*(RwReg *)0x42001C30UL) /**< \brief (TCC0) Status */ -#define REG_TCC0_COUNT (*(RwReg *)0x42001C34UL) /**< \brief (TCC0) Count */ -#define REG_TCC0_PATT (*(RwReg16*)0x42001C38UL) /**< \brief (TCC0) Pattern */ -#define REG_TCC0_WAVE (*(RwReg *)0x42001C3CUL) /**< \brief (TCC0) Waveform Control */ -#define REG_TCC0_PER (*(RwReg *)0x42001C40UL) /**< \brief (TCC0) Period */ -#define REG_TCC0_CC0 (*(RwReg *)0x42001C44UL) /**< \brief (TCC0) Compare and Capture 0 */ -#define REG_TCC0_CC1 (*(RwReg *)0x42001C48UL) /**< \brief (TCC0) Compare and Capture 1 */ -#define REG_TCC0_CC2 (*(RwReg *)0x42001C4CUL) /**< \brief (TCC0) Compare and Capture 2 */ -#define REG_TCC0_CC3 (*(RwReg *)0x42001C50UL) /**< \brief (TCC0) Compare and Capture 3 */ -#define REG_TCC0_PATTBUF (*(RwReg16*)0x42001C64UL) /**< \brief (TCC0) Pattern Buffer */ -#define REG_TCC0_PERBUF (*(RwReg *)0x42001C6CUL) /**< \brief (TCC0) Period Buffer */ -#define REG_TCC0_CCBUF0 (*(RwReg *)0x42001C70UL) /**< \brief (TCC0) Compare and Capture Buffer 0 */ -#define REG_TCC0_CCBUF1 (*(RwReg *)0x42001C74UL) /**< \brief (TCC0) Compare and Capture Buffer 1 */ -#define REG_TCC0_CCBUF2 (*(RwReg *)0x42001C78UL) /**< \brief (TCC0) Compare and Capture Buffer 2 */ -#define REG_TCC0_CCBUF3 (*(RwReg *)0x42001C7CUL) /**< \brief (TCC0) Compare and Capture Buffer 3 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for TCC0 peripheral ========== */ -#define TCC0_CC_NUM 4 // Number of Compare/Capture units -#define TCC0_DITHERING 1 // Dithering feature implemented -#define TCC0_DMAC_ID_MC_0 15 -#define TCC0_DMAC_ID_MC_1 16 -#define TCC0_DMAC_ID_MC_2 17 -#define TCC0_DMAC_ID_MC_3 18 -#define TCC0_DMAC_ID_MC_LSB 15 -#define TCC0_DMAC_ID_MC_MSB 18 -#define TCC0_DMAC_ID_MC_SIZE 4 -#define TCC0_DMAC_ID_OVF 14 // DMA overflow/underflow/retrigger trigger -#define TCC0_DTI 1 // Dead-Time-Insertion feature implemented -#define TCC0_EXT 31 // Coding of implemented extended features -#define TCC0_GCLK_ID 22 // Index of Generic Clock -#define TCC0_OTMX 1 // Output Matrix feature implemented -#define TCC0_OW_NUM 8 // Number of Output Waveforms -#define TCC0_PG 1 // Pattern Generation feature implemented -#define TCC0_SIZE 24 -#define TCC0_SWAP 1 // DTI outputs swap feature implemented -#define TCC0_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave - -#endif /* _SAML22_TCC0_INSTANCE_ */ diff --git a/watch-library/include/instance/trng.h b/watch-library/include/instance/trng.h deleted file mode 100644 index 0f80f00a..00000000 --- a/watch-library/include/instance/trng.h +++ /dev/null @@ -1,51 +0,0 @@ -/** - * \file - * - * \brief Instance description for TRNG - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_TRNG_INSTANCE_ -#define _SAML22_TRNG_INSTANCE_ - -/* ========== Register definition for TRNG peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_TRNG_CTRLA (0x42004400) /**< \brief (TRNG) Control A */ -#define REG_TRNG_EVCTRL (0x42004404) /**< \brief (TRNG) Event Control */ -#define REG_TRNG_INTENCLR (0x42004408) /**< \brief (TRNG) Interrupt Enable Clear */ -#define REG_TRNG_INTENSET (0x42004409) /**< \brief (TRNG) Interrupt Enable Set */ -#define REG_TRNG_INTFLAG (0x4200440A) /**< \brief (TRNG) Interrupt Flag Status and Clear */ -#define REG_TRNG_DATA (0x42004420) /**< \brief (TRNG) Output Data */ -#else -#define REG_TRNG_CTRLA (*(RwReg8 *)0x42004400UL) /**< \brief (TRNG) Control A */ -#define REG_TRNG_EVCTRL (*(RwReg8 *)0x42004404UL) /**< \brief (TRNG) Event Control */ -#define REG_TRNG_INTENCLR (*(RwReg8 *)0x42004408UL) /**< \brief (TRNG) Interrupt Enable Clear */ -#define REG_TRNG_INTENSET (*(RwReg8 *)0x42004409UL) /**< \brief (TRNG) Interrupt Enable Set */ -#define REG_TRNG_INTFLAG (*(RwReg8 *)0x4200440AUL) /**< \brief (TRNG) Interrupt Flag Status and Clear */ -#define REG_TRNG_DATA (*(RoReg *)0x42004420UL) /**< \brief (TRNG) Output Data */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - - -#endif /* _SAML22_TRNG_INSTANCE_ */ diff --git a/watch-library/include/instance/usb.h b/watch-library/include/instance/usb.h deleted file mode 100644 index 9060d62e..00000000 --- a/watch-library/include/instance/usb.h +++ /dev/null @@ -1,184 +0,0 @@ -/** - * \file - * - * \brief Instance description for USB - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_USB_INSTANCE_ -#define _SAML22_USB_INSTANCE_ - -/* ========== Register definition for USB peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_USB_CTRLA (0x41000000) /**< \brief (USB) Control A */ -#define REG_USB_SYNCBUSY (0x41000002) /**< \brief (USB) Synchronization Busy */ -#define REG_USB_QOSCTRL (0x41000003) /**< \brief (USB) USB Quality Of Service */ -#define REG_USB_FSMSTATUS (0x4100000D) /**< \brief (USB) Finite State Machine Status */ -#define REG_USB_DESCADD (0x41000024) /**< \brief (USB) Descriptor Address */ -#define REG_USB_PADCAL (0x41000028) /**< \brief (USB) USB PAD Calibration */ -#define REG_USB_DEVICE_CTRLB (0x41000008) /**< \brief (USB) DEVICE Control B */ -#define REG_USB_DEVICE_DADD (0x4100000A) /**< \brief (USB) DEVICE Device Address */ -#define REG_USB_DEVICE_STATUS (0x4100000C) /**< \brief (USB) DEVICE Status */ -#define REG_USB_DEVICE_FNUM (0x41000010) /**< \brief (USB) DEVICE Device Frame Number */ -#define REG_USB_DEVICE_INTENCLR (0x41000014) /**< \brief (USB) DEVICE Device Interrupt Enable Clear */ -#define REG_USB_DEVICE_INTENSET (0x41000018) /**< \brief (USB) DEVICE Device Interrupt Enable Set */ -#define REG_USB_DEVICE_INTFLAG (0x4100001C) /**< \brief (USB) DEVICE Device Interrupt Flag */ -#define REG_USB_DEVICE_EPINTSMRY (0x41000020) /**< \brief (USB) DEVICE End Point Interrupt Summary */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG0 (0x41000100) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR0 (0x41000104) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET0 (0x41000105) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS0 (0x41000106) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG0 (0x41000107) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR0 (0x41000108) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET0 (0x41000109) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG1 (0x41000120) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR1 (0x41000124) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET1 (0x41000125) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS1 (0x41000126) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG1 (0x41000127) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR1 (0x41000128) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET1 (0x41000129) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG2 (0x41000140) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR2 (0x41000144) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET2 (0x41000145) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS2 (0x41000146) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG2 (0x41000147) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR2 (0x41000148) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET2 (0x41000149) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG3 (0x41000160) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR3 (0x41000164) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET3 (0x41000165) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS3 (0x41000166) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG3 (0x41000167) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR3 (0x41000168) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET3 (0x41000169) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG4 (0x41000180) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR4 (0x41000184) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET4 (0x41000185) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS4 (0x41000186) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG4 (0x41000187) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR4 (0x41000188) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET4 (0x41000189) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG5 (0x410001A0) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR5 (0x410001A4) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET5 (0x410001A5) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS5 (0x410001A6) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG5 (0x410001A7) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR5 (0x410001A8) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET5 (0x410001A9) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG6 (0x410001C0) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR6 (0x410001C4) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET6 (0x410001C5) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS6 (0x410001C6) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG6 (0x410001C7) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR6 (0x410001C8) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET6 (0x410001C9) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG7 (0x410001E0) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR7 (0x410001E4) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET7 (0x410001E5) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS7 (0x410001E6) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG7 (0x410001E7) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR7 (0x410001E8) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET7 (0x410001E9) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 7 */ -#else -#define REG_USB_CTRLA (*(RwReg8 *)0x41000000UL) /**< \brief (USB) Control A */ -#define REG_USB_SYNCBUSY (*(RoReg8 *)0x41000002UL) /**< \brief (USB) Synchronization Busy */ -#define REG_USB_QOSCTRL (*(RwReg8 *)0x41000003UL) /**< \brief (USB) USB Quality Of Service */ -#define REG_USB_FSMSTATUS (*(RoReg8 *)0x4100000DUL) /**< \brief (USB) Finite State Machine Status */ -#define REG_USB_DESCADD (*(RwReg *)0x41000024UL) /**< \brief (USB) Descriptor Address */ -#define REG_USB_PADCAL (*(RwReg16*)0x41000028UL) /**< \brief (USB) USB PAD Calibration */ -#define REG_USB_DEVICE_CTRLB (*(RwReg16*)0x41000008UL) /**< \brief (USB) DEVICE Control B */ -#define REG_USB_DEVICE_DADD (*(RwReg8 *)0x4100000AUL) /**< \brief (USB) DEVICE Device Address */ -#define REG_USB_DEVICE_STATUS (*(RoReg8 *)0x4100000CUL) /**< \brief (USB) DEVICE Status */ -#define REG_USB_DEVICE_FNUM (*(RoReg16*)0x41000010UL) /**< \brief (USB) DEVICE Device Frame Number */ -#define REG_USB_DEVICE_INTENCLR (*(RwReg16*)0x41000014UL) /**< \brief (USB) DEVICE Device Interrupt Enable Clear */ -#define REG_USB_DEVICE_INTENSET (*(RwReg16*)0x41000018UL) /**< \brief (USB) DEVICE Device Interrupt Enable Set */ -#define REG_USB_DEVICE_INTFLAG (*(RwReg16*)0x4100001CUL) /**< \brief (USB) DEVICE Device Interrupt Flag */ -#define REG_USB_DEVICE_EPINTSMRY (*(RoReg16*)0x41000020UL) /**< \brief (USB) DEVICE End Point Interrupt Summary */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG0 (*(RwReg8 *)0x41000100UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR0 (*(WoReg8 *)0x41000104UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET0 (*(WoReg8 *)0x41000105UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS0 (*(RoReg8 *)0x41000106UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG0 (*(RwReg8 *)0x41000107UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR0 (*(RwReg8 *)0x41000108UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET0 (*(RwReg8 *)0x41000109UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 0 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG1 (*(RwReg8 *)0x41000120UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR1 (*(WoReg8 *)0x41000124UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET1 (*(WoReg8 *)0x41000125UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS1 (*(RoReg8 *)0x41000126UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG1 (*(RwReg8 *)0x41000127UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR1 (*(RwReg8 *)0x41000128UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET1 (*(RwReg8 *)0x41000129UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 1 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG2 (*(RwReg8 *)0x41000140UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR2 (*(WoReg8 *)0x41000144UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET2 (*(WoReg8 *)0x41000145UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS2 (*(RoReg8 *)0x41000146UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG2 (*(RwReg8 *)0x41000147UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR2 (*(RwReg8 *)0x41000148UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET2 (*(RwReg8 *)0x41000149UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 2 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG3 (*(RwReg8 *)0x41000160UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR3 (*(WoReg8 *)0x41000164UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET3 (*(WoReg8 *)0x41000165UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS3 (*(RoReg8 *)0x41000166UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG3 (*(RwReg8 *)0x41000167UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR3 (*(RwReg8 *)0x41000168UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET3 (*(RwReg8 *)0x41000169UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 3 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG4 (*(RwReg8 *)0x41000180UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR4 (*(WoReg8 *)0x41000184UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET4 (*(WoReg8 *)0x41000185UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS4 (*(RoReg8 *)0x41000186UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG4 (*(RwReg8 *)0x41000187UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR4 (*(RwReg8 *)0x41000188UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET4 (*(RwReg8 *)0x41000189UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 4 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG5 (*(RwReg8 *)0x410001A0UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR5 (*(WoReg8 *)0x410001A4UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET5 (*(WoReg8 *)0x410001A5UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS5 (*(RoReg8 *)0x410001A6UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG5 (*(RwReg8 *)0x410001A7UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR5 (*(RwReg8 *)0x410001A8UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET5 (*(RwReg8 *)0x410001A9UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 5 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG6 (*(RwReg8 *)0x410001C0UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR6 (*(WoReg8 *)0x410001C4UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET6 (*(WoReg8 *)0x410001C5UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS6 (*(RoReg8 *)0x410001C6UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG6 (*(RwReg8 *)0x410001C7UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR6 (*(RwReg8 *)0x410001C8UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET6 (*(RwReg8 *)0x410001C9UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 6 */ -#define REG_USB_DEVICE_ENDPOINT_EPCFG7 (*(RwReg8 *)0x410001E0UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR7 (*(WoReg8 *)0x410001E4UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET7 (*(WoReg8 *)0x410001E5UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPSTATUS7 (*(RoReg8 *)0x410001E6UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG7 (*(RwReg8 *)0x410001E7UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR7 (*(RwReg8 *)0x410001E8UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 7 */ -#define REG_USB_DEVICE_ENDPOINT_EPINTENSET7 (*(RwReg8 *)0x410001E9UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 7 */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* ========== Instance parameters for USB peripheral ========== */ -#define USB_EPT_NBR 8 // Number of USB end points (obsolete) -#define USB_EPT_NUM 8 // Number of USB end points -#define USB_GCLK_ID 6 // Index of Generic Clock -#define USB_PIPE_NUM 0 // Number of USB pipes - -#endif /* _SAML22_USB_INSTANCE_ */ diff --git a/watch-library/include/instance/wdt.h b/watch-library/include/instance/wdt.h deleted file mode 100644 index 2bb1d1ba..00000000 --- a/watch-library/include/instance/wdt.h +++ /dev/null @@ -1,55 +0,0 @@ -/** - * \file - * - * \brief Instance description for WDT - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAML22_WDT_INSTANCE_ -#define _SAML22_WDT_INSTANCE_ - -/* ========== Register definition for WDT peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_WDT_CTRLA (0x40002000) /**< \brief (WDT) Control */ -#define REG_WDT_CONFIG (0x40002001) /**< \brief (WDT) Configuration */ -#define REG_WDT_EWCTRL (0x40002002) /**< \brief (WDT) Early Warning Interrupt Control */ -#define REG_WDT_INTENCLR (0x40002004) /**< \brief (WDT) Interrupt Enable Clear */ -#define REG_WDT_INTENSET (0x40002005) /**< \brief (WDT) Interrupt Enable Set */ -#define REG_WDT_INTFLAG (0x40002006) /**< \brief (WDT) Interrupt Flag Status and Clear */ -#define REG_WDT_SYNCBUSY (0x40002008) /**< \brief (WDT) Synchronization Busy */ -#define REG_WDT_CLEAR (0x4000200C) /**< \brief (WDT) Clear */ -#else -#define REG_WDT_CTRLA (*(RwReg8 *)0x40002000UL) /**< \brief (WDT) Control */ -#define REG_WDT_CONFIG (*(RwReg8 *)0x40002001UL) /**< \brief (WDT) Configuration */ -#define REG_WDT_EWCTRL (*(RwReg8 *)0x40002002UL) /**< \brief (WDT) Early Warning Interrupt Control */ -#define REG_WDT_INTENCLR (*(RwReg8 *)0x40002004UL) /**< \brief (WDT) Interrupt Enable Clear */ -#define REG_WDT_INTENSET (*(RwReg8 *)0x40002005UL) /**< \brief (WDT) Interrupt Enable Set */ -#define REG_WDT_INTFLAG (*(RwReg8 *)0x40002006UL) /**< \brief (WDT) Interrupt Flag Status and Clear */ -#define REG_WDT_SYNCBUSY (*(RoReg *)0x40002008UL) /**< \brief (WDT) Synchronization Busy */ -#define REG_WDT_CLEAR (*(WoReg8 *)0x4000200CUL) /**< \brief (WDT) Clear */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - - -#endif /* _SAML22_WDT_INSTANCE_ */ |