summaryrefslogtreecommitdiffstats
path: root/watch-library/watch
diff options
context:
space:
mode:
authorJoey Castillo <jose.castillo@gmail.com>2021-08-30 14:37:14 -0400
committerJoey Castillo <jose.castillo@gmail.com>2021-08-30 14:37:14 -0400
commitb0845cc3f1a8234a30c980eccf10e44765e4e105 (patch)
tree7a514b4d21dd0d2a324a5e1313a144f26bf20799 /watch-library/watch
parent6650e8aef0d2d8faf0bc29aa80d91956f5d8b316 (diff)
downloadSensor-Watch-b0845cc3f1a8234a30c980eccf10e44765e4e105.tar.gz
Sensor-Watch-b0845cc3f1a8234a30c980eccf10e44765e4e105.tar.bz2
Sensor-Watch-b0845cc3f1a8234a30c980eccf10e44765e4e105.zip
fix typo
Diffstat (limited to 'watch-library/watch')
-rw-r--r--watch-library/watch/watch_private.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/watch-library/watch/watch_private.c b/watch-library/watch/watch_private.c
index bffa1baa..a4e2f72c 100644
--- a/watch-library/watch/watch_private.c
+++ b/watch-library/watch/watch_private.c
@@ -147,7 +147,7 @@ void _watch_enable_usb() {
hri_tc_write_CTRLA_reg(TC0, TC_CTRLA_SWRST);
hri_tc_wait_for_sync(TC0, TC_SYNCBUSY_SWRST);
// configure the TC to overflow 1,000 times per second
- hri_tc_write_CTRLA_reg(TC0, TC_CTRLA_PRESCALER_DIV16 | // divide the 8 MHz clock by 64 to count at 125 KHz
+ hri_tc_write_CTRLA_reg(TC0, TC_CTRLA_PRESCALER_DIV64 | // divide the 8 MHz clock by 64 to count at 125 KHz
TC_CTRLA_MODE_COUNT8 | // count in 8-bit mode
TC_CTRLA_RUNSTDBY); // run in standby, just in case we figure that out
hri_tccount8_write_PER_reg(TC0, 125); // 125000 Hz / 125 = 1,000 Hz