diff options
Diffstat (limited to 'Sensor Watch Starter Project/include/instance/tc3.h')
| -rw-r--r--[-rwxr-xr-x] | Sensor Watch Starter Project/include/instance/tc3.h | 232 |
1 files changed, 109 insertions, 123 deletions
diff --git a/Sensor Watch Starter Project/include/instance/tc3.h b/Sensor Watch Starter Project/include/instance/tc3.h index dc7af021..7555903a 100755..100644 --- a/Sensor Watch Starter Project/include/instance/tc3.h +++ b/Sensor Watch Starter Project/include/instance/tc3.h @@ -1,123 +1,109 @@ -/**
- * \file
- *
- * \brief Instance description for TC3
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _SAML22_TC3_INSTANCE_
-#define _SAML22_TC3_INSTANCE_
-
-/* ========== Register definition for TC3 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define REG_TC3_CTRLA (0x42002C00U) /**< \brief (TC3) Control A */
-#define REG_TC3_CTRLBCLR (0x42002C04U) /**< \brief (TC3) Control B Clear */
-#define REG_TC3_CTRLBSET (0x42002C05U) /**< \brief (TC3) Control B Set */
-#define REG_TC3_EVCTRL (0x42002C06U) /**< \brief (TC3) Event Control */
-#define REG_TC3_INTENCLR (0x42002C08U) /**< \brief (TC3) Interrupt Enable Clear */
-#define REG_TC3_INTENSET (0x42002C09U) /**< \brief (TC3) Interrupt Enable Set */
-#define REG_TC3_INTFLAG (0x42002C0AU) /**< \brief (TC3) Interrupt Flag Status and Clear */
-#define REG_TC3_STATUS (0x42002C0BU) /**< \brief (TC3) Status */
-#define REG_TC3_WAVE (0x42002C0CU) /**< \brief (TC3) Waveform Generation Control */
-#define REG_TC3_DRVCTRL (0x42002C0DU) /**< \brief (TC3) Control C */
-#define REG_TC3_DBGCTRL (0x42002C0FU) /**< \brief (TC3) Debug Control */
-#define REG_TC3_SYNCBUSY (0x42002C10U) /**< \brief (TC3) Synchronization Status */
-#define REG_TC3_COUNT16_COUNT (0x42002C14U) /**< \brief (TC3) COUNT16 Count */
-#define REG_TC3_COUNT16_CC0 (0x42002C1CU) /**< \brief (TC3) COUNT16 Compare and Capture 0 */
-#define REG_TC3_COUNT16_CC1 (0x42002C1EU) /**< \brief (TC3) COUNT16 Compare and Capture 1 */
-#define REG_TC3_COUNT16_CCBUF0 (0x42002C30U) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 0 */
-#define REG_TC3_COUNT16_CCBUF1 (0x42002C32U) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 1 */
-#define REG_TC3_COUNT32_COUNT (0x42002C14U) /**< \brief (TC3) COUNT32 Count */
-#define REG_TC3_COUNT32_CC0 (0x42002C1CU) /**< \brief (TC3) COUNT32 Compare and Capture 0 */
-#define REG_TC3_COUNT32_CC1 (0x42002C20U) /**< \brief (TC3) COUNT32 Compare and Capture 1 */
-#define REG_TC3_COUNT32_CCBUF0 (0x42002C30U) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 0 */
-#define REG_TC3_COUNT32_CCBUF1 (0x42002C34U) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 1 */
-#define REG_TC3_COUNT8_COUNT (0x42002C14U) /**< \brief (TC3) COUNT8 Count */
-#define REG_TC3_COUNT8_PER (0x42002C1BU) /**< \brief (TC3) COUNT8 Period */
-#define REG_TC3_COUNT8_CC0 (0x42002C1CU) /**< \brief (TC3) COUNT8 Compare and Capture 0 */
-#define REG_TC3_COUNT8_CC1 (0x42002C1DU) /**< \brief (TC3) COUNT8 Compare and Capture 1 */
-#define REG_TC3_COUNT8_PERBUF (0x42002C2FU) /**< \brief (TC3) COUNT8 Period Buffer */
-#define REG_TC3_COUNT8_CCBUF0 (0x42002C30U) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 0 */
-#define REG_TC3_COUNT8_CCBUF1 (0x42002C31U) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 1 */
-#else
-#define REG_TC3_CTRLA (*(RwReg *)0x42002C00U) /**< \brief (TC3) Control A */
-#define REG_TC3_CTRLBCLR (*(RwReg8 *)0x42002C04U) /**< \brief (TC3) Control B Clear */
-#define REG_TC3_CTRLBSET (*(RwReg8 *)0x42002C05U) /**< \brief (TC3) Control B Set */
-#define REG_TC3_EVCTRL (*(RwReg16*)0x42002C06U) /**< \brief (TC3) Event Control */
-#define REG_TC3_INTENCLR (*(RwReg8 *)0x42002C08U) /**< \brief (TC3) Interrupt Enable Clear */
-#define REG_TC3_INTENSET (*(RwReg8 *)0x42002C09U) /**< \brief (TC3) Interrupt Enable Set */
-#define REG_TC3_INTFLAG (*(RwReg8 *)0x42002C0AU) /**< \brief (TC3) Interrupt Flag Status and Clear */
-#define REG_TC3_STATUS (*(RwReg8 *)0x42002C0BU) /**< \brief (TC3) Status */
-#define REG_TC3_WAVE (*(RwReg8 *)0x42002C0CU) /**< \brief (TC3) Waveform Generation Control */
-#define REG_TC3_DRVCTRL (*(RwReg8 *)0x42002C0DU) /**< \brief (TC3) Control C */
-#define REG_TC3_DBGCTRL (*(RwReg8 *)0x42002C0FU) /**< \brief (TC3) Debug Control */
-#define REG_TC3_SYNCBUSY (*(RoReg *)0x42002C10U) /**< \brief (TC3) Synchronization Status */
-#define REG_TC3_COUNT16_COUNT (*(RwReg16*)0x42002C14U) /**< \brief (TC3) COUNT16 Count */
-#define REG_TC3_COUNT16_CC0 (*(RwReg16*)0x42002C1CU) /**< \brief (TC3) COUNT16 Compare and Capture 0 */
-#define REG_TC3_COUNT16_CC1 (*(RwReg16*)0x42002C1EU) /**< \brief (TC3) COUNT16 Compare and Capture 1 */
-#define REG_TC3_COUNT16_CCBUF0 (*(RwReg16*)0x42002C30U) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 0 */
-#define REG_TC3_COUNT16_CCBUF1 (*(RwReg16*)0x42002C32U) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 1 */
-#define REG_TC3_COUNT32_COUNT (*(RwReg *)0x42002C14U) /**< \brief (TC3) COUNT32 Count */
-#define REG_TC3_COUNT32_CC0 (*(RwReg *)0x42002C1CU) /**< \brief (TC3) COUNT32 Compare and Capture 0 */
-#define REG_TC3_COUNT32_CC1 (*(RwReg *)0x42002C20U) /**< \brief (TC3) COUNT32 Compare and Capture 1 */
-#define REG_TC3_COUNT32_CCBUF0 (*(RwReg *)0x42002C30U) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 0 */
-#define REG_TC3_COUNT32_CCBUF1 (*(RwReg *)0x42002C34U) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 1 */
-#define REG_TC3_COUNT8_COUNT (*(RwReg8 *)0x42002C14U) /**< \brief (TC3) COUNT8 Count */
-#define REG_TC3_COUNT8_PER (*(RwReg8 *)0x42002C1BU) /**< \brief (TC3) COUNT8 Period */
-#define REG_TC3_COUNT8_CC0 (*(RwReg8 *)0x42002C1CU) /**< \brief (TC3) COUNT8 Compare and Capture 0 */
-#define REG_TC3_COUNT8_CC1 (*(RwReg8 *)0x42002C1DU) /**< \brief (TC3) COUNT8 Compare and Capture 1 */
-#define REG_TC3_COUNT8_PERBUF (*(RwReg8 *)0x42002C2FU) /**< \brief (TC3) COUNT8 Period Buffer */
-#define REG_TC3_COUNT8_CCBUF0 (*(RwReg8 *)0x42002C30U) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 0 */
-#define REG_TC3_COUNT8_CCBUF1 (*(RwReg8 *)0x42002C31U) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 1 */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-/* ========== Instance parameters for TC3 peripheral ========== */
-#define TC3_CC_NUM 2
-#define TC3_DMAC_ID_MC_0 29
-#define TC3_DMAC_ID_MC_1 30
-#define TC3_DMAC_ID_MC_LSB 29
-#define TC3_DMAC_ID_MC_MSB 30
-#define TC3_DMAC_ID_MC_SIZE 2
-#define TC3_DMAC_ID_OVF 28 // Indexes of DMA Overflow trigger
-#define TC3_EXT 0
-#define TC3_GCLK_ID 24
-#define TC3_MASTER 0
-#define TC3_OW_NUM 2
-
-#endif /* _SAML22_TC3_INSTANCE_ */
+/** + * \file + * + * \brief Instance description for TC3 + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_TC3_INSTANCE_ +#define _SAML22_TC3_INSTANCE_ + +/* ========== Register definition for TC3 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TC3_CTRLA (0x42002C00) /**< \brief (TC3) Control A */ +#define REG_TC3_CTRLBCLR (0x42002C04) /**< \brief (TC3) Control B Clear */ +#define REG_TC3_CTRLBSET (0x42002C05) /**< \brief (TC3) Control B Set */ +#define REG_TC3_EVCTRL (0x42002C06) /**< \brief (TC3) Event Control */ +#define REG_TC3_INTENCLR (0x42002C08) /**< \brief (TC3) Interrupt Enable Clear */ +#define REG_TC3_INTENSET (0x42002C09) /**< \brief (TC3) Interrupt Enable Set */ +#define REG_TC3_INTFLAG (0x42002C0A) /**< \brief (TC3) Interrupt Flag Status and Clear */ +#define REG_TC3_STATUS (0x42002C0B) /**< \brief (TC3) Status */ +#define REG_TC3_WAVE (0x42002C0C) /**< \brief (TC3) Waveform Generation Control */ +#define REG_TC3_DRVCTRL (0x42002C0D) /**< \brief (TC3) Control C */ +#define REG_TC3_DBGCTRL (0x42002C0F) /**< \brief (TC3) Debug Control */ +#define REG_TC3_SYNCBUSY (0x42002C10) /**< \brief (TC3) Synchronization Status */ +#define REG_TC3_COUNT16_COUNT (0x42002C14) /**< \brief (TC3) COUNT16 Count */ +#define REG_TC3_COUNT16_CC0 (0x42002C1C) /**< \brief (TC3) COUNT16 Compare and Capture 0 */ +#define REG_TC3_COUNT16_CC1 (0x42002C1E) /**< \brief (TC3) COUNT16 Compare and Capture 1 */ +#define REG_TC3_COUNT16_CCBUF0 (0x42002C30) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 0 */ +#define REG_TC3_COUNT16_CCBUF1 (0x42002C32) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 1 */ +#define REG_TC3_COUNT32_COUNT (0x42002C14) /**< \brief (TC3) COUNT32 Count */ +#define REG_TC3_COUNT32_CC0 (0x42002C1C) /**< \brief (TC3) COUNT32 Compare and Capture 0 */ +#define REG_TC3_COUNT32_CC1 (0x42002C20) /**< \brief (TC3) COUNT32 Compare and Capture 1 */ +#define REG_TC3_COUNT32_CCBUF0 (0x42002C30) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 0 */ +#define REG_TC3_COUNT32_CCBUF1 (0x42002C34) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 1 */ +#define REG_TC3_COUNT8_COUNT (0x42002C14) /**< \brief (TC3) COUNT8 Count */ +#define REG_TC3_COUNT8_PER (0x42002C1B) /**< \brief (TC3) COUNT8 Period */ +#define REG_TC3_COUNT8_CC0 (0x42002C1C) /**< \brief (TC3) COUNT8 Compare and Capture 0 */ +#define REG_TC3_COUNT8_CC1 (0x42002C1D) /**< \brief (TC3) COUNT8 Compare and Capture 1 */ +#define REG_TC3_COUNT8_PERBUF (0x42002C2F) /**< \brief (TC3) COUNT8 Period Buffer */ +#define REG_TC3_COUNT8_CCBUF0 (0x42002C30) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 0 */ +#define REG_TC3_COUNT8_CCBUF1 (0x42002C31) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 1 */ +#else +#define REG_TC3_CTRLA (*(RwReg *)0x42002C00UL) /**< \brief (TC3) Control A */ +#define REG_TC3_CTRLBCLR (*(RwReg8 *)0x42002C04UL) /**< \brief (TC3) Control B Clear */ +#define REG_TC3_CTRLBSET (*(RwReg8 *)0x42002C05UL) /**< \brief (TC3) Control B Set */ +#define REG_TC3_EVCTRL (*(RwReg16*)0x42002C06UL) /**< \brief (TC3) Event Control */ +#define REG_TC3_INTENCLR (*(RwReg8 *)0x42002C08UL) /**< \brief (TC3) Interrupt Enable Clear */ +#define REG_TC3_INTENSET (*(RwReg8 *)0x42002C09UL) /**< \brief (TC3) Interrupt Enable Set */ +#define REG_TC3_INTFLAG (*(RwReg8 *)0x42002C0AUL) /**< \brief (TC3) Interrupt Flag Status and Clear */ +#define REG_TC3_STATUS (*(RwReg8 *)0x42002C0BUL) /**< \brief (TC3) Status */ +#define REG_TC3_WAVE (*(RwReg8 *)0x42002C0CUL) /**< \brief (TC3) Waveform Generation Control */ +#define REG_TC3_DRVCTRL (*(RwReg8 *)0x42002C0DUL) /**< \brief (TC3) Control C */ +#define REG_TC3_DBGCTRL (*(RwReg8 *)0x42002C0FUL) /**< \brief (TC3) Debug Control */ +#define REG_TC3_SYNCBUSY (*(RoReg *)0x42002C10UL) /**< \brief (TC3) Synchronization Status */ +#define REG_TC3_COUNT16_COUNT (*(RwReg16*)0x42002C14UL) /**< \brief (TC3) COUNT16 Count */ +#define REG_TC3_COUNT16_CC0 (*(RwReg16*)0x42002C1CUL) /**< \brief (TC3) COUNT16 Compare and Capture 0 */ +#define REG_TC3_COUNT16_CC1 (*(RwReg16*)0x42002C1EUL) /**< \brief (TC3) COUNT16 Compare and Capture 1 */ +#define REG_TC3_COUNT16_CCBUF0 (*(RwReg16*)0x42002C30UL) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 0 */ +#define REG_TC3_COUNT16_CCBUF1 (*(RwReg16*)0x42002C32UL) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 1 */ +#define REG_TC3_COUNT32_COUNT (*(RwReg *)0x42002C14UL) /**< \brief (TC3) COUNT32 Count */ +#define REG_TC3_COUNT32_CC0 (*(RwReg *)0x42002C1CUL) /**< \brief (TC3) COUNT32 Compare and Capture 0 */ +#define REG_TC3_COUNT32_CC1 (*(RwReg *)0x42002C20UL) /**< \brief (TC3) COUNT32 Compare and Capture 1 */ +#define REG_TC3_COUNT32_CCBUF0 (*(RwReg *)0x42002C30UL) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 0 */ +#define REG_TC3_COUNT32_CCBUF1 (*(RwReg *)0x42002C34UL) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 1 */ +#define REG_TC3_COUNT8_COUNT (*(RwReg8 *)0x42002C14UL) /**< \brief (TC3) COUNT8 Count */ +#define REG_TC3_COUNT8_PER (*(RwReg8 *)0x42002C1BUL) /**< \brief (TC3) COUNT8 Period */ +#define REG_TC3_COUNT8_CC0 (*(RwReg8 *)0x42002C1CUL) /**< \brief (TC3) COUNT8 Compare and Capture 0 */ +#define REG_TC3_COUNT8_CC1 (*(RwReg8 *)0x42002C1DUL) /**< \brief (TC3) COUNT8 Compare and Capture 1 */ +#define REG_TC3_COUNT8_PERBUF (*(RwReg8 *)0x42002C2FUL) /**< \brief (TC3) COUNT8 Period Buffer */ +#define REG_TC3_COUNT8_CCBUF0 (*(RwReg8 *)0x42002C30UL) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 0 */ +#define REG_TC3_COUNT8_CCBUF1 (*(RwReg8 *)0x42002C31UL) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for TC3 peripheral ========== */ +#define TC3_CC_NUM 2 +#define TC3_DMAC_ID_MC_0 29 +#define TC3_DMAC_ID_MC_1 30 +#define TC3_DMAC_ID_MC_LSB 29 +#define TC3_DMAC_ID_MC_MSB 30 +#define TC3_DMAC_ID_MC_SIZE 2 +#define TC3_DMAC_ID_OVF 28 // Indexes of DMA Overflow trigger +#define TC3_EXT 0 +#define TC3_GCLK_ID 24 +#define TC3_MASTER 0 +#define TC3_OW_NUM 2 + +#endif /* _SAML22_TC3_INSTANCE_ */ |