diff options
Diffstat (limited to 'Sensor Watch Starter Project/include/instance')
37 files changed, 4414 insertions, 0 deletions
diff --git a/Sensor Watch Starter Project/include/instance/ac.h b/Sensor Watch Starter Project/include/instance/ac.h new file mode 100755 index 00000000..1ee7fac6 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/ac.h @@ -0,0 +1,88 @@ +/**
+ * \file
+ *
+ * \brief Instance description for AC
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAML22_AC_INSTANCE_
+#define _SAML22_AC_INSTANCE_
+
+/* ========== Register definition for AC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_AC_CTRLA (0x42003400U) /**< \brief (AC) Control A */
+#define REG_AC_CTRLB (0x42003401U) /**< \brief (AC) Control B */
+#define REG_AC_EVCTRL (0x42003402U) /**< \brief (AC) Event Control */
+#define REG_AC_INTENCLR (0x42003404U) /**< \brief (AC) Interrupt Enable Clear */
+#define REG_AC_INTENSET (0x42003405U) /**< \brief (AC) Interrupt Enable Set */
+#define REG_AC_INTFLAG (0x42003406U) /**< \brief (AC) Interrupt Flag Status and Clear */
+#define REG_AC_STATUSA (0x42003407U) /**< \brief (AC) Status A */
+#define REG_AC_STATUSB (0x42003408U) /**< \brief (AC) Status B */
+#define REG_AC_DBGCTRL (0x42003409U) /**< \brief (AC) Debug Control */
+#define REG_AC_WINCTRL (0x4200340AU) /**< \brief (AC) Window Control */
+#define REG_AC_SCALER0 (0x4200340CU) /**< \brief (AC) Scaler 0 */
+#define REG_AC_SCALER1 (0x4200340DU) /**< \brief (AC) Scaler 1 */
+#define REG_AC_COMPCTRL0 (0x42003410U) /**< \brief (AC) Comparator Control 0 */
+#define REG_AC_COMPCTRL1 (0x42003414U) /**< \brief (AC) Comparator Control 1 */
+#define REG_AC_SYNCBUSY (0x42003420U) /**< \brief (AC) Synchronization Busy */
+#else
+#define REG_AC_CTRLA (*(RwReg8 *)0x42003400U) /**< \brief (AC) Control A */
+#define REG_AC_CTRLB (*(WoReg8 *)0x42003401U) /**< \brief (AC) Control B */
+#define REG_AC_EVCTRL (*(RwReg16*)0x42003402U) /**< \brief (AC) Event Control */
+#define REG_AC_INTENCLR (*(RwReg8 *)0x42003404U) /**< \brief (AC) Interrupt Enable Clear */
+#define REG_AC_INTENSET (*(RwReg8 *)0x42003405U) /**< \brief (AC) Interrupt Enable Set */
+#define REG_AC_INTFLAG (*(RwReg8 *)0x42003406U) /**< \brief (AC) Interrupt Flag Status and Clear */
+#define REG_AC_STATUSA (*(RoReg8 *)0x42003407U) /**< \brief (AC) Status A */
+#define REG_AC_STATUSB (*(RoReg8 *)0x42003408U) /**< \brief (AC) Status B */
+#define REG_AC_DBGCTRL (*(RwReg8 *)0x42003409U) /**< \brief (AC) Debug Control */
+#define REG_AC_WINCTRL (*(RwReg8 *)0x4200340AU) /**< \brief (AC) Window Control */
+#define REG_AC_SCALER0 (*(RwReg8 *)0x4200340CU) /**< \brief (AC) Scaler 0 */
+#define REG_AC_SCALER1 (*(RwReg8 *)0x4200340DU) /**< \brief (AC) Scaler 1 */
+#define REG_AC_COMPCTRL0 (*(RwReg *)0x42003410U) /**< \brief (AC) Comparator Control 0 */
+#define REG_AC_COMPCTRL1 (*(RwReg *)0x42003414U) /**< \brief (AC) Comparator Control 1 */
+#define REG_AC_SYNCBUSY (*(RoReg *)0x42003420U) /**< \brief (AC) Synchronization Busy */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for AC peripheral ========== */
+#define AC_COMPCTRL_MUXNEG_OPAMP 7 // OPAMP selection for MUXNEG
+#define AC_GCLK_ID 26 // Index of Generic Clock
+#define AC_NUM_CMP 2 // Number of comparators
+#define AC_PAIRS 1 // Number of pairs of comparators
+
+#endif /* _SAML22_AC_INSTANCE_ */
diff --git a/Sensor Watch Starter Project/include/instance/adc.h b/Sensor Watch Starter Project/include/instance/adc.h new file mode 100755 index 00000000..418a3e93 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/adc.h @@ -0,0 +1,103 @@ +/**
+ * \file
+ *
+ * \brief Instance description for ADC
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAML22_ADC_INSTANCE_
+#define _SAML22_ADC_INSTANCE_
+
+/* ========== Register definition for ADC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_ADC_CTRLA (0x42003000U) /**< \brief (ADC) Control A */
+#define REG_ADC_CTRLB (0x42003001U) /**< \brief (ADC) Control B */
+#define REG_ADC_REFCTRL (0x42003002U) /**< \brief (ADC) Reference Control */
+#define REG_ADC_EVCTRL (0x42003003U) /**< \brief (ADC) Event Control */
+#define REG_ADC_INTENCLR (0x42003004U) /**< \brief (ADC) Interrupt Enable Clear */
+#define REG_ADC_INTENSET (0x42003005U) /**< \brief (ADC) Interrupt Enable Set */
+#define REG_ADC_INTFLAG (0x42003006U) /**< \brief (ADC) Interrupt Flag Status and Clear */
+#define REG_ADC_SEQSTATUS (0x42003007U) /**< \brief (ADC) Sequence Status */
+#define REG_ADC_INPUTCTRL (0x42003008U) /**< \brief (ADC) Input Control */
+#define REG_ADC_CTRLC (0x4200300AU) /**< \brief (ADC) Control C */
+#define REG_ADC_AVGCTRL (0x4200300CU) /**< \brief (ADC) Average Control */
+#define REG_ADC_SAMPCTRL (0x4200300DU) /**< \brief (ADC) Sample Time Control */
+#define REG_ADC_WINLT (0x4200300EU) /**< \brief (ADC) Window Monitor Lower Threshold */
+#define REG_ADC_WINUT (0x42003010U) /**< \brief (ADC) Window Monitor Upper Threshold */
+#define REG_ADC_GAINCORR (0x42003012U) /**< \brief (ADC) Gain Correction */
+#define REG_ADC_OFFSETCORR (0x42003014U) /**< \brief (ADC) Offset Correction */
+#define REG_ADC_SWTRIG (0x42003018U) /**< \brief (ADC) Software Trigger */
+#define REG_ADC_DBGCTRL (0x4200301CU) /**< \brief (ADC) Debug Control */
+#define REG_ADC_SYNCBUSY (0x42003020U) /**< \brief (ADC) Synchronization Busy */
+#define REG_ADC_RESULT (0x42003024U) /**< \brief (ADC) Result */
+#define REG_ADC_SEQCTRL (0x42003028U) /**< \brief (ADC) Sequence Control */
+#define REG_ADC_CALIB (0x4200302CU) /**< \brief (ADC) Calibration */
+#else
+#define REG_ADC_CTRLA (*(RwReg8 *)0x42003000U) /**< \brief (ADC) Control A */
+#define REG_ADC_CTRLB (*(RwReg8 *)0x42003001U) /**< \brief (ADC) Control B */
+#define REG_ADC_REFCTRL (*(RwReg8 *)0x42003002U) /**< \brief (ADC) Reference Control */
+#define REG_ADC_EVCTRL (*(RwReg8 *)0x42003003U) /**< \brief (ADC) Event Control */
+#define REG_ADC_INTENCLR (*(RwReg8 *)0x42003004U) /**< \brief (ADC) Interrupt Enable Clear */
+#define REG_ADC_INTENSET (*(RwReg8 *)0x42003005U) /**< \brief (ADC) Interrupt Enable Set */
+#define REG_ADC_INTFLAG (*(RwReg8 *)0x42003006U) /**< \brief (ADC) Interrupt Flag Status and Clear */
+#define REG_ADC_SEQSTATUS (*(RoReg8 *)0x42003007U) /**< \brief (ADC) Sequence Status */
+#define REG_ADC_INPUTCTRL (*(RwReg16*)0x42003008U) /**< \brief (ADC) Input Control */
+#define REG_ADC_CTRLC (*(RwReg16*)0x4200300AU) /**< \brief (ADC) Control C */
+#define REG_ADC_AVGCTRL (*(RwReg8 *)0x4200300CU) /**< \brief (ADC) Average Control */
+#define REG_ADC_SAMPCTRL (*(RwReg8 *)0x4200300DU) /**< \brief (ADC) Sample Time Control */
+#define REG_ADC_WINLT (*(RwReg16*)0x4200300EU) /**< \brief (ADC) Window Monitor Lower Threshold */
+#define REG_ADC_WINUT (*(RwReg16*)0x42003010U) /**< \brief (ADC) Window Monitor Upper Threshold */
+#define REG_ADC_GAINCORR (*(RwReg16*)0x42003012U) /**< \brief (ADC) Gain Correction */
+#define REG_ADC_OFFSETCORR (*(RwReg16*)0x42003014U) /**< \brief (ADC) Offset Correction */
+#define REG_ADC_SWTRIG (*(RwReg8 *)0x42003018U) /**< \brief (ADC) Software Trigger */
+#define REG_ADC_DBGCTRL (*(RwReg8 *)0x4200301CU) /**< \brief (ADC) Debug Control */
+#define REG_ADC_SYNCBUSY (*(RoReg16*)0x42003020U) /**< \brief (ADC) Synchronization Busy */
+#define REG_ADC_RESULT (*(RoReg16*)0x42003024U) /**< \brief (ADC) Result */
+#define REG_ADC_SEQCTRL (*(RwReg *)0x42003028U) /**< \brief (ADC) Sequence Control */
+#define REG_ADC_CALIB (*(RwReg16*)0x4200302CU) /**< \brief (ADC) Calibration */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for ADC peripheral ========== */
+#define ADC_DMAC_ID_RESRDY 31 // index of DMA RESRDY trigger
+#define ADC_EXTCHANNEL_MSB 19 // Number of external channels
+#define ADC_GCLK_ID 25 // index of Generic Clock
+#define ADC_INT_CH30 2 // Select OPAMP or CTAT on Channel 30
+#define ADC_MASTER_SLAVE_MODE 0 // ADC Master/Slave Mode
+
+#endif /* _SAML22_ADC_INSTANCE_ */
diff --git a/Sensor Watch Starter Project/include/instance/aes.h b/Sensor Watch Starter Project/include/instance/aes.h new file mode 100755 index 00000000..93105182 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/aes.h @@ -0,0 +1,116 @@ +/**
+ * \file
+ *
+ * \brief Instance description for AES
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAML22_AES_INSTANCE_
+#define _SAML22_AES_INSTANCE_
+
+/* ========== Register definition for AES peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_AES_CTRLA (0x42004000U) /**< \brief (AES) Control A */
+#define REG_AES_CTRLB (0x42004004U) /**< \brief (AES) Control B */
+#define REG_AES_INTENCLR (0x42004005U) /**< \brief (AES) Interrupt Enable Clear */
+#define REG_AES_INTENSET (0x42004006U) /**< \brief (AES) Interrupt Enable Set */
+#define REG_AES_INTFLAG (0x42004007U) /**< \brief (AES) Interrupt Flag Status */
+#define REG_AES_DATABUFPTR (0x42004008U) /**< \brief (AES) Data buffer pointer */
+#define REG_AES_DBGCTRL (0x42004009U) /**< \brief (AES) Debug control */
+#define REG_AES_KEYWORD0 (0x4200400CU) /**< \brief (AES) Keyword 0 */
+#define REG_AES_KEYWORD1 (0x42004010U) /**< \brief (AES) Keyword 1 */
+#define REG_AES_KEYWORD2 (0x42004014U) /**< \brief (AES) Keyword 2 */
+#define REG_AES_KEYWORD3 (0x42004018U) /**< \brief (AES) Keyword 3 */
+#define REG_AES_KEYWORD4 (0x4200401CU) /**< \brief (AES) Keyword 4 */
+#define REG_AES_KEYWORD5 (0x42004020U) /**< \brief (AES) Keyword 5 */
+#define REG_AES_KEYWORD6 (0x42004024U) /**< \brief (AES) Keyword 6 */
+#define REG_AES_KEYWORD7 (0x42004028U) /**< \brief (AES) Keyword 7 */
+#define REG_AES_INDATA (0x42004038U) /**< \brief (AES) Indata */
+#define REG_AES_INTVECTV0 (0x4200403CU) /**< \brief (AES) Initialisation Vector 0 */
+#define REG_AES_INTVECTV1 (0x42004040U) /**< \brief (AES) Initialisation Vector 1 */
+#define REG_AES_INTVECTV2 (0x42004044U) /**< \brief (AES) Initialisation Vector 2 */
+#define REG_AES_INTVECTV3 (0x42004048U) /**< \brief (AES) Initialisation Vector 3 */
+#define REG_AES_HASHKEY0 (0x4200405CU) /**< \brief (AES) Hash key 0 */
+#define REG_AES_HASHKEY1 (0x42004060U) /**< \brief (AES) Hash key 1 */
+#define REG_AES_HASHKEY2 (0x42004064U) /**< \brief (AES) Hash key 2 */
+#define REG_AES_HASHKEY3 (0x42004068U) /**< \brief (AES) Hash key 3 */
+#define REG_AES_GHASH0 (0x4200406CU) /**< \brief (AES) Galois Hash 0 */
+#define REG_AES_GHASH1 (0x42004070U) /**< \brief (AES) Galois Hash 1 */
+#define REG_AES_GHASH2 (0x42004074U) /**< \brief (AES) Galois Hash 2 */
+#define REG_AES_GHASH3 (0x42004078U) /**< \brief (AES) Galois Hash 3 */
+#define REG_AES_CIPLEN (0x42004080U) /**< \brief (AES) Cipher Length */
+#define REG_AES_RANDSEED (0x42004084U) /**< \brief (AES) Random Seed */
+#else
+#define REG_AES_CTRLA (*(RwReg *)0x42004000U) /**< \brief (AES) Control A */
+#define REG_AES_CTRLB (*(RwReg8 *)0x42004004U) /**< \brief (AES) Control B */
+#define REG_AES_INTENCLR (*(RwReg8 *)0x42004005U) /**< \brief (AES) Interrupt Enable Clear */
+#define REG_AES_INTENSET (*(RwReg8 *)0x42004006U) /**< \brief (AES) Interrupt Enable Set */
+#define REG_AES_INTFLAG (*(RwReg8 *)0x42004007U) /**< \brief (AES) Interrupt Flag Status */
+#define REG_AES_DATABUFPTR (*(RwReg8 *)0x42004008U) /**< \brief (AES) Data buffer pointer */
+#define REG_AES_DBGCTRL (*(WoReg8 *)0x42004009U) /**< \brief (AES) Debug control */
+#define REG_AES_KEYWORD0 (*(WoReg *)0x4200400CU) /**< \brief (AES) Keyword 0 */
+#define REG_AES_KEYWORD1 (*(WoReg *)0x42004010U) /**< \brief (AES) Keyword 1 */
+#define REG_AES_KEYWORD2 (*(WoReg *)0x42004014U) /**< \brief (AES) Keyword 2 */
+#define REG_AES_KEYWORD3 (*(WoReg *)0x42004018U) /**< \brief (AES) Keyword 3 */
+#define REG_AES_KEYWORD4 (*(WoReg *)0x4200401CU) /**< \brief (AES) Keyword 4 */
+#define REG_AES_KEYWORD5 (*(WoReg *)0x42004020U) /**< \brief (AES) Keyword 5 */
+#define REG_AES_KEYWORD6 (*(WoReg *)0x42004024U) /**< \brief (AES) Keyword 6 */
+#define REG_AES_KEYWORD7 (*(WoReg *)0x42004028U) /**< \brief (AES) Keyword 7 */
+#define REG_AES_INDATA (*(RwReg *)0x42004038U) /**< \brief (AES) Indata */
+#define REG_AES_INTVECTV0 (*(WoReg *)0x4200403CU) /**< \brief (AES) Initialisation Vector 0 */
+#define REG_AES_INTVECTV1 (*(WoReg *)0x42004040U) /**< \brief (AES) Initialisation Vector 1 */
+#define REG_AES_INTVECTV2 (*(WoReg *)0x42004044U) /**< \brief (AES) Initialisation Vector 2 */
+#define REG_AES_INTVECTV3 (*(WoReg *)0x42004048U) /**< \brief (AES) Initialisation Vector 3 */
+#define REG_AES_HASHKEY0 (*(RwReg *)0x4200405CU) /**< \brief (AES) Hash key 0 */
+#define REG_AES_HASHKEY1 (*(RwReg *)0x42004060U) /**< \brief (AES) Hash key 1 */
+#define REG_AES_HASHKEY2 (*(RwReg *)0x42004064U) /**< \brief (AES) Hash key 2 */
+#define REG_AES_HASHKEY3 (*(RwReg *)0x42004068U) /**< \brief (AES) Hash key 3 */
+#define REG_AES_GHASH0 (*(RwReg *)0x4200406CU) /**< \brief (AES) Galois Hash 0 */
+#define REG_AES_GHASH1 (*(RwReg *)0x42004070U) /**< \brief (AES) Galois Hash 1 */
+#define REG_AES_GHASH2 (*(RwReg *)0x42004074U) /**< \brief (AES) Galois Hash 2 */
+#define REG_AES_GHASH3 (*(RwReg *)0x42004078U) /**< \brief (AES) Galois Hash 3 */
+#define REG_AES_CIPLEN (*(RwReg *)0x42004080U) /**< \brief (AES) Cipher Length */
+#define REG_AES_RANDSEED (*(RwReg *)0x42004084U) /**< \brief (AES) Random Seed */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for AES peripheral ========== */
+#define AES_DMAC_ID_RD 36 // DMA DATA Read trigger
+#define AES_DMAC_ID_WR 35 // DMA DATA Write trigger
+
+#endif /* _SAML22_AES_INSTANCE_ */
diff --git a/Sensor Watch Starter Project/include/instance/ccl.h b/Sensor Watch Starter Project/include/instance/ccl.h new file mode 100755 index 00000000..d5dfb386 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/ccl.h @@ -0,0 +1,72 @@ +/**
+ * \file
+ *
+ * \brief Instance description for CCL
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAML22_CCL_INSTANCE_
+#define _SAML22_CCL_INSTANCE_
+
+/* ========== Register definition for CCL peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_CCL_CTRL (0x42004800U) /**< \brief (CCL) Control */
+#define REG_CCL_SEQCTRL0 (0x42004804U) /**< \brief (CCL) SEQ Control x 0 */
+#define REG_CCL_SEQCTRL1 (0x42004805U) /**< \brief (CCL) SEQ Control x 1 */
+#define REG_CCL_LUTCTRL0 (0x42004808U) /**< \brief (CCL) LUT Control x 0 */
+#define REG_CCL_LUTCTRL1 (0x4200480CU) /**< \brief (CCL) LUT Control x 1 */
+#define REG_CCL_LUTCTRL2 (0x42004810U) /**< \brief (CCL) LUT Control x 2 */
+#define REG_CCL_LUTCTRL3 (0x42004814U) /**< \brief (CCL) LUT Control x 3 */
+#else
+#define REG_CCL_CTRL (*(RwReg8 *)0x42004800U) /**< \brief (CCL) Control */
+#define REG_CCL_SEQCTRL0 (*(RwReg8 *)0x42004804U) /**< \brief (CCL) SEQ Control x 0 */
+#define REG_CCL_SEQCTRL1 (*(RwReg8 *)0x42004805U) /**< \brief (CCL) SEQ Control x 1 */
+#define REG_CCL_LUTCTRL0 (*(RwReg *)0x42004808U) /**< \brief (CCL) LUT Control x 0 */
+#define REG_CCL_LUTCTRL1 (*(RwReg *)0x4200480CU) /**< \brief (CCL) LUT Control x 1 */
+#define REG_CCL_LUTCTRL2 (*(RwReg *)0x42004810U) /**< \brief (CCL) LUT Control x 2 */
+#define REG_CCL_LUTCTRL3 (*(RwReg *)0x42004814U) /**< \brief (CCL) LUT Control x 3 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for CCL peripheral ========== */
+#define CCL_GCLK_ID 28 // GCLK index for CCL
+#define CCL_IO_NUM 12 // Numer of input pins
+#define CCL_LUT_NUM 4 // Number of LUT in a CCL
+#define CCL_SEQ_NUM 2 // Number of SEQ in a CCL
+
+#endif /* _SAML22_CCL_INSTANCE_ */
diff --git a/Sensor Watch Starter Project/include/instance/dmac.h b/Sensor Watch Starter Project/include/instance/dmac.h new file mode 100755 index 00000000..3bb38f19 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/dmac.h @@ -0,0 +1,110 @@ +/**
+ * \file
+ *
+ * \brief Instance description for DMAC
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAML22_DMAC_INSTANCE_
+#define _SAML22_DMAC_INSTANCE_
+
+/* ========== Register definition for DMAC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_DMAC_CTRL (0x41008000U) /**< \brief (DMAC) Control */
+#define REG_DMAC_CRCCTRL (0x41008002U) /**< \brief (DMAC) CRC Control */
+#define REG_DMAC_CRCDATAIN (0x41008004U) /**< \brief (DMAC) CRC Data Input */
+#define REG_DMAC_CRCCHKSUM (0x41008008U) /**< \brief (DMAC) CRC Checksum */
+#define REG_DMAC_CRCSTATUS (0x4100800CU) /**< \brief (DMAC) CRC Status */
+#define REG_DMAC_DBGCTRL (0x4100800DU) /**< \brief (DMAC) Debug Control */
+#define REG_DMAC_SWTRIGCTRL (0x41008010U) /**< \brief (DMAC) Software Trigger Control */
+#define REG_DMAC_PRICTRL0 (0x41008014U) /**< \brief (DMAC) Priority Control 0 */
+#define REG_DMAC_INTPEND (0x41008020U) /**< \brief (DMAC) Interrupt Pending */
+#define REG_DMAC_INTSTATUS (0x41008024U) /**< \brief (DMAC) Interrupt Status */
+#define REG_DMAC_BUSYCH (0x41008028U) /**< \brief (DMAC) Busy Channels */
+#define REG_DMAC_PENDCH (0x4100802CU) /**< \brief (DMAC) Pending Channels */
+#define REG_DMAC_ACTIVE (0x41008030U) /**< \brief (DMAC) Active Channel and Levels */
+#define REG_DMAC_BASEADDR (0x41008034U) /**< \brief (DMAC) Descriptor Memory Section Base Address */
+#define REG_DMAC_WRBADDR (0x41008038U) /**< \brief (DMAC) Write-Back Memory Section Base Address */
+#define REG_DMAC_CHID (0x4100803FU) /**< \brief (DMAC) Channel ID */
+#define REG_DMAC_CHCTRLA (0x41008040U) /**< \brief (DMAC) Channel Control A */
+#define REG_DMAC_CHCTRLB (0x41008044U) /**< \brief (DMAC) Channel Control B */
+#define REG_DMAC_CHINTENCLR (0x4100804CU) /**< \brief (DMAC) Channel Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET (0x4100804DU) /**< \brief (DMAC) Channel Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG (0x4100804EU) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS (0x4100804FU) /**< \brief (DMAC) Channel Status */
+#else
+#define REG_DMAC_CTRL (*(RwReg16*)0x41008000U) /**< \brief (DMAC) Control */
+#define REG_DMAC_CRCCTRL (*(RwReg16*)0x41008002U) /**< \brief (DMAC) CRC Control */
+#define REG_DMAC_CRCDATAIN (*(RwReg *)0x41008004U) /**< \brief (DMAC) CRC Data Input */
+#define REG_DMAC_CRCCHKSUM (*(RwReg *)0x41008008U) /**< \brief (DMAC) CRC Checksum */
+#define REG_DMAC_CRCSTATUS (*(RwReg8 *)0x4100800CU) /**< \brief (DMAC) CRC Status */
+#define REG_DMAC_DBGCTRL (*(RwReg8 *)0x4100800DU) /**< \brief (DMAC) Debug Control */
+#define REG_DMAC_SWTRIGCTRL (*(RwReg *)0x41008010U) /**< \brief (DMAC) Software Trigger Control */
+#define REG_DMAC_PRICTRL0 (*(RwReg *)0x41008014U) /**< \brief (DMAC) Priority Control 0 */
+#define REG_DMAC_INTPEND (*(RwReg16*)0x41008020U) /**< \brief (DMAC) Interrupt Pending */
+#define REG_DMAC_INTSTATUS (*(RoReg *)0x41008024U) /**< \brief (DMAC) Interrupt Status */
+#define REG_DMAC_BUSYCH (*(RoReg *)0x41008028U) /**< \brief (DMAC) Busy Channels */
+#define REG_DMAC_PENDCH (*(RoReg *)0x4100802CU) /**< \brief (DMAC) Pending Channels */
+#define REG_DMAC_ACTIVE (*(RoReg *)0x41008030U) /**< \brief (DMAC) Active Channel and Levels */
+#define REG_DMAC_BASEADDR (*(RwReg *)0x41008034U) /**< \brief (DMAC) Descriptor Memory Section Base Address */
+#define REG_DMAC_WRBADDR (*(RwReg *)0x41008038U) /**< \brief (DMAC) Write-Back Memory Section Base Address */
+#define REG_DMAC_CHID (*(RwReg8 *)0x4100803FU) /**< \brief (DMAC) Channel ID */
+#define REG_DMAC_CHCTRLA (*(RwReg8 *)0x41008040U) /**< \brief (DMAC) Channel Control A */
+#define REG_DMAC_CHCTRLB (*(RwReg *)0x41008044U) /**< \brief (DMAC) Channel Control B */
+#define REG_DMAC_CHINTENCLR (*(RwReg8 *)0x4100804CU) /**< \brief (DMAC) Channel Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET (*(RwReg8 *)0x4100804DU) /**< \brief (DMAC) Channel Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG (*(RwReg8 *)0x4100804EU) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS (*(RoReg8 *)0x4100804FU) /**< \brief (DMAC) Channel Status */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for DMAC peripheral ========== */
+#define DMAC_CH_BITS 4 // Number of bits to select channel
+#define DMAC_CH_NUM 16 // Number of channels
+#define DMAC_CLK_AHB_ID 3 // AHB clock index
+#define DMAC_EVIN_NUM 4 // Number of input events
+#define DMAC_EVOUT_NUM 4 // Number of output events
+#define DMAC_LVL_BITS 2 // Number of bit to select level priority
+#define DMAC_LVL_NUM 4 // Enable priority level number
+#define DMAC_QOSCTRL_D_RESETVALUE 2 // QOS dmac ahb interface reset value
+#define DMAC_QOSCTRL_F_RESETVALUE 2 // QOS dmac fetch interface reset value
+#define DMAC_QOSCTRL_WRB_RESETVALUE 2 // QOS dmac write back interface reset value
+#define DMAC_TRIG_BITS 6 // Number of bits to select trigger source
+#define DMAC_TRIG_NUM 40 // Number of peripheral triggers
+
+#endif /* _SAML22_DMAC_INSTANCE_ */
diff --git a/Sensor Watch Starter Project/include/instance/dsu.h b/Sensor Watch Starter Project/include/instance/dsu.h new file mode 100755 index 00000000..0706711f --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/dsu.h @@ -0,0 +1,109 @@ +/**
+ * \file
+ *
+ * \brief Instance description for DSU
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAML22_DSU_INSTANCE_
+#define _SAML22_DSU_INSTANCE_
+
+/* ========== Register definition for DSU peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_DSU_CTRL (0x41002000U) /**< \brief (DSU) Control */
+#define REG_DSU_STATUSA (0x41002001U) /**< \brief (DSU) Status A */
+#define REG_DSU_STATUSB (0x41002002U) /**< \brief (DSU) Status B */
+#define REG_DSU_ADDR (0x41002004U) /**< \brief (DSU) Address */
+#define REG_DSU_LENGTH (0x41002008U) /**< \brief (DSU) Length */
+#define REG_DSU_DATA (0x4100200CU) /**< \brief (DSU) Data */
+#define REG_DSU_DCC0 (0x41002010U) /**< \brief (DSU) Debug Communication Channel 0 */
+#define REG_DSU_DCC1 (0x41002014U) /**< \brief (DSU) Debug Communication Channel 1 */
+#define REG_DSU_DID (0x41002018U) /**< \brief (DSU) Device Identification */
+#define REG_DSU_DCFG0 (0x410020F0U) /**< \brief (DSU) Device Configuration 0 */
+#define REG_DSU_DCFG1 (0x410020F4U) /**< \brief (DSU) Device Configuration 1 */
+#define REG_DSU_ENTRY0 (0x41003000U) /**< \brief (DSU) Coresight ROM Table Entry 0 */
+#define REG_DSU_ENTRY1 (0x41003004U) /**< \brief (DSU) Coresight ROM Table Entry 1 */
+#define REG_DSU_END (0x41003008U) /**< \brief (DSU) Coresight ROM Table End */
+#define REG_DSU_MEMTYPE (0x41003FCCU) /**< \brief (DSU) Coresight ROM Table Memory Type */
+#define REG_DSU_PID4 (0x41003FD0U) /**< \brief (DSU) Peripheral Identification 4 */
+#define REG_DSU_PID5 (0x41003FD4U) /**< \brief (DSU) Peripheral Identification 5 */
+#define REG_DSU_PID6 (0x41003FD8U) /**< \brief (DSU) Peripheral Identification 6 */
+#define REG_DSU_PID7 (0x41003FDCU) /**< \brief (DSU) Peripheral Identification 7 */
+#define REG_DSU_PID0 (0x41003FE0U) /**< \brief (DSU) Peripheral Identification 0 */
+#define REG_DSU_PID1 (0x41003FE4U) /**< \brief (DSU) Peripheral Identification 1 */
+#define REG_DSU_PID2 (0x41003FE8U) /**< \brief (DSU) Peripheral Identification 2 */
+#define REG_DSU_PID3 (0x41003FECU) /**< \brief (DSU) Peripheral Identification 3 */
+#define REG_DSU_CID0 (0x41003FF0U) /**< \brief (DSU) Component Identification 0 */
+#define REG_DSU_CID1 (0x41003FF4U) /**< \brief (DSU) Component Identification 1 */
+#define REG_DSU_CID2 (0x41003FF8U) /**< \brief (DSU) Component Identification 2 */
+#define REG_DSU_CID3 (0x41003FFCU) /**< \brief (DSU) Component Identification 3 */
+#else
+#define REG_DSU_CTRL (*(WoReg8 *)0x41002000U) /**< \brief (DSU) Control */
+#define REG_DSU_STATUSA (*(RwReg8 *)0x41002001U) /**< \brief (DSU) Status A */
+#define REG_DSU_STATUSB (*(RoReg8 *)0x41002002U) /**< \brief (DSU) Status B */
+#define REG_DSU_ADDR (*(RwReg *)0x41002004U) /**< \brief (DSU) Address */
+#define REG_DSU_LENGTH (*(RwReg *)0x41002008U) /**< \brief (DSU) Length */
+#define REG_DSU_DATA (*(RwReg *)0x4100200CU) /**< \brief (DSU) Data */
+#define REG_DSU_DCC0 (*(RwReg *)0x41002010U) /**< \brief (DSU) Debug Communication Channel 0 */
+#define REG_DSU_DCC1 (*(RwReg *)0x41002014U) /**< \brief (DSU) Debug Communication Channel 1 */
+#define REG_DSU_DID (*(RoReg *)0x41002018U) /**< \brief (DSU) Device Identification */
+#define REG_DSU_DCFG0 (*(RwReg *)0x410020F0U) /**< \brief (DSU) Device Configuration 0 */
+#define REG_DSU_DCFG1 (*(RwReg *)0x410020F4U) /**< \brief (DSU) Device Configuration 1 */
+#define REG_DSU_ENTRY0 (*(RoReg *)0x41003000U) /**< \brief (DSU) Coresight ROM Table Entry 0 */
+#define REG_DSU_ENTRY1 (*(RoReg *)0x41003004U) /**< \brief (DSU) Coresight ROM Table Entry 1 */
+#define REG_DSU_END (*(RoReg *)0x41003008U) /**< \brief (DSU) Coresight ROM Table End */
+#define REG_DSU_MEMTYPE (*(RoReg *)0x41003FCCU) /**< \brief (DSU) Coresight ROM Table Memory Type */
+#define REG_DSU_PID4 (*(RoReg *)0x41003FD0U) /**< \brief (DSU) Peripheral Identification 4 */
+#define REG_DSU_PID5 (*(RoReg *)0x41003FD4U) /**< \brief (DSU) Peripheral Identification 5 */
+#define REG_DSU_PID6 (*(RoReg *)0x41003FD8U) /**< \brief (DSU) Peripheral Identification 6 */
+#define REG_DSU_PID7 (*(RoReg *)0x41003FDCU) /**< \brief (DSU) Peripheral Identification 7 */
+#define REG_DSU_PID0 (*(RoReg *)0x41003FE0U) /**< \brief (DSU) Peripheral Identification 0 */
+#define REG_DSU_PID1 (*(RoReg *)0x41003FE4U) /**< \brief (DSU) Peripheral Identification 1 */
+#define REG_DSU_PID2 (*(RoReg *)0x41003FE8U) /**< \brief (DSU) Peripheral Identification 2 */
+#define REG_DSU_PID3 (*(RoReg *)0x41003FECU) /**< \brief (DSU) Peripheral Identification 3 */
+#define REG_DSU_CID0 (*(RoReg *)0x41003FF0U) /**< \brief (DSU) Component Identification 0 */
+#define REG_DSU_CID1 (*(RoReg *)0x41003FF4U) /**< \brief (DSU) Component Identification 1 */
+#define REG_DSU_CID2 (*(RoReg *)0x41003FF8U) /**< \brief (DSU) Component Identification 2 */
+#define REG_DSU_CID3 (*(RoReg *)0x41003FFCU) /**< \brief (DSU) Component Identification 3 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for DSU peripheral ========== */
+#define DSU_CLK_AHB_ID 5
+
+#endif /* _SAML22_DSU_INSTANCE_ */
diff --git a/Sensor Watch Starter Project/include/instance/eic.h b/Sensor Watch Starter Project/include/instance/eic.h new file mode 100755 index 00000000..5c5b2b10 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/eic.h @@ -0,0 +1,80 @@ +/**
+ * \file
+ *
+ * \brief Instance description for EIC
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAML22_EIC_INSTANCE_
+#define _SAML22_EIC_INSTANCE_
+
+/* ========== Register definition for EIC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_EIC_CTRLA (0x40002800U) /**< \brief (EIC) Control */
+#define REG_EIC_NMICTRL (0x40002801U) /**< \brief (EIC) NMI Control */
+#define REG_EIC_NMIFLAG (0x40002802U) /**< \brief (EIC) NMI Interrupt Flag */
+#define REG_EIC_SYNCBUSY (0x40002804U) /**< \brief (EIC) Syncbusy register */
+#define REG_EIC_EVCTRL (0x40002808U) /**< \brief (EIC) Event Control */
+#define REG_EIC_INTENCLR (0x4000280CU) /**< \brief (EIC) Interrupt Enable Clear */
+#define REG_EIC_INTENSET (0x40002810U) /**< \brief (EIC) Interrupt Enable Set */
+#define REG_EIC_INTFLAG (0x40002814U) /**< \brief (EIC) Interrupt Flag Status and Clear */
+#define REG_EIC_ASYNCH (0x40002818U) /**< \brief (EIC) EIC Asynchronous edge Detection Enable */
+#define REG_EIC_CONFIG0 (0x4000281CU) /**< \brief (EIC) Configuration 0 */
+#define REG_EIC_CONFIG1 (0x40002820U) /**< \brief (EIC) Configuration 1 */
+#else
+#define REG_EIC_CTRLA (*(RwReg8 *)0x40002800U) /**< \brief (EIC) Control */
+#define REG_EIC_NMICTRL (*(RwReg8 *)0x40002801U) /**< \brief (EIC) NMI Control */
+#define REG_EIC_NMIFLAG (*(RwReg16*)0x40002802U) /**< \brief (EIC) NMI Interrupt Flag */
+#define REG_EIC_SYNCBUSY (*(RoReg *)0x40002804U) /**< \brief (EIC) Syncbusy register */
+#define REG_EIC_EVCTRL (*(RwReg *)0x40002808U) /**< \brief (EIC) Event Control */
+#define REG_EIC_INTENCLR (*(RwReg *)0x4000280CU) /**< \brief (EIC) Interrupt Enable Clear */
+#define REG_EIC_INTENSET (*(RwReg *)0x40002810U) /**< \brief (EIC) Interrupt Enable Set */
+#define REG_EIC_INTFLAG (*(RwReg *)0x40002814U) /**< \brief (EIC) Interrupt Flag Status and Clear */
+#define REG_EIC_ASYNCH (*(RwReg *)0x40002818U) /**< \brief (EIC) EIC Asynchronous edge Detection Enable */
+#define REG_EIC_CONFIG0 (*(RwReg *)0x4000281CU) /**< \brief (EIC) Configuration 0 */
+#define REG_EIC_CONFIG1 (*(RwReg *)0x40002820U) /**< \brief (EIC) Configuration 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for EIC peripheral ========== */
+#define EIC_EXTINT_NUM 16
+#define EIC_GCLK_ID 3
+#define EIC_NUMBER_OF_CONFIG_REGS 2
+#define EIC_NUMBER_OF_INTERRUPTS 16
+
+#endif /* _SAML22_EIC_INSTANCE_ */
diff --git a/Sensor Watch Starter Project/include/instance/evsys.h b/Sensor Watch Starter Project/include/instance/evsys.h new file mode 100755 index 00000000..a3d62079 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/evsys.h @@ -0,0 +1,269 @@ +/**
+ * \file
+ *
+ * \brief Instance description for EVSYS
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAML22_EVSYS_INSTANCE_
+#define _SAML22_EVSYS_INSTANCE_
+
+/* ========== Register definition for EVSYS peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_EVSYS_CTRLA (0x42000000U) /**< \brief (EVSYS) Control */
+#define REG_EVSYS_CHSTATUS (0x4200000CU) /**< \brief (EVSYS) Channel Status */
+#define REG_EVSYS_INTENCLR (0x42000010U) /**< \brief (EVSYS) Interrupt Enable Clear */
+#define REG_EVSYS_INTENSET (0x42000014U) /**< \brief (EVSYS) Interrupt Enable Set */
+#define REG_EVSYS_INTFLAG (0x42000018U) /**< \brief (EVSYS) Interrupt Flag Status and Clear */
+#define REG_EVSYS_SWEVT (0x4200001CU) /**< \brief (EVSYS) Software Event */
+#define REG_EVSYS_CHANNEL0 (0x42000020U) /**< \brief (EVSYS) Channel 0 */
+#define REG_EVSYS_CHANNEL1 (0x42000024U) /**< \brief (EVSYS) Channel 1 */
+#define REG_EVSYS_CHANNEL2 (0x42000028U) /**< \brief (EVSYS) Channel 2 */
+#define REG_EVSYS_CHANNEL3 (0x4200002CU) /**< \brief (EVSYS) Channel 3 */
+#define REG_EVSYS_CHANNEL4 (0x42000030U) /**< \brief (EVSYS) Channel 4 */
+#define REG_EVSYS_CHANNEL5 (0x42000034U) /**< \brief (EVSYS) Channel 5 */
+#define REG_EVSYS_CHANNEL6 (0x42000038U) /**< \brief (EVSYS) Channel 6 */
+#define REG_EVSYS_CHANNEL7 (0x4200003CU) /**< \brief (EVSYS) Channel 7 */
+#define REG_EVSYS_USER0 (0x42000080U) /**< \brief (EVSYS) User Multiplexer 0 */
+#define REG_EVSYS_USER1 (0x42000084U) /**< \brief (EVSYS) User Multiplexer 1 */
+#define REG_EVSYS_USER2 (0x42000088U) /**< \brief (EVSYS) User Multiplexer 2 */
+#define REG_EVSYS_USER3 (0x4200008CU) /**< \brief (EVSYS) User Multiplexer 3 */
+#define REG_EVSYS_USER4 (0x42000090U) /**< \brief (EVSYS) User Multiplexer 4 */
+#define REG_EVSYS_USER5 (0x42000094U) /**< \brief (EVSYS) User Multiplexer 5 */
+#define REG_EVSYS_USER6 (0x42000098U) /**< \brief (EVSYS) User Multiplexer 6 */
+#define REG_EVSYS_USER7 (0x4200009CU) /**< \brief (EVSYS) User Multiplexer 7 */
+#define REG_EVSYS_USER8 (0x420000A0U) /**< \brief (EVSYS) User Multiplexer 8 */
+#define REG_EVSYS_USER9 (0x420000A4U) /**< \brief (EVSYS) User Multiplexer 9 */
+#define REG_EVSYS_USER10 (0x420000A8U) /**< \brief (EVSYS) User Multiplexer 10 */
+#define REG_EVSYS_USER11 (0x420000ACU) /**< \brief (EVSYS) User Multiplexer 11 */
+#define REG_EVSYS_USER12 (0x420000B0U) /**< \brief (EVSYS) User Multiplexer 12 */
+#define REG_EVSYS_USER13 (0x420000B4U) /**< \brief (EVSYS) User Multiplexer 13 */
+#define REG_EVSYS_USER14 (0x420000B8U) /**< \brief (EVSYS) User Multiplexer 14 */
+#define REG_EVSYS_USER15 (0x420000BCU) /**< \brief (EVSYS) User Multiplexer 15 */
+#define REG_EVSYS_USER16 (0x420000C0U) /**< \brief (EVSYS) User Multiplexer 16 */
+#define REG_EVSYS_USER17 (0x420000C4U) /**< \brief (EVSYS) User Multiplexer 17 */
+#define REG_EVSYS_USER18 (0x420000C8U) /**< \brief (EVSYS) User Multiplexer 18 */
+#define REG_EVSYS_USER19 (0x420000CCU) /**< \brief (EVSYS) User Multiplexer 19 */
+#define REG_EVSYS_USER20 (0x420000D0U) /**< \brief (EVSYS) User Multiplexer 20 */
+#define REG_EVSYS_USER21 (0x420000D4U) /**< \brief (EVSYS) User Multiplexer 21 */
+#define REG_EVSYS_USER22 (0x420000D8U) /**< \brief (EVSYS) User Multiplexer 22 */
+#define REG_EVSYS_USER23 (0x420000DCU) /**< \brief (EVSYS) User Multiplexer 23 */
+#define REG_EVSYS_USER24 (0x420000E0U) /**< \brief (EVSYS) User Multiplexer 24 */
+#define REG_EVSYS_USER25 (0x420000E4U) /**< \brief (EVSYS) User Multiplexer 25 */
+#define REG_EVSYS_USER26 (0x420000E8U) /**< \brief (EVSYS) User Multiplexer 26 */
+#define REG_EVSYS_USER27 (0x420000ECU) /**< \brief (EVSYS) User Multiplexer 27 */
+#define REG_EVSYS_USER28 (0x420000F0U) /**< \brief (EVSYS) User Multiplexer 28 */
+#define REG_EVSYS_USER29 (0x420000F4U) /**< \brief (EVSYS) User Multiplexer 29 */
+#define REG_EVSYS_USER30 (0x420000F8U) /**< \brief (EVSYS) User Multiplexer 30 */
+#else
+#define REG_EVSYS_CTRLA (*(RwReg8 *)0x42000000U) /**< \brief (EVSYS) Control */
+#define REG_EVSYS_CHSTATUS (*(RoReg *)0x4200000CU) /**< \brief (EVSYS) Channel Status */
+#define REG_EVSYS_INTENCLR (*(RwReg *)0x42000010U) /**< \brief (EVSYS) Interrupt Enable Clear */
+#define REG_EVSYS_INTENSET (*(RwReg *)0x42000014U) /**< \brief (EVSYS) Interrupt Enable Set */
+#define REG_EVSYS_INTFLAG (*(RwReg *)0x42000018U) /**< \brief (EVSYS) Interrupt Flag Status and Clear */
+#define REG_EVSYS_SWEVT (*(WoReg *)0x4200001CU) /**< \brief (EVSYS) Software Event */
+#define REG_EVSYS_CHANNEL0 (*(RwReg *)0x42000020U) /**< \brief (EVSYS) Channel 0 */
+#define REG_EVSYS_CHANNEL1 (*(RwReg *)0x42000024U) /**< \brief (EVSYS) Channel 1 */
+#define REG_EVSYS_CHANNEL2 (*(RwReg *)0x42000028U) /**< \brief (EVSYS) Channel 2 */
+#define REG_EVSYS_CHANNEL3 (*(RwReg *)0x4200002CU) /**< \brief (EVSYS) Channel 3 */
+#define REG_EVSYS_CHANNEL4 (*(RwReg *)0x42000030U) /**< \brief (EVSYS) Channel 4 */
+#define REG_EVSYS_CHANNEL5 (*(RwReg *)0x42000034U) /**< \brief (EVSYS) Channel 5 */
+#define REG_EVSYS_CHANNEL6 (*(RwReg *)0x42000038U) /**< \brief (EVSYS) Channel 6 */
+#define REG_EVSYS_CHANNEL7 (*(RwReg *)0x4200003CU) /**< \brief (EVSYS) Channel 7 */
+#define REG_EVSYS_USER0 (*(RwReg *)0x42000080U) /**< \brief (EVSYS) User Multiplexer 0 */
+#define REG_EVSYS_USER1 (*(RwReg *)0x42000084U) /**< \brief (EVSYS) User Multiplexer 1 */
+#define REG_EVSYS_USER2 (*(RwReg *)0x42000088U) /**< \brief (EVSYS) User Multiplexer 2 */
+#define REG_EVSYS_USER3 (*(RwReg *)0x4200008CU) /**< \brief (EVSYS) User Multiplexer 3 */
+#define REG_EVSYS_USER4 (*(RwReg *)0x42000090U) /**< \brief (EVSYS) User Multiplexer 4 */
+#define REG_EVSYS_USER5 (*(RwReg *)0x42000094U) /**< \brief (EVSYS) User Multiplexer 5 */
+#define REG_EVSYS_USER6 (*(RwReg *)0x42000098U) /**< \brief (EVSYS) User Multiplexer 6 */
+#define REG_EVSYS_USER7 (*(RwReg *)0x4200009CU) /**< \brief (EVSYS) User Multiplexer 7 */
+#define REG_EVSYS_USER8 (*(RwReg *)0x420000A0U) /**< \brief (EVSYS) User Multiplexer 8 */
+#define REG_EVSYS_USER9 (*(RwReg *)0x420000A4U) /**< \brief (EVSYS) User Multiplexer 9 */
+#define REG_EVSYS_USER10 (*(RwReg *)0x420000A8U) /**< \brief (EVSYS) User Multiplexer 10 */
+#define REG_EVSYS_USER11 (*(RwReg *)0x420000ACU) /**< \brief (EVSYS) User Multiplexer 11 */
+#define REG_EVSYS_USER12 (*(RwReg *)0x420000B0U) /**< \brief (EVSYS) User Multiplexer 12 */
+#define REG_EVSYS_USER13 (*(RwReg *)0x420000B4U) /**< \brief (EVSYS) User Multiplexer 13 */
+#define REG_EVSYS_USER14 (*(RwReg *)0x420000B8U) /**< \brief (EVSYS) User Multiplexer 14 */
+#define REG_EVSYS_USER15 (*(RwReg *)0x420000BCU) /**< \brief (EVSYS) User Multiplexer 15 */
+#define REG_EVSYS_USER16 (*(RwReg *)0x420000C0U) /**< \brief (EVSYS) User Multiplexer 16 */
+#define REG_EVSYS_USER17 (*(RwReg *)0x420000C4U) /**< \brief (EVSYS) User Multiplexer 17 */
+#define REG_EVSYS_USER18 (*(RwReg *)0x420000C8U) /**< \brief (EVSYS) User Multiplexer 18 */
+#define REG_EVSYS_USER19 (*(RwReg *)0x420000CCU) /**< \brief (EVSYS) User Multiplexer 19 */
+#define REG_EVSYS_USER20 (*(RwReg *)0x420000D0U) /**< \brief (EVSYS) User Multiplexer 20 */
+#define REG_EVSYS_USER21 (*(RwReg *)0x420000D4U) /**< \brief (EVSYS) User Multiplexer 21 */
+#define REG_EVSYS_USER22 (*(RwReg *)0x420000D8U) /**< \brief (EVSYS) User Multiplexer 22 */
+#define REG_EVSYS_USER23 (*(RwReg *)0x420000DCU) /**< \brief (EVSYS) User Multiplexer 23 */
+#define REG_EVSYS_USER24 (*(RwReg *)0x420000E0U) /**< \brief (EVSYS) User Multiplexer 24 */
+#define REG_EVSYS_USER25 (*(RwReg *)0x420000E4U) /**< \brief (EVSYS) User Multiplexer 25 */
+#define REG_EVSYS_USER26 (*(RwReg *)0x420000E8U) /**< \brief (EVSYS) User Multiplexer 26 */
+#define REG_EVSYS_USER27 (*(RwReg *)0x420000ECU) /**< \brief (EVSYS) User Multiplexer 27 */
+#define REG_EVSYS_USER28 (*(RwReg *)0x420000F0U) /**< \brief (EVSYS) User Multiplexer 28 */
+#define REG_EVSYS_USER29 (*(RwReg *)0x420000F4U) /**< \brief (EVSYS) User Multiplexer 29 */
+#define REG_EVSYS_USER30 (*(RwReg *)0x420000F8U) /**< \brief (EVSYS) User Multiplexer 30 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for EVSYS peripheral ========== */
+#define EVSYS_CHANNELS 8 // Number of Channels
+#define EVSYS_CHANNELS_BITS 3 // Number of bits to select Channel
+#define EVSYS_CHANNELS_MSB 7 // Number of Channels - 1
+#define EVSYS_EXTEVT_NUM 0 // Number of External Event Generators
+#define EVSYS_GCLK_ID_0 7
+#define EVSYS_GCLK_ID_1 8
+#define EVSYS_GCLK_ID_2 9
+#define EVSYS_GCLK_ID_3 10
+#define EVSYS_GCLK_ID_4 11
+#define EVSYS_GCLK_ID_5 12
+#define EVSYS_GCLK_ID_6 13
+#define EVSYS_GCLK_ID_7 14
+#define EVSYS_GCLK_ID_LSB 7
+#define EVSYS_GCLK_ID_MSB 14
+#define EVSYS_GCLK_ID_SIZE 8
+#define EVSYS_GENERATORS 71 // Total Number of Event Generators
+#define EVSYS_GENERATORS_BITS 7 // Number of bits to select Event Generator
+#define EVSYS_USERS 31 // Total Number of Event Users
+#define EVSYS_USERS_BITS 5 // Number of bits to select Event User
+
+// GENERATORS
+#define EVSYS_ID_GEN_OSCCTRL_XOSC_FAIL 1
+#define EVSYS_ID_GEN_OSC32KCTRL_XOSC32K_FAIL 2
+#define EVSYS_ID_GEN_RTC_CMP_0 3
+#define EVSYS_ID_GEN_RTC_CMP_1 4
+#define EVSYS_ID_GEN_RTC_TAMPER 5
+#define EVSYS_ID_GEN_RTC_OVF 6
+#define EVSYS_ID_GEN_RTC_PER_0 7
+#define EVSYS_ID_GEN_RTC_PER_1 8
+#define EVSYS_ID_GEN_RTC_PER_2 9
+#define EVSYS_ID_GEN_RTC_PER_3 10
+#define EVSYS_ID_GEN_RTC_PER_4 11
+#define EVSYS_ID_GEN_RTC_PER_5 12
+#define EVSYS_ID_GEN_RTC_PER_6 13
+#define EVSYS_ID_GEN_RTC_PER_7 14
+#define EVSYS_ID_GEN_EIC_EXTINT_0 15
+#define EVSYS_ID_GEN_EIC_EXTINT_1 16
+#define EVSYS_ID_GEN_EIC_EXTINT_2 17
+#define EVSYS_ID_GEN_EIC_EXTINT_3 18
+#define EVSYS_ID_GEN_EIC_EXTINT_4 19
+#define EVSYS_ID_GEN_EIC_EXTINT_5 20
+#define EVSYS_ID_GEN_EIC_EXTINT_6 21
+#define EVSYS_ID_GEN_EIC_EXTINT_7 22
+#define EVSYS_ID_GEN_EIC_EXTINT_8 23
+#define EVSYS_ID_GEN_EIC_EXTINT_9 24
+#define EVSYS_ID_GEN_EIC_EXTINT_10 25
+#define EVSYS_ID_GEN_EIC_EXTINT_11 26
+#define EVSYS_ID_GEN_EIC_EXTINT_12 27
+#define EVSYS_ID_GEN_EIC_EXTINT_13 28
+#define EVSYS_ID_GEN_EIC_EXTINT_14 29
+#define EVSYS_ID_GEN_EIC_EXTINT_15 30
+#define EVSYS_ID_GEN_DMAC_CH_0 31
+#define EVSYS_ID_GEN_DMAC_CH_1 32
+#define EVSYS_ID_GEN_DMAC_CH_2 33
+#define EVSYS_ID_GEN_DMAC_CH_3 34
+#define EVSYS_ID_GEN_TCC0_OVF 35
+#define EVSYS_ID_GEN_TCC0_TRG 36
+#define EVSYS_ID_GEN_TCC0_CNT 37
+#define EVSYS_ID_GEN_TCC0_MCX_0 38
+#define EVSYS_ID_GEN_TCC0_MCX_1 39
+#define EVSYS_ID_GEN_TCC0_MCX_2 40
+#define EVSYS_ID_GEN_TCC0_MCX_3 41
+#define EVSYS_ID_GEN_TC0_OVF 42
+#define EVSYS_ID_GEN_TC0_MCX_0 43
+#define EVSYS_ID_GEN_TC0_MCX_1 44
+#define EVSYS_ID_GEN_TC1_OVF 45
+#define EVSYS_ID_GEN_TC1_MCX_0 46
+#define EVSYS_ID_GEN_TC1_MCX_1 47
+#define EVSYS_ID_GEN_TC2_OVF 48
+#define EVSYS_ID_GEN_TC2_MCX_0 49
+#define EVSYS_ID_GEN_TC2_MCX_1 50
+#define EVSYS_ID_GEN_TC3_OVF 51
+#define EVSYS_ID_GEN_TC3_MCX_0 52
+#define EVSYS_ID_GEN_TC3_MCX_1 53
+#define EVSYS_ID_GEN_ADC_RESRDY 54
+#define EVSYS_ID_GEN_ADC_WINMON 55
+#define EVSYS_ID_GEN_AC_COMP_0 56
+#define EVSYS_ID_GEN_AC_COMP_1 57
+#define EVSYS_ID_GEN_AC_WIN_0 58
+#define EVSYS_ID_GEN_PTC_EOC 59
+#define EVSYS_ID_GEN_PTC_WCOMP 60
+#define EVSYS_ID_GEN_SLCD_FC0OVERFLOW 61
+#define EVSYS_ID_GEN_SLCD_FC1OVERFLOW 62
+#define EVSYS_ID_GEN_SLCD_FC2OVERFLOW 63
+#define EVSYS_ID_GEN_SLCD_DT 64
+#define EVSYS_ID_GEN_TRNG_READY 65
+#define EVSYS_ID_GEN_CCL_LUTOUT_0 66
+#define EVSYS_ID_GEN_CCL_LUTOUT_1 67
+#define EVSYS_ID_GEN_CCL_LUTOUT_2 68
+#define EVSYS_ID_GEN_CCL_LUTOUT_3 69
+#define EVSYS_ID_GEN_PAC_ACCERR 70
+#define EVSYS_ID_GEN_TAL_BRK 71
+
+// USERS
+#define EVSYS_ID_USER_RTC_TAMPER 0
+#define EVSYS_ID_USER_PORT_EV_0 1
+#define EVSYS_ID_USER_PORT_EV_1 2
+#define EVSYS_ID_USER_PORT_EV_2 3
+#define EVSYS_ID_USER_PORT_EV_3 4
+#define EVSYS_ID_USER_DMAC_CH_0 5
+#define EVSYS_ID_USER_DMAC_CH_1 6
+#define EVSYS_ID_USER_DMAC_CH_2 7
+#define EVSYS_ID_USER_DMAC_CH_3 8
+#define EVSYS_ID_USER_TCC0_EV_0 9
+#define EVSYS_ID_USER_TCC0_EV_1 10
+#define EVSYS_ID_USER_TCC0_MC_0 11
+#define EVSYS_ID_USER_TCC0_MC_1 12
+#define EVSYS_ID_USER_TCC0_MC_2 13
+#define EVSYS_ID_USER_TCC0_MC_3 14
+#define EVSYS_ID_USER_TC0_EVU 15
+#define EVSYS_ID_USER_TC1_EVU 16
+#define EVSYS_ID_USER_TC2_EVU 17
+#define EVSYS_ID_USER_TC3_EVU 18
+#define EVSYS_ID_USER_ADC_START 19
+#define EVSYS_ID_USER_ADC_SYNC 20
+#define EVSYS_ID_USER_AC_SOC_0 21
+#define EVSYS_ID_USER_AC_SOC_1 22
+#define EVSYS_ID_USER_PTC_STCONV 23
+#define EVSYS_ID_USER_CCL_LUTIN_0 24
+#define EVSYS_ID_USER_CCL_LUTIN_1 25
+#define EVSYS_ID_USER_CCL_LUTIN_2 26
+#define EVSYS_ID_USER_CCL_LUTIN_3 27
+#define EVSYS_ID_USER_TAL_BRK 28
+#define EVSYS_ID_USER_MTB_START 29
+#define EVSYS_ID_USER_MTB_STOP 30
+
+#endif /* _SAML22_EVSYS_INSTANCE_ */
diff --git a/Sensor Watch Starter Project/include/instance/freqm.h b/Sensor Watch Starter Project/include/instance/freqm.h new file mode 100755 index 00000000..63b21c17 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/freqm.h @@ -0,0 +1,74 @@ +/**
+ * \file
+ *
+ * \brief Instance description for FREQM
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAML22_FREQM_INSTANCE_
+#define _SAML22_FREQM_INSTANCE_
+
+/* ========== Register definition for FREQM peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_FREQM_CTRLA (0x40002C00U) /**< \brief (FREQM) Control A Register */
+#define REG_FREQM_CTRLB (0x40002C01U) /**< \brief (FREQM) Control B Register */
+#define REG_FREQM_CFGA (0x40002C02U) /**< \brief (FREQM) Config A register */
+#define REG_FREQM_INTENCLR (0x40002C08U) /**< \brief (FREQM) Interrupt Enable Clear Register */
+#define REG_FREQM_INTENSET (0x40002C09U) /**< \brief (FREQM) Interrupt Enable Set Register */
+#define REG_FREQM_INTFLAG (0x40002C0AU) /**< \brief (FREQM) Interrupt Flag Register */
+#define REG_FREQM_STATUS (0x40002C0BU) /**< \brief (FREQM) Status Register */
+#define REG_FREQM_SYNCBUSY (0x40002C0CU) /**< \brief (FREQM) Synchronization Busy Register */
+#define REG_FREQM_VALUE (0x40002C10U) /**< \brief (FREQM) Count Value Register */
+#else
+#define REG_FREQM_CTRLA (*(RwReg8 *)0x40002C00U) /**< \brief (FREQM) Control A Register */
+#define REG_FREQM_CTRLB (*(WoReg8 *)0x40002C01U) /**< \brief (FREQM) Control B Register */
+#define REG_FREQM_CFGA (*(RwReg16*)0x40002C02U) /**< \brief (FREQM) Config A register */
+#define REG_FREQM_INTENCLR (*(RwReg8 *)0x40002C08U) /**< \brief (FREQM) Interrupt Enable Clear Register */
+#define REG_FREQM_INTENSET (*(RwReg8 *)0x40002C09U) /**< \brief (FREQM) Interrupt Enable Set Register */
+#define REG_FREQM_INTFLAG (*(RwReg8 *)0x40002C0AU) /**< \brief (FREQM) Interrupt Flag Register */
+#define REG_FREQM_STATUS (*(RwReg8 *)0x40002C0BU) /**< \brief (FREQM) Status Register */
+#define REG_FREQM_SYNCBUSY (*(RoReg *)0x40002C0CU) /**< \brief (FREQM) Synchronization Busy Register */
+#define REG_FREQM_VALUE (*(RoReg *)0x40002C10U) /**< \brief (FREQM) Count Value Register */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for FREQM peripheral ========== */
+#define FREQM_GCLK_ID_MSR 4 // Index of measure generic clock
+#define FREQM_GCLK_ID_REF 5 // Index of reference generic clock
+
+#endif /* _SAML22_FREQM_INSTANCE_ */
diff --git a/Sensor Watch Starter Project/include/instance/gclk.h b/Sensor Watch Starter Project/include/instance/gclk.h new file mode 100755 index 00000000..7453e366 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/gclk.h @@ -0,0 +1,144 @@ +/**
+ * \file
+ *
+ * \brief Instance description for GCLK
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAML22_GCLK_INSTANCE_
+#define _SAML22_GCLK_INSTANCE_
+
+/* ========== Register definition for GCLK peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_GCLK_CTRLA (0x40001C00U) /**< \brief (GCLK) Control */
+#define REG_GCLK_SYNCBUSY (0x40001C04U) /**< \brief (GCLK) Synchronization Busy */
+#define REG_GCLK_GENCTRL0 (0x40001C20U) /**< \brief (GCLK) Generic Clock Generator Control 0 */
+#define REG_GCLK_GENCTRL1 (0x40001C24U) /**< \brief (GCLK) Generic Clock Generator Control 1 */
+#define REG_GCLK_GENCTRL2 (0x40001C28U) /**< \brief (GCLK) Generic Clock Generator Control 2 */
+#define REG_GCLK_GENCTRL3 (0x40001C2CU) /**< \brief (GCLK) Generic Clock Generator Control 3 */
+#define REG_GCLK_GENCTRL4 (0x40001C30U) /**< \brief (GCLK) Generic Clock Generator Control 4 */
+#define REG_GCLK_PCHCTRL0 (0x40001C80U) /**< \brief (GCLK) Peripheral Clock Control 0 */
+#define REG_GCLK_PCHCTRL1 (0x40001C84U) /**< \brief (GCLK) Peripheral Clock Control 1 */
+#define REG_GCLK_PCHCTRL2 (0x40001C88U) /**< \brief (GCLK) Peripheral Clock Control 2 */
+#define REG_GCLK_PCHCTRL3 (0x40001C8CU) /**< \brief (GCLK) Peripheral Clock Control 3 */
+#define REG_GCLK_PCHCTRL4 (0x40001C90U) /**< \brief (GCLK) Peripheral Clock Control 4 */
+#define REG_GCLK_PCHCTRL5 (0x40001C94U) /**< \brief (GCLK) Peripheral Clock Control 5 */
+#define REG_GCLK_PCHCTRL6 (0x40001C98U) /**< \brief (GCLK) Peripheral Clock Control 6 */
+#define REG_GCLK_PCHCTRL7 (0x40001C9CU) /**< \brief (GCLK) Peripheral Clock Control 7 */
+#define REG_GCLK_PCHCTRL8 (0x40001CA0U) /**< \brief (GCLK) Peripheral Clock Control 8 */
+#define REG_GCLK_PCHCTRL9 (0x40001CA4U) /**< \brief (GCLK) Peripheral Clock Control 9 */
+#define REG_GCLK_PCHCTRL10 (0x40001CA8U) /**< \brief (GCLK) Peripheral Clock Control 10 */
+#define REG_GCLK_PCHCTRL11 (0x40001CACU) /**< \brief (GCLK) Peripheral Clock Control 11 */
+#define REG_GCLK_PCHCTRL12 (0x40001CB0U) /**< \brief (GCLK) Peripheral Clock Control 12 */
+#define REG_GCLK_PCHCTRL13 (0x40001CB4U) /**< \brief (GCLK) Peripheral Clock Control 13 */
+#define REG_GCLK_PCHCTRL14 (0x40001CB8U) /**< \brief (GCLK) Peripheral Clock Control 14 */
+#define REG_GCLK_PCHCTRL15 (0x40001CBCU) /**< \brief (GCLK) Peripheral Clock Control 15 */
+#define REG_GCLK_PCHCTRL16 (0x40001CC0U) /**< \brief (GCLK) Peripheral Clock Control 16 */
+#define REG_GCLK_PCHCTRL17 (0x40001CC4U) /**< \brief (GCLK) Peripheral Clock Control 17 */
+#define REG_GCLK_PCHCTRL18 (0x40001CC8U) /**< \brief (GCLK) Peripheral Clock Control 18 */
+#define REG_GCLK_PCHCTRL19 (0x40001CCCU) /**< \brief (GCLK) Peripheral Clock Control 19 */
+#define REG_GCLK_PCHCTRL20 (0x40001CD0U) /**< \brief (GCLK) Peripheral Clock Control 20 */
+#define REG_GCLK_PCHCTRL21 (0x40001CD4U) /**< \brief (GCLK) Peripheral Clock Control 21 */
+#define REG_GCLK_PCHCTRL22 (0x40001CD8U) /**< \brief (GCLK) Peripheral Clock Control 22 */
+#define REG_GCLK_PCHCTRL23 (0x40001CDCU) /**< \brief (GCLK) Peripheral Clock Control 23 */
+#define REG_GCLK_PCHCTRL24 (0x40001CE0U) /**< \brief (GCLK) Peripheral Clock Control 24 */
+#define REG_GCLK_PCHCTRL25 (0x40001CE4U) /**< \brief (GCLK) Peripheral Clock Control 25 */
+#define REG_GCLK_PCHCTRL26 (0x40001CE8U) /**< \brief (GCLK) Peripheral Clock Control 26 */
+#define REG_GCLK_PCHCTRL27 (0x40001CECU) /**< \brief (GCLK) Peripheral Clock Control 27 */
+#define REG_GCLK_PCHCTRL28 (0x40001CF0U) /**< \brief (GCLK) Peripheral Clock Control 28 */
+#define REG_GCLK_PCHCTRL29 (0x40001CF4U) /**< \brief (GCLK) Peripheral Clock Control 29 */
+#else
+#define REG_GCLK_CTRLA (*(RwReg8 *)0x40001C00U) /**< \brief (GCLK) Control */
+#define REG_GCLK_SYNCBUSY (*(RoReg *)0x40001C04U) /**< \brief (GCLK) Synchronization Busy */
+#define REG_GCLK_GENCTRL0 (*(RwReg *)0x40001C20U) /**< \brief (GCLK) Generic Clock Generator Control 0 */
+#define REG_GCLK_GENCTRL1 (*(RwReg *)0x40001C24U) /**< \brief (GCLK) Generic Clock Generator Control 1 */
+#define REG_GCLK_GENCTRL2 (*(RwReg *)0x40001C28U) /**< \brief (GCLK) Generic Clock Generator Control 2 */
+#define REG_GCLK_GENCTRL3 (*(RwReg *)0x40001C2CU) /**< \brief (GCLK) Generic Clock Generator Control 3 */
+#define REG_GCLK_GENCTRL4 (*(RwReg *)0x40001C30U) /**< \brief (GCLK) Generic Clock Generator Control 4 */
+#define REG_GCLK_PCHCTRL0 (*(RwReg *)0x40001C80U) /**< \brief (GCLK) Peripheral Clock Control 0 */
+#define REG_GCLK_PCHCTRL1 (*(RwReg *)0x40001C84U) /**< \brief (GCLK) Peripheral Clock Control 1 */
+#define REG_GCLK_PCHCTRL2 (*(RwReg *)0x40001C88U) /**< \brief (GCLK) Peripheral Clock Control 2 */
+#define REG_GCLK_PCHCTRL3 (*(RwReg *)0x40001C8CU) /**< \brief (GCLK) Peripheral Clock Control 3 */
+#define REG_GCLK_PCHCTRL4 (*(RwReg *)0x40001C90U) /**< \brief (GCLK) Peripheral Clock Control 4 */
+#define REG_GCLK_PCHCTRL5 (*(RwReg *)0x40001C94U) /**< \brief (GCLK) Peripheral Clock Control 5 */
+#define REG_GCLK_PCHCTRL6 (*(RwReg *)0x40001C98U) /**< \brief (GCLK) Peripheral Clock Control 6 */
+#define REG_GCLK_PCHCTRL7 (*(RwReg *)0x40001C9CU) /**< \brief (GCLK) Peripheral Clock Control 7 */
+#define REG_GCLK_PCHCTRL8 (*(RwReg *)0x40001CA0U) /**< \brief (GCLK) Peripheral Clock Control 8 */
+#define REG_GCLK_PCHCTRL9 (*(RwReg *)0x40001CA4U) /**< \brief (GCLK) Peripheral Clock Control 9 */
+#define REG_GCLK_PCHCTRL10 (*(RwReg *)0x40001CA8U) /**< \brief (GCLK) Peripheral Clock Control 10 */
+#define REG_GCLK_PCHCTRL11 (*(RwReg *)0x40001CACU) /**< \brief (GCLK) Peripheral Clock Control 11 */
+#define REG_GCLK_PCHCTRL12 (*(RwReg *)0x40001CB0U) /**< \brief (GCLK) Peripheral Clock Control 12 */
+#define REG_GCLK_PCHCTRL13 (*(RwReg *)0x40001CB4U) /**< \brief (GCLK) Peripheral Clock Control 13 */
+#define REG_GCLK_PCHCTRL14 (*(RwReg *)0x40001CB8U) /**< \brief (GCLK) Peripheral Clock Control 14 */
+#define REG_GCLK_PCHCTRL15 (*(RwReg *)0x40001CBCU) /**< \brief (GCLK) Peripheral Clock Control 15 */
+#define REG_GCLK_PCHCTRL16 (*(RwReg *)0x40001CC0U) /**< \brief (GCLK) Peripheral Clock Control 16 */
+#define REG_GCLK_PCHCTRL17 (*(RwReg *)0x40001CC4U) /**< \brief (GCLK) Peripheral Clock Control 17 */
+#define REG_GCLK_PCHCTRL18 (*(RwReg *)0x40001CC8U) /**< \brief (GCLK) Peripheral Clock Control 18 */
+#define REG_GCLK_PCHCTRL19 (*(RwReg *)0x40001CCCU) /**< \brief (GCLK) Peripheral Clock Control 19 */
+#define REG_GCLK_PCHCTRL20 (*(RwReg *)0x40001CD0U) /**< \brief (GCLK) Peripheral Clock Control 20 */
+#define REG_GCLK_PCHCTRL21 (*(RwReg *)0x40001CD4U) /**< \brief (GCLK) Peripheral Clock Control 21 */
+#define REG_GCLK_PCHCTRL22 (*(RwReg *)0x40001CD8U) /**< \brief (GCLK) Peripheral Clock Control 22 */
+#define REG_GCLK_PCHCTRL23 (*(RwReg *)0x40001CDCU) /**< \brief (GCLK) Peripheral Clock Control 23 */
+#define REG_GCLK_PCHCTRL24 (*(RwReg *)0x40001CE0U) /**< \brief (GCLK) Peripheral Clock Control 24 */
+#define REG_GCLK_PCHCTRL25 (*(RwReg *)0x40001CE4U) /**< \brief (GCLK) Peripheral Clock Control 25 */
+#define REG_GCLK_PCHCTRL26 (*(RwReg *)0x40001CE8U) /**< \brief (GCLK) Peripheral Clock Control 26 */
+#define REG_GCLK_PCHCTRL27 (*(RwReg *)0x40001CECU) /**< \brief (GCLK) Peripheral Clock Control 27 */
+#define REG_GCLK_PCHCTRL28 (*(RwReg *)0x40001CF0U) /**< \brief (GCLK) Peripheral Clock Control 28 */
+#define REG_GCLK_PCHCTRL29 (*(RwReg *)0x40001CF4U) /**< \brief (GCLK) Peripheral Clock Control 29 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for GCLK peripheral ========== */
+#define GCLK_GENDIV_BITS 16
+#define GCLK_GEN_BITS 3
+#define GCLK_GEN_NUM 5 // Number of Generic Clock Generators
+#define GCLK_GEN_NUM_MSB 4 // Number of Generic Clock Generators - 1
+#define GCLK_GEN_SOURCE_NUM_MSB 7 // Number of Generic Clock Sources - 1
+#define GCLK_NUM 30 // Number of Generic Clock Users
+#define GCLK_SOURCE_BITS 3
+#define GCLK_SOURCE_DFLL48M 6
+#define GCLK_SOURCE_FDPLL 7
+#define GCLK_SOURCE_GCLKGEN1 2
+#define GCLK_SOURCE_GCLKIN 1
+#define GCLK_SOURCE_NUM 8 // Number of Generic Clock Sources
+#define GCLK_SOURCE_OSCULP32K 3
+#define GCLK_SOURCE_OSC16M 5
+#define GCLK_SOURCE_XOSC 0
+#define GCLK_SOURCE_XOSC32K 4
+
+#endif /* _SAML22_GCLK_INSTANCE_ */
diff --git a/Sensor Watch Starter Project/include/instance/mclk.h b/Sensor Watch Starter Project/include/instance/mclk.h new file mode 100755 index 00000000..25115a05 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/mclk.h @@ -0,0 +1,76 @@ +/**
+ * \file
+ *
+ * \brief Instance description for MCLK
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAML22_MCLK_INSTANCE_
+#define _SAML22_MCLK_INSTANCE_
+
+/* ========== Register definition for MCLK peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_MCLK_INTENCLR (0x40000801U) /**< \brief (MCLK) Interrupt Enable Clear */
+#define REG_MCLK_INTENSET (0x40000802U) /**< \brief (MCLK) Interrupt Enable Set */
+#define REG_MCLK_INTFLAG (0x40000803U) /**< \brief (MCLK) Interrupt Flag Status and Clear */
+#define REG_MCLK_CPUDIV (0x40000804U) /**< \brief (MCLK) CPU Clock Division */
+#define REG_MCLK_BUPDIV (0x40000806U) /**< \brief (MCLK) Backup Clock Division */
+#define REG_MCLK_AHBMASK (0x40000810U) /**< \brief (MCLK) AHB Mask */
+#define REG_MCLK_APBAMASK (0x40000814U) /**< \brief (MCLK) APBA Mask */
+#define REG_MCLK_APBBMASK (0x40000818U) /**< \brief (MCLK) APBB Mask */
+#define REG_MCLK_APBCMASK (0x4000081CU) /**< \brief (MCLK) APBC Mask */
+#else
+#define REG_MCLK_INTENCLR (*(RwReg8 *)0x40000801U) /**< \brief (MCLK) Interrupt Enable Clear */
+#define REG_MCLK_INTENSET (*(RwReg8 *)0x40000802U) /**< \brief (MCLK) Interrupt Enable Set */
+#define REG_MCLK_INTFLAG (*(RwReg8 *)0x40000803U) /**< \brief (MCLK) Interrupt Flag Status and Clear */
+#define REG_MCLK_CPUDIV (*(RwReg8 *)0x40000804U) /**< \brief (MCLK) CPU Clock Division */
+#define REG_MCLK_BUPDIV (*(RwReg8 *)0x40000806U) /**< \brief (MCLK) Backup Clock Division */
+#define REG_MCLK_AHBMASK (*(RwReg *)0x40000810U) /**< \brief (MCLK) AHB Mask */
+#define REG_MCLK_APBAMASK (*(RwReg *)0x40000814U) /**< \brief (MCLK) APBA Mask */
+#define REG_MCLK_APBBMASK (*(RwReg *)0x40000818U) /**< \brief (MCLK) APBB Mask */
+#define REG_MCLK_APBCMASK (*(RwReg *)0x4000081CU) /**< \brief (MCLK) APBC Mask */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for MCLK peripheral ========== */
+#define MCLK_BUPDIV_IMPLEMENTED 1
+#define MCLK_CTRLA_MCSEL_GCLK 1
+#define MCLK_CTRLA_MCSEL_OSC8M 0
+#define MCLK_MCLK_CLK_APB_NUM 3
+
+#endif /* _SAML22_MCLK_INSTANCE_ */
diff --git a/Sensor Watch Starter Project/include/instance/mtb.h b/Sensor Watch Starter Project/include/instance/mtb.h new file mode 100755 index 00000000..09851e4e --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/mtb.h @@ -0,0 +1,103 @@ +/**
+ * \file
+ *
+ * \brief Instance description for MTB
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAML22_MTB_INSTANCE_
+#define _SAML22_MTB_INSTANCE_
+
+/* ========== Register definition for MTB peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_MTB_POSITION (0x4100A000U) /**< \brief (MTB) MTB Position */
+#define REG_MTB_MASTER (0x4100A004U) /**< \brief (MTB) MTB Master */
+#define REG_MTB_FLOW (0x4100A008U) /**< \brief (MTB) MTB Flow */
+#define REG_MTB_BASE (0x4100A00CU) /**< \brief (MTB) MTB Base */
+#define REG_MTB_ITCTRL (0x4100AF00U) /**< \brief (MTB) MTB Integration Mode Control */
+#define REG_MTB_CLAIMSET (0x4100AFA0U) /**< \brief (MTB) MTB Claim Set */
+#define REG_MTB_CLAIMCLR (0x4100AFA4U) /**< \brief (MTB) MTB Claim Clear */
+#define REG_MTB_LOCKACCESS (0x4100AFB0U) /**< \brief (MTB) MTB Lock Access */
+#define REG_MTB_LOCKSTATUS (0x4100AFB4U) /**< \brief (MTB) MTB Lock Status */
+#define REG_MTB_AUTHSTATUS (0x4100AFB8U) /**< \brief (MTB) MTB Authentication Status */
+#define REG_MTB_DEVARCH (0x4100AFBCU) /**< \brief (MTB) MTB Device Architecture */
+#define REG_MTB_DEVID (0x4100AFC8U) /**< \brief (MTB) MTB Device Configuration */
+#define REG_MTB_DEVTYPE (0x4100AFCCU) /**< \brief (MTB) MTB Device Type */
+#define REG_MTB_PID4 (0x4100AFD0U) /**< \brief (MTB) Peripheral Identification 4 */
+#define REG_MTB_PID5 (0x4100AFD4U) /**< \brief (MTB) Peripheral Identification 5 */
+#define REG_MTB_PID6 (0x4100AFD8U) /**< \brief (MTB) Peripheral Identification 6 */
+#define REG_MTB_PID7 (0x4100AFDCU) /**< \brief (MTB) Peripheral Identification 7 */
+#define REG_MTB_PID0 (0x4100AFE0U) /**< \brief (MTB) Peripheral Identification 0 */
+#define REG_MTB_PID1 (0x4100AFE4U) /**< \brief (MTB) Peripheral Identification 1 */
+#define REG_MTB_PID2 (0x4100AFE8U) /**< \brief (MTB) Peripheral Identification 2 */
+#define REG_MTB_PID3 (0x4100AFECU) /**< \brief (MTB) Peripheral Identification 3 */
+#define REG_MTB_CID0 (0x4100AFF0U) /**< \brief (MTB) Component Identification 0 */
+#define REG_MTB_CID1 (0x4100AFF4U) /**< \brief (MTB) Component Identification 1 */
+#define REG_MTB_CID2 (0x4100AFF8U) /**< \brief (MTB) Component Identification 2 */
+#define REG_MTB_CID3 (0x4100AFFCU) /**< \brief (MTB) Component Identification 3 */
+#else
+#define REG_MTB_POSITION (*(RwReg *)0x4100A000U) /**< \brief (MTB) MTB Position */
+#define REG_MTB_MASTER (*(RwReg *)0x4100A004U) /**< \brief (MTB) MTB Master */
+#define REG_MTB_FLOW (*(RwReg *)0x4100A008U) /**< \brief (MTB) MTB Flow */
+#define REG_MTB_BASE (*(RoReg *)0x4100A00CU) /**< \brief (MTB) MTB Base */
+#define REG_MTB_ITCTRL (*(RwReg *)0x4100AF00U) /**< \brief (MTB) MTB Integration Mode Control */
+#define REG_MTB_CLAIMSET (*(RwReg *)0x4100AFA0U) /**< \brief (MTB) MTB Claim Set */
+#define REG_MTB_CLAIMCLR (*(RwReg *)0x4100AFA4U) /**< \brief (MTB) MTB Claim Clear */
+#define REG_MTB_LOCKACCESS (*(RwReg *)0x4100AFB0U) /**< \brief (MTB) MTB Lock Access */
+#define REG_MTB_LOCKSTATUS (*(RoReg *)0x4100AFB4U) /**< \brief (MTB) MTB Lock Status */
+#define REG_MTB_AUTHSTATUS (*(RoReg *)0x4100AFB8U) /**< \brief (MTB) MTB Authentication Status */
+#define REG_MTB_DEVARCH (*(RoReg *)0x4100AFBCU) /**< \brief (MTB) MTB Device Architecture */
+#define REG_MTB_DEVID (*(RoReg *)0x4100AFC8U) /**< \brief (MTB) MTB Device Configuration */
+#define REG_MTB_DEVTYPE (*(RoReg *)0x4100AFCCU) /**< \brief (MTB) MTB Device Type */
+#define REG_MTB_PID4 (*(RoReg *)0x4100AFD0U) /**< \brief (MTB) Peripheral Identification 4 */
+#define REG_MTB_PID5 (*(RoReg *)0x4100AFD4U) /**< \brief (MTB) Peripheral Identification 5 */
+#define REG_MTB_PID6 (*(RoReg *)0x4100AFD8U) /**< \brief (MTB) Peripheral Identification 6 */
+#define REG_MTB_PID7 (*(RoReg *)0x4100AFDCU) /**< \brief (MTB) Peripheral Identification 7 */
+#define REG_MTB_PID0 (*(RoReg *)0x4100AFE0U) /**< \brief (MTB) Peripheral Identification 0 */
+#define REG_MTB_PID1 (*(RoReg *)0x4100AFE4U) /**< \brief (MTB) Peripheral Identification 1 */
+#define REG_MTB_PID2 (*(RoReg *)0x4100AFE8U) /**< \brief (MTB) Peripheral Identification 2 */
+#define REG_MTB_PID3 (*(RoReg *)0x4100AFECU) /**< \brief (MTB) Peripheral Identification 3 */
+#define REG_MTB_CID0 (*(RoReg *)0x4100AFF0U) /**< \brief (MTB) Component Identification 0 */
+#define REG_MTB_CID1 (*(RoReg *)0x4100AFF4U) /**< \brief (MTB) Component Identification 1 */
+#define REG_MTB_CID2 (*(RoReg *)0x4100AFF8U) /**< \brief (MTB) Component Identification 2 */
+#define REG_MTB_CID3 (*(RoReg *)0x4100AFFCU) /**< \brief (MTB) Component Identification 3 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+
+#endif /* _SAML22_MTB_INSTANCE_ */
diff --git a/Sensor Watch Starter Project/include/instance/nvmctrl.h b/Sensor Watch Starter Project/include/instance/nvmctrl.h new file mode 100755 index 00000000..6c3257b0 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/nvmctrl.h @@ -0,0 +1,94 @@ +/**
+ * \file
+ *
+ * \brief Instance description for NVMCTRL
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAML22_NVMCTRL_INSTANCE_
+#define _SAML22_NVMCTRL_INSTANCE_
+
+/* ========== Register definition for NVMCTRL peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_NVMCTRL_CTRLA (0x41004000U) /**< \brief (NVMCTRL) Control A */
+#define REG_NVMCTRL_CTRLB (0x41004004U) /**< \brief (NVMCTRL) Control B */
+#define REG_NVMCTRL_PARAM (0x41004008U) /**< \brief (NVMCTRL) NVM Parameter */
+#define REG_NVMCTRL_INTENCLR (0x4100400CU) /**< \brief (NVMCTRL) Interrupt Enable Clear */
+#define REG_NVMCTRL_INTENSET (0x41004010U) /**< \brief (NVMCTRL) Interrupt Enable Set */
+#define REG_NVMCTRL_INTFLAG (0x41004014U) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */
+#define REG_NVMCTRL_STATUS (0x41004018U) /**< \brief (NVMCTRL) Status */
+#define REG_NVMCTRL_ADDR (0x4100401CU) /**< \brief (NVMCTRL) Address */
+#define REG_NVMCTRL_LOCK (0x41004020U) /**< \brief (NVMCTRL) Lock Section */
+#else
+#define REG_NVMCTRL_CTRLA (*(RwReg16*)0x41004000U) /**< \brief (NVMCTRL) Control A */
+#define REG_NVMCTRL_CTRLB (*(RwReg *)0x41004004U) /**< \brief (NVMCTRL) Control B */
+#define REG_NVMCTRL_PARAM (*(RwReg *)0x41004008U) /**< \brief (NVMCTRL) NVM Parameter */
+#define REG_NVMCTRL_INTENCLR (*(RwReg8 *)0x4100400CU) /**< \brief (NVMCTRL) Interrupt Enable Clear */
+#define REG_NVMCTRL_INTENSET (*(RwReg8 *)0x41004010U) /**< \brief (NVMCTRL) Interrupt Enable Set */
+#define REG_NVMCTRL_INTFLAG (*(RwReg8 *)0x41004014U) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */
+#define REG_NVMCTRL_STATUS (*(RwReg16*)0x41004018U) /**< \brief (NVMCTRL) Status */
+#define REG_NVMCTRL_ADDR (*(RwReg *)0x4100401CU) /**< \brief (NVMCTRL) Address */
+#define REG_NVMCTRL_LOCK (*(RwReg16*)0x41004020U) /**< \brief (NVMCTRL) Lock Section */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for NVMCTRL peripheral ========== */
+#define NVMCTRL_AUX0_ADDRESS 0x00804000
+#define NVMCTRL_AUX1_ADDRESS 0x00806000
+#define NVMCTRL_AUX2_ADDRESS 0x00808000
+#define NVMCTRL_AUX3_ADDRESS 0x0080A000
+#define NVMCTRL_CLK_AHB_ID 8 // Index of AHB Clock in PM.AHBMASK register
+#define NVMCTRL_CLK_AHB_ID_PICACHU 10 // Index of PICACHU AHB Clock
+#define NVMCTRL_FACTORY_WORD_IMPLEMENTED_MASK 0XC0000007FFFFFFFF
+#define NVMCTRL_FLASH_SIZE 262144
+#define NVMCTRL_GCLK_ID 29 // Index of Generic Clock for test
+#define NVMCTRL_LOCKBIT_ADDRESS 0x00802000
+#define NVMCTRL_PAGE_HW 32
+#define NVMCTRL_PAGE_SIZE 64
+#define NVMCTRL_PAGE_W 16
+#define NVMCTRL_PMSB 3
+#define NVMCTRL_PSZ_BITS 6
+#define NVMCTRL_ROW_PAGES 4
+#define NVMCTRL_ROW_SIZE 256
+#define NVMCTRL_USER_PAGE_ADDRESS 0x00800000
+#define NVMCTRL_USER_PAGE_OFFSET 0x00800000
+#define NVMCTRL_USER_WORD_IMPLEMENTED_MASK 0XC01FFFFFFFFFFFFF
+#define NVMCTRL_RWWEE_PAGES 128
+#define NVMCTRL_RWW_EEPROM_ADDR 0x00400000 // Start address of the RWW EEPROM area
+
+#endif /* _SAML22_NVMCTRL_INSTANCE_ */
diff --git a/Sensor Watch Starter Project/include/instance/osc32kctrl.h b/Sensor Watch Starter Project/include/instance/osc32kctrl.h new file mode 100755 index 00000000..13660423 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/osc32kctrl.h @@ -0,0 +1,75 @@ +/**
+ * \file
+ *
+ * \brief Instance description for OSC32KCTRL
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAML22_OSC32KCTRL_INSTANCE_
+#define _SAML22_OSC32KCTRL_INSTANCE_
+
+/* ========== Register definition for OSC32KCTRL peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_OSC32KCTRL_INTENCLR (0x40001400U) /**< \brief (OSC32KCTRL) Interrupt Enable Clear */
+#define REG_OSC32KCTRL_INTENSET (0x40001404U) /**< \brief (OSC32KCTRL) Interrupt Enable Set */
+#define REG_OSC32KCTRL_INTFLAG (0x40001408U) /**< \brief (OSC32KCTRL) Interrupt Flag Status and Clear */
+#define REG_OSC32KCTRL_STATUS (0x4000140CU) /**< \brief (OSC32KCTRL) Power and Clocks Status */
+#define REG_OSC32KCTRL_RTCCTRL (0x40001410U) /**< \brief (OSC32KCTRL) RTC Clock Selection */
+#define REG_OSC32KCTRL_SLCDCTRL (0x40001411U) /**< \brief (OSC32KCTRL) SLCD Clock Selection */
+#define REG_OSC32KCTRL_XOSC32K (0x40001414U) /**< \brief (OSC32KCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */
+#define REG_OSC32KCTRL_CFDCTRL (0x40001416U) /**< \brief (OSC32KCTRL) Clock Failure Detector Control */
+#define REG_OSC32KCTRL_EVCTRL (0x40001417U) /**< \brief (OSC32KCTRL) Event Control */
+#define REG_OSC32KCTRL_OSCULP32K (0x4000141CU) /**< \brief (OSC32KCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
+#else
+#define REG_OSC32KCTRL_INTENCLR (*(RwReg *)0x40001400U) /**< \brief (OSC32KCTRL) Interrupt Enable Clear */
+#define REG_OSC32KCTRL_INTENSET (*(RwReg *)0x40001404U) /**< \brief (OSC32KCTRL) Interrupt Enable Set */
+#define REG_OSC32KCTRL_INTFLAG (*(RwReg *)0x40001408U) /**< \brief (OSC32KCTRL) Interrupt Flag Status and Clear */
+#define REG_OSC32KCTRL_STATUS (*(RoReg *)0x4000140CU) /**< \brief (OSC32KCTRL) Power and Clocks Status */
+#define REG_OSC32KCTRL_RTCCTRL (*(RwReg8 *)0x40001410U) /**< \brief (OSC32KCTRL) RTC Clock Selection */
+#define REG_OSC32KCTRL_SLCDCTRL (*(RwReg8 *)0x40001411U) /**< \brief (OSC32KCTRL) SLCD Clock Selection */
+#define REG_OSC32KCTRL_XOSC32K (*(RwReg16*)0x40001414U) /**< \brief (OSC32KCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */
+#define REG_OSC32KCTRL_CFDCTRL (*(RwReg8 *)0x40001416U) /**< \brief (OSC32KCTRL) Clock Failure Detector Control */
+#define REG_OSC32KCTRL_EVCTRL (*(RwReg8 *)0x40001417U) /**< \brief (OSC32KCTRL) Event Control */
+#define REG_OSC32KCTRL_OSCULP32K (*(RwReg *)0x4000141CU) /**< \brief (OSC32KCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for OSC32KCTRL peripheral ========== */
+#define OSC32KCTRL_OSC32K_COARSE_CALIB_MSB 6
+
+#endif /* _SAML22_OSC32KCTRL_INSTANCE_ */
diff --git a/Sensor Watch Starter Project/include/instance/oscctrl.h b/Sensor Watch Starter Project/include/instance/oscctrl.h new file mode 100755 index 00000000..c0bd0b5e --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/oscctrl.h @@ -0,0 +1,100 @@ +/**
+ * \file
+ *
+ * \brief Instance description for OSCCTRL
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAML22_OSCCTRL_INSTANCE_
+#define _SAML22_OSCCTRL_INSTANCE_
+
+/* ========== Register definition for OSCCTRL peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_OSCCTRL_INTENCLR (0x40001000U) /**< \brief (OSCCTRL) Interrupt Enable Clear */
+#define REG_OSCCTRL_INTENSET (0x40001004U) /**< \brief (OSCCTRL) Interrupt Enable Set */
+#define REG_OSCCTRL_INTFLAG (0x40001008U) /**< \brief (OSCCTRL) Interrupt Flag Status and Clear */
+#define REG_OSCCTRL_STATUS (0x4000100CU) /**< \brief (OSCCTRL) Power and Clocks Status */
+#define REG_OSCCTRL_XOSCCTRL (0x40001010U) /**< \brief (OSCCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */
+#define REG_OSCCTRL_CFDPRESC (0x40001012U) /**< \brief (OSCCTRL) Cloc Failure Detector Prescaler */
+#define REG_OSCCTRL_EVCTRL (0x40001013U) /**< \brief (OSCCTRL) Event Control */
+#define REG_OSCCTRL_OSC16MCTRL (0x40001014U) /**< \brief (OSCCTRL) 16MHz Internal Oscillator (OSC16M) Control */
+#define REG_OSCCTRL_DFLLCTRL (0x40001018U) /**< \brief (OSCCTRL) DFLL48M Control */
+#define REG_OSCCTRL_DFLLVAL (0x4000101CU) /**< \brief (OSCCTRL) DFLL48M Value */
+#define REG_OSCCTRL_DFLLMUL (0x40001020U) /**< \brief (OSCCTRL) DFLL48M Multiplier */
+#define REG_OSCCTRL_DFLLSYNC (0x40001024U) /**< \brief (OSCCTRL) DFLL48M Synchronization */
+#define REG_OSCCTRL_DPLLCTRLA (0x40001028U) /**< \brief (OSCCTRL) DPLL Control */
+#define REG_OSCCTRL_DPLLRATIO (0x4000102CU) /**< \brief (OSCCTRL) DPLL Ratio Control */
+#define REG_OSCCTRL_DPLLCTRLB (0x40001030U) /**< \brief (OSCCTRL) Digital Core Configuration */
+#define REG_OSCCTRL_DPLLPRESC (0x40001034U) /**< \brief (OSCCTRL) DPLL Prescaler */
+#define REG_OSCCTRL_DPLLSYNCBUSY (0x40001038U) /**< \brief (OSCCTRL) DPLL Synchronization Busy */
+#define REG_OSCCTRL_DPLLSTATUS (0x4000103CU) /**< \brief (OSCCTRL) DPLL Status */
+#else
+#define REG_OSCCTRL_INTENCLR (*(RwReg *)0x40001000U) /**< \brief (OSCCTRL) Interrupt Enable Clear */
+#define REG_OSCCTRL_INTENSET (*(RwReg *)0x40001004U) /**< \brief (OSCCTRL) Interrupt Enable Set */
+#define REG_OSCCTRL_INTFLAG (*(RwReg *)0x40001008U) /**< \brief (OSCCTRL) Interrupt Flag Status and Clear */
+#define REG_OSCCTRL_STATUS (*(RoReg *)0x4000100CU) /**< \brief (OSCCTRL) Power and Clocks Status */
+#define REG_OSCCTRL_XOSCCTRL (*(RwReg16*)0x40001010U) /**< \brief (OSCCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */
+#define REG_OSCCTRL_CFDPRESC (*(RwReg8 *)0x40001012U) /**< \brief (OSCCTRL) Cloc Failure Detector Prescaler */
+#define REG_OSCCTRL_EVCTRL (*(RwReg8 *)0x40001013U) /**< \brief (OSCCTRL) Event Control */
+#define REG_OSCCTRL_OSC16MCTRL (*(RwReg8 *)0x40001014U) /**< \brief (OSCCTRL) 16MHz Internal Oscillator (OSC16M) Control */
+#define REG_OSCCTRL_DFLLCTRL (*(RwReg16*)0x40001018U) /**< \brief (OSCCTRL) DFLL48M Control */
+#define REG_OSCCTRL_DFLLVAL (*(RwReg *)0x4000101CU) /**< \brief (OSCCTRL) DFLL48M Value */
+#define REG_OSCCTRL_DFLLMUL (*(RwReg *)0x40001020U) /**< \brief (OSCCTRL) DFLL48M Multiplier */
+#define REG_OSCCTRL_DFLLSYNC (*(RwReg8 *)0x40001024U) /**< \brief (OSCCTRL) DFLL48M Synchronization */
+#define REG_OSCCTRL_DPLLCTRLA (*(RwReg8 *)0x40001028U) /**< \brief (OSCCTRL) DPLL Control */
+#define REG_OSCCTRL_DPLLRATIO (*(RwReg *)0x4000102CU) /**< \brief (OSCCTRL) DPLL Ratio Control */
+#define REG_OSCCTRL_DPLLCTRLB (*(RwReg *)0x40001030U) /**< \brief (OSCCTRL) Digital Core Configuration */
+#define REG_OSCCTRL_DPLLPRESC (*(RwReg8 *)0x40001034U) /**< \brief (OSCCTRL) DPLL Prescaler */
+#define REG_OSCCTRL_DPLLSYNCBUSY (*(RoReg8 *)0x40001038U) /**< \brief (OSCCTRL) DPLL Synchronization Busy */
+#define REG_OSCCTRL_DPLLSTATUS (*(RoReg8 *)0x4000103CU) /**< \brief (OSCCTRL) DPLL Status */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for OSCCTRL peripheral ========== */
+#define OSCCTRL_DFLL48M_COARSE_MSB 5
+#define OSCCTRL_DFLL48M_FINE_MSB 9
+#define OSCCTRL_GCLK_ID_DFLL48 0 // Index of Generic Clock for DFLL48
+#define OSCCTRL_GCLK_ID_FDPLL 1 // Index of Generic Clock for DPLL
+#define OSCCTRL_GCLK_ID_FDPLL32K 2 // Index of Generic Clock for DPLL 32K
+#define OSCCTRL_CFD_VERSION 0x100
+#define OSCCTRL_DFLL48M_VERSION 0x320
+#define OSCCTRL_FDPLL_VERSION 0x211
+#define OSCCTRL_OSC16M_VERSION 0x101
+#define OSCCTRL_XOSC_VERSION 0x201
+
+#endif /* _SAML22_OSCCTRL_INSTANCE_ */
diff --git a/Sensor Watch Starter Project/include/instance/pac.h b/Sensor Watch Starter Project/include/instance/pac.h new file mode 100755 index 00000000..22593a03 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/pac.h @@ -0,0 +1,80 @@ +/**
+ * \file
+ *
+ * \brief Instance description for PAC
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAML22_PAC_INSTANCE_
+#define _SAML22_PAC_INSTANCE_
+
+/* ========== Register definition for PAC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PAC_WRCTRL (0x40000000U) /**< \brief (PAC) Write control */
+#define REG_PAC_EVCTRL (0x40000004U) /**< \brief (PAC) Event control */
+#define REG_PAC_INTENCLR (0x40000008U) /**< \brief (PAC) Interrupt enable clear */
+#define REG_PAC_INTENSET (0x40000009U) /**< \brief (PAC) Interrupt enable set */
+#define REG_PAC_INTFLAGAHB (0x40000010U) /**< \brief (PAC) Bridge interrupt flag status */
+#define REG_PAC_INTFLAGA (0x40000014U) /**< \brief (PAC) Peripheral interrupt flag status - Bridge A */
+#define REG_PAC_INTFLAGB (0x40000018U) /**< \brief (PAC) Peripheral interrupt flag status - Bridge B */
+#define REG_PAC_INTFLAGC (0x4000001CU) /**< \brief (PAC) Peripheral interrupt flag status - Bridge C */
+#define REG_PAC_STATUSA (0x40000034U) /**< \brief (PAC) Peripheral write protection status - Bridge A */
+#define REG_PAC_STATUSB (0x40000038U) /**< \brief (PAC) Peripheral write protection status - Bridge B */
+#define REG_PAC_STATUSC (0x4000003CU) /**< \brief (PAC) Peripheral write protection status - Bridge C */
+#else
+#define REG_PAC_WRCTRL (*(RwReg *)0x40000000U) /**< \brief (PAC) Write control */
+#define REG_PAC_EVCTRL (*(RwReg8 *)0x40000004U) /**< \brief (PAC) Event control */
+#define REG_PAC_INTENCLR (*(RwReg8 *)0x40000008U) /**< \brief (PAC) Interrupt enable clear */
+#define REG_PAC_INTENSET (*(RwReg8 *)0x40000009U) /**< \brief (PAC) Interrupt enable set */
+#define REG_PAC_INTFLAGAHB (*(RwReg *)0x40000010U) /**< \brief (PAC) Bridge interrupt flag status */
+#define REG_PAC_INTFLAGA (*(RwReg *)0x40000014U) /**< \brief (PAC) Peripheral interrupt flag status - Bridge A */
+#define REG_PAC_INTFLAGB (*(RwReg *)0x40000018U) /**< \brief (PAC) Peripheral interrupt flag status - Bridge B */
+#define REG_PAC_INTFLAGC (*(RwReg *)0x4000001CU) /**< \brief (PAC) Peripheral interrupt flag status - Bridge C */
+#define REG_PAC_STATUSA (*(RoReg *)0x40000034U) /**< \brief (PAC) Peripheral write protection status - Bridge A */
+#define REG_PAC_STATUSB (*(RoReg *)0x40000038U) /**< \brief (PAC) Peripheral write protection status - Bridge B */
+#define REG_PAC_STATUSC (*(RoReg *)0x4000003CU) /**< \brief (PAC) Peripheral write protection status - Bridge C */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for PAC peripheral ========== */
+#define PAC_CLK_AHB_DOMAIN // Clock domain of AHB clock
+#define PAC_CLK_AHB_ID 7 // AHB clock index
+#define PAC_HPB_NUM 3 // Number of bridges AHB/APB
+#define PAC_INTFLAG_NUM 4 // Number of intflag registers
+
+#endif /* _SAML22_PAC_INSTANCE_ */
diff --git a/Sensor Watch Starter Project/include/instance/pm.h b/Sensor Watch Starter Project/include/instance/pm.h new file mode 100755 index 00000000..e3637a45 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/pm.h @@ -0,0 +1,70 @@ +/**
+ * \file
+ *
+ * \brief Instance description for PM
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAML22_PM_INSTANCE_
+#define _SAML22_PM_INSTANCE_
+
+/* ========== Register definition for PM peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PM_CTRLA (0x40000400U) /**< \brief (PM) Control A */
+#define REG_PM_SLEEPCFG (0x40000401U) /**< \brief (PM) Sleep Configuration */
+#define REG_PM_PLCFG (0x40000402U) /**< \brief (PM) Performance Level Configuration */
+#define REG_PM_INTENCLR (0x40000404U) /**< \brief (PM) Interrupt Enable Clear */
+#define REG_PM_INTENSET (0x40000405U) /**< \brief (PM) Interrupt Enable Set */
+#define REG_PM_INTFLAG (0x40000406U) /**< \brief (PM) Interrupt Flag Status and Clear */
+#define REG_PM_STDBYCFG (0x40000408U) /**< \brief (PM) Standby Configuration */
+#else
+#define REG_PM_CTRLA (*(RwReg8 *)0x40000400U) /**< \brief (PM) Control A */
+#define REG_PM_SLEEPCFG (*(RwReg8 *)0x40000401U) /**< \brief (PM) Sleep Configuration */
+#define REG_PM_PLCFG (*(RwReg8 *)0x40000402U) /**< \brief (PM) Performance Level Configuration */
+#define REG_PM_INTENCLR (*(RwReg8 *)0x40000404U) /**< \brief (PM) Interrupt Enable Clear */
+#define REG_PM_INTENSET (*(RwReg8 *)0x40000405U) /**< \brief (PM) Interrupt Enable Set */
+#define REG_PM_INTFLAG (*(RwReg8 *)0x40000406U) /**< \brief (PM) Interrupt Flag Status and Clear */
+#define REG_PM_STDBYCFG (*(RwReg16*)0x40000408U) /**< \brief (PM) Standby Configuration */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for PM peripheral ========== */
+#define PM_BIAS_RAM_HS 1 // one if RAM HS can be back biased
+#define PM_PD_NUM 0 // Number of switchable Power Domain
+
+#endif /* _SAML22_PM_INSTANCE_ */
diff --git a/Sensor Watch Starter Project/include/instance/port.h b/Sensor Watch Starter Project/include/instance/port.h new file mode 100755 index 00000000..95a50484 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/port.h @@ -0,0 +1,169 @@ +/**
+ * \file
+ *
+ * \brief Instance description for PORT
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAML22_PORT_INSTANCE_
+#define _SAML22_PORT_INSTANCE_
+
+/* ========== Register definition for PORT peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PORT_DIR0 (0x41006000U) /**< \brief (PORT) Data Direction 0 */
+#define REG_PORT_DIRCLR0 (0x41006004U) /**< \brief (PORT) Data Direction Clear 0 */
+#define REG_PORT_DIRSET0 (0x41006008U) /**< \brief (PORT) Data Direction Set 0 */
+#define REG_PORT_DIRTGL0 (0x4100600CU) /**< \brief (PORT) Data Direction Toggle 0 */
+#define REG_PORT_OUT0 (0x41006010U) /**< \brief (PORT) Data Output Value 0 */
+#define REG_PORT_OUTCLR0 (0x41006014U) /**< \brief (PORT) Data Output Value Clear 0 */
+#define REG_PORT_OUTSET0 (0x41006018U) /**< \brief (PORT) Data Output Value Set 0 */
+#define REG_PORT_OUTTGL0 (0x4100601CU) /**< \brief (PORT) Data Output Value Toggle 0 */
+#define REG_PORT_IN0 (0x41006020U) /**< \brief (PORT) Data Input Value 0 */
+#define REG_PORT_CTRL0 (0x41006024U) /**< \brief (PORT) Control 0 */
+#define REG_PORT_WRCONFIG0 (0x41006028U) /**< \brief (PORT) Write Configuration 0 */
+#define REG_PORT_EVCTRL0 (0x4100602CU) /**< \brief (PORT) Event Input Control 0 */
+#define REG_PORT_PMUX0 (0x41006030U) /**< \brief (PORT) Peripheral Multiplexing 0 */
+#define REG_PORT_PINCFG0 (0x41006040U) /**< \brief (PORT) Pin Configuration 0 */
+#define REG_PORT_DIR1 (0x41006080U) /**< \brief (PORT) Data Direction 1 */
+#define REG_PORT_DIRCLR1 (0x41006084U) /**< \brief (PORT) Data Direction Clear 1 */
+#define REG_PORT_DIRSET1 (0x41006088U) /**< \brief (PORT) Data Direction Set 1 */
+#define REG_PORT_DIRTGL1 (0x4100608CU) /**< \brief (PORT) Data Direction Toggle 1 */
+#define REG_PORT_OUT1 (0x41006090U) /**< \brief (PORT) Data Output Value 1 */
+#define REG_PORT_OUTCLR1 (0x41006094U) /**< \brief (PORT) Data Output Value Clear 1 */
+#define REG_PORT_OUTSET1 (0x41006098U) /**< \brief (PORT) Data Output Value Set 1 */
+#define REG_PORT_OUTTGL1 (0x4100609CU) /**< \brief (PORT) Data Output Value Toggle 1 */
+#define REG_PORT_IN1 (0x410060A0U) /**< \brief (PORT) Data Input Value 1 */
+#define REG_PORT_CTRL1 (0x410060A4U) /**< \brief (PORT) Control 1 */
+#define REG_PORT_WRCONFIG1 (0x410060A8U) /**< \brief (PORT) Write Configuration 1 */
+#define REG_PORT_EVCTRL1 (0x410060ACU) /**< \brief (PORT) Event Input Control 1 */
+#define REG_PORT_PMUX1 (0x410060B0U) /**< \brief (PORT) Peripheral Multiplexing 1 */
+#define REG_PORT_PINCFG1 (0x410060C0U) /**< \brief (PORT) Pin Configuration 1 */
+#define REG_PORT_DIR2 (0x41006100U) /**< \brief (PORT) Data Direction 2 */
+#define REG_PORT_DIRCLR2 (0x41006104U) /**< \brief (PORT) Data Direction Clear 2 */
+#define REG_PORT_DIRSET2 (0x41006108U) /**< \brief (PORT) Data Direction Set 2 */
+#define REG_PORT_DIRTGL2 (0x4100610CU) /**< \brief (PORT) Data Direction Toggle 2 */
+#define REG_PORT_OUT2 (0x41006110U) /**< \brief (PORT) Data Output Value 2 */
+#define REG_PORT_OUTCLR2 (0x41006114U) /**< \brief (PORT) Data Output Value Clear 2 */
+#define REG_PORT_OUTSET2 (0x41006118U) /**< \brief (PORT) Data Output Value Set 2 */
+#define REG_PORT_OUTTGL2 (0x4100611CU) /**< \brief (PORT) Data Output Value Toggle 2 */
+#define REG_PORT_IN2 (0x41006120U) /**< \brief (PORT) Data Input Value 2 */
+#define REG_PORT_CTRL2 (0x41006124U) /**< \brief (PORT) Control 2 */
+#define REG_PORT_WRCONFIG2 (0x41006128U) /**< \brief (PORT) Write Configuration 2 */
+#define REG_PORT_EVCTRL2 (0x4100612CU) /**< \brief (PORT) Event Input Control 2 */
+#define REG_PORT_PMUX2 (0x41006130U) /**< \brief (PORT) Peripheral Multiplexing 2 */
+#define REG_PORT_PINCFG2 (0x41006140U) /**< \brief (PORT) Pin Configuration 2 */
+#else
+#define REG_PORT_DIR0 (*(RwReg *)0x41006000U) /**< \brief (PORT) Data Direction 0 */
+#define REG_PORT_DIRCLR0 (*(RwReg *)0x41006004U) /**< \brief (PORT) Data Direction Clear 0 */
+#define REG_PORT_DIRSET0 (*(RwReg *)0x41006008U) /**< \brief (PORT) Data Direction Set 0 */
+#define REG_PORT_DIRTGL0 (*(RwReg *)0x4100600CU) /**< \brief (PORT) Data Direction Toggle 0 */
+#define REG_PORT_OUT0 (*(RwReg *)0x41006010U) /**< \brief (PORT) Data Output Value 0 */
+#define REG_PORT_OUTCLR0 (*(RwReg *)0x41006014U) /**< \brief (PORT) Data Output Value Clear 0 */
+#define REG_PORT_OUTSET0 (*(RwReg *)0x41006018U) /**< \brief (PORT) Data Output Value Set 0 */
+#define REG_PORT_OUTTGL0 (*(RwReg *)0x4100601CU) /**< \brief (PORT) Data Output Value Toggle 0 */
+#define REG_PORT_IN0 (*(RoReg *)0x41006020U) /**< \brief (PORT) Data Input Value 0 */
+#define REG_PORT_CTRL0 (*(RwReg *)0x41006024U) /**< \brief (PORT) Control 0 */
+#define REG_PORT_WRCONFIG0 (*(WoReg *)0x41006028U) /**< \brief (PORT) Write Configuration 0 */
+#define REG_PORT_EVCTRL0 (*(RwReg *)0x4100602CU) /**< \brief (PORT) Event Input Control 0 */
+#define REG_PORT_PMUX0 (*(RwReg *)0x41006030U) /**< \brief (PORT) Peripheral Multiplexing 0 */
+#define REG_PORT_PINCFG0 (*(RwReg *)0x41006040U) /**< \brief (PORT) Pin Configuration 0 */
+#define REG_PORT_DIR1 (*(RwReg *)0x41006080U) /**< \brief (PORT) Data Direction 1 */
+#define REG_PORT_DIRCLR1 (*(RwReg *)0x41006084U) /**< \brief (PORT) Data Direction Clear 1 */
+#define REG_PORT_DIRSET1 (*(RwReg *)0x41006088U) /**< \brief (PORT) Data Direction Set 1 */
+#define REG_PORT_DIRTGL1 (*(RwReg *)0x4100608CU) /**< \brief (PORT) Data Direction Toggle 1 */
+#define REG_PORT_OUT1 (*(RwReg *)0x41006090U) /**< \brief (PORT) Data Output Value 1 */
+#define REG_PORT_OUTCLR1 (*(RwReg *)0x41006094U) /**< \brief (PORT) Data Output Value Clear 1 */
+#define REG_PORT_OUTSET1 (*(RwReg *)0x41006098U) /**< \brief (PORT) Data Output Value Set 1 */
+#define REG_PORT_OUTTGL1 (*(RwReg *)0x4100609CU) /**< \brief (PORT) Data Output Value Toggle 1 */
+#define REG_PORT_IN1 (*(RoReg *)0x410060A0U) /**< \brief (PORT) Data Input Value 1 */
+#define REG_PORT_CTRL1 (*(RwReg *)0x410060A4U) /**< \brief (PORT) Control 1 */
+#define REG_PORT_WRCONFIG1 (*(WoReg *)0x410060A8U) /**< \brief (PORT) Write Configuration 1 */
+#define REG_PORT_EVCTRL1 (*(RwReg *)0x410060ACU) /**< \brief (PORT) Event Input Control 1 */
+#define REG_PORT_PMUX1 (*(RwReg *)0x410060B0U) /**< \brief (PORT) Peripheral Multiplexing 1 */
+#define REG_PORT_PINCFG1 (*(RwReg *)0x410060C0U) /**< \brief (PORT) Pin Configuration 1 */
+#define REG_PORT_DIR2 (*(RwReg *)0x41006100U) /**< \brief (PORT) Data Direction 2 */
+#define REG_PORT_DIRCLR2 (*(RwReg *)0x41006104U) /**< \brief (PORT) Data Direction Clear 2 */
+#define REG_PORT_DIRSET2 (*(RwReg *)0x41006108U) /**< \brief (PORT) Data Direction Set 2 */
+#define REG_PORT_DIRTGL2 (*(RwReg *)0x4100610CU) /**< \brief (PORT) Data Direction Toggle 2 */
+#define REG_PORT_OUT2 (*(RwReg *)0x41006110U) /**< \brief (PORT) Data Output Value 2 */
+#define REG_PORT_OUTCLR2 (*(RwReg *)0x41006114U) /**< \brief (PORT) Data Output Value Clear 2 */
+#define REG_PORT_OUTSET2 (*(RwReg *)0x41006118U) /**< \brief (PORT) Data Output Value Set 2 */
+#define REG_PORT_OUTTGL2 (*(RwReg *)0x4100611CU) /**< \brief (PORT) Data Output Value Toggle 2 */
+#define REG_PORT_IN2 (*(RoReg *)0x41006120U) /**< \brief (PORT) Data Input Value 2 */
+#define REG_PORT_CTRL2 (*(RwReg *)0x41006124U) /**< \brief (PORT) Control 2 */
+#define REG_PORT_WRCONFIG2 (*(WoReg *)0x41006128U) /**< \brief (PORT) Write Configuration 2 */
+#define REG_PORT_EVCTRL2 (*(RwReg *)0x4100612CU) /**< \brief (PORT) Event Input Control 2 */
+#define REG_PORT_PMUX2 (*(RwReg *)0x41006130U) /**< \brief (PORT) Peripheral Multiplexing 2 */
+#define REG_PORT_PINCFG2 (*(RwReg *)0x41006140U) /**< \brief (PORT) Pin Configuration 2 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for PORT peripheral ========== */
+#define PORT_BITS 93
+#define PORT_DIR_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 }
+#define PORT_DIR_IMPLEMENTED { 0xCBFFFFFF, 0xC3FFFBFF, 0x1F3FFFEF }
+#define PORT_DRVSTR 1 // DRVSTR supported
+#define PORT_DRVSTR_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 }
+#define PORT_DRVSTR_IMPLEMENTED { 0xC8FFFFFF, 0xC3FFFBFF, 0x1F3FF0EF }
+#define PORT_EVENT_IMPLEMENTED { 0xCBFFFFFF, 0xC3FFFBFF, 0x1F03F0EF }
+#define PORT_EV_NUM 4
+#define PORT_INEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 }
+#define PORT_INEN_IMPLEMENTED { 0xCBFFFFFF, 0xC3FFFBFF, 0x1F3FFFEF }
+#define PORT_ODRAIN 0 // ODRAIN supported
+#define PORT_ODRAIN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 }
+#define PORT_ODRAIN_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 }
+#define PORT_OUT_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 }
+#define PORT_OUT_IMPLEMENTED { 0xCBFFFFFF, 0xC3FFFBFF, 0x1F3FFFEF }
+#define PORT_PIN_IMPLEMENTED { 0xCBFFFFFF, 0xC3FFFBFF, 0x1F3FFFEF }
+#define PORT_PMUXBIT0_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 }
+#define PORT_PMUXBIT0_IMPLEMENTED { 0xCBFFFFFF, 0xC3FFFBFF, 0x1F3FFFEF }
+#define PORT_PMUXBIT1_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000 }
+#define PORT_PMUXBIT1_IMPLEMENTED { 0xCBFFFFF7, 0xC3FFFB0F, 0x1B003C03 }
+#define PORT_PMUXBIT2_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000 }
+#define PORT_PMUXBIT2_IMPLEMENTED { 0x4BFFFF34, 0xC3FFFB0F, 0x1F000003 }
+#define PORT_PMUXBIT3_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 }
+#define PORT_PMUXBIT3_IMPLEMENTED { 0xC3CF0FF0, 0x00C3CBC7, 0x18300000 }
+#define PORT_PMUXEN_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000 }
+#define PORT_PMUXEN_IMPLEMENTED { 0xCBFFFFFF, 0xC3FFFBFF, 0x1F3FFFEF }
+#define PORT_PULLEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 }
+#define PORT_PULLEN_IMPLEMENTED { 0xCBFFFFFF, 0xC3FFFBFF, 0x1F3FFFEF }
+#define PORT_SLEWLIM 0 // SLEWLIM supported
+#define PORT_SLEWLIM_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 }
+#define PORT_SLEWLIM_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 }
+
+#endif /* _SAML22_PORT_INSTANCE_ */
diff --git a/Sensor Watch Starter Project/include/instance/rstc.h b/Sensor Watch Starter Project/include/instance/rstc.h new file mode 100755 index 00000000..8ab6a147 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/rstc.h @@ -0,0 +1,60 @@ +/**
+ * \file
+ *
+ * \brief Instance description for RSTC
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAML22_RSTC_INSTANCE_
+#define _SAML22_RSTC_INSTANCE_
+
+/* ========== Register definition for RSTC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_RSTC_RCAUSE (0x40000C00U) /**< \brief (RSTC) Reset Cause */
+#define REG_RSTC_BKUPEXIT (0x40000C02U) /**< \brief (RSTC) Backup Exit Source */
+#else
+#define REG_RSTC_RCAUSE (*(RoReg8 *)0x40000C00U) /**< \brief (RSTC) Reset Cause */
+#define REG_RSTC_BKUPEXIT (*(RoReg8 *)0x40000C02U) /**< \brief (RSTC) Backup Exit Source */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for RSTC peripheral ========== */
+#define RSTC_BACKUP_IMPLEMENTED 1
+#define RSTC_NUMBER_OF_EXTWAKE 0 // number of external wakeup line
+
+#endif /* _SAML22_RSTC_INSTANCE_ */
diff --git a/Sensor Watch Starter Project/include/instance/rtc.h b/Sensor Watch Starter Project/include/instance/rtc.h new file mode 100755 index 00000000..b1e3a0d4 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/rtc.h @@ -0,0 +1,156 @@ +/**
+ * \file
+ *
+ * \brief Instance description for RTC
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAML22_RTC_INSTANCE_
+#define _SAML22_RTC_INSTANCE_
+
+/* ========== Register definition for RTC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_RTC_DBGCTRL (0x4000240EU) /**< \brief (RTC) Debug Control */
+#define REG_RTC_FREQCORR (0x40002414U) /**< \brief (RTC) Frequency Correction */
+#define REG_RTC_GP0 (0x40002440U) /**< \brief (RTC) General Purpose 0 */
+#define REG_RTC_GP1 (0x40002444U) /**< \brief (RTC) General Purpose 1 */
+#define REG_RTC_TAMPCTRL (0x40002460U) /**< \brief (RTC) Tamper Control */
+#define REG_RTC_TAMPID (0x40002468U) /**< \brief (RTC) Tamper ID */
+#define REG_RTC_BKUP0 (0x40002480U) /**< \brief (RTC) Backup 0 */
+#define REG_RTC_BKUP1 (0x40002484U) /**< \brief (RTC) Backup 1 */
+#define REG_RTC_BKUP2 (0x40002488U) /**< \brief (RTC) Backup 2 */
+#define REG_RTC_BKUP3 (0x4000248CU) /**< \brief (RTC) Backup 3 */
+#define REG_RTC_BKUP4 (0x40002490U) /**< \brief (RTC) Backup 4 */
+#define REG_RTC_BKUP5 (0x40002494U) /**< \brief (RTC) Backup 5 */
+#define REG_RTC_BKUP6 (0x40002498U) /**< \brief (RTC) Backup 6 */
+#define REG_RTC_BKUP7 (0x4000249CU) /**< \brief (RTC) Backup 7 */
+#define REG_RTC_MODE0_CTRLA (0x40002400U) /**< \brief (RTC) MODE0 Control A */
+#define REG_RTC_MODE0_CTRLB (0x40002402U) /**< \brief (RTC) MODE0 Control B */
+#define REG_RTC_MODE0_EVCTRL (0x40002404U) /**< \brief (RTC) MODE0 Event Control */
+#define REG_RTC_MODE0_INTENCLR (0x40002408U) /**< \brief (RTC) MODE0 Interrupt Enable Clear */
+#define REG_RTC_MODE0_INTENSET (0x4000240AU) /**< \brief (RTC) MODE0 Interrupt Enable Set */
+#define REG_RTC_MODE0_INTFLAG (0x4000240CU) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */
+#define REG_RTC_MODE0_SYNCBUSY (0x40002410U) /**< \brief (RTC) MODE0 Synchronization Busy Status */
+#define REG_RTC_MODE0_COUNT (0x40002418U) /**< \brief (RTC) MODE0 Counter Value */
+#define REG_RTC_MODE0_COMP0 (0x40002420U) /**< \brief (RTC) MODE0 Compare 0 Value */
+#define REG_RTC_MODE0_TIMESTAMP (0x40002464U) /**< \brief (RTC) MODE0 Timestamp */
+#define REG_RTC_MODE1_CTRLA (0x40002400U) /**< \brief (RTC) MODE1 Control A */
+#define REG_RTC_MODE1_CTRLB (0x40002402U) /**< \brief (RTC) MODE1 Control B */
+#define REG_RTC_MODE1_EVCTRL (0x40002404U) /**< \brief (RTC) MODE1 Event Control */
+#define REG_RTC_MODE1_INTENCLR (0x40002408U) /**< \brief (RTC) MODE1 Interrupt Enable Clear */
+#define REG_RTC_MODE1_INTENSET (0x4000240AU) /**< \brief (RTC) MODE1 Interrupt Enable Set */
+#define REG_RTC_MODE1_INTFLAG (0x4000240CU) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */
+#define REG_RTC_MODE1_SYNCBUSY (0x40002410U) /**< \brief (RTC) MODE1 Synchronization Busy Status */
+#define REG_RTC_MODE1_COUNT (0x40002418U) /**< \brief (RTC) MODE1 Counter Value */
+#define REG_RTC_MODE1_PER (0x4000241CU) /**< \brief (RTC) MODE1 Counter Period */
+#define REG_RTC_MODE1_COMP0 (0x40002420U) /**< \brief (RTC) MODE1 Compare 0 Value */
+#define REG_RTC_MODE1_COMP1 (0x40002422U) /**< \brief (RTC) MODE1 Compare 1 Value */
+#define REG_RTC_MODE1_TIMESTAMP (0x40002464U) /**< \brief (RTC) MODE1 Timestamp */
+#define REG_RTC_MODE2_CTRLA (0x40002400U) /**< \brief (RTC) MODE2 Control A */
+#define REG_RTC_MODE2_CTRLB (0x40002402U) /**< \brief (RTC) MODE2 Control B */
+#define REG_RTC_MODE2_EVCTRL (0x40002404U) /**< \brief (RTC) MODE2 Event Control */
+#define REG_RTC_MODE2_INTENCLR (0x40002408U) /**< \brief (RTC) MODE2 Interrupt Enable Clear */
+#define REG_RTC_MODE2_INTENSET (0x4000240AU) /**< \brief (RTC) MODE2 Interrupt Enable Set */
+#define REG_RTC_MODE2_INTFLAG (0x4000240CU) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */
+#define REG_RTC_MODE2_SYNCBUSY (0x40002410U) /**< \brief (RTC) MODE2 Synchronization Busy Status */
+#define REG_RTC_MODE2_CLOCK (0x40002418U) /**< \brief (RTC) MODE2 Clock Value */
+#define REG_RTC_MODE2_TIMESTAMP (0x40002464U) /**< \brief (RTC) MODE2 Timestamp */
+#define REG_RTC_MODE2_ALARM_ALARM0 (0x40002420U) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */
+#define REG_RTC_MODE2_ALARM_MASK0 (0x40002424U) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */
+#else
+#define REG_RTC_DBGCTRL (*(RwReg8 *)0x4000240EU) /**< \brief (RTC) Debug Control */
+#define REG_RTC_FREQCORR (*(RwReg8 *)0x40002414U) /**< \brief (RTC) Frequency Correction */
+#define REG_RTC_GP0 (*(RwReg *)0x40002440U) /**< \brief (RTC) General Purpose 0 */
+#define REG_RTC_GP1 (*(RwReg *)0x40002444U) /**< \brief (RTC) General Purpose 1 */
+#define REG_RTC_TAMPCTRL (*(RwReg *)0x40002460U) /**< \brief (RTC) Tamper Control */
+#define REG_RTC_TAMPID (*(RwReg *)0x40002468U) /**< \brief (RTC) Tamper ID */
+#define REG_RTC_BKUP0 (*(RwReg *)0x40002480U) /**< \brief (RTC) Backup 0 */
+#define REG_RTC_BKUP1 (*(RwReg *)0x40002484U) /**< \brief (RTC) Backup 1 */
+#define REG_RTC_BKUP2 (*(RwReg *)0x40002488U) /**< \brief (RTC) Backup 2 */
+#define REG_RTC_BKUP3 (*(RwReg *)0x4000248CU) /**< \brief (RTC) Backup 3 */
+#define REG_RTC_BKUP4 (*(RwReg *)0x40002490U) /**< \brief (RTC) Backup 4 */
+#define REG_RTC_BKUP5 (*(RwReg *)0x40002494U) /**< \brief (RTC) Backup 5 */
+#define REG_RTC_BKUP6 (*(RwReg *)0x40002498U) /**< \brief (RTC) Backup 6 */
+#define REG_RTC_BKUP7 (*(RwReg *)0x4000249CU) /**< \brief (RTC) Backup 7 */
+#define REG_RTC_MODE0_CTRLA (*(RwReg16*)0x40002400U) /**< \brief (RTC) MODE0 Control A */
+#define REG_RTC_MODE0_CTRLB (*(RwReg16*)0x40002402U) /**< \brief (RTC) MODE0 Control B */
+#define REG_RTC_MODE0_EVCTRL (*(RwReg *)0x40002404U) /**< \brief (RTC) MODE0 Event Control */
+#define REG_RTC_MODE0_INTENCLR (*(RwReg16*)0x40002408U) /**< \brief (RTC) MODE0 Interrupt Enable Clear */
+#define REG_RTC_MODE0_INTENSET (*(RwReg16*)0x4000240AU) /**< \brief (RTC) MODE0 Interrupt Enable Set */
+#define REG_RTC_MODE0_INTFLAG (*(RwReg16*)0x4000240CU) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */
+#define REG_RTC_MODE0_SYNCBUSY (*(RoReg *)0x40002410U) /**< \brief (RTC) MODE0 Synchronization Busy Status */
+#define REG_RTC_MODE0_COUNT (*(RwReg *)0x40002418U) /**< \brief (RTC) MODE0 Counter Value */
+#define REG_RTC_MODE0_COMP0 (*(RwReg *)0x40002420U) /**< \brief (RTC) MODE0 Compare 0 Value */
+#define REG_RTC_MODE0_TIMESTAMP (*(RoReg *)0x40002464U) /**< \brief (RTC) MODE0 Timestamp */
+#define REG_RTC_MODE1_CTRLA (*(RwReg16*)0x40002400U) /**< \brief (RTC) MODE1 Control A */
+#define REG_RTC_MODE1_CTRLB (*(RwReg16*)0x40002402U) /**< \brief (RTC) MODE1 Control B */
+#define REG_RTC_MODE1_EVCTRL (*(RwReg *)0x40002404U) /**< \brief (RTC) MODE1 Event Control */
+#define REG_RTC_MODE1_INTENCLR (*(RwReg16*)0x40002408U) /**< \brief (RTC) MODE1 Interrupt Enable Clear */
+#define REG_RTC_MODE1_INTENSET (*(RwReg16*)0x4000240AU) /**< \brief (RTC) MODE1 Interrupt Enable Set */
+#define REG_RTC_MODE1_INTFLAG (*(RwReg16*)0x4000240CU) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */
+#define REG_RTC_MODE1_SYNCBUSY (*(RoReg *)0x40002410U) /**< \brief (RTC) MODE1 Synchronization Busy Status */
+#define REG_RTC_MODE1_COUNT (*(RwReg16*)0x40002418U) /**< \brief (RTC) MODE1 Counter Value */
+#define REG_RTC_MODE1_PER (*(RwReg16*)0x4000241CU) /**< \brief (RTC) MODE1 Counter Period */
+#define REG_RTC_MODE1_COMP0 (*(RwReg16*)0x40002420U) /**< \brief (RTC) MODE1 Compare 0 Value */
+#define REG_RTC_MODE1_COMP1 (*(RwReg16*)0x40002422U) /**< \brief (RTC) MODE1 Compare 1 Value */
+#define REG_RTC_MODE1_TIMESTAMP (*(RoReg *)0x40002464U) /**< \brief (RTC) MODE1 Timestamp */
+#define REG_RTC_MODE2_CTRLA (*(RwReg16*)0x40002400U) /**< \brief (RTC) MODE2 Control A */
+#define REG_RTC_MODE2_CTRLB (*(RwReg16*)0x40002402U) /**< \brief (RTC) MODE2 Control B */
+#define REG_RTC_MODE2_EVCTRL (*(RwReg *)0x40002404U) /**< \brief (RTC) MODE2 Event Control */
+#define REG_RTC_MODE2_INTENCLR (*(RwReg16*)0x40002408U) /**< \brief (RTC) MODE2 Interrupt Enable Clear */
+#define REG_RTC_MODE2_INTENSET (*(RwReg16*)0x4000240AU) /**< \brief (RTC) MODE2 Interrupt Enable Set */
+#define REG_RTC_MODE2_INTFLAG (*(RwReg16*)0x4000240CU) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */
+#define REG_RTC_MODE2_SYNCBUSY (*(RoReg *)0x40002410U) /**< \brief (RTC) MODE2 Synchronization Busy Status */
+#define REG_RTC_MODE2_CLOCK (*(RwReg *)0x40002418U) /**< \brief (RTC) MODE2 Clock Value */
+#define REG_RTC_MODE2_TIMESTAMP (*(RoReg *)0x40002464U) /**< \brief (RTC) MODE2 Timestamp */
+#define REG_RTC_MODE2_ALARM_ALARM0 (*(RwReg *)0x40002420U) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */
+#define REG_RTC_MODE2_ALARM_MASK0 (*(RwReg *)0x40002424U) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for RTC peripheral ========== */
+#define RTC_ALARM_NUM 1 // Number of Alarms
+#define RTC_BKUP_NUM 8 // Number of Backup Registers
+#define RTC_COMP16_NUM 2 // Number of 16-bit Comparators
+#define RTC_COMP32_NUM 1 // Number of 32-bit Comparators
+#define RTC_DMAC_ID_TIMESTAMP 1 // DMA RTC timestamp trigger
+#define RTC_GPR_NUM 2 // Number of General-Purpose Registers
+#define RTC_PER_NUM 8 // Number of Periodic Intervals
+#define RTC_TAMPER_NUM 5 // Number of Tamper Inputs
+
+#endif /* _SAML22_RTC_INSTANCE_ */
diff --git a/Sensor Watch Starter Project/include/instance/sercom0.h b/Sensor Watch Starter Project/include/instance/sercom0.h new file mode 100755 index 00000000..0eb9f52b --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/sercom0.h @@ -0,0 +1,156 @@ +/**
+ * \file
+ *
+ * \brief Instance description for SERCOM0
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAML22_SERCOM0_INSTANCE_
+#define _SAML22_SERCOM0_INSTANCE_
+
+/* ========== Register definition for SERCOM0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM0_I2CM_CTRLA (0x42000400U) /**< \brief (SERCOM0) I2CM Control A */
+#define REG_SERCOM0_I2CM_CTRLB (0x42000404U) /**< \brief (SERCOM0) I2CM Control B */
+#define REG_SERCOM0_I2CM_BAUD (0x4200040CU) /**< \brief (SERCOM0) I2CM Baud Rate */
+#define REG_SERCOM0_I2CM_INTENCLR (0x42000414U) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */
+#define REG_SERCOM0_I2CM_INTENSET (0x42000416U) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */
+#define REG_SERCOM0_I2CM_INTFLAG (0x42000418U) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM0_I2CM_STATUS (0x4200041AU) /**< \brief (SERCOM0) I2CM Status */
+#define REG_SERCOM0_I2CM_SYNCBUSY (0x4200041CU) /**< \brief (SERCOM0) I2CM Synchronization Busy */
+#define REG_SERCOM0_I2CM_ADDR (0x42000424U) /**< \brief (SERCOM0) I2CM Address */
+#define REG_SERCOM0_I2CM_DATA (0x42000428U) /**< \brief (SERCOM0) I2CM Data */
+#define REG_SERCOM0_I2CM_DBGCTRL (0x42000430U) /**< \brief (SERCOM0) I2CM Debug Control */
+#define REG_SERCOM0_I2CS_CTRLA (0x42000400U) /**< \brief (SERCOM0) I2CS Control A */
+#define REG_SERCOM0_I2CS_CTRLB (0x42000404U) /**< \brief (SERCOM0) I2CS Control B */
+#define REG_SERCOM0_I2CS_INTENCLR (0x42000414U) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */
+#define REG_SERCOM0_I2CS_INTENSET (0x42000416U) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */
+#define REG_SERCOM0_I2CS_INTFLAG (0x42000418U) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM0_I2CS_STATUS (0x4200041AU) /**< \brief (SERCOM0) I2CS Status */
+#define REG_SERCOM0_I2CS_SYNCBUSY (0x4200041CU) /**< \brief (SERCOM0) I2CS Synchronization Busy */
+#define REG_SERCOM0_I2CS_ADDR (0x42000424U) /**< \brief (SERCOM0) I2CS Address */
+#define REG_SERCOM0_I2CS_DATA (0x42000428U) /**< \brief (SERCOM0) I2CS Data */
+#define REG_SERCOM0_SPI_CTRLA (0x42000400U) /**< \brief (SERCOM0) SPI Control A */
+#define REG_SERCOM0_SPI_CTRLB (0x42000404U) /**< \brief (SERCOM0) SPI Control B */
+#define REG_SERCOM0_SPI_BAUD (0x4200040CU) /**< \brief (SERCOM0) SPI Baud Rate */
+#define REG_SERCOM0_SPI_INTENCLR (0x42000414U) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */
+#define REG_SERCOM0_SPI_INTENSET (0x42000416U) /**< \brief (SERCOM0) SPI Interrupt Enable Set */
+#define REG_SERCOM0_SPI_INTFLAG (0x42000418U) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM0_SPI_STATUS (0x4200041AU) /**< \brief (SERCOM0) SPI Status */
+#define REG_SERCOM0_SPI_SYNCBUSY (0x4200041CU) /**< \brief (SERCOM0) SPI Synchronization Busy */
+#define REG_SERCOM0_SPI_ADDR (0x42000424U) /**< \brief (SERCOM0) SPI Address */
+#define REG_SERCOM0_SPI_DATA (0x42000428U) /**< \brief (SERCOM0) SPI Data */
+#define REG_SERCOM0_SPI_DBGCTRL (0x42000430U) /**< \brief (SERCOM0) SPI Debug Control */
+#define REG_SERCOM0_USART_CTRLA (0x42000400U) /**< \brief (SERCOM0) USART Control A */
+#define REG_SERCOM0_USART_CTRLB (0x42000404U) /**< \brief (SERCOM0) USART Control B */
+#define REG_SERCOM0_USART_CTRLC (0x42000408U) /**< \brief (SERCOM0) USART Control C */
+#define REG_SERCOM0_USART_BAUD (0x4200040CU) /**< \brief (SERCOM0) USART Baud Rate */
+#define REG_SERCOM0_USART_RXPL (0x4200040EU) /**< \brief (SERCOM0) USART Receive Pulse Length */
+#define REG_SERCOM0_USART_INTENCLR (0x42000414U) /**< \brief (SERCOM0) USART Interrupt Enable Clear */
+#define REG_SERCOM0_USART_INTENSET (0x42000416U) /**< \brief (SERCOM0) USART Interrupt Enable Set */
+#define REG_SERCOM0_USART_INTFLAG (0x42000418U) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM0_USART_STATUS (0x4200041AU) /**< \brief (SERCOM0) USART Status */
+#define REG_SERCOM0_USART_SYNCBUSY (0x4200041CU) /**< \brief (SERCOM0) USART Synchronization Busy */
+#define REG_SERCOM0_USART_RXERRCNT (0x42000420U) /**< \brief (SERCOM0) USART Receive Error Count */
+#define REG_SERCOM0_USART_DATA (0x42000428U) /**< \brief (SERCOM0) USART Data */
+#define REG_SERCOM0_USART_DBGCTRL (0x42000430U) /**< \brief (SERCOM0) USART Debug Control */
+#else
+#define REG_SERCOM0_I2CM_CTRLA (*(RwReg *)0x42000400U) /**< \brief (SERCOM0) I2CM Control A */
+#define REG_SERCOM0_I2CM_CTRLB (*(RwReg *)0x42000404U) /**< \brief (SERCOM0) I2CM Control B */
+#define REG_SERCOM0_I2CM_BAUD (*(RwReg *)0x4200040CU) /**< \brief (SERCOM0) I2CM Baud Rate */
+#define REG_SERCOM0_I2CM_INTENCLR (*(RwReg8 *)0x42000414U) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */
+#define REG_SERCOM0_I2CM_INTENSET (*(RwReg8 *)0x42000416U) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */
+#define REG_SERCOM0_I2CM_INTFLAG (*(RwReg8 *)0x42000418U) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM0_I2CM_STATUS (*(RwReg16*)0x4200041AU) /**< \brief (SERCOM0) I2CM Status */
+#define REG_SERCOM0_I2CM_SYNCBUSY (*(RoReg *)0x4200041CU) /**< \brief (SERCOM0) I2CM Synchronization Busy */
+#define REG_SERCOM0_I2CM_ADDR (*(RwReg *)0x42000424U) /**< \brief (SERCOM0) I2CM Address */
+#define REG_SERCOM0_I2CM_DATA (*(RwReg8 *)0x42000428U) /**< \brief (SERCOM0) I2CM Data */
+#define REG_SERCOM0_I2CM_DBGCTRL (*(RwReg8 *)0x42000430U) /**< \brief (SERCOM0) I2CM Debug Control */
+#define REG_SERCOM0_I2CS_CTRLA (*(RwReg *)0x42000400U) /**< \brief (SERCOM0) I2CS Control A */
+#define REG_SERCOM0_I2CS_CTRLB (*(RwReg *)0x42000404U) /**< \brief (SERCOM0) I2CS Control B */
+#define REG_SERCOM0_I2CS_INTENCLR (*(RwReg8 *)0x42000414U) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */
+#define REG_SERCOM0_I2CS_INTENSET (*(RwReg8 *)0x42000416U) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */
+#define REG_SERCOM0_I2CS_INTFLAG (*(RwReg8 *)0x42000418U) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM0_I2CS_STATUS (*(RwReg16*)0x4200041AU) /**< \brief (SERCOM0) I2CS Status */
+#define REG_SERCOM0_I2CS_SYNCBUSY (*(RoReg *)0x4200041CU) /**< \brief (SERCOM0) I2CS Synchronization Busy */
+#define REG_SERCOM0_I2CS_ADDR (*(RwReg *)0x42000424U) /**< \brief (SERCOM0) I2CS Address */
+#define REG_SERCOM0_I2CS_DATA (*(RwReg8 *)0x42000428U) /**< \brief (SERCOM0) I2CS Data */
+#define REG_SERCOM0_SPI_CTRLA (*(RwReg *)0x42000400U) /**< \brief (SERCOM0) SPI Control A */
+#define REG_SERCOM0_SPI_CTRLB (*(RwReg *)0x42000404U) /**< \brief (SERCOM0) SPI Control B */
+#define REG_SERCOM0_SPI_BAUD (*(RwReg8 *)0x4200040CU) /**< \brief (SERCOM0) SPI Baud Rate */
+#define REG_SERCOM0_SPI_INTENCLR (*(RwReg8 *)0x42000414U) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */
+#define REG_SERCOM0_SPI_INTENSET (*(RwReg8 *)0x42000416U) /**< \brief (SERCOM0) SPI Interrupt Enable Set */
+#define REG_SERCOM0_SPI_INTFLAG (*(RwReg8 *)0x42000418U) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM0_SPI_STATUS (*(RwReg16*)0x4200041AU) /**< \brief (SERCOM0) SPI Status */
+#define REG_SERCOM0_SPI_SYNCBUSY (*(RoReg *)0x4200041CU) /**< \brief (SERCOM0) SPI Synchronization Busy */
+#define REG_SERCOM0_SPI_ADDR (*(RwReg *)0x42000424U) /**< \brief (SERCOM0) SPI Address */
+#define REG_SERCOM0_SPI_DATA (*(RwReg *)0x42000428U) /**< \brief (SERCOM0) SPI Data */
+#define REG_SERCOM0_SPI_DBGCTRL (*(RwReg8 *)0x42000430U) /**< \brief (SERCOM0) SPI Debug Control */
+#define REG_SERCOM0_USART_CTRLA (*(RwReg *)0x42000400U) /**< \brief (SERCOM0) USART Control A */
+#define REG_SERCOM0_USART_CTRLB (*(RwReg *)0x42000404U) /**< \brief (SERCOM0) USART Control B */
+#define REG_SERCOM0_USART_CTRLC (*(RwReg *)0x42000408U) /**< \brief (SERCOM0) USART Control C */
+#define REG_SERCOM0_USART_BAUD (*(RwReg16*)0x4200040CU) /**< \brief (SERCOM0) USART Baud Rate */
+#define REG_SERCOM0_USART_RXPL (*(RwReg8 *)0x4200040EU) /**< \brief (SERCOM0) USART Receive Pulse Length */
+#define REG_SERCOM0_USART_INTENCLR (*(RwReg8 *)0x42000414U) /**< \brief (SERCOM0) USART Interrupt Enable Clear */
+#define REG_SERCOM0_USART_INTENSET (*(RwReg8 *)0x42000416U) /**< \brief (SERCOM0) USART Interrupt Enable Set */
+#define REG_SERCOM0_USART_INTFLAG (*(RwReg8 *)0x42000418U) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM0_USART_STATUS (*(RwReg16*)0x4200041AU) /**< \brief (SERCOM0) USART Status */
+#define REG_SERCOM0_USART_SYNCBUSY (*(RoReg *)0x4200041CU) /**< \brief (SERCOM0) USART Synchronization Busy */
+#define REG_SERCOM0_USART_RXERRCNT (*(RoReg8 *)0x42000420U) /**< \brief (SERCOM0) USART Receive Error Count */
+#define REG_SERCOM0_USART_DATA (*(RwReg16*)0x42000428U) /**< \brief (SERCOM0) USART Data */
+#define REG_SERCOM0_USART_DBGCTRL (*(RwReg8 *)0x42000430U) /**< \brief (SERCOM0) USART Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM0 peripheral ========== */
+#define SERCOM0_DMAC_ID_RX 2 // Index of DMA RX trigger
+#define SERCOM0_DMAC_ID_TX 3 // Index of DMA TX trigger
+#define SERCOM0_GCLK_ID_CORE 16
+#define SERCOM0_GCLK_ID_SLOW 15
+#define SERCOM0_INT_MSB 6
+#define SERCOM0_PMSB 3
+#define SERCOM0_SPI 1 // SPI mode implemented?
+#define SERCOM0_TWIM 0 // TWI Master mode implemented?
+#define SERCOM0_TWIS 0 // TWI Slave mode implemented?
+#define SERCOM0_TWI_HSMODE 0 // TWI HighSpeed mode implemented?
+#define SERCOM0_USART 1 // USART mode implemented?
+#define SERCOM0_USART_ISO7816 1 // USART ISO7816 mode implemented?
+#define SERCOM0_USART_LIN_MASTER 0 // USART LIN Master mode implemented?
+#define SERCOM0_USART_RS485 1 // USART RS485 mode implemented?
+
+#endif /* _SAML22_SERCOM0_INSTANCE_ */
diff --git a/Sensor Watch Starter Project/include/instance/sercom1.h b/Sensor Watch Starter Project/include/instance/sercom1.h new file mode 100755 index 00000000..85ad084b --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/sercom1.h @@ -0,0 +1,156 @@ +/**
+ * \file
+ *
+ * \brief Instance description for SERCOM1
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAML22_SERCOM1_INSTANCE_
+#define _SAML22_SERCOM1_INSTANCE_
+
+/* ========== Register definition for SERCOM1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM1_I2CM_CTRLA (0x42000800U) /**< \brief (SERCOM1) I2CM Control A */
+#define REG_SERCOM1_I2CM_CTRLB (0x42000804U) /**< \brief (SERCOM1) I2CM Control B */
+#define REG_SERCOM1_I2CM_BAUD (0x4200080CU) /**< \brief (SERCOM1) I2CM Baud Rate */
+#define REG_SERCOM1_I2CM_INTENCLR (0x42000814U) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */
+#define REG_SERCOM1_I2CM_INTENSET (0x42000816U) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */
+#define REG_SERCOM1_I2CM_INTFLAG (0x42000818U) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM1_I2CM_STATUS (0x4200081AU) /**< \brief (SERCOM1) I2CM Status */
+#define REG_SERCOM1_I2CM_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM1) I2CM Synchronization Busy */
+#define REG_SERCOM1_I2CM_ADDR (0x42000824U) /**< \brief (SERCOM1) I2CM Address */
+#define REG_SERCOM1_I2CM_DATA (0x42000828U) /**< \brief (SERCOM1) I2CM Data */
+#define REG_SERCOM1_I2CM_DBGCTRL (0x42000830U) /**< \brief (SERCOM1) I2CM Debug Control */
+#define REG_SERCOM1_I2CS_CTRLA (0x42000800U) /**< \brief (SERCOM1) I2CS Control A */
+#define REG_SERCOM1_I2CS_CTRLB (0x42000804U) /**< \brief (SERCOM1) I2CS Control B */
+#define REG_SERCOM1_I2CS_INTENCLR (0x42000814U) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */
+#define REG_SERCOM1_I2CS_INTENSET (0x42000816U) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */
+#define REG_SERCOM1_I2CS_INTFLAG (0x42000818U) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM1_I2CS_STATUS (0x4200081AU) /**< \brief (SERCOM1) I2CS Status */
+#define REG_SERCOM1_I2CS_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM1) I2CS Synchronization Busy */
+#define REG_SERCOM1_I2CS_ADDR (0x42000824U) /**< \brief (SERCOM1) I2CS Address */
+#define REG_SERCOM1_I2CS_DATA (0x42000828U) /**< \brief (SERCOM1) I2CS Data */
+#define REG_SERCOM1_SPI_CTRLA (0x42000800U) /**< \brief (SERCOM1) SPI Control A */
+#define REG_SERCOM1_SPI_CTRLB (0x42000804U) /**< \brief (SERCOM1) SPI Control B */
+#define REG_SERCOM1_SPI_BAUD (0x4200080CU) /**< \brief (SERCOM1) SPI Baud Rate */
+#define REG_SERCOM1_SPI_INTENCLR (0x42000814U) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */
+#define REG_SERCOM1_SPI_INTENSET (0x42000816U) /**< \brief (SERCOM1) SPI Interrupt Enable Set */
+#define REG_SERCOM1_SPI_INTFLAG (0x42000818U) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM1_SPI_STATUS (0x4200081AU) /**< \brief (SERCOM1) SPI Status */
+#define REG_SERCOM1_SPI_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM1) SPI Synchronization Busy */
+#define REG_SERCOM1_SPI_ADDR (0x42000824U) /**< \brief (SERCOM1) SPI Address */
+#define REG_SERCOM1_SPI_DATA (0x42000828U) /**< \brief (SERCOM1) SPI Data */
+#define REG_SERCOM1_SPI_DBGCTRL (0x42000830U) /**< \brief (SERCOM1) SPI Debug Control */
+#define REG_SERCOM1_USART_CTRLA (0x42000800U) /**< \brief (SERCOM1) USART Control A */
+#define REG_SERCOM1_USART_CTRLB (0x42000804U) /**< \brief (SERCOM1) USART Control B */
+#define REG_SERCOM1_USART_CTRLC (0x42000808U) /**< \brief (SERCOM1) USART Control C */
+#define REG_SERCOM1_USART_BAUD (0x4200080CU) /**< \brief (SERCOM1) USART Baud Rate */
+#define REG_SERCOM1_USART_RXPL (0x4200080EU) /**< \brief (SERCOM1) USART Receive Pulse Length */
+#define REG_SERCOM1_USART_INTENCLR (0x42000814U) /**< \brief (SERCOM1) USART Interrupt Enable Clear */
+#define REG_SERCOM1_USART_INTENSET (0x42000816U) /**< \brief (SERCOM1) USART Interrupt Enable Set */
+#define REG_SERCOM1_USART_INTFLAG (0x42000818U) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM1_USART_STATUS (0x4200081AU) /**< \brief (SERCOM1) USART Status */
+#define REG_SERCOM1_USART_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM1) USART Synchronization Busy */
+#define REG_SERCOM1_USART_RXERRCNT (0x42000820U) /**< \brief (SERCOM1) USART Receive Error Count */
+#define REG_SERCOM1_USART_DATA (0x42000828U) /**< \brief (SERCOM1) USART Data */
+#define REG_SERCOM1_USART_DBGCTRL (0x42000830U) /**< \brief (SERCOM1) USART Debug Control */
+#else
+#define REG_SERCOM1_I2CM_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM1) I2CM Control A */
+#define REG_SERCOM1_I2CM_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM1) I2CM Control B */
+#define REG_SERCOM1_I2CM_BAUD (*(RwReg *)0x4200080CU) /**< \brief (SERCOM1) I2CM Baud Rate */
+#define REG_SERCOM1_I2CM_INTENCLR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */
+#define REG_SERCOM1_I2CM_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */
+#define REG_SERCOM1_I2CM_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM1_I2CM_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM1) I2CM Status */
+#define REG_SERCOM1_I2CM_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM1) I2CM Synchronization Busy */
+#define REG_SERCOM1_I2CM_ADDR (*(RwReg *)0x42000824U) /**< \brief (SERCOM1) I2CM Address */
+#define REG_SERCOM1_I2CM_DATA (*(RwReg8 *)0x42000828U) /**< \brief (SERCOM1) I2CM Data */
+#define REG_SERCOM1_I2CM_DBGCTRL (*(RwReg8 *)0x42000830U) /**< \brief (SERCOM1) I2CM Debug Control */
+#define REG_SERCOM1_I2CS_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM1) I2CS Control A */
+#define REG_SERCOM1_I2CS_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM1) I2CS Control B */
+#define REG_SERCOM1_I2CS_INTENCLR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */
+#define REG_SERCOM1_I2CS_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */
+#define REG_SERCOM1_I2CS_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM1_I2CS_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM1) I2CS Status */
+#define REG_SERCOM1_I2CS_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM1) I2CS Synchronization Busy */
+#define REG_SERCOM1_I2CS_ADDR (*(RwReg *)0x42000824U) /**< \brief (SERCOM1) I2CS Address */
+#define REG_SERCOM1_I2CS_DATA (*(RwReg8 *)0x42000828U) /**< \brief (SERCOM1) I2CS Data */
+#define REG_SERCOM1_SPI_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM1) SPI Control A */
+#define REG_SERCOM1_SPI_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM1) SPI Control B */
+#define REG_SERCOM1_SPI_BAUD (*(RwReg8 *)0x4200080CU) /**< \brief (SERCOM1) SPI Baud Rate */
+#define REG_SERCOM1_SPI_INTENCLR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */
+#define REG_SERCOM1_SPI_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM1) SPI Interrupt Enable Set */
+#define REG_SERCOM1_SPI_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM1_SPI_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM1) SPI Status */
+#define REG_SERCOM1_SPI_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM1) SPI Synchronization Busy */
+#define REG_SERCOM1_SPI_ADDR (*(RwReg *)0x42000824U) /**< \brief (SERCOM1) SPI Address */
+#define REG_SERCOM1_SPI_DATA (*(RwReg *)0x42000828U) /**< \brief (SERCOM1) SPI Data */
+#define REG_SERCOM1_SPI_DBGCTRL (*(RwReg8 *)0x42000830U) /**< \brief (SERCOM1) SPI Debug Control */
+#define REG_SERCOM1_USART_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM1) USART Control A */
+#define REG_SERCOM1_USART_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM1) USART Control B */
+#define REG_SERCOM1_USART_CTRLC (*(RwReg *)0x42000808U) /**< \brief (SERCOM1) USART Control C */
+#define REG_SERCOM1_USART_BAUD (*(RwReg16*)0x4200080CU) /**< \brief (SERCOM1) USART Baud Rate */
+#define REG_SERCOM1_USART_RXPL (*(RwReg8 *)0x4200080EU) /**< \brief (SERCOM1) USART Receive Pulse Length */
+#define REG_SERCOM1_USART_INTENCLR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM1) USART Interrupt Enable Clear */
+#define REG_SERCOM1_USART_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM1) USART Interrupt Enable Set */
+#define REG_SERCOM1_USART_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM1_USART_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM1) USART Status */
+#define REG_SERCOM1_USART_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM1) USART Synchronization Busy */
+#define REG_SERCOM1_USART_RXERRCNT (*(RoReg8 *)0x42000820U) /**< \brief (SERCOM1) USART Receive Error Count */
+#define REG_SERCOM1_USART_DATA (*(RwReg16*)0x42000828U) /**< \brief (SERCOM1) USART Data */
+#define REG_SERCOM1_USART_DBGCTRL (*(RwReg8 *)0x42000830U) /**< \brief (SERCOM1) USART Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM1 peripheral ========== */
+#define SERCOM1_DMAC_ID_RX 4 // Index of DMA RX trigger
+#define SERCOM1_DMAC_ID_TX 5 // Index of DMA TX trigger
+#define SERCOM1_GCLK_ID_CORE 17
+#define SERCOM1_GCLK_ID_SLOW 15
+#define SERCOM1_INT_MSB 6
+#define SERCOM1_PMSB 3
+#define SERCOM1_SPI 1 // SPI mode implemented?
+#define SERCOM1_TWIM 1 // TWI Master mode implemented?
+#define SERCOM1_TWIS 1 // TWI Slave mode implemented?
+#define SERCOM1_TWI_HSMODE 1 // TWI HighSpeed mode implemented?
+#define SERCOM1_USART 1 // USART mode implemented?
+#define SERCOM1_USART_ISO7816 1 // USART ISO7816 mode implemented?
+#define SERCOM1_USART_LIN_MASTER 0 // USART LIN Master mode implemented?
+#define SERCOM1_USART_RS485 1 // USART RS485 mode implemented?
+
+#endif /* _SAML22_SERCOM1_INSTANCE_ */
diff --git a/Sensor Watch Starter Project/include/instance/sercom2.h b/Sensor Watch Starter Project/include/instance/sercom2.h new file mode 100755 index 00000000..da68d71f --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/sercom2.h @@ -0,0 +1,156 @@ +/**
+ * \file
+ *
+ * \brief Instance description for SERCOM2
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAML22_SERCOM2_INSTANCE_
+#define _SAML22_SERCOM2_INSTANCE_
+
+/* ========== Register definition for SERCOM2 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM2_I2CM_CTRLA (0x42000C00U) /**< \brief (SERCOM2) I2CM Control A */
+#define REG_SERCOM2_I2CM_CTRLB (0x42000C04U) /**< \brief (SERCOM2) I2CM Control B */
+#define REG_SERCOM2_I2CM_BAUD (0x42000C0CU) /**< \brief (SERCOM2) I2CM Baud Rate */
+#define REG_SERCOM2_I2CM_INTENCLR (0x42000C14U) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */
+#define REG_SERCOM2_I2CM_INTENSET (0x42000C16U) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */
+#define REG_SERCOM2_I2CM_INTFLAG (0x42000C18U) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM2_I2CM_STATUS (0x42000C1AU) /**< \brief (SERCOM2) I2CM Status */
+#define REG_SERCOM2_I2CM_SYNCBUSY (0x42000C1CU) /**< \brief (SERCOM2) I2CM Synchronization Busy */
+#define REG_SERCOM2_I2CM_ADDR (0x42000C24U) /**< \brief (SERCOM2) I2CM Address */
+#define REG_SERCOM2_I2CM_DATA (0x42000C28U) /**< \brief (SERCOM2) I2CM Data */
+#define REG_SERCOM2_I2CM_DBGCTRL (0x42000C30U) /**< \brief (SERCOM2) I2CM Debug Control */
+#define REG_SERCOM2_I2CS_CTRLA (0x42000C00U) /**< \brief (SERCOM2) I2CS Control A */
+#define REG_SERCOM2_I2CS_CTRLB (0x42000C04U) /**< \brief (SERCOM2) I2CS Control B */
+#define REG_SERCOM2_I2CS_INTENCLR (0x42000C14U) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */
+#define REG_SERCOM2_I2CS_INTENSET (0x42000C16U) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */
+#define REG_SERCOM2_I2CS_INTFLAG (0x42000C18U) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM2_I2CS_STATUS (0x42000C1AU) /**< \brief (SERCOM2) I2CS Status */
+#define REG_SERCOM2_I2CS_SYNCBUSY (0x42000C1CU) /**< \brief (SERCOM2) I2CS Synchronization Busy */
+#define REG_SERCOM2_I2CS_ADDR (0x42000C24U) /**< \brief (SERCOM2) I2CS Address */
+#define REG_SERCOM2_I2CS_DATA (0x42000C28U) /**< \brief (SERCOM2) I2CS Data */
+#define REG_SERCOM2_SPI_CTRLA (0x42000C00U) /**< \brief (SERCOM2) SPI Control A */
+#define REG_SERCOM2_SPI_CTRLB (0x42000C04U) /**< \brief (SERCOM2) SPI Control B */
+#define REG_SERCOM2_SPI_BAUD (0x42000C0CU) /**< \brief (SERCOM2) SPI Baud Rate */
+#define REG_SERCOM2_SPI_INTENCLR (0x42000C14U) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */
+#define REG_SERCOM2_SPI_INTENSET (0x42000C16U) /**< \brief (SERCOM2) SPI Interrupt Enable Set */
+#define REG_SERCOM2_SPI_INTFLAG (0x42000C18U) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM2_SPI_STATUS (0x42000C1AU) /**< \brief (SERCOM2) SPI Status */
+#define REG_SERCOM2_SPI_SYNCBUSY (0x42000C1CU) /**< \brief (SERCOM2) SPI Synchronization Busy */
+#define REG_SERCOM2_SPI_ADDR (0x42000C24U) /**< \brief (SERCOM2) SPI Address */
+#define REG_SERCOM2_SPI_DATA (0x42000C28U) /**< \brief (SERCOM2) SPI Data */
+#define REG_SERCOM2_SPI_DBGCTRL (0x42000C30U) /**< \brief (SERCOM2) SPI Debug Control */
+#define REG_SERCOM2_USART_CTRLA (0x42000C00U) /**< \brief (SERCOM2) USART Control A */
+#define REG_SERCOM2_USART_CTRLB (0x42000C04U) /**< \brief (SERCOM2) USART Control B */
+#define REG_SERCOM2_USART_CTRLC (0x42000C08U) /**< \brief (SERCOM2) USART Control C */
+#define REG_SERCOM2_USART_BAUD (0x42000C0CU) /**< \brief (SERCOM2) USART Baud Rate */
+#define REG_SERCOM2_USART_RXPL (0x42000C0EU) /**< \brief (SERCOM2) USART Receive Pulse Length */
+#define REG_SERCOM2_USART_INTENCLR (0x42000C14U) /**< \brief (SERCOM2) USART Interrupt Enable Clear */
+#define REG_SERCOM2_USART_INTENSET (0x42000C16U) /**< \brief (SERCOM2) USART Interrupt Enable Set */
+#define REG_SERCOM2_USART_INTFLAG (0x42000C18U) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM2_USART_STATUS (0x42000C1AU) /**< \brief (SERCOM2) USART Status */
+#define REG_SERCOM2_USART_SYNCBUSY (0x42000C1CU) /**< \brief (SERCOM2) USART Synchronization Busy */
+#define REG_SERCOM2_USART_RXERRCNT (0x42000C20U) /**< \brief (SERCOM2) USART Receive Error Count */
+#define REG_SERCOM2_USART_DATA (0x42000C28U) /**< \brief (SERCOM2) USART Data */
+#define REG_SERCOM2_USART_DBGCTRL (0x42000C30U) /**< \brief (SERCOM2) USART Debug Control */
+#else
+#define REG_SERCOM2_I2CM_CTRLA (*(RwReg *)0x42000C00U) /**< \brief (SERCOM2) I2CM Control A */
+#define REG_SERCOM2_I2CM_CTRLB (*(RwReg *)0x42000C04U) /**< \brief (SERCOM2) I2CM Control B */
+#define REG_SERCOM2_I2CM_BAUD (*(RwReg *)0x42000C0CU) /**< \brief (SERCOM2) I2CM Baud Rate */
+#define REG_SERCOM2_I2CM_INTENCLR (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */
+#define REG_SERCOM2_I2CM_INTENSET (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */
+#define REG_SERCOM2_I2CM_INTFLAG (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM2_I2CM_STATUS (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM2) I2CM Status */
+#define REG_SERCOM2_I2CM_SYNCBUSY (*(RoReg *)0x42000C1CU) /**< \brief (SERCOM2) I2CM Synchronization Busy */
+#define REG_SERCOM2_I2CM_ADDR (*(RwReg *)0x42000C24U) /**< \brief (SERCOM2) I2CM Address */
+#define REG_SERCOM2_I2CM_DATA (*(RwReg8 *)0x42000C28U) /**< \brief (SERCOM2) I2CM Data */
+#define REG_SERCOM2_I2CM_DBGCTRL (*(RwReg8 *)0x42000C30U) /**< \brief (SERCOM2) I2CM Debug Control */
+#define REG_SERCOM2_I2CS_CTRLA (*(RwReg *)0x42000C00U) /**< \brief (SERCOM2) I2CS Control A */
+#define REG_SERCOM2_I2CS_CTRLB (*(RwReg *)0x42000C04U) /**< \brief (SERCOM2) I2CS Control B */
+#define REG_SERCOM2_I2CS_INTENCLR (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */
+#define REG_SERCOM2_I2CS_INTENSET (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */
+#define REG_SERCOM2_I2CS_INTFLAG (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM2_I2CS_STATUS (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM2) I2CS Status */
+#define REG_SERCOM2_I2CS_SYNCBUSY (*(RoReg *)0x42000C1CU) /**< \brief (SERCOM2) I2CS Synchronization Busy */
+#define REG_SERCOM2_I2CS_ADDR (*(RwReg *)0x42000C24U) /**< \brief (SERCOM2) I2CS Address */
+#define REG_SERCOM2_I2CS_DATA (*(RwReg8 *)0x42000C28U) /**< \brief (SERCOM2) I2CS Data */
+#define REG_SERCOM2_SPI_CTRLA (*(RwReg *)0x42000C00U) /**< \brief (SERCOM2) SPI Control A */
+#define REG_SERCOM2_SPI_CTRLB (*(RwReg *)0x42000C04U) /**< \brief (SERCOM2) SPI Control B */
+#define REG_SERCOM2_SPI_BAUD (*(RwReg8 *)0x42000C0CU) /**< \brief (SERCOM2) SPI Baud Rate */
+#define REG_SERCOM2_SPI_INTENCLR (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */
+#define REG_SERCOM2_SPI_INTENSET (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM2) SPI Interrupt Enable Set */
+#define REG_SERCOM2_SPI_INTFLAG (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM2_SPI_STATUS (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM2) SPI Status */
+#define REG_SERCOM2_SPI_SYNCBUSY (*(RoReg *)0x42000C1CU) /**< \brief (SERCOM2) SPI Synchronization Busy */
+#define REG_SERCOM2_SPI_ADDR (*(RwReg *)0x42000C24U) /**< \brief (SERCOM2) SPI Address */
+#define REG_SERCOM2_SPI_DATA (*(RwReg *)0x42000C28U) /**< \brief (SERCOM2) SPI Data */
+#define REG_SERCOM2_SPI_DBGCTRL (*(RwReg8 *)0x42000C30U) /**< \brief (SERCOM2) SPI Debug Control */
+#define REG_SERCOM2_USART_CTRLA (*(RwReg *)0x42000C00U) /**< \brief (SERCOM2) USART Control A */
+#define REG_SERCOM2_USART_CTRLB (*(RwReg *)0x42000C04U) /**< \brief (SERCOM2) USART Control B */
+#define REG_SERCOM2_USART_CTRLC (*(RwReg *)0x42000C08U) /**< \brief (SERCOM2) USART Control C */
+#define REG_SERCOM2_USART_BAUD (*(RwReg16*)0x42000C0CU) /**< \brief (SERCOM2) USART Baud Rate */
+#define REG_SERCOM2_USART_RXPL (*(RwReg8 *)0x42000C0EU) /**< \brief (SERCOM2) USART Receive Pulse Length */
+#define REG_SERCOM2_USART_INTENCLR (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM2) USART Interrupt Enable Clear */
+#define REG_SERCOM2_USART_INTENSET (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM2) USART Interrupt Enable Set */
+#define REG_SERCOM2_USART_INTFLAG (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM2_USART_STATUS (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM2) USART Status */
+#define REG_SERCOM2_USART_SYNCBUSY (*(RoReg *)0x42000C1CU) /**< \brief (SERCOM2) USART Synchronization Busy */
+#define REG_SERCOM2_USART_RXERRCNT (*(RoReg8 *)0x42000C20U) /**< \brief (SERCOM2) USART Receive Error Count */
+#define REG_SERCOM2_USART_DATA (*(RwReg16*)0x42000C28U) /**< \brief (SERCOM2) USART Data */
+#define REG_SERCOM2_USART_DBGCTRL (*(RwReg8 *)0x42000C30U) /**< \brief (SERCOM2) USART Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM2 peripheral ========== */
+#define SERCOM2_DMAC_ID_RX 6 // Index of DMA RX trigger
+#define SERCOM2_DMAC_ID_TX 7 // Index of DMA TX trigger
+#define SERCOM2_GCLK_ID_CORE 18
+#define SERCOM2_GCLK_ID_SLOW 15
+#define SERCOM2_INT_MSB 6
+#define SERCOM2_PMSB 3
+#define SERCOM2_SPI 1 // SPI mode implemented?
+#define SERCOM2_TWIM 1 // TWI Master mode implemented?
+#define SERCOM2_TWIS 1 // TWI Slave mode implemented?
+#define SERCOM2_TWI_HSMODE 0 // TWI HighSpeed mode implemented?
+#define SERCOM2_USART 1 // USART mode implemented?
+#define SERCOM2_USART_ISO7816 1 // USART ISO7816 mode implemented?
+#define SERCOM2_USART_LIN_MASTER 0 // USART LIN Master mode implemented?
+#define SERCOM2_USART_RS485 1 // USART RS485 mode implemented?
+
+#endif /* _SAML22_SERCOM2_INSTANCE_ */
diff --git a/Sensor Watch Starter Project/include/instance/sercom3.h b/Sensor Watch Starter Project/include/instance/sercom3.h new file mode 100755 index 00000000..2d310a73 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/sercom3.h @@ -0,0 +1,156 @@ +/**
+ * \file
+ *
+ * \brief Instance description for SERCOM3
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAML22_SERCOM3_INSTANCE_
+#define _SAML22_SERCOM3_INSTANCE_
+
+/* ========== Register definition for SERCOM3 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM3_I2CM_CTRLA (0x42001000U) /**< \brief (SERCOM3) I2CM Control A */
+#define REG_SERCOM3_I2CM_CTRLB (0x42001004U) /**< \brief (SERCOM3) I2CM Control B */
+#define REG_SERCOM3_I2CM_BAUD (0x4200100CU) /**< \brief (SERCOM3) I2CM Baud Rate */
+#define REG_SERCOM3_I2CM_INTENCLR (0x42001014U) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */
+#define REG_SERCOM3_I2CM_INTENSET (0x42001016U) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */
+#define REG_SERCOM3_I2CM_INTFLAG (0x42001018U) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM3_I2CM_STATUS (0x4200101AU) /**< \brief (SERCOM3) I2CM Status */
+#define REG_SERCOM3_I2CM_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM3) I2CM Synchronization Busy */
+#define REG_SERCOM3_I2CM_ADDR (0x42001024U) /**< \brief (SERCOM3) I2CM Address */
+#define REG_SERCOM3_I2CM_DATA (0x42001028U) /**< \brief (SERCOM3) I2CM Data */
+#define REG_SERCOM3_I2CM_DBGCTRL (0x42001030U) /**< \brief (SERCOM3) I2CM Debug Control */
+#define REG_SERCOM3_I2CS_CTRLA (0x42001000U) /**< \brief (SERCOM3) I2CS Control A */
+#define REG_SERCOM3_I2CS_CTRLB (0x42001004U) /**< \brief (SERCOM3) I2CS Control B */
+#define REG_SERCOM3_I2CS_INTENCLR (0x42001014U) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */
+#define REG_SERCOM3_I2CS_INTENSET (0x42001016U) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */
+#define REG_SERCOM3_I2CS_INTFLAG (0x42001018U) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM3_I2CS_STATUS (0x4200101AU) /**< \brief (SERCOM3) I2CS Status */
+#define REG_SERCOM3_I2CS_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM3) I2CS Synchronization Busy */
+#define REG_SERCOM3_I2CS_ADDR (0x42001024U) /**< \brief (SERCOM3) I2CS Address */
+#define REG_SERCOM3_I2CS_DATA (0x42001028U) /**< \brief (SERCOM3) I2CS Data */
+#define REG_SERCOM3_SPI_CTRLA (0x42001000U) /**< \brief (SERCOM3) SPI Control A */
+#define REG_SERCOM3_SPI_CTRLB (0x42001004U) /**< \brief (SERCOM3) SPI Control B */
+#define REG_SERCOM3_SPI_BAUD (0x4200100CU) /**< \brief (SERCOM3) SPI Baud Rate */
+#define REG_SERCOM3_SPI_INTENCLR (0x42001014U) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */
+#define REG_SERCOM3_SPI_INTENSET (0x42001016U) /**< \brief (SERCOM3) SPI Interrupt Enable Set */
+#define REG_SERCOM3_SPI_INTFLAG (0x42001018U) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM3_SPI_STATUS (0x4200101AU) /**< \brief (SERCOM3) SPI Status */
+#define REG_SERCOM3_SPI_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM3) SPI Synchronization Busy */
+#define REG_SERCOM3_SPI_ADDR (0x42001024U) /**< \brief (SERCOM3) SPI Address */
+#define REG_SERCOM3_SPI_DATA (0x42001028U) /**< \brief (SERCOM3) SPI Data */
+#define REG_SERCOM3_SPI_DBGCTRL (0x42001030U) /**< \brief (SERCOM3) SPI Debug Control */
+#define REG_SERCOM3_USART_CTRLA (0x42001000U) /**< \brief (SERCOM3) USART Control A */
+#define REG_SERCOM3_USART_CTRLB (0x42001004U) /**< \brief (SERCOM3) USART Control B */
+#define REG_SERCOM3_USART_CTRLC (0x42001008U) /**< \brief (SERCOM3) USART Control C */
+#define REG_SERCOM3_USART_BAUD (0x4200100CU) /**< \brief (SERCOM3) USART Baud Rate */
+#define REG_SERCOM3_USART_RXPL (0x4200100EU) /**< \brief (SERCOM3) USART Receive Pulse Length */
+#define REG_SERCOM3_USART_INTENCLR (0x42001014U) /**< \brief (SERCOM3) USART Interrupt Enable Clear */
+#define REG_SERCOM3_USART_INTENSET (0x42001016U) /**< \brief (SERCOM3) USART Interrupt Enable Set */
+#define REG_SERCOM3_USART_INTFLAG (0x42001018U) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM3_USART_STATUS (0x4200101AU) /**< \brief (SERCOM3) USART Status */
+#define REG_SERCOM3_USART_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM3) USART Synchronization Busy */
+#define REG_SERCOM3_USART_RXERRCNT (0x42001020U) /**< \brief (SERCOM3) USART Receive Error Count */
+#define REG_SERCOM3_USART_DATA (0x42001028U) /**< \brief (SERCOM3) USART Data */
+#define REG_SERCOM3_USART_DBGCTRL (0x42001030U) /**< \brief (SERCOM3) USART Debug Control */
+#else
+#define REG_SERCOM3_I2CM_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM3) I2CM Control A */
+#define REG_SERCOM3_I2CM_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM3) I2CM Control B */
+#define REG_SERCOM3_I2CM_BAUD (*(RwReg *)0x4200100CU) /**< \brief (SERCOM3) I2CM Baud Rate */
+#define REG_SERCOM3_I2CM_INTENCLR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */
+#define REG_SERCOM3_I2CM_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */
+#define REG_SERCOM3_I2CM_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM3_I2CM_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM3) I2CM Status */
+#define REG_SERCOM3_I2CM_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM3) I2CM Synchronization Busy */
+#define REG_SERCOM3_I2CM_ADDR (*(RwReg *)0x42001024U) /**< \brief (SERCOM3) I2CM Address */
+#define REG_SERCOM3_I2CM_DATA (*(RwReg8 *)0x42001028U) /**< \brief (SERCOM3) I2CM Data */
+#define REG_SERCOM3_I2CM_DBGCTRL (*(RwReg8 *)0x42001030U) /**< \brief (SERCOM3) I2CM Debug Control */
+#define REG_SERCOM3_I2CS_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM3) I2CS Control A */
+#define REG_SERCOM3_I2CS_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM3) I2CS Control B */
+#define REG_SERCOM3_I2CS_INTENCLR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */
+#define REG_SERCOM3_I2CS_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */
+#define REG_SERCOM3_I2CS_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM3_I2CS_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM3) I2CS Status */
+#define REG_SERCOM3_I2CS_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM3) I2CS Synchronization Busy */
+#define REG_SERCOM3_I2CS_ADDR (*(RwReg *)0x42001024U) /**< \brief (SERCOM3) I2CS Address */
+#define REG_SERCOM3_I2CS_DATA (*(RwReg8 *)0x42001028U) /**< \brief (SERCOM3) I2CS Data */
+#define REG_SERCOM3_SPI_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM3) SPI Control A */
+#define REG_SERCOM3_SPI_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM3) SPI Control B */
+#define REG_SERCOM3_SPI_BAUD (*(RwReg8 *)0x4200100CU) /**< \brief (SERCOM3) SPI Baud Rate */
+#define REG_SERCOM3_SPI_INTENCLR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */
+#define REG_SERCOM3_SPI_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM3) SPI Interrupt Enable Set */
+#define REG_SERCOM3_SPI_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM3_SPI_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM3) SPI Status */
+#define REG_SERCOM3_SPI_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM3) SPI Synchronization Busy */
+#define REG_SERCOM3_SPI_ADDR (*(RwReg *)0x42001024U) /**< \brief (SERCOM3) SPI Address */
+#define REG_SERCOM3_SPI_DATA (*(RwReg *)0x42001028U) /**< \brief (SERCOM3) SPI Data */
+#define REG_SERCOM3_SPI_DBGCTRL (*(RwReg8 *)0x42001030U) /**< \brief (SERCOM3) SPI Debug Control */
+#define REG_SERCOM3_USART_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM3) USART Control A */
+#define REG_SERCOM3_USART_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM3) USART Control B */
+#define REG_SERCOM3_USART_CTRLC (*(RwReg *)0x42001008U) /**< \brief (SERCOM3) USART Control C */
+#define REG_SERCOM3_USART_BAUD (*(RwReg16*)0x4200100CU) /**< \brief (SERCOM3) USART Baud Rate */
+#define REG_SERCOM3_USART_RXPL (*(RwReg8 *)0x4200100EU) /**< \brief (SERCOM3) USART Receive Pulse Length */
+#define REG_SERCOM3_USART_INTENCLR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM3) USART Interrupt Enable Clear */
+#define REG_SERCOM3_USART_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM3) USART Interrupt Enable Set */
+#define REG_SERCOM3_USART_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM3_USART_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM3) USART Status */
+#define REG_SERCOM3_USART_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM3) USART Synchronization Busy */
+#define REG_SERCOM3_USART_RXERRCNT (*(RoReg8 *)0x42001020U) /**< \brief (SERCOM3) USART Receive Error Count */
+#define REG_SERCOM3_USART_DATA (*(RwReg16*)0x42001028U) /**< \brief (SERCOM3) USART Data */
+#define REG_SERCOM3_USART_DBGCTRL (*(RwReg8 *)0x42001030U) /**< \brief (SERCOM3) USART Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM3 peripheral ========== */
+#define SERCOM3_DMAC_ID_RX 8 // Index of DMA RX trigger
+#define SERCOM3_DMAC_ID_TX 9 // Index of DMA TX trigger
+#define SERCOM3_GCLK_ID_CORE 19
+#define SERCOM3_GCLK_ID_SLOW 15
+#define SERCOM3_INT_MSB 6
+#define SERCOM3_PMSB 3
+#define SERCOM3_SPI 1 // SPI mode implemented?
+#define SERCOM3_TWIM 1 // TWI Master mode implemented?
+#define SERCOM3_TWIS 1 // TWI Slave mode implemented?
+#define SERCOM3_TWI_HSMODE 0 // TWI HighSpeed mode implemented?
+#define SERCOM3_USART 1 // USART mode implemented?
+#define SERCOM3_USART_ISO7816 1 // USART ISO7816 mode implemented?
+#define SERCOM3_USART_LIN_MASTER 0 // USART LIN Master mode implemented?
+#define SERCOM3_USART_RS485 1 // USART RS485 mode implemented?
+
+#endif /* _SAML22_SERCOM3_INSTANCE_ */
diff --git a/Sensor Watch Starter Project/include/instance/sercom4.h b/Sensor Watch Starter Project/include/instance/sercom4.h new file mode 100755 index 00000000..ce53d4f2 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/sercom4.h @@ -0,0 +1,156 @@ +/**
+ * \file
+ *
+ * \brief Instance description for SERCOM4
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAML22_SERCOM4_INSTANCE_
+#define _SAML22_SERCOM4_INSTANCE_
+
+/* ========== Register definition for SERCOM4 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM4_I2CM_CTRLA (0x42001400U) /**< \brief (SERCOM4) I2CM Control A */
+#define REG_SERCOM4_I2CM_CTRLB (0x42001404U) /**< \brief (SERCOM4) I2CM Control B */
+#define REG_SERCOM4_I2CM_BAUD (0x4200140CU) /**< \brief (SERCOM4) I2CM Baud Rate */
+#define REG_SERCOM4_I2CM_INTENCLR (0x42001414U) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */
+#define REG_SERCOM4_I2CM_INTENSET (0x42001416U) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */
+#define REG_SERCOM4_I2CM_INTFLAG (0x42001418U) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM4_I2CM_STATUS (0x4200141AU) /**< \brief (SERCOM4) I2CM Status */
+#define REG_SERCOM4_I2CM_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM4) I2CM Synchronization Busy */
+#define REG_SERCOM4_I2CM_ADDR (0x42001424U) /**< \brief (SERCOM4) I2CM Address */
+#define REG_SERCOM4_I2CM_DATA (0x42001428U) /**< \brief (SERCOM4) I2CM Data */
+#define REG_SERCOM4_I2CM_DBGCTRL (0x42001430U) /**< \brief (SERCOM4) I2CM Debug Control */
+#define REG_SERCOM4_I2CS_CTRLA (0x42001400U) /**< \brief (SERCOM4) I2CS Control A */
+#define REG_SERCOM4_I2CS_CTRLB (0x42001404U) /**< \brief (SERCOM4) I2CS Control B */
+#define REG_SERCOM4_I2CS_INTENCLR (0x42001414U) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */
+#define REG_SERCOM4_I2CS_INTENSET (0x42001416U) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */
+#define REG_SERCOM4_I2CS_INTFLAG (0x42001418U) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM4_I2CS_STATUS (0x4200141AU) /**< \brief (SERCOM4) I2CS Status */
+#define REG_SERCOM4_I2CS_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM4) I2CS Synchronization Busy */
+#define REG_SERCOM4_I2CS_ADDR (0x42001424U) /**< \brief (SERCOM4) I2CS Address */
+#define REG_SERCOM4_I2CS_DATA (0x42001428U) /**< \brief (SERCOM4) I2CS Data */
+#define REG_SERCOM4_SPI_CTRLA (0x42001400U) /**< \brief (SERCOM4) SPI Control A */
+#define REG_SERCOM4_SPI_CTRLB (0x42001404U) /**< \brief (SERCOM4) SPI Control B */
+#define REG_SERCOM4_SPI_BAUD (0x4200140CU) /**< \brief (SERCOM4) SPI Baud Rate */
+#define REG_SERCOM4_SPI_INTENCLR (0x42001414U) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */
+#define REG_SERCOM4_SPI_INTENSET (0x42001416U) /**< \brief (SERCOM4) SPI Interrupt Enable Set */
+#define REG_SERCOM4_SPI_INTFLAG (0x42001418U) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM4_SPI_STATUS (0x4200141AU) /**< \brief (SERCOM4) SPI Status */
+#define REG_SERCOM4_SPI_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM4) SPI Synchronization Busy */
+#define REG_SERCOM4_SPI_ADDR (0x42001424U) /**< \brief (SERCOM4) SPI Address */
+#define REG_SERCOM4_SPI_DATA (0x42001428U) /**< \brief (SERCOM4) SPI Data */
+#define REG_SERCOM4_SPI_DBGCTRL (0x42001430U) /**< \brief (SERCOM4) SPI Debug Control */
+#define REG_SERCOM4_USART_CTRLA (0x42001400U) /**< \brief (SERCOM4) USART Control A */
+#define REG_SERCOM4_USART_CTRLB (0x42001404U) /**< \brief (SERCOM4) USART Control B */
+#define REG_SERCOM4_USART_CTRLC (0x42001408U) /**< \brief (SERCOM4) USART Control C */
+#define REG_SERCOM4_USART_BAUD (0x4200140CU) /**< \brief (SERCOM4) USART Baud Rate */
+#define REG_SERCOM4_USART_RXPL (0x4200140EU) /**< \brief (SERCOM4) USART Receive Pulse Length */
+#define REG_SERCOM4_USART_INTENCLR (0x42001414U) /**< \brief (SERCOM4) USART Interrupt Enable Clear */
+#define REG_SERCOM4_USART_INTENSET (0x42001416U) /**< \brief (SERCOM4) USART Interrupt Enable Set */
+#define REG_SERCOM4_USART_INTFLAG (0x42001418U) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM4_USART_STATUS (0x4200141AU) /**< \brief (SERCOM4) USART Status */
+#define REG_SERCOM4_USART_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM4) USART Synchronization Busy */
+#define REG_SERCOM4_USART_RXERRCNT (0x42001420U) /**< \brief (SERCOM4) USART Receive Error Count */
+#define REG_SERCOM4_USART_DATA (0x42001428U) /**< \brief (SERCOM4) USART Data */
+#define REG_SERCOM4_USART_DBGCTRL (0x42001430U) /**< \brief (SERCOM4) USART Debug Control */
+#else
+#define REG_SERCOM4_I2CM_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM4) I2CM Control A */
+#define REG_SERCOM4_I2CM_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM4) I2CM Control B */
+#define REG_SERCOM4_I2CM_BAUD (*(RwReg *)0x4200140CU) /**< \brief (SERCOM4) I2CM Baud Rate */
+#define REG_SERCOM4_I2CM_INTENCLR (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */
+#define REG_SERCOM4_I2CM_INTENSET (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */
+#define REG_SERCOM4_I2CM_INTFLAG (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM4_I2CM_STATUS (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM4) I2CM Status */
+#define REG_SERCOM4_I2CM_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM4) I2CM Synchronization Busy */
+#define REG_SERCOM4_I2CM_ADDR (*(RwReg *)0x42001424U) /**< \brief (SERCOM4) I2CM Address */
+#define REG_SERCOM4_I2CM_DATA (*(RwReg8 *)0x42001428U) /**< \brief (SERCOM4) I2CM Data */
+#define REG_SERCOM4_I2CM_DBGCTRL (*(RwReg8 *)0x42001430U) /**< \brief (SERCOM4) I2CM Debug Control */
+#define REG_SERCOM4_I2CS_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM4) I2CS Control A */
+#define REG_SERCOM4_I2CS_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM4) I2CS Control B */
+#define REG_SERCOM4_I2CS_INTENCLR (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */
+#define REG_SERCOM4_I2CS_INTENSET (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */
+#define REG_SERCOM4_I2CS_INTFLAG (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM4_I2CS_STATUS (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM4) I2CS Status */
+#define REG_SERCOM4_I2CS_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM4) I2CS Synchronization Busy */
+#define REG_SERCOM4_I2CS_ADDR (*(RwReg *)0x42001424U) /**< \brief (SERCOM4) I2CS Address */
+#define REG_SERCOM4_I2CS_DATA (*(RwReg8 *)0x42001428U) /**< \brief (SERCOM4) I2CS Data */
+#define REG_SERCOM4_SPI_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM4) SPI Control A */
+#define REG_SERCOM4_SPI_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM4) SPI Control B */
+#define REG_SERCOM4_SPI_BAUD (*(RwReg8 *)0x4200140CU) /**< \brief (SERCOM4) SPI Baud Rate */
+#define REG_SERCOM4_SPI_INTENCLR (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */
+#define REG_SERCOM4_SPI_INTENSET (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM4) SPI Interrupt Enable Set */
+#define REG_SERCOM4_SPI_INTFLAG (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM4_SPI_STATUS (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM4) SPI Status */
+#define REG_SERCOM4_SPI_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM4) SPI Synchronization Busy */
+#define REG_SERCOM4_SPI_ADDR (*(RwReg *)0x42001424U) /**< \brief (SERCOM4) SPI Address */
+#define REG_SERCOM4_SPI_DATA (*(RwReg *)0x42001428U) /**< \brief (SERCOM4) SPI Data */
+#define REG_SERCOM4_SPI_DBGCTRL (*(RwReg8 *)0x42001430U) /**< \brief (SERCOM4) SPI Debug Control */
+#define REG_SERCOM4_USART_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM4) USART Control A */
+#define REG_SERCOM4_USART_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM4) USART Control B */
+#define REG_SERCOM4_USART_CTRLC (*(RwReg *)0x42001408U) /**< \brief (SERCOM4) USART Control C */
+#define REG_SERCOM4_USART_BAUD (*(RwReg16*)0x4200140CU) /**< \brief (SERCOM4) USART Baud Rate */
+#define REG_SERCOM4_USART_RXPL (*(RwReg8 *)0x4200140EU) /**< \brief (SERCOM4) USART Receive Pulse Length */
+#define REG_SERCOM4_USART_INTENCLR (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM4) USART Interrupt Enable Clear */
+#define REG_SERCOM4_USART_INTENSET (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM4) USART Interrupt Enable Set */
+#define REG_SERCOM4_USART_INTFLAG (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM4_USART_STATUS (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM4) USART Status */
+#define REG_SERCOM4_USART_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM4) USART Synchronization Busy */
+#define REG_SERCOM4_USART_RXERRCNT (*(RoReg8 *)0x42001420U) /**< \brief (SERCOM4) USART Receive Error Count */
+#define REG_SERCOM4_USART_DATA (*(RwReg16*)0x42001428U) /**< \brief (SERCOM4) USART Data */
+#define REG_SERCOM4_USART_DBGCTRL (*(RwReg8 *)0x42001430U) /**< \brief (SERCOM4) USART Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM4 peripheral ========== */
+#define SERCOM4_DMAC_ID_RX 10 // Index of DMA RX trigger
+#define SERCOM4_DMAC_ID_TX 11 // Index of DMA TX trigger
+#define SERCOM4_GCLK_ID_CORE 20
+#define SERCOM4_GCLK_ID_SLOW 15
+#define SERCOM4_INT_MSB 6
+#define SERCOM4_PMSB 3
+#define SERCOM4_SPI 1 // SPI mode implemented?
+#define SERCOM4_TWIM 1 // TWI Master mode implemented?
+#define SERCOM4_TWIS 1 // TWI Slave mode implemented?
+#define SERCOM4_TWI_HSMODE 0 // TWI HighSpeed mode implemented?
+#define SERCOM4_USART 1 // USART mode implemented?
+#define SERCOM4_USART_ISO7816 1 // USART ISO7816 mode implemented?
+#define SERCOM4_USART_LIN_MASTER 0 // USART LIN Master mode implemented?
+#define SERCOM4_USART_RS485 1 // USART RS485 mode implemented?
+
+#endif /* _SAML22_SERCOM4_INSTANCE_ */
diff --git a/Sensor Watch Starter Project/include/instance/sercom5.h b/Sensor Watch Starter Project/include/instance/sercom5.h new file mode 100755 index 00000000..6aabf3a8 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/sercom5.h @@ -0,0 +1,156 @@ +/**
+ * \file
+ *
+ * \brief Instance description for SERCOM5
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAML22_SERCOM5_INSTANCE_
+#define _SAML22_SERCOM5_INSTANCE_
+
+/* ========== Register definition for SERCOM5 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM5_I2CM_CTRLA (0x42001800U) /**< \brief (SERCOM5) I2CM Control A */
+#define REG_SERCOM5_I2CM_CTRLB (0x42001804U) /**< \brief (SERCOM5) I2CM Control B */
+#define REG_SERCOM5_I2CM_BAUD (0x4200180CU) /**< \brief (SERCOM5) I2CM Baud Rate */
+#define REG_SERCOM5_I2CM_INTENCLR (0x42001814U) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */
+#define REG_SERCOM5_I2CM_INTENSET (0x42001816U) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */
+#define REG_SERCOM5_I2CM_INTFLAG (0x42001818U) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM5_I2CM_STATUS (0x4200181AU) /**< \brief (SERCOM5) I2CM Status */
+#define REG_SERCOM5_I2CM_SYNCBUSY (0x4200181CU) /**< \brief (SERCOM5) I2CM Synchronization Busy */
+#define REG_SERCOM5_I2CM_ADDR (0x42001824U) /**< \brief (SERCOM5) I2CM Address */
+#define REG_SERCOM5_I2CM_DATA (0x42001828U) /**< \brief (SERCOM5) I2CM Data */
+#define REG_SERCOM5_I2CM_DBGCTRL (0x42001830U) /**< \brief (SERCOM5) I2CM Debug Control */
+#define REG_SERCOM5_I2CS_CTRLA (0x42001800U) /**< \brief (SERCOM5) I2CS Control A */
+#define REG_SERCOM5_I2CS_CTRLB (0x42001804U) /**< \brief (SERCOM5) I2CS Control B */
+#define REG_SERCOM5_I2CS_INTENCLR (0x42001814U) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */
+#define REG_SERCOM5_I2CS_INTENSET (0x42001816U) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */
+#define REG_SERCOM5_I2CS_INTFLAG (0x42001818U) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM5_I2CS_STATUS (0x4200181AU) /**< \brief (SERCOM5) I2CS Status */
+#define REG_SERCOM5_I2CS_SYNCBUSY (0x4200181CU) /**< \brief (SERCOM5) I2CS Synchronization Busy */
+#define REG_SERCOM5_I2CS_ADDR (0x42001824U) /**< \brief (SERCOM5) I2CS Address */
+#define REG_SERCOM5_I2CS_DATA (0x42001828U) /**< \brief (SERCOM5) I2CS Data */
+#define REG_SERCOM5_SPI_CTRLA (0x42001800U) /**< \brief (SERCOM5) SPI Control A */
+#define REG_SERCOM5_SPI_CTRLB (0x42001804U) /**< \brief (SERCOM5) SPI Control B */
+#define REG_SERCOM5_SPI_BAUD (0x4200180CU) /**< \brief (SERCOM5) SPI Baud Rate */
+#define REG_SERCOM5_SPI_INTENCLR (0x42001814U) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */
+#define REG_SERCOM5_SPI_INTENSET (0x42001816U) /**< \brief (SERCOM5) SPI Interrupt Enable Set */
+#define REG_SERCOM5_SPI_INTFLAG (0x42001818U) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM5_SPI_STATUS (0x4200181AU) /**< \brief (SERCOM5) SPI Status */
+#define REG_SERCOM5_SPI_SYNCBUSY (0x4200181CU) /**< \brief (SERCOM5) SPI Synchronization Busy */
+#define REG_SERCOM5_SPI_ADDR (0x42001824U) /**< \brief (SERCOM5) SPI Address */
+#define REG_SERCOM5_SPI_DATA (0x42001828U) /**< \brief (SERCOM5) SPI Data */
+#define REG_SERCOM5_SPI_DBGCTRL (0x42001830U) /**< \brief (SERCOM5) SPI Debug Control */
+#define REG_SERCOM5_USART_CTRLA (0x42001800U) /**< \brief (SERCOM5) USART Control A */
+#define REG_SERCOM5_USART_CTRLB (0x42001804U) /**< \brief (SERCOM5) USART Control B */
+#define REG_SERCOM5_USART_CTRLC (0x42001808U) /**< \brief (SERCOM5) USART Control C */
+#define REG_SERCOM5_USART_BAUD (0x4200180CU) /**< \brief (SERCOM5) USART Baud Rate */
+#define REG_SERCOM5_USART_RXPL (0x4200180EU) /**< \brief (SERCOM5) USART Receive Pulse Length */
+#define REG_SERCOM5_USART_INTENCLR (0x42001814U) /**< \brief (SERCOM5) USART Interrupt Enable Clear */
+#define REG_SERCOM5_USART_INTENSET (0x42001816U) /**< \brief (SERCOM5) USART Interrupt Enable Set */
+#define REG_SERCOM5_USART_INTFLAG (0x42001818U) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM5_USART_STATUS (0x4200181AU) /**< \brief (SERCOM5) USART Status */
+#define REG_SERCOM5_USART_SYNCBUSY (0x4200181CU) /**< \brief (SERCOM5) USART Synchronization Busy */
+#define REG_SERCOM5_USART_RXERRCNT (0x42001820U) /**< \brief (SERCOM5) USART Receive Error Count */
+#define REG_SERCOM5_USART_DATA (0x42001828U) /**< \brief (SERCOM5) USART Data */
+#define REG_SERCOM5_USART_DBGCTRL (0x42001830U) /**< \brief (SERCOM5) USART Debug Control */
+#else
+#define REG_SERCOM5_I2CM_CTRLA (*(RwReg *)0x42001800U) /**< \brief (SERCOM5) I2CM Control A */
+#define REG_SERCOM5_I2CM_CTRLB (*(RwReg *)0x42001804U) /**< \brief (SERCOM5) I2CM Control B */
+#define REG_SERCOM5_I2CM_BAUD (*(RwReg *)0x4200180CU) /**< \brief (SERCOM5) I2CM Baud Rate */
+#define REG_SERCOM5_I2CM_INTENCLR (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */
+#define REG_SERCOM5_I2CM_INTENSET (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */
+#define REG_SERCOM5_I2CM_INTFLAG (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM5_I2CM_STATUS (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM5) I2CM Status */
+#define REG_SERCOM5_I2CM_SYNCBUSY (*(RoReg *)0x4200181CU) /**< \brief (SERCOM5) I2CM Synchronization Busy */
+#define REG_SERCOM5_I2CM_ADDR (*(RwReg *)0x42001824U) /**< \brief (SERCOM5) I2CM Address */
+#define REG_SERCOM5_I2CM_DATA (*(RwReg8 *)0x42001828U) /**< \brief (SERCOM5) I2CM Data */
+#define REG_SERCOM5_I2CM_DBGCTRL (*(RwReg8 *)0x42001830U) /**< \brief (SERCOM5) I2CM Debug Control */
+#define REG_SERCOM5_I2CS_CTRLA (*(RwReg *)0x42001800U) /**< \brief (SERCOM5) I2CS Control A */
+#define REG_SERCOM5_I2CS_CTRLB (*(RwReg *)0x42001804U) /**< \brief (SERCOM5) I2CS Control B */
+#define REG_SERCOM5_I2CS_INTENCLR (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */
+#define REG_SERCOM5_I2CS_INTENSET (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */
+#define REG_SERCOM5_I2CS_INTFLAG (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM5_I2CS_STATUS (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM5) I2CS Status */
+#define REG_SERCOM5_I2CS_SYNCBUSY (*(RoReg *)0x4200181CU) /**< \brief (SERCOM5) I2CS Synchronization Busy */
+#define REG_SERCOM5_I2CS_ADDR (*(RwReg *)0x42001824U) /**< \brief (SERCOM5) I2CS Address */
+#define REG_SERCOM5_I2CS_DATA (*(RwReg8 *)0x42001828U) /**< \brief (SERCOM5) I2CS Data */
+#define REG_SERCOM5_SPI_CTRLA (*(RwReg *)0x42001800U) /**< \brief (SERCOM5) SPI Control A */
+#define REG_SERCOM5_SPI_CTRLB (*(RwReg *)0x42001804U) /**< \brief (SERCOM5) SPI Control B */
+#define REG_SERCOM5_SPI_BAUD (*(RwReg8 *)0x4200180CU) /**< \brief (SERCOM5) SPI Baud Rate */
+#define REG_SERCOM5_SPI_INTENCLR (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */
+#define REG_SERCOM5_SPI_INTENSET (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM5) SPI Interrupt Enable Set */
+#define REG_SERCOM5_SPI_INTFLAG (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM5_SPI_STATUS (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM5) SPI Status */
+#define REG_SERCOM5_SPI_SYNCBUSY (*(RoReg *)0x4200181CU) /**< \brief (SERCOM5) SPI Synchronization Busy */
+#define REG_SERCOM5_SPI_ADDR (*(RwReg *)0x42001824U) /**< \brief (SERCOM5) SPI Address */
+#define REG_SERCOM5_SPI_DATA (*(RwReg *)0x42001828U) /**< \brief (SERCOM5) SPI Data */
+#define REG_SERCOM5_SPI_DBGCTRL (*(RwReg8 *)0x42001830U) /**< \brief (SERCOM5) SPI Debug Control */
+#define REG_SERCOM5_USART_CTRLA (*(RwReg *)0x42001800U) /**< \brief (SERCOM5) USART Control A */
+#define REG_SERCOM5_USART_CTRLB (*(RwReg *)0x42001804U) /**< \brief (SERCOM5) USART Control B */
+#define REG_SERCOM5_USART_CTRLC (*(RwReg *)0x42001808U) /**< \brief (SERCOM5) USART Control C */
+#define REG_SERCOM5_USART_BAUD (*(RwReg16*)0x4200180CU) /**< \brief (SERCOM5) USART Baud Rate */
+#define REG_SERCOM5_USART_RXPL (*(RwReg8 *)0x4200180EU) /**< \brief (SERCOM5) USART Receive Pulse Length */
+#define REG_SERCOM5_USART_INTENCLR (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM5) USART Interrupt Enable Clear */
+#define REG_SERCOM5_USART_INTENSET (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM5) USART Interrupt Enable Set */
+#define REG_SERCOM5_USART_INTFLAG (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM5_USART_STATUS (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM5) USART Status */
+#define REG_SERCOM5_USART_SYNCBUSY (*(RoReg *)0x4200181CU) /**< \brief (SERCOM5) USART Synchronization Busy */
+#define REG_SERCOM5_USART_RXERRCNT (*(RoReg8 *)0x42001820U) /**< \brief (SERCOM5) USART Receive Error Count */
+#define REG_SERCOM5_USART_DATA (*(RwReg16*)0x42001828U) /**< \brief (SERCOM5) USART Data */
+#define REG_SERCOM5_USART_DBGCTRL (*(RwReg8 *)0x42001830U) /**< \brief (SERCOM5) USART Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM5 peripheral ========== */
+#define SERCOM5_DMAC_ID_RX 12 // Index of DMA RX trigger
+#define SERCOM5_DMAC_ID_TX 13 // Index of DMA TX trigger
+#define SERCOM5_GCLK_ID_CORE 21
+#define SERCOM5_GCLK_ID_SLOW 15
+#define SERCOM5_INT_MSB 3
+#define SERCOM5_PMSB 3
+#define SERCOM5_SPI 1 // SPI mode implemented?
+#define SERCOM5_TWIM 1 // TWI Master mode implemented?
+#define SERCOM5_TWIS 1 // TWI Slave mode implemented?
+#define SERCOM5_TWI_HSMODE 1 // TWI HighSpeed mode implemented?
+#define SERCOM5_USART 1 // USART mode implemented?
+#define SERCOM5_USART_ISO7816 1 // USART ISO7816 mode implemented?
+#define SERCOM5_USART_LIN_MASTER 0 // USART LIN Master mode implemented?
+#define SERCOM5_USART_RS485 1 // USART RS485 mode implemented?
+
+#endif /* _SAML22_SERCOM5_INSTANCE_ */
diff --git a/Sensor Watch Starter Project/include/instance/slcd.h b/Sensor Watch Starter Project/include/instance/slcd.h new file mode 100755 index 00000000..6899f87b --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/slcd.h @@ -0,0 +1,140 @@ +/**
+ * \file
+ *
+ * \brief Instance description for SLCD
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAML22_SLCD_INSTANCE_
+#define _SAML22_SLCD_INSTANCE_
+
+/* ========== Register definition for SLCD peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SLCD_CTRLA (0x42003C00U) /**< \brief (SLCD) Control A */
+#define REG_SLCD_CTRLB (0x42003C04U) /**< \brief (SLCD) Control B */
+#define REG_SLCD_CTRLC (0x42003C06U) /**< \brief (SLCD) Control C */
+#define REG_SLCD_CTRLD (0x42003C08U) /**< \brief (SLCD) Control D */
+#define REG_SLCD_EVCTRL (0x42003C0CU) /**< \brief (SLCD) Event Control */
+#define REG_SLCD_INTENCLR (0x42003C0DU) /**< \brief (SLCD) Interrupt Enable Clear */
+#define REG_SLCD_INTENSET (0x42003C0EU) /**< \brief (SLCD) Interrupt Enable Set */
+#define REG_SLCD_INTFLAG (0x42003C0FU) /**< \brief (SLCD) Interrupt Flag Status and Clear */
+#define REG_SLCD_STATUS (0x42003C10U) /**< \brief (SLCD) Status */
+#define REG_SLCD_SYNCBUSY (0x42003C14U) /**< \brief (SLCD) Synchronization Busy */
+#define REG_SLCD_FC0 (0x42003C18U) /**< \brief (SLCD) Frame Counter 0 Configuration */
+#define REG_SLCD_FC1 (0x42003C19U) /**< \brief (SLCD) Frame Counter 1 Configuration */
+#define REG_SLCD_FC2 (0x42003C1AU) /**< \brief (SLCD) Frame Counter 2 Configuration */
+#define REG_SLCD_LPENL (0x42003C1CU) /**< \brief (SLCD) LCD Pin Enable Low */
+#define REG_SLCD_LPENH (0x42003C20U) /**< \brief (SLCD) LCD Pin Enable High */
+#define REG_SLCD_SDATAL0 (0x42003C24U) /**< \brief (SLCD) Segments Data Low for COM0 Line */
+#define REG_SLCD_SDATAH0 (0x42003C28U) /**< \brief (SLCD) Segments Data High for COM0 Line */
+#define REG_SLCD_SDATAL1 (0x42003C2CU) /**< \brief (SLCD) Segments Data Low for COM1 Line */
+#define REG_SLCD_SDATAH1 (0x42003C30U) /**< \brief (SLCD) Segments Data High for COM1 Line */
+#define REG_SLCD_SDATAL2 (0x42003C34U) /**< \brief (SLCD) Segments Data Low for COM2 Line */
+#define REG_SLCD_SDATAH2 (0x42003C38U) /**< \brief (SLCD) Segments Data High for COM2 Line */
+#define REG_SLCD_SDATAL3 (0x42003C3CU) /**< \brief (SLCD) Segments Data Low for COM3 Line */
+#define REG_SLCD_SDATAH3 (0x42003C40U) /**< \brief (SLCD) Segments Data High for COM3 Line */
+#define REG_SLCD_SDATAL4 (0x42003C44U) /**< \brief (SLCD) Segments Data Low for COM4 Line */
+#define REG_SLCD_SDATAH4 (0x42003C48U) /**< \brief (SLCD) Segments Data High for COM4 Line */
+#define REG_SLCD_SDATAL5 (0x42003C4CU) /**< \brief (SLCD) Segments Data Low for COM5 Line */
+#define REG_SLCD_SDATAH5 (0x42003C50U) /**< \brief (SLCD) Segments Data High for COM5 Line */
+#define REG_SLCD_SDATAL6 (0x42003C54U) /**< \brief (SLCD) Segments Data Low for COM6 Line */
+#define REG_SLCD_SDATAH6 (0x42003C58U) /**< \brief (SLCD) Segments Data High for COM6 Line */
+#define REG_SLCD_SDATAL7 (0x42003C5CU) /**< \brief (SLCD) Segments Data Low for COM7 Line */
+#define REG_SLCD_SDATAH7 (0x42003C60U) /**< \brief (SLCD) Segments Data High for COM7 Line */
+#define REG_SLCD_ISDATA (0x42003C64U) /**< \brief (SLCD) Indirect Segments Data Access */
+#define REG_SLCD_BCFG (0x42003C68U) /**< \brief (SLCD) Blink Configuration */
+#define REG_SLCD_CSRCFG (0x42003C6CU) /**< \brief (SLCD) Circular Shift Register Configuration */
+#define REG_SLCD_CMCFG (0x42003C70U) /**< \brief (SLCD) Character Mapping Configuration */
+#define REG_SLCD_ACMCFG (0x42003C74U) /**< \brief (SLCD) Automated Character Mapping Configuration */
+#define REG_SLCD_ABMCFG (0x42003C78U) /**< \brief (SLCD) Automated Bit Mapping Configuration */
+#define REG_SLCD_CMDATA (0x42003C7CU) /**< \brief (SLCD) Character Mapping Segments Data */
+#define REG_SLCD_CMDMASK (0x42003C80U) /**< \brief (SLCD) Character Mapping Segments Data Mask */
+#define REG_SLCD_CMINDEX (0x42003C84U) /**< \brief (SLCD) Character Mapping SEG/COM Index */
+#else
+#define REG_SLCD_CTRLA (*(RwReg *)0x42003C00U) /**< \brief (SLCD) Control A */
+#define REG_SLCD_CTRLB (*(RwReg16*)0x42003C04U) /**< \brief (SLCD) Control B */
+#define REG_SLCD_CTRLC (*(RwReg16*)0x42003C06U) /**< \brief (SLCD) Control C */
+#define REG_SLCD_CTRLD (*(RwReg8 *)0x42003C08U) /**< \brief (SLCD) Control D */
+#define REG_SLCD_EVCTRL (*(RwReg8 *)0x42003C0CU) /**< \brief (SLCD) Event Control */
+#define REG_SLCD_INTENCLR (*(RwReg8 *)0x42003C0DU) /**< \brief (SLCD) Interrupt Enable Clear */
+#define REG_SLCD_INTENSET (*(RwReg8 *)0x42003C0EU) /**< \brief (SLCD) Interrupt Enable Set */
+#define REG_SLCD_INTFLAG (*(RwReg8 *)0x42003C0FU) /**< \brief (SLCD) Interrupt Flag Status and Clear */
+#define REG_SLCD_STATUS (*(RoReg8 *)0x42003C10U) /**< \brief (SLCD) Status */
+#define REG_SLCD_SYNCBUSY (*(RoReg *)0x42003C14U) /**< \brief (SLCD) Synchronization Busy */
+#define REG_SLCD_FC0 (*(RwReg8 *)0x42003C18U) /**< \brief (SLCD) Frame Counter 0 Configuration */
+#define REG_SLCD_FC1 (*(RwReg8 *)0x42003C19U) /**< \brief (SLCD) Frame Counter 1 Configuration */
+#define REG_SLCD_FC2 (*(RwReg8 *)0x42003C1AU) /**< \brief (SLCD) Frame Counter 2 Configuration */
+#define REG_SLCD_LPENL (*(RwReg *)0x42003C1CU) /**< \brief (SLCD) LCD Pin Enable Low */
+#define REG_SLCD_LPENH (*(RwReg *)0x42003C20U) /**< \brief (SLCD) LCD Pin Enable High */
+#define REG_SLCD_SDATAL0 (*(RwReg *)0x42003C24U) /**< \brief (SLCD) Segments Data Low for COM0 Line */
+#define REG_SLCD_SDATAH0 (*(RwReg *)0x42003C28U) /**< \brief (SLCD) Segments Data High for COM0 Line */
+#define REG_SLCD_SDATAL1 (*(RwReg *)0x42003C2CU) /**< \brief (SLCD) Segments Data Low for COM1 Line */
+#define REG_SLCD_SDATAH1 (*(RwReg *)0x42003C30U) /**< \brief (SLCD) Segments Data High for COM1 Line */
+#define REG_SLCD_SDATAL2 (*(RwReg *)0x42003C34U) /**< \brief (SLCD) Segments Data Low for COM2 Line */
+#define REG_SLCD_SDATAH2 (*(RwReg *)0x42003C38U) /**< \brief (SLCD) Segments Data High for COM2 Line */
+#define REG_SLCD_SDATAL3 (*(RwReg *)0x42003C3CU) /**< \brief (SLCD) Segments Data Low for COM3 Line */
+#define REG_SLCD_SDATAH3 (*(RwReg *)0x42003C40U) /**< \brief (SLCD) Segments Data High for COM3 Line */
+#define REG_SLCD_SDATAL4 (*(RwReg *)0x42003C44U) /**< \brief (SLCD) Segments Data Low for COM4 Line */
+#define REG_SLCD_SDATAH4 (*(RwReg *)0x42003C48U) /**< \brief (SLCD) Segments Data High for COM4 Line */
+#define REG_SLCD_SDATAL5 (*(RwReg *)0x42003C4CU) /**< \brief (SLCD) Segments Data Low for COM5 Line */
+#define REG_SLCD_SDATAH5 (*(RwReg *)0x42003C50U) /**< \brief (SLCD) Segments Data High for COM5 Line */
+#define REG_SLCD_SDATAL6 (*(RwReg *)0x42003C54U) /**< \brief (SLCD) Segments Data Low for COM6 Line */
+#define REG_SLCD_SDATAH6 (*(RwReg *)0x42003C58U) /**< \brief (SLCD) Segments Data High for COM6 Line */
+#define REG_SLCD_SDATAL7 (*(RwReg *)0x42003C5CU) /**< \brief (SLCD) Segments Data Low for COM7 Line */
+#define REG_SLCD_SDATAH7 (*(RwReg *)0x42003C60U) /**< \brief (SLCD) Segments Data High for COM7 Line */
+#define REG_SLCD_ISDATA (*(WoReg *)0x42003C64U) /**< \brief (SLCD) Indirect Segments Data Access */
+#define REG_SLCD_BCFG (*(RwReg *)0x42003C68U) /**< \brief (SLCD) Blink Configuration */
+#define REG_SLCD_CSRCFG (*(RwReg *)0x42003C6CU) /**< \brief (SLCD) Circular Shift Register Configuration */
+#define REG_SLCD_CMCFG (*(RwReg8 *)0x42003C70U) /**< \brief (SLCD) Character Mapping Configuration */
+#define REG_SLCD_ACMCFG (*(RwReg *)0x42003C74U) /**< \brief (SLCD) Automated Character Mapping Configuration */
+#define REG_SLCD_ABMCFG (*(RwReg8 *)0x42003C78U) /**< \brief (SLCD) Automated Bit Mapping Configuration */
+#define REG_SLCD_CMDATA (*(WoReg *)0x42003C7CU) /**< \brief (SLCD) Character Mapping Segments Data */
+#define REG_SLCD_CMDMASK (*(RwReg *)0x42003C80U) /**< \brief (SLCD) Character Mapping Segments Data Mask */
+#define REG_SLCD_CMINDEX (*(RwReg16*)0x42003C84U) /**< \brief (SLCD) Character Mapping SEG/COM Index */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SLCD peripheral ========== */
+#define SLCD_DMAC_ID_ABMDRDY 34
+#define SLCD_DMAC_ID_ACMDRDY 33
+#define SLCD_DMAC_ID_DMU 32
+#define SLCD_MAX_COM 8 // Max number of COM lines (4 or 8)
+#define SLCD_MAX_SEG 44 // Max number of SEG lines (24 or 44)
+#define SLCD_NB_LP 52 // Number of LCD pins ([28..64] or [48..64])
+
+#endif /* _SAML22_SLCD_INSTANCE_ */
diff --git a/Sensor Watch Starter Project/include/instance/supc.h b/Sensor Watch Starter Project/include/instance/supc.h new file mode 100755 index 00000000..b148c204 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/supc.h @@ -0,0 +1,79 @@ +/**
+ * \file
+ *
+ * \brief Instance description for SUPC
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAML22_SUPC_INSTANCE_
+#define _SAML22_SUPC_INSTANCE_
+
+/* ========== Register definition for SUPC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SUPC_INTENCLR (0x40001800U) /**< \brief (SUPC) Interrupt Enable Clear */
+#define REG_SUPC_INTENSET (0x40001804U) /**< \brief (SUPC) Interrupt Enable Set */
+#define REG_SUPC_INTFLAG (0x40001808U) /**< \brief (SUPC) Interrupt Flag Status and Clear */
+#define REG_SUPC_STATUS (0x4000180CU) /**< \brief (SUPC) Power and Clocks Status */
+#define REG_SUPC_BOD33 (0x40001810U) /**< \brief (SUPC) BOD33 Control */
+#define REG_SUPC_BOD12 (0x40001814U) /**< \brief (SUPC) BOD12 Control */
+#define REG_SUPC_VREG (0x40001818U) /**< \brief (SUPC) VREG Control */
+#define REG_SUPC_VREF (0x4000181CU) /**< \brief (SUPC) VREF Control */
+#define REG_SUPC_BBPS (0x40001820U) /**< \brief (SUPC) Battery Backup Power Switch */
+#define REG_SUPC_BKOUT (0x40001824U) /**< \brief (SUPC) Backup Output Control */
+#define REG_SUPC_BKIN (0x40001828U) /**< \brief (SUPC) Backup Input Control */
+#else
+#define REG_SUPC_INTENCLR (*(RwReg *)0x40001800U) /**< \brief (SUPC) Interrupt Enable Clear */
+#define REG_SUPC_INTENSET (*(RwReg *)0x40001804U) /**< \brief (SUPC) Interrupt Enable Set */
+#define REG_SUPC_INTFLAG (*(RwReg *)0x40001808U) /**< \brief (SUPC) Interrupt Flag Status and Clear */
+#define REG_SUPC_STATUS (*(RoReg *)0x4000180CU) /**< \brief (SUPC) Power and Clocks Status */
+#define REG_SUPC_BOD33 (*(RwReg *)0x40001810U) /**< \brief (SUPC) BOD33 Control */
+#define REG_SUPC_BOD12 (*(RwReg *)0x40001814U) /**< \brief (SUPC) BOD12 Control */
+#define REG_SUPC_VREG (*(RwReg *)0x40001818U) /**< \brief (SUPC) VREG Control */
+#define REG_SUPC_VREF (*(RwReg *)0x4000181CU) /**< \brief (SUPC) VREF Control */
+#define REG_SUPC_BBPS (*(RwReg *)0x40001820U) /**< \brief (SUPC) Battery Backup Power Switch */
+#define REG_SUPC_BKOUT (*(RwReg *)0x40001824U) /**< \brief (SUPC) Backup Output Control */
+#define REG_SUPC_BKIN (*(RoReg *)0x40001828U) /**< \brief (SUPC) Backup Input Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SUPC peripheral ========== */
+#define SUPC_BOD12_CALIB_MSB 5
+#define SUPC_BOD33_CALIB_MSB 5
+#define SUPC_OUT_NUM_MSB 1 // MSB of backup output pad Number
+
+#endif /* _SAML22_SUPC_INSTANCE_ */
diff --git a/Sensor Watch Starter Project/include/instance/tal.h b/Sensor Watch Starter Project/include/instance/tal.h new file mode 100755 index 00000000..994abf90 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/tal.h @@ -0,0 +1,160 @@ +/**
+ * \file
+ *
+ * \brief Instance description for TAL
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAML22_TAL_INSTANCE_
+#define _SAML22_TAL_INSTANCE_
+
+/* ========== Register definition for TAL peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TAL_CTRLA (0x40003000U) /**< \brief (TAL) Control A */
+#define REG_TAL_RSTCTRL (0x40003004U) /**< \brief (TAL) Reset Control */
+#define REG_TAL_EXTCTRL (0x40003005U) /**< \brief (TAL) External Break Control */
+#define REG_TAL_EVCTRL (0x40003006U) /**< \brief (TAL) Event Control */
+#define REG_TAL_INTENCLR (0x40003008U) /**< \brief (TAL) Interrupt Enable Clear */
+#define REG_TAL_INTENSET (0x40003009U) /**< \brief (TAL) Interrupt Enable Set */
+#define REG_TAL_INTFLAG (0x4000300AU) /**< \brief (TAL) Interrupt Flag Status and Clear */
+#define REG_TAL_GLOBMASK (0x4000300BU) /**< \brief (TAL) Global Break Requests Mask */
+#define REG_TAL_HALT (0x4000300CU) /**< \brief (TAL) Debug Halt Request */
+#define REG_TAL_RESTART (0x4000300DU) /**< \brief (TAL) Debug Restart Request */
+#define REG_TAL_BRKSTATUS (0x4000300EU) /**< \brief (TAL) Break Request Status */
+#define REG_TAL_CTICTRLA0 (0x40003010U) /**< \brief (TAL) Cross-Trigger Interface 0 Control A */
+#define REG_TAL_CTIMASK0 (0x40003011U) /**< \brief (TAL) Cross-Trigger Interface 0 Mask */
+#define REG_TAL_CTICTRLA1 (0x40003012U) /**< \brief (TAL) Cross-Trigger Interface 1 Control A */
+#define REG_TAL_CTIMASK1 (0x40003013U) /**< \brief (TAL) Cross-Trigger Interface 1 Mask */
+#define REG_TAL_CTICTRLA2 (0x40003014U) /**< \brief (TAL) Cross-Trigger Interface 2 Control A */
+#define REG_TAL_CTIMASK2 (0x40003015U) /**< \brief (TAL) Cross-Trigger Interface 2 Mask */
+#define REG_TAL_INTSTATUS0 (0x40003020U) /**< \brief (TAL) Interrupt 0 Status */
+#define REG_TAL_INTSTATUS1 (0x40003021U) /**< \brief (TAL) Interrupt 1 Status */
+#define REG_TAL_INTSTATUS2 (0x40003022U) /**< \brief (TAL) Interrupt 2 Status */
+#define REG_TAL_INTSTATUS3 (0x40003023U) /**< \brief (TAL) Interrupt 3 Status */
+#define REG_TAL_INTSTATUS4 (0x40003024U) /**< \brief (TAL) Interrupt 4 Status */
+#define REG_TAL_INTSTATUS5 (0x40003025U) /**< \brief (TAL) Interrupt 5 Status */
+#define REG_TAL_INTSTATUS6 (0x40003026U) /**< \brief (TAL) Interrupt 6 Status */
+#define REG_TAL_INTSTATUS7 (0x40003027U) /**< \brief (TAL) Interrupt 7 Status */
+#define REG_TAL_INTSTATUS8 (0x40003028U) /**< \brief (TAL) Interrupt 8 Status */
+#define REG_TAL_INTSTATUS9 (0x40003029U) /**< \brief (TAL) Interrupt 9 Status */
+#define REG_TAL_INTSTATUS10 (0x4000302AU) /**< \brief (TAL) Interrupt 10 Status */
+#define REG_TAL_INTSTATUS11 (0x4000302BU) /**< \brief (TAL) Interrupt 11 Status */
+#define REG_TAL_INTSTATUS12 (0x4000302CU) /**< \brief (TAL) Interrupt 12 Status */
+#define REG_TAL_INTSTATUS13 (0x4000302DU) /**< \brief (TAL) Interrupt 13 Status */
+#define REG_TAL_INTSTATUS14 (0x4000302EU) /**< \brief (TAL) Interrupt 14 Status */
+#define REG_TAL_INTSTATUS15 (0x4000302FU) /**< \brief (TAL) Interrupt 15 Status */
+#define REG_TAL_INTSTATUS16 (0x40003030U) /**< \brief (TAL) Interrupt 16 Status */
+#define REG_TAL_INTSTATUS17 (0x40003031U) /**< \brief (TAL) Interrupt 17 Status */
+#define REG_TAL_INTSTATUS18 (0x40003032U) /**< \brief (TAL) Interrupt 18 Status */
+#define REG_TAL_INTSTATUS19 (0x40003033U) /**< \brief (TAL) Interrupt 19 Status */
+#define REG_TAL_INTSTATUS20 (0x40003034U) /**< \brief (TAL) Interrupt 20 Status */
+#define REG_TAL_INTSTATUS21 (0x40003035U) /**< \brief (TAL) Interrupt 21 Status */
+#define REG_TAL_INTSTATUS22 (0x40003036U) /**< \brief (TAL) Interrupt 22 Status */
+#define REG_TAL_INTSTATUS23 (0x40003037U) /**< \brief (TAL) Interrupt 23 Status */
+#define REG_TAL_INTSTATUS24 (0x40003038U) /**< \brief (TAL) Interrupt 24 Status */
+#define REG_TAL_INTSTATUS25 (0x40003039U) /**< \brief (TAL) Interrupt 25 Status */
+#define REG_TAL_DMACPUSEL0 (0x40003040U) /**< \brief (TAL) DMA Channel Interrupts CPU Select 0 */
+#define REG_TAL_EVCPUSEL0 (0x40003048U) /**< \brief (TAL) EVSYS Channel Interrupts CPU Select 0 */
+#define REG_TAL_EICCPUSEL0 (0x40003050U) /**< \brief (TAL) EIC External Interrupts CPU Select 0 */
+#define REG_TAL_INTCPUSEL0 (0x40003058U) /**< \brief (TAL) Interrupts CPU Select 0 */
+#define REG_TAL_INTCPUSEL1 (0x4000305CU) /**< \brief (TAL) Interrupts CPU Select 1 */
+#define REG_TAL_IRQTRIG (0x40003060U) /**< \brief (TAL) Interrupt Trigger */
+#define REG_TAL_CPUIRQS0 (0x40003064U) /**< \brief (TAL) Interrupt Status for CPU 0 */
+#else
+#define REG_TAL_CTRLA (*(RwReg8 *)0x40003000U) /**< \brief (TAL) Control A */
+#define REG_TAL_RSTCTRL (*(RwReg8 *)0x40003004U) /**< \brief (TAL) Reset Control */
+#define REG_TAL_EXTCTRL (*(RwReg8 *)0x40003005U) /**< \brief (TAL) External Break Control */
+#define REG_TAL_EVCTRL (*(RwReg8 *)0x40003006U) /**< \brief (TAL) Event Control */
+#define REG_TAL_INTENCLR (*(RwReg8 *)0x40003008U) /**< \brief (TAL) Interrupt Enable Clear */
+#define REG_TAL_INTENSET (*(RwReg8 *)0x40003009U) /**< \brief (TAL) Interrupt Enable Set */
+#define REG_TAL_INTFLAG (*(RwReg8 *)0x4000300AU) /**< \brief (TAL) Interrupt Flag Status and Clear */
+#define REG_TAL_GLOBMASK (*(RwReg8 *)0x4000300BU) /**< \brief (TAL) Global Break Requests Mask */
+#define REG_TAL_HALT (*(WoReg8 *)0x4000300CU) /**< \brief (TAL) Debug Halt Request */
+#define REG_TAL_RESTART (*(WoReg8 *)0x4000300DU) /**< \brief (TAL) Debug Restart Request */
+#define REG_TAL_BRKSTATUS (*(RoReg16*)0x4000300EU) /**< \brief (TAL) Break Request Status */
+#define REG_TAL_CTICTRLA0 (*(RwReg8 *)0x40003010U) /**< \brief (TAL) Cross-Trigger Interface 0 Control A */
+#define REG_TAL_CTIMASK0 (*(RwReg8 *)0x40003011U) /**< \brief (TAL) Cross-Trigger Interface 0 Mask */
+#define REG_TAL_CTICTRLA1 (*(RwReg8 *)0x40003012U) /**< \brief (TAL) Cross-Trigger Interface 1 Control A */
+#define REG_TAL_CTIMASK1 (*(RwReg8 *)0x40003013U) /**< \brief (TAL) Cross-Trigger Interface 1 Mask */
+#define REG_TAL_CTICTRLA2 (*(RwReg8 *)0x40003014U) /**< \brief (TAL) Cross-Trigger Interface 2 Control A */
+#define REG_TAL_CTIMASK2 (*(RwReg8 *)0x40003015U) /**< \brief (TAL) Cross-Trigger Interface 2 Mask */
+#define REG_TAL_INTSTATUS0 (*(RoReg8 *)0x40003020U) /**< \brief (TAL) Interrupt 0 Status */
+#define REG_TAL_INTSTATUS1 (*(RoReg8 *)0x40003021U) /**< \brief (TAL) Interrupt 1 Status */
+#define REG_TAL_INTSTATUS2 (*(RoReg8 *)0x40003022U) /**< \brief (TAL) Interrupt 2 Status */
+#define REG_TAL_INTSTATUS3 (*(RoReg8 *)0x40003023U) /**< \brief (TAL) Interrupt 3 Status */
+#define REG_TAL_INTSTATUS4 (*(RoReg8 *)0x40003024U) /**< \brief (TAL) Interrupt 4 Status */
+#define REG_TAL_INTSTATUS5 (*(RoReg8 *)0x40003025U) /**< \brief (TAL) Interrupt 5 Status */
+#define REG_TAL_INTSTATUS6 (*(RoReg8 *)0x40003026U) /**< \brief (TAL) Interrupt 6 Status */
+#define REG_TAL_INTSTATUS7 (*(RoReg8 *)0x40003027U) /**< \brief (TAL) Interrupt 7 Status */
+#define REG_TAL_INTSTATUS8 (*(RoReg8 *)0x40003028U) /**< \brief (TAL) Interrupt 8 Status */
+#define REG_TAL_INTSTATUS9 (*(RoReg8 *)0x40003029U) /**< \brief (TAL) Interrupt 9 Status */
+#define REG_TAL_INTSTATUS10 (*(RoReg8 *)0x4000302AU) /**< \brief (TAL) Interrupt 10 Status */
+#define REG_TAL_INTSTATUS11 (*(RoReg8 *)0x4000302BU) /**< \brief (TAL) Interrupt 11 Status */
+#define REG_TAL_INTSTATUS12 (*(RoReg8 *)0x4000302CU) /**< \brief (TAL) Interrupt 12 Status */
+#define REG_TAL_INTSTATUS13 (*(RoReg8 *)0x4000302DU) /**< \brief (TAL) Interrupt 13 Status */
+#define REG_TAL_INTSTATUS14 (*(RoReg8 *)0x4000302EU) /**< \brief (TAL) Interrupt 14 Status */
+#define REG_TAL_INTSTATUS15 (*(RoReg8 *)0x4000302FU) /**< \brief (TAL) Interrupt 15 Status */
+#define REG_TAL_INTSTATUS16 (*(RoReg8 *)0x40003030U) /**< \brief (TAL) Interrupt 16 Status */
+#define REG_TAL_INTSTATUS17 (*(RoReg8 *)0x40003031U) /**< \brief (TAL) Interrupt 17 Status */
+#define REG_TAL_INTSTATUS18 (*(RoReg8 *)0x40003032U) /**< \brief (TAL) Interrupt 18 Status */
+#define REG_TAL_INTSTATUS19 (*(RoReg8 *)0x40003033U) /**< \brief (TAL) Interrupt 19 Status */
+#define REG_TAL_INTSTATUS20 (*(RoReg8 *)0x40003034U) /**< \brief (TAL) Interrupt 20 Status */
+#define REG_TAL_INTSTATUS21 (*(RoReg8 *)0x40003035U) /**< \brief (TAL) Interrupt 21 Status */
+#define REG_TAL_INTSTATUS22 (*(RoReg8 *)0x40003036U) /**< \brief (TAL) Interrupt 22 Status */
+#define REG_TAL_INTSTATUS23 (*(RoReg8 *)0x40003037U) /**< \brief (TAL) Interrupt 23 Status */
+#define REG_TAL_INTSTATUS24 (*(RoReg8 *)0x40003038U) /**< \brief (TAL) Interrupt 24 Status */
+#define REG_TAL_INTSTATUS25 (*(RoReg8 *)0x40003039U) /**< \brief (TAL) Interrupt 25 Status */
+#define REG_TAL_DMACPUSEL0 (*(RwReg *)0x40003040U) /**< \brief (TAL) DMA Channel Interrupts CPU Select 0 */
+#define REG_TAL_EVCPUSEL0 (*(RwReg *)0x40003048U) /**< \brief (TAL) EVSYS Channel Interrupts CPU Select 0 */
+#define REG_TAL_EICCPUSEL0 (*(RwReg *)0x40003050U) /**< \brief (TAL) EIC External Interrupts CPU Select 0 */
+#define REG_TAL_INTCPUSEL0 (*(RwReg *)0x40003058U) /**< \brief (TAL) Interrupts CPU Select 0 */
+#define REG_TAL_INTCPUSEL1 (*(RwReg *)0x4000305CU) /**< \brief (TAL) Interrupts CPU Select 1 */
+#define REG_TAL_IRQTRIG (*(RwReg16*)0x40003060U) /**< \brief (TAL) Interrupt Trigger */
+#define REG_TAL_CPUIRQS0 (*(RoReg *)0x40003064U) /**< \brief (TAL) Interrupt Status for CPU 0 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TAL peripheral ========== */
+#define TAL_CPU_NUM 1 // Number of CPUs
+#define TAL_CTI_NUM 3 // Number of Cross-Trigger Interfaces
+#define TAL_DMA_CH_NUM 16 // Number of DMAC Channels
+#define TAL_EV_CH_NUM 8 // Number of EVSYS Channels
+#define TAL_EXTINT_NUM 16 // Number of EIC External Interrrupts
+#define TAL_INT_NUM 26 // Number of Interrupt Requests
+
+#endif /* _SAML22_TAL_INSTANCE_ */
diff --git a/Sensor Watch Starter Project/include/instance/tc0.h b/Sensor Watch Starter Project/include/instance/tc0.h new file mode 100755 index 00000000..231bbea9 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/tc0.h @@ -0,0 +1,123 @@ +/**
+ * \file
+ *
+ * \brief Instance description for TC0
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAML22_TC0_INSTANCE_
+#define _SAML22_TC0_INSTANCE_
+
+/* ========== Register definition for TC0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC0_CTRLA (0x42002000U) /**< \brief (TC0) Control A */
+#define REG_TC0_CTRLBCLR (0x42002004U) /**< \brief (TC0) Control B Clear */
+#define REG_TC0_CTRLBSET (0x42002005U) /**< \brief (TC0) Control B Set */
+#define REG_TC0_EVCTRL (0x42002006U) /**< \brief (TC0) Event Control */
+#define REG_TC0_INTENCLR (0x42002008U) /**< \brief (TC0) Interrupt Enable Clear */
+#define REG_TC0_INTENSET (0x42002009U) /**< \brief (TC0) Interrupt Enable Set */
+#define REG_TC0_INTFLAG (0x4200200AU) /**< \brief (TC0) Interrupt Flag Status and Clear */
+#define REG_TC0_STATUS (0x4200200BU) /**< \brief (TC0) Status */
+#define REG_TC0_WAVE (0x4200200CU) /**< \brief (TC0) Waveform Generation Control */
+#define REG_TC0_DRVCTRL (0x4200200DU) /**< \brief (TC0) Control C */
+#define REG_TC0_DBGCTRL (0x4200200FU) /**< \brief (TC0) Debug Control */
+#define REG_TC0_SYNCBUSY (0x42002010U) /**< \brief (TC0) Synchronization Status */
+#define REG_TC0_COUNT16_COUNT (0x42002014U) /**< \brief (TC0) COUNT16 Count */
+#define REG_TC0_COUNT16_CC0 (0x4200201CU) /**< \brief (TC0) COUNT16 Compare and Capture 0 */
+#define REG_TC0_COUNT16_CC1 (0x4200201EU) /**< \brief (TC0) COUNT16 Compare and Capture 1 */
+#define REG_TC0_COUNT16_CCBUF0 (0x42002030U) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 0 */
+#define REG_TC0_COUNT16_CCBUF1 (0x42002032U) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 1 */
+#define REG_TC0_COUNT32_COUNT (0x42002014U) /**< \brief (TC0) COUNT32 Count */
+#define REG_TC0_COUNT32_CC0 (0x4200201CU) /**< \brief (TC0) COUNT32 Compare and Capture 0 */
+#define REG_TC0_COUNT32_CC1 (0x42002020U) /**< \brief (TC0) COUNT32 Compare and Capture 1 */
+#define REG_TC0_COUNT32_CCBUF0 (0x42002030U) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 0 */
+#define REG_TC0_COUNT32_CCBUF1 (0x42002034U) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 1 */
+#define REG_TC0_COUNT8_COUNT (0x42002014U) /**< \brief (TC0) COUNT8 Count */
+#define REG_TC0_COUNT8_PER (0x4200201BU) /**< \brief (TC0) COUNT8 Period */
+#define REG_TC0_COUNT8_CC0 (0x4200201CU) /**< \brief (TC0) COUNT8 Compare and Capture 0 */
+#define REG_TC0_COUNT8_CC1 (0x4200201DU) /**< \brief (TC0) COUNT8 Compare and Capture 1 */
+#define REG_TC0_COUNT8_PERBUF (0x4200202FU) /**< \brief (TC0) COUNT8 Period Buffer */
+#define REG_TC0_COUNT8_CCBUF0 (0x42002030U) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 0 */
+#define REG_TC0_COUNT8_CCBUF1 (0x42002031U) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 1 */
+#else
+#define REG_TC0_CTRLA (*(RwReg *)0x42002000U) /**< \brief (TC0) Control A */
+#define REG_TC0_CTRLBCLR (*(RwReg8 *)0x42002004U) /**< \brief (TC0) Control B Clear */
+#define REG_TC0_CTRLBSET (*(RwReg8 *)0x42002005U) /**< \brief (TC0) Control B Set */
+#define REG_TC0_EVCTRL (*(RwReg16*)0x42002006U) /**< \brief (TC0) Event Control */
+#define REG_TC0_INTENCLR (*(RwReg8 *)0x42002008U) /**< \brief (TC0) Interrupt Enable Clear */
+#define REG_TC0_INTENSET (*(RwReg8 *)0x42002009U) /**< \brief (TC0) Interrupt Enable Set */
+#define REG_TC0_INTFLAG (*(RwReg8 *)0x4200200AU) /**< \brief (TC0) Interrupt Flag Status and Clear */
+#define REG_TC0_STATUS (*(RwReg8 *)0x4200200BU) /**< \brief (TC0) Status */
+#define REG_TC0_WAVE (*(RwReg8 *)0x4200200CU) /**< \brief (TC0) Waveform Generation Control */
+#define REG_TC0_DRVCTRL (*(RwReg8 *)0x4200200DU) /**< \brief (TC0) Control C */
+#define REG_TC0_DBGCTRL (*(RwReg8 *)0x4200200FU) /**< \brief (TC0) Debug Control */
+#define REG_TC0_SYNCBUSY (*(RoReg *)0x42002010U) /**< \brief (TC0) Synchronization Status */
+#define REG_TC0_COUNT16_COUNT (*(RwReg16*)0x42002014U) /**< \brief (TC0) COUNT16 Count */
+#define REG_TC0_COUNT16_CC0 (*(RwReg16*)0x4200201CU) /**< \brief (TC0) COUNT16 Compare and Capture 0 */
+#define REG_TC0_COUNT16_CC1 (*(RwReg16*)0x4200201EU) /**< \brief (TC0) COUNT16 Compare and Capture 1 */
+#define REG_TC0_COUNT16_CCBUF0 (*(RwReg16*)0x42002030U) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 0 */
+#define REG_TC0_COUNT16_CCBUF1 (*(RwReg16*)0x42002032U) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 1 */
+#define REG_TC0_COUNT32_COUNT (*(RwReg *)0x42002014U) /**< \brief (TC0) COUNT32 Count */
+#define REG_TC0_COUNT32_CC0 (*(RwReg *)0x4200201CU) /**< \brief (TC0) COUNT32 Compare and Capture 0 */
+#define REG_TC0_COUNT32_CC1 (*(RwReg *)0x42002020U) /**< \brief (TC0) COUNT32 Compare and Capture 1 */
+#define REG_TC0_COUNT32_CCBUF0 (*(RwReg *)0x42002030U) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 0 */
+#define REG_TC0_COUNT32_CCBUF1 (*(RwReg *)0x42002034U) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 1 */
+#define REG_TC0_COUNT8_COUNT (*(RwReg8 *)0x42002014U) /**< \brief (TC0) COUNT8 Count */
+#define REG_TC0_COUNT8_PER (*(RwReg8 *)0x4200201BU) /**< \brief (TC0) COUNT8 Period */
+#define REG_TC0_COUNT8_CC0 (*(RwReg8 *)0x4200201CU) /**< \brief (TC0) COUNT8 Compare and Capture 0 */
+#define REG_TC0_COUNT8_CC1 (*(RwReg8 *)0x4200201DU) /**< \brief (TC0) COUNT8 Compare and Capture 1 */
+#define REG_TC0_COUNT8_PERBUF (*(RwReg8 *)0x4200202FU) /**< \brief (TC0) COUNT8 Period Buffer */
+#define REG_TC0_COUNT8_CCBUF0 (*(RwReg8 *)0x42002030U) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 0 */
+#define REG_TC0_COUNT8_CCBUF1 (*(RwReg8 *)0x42002031U) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TC0 peripheral ========== */
+#define TC0_CC_NUM 2
+#define TC0_DMAC_ID_MC_0 20
+#define TC0_DMAC_ID_MC_1 21
+#define TC0_DMAC_ID_MC_LSB 20
+#define TC0_DMAC_ID_MC_MSB 21
+#define TC0_DMAC_ID_MC_SIZE 2
+#define TC0_DMAC_ID_OVF 19 // Indexes of DMA Overflow trigger
+#define TC0_EXT 0
+#define TC0_GCLK_ID 23
+#define TC0_MASTER 1
+#define TC0_OW_NUM 2
+
+#endif /* _SAML22_TC0_INSTANCE_ */
diff --git a/Sensor Watch Starter Project/include/instance/tc1.h b/Sensor Watch Starter Project/include/instance/tc1.h new file mode 100755 index 00000000..fc76b275 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/tc1.h @@ -0,0 +1,123 @@ +/**
+ * \file
+ *
+ * \brief Instance description for TC1
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAML22_TC1_INSTANCE_
+#define _SAML22_TC1_INSTANCE_
+
+/* ========== Register definition for TC1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC1_CTRLA (0x42002400U) /**< \brief (TC1) Control A */
+#define REG_TC1_CTRLBCLR (0x42002404U) /**< \brief (TC1) Control B Clear */
+#define REG_TC1_CTRLBSET (0x42002405U) /**< \brief (TC1) Control B Set */
+#define REG_TC1_EVCTRL (0x42002406U) /**< \brief (TC1) Event Control */
+#define REG_TC1_INTENCLR (0x42002408U) /**< \brief (TC1) Interrupt Enable Clear */
+#define REG_TC1_INTENSET (0x42002409U) /**< \brief (TC1) Interrupt Enable Set */
+#define REG_TC1_INTFLAG (0x4200240AU) /**< \brief (TC1) Interrupt Flag Status and Clear */
+#define REG_TC1_STATUS (0x4200240BU) /**< \brief (TC1) Status */
+#define REG_TC1_WAVE (0x4200240CU) /**< \brief (TC1) Waveform Generation Control */
+#define REG_TC1_DRVCTRL (0x4200240DU) /**< \brief (TC1) Control C */
+#define REG_TC1_DBGCTRL (0x4200240FU) /**< \brief (TC1) Debug Control */
+#define REG_TC1_SYNCBUSY (0x42002410U) /**< \brief (TC1) Synchronization Status */
+#define REG_TC1_COUNT16_COUNT (0x42002414U) /**< \brief (TC1) COUNT16 Count */
+#define REG_TC1_COUNT16_CC0 (0x4200241CU) /**< \brief (TC1) COUNT16 Compare and Capture 0 */
+#define REG_TC1_COUNT16_CC1 (0x4200241EU) /**< \brief (TC1) COUNT16 Compare and Capture 1 */
+#define REG_TC1_COUNT16_CCBUF0 (0x42002430U) /**< \brief (TC1) COUNT16 Compare and Capture Buffer 0 */
+#define REG_TC1_COUNT16_CCBUF1 (0x42002432U) /**< \brief (TC1) COUNT16 Compare and Capture Buffer 1 */
+#define REG_TC1_COUNT32_COUNT (0x42002414U) /**< \brief (TC1) COUNT32 Count */
+#define REG_TC1_COUNT32_CC0 (0x4200241CU) /**< \brief (TC1) COUNT32 Compare and Capture 0 */
+#define REG_TC1_COUNT32_CC1 (0x42002420U) /**< \brief (TC1) COUNT32 Compare and Capture 1 */
+#define REG_TC1_COUNT32_CCBUF0 (0x42002430U) /**< \brief (TC1) COUNT32 Compare and Capture Buffer 0 */
+#define REG_TC1_COUNT32_CCBUF1 (0x42002434U) /**< \brief (TC1) COUNT32 Compare and Capture Buffer 1 */
+#define REG_TC1_COUNT8_COUNT (0x42002414U) /**< \brief (TC1) COUNT8 Count */
+#define REG_TC1_COUNT8_PER (0x4200241BU) /**< \brief (TC1) COUNT8 Period */
+#define REG_TC1_COUNT8_CC0 (0x4200241CU) /**< \brief (TC1) COUNT8 Compare and Capture 0 */
+#define REG_TC1_COUNT8_CC1 (0x4200241DU) /**< \brief (TC1) COUNT8 Compare and Capture 1 */
+#define REG_TC1_COUNT8_PERBUF (0x4200242FU) /**< \brief (TC1) COUNT8 Period Buffer */
+#define REG_TC1_COUNT8_CCBUF0 (0x42002430U) /**< \brief (TC1) COUNT8 Compare and Capture Buffer 0 */
+#define REG_TC1_COUNT8_CCBUF1 (0x42002431U) /**< \brief (TC1) COUNT8 Compare and Capture Buffer 1 */
+#else
+#define REG_TC1_CTRLA (*(RwReg *)0x42002400U) /**< \brief (TC1) Control A */
+#define REG_TC1_CTRLBCLR (*(RwReg8 *)0x42002404U) /**< \brief (TC1) Control B Clear */
+#define REG_TC1_CTRLBSET (*(RwReg8 *)0x42002405U) /**< \brief (TC1) Control B Set */
+#define REG_TC1_EVCTRL (*(RwReg16*)0x42002406U) /**< \brief (TC1) Event Control */
+#define REG_TC1_INTENCLR (*(RwReg8 *)0x42002408U) /**< \brief (TC1) Interrupt Enable Clear */
+#define REG_TC1_INTENSET (*(RwReg8 *)0x42002409U) /**< \brief (TC1) Interrupt Enable Set */
+#define REG_TC1_INTFLAG (*(RwReg8 *)0x4200240AU) /**< \brief (TC1) Interrupt Flag Status and Clear */
+#define REG_TC1_STATUS (*(RwReg8 *)0x4200240BU) /**< \brief (TC1) Status */
+#define REG_TC1_WAVE (*(RwReg8 *)0x4200240CU) /**< \brief (TC1) Waveform Generation Control */
+#define REG_TC1_DRVCTRL (*(RwReg8 *)0x4200240DU) /**< \brief (TC1) Control C */
+#define REG_TC1_DBGCTRL (*(RwReg8 *)0x4200240FU) /**< \brief (TC1) Debug Control */
+#define REG_TC1_SYNCBUSY (*(RoReg *)0x42002410U) /**< \brief (TC1) Synchronization Status */
+#define REG_TC1_COUNT16_COUNT (*(RwReg16*)0x42002414U) /**< \brief (TC1) COUNT16 Count */
+#define REG_TC1_COUNT16_CC0 (*(RwReg16*)0x4200241CU) /**< \brief (TC1) COUNT16 Compare and Capture 0 */
+#define REG_TC1_COUNT16_CC1 (*(RwReg16*)0x4200241EU) /**< \brief (TC1) COUNT16 Compare and Capture 1 */
+#define REG_TC1_COUNT16_CCBUF0 (*(RwReg16*)0x42002430U) /**< \brief (TC1) COUNT16 Compare and Capture Buffer 0 */
+#define REG_TC1_COUNT16_CCBUF1 (*(RwReg16*)0x42002432U) /**< \brief (TC1) COUNT16 Compare and Capture Buffer 1 */
+#define REG_TC1_COUNT32_COUNT (*(RwReg *)0x42002414U) /**< \brief (TC1) COUNT32 Count */
+#define REG_TC1_COUNT32_CC0 (*(RwReg *)0x4200241CU) /**< \brief (TC1) COUNT32 Compare and Capture 0 */
+#define REG_TC1_COUNT32_CC1 (*(RwReg *)0x42002420U) /**< \brief (TC1) COUNT32 Compare and Capture 1 */
+#define REG_TC1_COUNT32_CCBUF0 (*(RwReg *)0x42002430U) /**< \brief (TC1) COUNT32 Compare and Capture Buffer 0 */
+#define REG_TC1_COUNT32_CCBUF1 (*(RwReg *)0x42002434U) /**< \brief (TC1) COUNT32 Compare and Capture Buffer 1 */
+#define REG_TC1_COUNT8_COUNT (*(RwReg8 *)0x42002414U) /**< \brief (TC1) COUNT8 Count */
+#define REG_TC1_COUNT8_PER (*(RwReg8 *)0x4200241BU) /**< \brief (TC1) COUNT8 Period */
+#define REG_TC1_COUNT8_CC0 (*(RwReg8 *)0x4200241CU) /**< \brief (TC1) COUNT8 Compare and Capture 0 */
+#define REG_TC1_COUNT8_CC1 (*(RwReg8 *)0x4200241DU) /**< \brief (TC1) COUNT8 Compare and Capture 1 */
+#define REG_TC1_COUNT8_PERBUF (*(RwReg8 *)0x4200242FU) /**< \brief (TC1) COUNT8 Period Buffer */
+#define REG_TC1_COUNT8_CCBUF0 (*(RwReg8 *)0x42002430U) /**< \brief (TC1) COUNT8 Compare and Capture Buffer 0 */
+#define REG_TC1_COUNT8_CCBUF1 (*(RwReg8 *)0x42002431U) /**< \brief (TC1) COUNT8 Compare and Capture Buffer 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TC1 peripheral ========== */
+#define TC1_CC_NUM 2
+#define TC1_DMAC_ID_MC_0 23
+#define TC1_DMAC_ID_MC_1 24
+#define TC1_DMAC_ID_MC_LSB 23
+#define TC1_DMAC_ID_MC_MSB 24
+#define TC1_DMAC_ID_MC_SIZE 2
+#define TC1_DMAC_ID_OVF 22 // Indexes of DMA Overflow trigger
+#define TC1_EXT 0
+#define TC1_GCLK_ID 23
+#define TC1_MASTER 0
+#define TC1_OW_NUM 2
+
+#endif /* _SAML22_TC1_INSTANCE_ */
diff --git a/Sensor Watch Starter Project/include/instance/tc2.h b/Sensor Watch Starter Project/include/instance/tc2.h new file mode 100755 index 00000000..7b5b2c84 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/tc2.h @@ -0,0 +1,123 @@ +/**
+ * \file
+ *
+ * \brief Instance description for TC2
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAML22_TC2_INSTANCE_
+#define _SAML22_TC2_INSTANCE_
+
+/* ========== Register definition for TC2 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC2_CTRLA (0x42002800U) /**< \brief (TC2) Control A */
+#define REG_TC2_CTRLBCLR (0x42002804U) /**< \brief (TC2) Control B Clear */
+#define REG_TC2_CTRLBSET (0x42002805U) /**< \brief (TC2) Control B Set */
+#define REG_TC2_EVCTRL (0x42002806U) /**< \brief (TC2) Event Control */
+#define REG_TC2_INTENCLR (0x42002808U) /**< \brief (TC2) Interrupt Enable Clear */
+#define REG_TC2_INTENSET (0x42002809U) /**< \brief (TC2) Interrupt Enable Set */
+#define REG_TC2_INTFLAG (0x4200280AU) /**< \brief (TC2) Interrupt Flag Status and Clear */
+#define REG_TC2_STATUS (0x4200280BU) /**< \brief (TC2) Status */
+#define REG_TC2_WAVE (0x4200280CU) /**< \brief (TC2) Waveform Generation Control */
+#define REG_TC2_DRVCTRL (0x4200280DU) /**< \brief (TC2) Control C */
+#define REG_TC2_DBGCTRL (0x4200280FU) /**< \brief (TC2) Debug Control */
+#define REG_TC2_SYNCBUSY (0x42002810U) /**< \brief (TC2) Synchronization Status */
+#define REG_TC2_COUNT16_COUNT (0x42002814U) /**< \brief (TC2) COUNT16 Count */
+#define REG_TC2_COUNT16_CC0 (0x4200281CU) /**< \brief (TC2) COUNT16 Compare and Capture 0 */
+#define REG_TC2_COUNT16_CC1 (0x4200281EU) /**< \brief (TC2) COUNT16 Compare and Capture 1 */
+#define REG_TC2_COUNT16_CCBUF0 (0x42002830U) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 0 */
+#define REG_TC2_COUNT16_CCBUF1 (0x42002832U) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 1 */
+#define REG_TC2_COUNT32_COUNT (0x42002814U) /**< \brief (TC2) COUNT32 Count */
+#define REG_TC2_COUNT32_CC0 (0x4200281CU) /**< \brief (TC2) COUNT32 Compare and Capture 0 */
+#define REG_TC2_COUNT32_CC1 (0x42002820U) /**< \brief (TC2) COUNT32 Compare and Capture 1 */
+#define REG_TC2_COUNT32_CCBUF0 (0x42002830U) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 0 */
+#define REG_TC2_COUNT32_CCBUF1 (0x42002834U) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 1 */
+#define REG_TC2_COUNT8_COUNT (0x42002814U) /**< \brief (TC2) COUNT8 Count */
+#define REG_TC2_COUNT8_PER (0x4200281BU) /**< \brief (TC2) COUNT8 Period */
+#define REG_TC2_COUNT8_CC0 (0x4200281CU) /**< \brief (TC2) COUNT8 Compare and Capture 0 */
+#define REG_TC2_COUNT8_CC1 (0x4200281DU) /**< \brief (TC2) COUNT8 Compare and Capture 1 */
+#define REG_TC2_COUNT8_PERBUF (0x4200282FU) /**< \brief (TC2) COUNT8 Period Buffer */
+#define REG_TC2_COUNT8_CCBUF0 (0x42002830U) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 0 */
+#define REG_TC2_COUNT8_CCBUF1 (0x42002831U) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 1 */
+#else
+#define REG_TC2_CTRLA (*(RwReg *)0x42002800U) /**< \brief (TC2) Control A */
+#define REG_TC2_CTRLBCLR (*(RwReg8 *)0x42002804U) /**< \brief (TC2) Control B Clear */
+#define REG_TC2_CTRLBSET (*(RwReg8 *)0x42002805U) /**< \brief (TC2) Control B Set */
+#define REG_TC2_EVCTRL (*(RwReg16*)0x42002806U) /**< \brief (TC2) Event Control */
+#define REG_TC2_INTENCLR (*(RwReg8 *)0x42002808U) /**< \brief (TC2) Interrupt Enable Clear */
+#define REG_TC2_INTENSET (*(RwReg8 *)0x42002809U) /**< \brief (TC2) Interrupt Enable Set */
+#define REG_TC2_INTFLAG (*(RwReg8 *)0x4200280AU) /**< \brief (TC2) Interrupt Flag Status and Clear */
+#define REG_TC2_STATUS (*(RwReg8 *)0x4200280BU) /**< \brief (TC2) Status */
+#define REG_TC2_WAVE (*(RwReg8 *)0x4200280CU) /**< \brief (TC2) Waveform Generation Control */
+#define REG_TC2_DRVCTRL (*(RwReg8 *)0x4200280DU) /**< \brief (TC2) Control C */
+#define REG_TC2_DBGCTRL (*(RwReg8 *)0x4200280FU) /**< \brief (TC2) Debug Control */
+#define REG_TC2_SYNCBUSY (*(RoReg *)0x42002810U) /**< \brief (TC2) Synchronization Status */
+#define REG_TC2_COUNT16_COUNT (*(RwReg16*)0x42002814U) /**< \brief (TC2) COUNT16 Count */
+#define REG_TC2_COUNT16_CC0 (*(RwReg16*)0x4200281CU) /**< \brief (TC2) COUNT16 Compare and Capture 0 */
+#define REG_TC2_COUNT16_CC1 (*(RwReg16*)0x4200281EU) /**< \brief (TC2) COUNT16 Compare and Capture 1 */
+#define REG_TC2_COUNT16_CCBUF0 (*(RwReg16*)0x42002830U) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 0 */
+#define REG_TC2_COUNT16_CCBUF1 (*(RwReg16*)0x42002832U) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 1 */
+#define REG_TC2_COUNT32_COUNT (*(RwReg *)0x42002814U) /**< \brief (TC2) COUNT32 Count */
+#define REG_TC2_COUNT32_CC0 (*(RwReg *)0x4200281CU) /**< \brief (TC2) COUNT32 Compare and Capture 0 */
+#define REG_TC2_COUNT32_CC1 (*(RwReg *)0x42002820U) /**< \brief (TC2) COUNT32 Compare and Capture 1 */
+#define REG_TC2_COUNT32_CCBUF0 (*(RwReg *)0x42002830U) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 0 */
+#define REG_TC2_COUNT32_CCBUF1 (*(RwReg *)0x42002834U) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 1 */
+#define REG_TC2_COUNT8_COUNT (*(RwReg8 *)0x42002814U) /**< \brief (TC2) COUNT8 Count */
+#define REG_TC2_COUNT8_PER (*(RwReg8 *)0x4200281BU) /**< \brief (TC2) COUNT8 Period */
+#define REG_TC2_COUNT8_CC0 (*(RwReg8 *)0x4200281CU) /**< \brief (TC2) COUNT8 Compare and Capture 0 */
+#define REG_TC2_COUNT8_CC1 (*(RwReg8 *)0x4200281DU) /**< \brief (TC2) COUNT8 Compare and Capture 1 */
+#define REG_TC2_COUNT8_PERBUF (*(RwReg8 *)0x4200282FU) /**< \brief (TC2) COUNT8 Period Buffer */
+#define REG_TC2_COUNT8_CCBUF0 (*(RwReg8 *)0x42002830U) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 0 */
+#define REG_TC2_COUNT8_CCBUF1 (*(RwReg8 *)0x42002831U) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TC2 peripheral ========== */
+#define TC2_CC_NUM 2
+#define TC2_DMAC_ID_MC_0 26
+#define TC2_DMAC_ID_MC_1 27
+#define TC2_DMAC_ID_MC_LSB 26
+#define TC2_DMAC_ID_MC_MSB 27
+#define TC2_DMAC_ID_MC_SIZE 2
+#define TC2_DMAC_ID_OVF 25 // Indexes of DMA Overflow trigger
+#define TC2_EXT 0
+#define TC2_GCLK_ID 24
+#define TC2_MASTER 1
+#define TC2_OW_NUM 2
+
+#endif /* _SAML22_TC2_INSTANCE_ */
diff --git a/Sensor Watch Starter Project/include/instance/tc3.h b/Sensor Watch Starter Project/include/instance/tc3.h new file mode 100755 index 00000000..dc7af021 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/tc3.h @@ -0,0 +1,123 @@ +/**
+ * \file
+ *
+ * \brief Instance description for TC3
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAML22_TC3_INSTANCE_
+#define _SAML22_TC3_INSTANCE_
+
+/* ========== Register definition for TC3 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC3_CTRLA (0x42002C00U) /**< \brief (TC3) Control A */
+#define REG_TC3_CTRLBCLR (0x42002C04U) /**< \brief (TC3) Control B Clear */
+#define REG_TC3_CTRLBSET (0x42002C05U) /**< \brief (TC3) Control B Set */
+#define REG_TC3_EVCTRL (0x42002C06U) /**< \brief (TC3) Event Control */
+#define REG_TC3_INTENCLR (0x42002C08U) /**< \brief (TC3) Interrupt Enable Clear */
+#define REG_TC3_INTENSET (0x42002C09U) /**< \brief (TC3) Interrupt Enable Set */
+#define REG_TC3_INTFLAG (0x42002C0AU) /**< \brief (TC3) Interrupt Flag Status and Clear */
+#define REG_TC3_STATUS (0x42002C0BU) /**< \brief (TC3) Status */
+#define REG_TC3_WAVE (0x42002C0CU) /**< \brief (TC3) Waveform Generation Control */
+#define REG_TC3_DRVCTRL (0x42002C0DU) /**< \brief (TC3) Control C */
+#define REG_TC3_DBGCTRL (0x42002C0FU) /**< \brief (TC3) Debug Control */
+#define REG_TC3_SYNCBUSY (0x42002C10U) /**< \brief (TC3) Synchronization Status */
+#define REG_TC3_COUNT16_COUNT (0x42002C14U) /**< \brief (TC3) COUNT16 Count */
+#define REG_TC3_COUNT16_CC0 (0x42002C1CU) /**< \brief (TC3) COUNT16 Compare and Capture 0 */
+#define REG_TC3_COUNT16_CC1 (0x42002C1EU) /**< \brief (TC3) COUNT16 Compare and Capture 1 */
+#define REG_TC3_COUNT16_CCBUF0 (0x42002C30U) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 0 */
+#define REG_TC3_COUNT16_CCBUF1 (0x42002C32U) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 1 */
+#define REG_TC3_COUNT32_COUNT (0x42002C14U) /**< \brief (TC3) COUNT32 Count */
+#define REG_TC3_COUNT32_CC0 (0x42002C1CU) /**< \brief (TC3) COUNT32 Compare and Capture 0 */
+#define REG_TC3_COUNT32_CC1 (0x42002C20U) /**< \brief (TC3) COUNT32 Compare and Capture 1 */
+#define REG_TC3_COUNT32_CCBUF0 (0x42002C30U) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 0 */
+#define REG_TC3_COUNT32_CCBUF1 (0x42002C34U) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 1 */
+#define REG_TC3_COUNT8_COUNT (0x42002C14U) /**< \brief (TC3) COUNT8 Count */
+#define REG_TC3_COUNT8_PER (0x42002C1BU) /**< \brief (TC3) COUNT8 Period */
+#define REG_TC3_COUNT8_CC0 (0x42002C1CU) /**< \brief (TC3) COUNT8 Compare and Capture 0 */
+#define REG_TC3_COUNT8_CC1 (0x42002C1DU) /**< \brief (TC3) COUNT8 Compare and Capture 1 */
+#define REG_TC3_COUNT8_PERBUF (0x42002C2FU) /**< \brief (TC3) COUNT8 Period Buffer */
+#define REG_TC3_COUNT8_CCBUF0 (0x42002C30U) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 0 */
+#define REG_TC3_COUNT8_CCBUF1 (0x42002C31U) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 1 */
+#else
+#define REG_TC3_CTRLA (*(RwReg *)0x42002C00U) /**< \brief (TC3) Control A */
+#define REG_TC3_CTRLBCLR (*(RwReg8 *)0x42002C04U) /**< \brief (TC3) Control B Clear */
+#define REG_TC3_CTRLBSET (*(RwReg8 *)0x42002C05U) /**< \brief (TC3) Control B Set */
+#define REG_TC3_EVCTRL (*(RwReg16*)0x42002C06U) /**< \brief (TC3) Event Control */
+#define REG_TC3_INTENCLR (*(RwReg8 *)0x42002C08U) /**< \brief (TC3) Interrupt Enable Clear */
+#define REG_TC3_INTENSET (*(RwReg8 *)0x42002C09U) /**< \brief (TC3) Interrupt Enable Set */
+#define REG_TC3_INTFLAG (*(RwReg8 *)0x42002C0AU) /**< \brief (TC3) Interrupt Flag Status and Clear */
+#define REG_TC3_STATUS (*(RwReg8 *)0x42002C0BU) /**< \brief (TC3) Status */
+#define REG_TC3_WAVE (*(RwReg8 *)0x42002C0CU) /**< \brief (TC3) Waveform Generation Control */
+#define REG_TC3_DRVCTRL (*(RwReg8 *)0x42002C0DU) /**< \brief (TC3) Control C */
+#define REG_TC3_DBGCTRL (*(RwReg8 *)0x42002C0FU) /**< \brief (TC3) Debug Control */
+#define REG_TC3_SYNCBUSY (*(RoReg *)0x42002C10U) /**< \brief (TC3) Synchronization Status */
+#define REG_TC3_COUNT16_COUNT (*(RwReg16*)0x42002C14U) /**< \brief (TC3) COUNT16 Count */
+#define REG_TC3_COUNT16_CC0 (*(RwReg16*)0x42002C1CU) /**< \brief (TC3) COUNT16 Compare and Capture 0 */
+#define REG_TC3_COUNT16_CC1 (*(RwReg16*)0x42002C1EU) /**< \brief (TC3) COUNT16 Compare and Capture 1 */
+#define REG_TC3_COUNT16_CCBUF0 (*(RwReg16*)0x42002C30U) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 0 */
+#define REG_TC3_COUNT16_CCBUF1 (*(RwReg16*)0x42002C32U) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 1 */
+#define REG_TC3_COUNT32_COUNT (*(RwReg *)0x42002C14U) /**< \brief (TC3) COUNT32 Count */
+#define REG_TC3_COUNT32_CC0 (*(RwReg *)0x42002C1CU) /**< \brief (TC3) COUNT32 Compare and Capture 0 */
+#define REG_TC3_COUNT32_CC1 (*(RwReg *)0x42002C20U) /**< \brief (TC3) COUNT32 Compare and Capture 1 */
+#define REG_TC3_COUNT32_CCBUF0 (*(RwReg *)0x42002C30U) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 0 */
+#define REG_TC3_COUNT32_CCBUF1 (*(RwReg *)0x42002C34U) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 1 */
+#define REG_TC3_COUNT8_COUNT (*(RwReg8 *)0x42002C14U) /**< \brief (TC3) COUNT8 Count */
+#define REG_TC3_COUNT8_PER (*(RwReg8 *)0x42002C1BU) /**< \brief (TC3) COUNT8 Period */
+#define REG_TC3_COUNT8_CC0 (*(RwReg8 *)0x42002C1CU) /**< \brief (TC3) COUNT8 Compare and Capture 0 */
+#define REG_TC3_COUNT8_CC1 (*(RwReg8 *)0x42002C1DU) /**< \brief (TC3) COUNT8 Compare and Capture 1 */
+#define REG_TC3_COUNT8_PERBUF (*(RwReg8 *)0x42002C2FU) /**< \brief (TC3) COUNT8 Period Buffer */
+#define REG_TC3_COUNT8_CCBUF0 (*(RwReg8 *)0x42002C30U) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 0 */
+#define REG_TC3_COUNT8_CCBUF1 (*(RwReg8 *)0x42002C31U) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TC3 peripheral ========== */
+#define TC3_CC_NUM 2
+#define TC3_DMAC_ID_MC_0 29
+#define TC3_DMAC_ID_MC_1 30
+#define TC3_DMAC_ID_MC_LSB 29
+#define TC3_DMAC_ID_MC_MSB 30
+#define TC3_DMAC_ID_MC_SIZE 2
+#define TC3_DMAC_ID_OVF 28 // Indexes of DMA Overflow trigger
+#define TC3_EXT 0
+#define TC3_GCLK_ID 24
+#define TC3_MASTER 0
+#define TC3_OW_NUM 2
+
+#endif /* _SAML22_TC3_INSTANCE_ */
diff --git a/Sensor Watch Starter Project/include/instance/tcc0.h b/Sensor Watch Starter Project/include/instance/tcc0.h new file mode 100755 index 00000000..263eaa85 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/tcc0.h @@ -0,0 +1,129 @@ +/**
+ * \file
+ *
+ * \brief Instance description for TCC0
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAML22_TCC0_INSTANCE_
+#define _SAML22_TCC0_INSTANCE_
+
+/* ========== Register definition for TCC0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TCC0_CTRLA (0x42001C00U) /**< \brief (TCC0) Control A */
+#define REG_TCC0_CTRLBCLR (0x42001C04U) /**< \brief (TCC0) Control B Clear */
+#define REG_TCC0_CTRLBSET (0x42001C05U) /**< \brief (TCC0) Control B Set */
+#define REG_TCC0_SYNCBUSY (0x42001C08U) /**< \brief (TCC0) Synchronization Busy */
+#define REG_TCC0_FCTRLA (0x42001C0CU) /**< \brief (TCC0) Recoverable Fault A Configuration */
+#define REG_TCC0_FCTRLB (0x42001C10U) /**< \brief (TCC0) Recoverable Fault B Configuration */
+#define REG_TCC0_WEXCTRL (0x42001C14U) /**< \brief (TCC0) Waveform Extension Configuration */
+#define REG_TCC0_DRVCTRL (0x42001C18U) /**< \brief (TCC0) Driver Control */
+#define REG_TCC0_DBGCTRL (0x42001C1EU) /**< \brief (TCC0) Debug Control */
+#define REG_TCC0_EVCTRL (0x42001C20U) /**< \brief (TCC0) Event Control */
+#define REG_TCC0_INTENCLR (0x42001C24U) /**< \brief (TCC0) Interrupt Enable Clear */
+#define REG_TCC0_INTENSET (0x42001C28U) /**< \brief (TCC0) Interrupt Enable Set */
+#define REG_TCC0_INTFLAG (0x42001C2CU) /**< \brief (TCC0) Interrupt Flag Status and Clear */
+#define REG_TCC0_STATUS (0x42001C30U) /**< \brief (TCC0) Status */
+#define REG_TCC0_COUNT (0x42001C34U) /**< \brief (TCC0) Count */
+#define REG_TCC0_PATT (0x42001C38U) /**< \brief (TCC0) Pattern */
+#define REG_TCC0_WAVE (0x42001C3CU) /**< \brief (TCC0) Waveform Control */
+#define REG_TCC0_PER (0x42001C40U) /**< \brief (TCC0) Period */
+#define REG_TCC0_CC0 (0x42001C44U) /**< \brief (TCC0) Compare and Capture 0 */
+#define REG_TCC0_CC1 (0x42001C48U) /**< \brief (TCC0) Compare and Capture 1 */
+#define REG_TCC0_CC2 (0x42001C4CU) /**< \brief (TCC0) Compare and Capture 2 */
+#define REG_TCC0_CC3 (0x42001C50U) /**< \brief (TCC0) Compare and Capture 3 */
+#define REG_TCC0_PATTBUF (0x42001C64U) /**< \brief (TCC0) Pattern Buffer */
+#define REG_TCC0_PERBUF (0x42001C6CU) /**< \brief (TCC0) Period Buffer */
+#define REG_TCC0_CCBUF0 (0x42001C70U) /**< \brief (TCC0) Compare and Capture Buffer 0 */
+#define REG_TCC0_CCBUF1 (0x42001C74U) /**< \brief (TCC0) Compare and Capture Buffer 1 */
+#define REG_TCC0_CCBUF2 (0x42001C78U) /**< \brief (TCC0) Compare and Capture Buffer 2 */
+#define REG_TCC0_CCBUF3 (0x42001C7CU) /**< \brief (TCC0) Compare and Capture Buffer 3 */
+#else
+#define REG_TCC0_CTRLA (*(RwReg *)0x42001C00U) /**< \brief (TCC0) Control A */
+#define REG_TCC0_CTRLBCLR (*(RwReg8 *)0x42001C04U) /**< \brief (TCC0) Control B Clear */
+#define REG_TCC0_CTRLBSET (*(RwReg8 *)0x42001C05U) /**< \brief (TCC0) Control B Set */
+#define REG_TCC0_SYNCBUSY (*(RoReg *)0x42001C08U) /**< \brief (TCC0) Synchronization Busy */
+#define REG_TCC0_FCTRLA (*(RwReg *)0x42001C0CU) /**< \brief (TCC0) Recoverable Fault A Configuration */
+#define REG_TCC0_FCTRLB (*(RwReg *)0x42001C10U) /**< \brief (TCC0) Recoverable Fault B Configuration */
+#define REG_TCC0_WEXCTRL (*(RwReg *)0x42001C14U) /**< \brief (TCC0) Waveform Extension Configuration */
+#define REG_TCC0_DRVCTRL (*(RwReg *)0x42001C18U) /**< \brief (TCC0) Driver Control */
+#define REG_TCC0_DBGCTRL (*(RwReg8 *)0x42001C1EU) /**< \brief (TCC0) Debug Control */
+#define REG_TCC0_EVCTRL (*(RwReg *)0x42001C20U) /**< \brief (TCC0) Event Control */
+#define REG_TCC0_INTENCLR (*(RwReg *)0x42001C24U) /**< \brief (TCC0) Interrupt Enable Clear */
+#define REG_TCC0_INTENSET (*(RwReg *)0x42001C28U) /**< \brief (TCC0) Interrupt Enable Set */
+#define REG_TCC0_INTFLAG (*(RwReg *)0x42001C2CU) /**< \brief (TCC0) Interrupt Flag Status and Clear */
+#define REG_TCC0_STATUS (*(RwReg *)0x42001C30U) /**< \brief (TCC0) Status */
+#define REG_TCC0_COUNT (*(RwReg *)0x42001C34U) /**< \brief (TCC0) Count */
+#define REG_TCC0_PATT (*(RwReg16*)0x42001C38U) /**< \brief (TCC0) Pattern */
+#define REG_TCC0_WAVE (*(RwReg *)0x42001C3CU) /**< \brief (TCC0) Waveform Control */
+#define REG_TCC0_PER (*(RwReg *)0x42001C40U) /**< \brief (TCC0) Period */
+#define REG_TCC0_CC0 (*(RwReg *)0x42001C44U) /**< \brief (TCC0) Compare and Capture 0 */
+#define REG_TCC0_CC1 (*(RwReg *)0x42001C48U) /**< \brief (TCC0) Compare and Capture 1 */
+#define REG_TCC0_CC2 (*(RwReg *)0x42001C4CU) /**< \brief (TCC0) Compare and Capture 2 */
+#define REG_TCC0_CC3 (*(RwReg *)0x42001C50U) /**< \brief (TCC0) Compare and Capture 3 */
+#define REG_TCC0_PATTBUF (*(RwReg16*)0x42001C64U) /**< \brief (TCC0) Pattern Buffer */
+#define REG_TCC0_PERBUF (*(RwReg *)0x42001C6CU) /**< \brief (TCC0) Period Buffer */
+#define REG_TCC0_CCBUF0 (*(RwReg *)0x42001C70U) /**< \brief (TCC0) Compare and Capture Buffer 0 */
+#define REG_TCC0_CCBUF1 (*(RwReg *)0x42001C74U) /**< \brief (TCC0) Compare and Capture Buffer 1 */
+#define REG_TCC0_CCBUF2 (*(RwReg *)0x42001C78U) /**< \brief (TCC0) Compare and Capture Buffer 2 */
+#define REG_TCC0_CCBUF3 (*(RwReg *)0x42001C7CU) /**< \brief (TCC0) Compare and Capture Buffer 3 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TCC0 peripheral ========== */
+#define TCC0_CC_NUM 4 // Number of Compare/Capture units
+#define TCC0_DITHERING 1 // Dithering feature implemented
+#define TCC0_DMAC_ID_MC_0 15
+#define TCC0_DMAC_ID_MC_1 16
+#define TCC0_DMAC_ID_MC_2 17
+#define TCC0_DMAC_ID_MC_3 18
+#define TCC0_DMAC_ID_MC_LSB 15
+#define TCC0_DMAC_ID_MC_MSB 18
+#define TCC0_DMAC_ID_MC_SIZE 4
+#define TCC0_DMAC_ID_OVF 14 // DMA overflow/underflow/retrigger trigger
+#define TCC0_DTI 1 // Dead-Time-Insertion feature implemented
+#define TCC0_EXT 31 // Coding of implemented extended features
+#define TCC0_GCLK_ID 22 // Index of Generic Clock
+#define TCC0_OTMX 1 // Output Matrix feature implemented
+#define TCC0_OW_NUM 8 // Number of Output Waveforms
+#define TCC0_PG 1 // Pattern Generation feature implemented
+#define TCC0_SIZE 24
+#define TCC0_SWAP 1 // DTI outputs swap feature implemented
+#define TCC0_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave
+
+#endif /* _SAML22_TCC0_INSTANCE_ */
diff --git a/Sensor Watch Starter Project/include/instance/trng.h b/Sensor Watch Starter Project/include/instance/trng.h new file mode 100755 index 00000000..b3f143ce --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/trng.h @@ -0,0 +1,65 @@ +/**
+ * \file
+ *
+ * \brief Instance description for TRNG
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAML22_TRNG_INSTANCE_
+#define _SAML22_TRNG_INSTANCE_
+
+/* ========== Register definition for TRNG peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TRNG_CTRLA (0x42004400U) /**< \brief (TRNG) Control A */
+#define REG_TRNG_EVCTRL (0x42004404U) /**< \brief (TRNG) Event Control */
+#define REG_TRNG_INTENCLR (0x42004408U) /**< \brief (TRNG) Interrupt Enable Clear */
+#define REG_TRNG_INTENSET (0x42004409U) /**< \brief (TRNG) Interrupt Enable Set */
+#define REG_TRNG_INTFLAG (0x4200440AU) /**< \brief (TRNG) Interrupt Flag Status and Clear */
+#define REG_TRNG_DATA (0x42004420U) /**< \brief (TRNG) Output Data */
+#else
+#define REG_TRNG_CTRLA (*(RwReg8 *)0x42004400U) /**< \brief (TRNG) Control A */
+#define REG_TRNG_EVCTRL (*(RwReg8 *)0x42004404U) /**< \brief (TRNG) Event Control */
+#define REG_TRNG_INTENCLR (*(RwReg8 *)0x42004408U) /**< \brief (TRNG) Interrupt Enable Clear */
+#define REG_TRNG_INTENSET (*(RwReg8 *)0x42004409U) /**< \brief (TRNG) Interrupt Enable Set */
+#define REG_TRNG_INTFLAG (*(RwReg8 *)0x4200440AU) /**< \brief (TRNG) Interrupt Flag Status and Clear */
+#define REG_TRNG_DATA (*(RoReg *)0x42004420U) /**< \brief (TRNG) Output Data */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+
+#endif /* _SAML22_TRNG_INSTANCE_ */
diff --git a/Sensor Watch Starter Project/include/instance/usb.h b/Sensor Watch Starter Project/include/instance/usb.h new file mode 100755 index 00000000..b6b020a1 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/usb.h @@ -0,0 +1,196 @@ +/**
+ * \file
+ *
+ * \brief Instance description for USB
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAML22_USB_INSTANCE_
+#define _SAML22_USB_INSTANCE_
+
+/* ========== Register definition for USB peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_USB_CTRLA (0x41000000U) /**< \brief (USB) Control A */
+#define REG_USB_SYNCBUSY (0x41000002U) /**< \brief (USB) Synchronization Busy */
+#define REG_USB_FSMSTATUS (0x4100000DU) /**< \brief (USB) Finite State Machine Status */
+#define REG_USB_DESCADD (0x41000024U) /**< \brief (USB) Descriptor Address */
+#define REG_USB_PADCAL (0x41000028U) /**< \brief (USB) USB PAD Calibration */
+#define REG_USB_DEVICE_CTRLB (0x41000008U) /**< \brief (USB) DEVICE Control B */
+#define REG_USB_DEVICE_DADD (0x4100000AU) /**< \brief (USB) DEVICE Device Address */
+#define REG_USB_DEVICE_STATUS (0x4100000CU) /**< \brief (USB) DEVICE Status */
+#define REG_USB_DEVICE_FNUM (0x41000010U) /**< \brief (USB) DEVICE Device Frame Number */
+#define REG_USB_DEVICE_INTENCLR (0x41000014U) /**< \brief (USB) DEVICE Device Interrupt Enable Clear */
+#define REG_USB_DEVICE_INTENSET (0x41000018U) /**< \brief (USB) DEVICE Device Interrupt Enable Set */
+#define REG_USB_DEVICE_INTFLAG (0x4100001CU) /**< \brief (USB) DEVICE Device Interrupt Flag */
+#define REG_USB_DEVICE_EPINTSMRY (0x41000020U) /**< \brief (USB) DEVICE End Point Interrupt Summary */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG0 (0x41000100U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR0 (0x41000104U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET0 (0x41000105U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS0 (0x41000106U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG0 (0x41000107U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR0 (0x41000108U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET0 (0x41000109U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG1 (0x41000120U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR1 (0x41000124U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET1 (0x41000125U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS1 (0x41000126U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG1 (0x41000127U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR1 (0x41000128U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET1 (0x41000129U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG2 (0x41000140U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR2 (0x41000144U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET2 (0x41000145U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS2 (0x41000146U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG2 (0x41000147U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR2 (0x41000148U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET2 (0x41000149U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG3 (0x41000160U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR3 (0x41000164U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET3 (0x41000165U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS3 (0x41000166U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG3 (0x41000167U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR3 (0x41000168U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET3 (0x41000169U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG4 (0x41000180U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR4 (0x41000184U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET4 (0x41000185U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS4 (0x41000186U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG4 (0x41000187U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR4 (0x41000188U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET4 (0x41000189U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG5 (0x410001A0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR5 (0x410001A4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET5 (0x410001A5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS5 (0x410001A6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG5 (0x410001A7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR5 (0x410001A8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET5 (0x410001A9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG6 (0x410001C0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR6 (0x410001C4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET6 (0x410001C5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS6 (0x410001C6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG6 (0x410001C7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR6 (0x410001C8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET6 (0x410001C9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG7 (0x410001E0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR7 (0x410001E4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET7 (0x410001E5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS7 (0x410001E6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG7 (0x410001E7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR7 (0x410001E8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET7 (0x410001E9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 7 */
+#else
+#define REG_USB_CTRLA (*(RwReg8 *)0x41000000U) /**< \brief (USB) Control A */
+#define REG_USB_SYNCBUSY (*(RoReg8 *)0x41000002U) /**< \brief (USB) Synchronization Busy */
+#define REG_USB_FSMSTATUS (*(RoReg8 *)0x4100000DU) /**< \brief (USB) Finite State Machine Status */
+#define REG_USB_DESCADD (*(RwReg *)0x41000024U) /**< \brief (USB) Descriptor Address */
+#define REG_USB_PADCAL (*(RwReg16*)0x41000028U) /**< \brief (USB) USB PAD Calibration */
+#define REG_USB_DEVICE_CTRLB (*(RwReg16*)0x41000008U) /**< \brief (USB) DEVICE Control B */
+#define REG_USB_DEVICE_DADD (*(RwReg8 *)0x4100000AU) /**< \brief (USB) DEVICE Device Address */
+#define REG_USB_DEVICE_STATUS (*(RoReg8 *)0x4100000CU) /**< \brief (USB) DEVICE Status */
+#define REG_USB_DEVICE_FNUM (*(RoReg16*)0x41000010U) /**< \brief (USB) DEVICE Device Frame Number */
+#define REG_USB_DEVICE_INTENCLR (*(RwReg16*)0x41000014U) /**< \brief (USB) DEVICE Device Interrupt Enable Clear */
+#define REG_USB_DEVICE_INTENSET (*(RwReg16*)0x41000018U) /**< \brief (USB) DEVICE Device Interrupt Enable Set */
+#define REG_USB_DEVICE_INTFLAG (*(RwReg16*)0x4100001CU) /**< \brief (USB) DEVICE Device Interrupt Flag */
+#define REG_USB_DEVICE_EPINTSMRY (*(RoReg16*)0x41000020U) /**< \brief (USB) DEVICE End Point Interrupt Summary */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG0 (*(RwReg8 *)0x41000100U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR0 (*(WoReg8 *)0x41000104U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET0 (*(WoReg8 *)0x41000105U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS0 (*(RoReg8 *)0x41000106U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG0 (*(RwReg8 *)0x41000107U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR0 (*(RwReg8 *)0x41000108U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET0 (*(RwReg8 *)0x41000109U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG1 (*(RwReg8 *)0x41000120U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR1 (*(WoReg8 *)0x41000124U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET1 (*(WoReg8 *)0x41000125U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS1 (*(RoReg8 *)0x41000126U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG1 (*(RwReg8 *)0x41000127U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR1 (*(RwReg8 *)0x41000128U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET1 (*(RwReg8 *)0x41000129U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG2 (*(RwReg8 *)0x41000140U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR2 (*(WoReg8 *)0x41000144U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET2 (*(WoReg8 *)0x41000145U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS2 (*(RoReg8 *)0x41000146U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG2 (*(RwReg8 *)0x41000147U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR2 (*(RwReg8 *)0x41000148U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET2 (*(RwReg8 *)0x41000149U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG3 (*(RwReg8 *)0x41000160U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR3 (*(WoReg8 *)0x41000164U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET3 (*(WoReg8 *)0x41000165U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS3 (*(RoReg8 *)0x41000166U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG3 (*(RwReg8 *)0x41000167U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR3 (*(RwReg8 *)0x41000168U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET3 (*(RwReg8 *)0x41000169U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG4 (*(RwReg8 *)0x41000180U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR4 (*(WoReg8 *)0x41000184U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET4 (*(WoReg8 *)0x41000185U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS4 (*(RoReg8 *)0x41000186U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG4 (*(RwReg8 *)0x41000187U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR4 (*(RwReg8 *)0x41000188U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET4 (*(RwReg8 *)0x41000189U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG5 (*(RwReg8 *)0x410001A0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR5 (*(WoReg8 *)0x410001A4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET5 (*(WoReg8 *)0x410001A5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS5 (*(RoReg8 *)0x410001A6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG5 (*(RwReg8 *)0x410001A7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR5 (*(RwReg8 *)0x410001A8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET5 (*(RwReg8 *)0x410001A9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG6 (*(RwReg8 *)0x410001C0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR6 (*(WoReg8 *)0x410001C4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET6 (*(WoReg8 *)0x410001C5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS6 (*(RoReg8 *)0x410001C6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG6 (*(RwReg8 *)0x410001C7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR6 (*(RwReg8 *)0x410001C8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET6 (*(RwReg8 *)0x410001C9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG7 (*(RwReg8 *)0x410001E0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR7 (*(WoReg8 *)0x410001E4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET7 (*(WoReg8 *)0x410001E5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS7 (*(RoReg8 *)0x410001E6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG7 (*(RwReg8 *)0x410001E7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR7 (*(RwReg8 *)0x410001E8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET7 (*(RwReg8 *)0x410001E9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 7 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for USB peripheral ========== */
+#define USB_EPT_NBR 8 // Number of USB end points (obsolete)
+#define USB_EPT_NUM 8 // Number of USB end points
+#define USB_GCLK_ID 6 // Index of Generic Clock
+#define USB_PIPE_NUM 0 // Number of USB pipes
+
+#endif /* _SAML22_USB_INSTANCE_ */
diff --git a/Sensor Watch Starter Project/include/instance/wdt.h b/Sensor Watch Starter Project/include/instance/wdt.h new file mode 100755 index 00000000..2149da28 --- /dev/null +++ b/Sensor Watch Starter Project/include/instance/wdt.h @@ -0,0 +1,69 @@ +/**
+ * \file
+ *
+ * \brief Instance description for WDT
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAML22_WDT_INSTANCE_
+#define _SAML22_WDT_INSTANCE_
+
+/* ========== Register definition for WDT peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_WDT_CTRLA (0x40002000U) /**< \brief (WDT) Control */
+#define REG_WDT_CONFIG (0x40002001U) /**< \brief (WDT) Configuration */
+#define REG_WDT_EWCTRL (0x40002002U) /**< \brief (WDT) Early Warning Interrupt Control */
+#define REG_WDT_INTENCLR (0x40002004U) /**< \brief (WDT) Interrupt Enable Clear */
+#define REG_WDT_INTENSET (0x40002005U) /**< \brief (WDT) Interrupt Enable Set */
+#define REG_WDT_INTFLAG (0x40002006U) /**< \brief (WDT) Interrupt Flag Status and Clear */
+#define REG_WDT_SYNCBUSY (0x40002008U) /**< \brief (WDT) Synchronization Busy */
+#define REG_WDT_CLEAR (0x4000200CU) /**< \brief (WDT) Clear */
+#else
+#define REG_WDT_CTRLA (*(RwReg8 *)0x40002000U) /**< \brief (WDT) Control */
+#define REG_WDT_CONFIG (*(RwReg8 *)0x40002001U) /**< \brief (WDT) Configuration */
+#define REG_WDT_EWCTRL (*(RwReg8 *)0x40002002U) /**< \brief (WDT) Early Warning Interrupt Control */
+#define REG_WDT_INTENCLR (*(RwReg8 *)0x40002004U) /**< \brief (WDT) Interrupt Enable Clear */
+#define REG_WDT_INTENSET (*(RwReg8 *)0x40002005U) /**< \brief (WDT) Interrupt Enable Set */
+#define REG_WDT_INTFLAG (*(RwReg8 *)0x40002006U) /**< \brief (WDT) Interrupt Flag Status and Clear */
+#define REG_WDT_SYNCBUSY (*(RoReg *)0x40002008U) /**< \brief (WDT) Synchronization Busy */
+#define REG_WDT_CLEAR (*(WoReg8 *)0x4000200CU) /**< \brief (WDT) Clear */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+
+#endif /* _SAML22_WDT_INSTANCE_ */
|