diff options
Diffstat (limited to 'tinyusb/hw/bsp/same70_xplained')
| -rwxr-xr-x | tinyusb/hw/bsp/same70_xplained/board.mk | 56 | ||||
| -rwxr-xr-x | tinyusb/hw/bsp/same70_xplained/hpl_pmc_config.h | 1053 | ||||
| -rwxr-xr-x | tinyusb/hw/bsp/same70_xplained/hpl_usart_config.h | 215 | ||||
| -rwxr-xr-x | tinyusb/hw/bsp/same70_xplained/hpl_xdmac_config.h | 4400 | ||||
| -rwxr-xr-x | tinyusb/hw/bsp/same70_xplained/peripheral_clk_config.h | 126 | ||||
| -rwxr-xr-x | tinyusb/hw/bsp/same70_xplained/same70_xplained.c | 156 |
6 files changed, 0 insertions, 6006 deletions
diff --git a/tinyusb/hw/bsp/same70_xplained/board.mk b/tinyusb/hw/bsp/same70_xplained/board.mk deleted file mode 100755 index c9bc0cea..00000000 --- a/tinyusb/hw/bsp/same70_xplained/board.mk +++ /dev/null @@ -1,56 +0,0 @@ -DEPS_SUBMODULES += hw/mcu/microchip - -CFLAGS += \ - -mthumb \ - -mabi=aapcs \ - -mcpu=cortex-m7 \ - -mfloat-abi=hard \ - -mfpu=fpv4-sp-d16 \ - -nostdlib -nostartfiles \ - -D__SAME70Q21B__ \ - -DCFG_TUSB_MCU=OPT_MCU_SAMX7X - -# suppress following warnings from mcu driver -CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align - -ASF_DIR = hw/mcu/microchip/same70 - -# All source paths should be relative to the top level. -LD_FILE = $(ASF_DIR)/same70b/gcc/gcc/same70q21b_flash.ld - -SRC_C += \ - src/portable/microchip/samx7x/dcd_samx7x.c \ - $(ASF_DIR)/same70b/gcc/gcc/startup_same70q21b.c \ - $(ASF_DIR)/same70b/gcc/system_same70q21b.c \ - $(ASF_DIR)/hpl/core/hpl_init.c \ - $(ASF_DIR)/hpl/usart/hpl_usart.c \ - $(ASF_DIR)/hpl/pmc/hpl_pmc.c \ - $(ASF_DIR)/hal/src/hal_usart_async.c \ - $(ASF_DIR)/hal/src/hal_io.c \ - $(ASF_DIR)/hal/src/hal_atomic.c \ - $(ASF_DIR)/hal/utils/src/utils_ringbuffer.c - -INC += \ - $(TOP)/hw/bsp/$(BOARD) \ - $(TOP)/$(ASF_DIR) \ - $(TOP)/$(ASF_DIR)/config \ - $(TOP)/$(ASF_DIR)/same70b/include \ - $(TOP)/$(ASF_DIR)/hal/include \ - $(TOP)/$(ASF_DIR)/hal/utils/include \ - $(TOP)/$(ASF_DIR)/hpl/core \ - $(TOP)/$(ASF_DIR)/hpl/pio \ - $(TOP)/$(ASF_DIR)/hpl/pmc \ - $(TOP)/$(ASF_DIR)/hri \ - $(TOP)/$(ASF_DIR)/CMSIS/Core/Include - -# For freeRTOS port source -FREERTOS_PORT = ARM_CM7 - -# For flash-jlink target -JLINK_DEVICE = SAME70Q21B - -# flash using edbg from https://github.com/ataradov/edbg -# Note: SAME70's GPNVM1 must be set to 1 to boot from flash with -# edbg -t same70 -F w0,1,1 -flash: $(BUILD)/$(PROJECT).bin - edbg --verbose -t same70 -pv -f $< diff --git a/tinyusb/hw/bsp/same70_xplained/hpl_pmc_config.h b/tinyusb/hw/bsp/same70_xplained/hpl_pmc_config.h deleted file mode 100755 index 387aaa5d..00000000 --- a/tinyusb/hw/bsp/same70_xplained/hpl_pmc_config.h +++ /dev/null @@ -1,1053 +0,0 @@ -/* Auto-generated config file hpl_pmc_config.h */ -#ifndef HPL_PMC_CONFIG_H -#define HPL_PMC_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -#include <peripheral_clk_config.h> - -#define CLK_SRC_OPTION_OSC32K 0 -#define CLK_SRC_OPTION_XOSC32K 1 -#define CLK_SRC_OPTION_OSC12M 2 -#define CLK_SRC_OPTION_XOSC20M 3 - -#define CLK_SRC_OPTION_SLCK 0 -#define CLK_SRC_OPTION_MAINCK 1 -#define CLK_SRC_OPTION_PLLACK 2 -#define CLK_SRC_OPTION_UPLLCKDIV 3 -#define CLK_SRC_OPTION_MCK 4 - -#define CLK_SRC_OPTION_UPLLCK 3 - -#define CONF_RC_4M 0 -#define CONF_RC_8M 1 -#define CONF_RC_12M 2 - -#define CONF_XOSC32K_NO_BYPASS 0 -#define CONF_XOSC32K_BYPASS 1 - -#define CONF_XOSC20M_NO_BYPASS 0 -#define CONF_XOSC20M_BYPASS 1 - -// <e> Clock_SLCK configuration -// <i> Indicates whether SLCK configuration is enabled or not -// <id> enable_clk_gen_slck -#ifndef CONF_CLK_SLCK_CONFIG -#define CONF_CLK_SLCK_CONFIG 1 -#endif - -//<h> Clock Generator -// <y> clock generator SLCK source - -// <CLK_SRC_OPTION_OSC32K"> 32kHz High Accuracy Internal Oscillator (OSC32K) - -// <CLK_SRC_OPTION_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) - -// <i> This defines the clock source for SLCK -// <id> clk_gen_slck_oscillator -#ifndef CONF_CLK_GEN_SLCK_SRC -#define CONF_CLK_GEN_SLCK_SRC CLK_SRC_OPTION_OSC32K -#endif - -// <q> Enable Clock_SLCK -// <i> Indicates whether SLCK is enabled or disable -// <id> clk_gen_slck_arch_enable -#ifndef CONF_CLK_SLCK_ENABLE -#define CONF_CLK_SLCK_ENABLE 1 -#endif - -// </h> - -// <h> - -// </h> -// </e>// <e> Clock_MAINCK configuration -// <i> Indicates whether MAINCK configuration is enabled or not -// <id> enable_clk_gen_mainck -#ifndef CONF_CLK_MAINCK_CONFIG -#define CONF_CLK_MAINCK_CONFIG 1 -#endif - -//<h> Clock Generator -// <y> clock generator MAINCK source - -// <CLK_SRC_OPTION_OSC12M"> Embedded 4/8/12MHz RC Oscillator (OSC12M) - -// <CLK_SRC_OPTION_XOSC20M"> External 3-20MHz Oscillator (XOSC20M) - -// <i> This defines the clock source for MAINCK -// <id> clk_gen_mainck_oscillator -#ifndef CONF_CLK_GEN_MAINCK_SRC -#define CONF_CLK_GEN_MAINCK_SRC CLK_SRC_OPTION_XOSC20M -#endif - -// <q> Enable Clock_MAINCK -// <i> Indicates whether MAINCK is enabled or disable -// <id> clk_gen_mainck_arch_enable -#ifndef CONF_CLK_MAINCK_ENABLE -#define CONF_CLK_MAINCK_ENABLE 1 -#endif - -// <q> Enable Main Clock Failure Detection -// <i> Indicates whether Main Clock Failure Detection is enabled or disable. -// <i> The 4/8/12 MHz RC oscillator must be selected as the source of MAINCK. -// <id> clk_gen_cfden_enable -#ifndef CONF_CLK_CFDEN_ENABLE -#define CONF_CLK_CFDEN_ENABLE 0 -#endif - -// </h> - -// <h> - -// </h> -// </e>// <e> Clock_MCKR configuration -// <i> Indicates whether MCKR configuration is enabled or not -// <id> enable_clk_gen_mckr -#ifndef CONF_CLK_MCKR_CONFIG -#define CONF_CLK_MCKR_CONFIG 1 -#endif - -//<h> Clock Generator -// <y> clock generator MCKR source - -// <CLK_SRC_OPTION_SLCK"> Slow Clock (SLCK) - -// <CLK_SRC_OPTION_MAINCK"> Main Clock (MAINCK) - -// <CLK_SRC_OPTION_PLLACK"> PLLA Clock (PLLACK) - -// <CLK_SRC_OPTION_UPLLCKDIV"> UDPLL with Divider (MCKR UPLLDIV2) - -// <i> This defines the clock source for MCKR -// <id> clk_gen_mckr_oscillator -#ifndef CONF_CLK_GEN_MCKR_SRC -#define CONF_CLK_GEN_MCKR_SRC CLK_SRC_OPTION_PLLACK -#endif - -// <q> Enable Clock_MCKR -// <i> Indicates whether MCKR is enabled or disable -// <id> clk_gen_mckr_arch_enable -#ifndef CONF_CLK_MCKR_ENABLE -#define CONF_CLK_MCKR_ENABLE 1 -#endif - -// </h> - -// <h> - -// <o> Master Clock Prescaler -// <0=> 1 -// <1=> 2 -// <2=> 4 -// <3=> 8 -// <4=> 16 -// <5=> 32 -// <6=> 64 -// <7=> 3 -// <i> Select the clock prescaler. -// <id> mckr_presc -#ifndef CONF_MCKR_PRESC -#define CONF_MCKR_PRESC 0 -#endif - -// </h> -// </e>// <e> Clock_MCK configuration -// <i> Indicates whether MCK configuration is enabled or not -// <id> enable_clk_gen_mck -#ifndef CONF_CLK_MCK_CONFIG -#define CONF_CLK_MCK_CONFIG 1 -#endif - -//<h> Clock Generator -// <y> clock generator MCK source - -// <CLK_SRC_OPTION_MCKR"> Master Clock Controller (PMC_MCKR) - -// <i> This defines the clock source for MCK -// <id> clk_gen_mck_oscillator -#ifndef CONF_CLK_GEN_MCK_SRC -#define CONF_CLK_GEN_MCK_SRC CLK_SRC_OPTION_MCKR -#endif - -// </h> - -// <h> - -//<o> Master Clock Controller Divider MCK divider -// <0=> 1 -// <1=> 2 -// <3=> 3 -// <2=> 4 -// <i> Select the master clock divider. -// <id> mck_div -#ifndef CONF_MCK_DIV -#define CONF_MCK_DIV 1 -#endif - -// </h> -// </e>// <e> Clock_SYSTICK configuration -// <i> Indicates whether SYSTICK configuration is enabled or not -// <id> enable_clk_gen_systick -#ifndef CONF_CLK_SYSTICK_CONFIG -#define CONF_CLK_SYSTICK_CONFIG 1 -#endif - -//<h> Clock Generator -// <y> clock generator SYSTICK source - -// <CLK_SRC_OPTION_MCKR"> Master Clock Controller (PMC_MCKR) - -// <i> This defines the clock source for SYSTICK -// <id> clk_gen_systick_oscillator -#ifndef CONF_CLK_GEN_SYSTICK_SRC -#define CONF_CLK_GEN_SYSTICK_SRC CLK_SRC_OPTION_MCKR -#endif - -// </h> - -// <h> - -// <o> Systick clock divider -// <8=> 8 -// <i> Select systick clock divider -// <id> systick_clock_div -#ifndef CONF_SYSTICK_DIV -#define CONF_SYSTICK_DIV 8 -#endif - -// </h> -// </e>// <e> Clock_FCLK configuration -// <i> Indicates whether FCLK configuration is enabled or not -// <id> enable_clk_gen_fclk -#ifndef CONF_CLK_FCLK_CONFIG -#define CONF_CLK_FCLK_CONFIG 1 -#endif - -//<h> Clock Generator -// <y> clock generator FCLK source - -// <CLK_SRC_OPTION_MCKR"> Master Clock Controller (PMC_MCKR) - -// <i> This defines the clock source for FCLK -// <id> clk_gen_fclk_oscillator -#ifndef CONF_CLK_GEN_FCLK_SRC -#define CONF_CLK_GEN_FCLK_SRC CLK_SRC_OPTION_MCKR -#endif - -// </h> - -// <h> - -// </h> -// </e>// <e> Clock_GCLK0 configuration -// <i> Indicates whether GCLK0 configuration is enabled or not -// <id> enable_clk_gen_gclk0 -#ifndef CONF_CLK_GCLK0_CONFIG -#define CONF_CLK_GCLK0_CONFIG 1 -#endif - -//<h> Clock Generator -// <y> clock generator GCLK0 source - -// <CLK_SRC_OPTION_SLCK"> Slow Clock (SLCK) - -// <CLK_SRC_OPTION_MAINCK"> Main Clock (MAINCK) - -// <CLK_SRC_OPTION_UPLLCK"> USB 480M Clock (UPLLCK) - -// <CLK_SRC_OPTION_PLLACK"> PLLA Clock (PLLACK) - -// <CLK_SRC_OPTION_MCK"> Master Clock (MCK) - -// <i> This defines the clock source for GCLK0 -// <id> clk_gen_gclk0_oscillator -#ifndef CONF_CLK_GEN_GCLK0_SRC -#define CONF_CLK_GEN_GCLK0_SRC CLK_SRC_OPTION_MCK -#endif - -// <q> Enable Clock_GCLK0 -// <i> Indicates whether GCLK0 is enabled or disable -// <id> clk_gen_gclk0_arch_enable -#ifndef CONF_CLK_GCLK0_ENABLE -#define CONF_CLK_GCLK0_ENABLE 1 -#endif - -// </h> - -// <h> -// <q> Enable GCLK0 GCLKEN -// <i> Indicates whether GCLK0 GCLKEN is enabled or disable -// <id> gclk0_gclken_enable -#ifndef CONF_GCLK0_GCLKEN_ENABLE -#define CONF_GCLK0_GCLKEN_ENABLE 0 -#endif - -// <o> Generic Clock GCLK0 divider <1-256> -// <i> Select the clock divider (divider = GCLKDIV + 1). -// <id> gclk0_div -#ifndef CONF_GCLK0_DIV -#define CONF_GCLK0_DIV 2 -#endif - -// </h> -// </e>// <e> Clock_GCLK1 configuration -// <i> Indicates whether GCLK1 configuration is enabled or not -// <id> enable_clk_gen_gclk1 -#ifndef CONF_CLK_GCLK1_CONFIG -#define CONF_CLK_GCLK1_CONFIG 1 -#endif - -//<h> Clock Generator -// <y> clock generator GCLK1 source - -// <CLK_SRC_OPTION_SLCK"> Slow Clock (SLCK) - -// <CLK_SRC_OPTION_MAINCK"> Main Clock (MAINCK) - -// <CLK_SRC_OPTION_UPLLCK"> USB 480M Clock (UPLLCK) - -// <CLK_SRC_OPTION_PLLACK"> PLLA Clock (PLLACK) - -// <CLK_SRC_OPTION_MCK"> Master Clock (MCK) - -// <i> This defines the clock source for GCLK1 -// <id> clk_gen_gclk1_oscillator -#ifndef CONF_CLK_GEN_GCLK1_SRC -#define CONF_CLK_GEN_GCLK1_SRC CLK_SRC_OPTION_PLLACK -#endif - -// <q> Enable Clock_GCLK1 -// <i> Indicates whether GCLK1 is enabled or disable -// <id> clk_gen_gclk1_arch_enable -#ifndef CONF_CLK_GCLK1_ENABLE -#define CONF_CLK_GCLK1_ENABLE 1 -#endif - -// </h> - -// <h> -// <q> Enable GCLK1 GCLKEN -// <i> Indicates whether GCLK1 GCLKEN is enabled or disable -// <id> gclk1_gclken_enable -#ifndef CONF_GCLK1_GCLKEN_ENABLE -#define CONF_GCLK1_GCLKEN_ENABLE 0 -#endif - -// <o> Generic Clock GCLK1 divider <1-256> -// <i> Select the clock divider (divider = GCLKDIV + 1). -// <id> gclk1_div -#ifndef CONF_GCLK1_DIV -#define CONF_GCLK1_DIV 3 -#endif - -// </h> -// </e>// <e> Clock_PCK0 configuration -// <i> Indicates whether PCK0 configuration is enabled or not -// <id> enable_clk_gen_pck0 -#ifndef CONF_CLK_PCK0_CONFIG -#define CONF_CLK_PCK0_CONFIG 1 -#endif - -//<h> Clock Generator -// <y> clock generator PCK0 source - -// <CLK_SRC_OPTION_SLCK"> Slow Clock (SLCK) - -// <CLK_SRC_OPTION_MAINCK"> Main Clock (MAINCK) - -// <CLK_SRC_OPTION_UPLLCKDIV"> UDPLL with Divider (MCKR UPLLDIV2) - -// <CLK_SRC_OPTION_PLLACK"> PLLA Clock (PLLACK) - -// <CLK_SRC_OPTION_MCK"> Master Clock (MCK) - -// <i> This defines the clock source for PCK0 -// <id> clk_gen_pck0_oscillator -#ifndef CONF_CLK_GEN_PCK0_SRC -#define CONF_CLK_GEN_PCK0_SRC CLK_SRC_OPTION_MAINCK -#endif - -// <q> Enable Clock_PCK0 -// <i> Indicates whether PCK0 is enabled or disable -// <id> clk_gen_pck0_arch_enable -#ifndef CONF_CLK_PCK0_ENABLE -#define CONF_CLK_PCK0_ENABLE 0 -#endif - -// </h> - -// <h> - -// <o> Programmable Clock Controller Prescaler <1-256> -// <i> Select the clock prescaler (prescaler = PRESC + 1). -// <id> pck0_presc -#ifndef CONF_PCK0_PRESC -#define CONF_PCK0_PRESC 1 -#endif - -// </h> -// </e>// <e> Clock_PCK1 configuration -// <i> Indicates whether PCK1 configuration is enabled or not -// <id> enable_clk_gen_pck1 -#ifndef CONF_CLK_PCK1_CONFIG -#define CONF_CLK_PCK1_CONFIG 1 -#endif - -//<h> Clock Generator -// <y> clock generator PCK1 source - -// <CLK_SRC_OPTION_SLCK"> Slow Clock (SLCK) - -// <CLK_SRC_OPTION_MAINCK"> Main Clock (MAINCK) - -// <CLK_SRC_OPTION_UPLLCKDIV"> UDPLL with Divider (MCKR UPLLDIV2) - -// <CLK_SRC_OPTION_PLLACK"> PLLA Clock (PLLACK) - -// <CLK_SRC_OPTION_MCK"> Master Clock (MCK) - -// <i> This defines the clock source for PCK1 -// <id> clk_gen_pck1_oscillator -#ifndef CONF_CLK_GEN_PCK1_SRC -#define CONF_CLK_GEN_PCK1_SRC CLK_SRC_OPTION_MAINCK -#endif - -// <q> Enable Clock_PCK1 -// <i> Indicates whether PCK1 is enabled or disable -// <id> clk_gen_pck1_arch_enable -#ifndef CONF_CLK_PCK1_ENABLE -#define CONF_CLK_PCK1_ENABLE 0 -#endif - -// </h> - -// <h> - -// <o> Programmable Clock Controller Prescaler <1-256> -// <i> Select the clock prescaler (prescaler = PRESC + 1). -// <id> pck1_presc -#ifndef CONF_PCK1_PRESC -#define CONF_PCK1_PRESC 2 -#endif - -// </h> -// </e>// <e> Clock_PCK2 configuration -// <i> Indicates whether PCK2 configuration is enabled or not -// <id> enable_clk_gen_pck2 -#ifndef CONF_CLK_PCK2_CONFIG -#define CONF_CLK_PCK2_CONFIG 1 -#endif - -//<h> Clock Generator -// <y> clock generator PCK2 source - -// <CLK_SRC_OPTION_SLCK"> Slow Clock (SLCK) - -// <CLK_SRC_OPTION_MAINCK"> Main Clock (MAINCK) - -// <CLK_SRC_OPTION_UPLLCKDIV"> UDPLL with Divider (MCKR UPLLDIV2) - -// <CLK_SRC_OPTION_PLLACK"> PLLA Clock (PLLACK) - -// <CLK_SRC_OPTION_MCK"> Master Clock (MCK) - -// <i> This defines the clock source for PCK2 -// <id> clk_gen_pck2_oscillator -#ifndef CONF_CLK_GEN_PCK2_SRC -#define CONF_CLK_GEN_PCK2_SRC CLK_SRC_OPTION_MAINCK -#endif - -// <q> Enable Clock_PCK2 -// <i> Indicates whether PCK2 is enabled or disable -// <id> clk_gen_pck2_arch_enable -#ifndef CONF_CLK_PCK2_ENABLE -#define CONF_CLK_PCK2_ENABLE 0 -#endif - -// </h> - -// <h> - -// <o> Programmable Clock Controller Prescaler <1-256> -// <i> Select the clock prescaler (prescaler = PRESC + 1). -// <id> pck2_presc -#ifndef CONF_PCK2_PRESC -#define CONF_PCK2_PRESC 3 -#endif - -// </h> -// </e>// <e> Clock_PCK3 configuration -// <i> Indicates whether PCK3 configuration is enabled or not -// <id> enable_clk_gen_pck3 -#ifndef CONF_CLK_PCK3_CONFIG -#define CONF_CLK_PCK3_CONFIG 1 -#endif - -//<h> Clock Generator -// <y> clock generator PCK3 source - -// <CLK_SRC_OPTION_SLCK"> Slow Clock (SLCK) - -// <CLK_SRC_OPTION_MAINCK"> Main Clock (MAINCK) - -// <CLK_SRC_OPTION_UPLLCKDIV"> UDPLL with Divider (MCKR UPLLDIV2) - -// <CLK_SRC_OPTION_PLLACK"> PLLA Clock (PLLACK) - -// <CLK_SRC_OPTION_MCK"> Master Clock (MCK) - -// <i> This defines the clock source for PCK3 -// <id> clk_gen_pck3_oscillator -#ifndef CONF_CLK_GEN_PCK3_SRC -#define CONF_CLK_GEN_PCK3_SRC CLK_SRC_OPTION_MAINCK -#endif - -// <q> Enable Clock_PCK3 -// <i> Indicates whether PCK3 is enabled or disable -// <id> clk_gen_pck3_arch_enable -#ifndef CONF_CLK_PCK3_ENABLE -#define CONF_CLK_PCK3_ENABLE 0 -#endif - -// </h> - -// <h> - -// <o> Programmable Clock Controller Prescaler <1-256> -// <i> Select the clock prescaler (prescaler = PRESC + 1). -// <id> pck3_presc -#ifndef CONF_PCK3_PRESC -#define CONF_PCK3_PRESC 4 -#endif - -// </h> -// </e>// <e> Clock_PCK4 configuration -// <i> Indicates whether PCK4 configuration is enabled or not -// <id> enable_clk_gen_pck4 -#ifndef CONF_CLK_PCK4_CONFIG -#define CONF_CLK_PCK4_CONFIG 1 -#endif - -//<h> Clock Generator -// <y> clock generator PCK4 source - -// <CLK_SRC_OPTION_SLCK"> Slow Clock (SLCK) - -// <CLK_SRC_OPTION_MAINCK"> Main Clock (MAINCK) - -// <CLK_SRC_OPTION_UPLLCKDIV"> UDPLL with Divider (MCKR UPLLDIV2) - -// <CLK_SRC_OPTION_PLLACK"> PLLA Clock (PLLACK) - -// <CLK_SRC_OPTION_MCK"> Master Clock (MCK) - -// <i> This defines the clock source for PCK4 -// <id> clk_gen_pck4_oscillator -#ifndef CONF_CLK_GEN_PCK4_SRC -#define CONF_CLK_GEN_PCK4_SRC CLK_SRC_OPTION_MAINCK -#endif - -// <q> Enable Clock_PCK4 -// <i> Indicates whether PCK4 is enabled or disable -// <id> clk_gen_pck4_arch_enable -#ifndef CONF_CLK_PCK4_ENABLE -#define CONF_CLK_PCK4_ENABLE 0 -#endif - -// </h> - -// <h> - -// <o> Programmable Clock Controller Prescaler <1-256> -// <i> Select the clock prescaler (prescaler = PRESC + 1). -// <id> pck4_presc -#ifndef CONF_PCK4_PRESC -#define CONF_PCK4_PRESC 5 -#endif - -// </h> -// </e>// <e> Clock_PCK5 configuration -// <i> Indicates whether PCK5 configuration is enabled or not -// <id> enable_clk_gen_pck5 -#ifndef CONF_CLK_PCK5_CONFIG -#define CONF_CLK_PCK5_CONFIG 1 -#endif - -//<h> Clock Generator -// <y> clock generator PCK5 source - -// <CLK_SRC_OPTION_SLCK"> Slow Clock (SLCK) - -// <CLK_SRC_OPTION_MAINCK"> Main Clock (MAINCK) - -// <CLK_SRC_OPTION_UPLLCKDIV"> UDPLL with Divider (MCKR UPLLDIV2) - -// <CLK_SRC_OPTION_PLLACK"> PLLA Clock (PLLACK) - -// <CLK_SRC_OPTION_MCK"> Master Clock (MCK) - -// <i> This defines the clock source for PCK5 -// <id> clk_gen_pck5_oscillator -#ifndef CONF_CLK_GEN_PCK5_SRC -#define CONF_CLK_GEN_PCK5_SRC CLK_SRC_OPTION_MAINCK -#endif - -// <q> Enable Clock_PCK5 -// <i> Indicates whether PCK5 is enabled or disable -// <id> clk_gen_pck5_arch_enable -#ifndef CONF_CLK_PCK5_ENABLE -#define CONF_CLK_PCK5_ENABLE 0 -#endif - -// </h> - -// <h> - -// <o> Programmable Clock Controller Prescaler <1-256> -// <i> Select the clock prescaler (prescaler = PRESC + 1). -// <id> pck5_presc -#ifndef CONF_PCK5_PRESC -#define CONF_PCK5_PRESC 6 -#endif - -// </h> -// </e>// <e> Clock_PCK6 configuration -// <i> Indicates whether PCK6 configuration is enabled or not -// <id> enable_clk_gen_pck6 -#ifndef CONF_CLK_PCK6_CONFIG -#define CONF_CLK_PCK6_CONFIG 1 -#endif - -//<h> Clock Generator -// <y> clock generator PCK6 source - -// <CLK_SRC_OPTION_SLCK"> Slow Clock (SLCK) - -// <CLK_SRC_OPTION_MAINCK"> Main Clock (MAINCK) - -// <CLK_SRC_OPTION_UPLLCKDIV"> UDPLL with Divider (MCKR UPLLDIV2) - -// <CLK_SRC_OPTION_PLLACK"> PLLA Clock (PLLACK) - -// <CLK_SRC_OPTION_MCK"> Master Clock (MCK) - -// <i> This defines the clock source for PCK6 -// <id> clk_gen_pck6_oscillator -#ifndef CONF_CLK_GEN_PCK6_SRC -#define CONF_CLK_GEN_PCK6_SRC CLK_SRC_OPTION_MAINCK -#endif - -// <q> Enable Clock_PCK6 -// <i> Indicates whether PCK6 is enabled or disable -// <id> clk_gen_pck6_arch_enable -#ifndef CONF_CLK_PCK6_ENABLE -#define CONF_CLK_PCK6_ENABLE 0 -#endif - -// </h> - -// <h> - -// <o> Programmable Clock Controller Prescaler <1-256> -// <i> Select the clock prescaler (prescaler = PRESC + 1). -// <id> pck6_presc -#ifndef CONF_PCK6_PRESC -#define CONF_PCK6_PRESC 7 -#endif - -// </h> -// </e>// <e> Clock_USB_480M configuration -// <i> Indicates whether USB_480M configuration is enabled or not -// <id> enable_clk_gen_usb_480m -#ifndef CONF_CLK_USB_480M_CONFIG -#define CONF_CLK_USB_480M_CONFIG 1 -#endif - -//<h> Clock Generator -// <y> clock generator USB_480M source - -// <CLK_SRC_OPTION_UPLLCK"> USB 480M Clock (UPLLCK) - -// <i> This defines the clock source for USB_480M -// <id> clk_gen_usb_480m_oscillator -#ifndef CONF_CLK_GEN_USB_480M_SRC -#define CONF_CLK_GEN_USB_480M_SRC CLK_SRC_OPTION_UPLLCK -#endif - -// </h> - -// <h> - -// </h> -// </e>// <e> Clock_USB_48M configuration -// <i> Indicates whether USB_48M configuration is enabled or not -// <id> enable_clk_gen_usb_48m -#ifndef CONF_CLK_USB_48M_CONFIG -#define CONF_CLK_USB_48M_CONFIG 1 -#endif - -//<h> Clock Generator -// <y> clock generator USB_48M source - -// <CLK_SRC_OPTION_PLLACK"> PLLA Clock (PLLACK) - -// <CLK_SRC_OPTION_UPLLCKDIV"> UDPLL with Divider (MCKR UPLLDIV2) - -// <i> This defines the clock source for USB_48M -// <id> clk_gen_usb_48m_oscillator -#ifndef CONF_CLK_GEN_USB_48M_SRC -#define CONF_CLK_GEN_USB_48M_SRC CLK_SRC_OPTION_UPLLCKDIV -#endif - -// <q> Enable Clock_USB_48M -// <i> Indicates whether USB_48M is enabled or disable -// <id> clk_gen_usb_48m_arch_enable -#ifndef CONF_CLK_USB_48M_ENABLE -#define CONF_CLK_USB_48M_ENABLE 1 -#endif - -// </h> - -// <h> - -// <o> USB Clock Controller Divider <1-16> -// <i> Select the USB clock divider (divider = USBDIV + 1). -// <id> usb_48m_div -#ifndef CONF_USB_48M_DIV -#define CONF_USB_48M_DIV 5 -#endif - -// </h> -// </e>// <e> Clock_SLCK2 configuration -// <i> Indicates whether SLCK2 configuration is enabled or not -// <id> enable_clk_gen_slck2 -#ifndef CONF_CLK_SLCK2_CONFIG -#define CONF_CLK_SLCK2_CONFIG 1 -#endif - -//<h> Clock Generator -// <y> clock generator SLCK2 source - -// <CLK_SRC_OPTION_SLCK"> Slow Clock (SLCK) - -// <i> This defines the clock source for SLCK2 -// <id> clk_gen_slck2_oscillator -#ifndef CONF_CLK_GEN_SLCK2_SRC -#define CONF_CLK_GEN_SLCK2_SRC CLK_SRC_OPTION_SLCK -#endif - -// </h> - -// <h> - -// </h> -// </e> - -// <e> System Configuration -// <i> Indicates whether configuration for system is enabled or not -// <id> enable_hclk_clock -#ifndef CONF_SYSTEM_CONFIG -#define CONF_SYSTEM_CONFIG 1 -#endif - -// <h> Processor Clock Settings -// <y> Processor Clock source -// <MCKR"> Master Clock Controller (PMC_MCKR) -// <i> This defines the clock source for the HCLK (Processor clock) -// <id> hclk_clock_source -#ifndef CONF_HCLK_SRC -#define CONF_HCLK_SRC MCKR -#endif - -// <o> Flash Wait State -// <0=> 1 cycle -// <1=> 2 cycles -// <2=> 3 cycles -// <3=> 4 cycles -// <4=> 5 cycles -// <5=> 6 cycles -// <6=> 7 cycles -// <i> This field defines the number of wait states for read and write operations. -// <id> efc_fws -#ifndef CONF_EFC_WAIT_STATE -#define CONF_EFC_WAIT_STATE 5 -#endif - -// </h> -// </e> - -// <e> SysTick Clock -// <id> enable_systick_clk_clock -#ifndef CONF_SYSTICK_CLK_CONFIG -#define CONF_SYSTICK_CLK_CONFIG 1 -#endif - -// <y> SysTick Clock source -// <MCKR"> Master Clock Controller (PMC_MCKR) -// <i> This defines the clock source for the SysTick Clock -// <id> systick_clk_clock_source -#ifndef CONF_SYSTICK_CLK_SRC -#define CONF_SYSTICK_CLK_SRC MCKR -#endif - -// <o> SysTick Clock Divider -// <8=> 8 -// <i> Fixed to 8 if Systick is not using Processor clock -// <id> systick_clk_clock_div -#ifndef CONF_SYSTICK_CLK_DIV -#define CONF_SYSTICK_CLK_DIV 8 -#endif - -// </e> - -// <e> OSC32K Oscillator Configuration -// <i> Indicates whether configuration for OSC32K is enabled or not -// <id> enable_osc32k -#ifndef CONF_OSC32K_CONFIG -#define CONF_OSC32K_CONFIG 1 -#endif - -// <h> OSC32K Oscillator Control -// <q> OSC32K Oscillator Enable -// <i> Indicates whether OSC32K Oscillator is enabled or not -// <id> osc32k_arch_enable -#ifndef CONF_OSC32K_ENABLE -#define CONF_OSC32K_ENABLE 0 -#endif -// </h> -// </e> - -// <e> XOSC32K Oscillator Configuration -// <i> Indicates whether configuration for XOSC32K is enabled or not -// <id> enable_xosc32k -#ifndef CONF_XOSC32K_CONFIG -#define CONF_XOSC32K_CONFIG 0 -#endif - -// <h> XOSC32K Oscillator Control -// <y> Oscillator Bypass Select -// <CONF_XOSC32K_NO_BYPASS"> The 32kHz crystal oscillator is not bypassed. -// <CONF_XOSC32K_BYPASS"> The 32kHz crystal oscillator is bypassed. -// <i> Indicates whether XOSC32K is bypassed. -// <id> xosc32k_bypass -#ifndef CONF_XOSC32K -#define CONF_XOSC32K CONF_XOSC32K_NO_BYPASS -#endif - -// <q> XOSC32K Oscillator Enable -// <i> Indicates whether XOSC32K Oscillator is enabled or not -// <id> xosc32k_arch_enable -#ifndef CONF_XOSC32K_ENABLE -#define CONF_XOSC32K_ENABLE 0 -#endif -// </h> -// </e> - -// <e> OSC12M Oscillator Configuration -// <i> Indicates whether configuration for OSC12M is enabled or not -// <id> enable_osc12m -#ifndef CONF_OSC12M_CONFIG -#define CONF_OSC12M_CONFIG 0 -#endif - -// <h> OSC12M Oscillator Control -// <q> OSC12M Oscillator Enable -// <i> Indicates whether OSC12M Oscillator is enabled or not. -// <id> osc12m_arch_enable -#ifndef CONF_OSC12M_ENABLE -#define CONF_OSC12M_ENABLE 0 -#endif - -// <o> OSC12M selector -// <0=> 4000000 -// <1=> 8000000 -// <2=> 12000000 -// <i> Select the frequency of embedded fast RC oscillator. -// <id> osc12m_selector -#ifndef CONF_OSC12M_SELECTOR -#define CONF_OSC12M_SELECTOR 2 -#endif -// </h> -// </e> - -// <e> XOSC20M Oscillator Configuration -// <i> Indicates whether configuration for XOSC20M is enabled or not. -// <id> enable_xosc20m -#ifndef CONF_XOSC20M_CONFIG -#define CONF_XOSC20M_CONFIG 1 -#endif - -// <h> XOSC20M Oscillator Control -// <o> XOSC20M selector <3000000-20000000> -// <i> Select the frequency of crystal or ceramic resonator oscillator. -// <id> xosc20m_selector -#ifndef CONF_XOSC20M_SELECTOR -#define CONF_XOSC20M_SELECTOR 12000000 -#endif - -// <o> Start up time for the external oscillator (ms): <0-256> -// <i> Select start-up time. -// <id> xosc20m_startup_time -#ifndef CONF_XOSC20M_STARTUP_TIME -#define CONF_XOSC20M_STARTUP_TIME 62 -#endif - -// <y> Oscillator Bypass Select -// <CONF_XOSC20M_NO_BYPASS"> The external crystal oscillator is not bypassed. -// <CONF_XOSC20M_BYPASS"> The external crystal oscillator is bypassed. -// <i> Indicates whether XOSC20M is bypassed. -// <id> xosc20m_bypass -#ifndef CONF_XOSC20M -#define CONF_XOSC20M CONF_XOSC20M_NO_BYPASS -#endif - -// <q> XOSC20M Oscillator Enable -// <i> Indicates whether XOSC20M Oscillator is enabled or not -// <id> xosc20m_arch_enable -#ifndef CONF_XOSC20M_ENABLE -#define CONF_XOSC20M_ENABLE 1 -#endif -// </h> -// </e> - -// <e> PLLACK Oscillator Configuration -// <i> Indicates whether configuration for PLLACK is enabled or not -// <id> enable_pllack -#ifndef CONF_PLLACK_CONFIG -#define CONF_PLLACK_CONFIG 1 -#endif - -// <y> PLLACK Reference Clock Source -// <MAINCK"> Main Clock (MAINCK) -// <i> Select the clock source. -// <id> pllack_ref_clock -#ifndef CONF_PLLACK_CLK -#define CONF_PLLACK_CLK MAINCK -#endif - -// <h> PLLACK Oscillator Control -// <q> PLLACK Oscillator Enable -// <i> Indicates whether PLLACK Oscillator is enabled or not -// <id> pllack_arch_enable -#ifndef CONF_PLLACK_ENABLE -#define CONF_PLLACK_ENABLE 1 -#endif - -// <o> PLLA Frontend Divider (DIVA) <1-255> -// <i> Select the clock divider -// <id> pllack_div -#ifndef CONF_PLLACK_DIV -#define CONF_PLLACK_DIV 1 -#endif - -// <o> PLLACK Muliplier <1-62> -// <i> Indicates PLLA multiplier (multiplier = MULA + 1). -// <id> pllack_mul -#ifndef CONF_PLLACK_MUL -#define CONF_PLLACK_MUL 25 -#endif -// </h> -// </e> - -// <e> UPLLCK Oscillator Configuration -// <i> Indicates whether configuration for UPLLCK is enabled or not -// <id> enable_upllck -#ifndef CONF_UPLLCK_CONFIG -#define CONF_UPLLCK_CONFIG 1 -#endif - -// <y> UPLLCK Reference Clock Source -// <XOSC20M"> External 3-20MHz Oscillator (XOSC20M) -// <i> Select the clock source,only when the input frequency is 12M or 16M, the upllck output is 480M. -// <id> upllck_ref_clock -#ifndef CONF_UPLLCK_CLK -#define CONF_UPLLCK_CLK XOSC20M -#endif - -// <h> UPLLCK Oscillator Control -// <q> UPLLCK Oscillator Enable -// <i> Indicates whether UPLLCK Oscillator is enabled or not -// <id> upllck_arch_enable -#ifndef CONF_UPLLCK_ENABLE -#define CONF_UPLLCK_ENABLE 1 -#endif -// </h> -// </e> - -// <e> UPLLCKDIV Oscillator Configuration -// <i> Indicates whether configuration for UPLLCKDIV is enabled or not -// <id> enable_upllckdiv -#ifndef CONF_UPLLCKDIV_CONFIG -#define CONF_UPLLCKDIV_CONFIG 1 -#endif - -// <y> UPLLCKDIV Reference Clock Source -// <UPLLCK"> USB 480M Clock (UPLLCK) -// <i> Select the clock source. -// <id> upllckdiv_ref_clock -#ifndef CONF_UPLLCKDIV_CLK -#define CONF_UPLLCKDIV_CLK UPLLCK -#endif - -// <h> UPLLCKDIV Oscillator Control -// <o> UPLLCKDIV Clock Divider -// <0=> 1 -// <1=> 2 -// <i> Select the clock divider. -// <id> upllckdiv_div -#ifndef CONF_UPLLCKDIV_DIV -#define CONF_UPLLCKDIV_DIV 1 -#endif -// </h> -// </e> - -// <e> MCK/8 -// <id> enable_mck_div_8 -#ifndef CONF_MCK_DIV_8_CONFIG -#define CONF_MCK_DIV_8_CONFIG 0 -#endif - -// <o> MCK/8 Source -// <0=> Master Clock (MCK) -// <id> mck_div_8_src -#ifndef CONF_MCK_DIV_8_SRC -#define CONF_MCK_DIV_8_SRC 0 -#endif -// </e> - -// <e> External Clock Input Configuration -// <id> enable_dummy_ext -#ifndef CONF_DUMMY_EXT_CONFIG -#define CONF_DUMMY_EXT_CONFIG 1 -#endif - -// <o> External Clock Input Source -// <i> All here are dummy values -// <i> Refer to the peripherals settings for actual input information -// <0=> Specific clock input from specific pin -// <id> dummy_ext_src -#ifndef CONF_DUMMY_EXT_SRC -#define CONF_DUMMY_EXT_SRC 0 -#endif -// </e> - -// <e> External Clock Configuration -// <id> enable_dummy_ext_clk -#ifndef CONF_DUMMY_EXT_CLK_CONFIG -#define CONF_DUMMY_EXT_CLK_CONFIG 1 -#endif - -// <o> External Clock Source -// <i> All here are dummy values -// <i> Refer to the peripherals settings for actual input information -// <0=> External Clock Input -// <id> dummy_ext_clk_src -#ifndef CONF_DUMMY_EXT_CLK_SRC -#define CONF_DUMMY_EXT_CLK_SRC 0 -#endif -// </e> - -// <<< end of configuration section >>> - -#endif // HPL_PMC_CONFIG_H diff --git a/tinyusb/hw/bsp/same70_xplained/hpl_usart_config.h b/tinyusb/hw/bsp/same70_xplained/hpl_usart_config.h deleted file mode 100755 index 50ca3f15..00000000 --- a/tinyusb/hw/bsp/same70_xplained/hpl_usart_config.h +++ /dev/null @@ -1,215 +0,0 @@ -/* Auto-generated config file hpl_usart_config.h */ -#ifndef HPL_USART_CONFIG_H -#define HPL_USART_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -#include <peripheral_clk_config.h> - -#ifndef CONF_USART_1_ENABLE -#define CONF_USART_1_ENABLE 1 -#endif - -// <h> Basic Configuration - -// <o> Frame parity -// <0x0=>Even parity -// <0x1=>Odd parity -// <0x2=>Parity forced to 0 -// <0x3=>Parity forced to 1 -// <0x4=>No parity -// <i> Parity bit mode for USART frame -// <id> usart_parity -#ifndef CONF_USART_1_PARITY -#define CONF_USART_1_PARITY 0x4 -#endif - -// <o> Character Size -// <0x0=>5 bits -// <0x1=>6 bits -// <0x2=>7 bits -// <0x3=>8 bits -// <i> Data character size in USART frame -// <id> usart_character_size -#ifndef CONF_USART_1_CHSIZE -#define CONF_USART_1_CHSIZE 0x3 -#endif - -// <o> Stop Bit -// <0=>1 stop bit -// <1=>1.5 stop bits -// <2=>2 stop bits -// <i> Number of stop bits in USART frame -// <id> usart_stop_bit -#ifndef CONF_USART_1_SBMODE -#define CONF_USART_1_SBMODE 0 -#endif - -// <o> Clock Output Select -// <0=>The USART does not drive the SCK pin -// <1=>The USART drives the SCK pin if USCLKS does not select the external clock SCK -// <i> Clock Output Select in USART sck, if in usrt master mode, please drive SCK. -// <id> usart_clock_output_select -#ifndef CONF_USART_1_CLKO -#define CONF_USART_1_CLKO 0 -#endif - -// <o> Baud rate <1-3000000> -// <i> USART baud rate setting -// <id> usart_baud_rate -#ifndef CONF_USART_1_BAUD -#define CONF_USART_1_BAUD 9600 -#endif - -// </h> - -// <e> Advanced configuration -// <id> usart_advanced -#ifndef CONF_USART_1_ADVANCED_CONFIG -#define CONF_USART_1_ADVANCED_CONFIG 0 -#endif - -// <o> Channel Mode -// <0=>Normal Mode -// <1=>Automatic Echo -// <2=>Local Loopback -// <3=>Remote Loopback -// <i> Channel mode in USART frame -// <id> usart_channel_mode -#ifndef CONF_USART_1_CHMODE -#define CONF_USART_1_CHMODE 0 -#endif - -// <q> 9 bits character enable -// <i> Enable 9 bits character, this has high priority than 5/6/7/8 bits. -// <id> usart_9bits_enable -#ifndef CONF_USART_1_MODE9 -#define CONF_USART_1_MODE9 0 -#endif - -// <o> Variable Sync -// <0=>User defined configuration -// <1=>sync field is updated when a character is written into US_THR -// <i> Variable Synchronization of Command/Data Sync Start Frarm Delimiter -// <id> variable_sync -#ifndef CONF_USART_1_VAR_SYNC -#define CONF_USART_1_VAR_SYNC 0 -#endif - -// <o> Oversampling Mode -// <0=>16 Oversampling -// <1=>8 Oversampling -// <i> Oversampling Mode in UART mode -// <id> usart__oversampling_mode -#ifndef CONF_USART_1_OVER -#define CONF_USART_1_OVER 0 -#endif - -// <o> Inhibit Non Ack -// <0=>The NACK is generated -// <1=>The NACK is not generated -// <i> Inhibit Non Acknowledge -// <id> usart__inack -#ifndef CONF_USART_1_INACK -#define CONF_USART_1_INACK 1 -#endif - -// <o> Disable Successive NACK -// <0=>NACK is sent on the ISO line as soon as a parity error occurs -// <1=>Many parity errors generate a NACK on the ISO line -// <i> Disable Successive NACK -// <id> usart_dsnack -#ifndef CONF_USART_1_DSNACK -#define CONF_USART_1_DSNACK 0 -#endif - -// <o> Inverted Data -// <0=>Data isn't inverted, nomal mode -// <1=>Data is inverted -// <i> Inverted Data -// <id> usart_invdata -#ifndef CONF_USART_1_INVDATA -#define CONF_USART_1_INVDATA 0 -#endif - -// <o> Maximum Number of Automatic Iteration <0-7> -// <i> Defines the maximum number of iterations in mode ISO7816, protocol T = 0. -// <id> usart_max_iteration -#ifndef CONF_USART_1_MAX_ITERATION -#define CONF_USART_1_MAX_ITERATION 0 -#endif - -// <q> Receive Line Filter enable -// <i> whether the USART filters the receive line using a three-sample filter -// <id> usart_receive_filter_enable -#ifndef CONF_USART_1_FILTER -#define CONF_USART_1_FILTER 0 -#endif - -// <q> Manchester Encoder/Decoder Enable -// <i> whether the USART Manchester Encoder/Decoder -// <id> usart_manchester_filter_enable -#ifndef CONF_USART_1_MAN -#define CONF_USART_1_MAN 0 -#endif - -// <o> Manchester Synchronization Mode -// <0=>The Manchester start bit is a 0 to 1 transition -// <1=>The Manchester start bit is a 1 to 0 transition -// <i> Manchester Synchronization Mode -// <id> usart_manchester_synchronization_mode -#ifndef CONF_USART_1_MODSYNC -#define CONF_USART_1_MODSYNC 0 -#endif - -// <o> Start Frame Delimiter Selector -// <0=>Start frame delimiter is COMMAND or DATA SYNC -// <1=>Start frame delimiter is one bit -// <i> Start Frame Delimiter Selector -// <id> usart_start_frame_delimiter -#ifndef CONF_USART_1_ONEBIT -#define CONF_USART_1_ONEBIT 0 -#endif - -// <o> Fractional Part <0-7> -// <i> Fractional part of the baud rate if baud rate generator is in fractional mode -// <id> usart_arch_fractional -#ifndef CONF_USART_1_FRACTIONAL -#define CONF_USART_1_FRACTIONAL 0x0 -#endif - -// <o> Data Order -// <0=>LSB is transmitted first -// <1=>MSB is transmitted first -// <i> Data order of the data bits in the frame -// <id> usart_arch_msbf -#ifndef CONF_USART_1_MSBF -#define CONF_USART_1_MSBF 0 -#endif - -// </e> - -#define CONF_USART_1_MODE 0x0 - -// Calculate BAUD register value in UART mode -#if CONF_USART1_CK_SRC < 3 -#ifndef CONF_USART_1_BAUD_CD -#define CONF_USART_1_BAUD_CD ((CONF_USART1_FREQUENCY) / CONF_USART_1_BAUD / 8 / (2 - CONF_USART_1_OVER)) -#endif -#ifndef CONF_USART_1_BAUD_FP -#define CONF_USART_1_BAUD_FP \ - ((CONF_USART1_FREQUENCY) / CONF_USART_1_BAUD / (2 - CONF_USART_1_OVER) - 8 * CONF_USART_1_BAUD_CD) -#endif -#elif CONF_USART1_CK_SRC == 3 -// No division is active. The value written in US_BRGR has no effect. -#ifndef CONF_USART_1_BAUD_CD -#define CONF_USART_1_BAUD_CD 1 -#endif -#ifndef CONF_USART_1_BAUD_FP -#define CONF_USART_1_BAUD_FP 1 -#endif -#endif - -// <<< end of configuration section >>> - -#endif // HPL_USART_CONFIG_H diff --git a/tinyusb/hw/bsp/same70_xplained/hpl_xdmac_config.h b/tinyusb/hw/bsp/same70_xplained/hpl_xdmac_config.h deleted file mode 100755 index a3d62c6f..00000000 --- a/tinyusb/hw/bsp/same70_xplained/hpl_xdmac_config.h +++ /dev/null @@ -1,4400 +0,0 @@ -/* Auto-generated config file hpl_xdmac_config.h */ -#ifndef HPL_XDMAC_CONFIG_H -#define HPL_XDMAC_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// <e> XDMAC enable -// <i> Indicates whether xdmac is enabled or not -// <id> xdmac_enable -#ifndef CONF_DMA_ENABLE -#define CONF_DMA_ENABLE 0 -#endif - -// <e> Channel 0 settings -// <id> dmac_channel_0_settings -#ifndef CONF_DMAC_CHANNEL_0_SETTINGS -#define CONF_DMAC_CHANNEL_0_SETTINGS 0 -#endif - -// <o> Burst Size -// <0x0=> 1 burst size -// <0x1=> 4 burst size -// <0x2=> 8 burst size -// <0x3=> 16 burst size -// <i> Define the memory burst size -// <id> dmac_burstsize_0 -#ifndef CONF_DMAC_BURSTSIZE_0 -#define CONF_DMAC_BURSTSIZE_0 0x0 -#endif - -// <o> Chunk Size -// <0x0=> 1 data transferred -// <0x1=> 2 data transferred -// <0x2=> 4 data transferred -// <0x3=> 8 data transferred -// <0x4=> 16 data transferred -// <i> Define the peripheral chunk size -// <id> dmac_chunksize_0 -#ifndef CONF_DMAC_CHUNKSIZE_0 -#define CONF_DMAC_CHUNKSIZE_0 0x0 -#endif - -// <o> Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// <i> Defines the size of one beat -// <id> dmac_beatsize_0 -#ifndef CONF_DMAC_BEATSIZE_0 -#define CONF_DMAC_BEATSIZE_0 0x0 -#endif - -// <o> Source Interface Identifier -// <0x0=> AHB_IF0 -// <0x1=> AHB_IF1 -// <i> Define the data is read through the system bus interface 0 or 1 -// <id> dma_src_interface_0 -#ifndef CONF_DMAC_SRC_INTERFACE_0 -#define CONF_DMAC_SRC_INTERFACE_0 0x0 -#endif - -// <o> Destination Interface Identifier -// <0x0=> AHB_IF0 -// <0x1=> AHB_IF1 -// <i> Define the data is written through the system bus interface 0 or 1 -// <id> dma_des_interface_0 -#ifndef CONF_DMAC_DES_INTERFACE_0 -#define CONF_DMAC_DES_INTERFACE_0 0x0 -#endif - -// <q> Source Address Increment -// <i> Indicates whether the source address incremented as beat size or not -// <id> dmac_srcinc_0 -#ifndef CONF_DMAC_SRCINC_0 -#define CONF_DMAC_SRCINC_0 0 -#endif - -// <q> Destination Address Increment -// <i> Indicates whether the destination address incremented as beat size or not -// <id> dmac_dstinc_0 -#ifndef CONF_DMAC_DSTINC_0 -#define CONF_DMAC_DSTINC_0 0 -#endif - -// <o> Transfer Type -// <0x0=> Memory to Memory Transfer -// <0x1=> Peripheral to Memory Transfer -// <0x2=> Memory to Peripheral Transfer -// <i> Define the data transfer type -// <id> dma_trans_type_0 -#ifndef CONF_DMAC_TRANS_TYPE_0 -#define CONF_DMAC_TRANS_TYPE_0 0x0 -#endif - -// <o> Trigger source -// <0xFF=> Software Trigger -// <0x00=> HSMCI TX/RX Trigger -// <0x01=> SPI0 TX Trigger -// <0x02=> SPI0 RX Trigger -// <0x03=> SPI1 TX Trigger -// <0x04=> SPI1 RX Trigger -// <0x05=> QSPI TX Trigger -// <0x06=> QSPI RX Trigger -// <0x07=> USART0 TX Trigger -// <0x08=> USART0 RX Trigger -// <0x09=> USART1 TX Trigger -// <0x0A=> USART1 RX Trigger -// <0x0B=> USART2 TX Trigger -// <0x0C=> USART2 RX Trigger -// <0x0D=> PWM0 TX Trigger -// <0x0E=> TWIHS0 TX Trigger -// <0x0F=> TWIHS0 RX Trigger -// <0x10=> TWIHS1 TX Trigger -// <0x11=> TWIHS1 RX Trigger -// <0x12=> TWIHS2 TX Trigger -// <0x13=> TWIHS2 RX Trigger -// <0x14=> UART0 TX Trigger -// <0x15=> UART0 RX Trigger -// <0x16=> UART1 TX Trigger -// <0x17=> UART1 RX Trigger -// <0x18=> UART2 TX Trigger -// <0x19=> UART2 RX Trigger -// <0x1A=> UART3 TX Trigger -// <0x1B=> UART3 RX Trigger -// <0x1C=> UART4 TX Trigger -// <0x1D=> UART4 RX Trigger -// <0x1E=> DACC TX Trigger -// <0x20=> SSC TX Trigger -// <0x21=> SSC RX Trigger -// <0x22=> PIOA RX Trigger -// <0x23=> AFEC0 RX Trigger -// <0x24=> AFEC1 RX Trigger -// <0x25=> AES TX Trigger -// <0x26=> AES RX Trigger -// <0x27=> PWM1 TX Trigger -// <0x28=> TC0 RX Trigger -// <0x29=> TC3 RX Trigger -// <0x2A=> TC6 RX Trigger -// <0x2B=> TC9 RX Trigger -// <0x2C=> I2SC0 TX Left Trigger -// <0x2D=> I2SC0 RX Left Trigger -// <0x2E=> I2SC1 TX Left Trigger -// <0x2F=> I2SC1 RX Left Trigger -// <0x30=> I2SC0 TX Right Trigger -// <0x31=> I2SC0 RX Right Trigger -// <0x32=> I2SC1 TX Right Trigger -// <0x33=> I2SC1 RX Right Trigger -// <i> Define the DMA trigger source -// <id> dmac_trifsrc_0 -#ifndef CONF_DMAC_TRIGSRC_0 -#define CONF_DMAC_TRIGSRC_0 0xff -#endif - -// </e> - -#if CONF_DMAC_TRANS_TYPE_0 == 0 -#define CONF_DMAC_TYPE_0 0 -#define CONF_DMAC_DSYNC_0 0 -#elif CONF_DMAC_TRANS_TYPE_0 == 1 -#define CONF_DMAC_TYPE_0 1 -#define CONF_DMAC_DSYNC_0 0 -#elif CONF_DMAC_TRANS_TYPE_0 == 2 -#define CONF_DMAC_TYPE_0 1 -#define CONF_DMAC_DSYNC_0 1 -#endif - -#if CONF_DMAC_TRIGSRC_0 == 0xFF -#define CONF_DMAC_SWREQ_0 1 -#else -#define CONF_DMAC_SWREQ_0 0 -#endif - -/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address - * or fixed destination address mode, source and destination addresses are incremented - * by 8-bit or 16-bit. - * Workaround: The user can fix the problem by setting the source addressing mode to - * use microblock and data striding with microblock stride set to 0 and data stride set to -1. - */ -#if (CONF_DMAC_CHANNEL_0_SETTINGS == 1 && CONF_DMAC_BEATSIZE_0 != 2 && ((!CONF_DMAC_SRCINC_0) || (!CONF_DMAC_DSTINC_0))) -#if (!CONF_DMAC_SRCINC_0) -#define CONF_DMAC_SRC_STRIDE_0 ((int16_t)(-1)) -#endif -#if (!CONF_DMAC_DSTINC_0) -#define CONF_DMAC_DES_STRIDE_0 ((int16_t)(-1)) -#endif -#endif - -#ifndef CONF_DMAC_SRC_STRIDE_0 -#define CONF_DMAC_SRC_STRIDE_0 0 -#endif - -#ifndef CONF_DMAC_DES_STRIDE_0 -#define CONF_DMAC_DES_STRIDE_0 0 -#endif - -// <e> Channel 1 settings -// <id> dmac_channel_1_settings -#ifndef CONF_DMAC_CHANNEL_1_SETTINGS -#define CONF_DMAC_CHANNEL_1_SETTINGS 0 -#endif - -// <o> Burst Size -// <0x0=> 1 burst size -// <0x1=> 4 burst size -// <0x2=> 8 burst size -// <0x3=> 16 burst size -// <i> Define the memory burst size -// <id> dmac_burstsize_1 -#ifndef CONF_DMAC_BURSTSIZE_1 -#define CONF_DMAC_BURSTSIZE_1 0x0 -#endif - -// <o> Chunk Size -// <0x0=> 1 data transferred -// <0x1=> 2 data transferred -// <0x2=> 4 data transferred -// <0x3=> 8 data transferred -// <0x4=> 16 data transferred -// <i> Define the peripheral chunk size -// <id> dmac_chunksize_1 -#ifndef CONF_DMAC_CHUNKSIZE_1 -#define CONF_DMAC_CHUNKSIZE_1 0x0 -#endif - -// <o> Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// <i> Defines the size of one beat -// <id> dmac_beatsize_1 -#ifndef CONF_DMAC_BEATSIZE_1 -#define CONF_DMAC_BEATSIZE_1 0x0 -#endif - -// <o> Source Interface Identifier -// <0x0=> AHB_IF0 -// <0x1=> AHB_IF1 -// <i> Define the data is read through the system bus interface 0 or 1 -// <id> dma_src_interface_1 -#ifndef CONF_DMAC_SRC_INTERFACE_1 -#define CONF_DMAC_SRC_INTERFACE_1 0x0 -#endif - -// <o> Destination Interface Identifier -// <0x0=> AHB_IF0 -// <0x1=> AHB_IF1 -// <i> Define the data is written through the system bus interface 0 or 1 -// <id> dma_des_interface_1 -#ifndef CONF_DMAC_DES_INTERFACE_1 -#define CONF_DMAC_DES_INTERFACE_1 0x0 -#endif - -// <q> Source Address Increment -// <i> Indicates whether the source address incremented as beat size or not -// <id> dmac_srcinc_1 -#ifndef CONF_DMAC_SRCINC_1 -#define CONF_DMAC_SRCINC_1 0 -#endif - -// <q> Destination Address Increment -// <i> Indicates whether the destination address incremented as beat size or not -// <id> dmac_dstinc_1 -#ifndef CONF_DMAC_DSTINC_1 -#define CONF_DMAC_DSTINC_1 0 -#endif - -// <o> Transfer Type -// <0x0=> Memory to Memory Transfer -// <0x1=> Peripheral to Memory Transfer -// <0x2=> Memory to Peripheral Transfer -// <i> Define the data transfer type -// <id> dma_trans_type_1 -#ifndef CONF_DMAC_TRANS_TYPE_1 -#define CONF_DMAC_TRANS_TYPE_1 0x0 -#endif - -// <o> Trigger source -// <0xFF=> Software Trigger -// <0x00=> HSMCI TX/RX Trigger -// <0x01=> SPI0 TX Trigger -// <0x02=> SPI0 RX Trigger -// <0x03=> SPI1 TX Trigger -// <0x04=> SPI1 RX Trigger -// <0x05=> QSPI TX Trigger -// <0x06=> QSPI RX Trigger -// <0x07=> USART0 TX Trigger -// <0x08=> USART0 RX Trigger -// <0x09=> USART1 TX Trigger -// <0x0A=> USART1 RX Trigger -// <0x0B=> USART2 TX Trigger -// <0x0C=> USART2 RX Trigger -// <0x0D=> PWM0 TX Trigger -// <0x0E=> TWIHS0 TX Trigger -// <0x0F=> TWIHS0 RX Trigger -// <0x10=> TWIHS1 TX Trigger -// <0x11=> TWIHS1 RX Trigger -// <0x12=> TWIHS2 TX Trigger -// <0x13=> TWIHS2 RX Trigger -// <0x14=> UART0 TX Trigger -// <0x15=> UART0 RX Trigger -// <0x16=> UART1 TX Trigger -// <0x17=> UART1 RX Trigger -// <0x18=> UART2 TX Trigger -// <0x19=> UART2 RX Trigger -// <0x1A=> UART3 TX Trigger -// <0x1B=> UART3 RX Trigger -// <0x1C=> UART4 TX Trigger -// <0x1D=> UART4 RX Trigger -// <0x1E=> DACC TX Trigger -// <0x20=> SSC TX Trigger -// <0x21=> SSC RX Trigger -// <0x22=> PIOA RX Trigger -// <0x23=> AFEC0 RX Trigger -// <0x24=> AFEC1 RX Trigger -// <0x25=> AES TX Trigger -// <0x26=> AES RX Trigger -// <0x27=> PWM1 TX Trigger -// <0x28=> TC0 RX Trigger -// <0x29=> TC3 RX Trigger -// <0x2A=> TC6 RX Trigger -// <0x2B=> TC9 RX Trigger -// <0x2C=> I2SC0 TX Left Trigger -// <0x2D=> I2SC0 RX Left Trigger -// <0x2E=> I2SC1 TX Left Trigger -// <0x2F=> I2SC1 RX Left Trigger -// <0x30=> I2SC0 TX Right Trigger -// <0x31=> I2SC0 RX Right Trigger -// <0x32=> I2SC1 TX Right Trigger -// <0x33=> I2SC1 RX Right Trigger -// <i> Define the DMA trigger source -// <id> dmac_trifsrc_1 -#ifndef CONF_DMAC_TRIGSRC_1 -#define CONF_DMAC_TRIGSRC_1 0xff -#endif - -// </e> - -#if CONF_DMAC_TRANS_TYPE_1 == 0 -#define CONF_DMAC_TYPE_1 0 -#define CONF_DMAC_DSYNC_1 0 -#elif CONF_DMAC_TRANS_TYPE_1 == 1 -#define CONF_DMAC_TYPE_1 1 -#define CONF_DMAC_DSYNC_1 0 -#elif CONF_DMAC_TRANS_TYPE_1 == 2 -#define CONF_DMAC_TYPE_1 1 -#define CONF_DMAC_DSYNC_1 1 -#endif - -#if CONF_DMAC_TRIGSRC_1 == 0xFF -#define CONF_DMAC_SWREQ_1 1 -#else -#define CONF_DMAC_SWREQ_1 0 -#endif - -/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address - * or fixed destination address mode, source and destination addresses are incremented - * by 8-bit or 16-bit. - * Workaround: The user can fix the problem by setting the source addressing mode to - * use microblock and data striding with microblock stride set to 0 and data stride set to -1. - */ -#if (CONF_DMAC_CHANNEL_1_SETTINGS == 1 && CONF_DMAC_BEATSIZE_1 != 2 && ((!CONF_DMAC_SRCINC_1) || (!CONF_DMAC_DSTINC_1))) -#if (!CONF_DMAC_SRCINC_1) -#define CONF_DMAC_SRC_STRIDE_1 ((int16_t)(-1)) -#endif -#if (!CONF_DMAC_DSTINC_1) -#define CONF_DMAC_DES_STRIDE_1 ((int16_t)(-1)) -#endif -#endif - -#ifndef CONF_DMAC_SRC_STRIDE_1 -#define CONF_DMAC_SRC_STRIDE_1 0 -#endif - -#ifndef CONF_DMAC_DES_STRIDE_1 -#define CONF_DMAC_DES_STRIDE_1 0 -#endif - -// <e> Channel 2 settings -// <id> dmac_channel_2_settings -#ifndef CONF_DMAC_CHANNEL_2_SETTINGS -#define CONF_DMAC_CHANNEL_2_SETTINGS 0 -#endif - -// <o> Burst Size -// <0x0=> 1 burst size -// <0x1=> 4 burst size -// <0x2=> 8 burst size -// <0x3=> 16 burst size -// <i> Define the memory burst size -// <id> dmac_burstsize_2 -#ifndef CONF_DMAC_BURSTSIZE_2 -#define CONF_DMAC_BURSTSIZE_2 0x0 -#endif - -// <o> Chunk Size -// <0x0=> 1 data transferred -// <0x1=> 2 data transferred -// <0x2=> 4 data transferred -// <0x3=> 8 data transferred -// <0x4=> 16 data transferred -// <i> Define the peripheral chunk size -// <id> dmac_chunksize_2 -#ifndef CONF_DMAC_CHUNKSIZE_2 -#define CONF_DMAC_CHUNKSIZE_2 0x0 -#endif - -// <o> Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// <i> Defines the size of one beat -// <id> dmac_beatsize_2 -#ifndef CONF_DMAC_BEATSIZE_2 -#define CONF_DMAC_BEATSIZE_2 0x0 -#endif - -// <o> Source Interface Identifier -// <0x0=> AHB_IF0 -// <0x1=> AHB_IF1 -// <i> Define the data is read through the system bus interface 0 or 1 -// <id> dma_src_interface_2 -#ifndef CONF_DMAC_SRC_INTERFACE_2 -#define CONF_DMAC_SRC_INTERFACE_2 0x0 -#endif - -// <o> Destination Interface Identifier -// <0x0=> AHB_IF0 -// <0x1=> AHB_IF1 -// <i> Define the data is written through the system bus interface 0 or 1 -// <id> dma_des_interface_2 -#ifndef CONF_DMAC_DES_INTERFACE_2 -#define CONF_DMAC_DES_INTERFACE_2 0x0 -#endif - -// <q> Source Address Increment -// <i> Indicates whether the source address incremented as beat size or not -// <id> dmac_srcinc_2 -#ifndef CONF_DMAC_SRCINC_2 -#define CONF_DMAC_SRCINC_2 0 -#endif - -// <q> Destination Address Increment -// <i> Indicates whether the destination address incremented as beat size or not -// <id> dmac_dstinc_2 -#ifndef CONF_DMAC_DSTINC_2 -#define CONF_DMAC_DSTINC_2 0 -#endif - -// <o> Transfer Type -// <0x0=> Memory to Memory Transfer -// <0x1=> Peripheral to Memory Transfer -// <0x2=> Memory to Peripheral Transfer -// <i> Define the data transfer type -// <id> dma_trans_type_2 -#ifndef CONF_DMAC_TRANS_TYPE_2 -#define CONF_DMAC_TRANS_TYPE_2 0x0 -#endif - -// <o> Trigger source -// <0xFF=> Software Trigger -// <0x00=> HSMCI TX/RX Trigger -// <0x01=> SPI0 TX Trigger -// <0x02=> SPI0 RX Trigger -// <0x03=> SPI1 TX Trigger -// <0x04=> SPI1 RX Trigger -// <0x05=> QSPI TX Trigger -// <0x06=> QSPI RX Trigger -// <0x07=> USART0 TX Trigger -// <0x08=> USART0 RX Trigger -// <0x09=> USART1 TX Trigger -// <0x0A=> USART1 RX Trigger -// <0x0B=> USART2 TX Trigger -// <0x0C=> USART2 RX Trigger -// <0x0D=> PWM0 TX Trigger -// <0x0E=> TWIHS0 TX Trigger -// <0x0F=> TWIHS0 RX Trigger -// <0x10=> TWIHS1 TX Trigger -// <0x11=> TWIHS1 RX Trigger -// <0x12=> TWIHS2 TX Trigger -// <0x13=> TWIHS2 RX Trigger -// <0x14=> UART0 TX Trigger -// <0x15=> UART0 RX Trigger -// <0x16=> UART1 TX Trigger -// <0x17=> UART1 RX Trigger -// <0x18=> UART2 TX Trigger -// <0x19=> UART2 RX Trigger -// <0x1A=> UART3 TX Trigger -// <0x1B=> UART3 RX Trigger -// <0x1C=> UART4 TX Trigger -// <0x1D=> UART4 RX Trigger -// <0x1E=> DACC TX Trigger -// <0x20=> SSC TX Trigger -// <0x21=> SSC RX Trigger -// <0x22=> PIOA RX Trigger -// <0x23=> AFEC0 RX Trigger -// <0x24=> AFEC1 RX Trigger -// <0x25=> AES TX Trigger -// <0x26=> AES RX Trigger -// <0x27=> PWM1 TX Trigger -// <0x28=> TC0 RX Trigger -// <0x29=> TC3 RX Trigger -// <0x2A=> TC6 RX Trigger -// <0x2B=> TC9 RX Trigger -// <0x2C=> I2SC0 TX Left Trigger -// <0x2D=> I2SC0 RX Left Trigger -// <0x2E=> I2SC1 TX Left Trigger -// <0x2F=> I2SC1 RX Left Trigger -// <0x30=> I2SC0 TX Right Trigger -// <0x31=> I2SC0 RX Right Trigger -// <0x32=> I2SC1 TX Right Trigger -// <0x33=> I2SC1 RX Right Trigger -// <i> Define the DMA trigger source -// <id> dmac_trifsrc_2 -#ifndef CONF_DMAC_TRIGSRC_2 -#define CONF_DMAC_TRIGSRC_2 0xff -#endif - -// </e> - -#if CONF_DMAC_TRANS_TYPE_2 == 0 -#define CONF_DMAC_TYPE_2 0 -#define CONF_DMAC_DSYNC_2 0 -#elif CONF_DMAC_TRANS_TYPE_2 == 1 -#define CONF_DMAC_TYPE_2 1 -#define CONF_DMAC_DSYNC_2 0 -#elif CONF_DMAC_TRANS_TYPE_2 == 2 -#define CONF_DMAC_TYPE_2 1 -#define CONF_DMAC_DSYNC_2 1 -#endif - -#if CONF_DMAC_TRIGSRC_2 == 0xFF -#define CONF_DMAC_SWREQ_2 1 -#else -#define CONF_DMAC_SWREQ_2 0 -#endif - -/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address - * or fixed destination address mode, source and destination addresses are incremented - * by 8-bit or 16-bit. - * Workaround: The user can fix the problem by setting the source addressing mode to - * use microblock and data striding with microblock stride set to 0 and data stride set to -1. - */ -#if (CONF_DMAC_CHANNEL_2_SETTINGS == 1 && CONF_DMAC_BEATSIZE_2 != 2 && ((!CONF_DMAC_SRCINC_2) || (!CONF_DMAC_DSTINC_2))) -#if (!CONF_DMAC_SRCINC_2) -#define CONF_DMAC_SRC_STRIDE_2 ((int16_t)(-1)) -#endif -#if (!CONF_DMAC_DSTINC_2) -#define CONF_DMAC_DES_STRIDE_2 ((int16_t)(-1)) -#endif -#endif - -#ifndef CONF_DMAC_SRC_STRIDE_2 -#define CONF_DMAC_SRC_STRIDE_2 0 -#endif - -#ifndef CONF_DMAC_DES_STRIDE_2 -#define CONF_DMAC_DES_STRIDE_2 0 -#endif - -// <e> Channel 3 settings -// <id> dmac_channel_3_settings -#ifndef CONF_DMAC_CHANNEL_3_SETTINGS -#define CONF_DMAC_CHANNEL_3_SETTINGS 0 -#endif - -// <o> Burst Size -// <0x0=> 1 burst size -// <0x1=> 4 burst size -// <0x2=> 8 burst size -// <0x3=> 16 burst size -// <i> Define the memory burst size -// <id> dmac_burstsize_3 -#ifndef CONF_DMAC_BURSTSIZE_3 -#define CONF_DMAC_BURSTSIZE_3 0x0 -#endif - -// <o> Chunk Size -// <0x0=> 1 data transferred -// <0x1=> 2 data transferred -// <0x2=> 4 data transferred -// <0x3=> 8 data transferred -// <0x4=> 16 data transferred -// <i> Define the peripheral chunk size -// <id> dmac_chunksize_3 -#ifndef CONF_DMAC_CHUNKSIZE_3 -#define CONF_DMAC_CHUNKSIZE_3 0x0 -#endif - -// <o> Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// <i> Defines the size of one beat -// <id> dmac_beatsize_3 -#ifndef CONF_DMAC_BEATSIZE_3 -#define CONF_DMAC_BEATSIZE_3 0x0 -#endif - -// <o> Source Interface Identifier -// <0x0=> AHB_IF0 -// <0x1=> AHB_IF1 -// <i> Define the data is read through the system bus interface 0 or 1 -// <id> dma_src_interface_3 -#ifndef CONF_DMAC_SRC_INTERFACE_3 -#define CONF_DMAC_SRC_INTERFACE_3 0x0 -#endif - -// <o> Destination Interface Identifier -// <0x0=> AHB_IF0 -// <0x1=> AHB_IF1 -// <i> Define the data is written through the system bus interface 0 or 1 -// <id> dma_des_interface_3 -#ifndef CONF_DMAC_DES_INTERFACE_3 -#define CONF_DMAC_DES_INTERFACE_3 0x0 -#endif - -// <q> Source Address Increment -// <i> Indicates whether the source address incremented as beat size or not -// <id> dmac_srcinc_3 -#ifndef CONF_DMAC_SRCINC_3 -#define CONF_DMAC_SRCINC_3 0 -#endif - -// <q> Destination Address Increment -// <i> Indicates whether the destination address incremented as beat size or not -// <id> dmac_dstinc_3 -#ifndef CONF_DMAC_DSTINC_3 -#define CONF_DMAC_DSTINC_3 0 -#endif - -// <o> Transfer Type -// <0x0=> Memory to Memory Transfer -// <0x1=> Peripheral to Memory Transfer -// <0x2=> Memory to Peripheral Transfer -// <i> Define the data transfer type -// <id> dma_trans_type_3 -#ifndef CONF_DMAC_TRANS_TYPE_3 -#define CONF_DMAC_TRANS_TYPE_3 0x0 -#endif - -// <o> Trigger source -// <0xFF=> Software Trigger -// <0x00=> HSMCI TX/RX Trigger -// <0x01=> SPI0 TX Trigger -// <0x02=> SPI0 RX Trigger -// <0x03=> SPI1 TX Trigger -// <0x04=> SPI1 RX Trigger -// <0x05=> QSPI TX Trigger -// <0x06=> QSPI RX Trigger -// <0x07=> USART0 TX Trigger -// <0x08=> USART0 RX Trigger -// <0x09=> USART1 TX Trigger -// <0x0A=> USART1 RX Trigger -// <0x0B=> USART2 TX Trigger -// <0x0C=> USART2 RX Trigger -// <0x0D=> PWM0 TX Trigger -// <0x0E=> TWIHS0 TX Trigger -// <0x0F=> TWIHS0 RX Trigger -// <0x10=> TWIHS1 TX Trigger -// <0x11=> TWIHS1 RX Trigger -// <0x12=> TWIHS2 TX Trigger -// <0x13=> TWIHS2 RX Trigger -// <0x14=> UART0 TX Trigger -// <0x15=> UART0 RX Trigger -// <0x16=> UART1 TX Trigger -// <0x17=> UART1 RX Trigger -// <0x18=> UART2 TX Trigger -// <0x19=> UART2 RX Trigger -// <0x1A=> UART3 TX Trigger -// <0x1B=> UART3 RX Trigger -// <0x1C=> UART4 TX Trigger -// <0x1D=> UART4 RX Trigger -// <0x1E=> DACC TX Trigger -// <0x20=> SSC TX Trigger -// <0x21=> SSC RX Trigger -// <0x22=> PIOA RX Trigger -// <0x23=> AFEC0 RX Trigger -// <0x24=> AFEC1 RX Trigger -// <0x25=> AES TX Trigger -// <0x26=> AES RX Trigger -// <0x27=> PWM1 TX Trigger -// <0x28=> TC0 RX Trigger -// <0x29=> TC3 RX Trigger -// <0x2A=> TC6 RX Trigger -// <0x2B=> TC9 RX Trigger -// <0x2C=> I2SC0 TX Left Trigger -// <0x2D=> I2SC0 RX Left Trigger -// <0x2E=> I2SC1 TX Left Trigger -// <0x2F=> I2SC1 RX Left Trigger -// <0x30=> I2SC0 TX Right Trigger -// <0x31=> I2SC0 RX Right Trigger -// <0x32=> I2SC1 TX Right Trigger -// <0x33=> I2SC1 RX Right Trigger -// <i> Define the DMA trigger source -// <id> dmac_trifsrc_3 -#ifndef CONF_DMAC_TRIGSRC_3 -#define CONF_DMAC_TRIGSRC_3 0xff -#endif - -// </e> - -#if CONF_DMAC_TRANS_TYPE_3 == 0 -#define CONF_DMAC_TYPE_3 0 -#define CONF_DMAC_DSYNC_3 0 -#elif CONF_DMAC_TRANS_TYPE_3 == 1 -#define CONF_DMAC_TYPE_3 1 -#define CONF_DMAC_DSYNC_3 0 -#elif CONF_DMAC_TRANS_TYPE_3 == 2 -#define CONF_DMAC_TYPE_3 1 -#define CONF_DMAC_DSYNC_3 1 -#endif - -#if CONF_DMAC_TRIGSRC_3 == 0xFF -#define CONF_DMAC_SWREQ_3 1 -#else -#define CONF_DMAC_SWREQ_3 0 -#endif - -/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address - * or fixed destination address mode, source and destination addresses are incremented - * by 8-bit or 16-bit. - * Workaround: The user can fix the problem by setting the source addressing mode to - * use microblock and data striding with microblock stride set to 0 and data stride set to -1. - */ -#if (CONF_DMAC_CHANNEL_3_SETTINGS == 1 && CONF_DMAC_BEATSIZE_3 != 2 && ((!CONF_DMAC_SRCINC_3) || (!CONF_DMAC_DSTINC_3))) -#if (!CONF_DMAC_SRCINC_3) -#define CONF_DMAC_SRC_STRIDE_3 ((int16_t)(-1)) -#endif -#if (!CONF_DMAC_DSTINC_3) -#define CONF_DMAC_DES_STRIDE_3 ((int16_t)(-1)) -#endif -#endif - -#ifndef CONF_DMAC_SRC_STRIDE_3 -#define CONF_DMAC_SRC_STRIDE_3 0 -#endif - -#ifndef CONF_DMAC_DES_STRIDE_3 -#define CONF_DMAC_DES_STRIDE_3 0 -#endif - -// <e> Channel 4 settings -// <id> dmac_channel_4_settings -#ifndef CONF_DMAC_CHANNEL_4_SETTINGS -#define CONF_DMAC_CHANNEL_4_SETTINGS 0 -#endif - -// <o> Burst Size -// <0x0=> 1 burst size -// <0x1=> 4 burst size -// <0x2=> 8 burst size -// <0x3=> 16 burst size -// <i> Define the memory burst size -// <id> dmac_burstsize_4 -#ifndef CONF_DMAC_BURSTSIZE_4 -#define CONF_DMAC_BURSTSIZE_4 0x0 -#endif - -// <o> Chunk Size -// <0x0=> 1 data transferred -// <0x1=> 2 data transferred -// <0x2=> 4 data transferred -// <0x3=> 8 data transferred -// <0x4=> 16 data transferred -// <i> Define the peripheral chunk size -// <id> dmac_chunksize_4 -#ifndef CONF_DMAC_CHUNKSIZE_4 -#define CONF_DMAC_CHUNKSIZE_4 0x0 -#endif - -// <o> Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// <i> Defines the size of one beat -// <id> dmac_beatsize_4 -#ifndef CONF_DMAC_BEATSIZE_4 -#define CONF_DMAC_BEATSIZE_4 0x0 -#endif - -// <o> Source Interface Identifier -// <0x0=> AHB_IF0 -// <0x1=> AHB_IF1 -// <i> Define the data is read through the system bus interface 0 or 1 -// <id> dma_src_interface_4 -#ifndef CONF_DMAC_SRC_INTERFACE_4 -#define CONF_DMAC_SRC_INTERFACE_4 0x0 -#endif - -// <o> Destination Interface Identifier -// <0x0=> AHB_IF0 -// <0x1=> AHB_IF1 -// <i> Define the data is written through the system bus interface 0 or 1 -// <id> dma_des_interface_4 -#ifndef CONF_DMAC_DES_INTERFACE_4 -#define CONF_DMAC_DES_INTERFACE_4 0x0 -#endif - -// <q> Source Address Increment -// <i> Indicates whether the source address incremented as beat size or not -// <id> dmac_srcinc_4 -#ifndef CONF_DMAC_SRCINC_4 -#define CONF_DMAC_SRCINC_4 0 -#endif - -// <q> Destination Address Increment -// <i> Indicates whether the destination address incremented as beat size or not -// <id> dmac_dstinc_4 -#ifndef CONF_DMAC_DSTINC_4 -#define CONF_DMAC_DSTINC_4 0 -#endif - -// <o> Transfer Type -// <0x0=> Memory to Memory Transfer -// <0x1=> Peripheral to Memory Transfer -// <0x2=> Memory to Peripheral Transfer -// <i> Define the data transfer type -// <id> dma_trans_type_4 -#ifndef CONF_DMAC_TRANS_TYPE_4 -#define CONF_DMAC_TRANS_TYPE_4 0x0 -#endif - -// <o> Trigger source -// <0xFF=> Software Trigger -// <0x00=> HSMCI TX/RX Trigger -// <0x01=> SPI0 TX Trigger -// <0x02=> SPI0 RX Trigger -// <0x03=> SPI1 TX Trigger -// <0x04=> SPI1 RX Trigger -// <0x05=> QSPI TX Trigger -// <0x06=> QSPI RX Trigger -// <0x07=> USART0 TX Trigger -// <0x08=> USART0 RX Trigger -// <0x09=> USART1 TX Trigger -// <0x0A=> USART1 RX Trigger -// <0x0B=> USART2 TX Trigger -// <0x0C=> USART2 RX Trigger -// <0x0D=> PWM0 TX Trigger -// <0x0E=> TWIHS0 TX Trigger -// <0x0F=> TWIHS0 RX Trigger -// <0x10=> TWIHS1 TX Trigger -// <0x11=> TWIHS1 RX Trigger -// <0x12=> TWIHS2 TX Trigger -// <0x13=> TWIHS2 RX Trigger -// <0x14=> UART0 TX Trigger -// <0x15=> UART0 RX Trigger -// <0x16=> UART1 TX Trigger -// <0x17=> UART1 RX Trigger -// <0x18=> UART2 TX Trigger -// <0x19=> UART2 RX Trigger -// <0x1A=> UART3 TX Trigger -// <0x1B=> UART3 RX Trigger -// <0x1C=> UART4 TX Trigger -// <0x1D=> UART4 RX Trigger -// <0x1E=> DACC TX Trigger -// <0x20=> SSC TX Trigger -// <0x21=> SSC RX Trigger -// <0x22=> PIOA RX Trigger -// <0x23=> AFEC0 RX Trigger -// <0x24=> AFEC1 RX Trigger -// <0x25=> AES TX Trigger -// <0x26=> AES RX Trigger -// <0x27=> PWM1 TX Trigger -// <0x28=> TC0 RX Trigger -// <0x29=> TC3 RX Trigger -// <0x2A=> TC6 RX Trigger -// <0x2B=> TC9 RX Trigger -// <0x2C=> I2SC0 TX Left Trigger -// <0x2D=> I2SC0 RX Left Trigger -// <0x2E=> I2SC1 TX Left Trigger -// <0x2F=> I2SC1 RX Left Trigger -// <0x30=> I2SC0 TX Right Trigger -// <0x31=> I2SC0 RX Right Trigger -// <0x32=> I2SC1 TX Right Trigger -// <0x33=> I2SC1 RX Right Trigger -// <i> Define the DMA trigger source -// <id> dmac_trifsrc_4 -#ifndef CONF_DMAC_TRIGSRC_4 -#define CONF_DMAC_TRIGSRC_4 0xff -#endif - -// </e> - -#if CONF_DMAC_TRANS_TYPE_4 == 0 -#define CONF_DMAC_TYPE_4 0 -#define CONF_DMAC_DSYNC_4 0 -#elif CONF_DMAC_TRANS_TYPE_4 == 1 -#define CONF_DMAC_TYPE_4 1 -#define CONF_DMAC_DSYNC_4 0 -#elif CONF_DMAC_TRANS_TYPE_4 == 2 -#define CONF_DMAC_TYPE_4 1 -#define CONF_DMAC_DSYNC_4 1 -#endif - -#if CONF_DMAC_TRIGSRC_4 == 0xFF -#define CONF_DMAC_SWREQ_4 1 -#else -#define CONF_DMAC_SWREQ_4 0 -#endif - -/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address - * or fixed destination address mode, source and destination addresses are incremented - * by 8-bit or 16-bit. - * Workaround: The user can fix the problem by setting the source addressing mode to - * use microblock and data striding with microblock stride set to 0 and data stride set to -1. - */ -#if (CONF_DMAC_CHANNEL_4_SETTINGS == 1 && CONF_DMAC_BEATSIZE_4 != 2 && ((!CONF_DMAC_SRCINC_4) || (!CONF_DMAC_DSTINC_4))) -#if (!CONF_DMAC_SRCINC_4) -#define CONF_DMAC_SRC_STRIDE_4 ((int16_t)(-1)) -#endif -#if (!CONF_DMAC_DSTINC_4) -#define CONF_DMAC_DES_STRIDE_4 ((int16_t)(-1)) -#endif -#endif - -#ifndef CONF_DMAC_SRC_STRIDE_4 -#define CONF_DMAC_SRC_STRIDE_4 0 -#endif - -#ifndef CONF_DMAC_DES_STRIDE_4 -#define CONF_DMAC_DES_STRIDE_4 0 -#endif - -// <e> Channel 5 settings -// <id> dmac_channel_5_settings -#ifndef CONF_DMAC_CHANNEL_5_SETTINGS -#define CONF_DMAC_CHANNEL_5_SETTINGS 0 -#endif - -// <o> Burst Size -// <0x0=> 1 burst size -// <0x1=> 4 burst size -// <0x2=> 8 burst size -// <0x3=> 16 burst size -// <i> Define the memory burst size -// <id> dmac_burstsize_5 -#ifndef CONF_DMAC_BURSTSIZE_5 -#define CONF_DMAC_BURSTSIZE_5 0x0 -#endif - -// <o> Chunk Size -// <0x0=> 1 data transferred -// <0x1=> 2 data transferred -// <0x2=> 4 data transferred -// <0x3=> 8 data transferred -// <0x4=> 16 data transferred -// <i> Define the peripheral chunk size -// <id> dmac_chunksize_5 -#ifndef CONF_DMAC_CHUNKSIZE_5 -#define CONF_DMAC_CHUNKSIZE_5 0x0 -#endif - -// <o> Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// <i> Defines the size of one beat -// <id> dmac_beatsize_5 -#ifndef CONF_DMAC_BEATSIZE_5 -#define CONF_DMAC_BEATSIZE_5 0x0 -#endif - -// <o> Source Interface Identifier -// <0x0=> AHB_IF0 -// <0x1=> AHB_IF1 -// <i> Define the data is read through the system bus interface 0 or 1 -// <id> dma_src_interface_5 -#ifndef CONF_DMAC_SRC_INTERFACE_5 -#define CONF_DMAC_SRC_INTERFACE_5 0x0 -#endif - -// <o> Destination Interface Identifier -// <0x0=> AHB_IF0 -// <0x1=> AHB_IF1 -// <i> Define the data is written through the system bus interface 0 or 1 -// <id> dma_des_interface_5 -#ifndef CONF_DMAC_DES_INTERFACE_5 -#define CONF_DMAC_DES_INTERFACE_5 0x0 -#endif - -// <q> Source Address Increment -// <i> Indicates whether the source address incremented as beat size or not -// <id> dmac_srcinc_5 -#ifndef CONF_DMAC_SRCINC_5 -#define CONF_DMAC_SRCINC_5 0 -#endif - -// <q> Destination Address Increment -// <i> Indicates whether the destination address incremented as beat size or not -// <id> dmac_dstinc_5 -#ifndef CONF_DMAC_DSTINC_5 -#define CONF_DMAC_DSTINC_5 0 -#endif - -// <o> Transfer Type -// <0x0=> Memory to Memory Transfer -// <0x1=> Peripheral to Memory Transfer -// <0x2=> Memory to Peripheral Transfer -// <i> Define the data transfer type -// <id> dma_trans_type_5 -#ifndef CONF_DMAC_TRANS_TYPE_5 -#define CONF_DMAC_TRANS_TYPE_5 0x0 -#endif - -// <o> Trigger source -// <0xFF=> Software Trigger -// <0x00=> HSMCI TX/RX Trigger -// <0x01=> SPI0 TX Trigger -// <0x02=> SPI0 RX Trigger -// <0x03=> SPI1 TX Trigger -// <0x04=> SPI1 RX Trigger -// <0x05=> QSPI TX Trigger -// <0x06=> QSPI RX Trigger -// <0x07=> USART0 TX Trigger -// <0x08=> USART0 RX Trigger -// <0x09=> USART1 TX Trigger -// <0x0A=> USART1 RX Trigger -// <0x0B=> USART2 TX Trigger -// <0x0C=> USART2 RX Trigger -// <0x0D=> PWM0 TX Trigger -// <0x0E=> TWIHS0 TX Trigger -// <0x0F=> TWIHS0 RX Trigger -// <0x10=> TWIHS1 TX Trigger -// <0x11=> TWIHS1 RX Trigger -// <0x12=> TWIHS2 TX Trigger -// <0x13=> TWIHS2 RX Trigger -// <0x14=> UART0 TX Trigger -// <0x15=> UART0 RX Trigger -// <0x16=> UART1 TX Trigger -// <0x17=> UART1 RX Trigger -// <0x18=> UART2 TX Trigger -// <0x19=> UART2 RX Trigger -// <0x1A=> UART3 TX Trigger -// <0x1B=> UART3 RX Trigger -// <0x1C=> UART4 TX Trigger -// <0x1D=> UART4 RX Trigger -// <0x1E=> DACC TX Trigger -// <0x20=> SSC TX Trigger -// <0x21=> SSC RX Trigger -// <0x22=> PIOA RX Trigger -// <0x23=> AFEC0 RX Trigger -// <0x24=> AFEC1 RX Trigger -// <0x25=> AES TX Trigger -// <0x26=> AES RX Trigger -// <0x27=> PWM1 TX Trigger -// <0x28=> TC0 RX Trigger -// <0x29=> TC3 RX Trigger -// <0x2A=> TC6 RX Trigger -// <0x2B=> TC9 RX Trigger -// <0x2C=> I2SC0 TX Left Trigger -// <0x2D=> I2SC0 RX Left Trigger -// <0x2E=> I2SC1 TX Left Trigger -// <0x2F=> I2SC1 RX Left Trigger -// <0x30=> I2SC0 TX Right Trigger -// <0x31=> I2SC0 RX Right Trigger -// <0x32=> I2SC1 TX Right Trigger -// <0x33=> I2SC1 RX Right Trigger -// <i> Define the DMA trigger source -// <id> dmac_trifsrc_5 -#ifndef CONF_DMAC_TRIGSRC_5 -#define CONF_DMAC_TRIGSRC_5 0xff -#endif - -// </e> - -#if CONF_DMAC_TRANS_TYPE_5 == 0 -#define CONF_DMAC_TYPE_5 0 -#define CONF_DMAC_DSYNC_5 0 -#elif CONF_DMAC_TRANS_TYPE_5 == 1 -#define CONF_DMAC_TYPE_5 1 -#define CONF_DMAC_DSYNC_5 0 -#elif CONF_DMAC_TRANS_TYPE_5 == 2 -#define CONF_DMAC_TYPE_5 1 -#define CONF_DMAC_DSYNC_5 1 -#endif - -#if CONF_DMAC_TRIGSRC_5 == 0xFF -#define CONF_DMAC_SWREQ_5 1 -#else -#define CONF_DMAC_SWREQ_5 0 -#endif - -/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address - * or fixed destination address mode, source and destination addresses are incremented - * by 8-bit or 16-bit. - * Workaround: The user can fix the problem by setting the source addressing mode to - * use microblock and data striding with microblock stride set to 0 and data stride set to -1. - */ -#if (CONF_DMAC_CHANNEL_5_SETTINGS == 1 && CONF_DMAC_BEATSIZE_5 != 2 && ((!CONF_DMAC_SRCINC_5) || (!CONF_DMAC_DSTINC_5))) -#if (!CONF_DMAC_SRCINC_5) -#define CONF_DMAC_SRC_STRIDE_5 ((int16_t)(-1)) -#endif -#if (!CONF_DMAC_DSTINC_5) -#define CONF_DMAC_DES_STRIDE_5 ((int16_t)(-1)) -#endif -#endif - -#ifndef CONF_DMAC_SRC_STRIDE_5 -#define CONF_DMAC_SRC_STRIDE_5 0 -#endif - -#ifndef CONF_DMAC_DES_STRIDE_5 -#define CONF_DMAC_DES_STRIDE_5 0 -#endif - -// <e> Channel 6 settings -// <id> dmac_channel_6_settings -#ifndef CONF_DMAC_CHANNEL_6_SETTINGS -#define CONF_DMAC_CHANNEL_6_SETTINGS 0 -#endif - -// <o> Burst Size -// <0x0=> 1 burst size -// <0x1=> 4 burst size -// <0x2=> 8 burst size -// <0x3=> 16 burst size -// <i> Define the memory burst size -// <id> dmac_burstsize_6 -#ifndef CONF_DMAC_BURSTSIZE_6 -#define CONF_DMAC_BURSTSIZE_6 0x0 -#endif - -// <o> Chunk Size -// <0x0=> 1 data transferred -// <0x1=> 2 data transferred -// <0x2=> 4 data transferred -// <0x3=> 8 data transferred -// <0x4=> 16 data transferred -// <i> Define the peripheral chunk size -// <id> dmac_chunksize_6 -#ifndef CONF_DMAC_CHUNKSIZE_6 -#define CONF_DMAC_CHUNKSIZE_6 0x0 -#endif - -// <o> Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// <i> Defines the size of one beat -// <id> dmac_beatsize_6 -#ifndef CONF_DMAC_BEATSIZE_6 -#define CONF_DMAC_BEATSIZE_6 0x0 -#endif - -// <o> Source Interface Identifier -// <0x0=> AHB_IF0 -// <0x1=> AHB_IF1 -// <i> Define the data is read through the system bus interface 0 or 1 -// <id> dma_src_interface_6 -#ifndef CONF_DMAC_SRC_INTERFACE_6 -#define CONF_DMAC_SRC_INTERFACE_6 0x0 -#endif - -// <o> Destination Interface Identifier -// <0x0=> AHB_IF0 -// <0x1=> AHB_IF1 -// <i> Define the data is written through the system bus interface 0 or 1 -// <id> dma_des_interface_6 -#ifndef CONF_DMAC_DES_INTERFACE_6 -#define CONF_DMAC_DES_INTERFACE_6 0x0 -#endif - -// <q> Source Address Increment -// <i> Indicates whether the source address incremented as beat size or not -// <id> dmac_srcinc_6 -#ifndef CONF_DMAC_SRCINC_6 -#define CONF_DMAC_SRCINC_6 0 -#endif - -// <q> Destination Address Increment -// <i> Indicates whether the destination address incremented as beat size or not -// <id> dmac_dstinc_6 -#ifndef CONF_DMAC_DSTINC_6 -#define CONF_DMAC_DSTINC_6 0 -#endif - -// <o> Transfer Type -// <0x0=> Memory to Memory Transfer -// <0x1=> Peripheral to Memory Transfer -// <0x2=> Memory to Peripheral Transfer -// <i> Define the data transfer type -// <id> dma_trans_type_6 -#ifndef CONF_DMAC_TRANS_TYPE_6 -#define CONF_DMAC_TRANS_TYPE_6 0x0 -#endif - -// <o> Trigger source -// <0xFF=> Software Trigger -// <0x00=> HSMCI TX/RX Trigger -// <0x01=> SPI0 TX Trigger -// <0x02=> SPI0 RX Trigger -// <0x03=> SPI1 TX Trigger -// <0x04=> SPI1 RX Trigger -// <0x05=> QSPI TX Trigger -// <0x06=> QSPI RX Trigger -// <0x07=> USART0 TX Trigger -// <0x08=> USART0 RX Trigger -// <0x09=> USART1 TX Trigger -// <0x0A=> USART1 RX Trigger -// <0x0B=> USART2 TX Trigger -// <0x0C=> USART2 RX Trigger -// <0x0D=> PWM0 TX Trigger -// <0x0E=> TWIHS0 TX Trigger -// <0x0F=> TWIHS0 RX Trigger -// <0x10=> TWIHS1 TX Trigger -// <0x11=> TWIHS1 RX Trigger -// <0x12=> TWIHS2 TX Trigger -// <0x13=> TWIHS2 RX Trigger -// <0x14=> UART0 TX Trigger -// <0x15=> UART0 RX Trigger -// <0x16=> UART1 TX Trigger -// <0x17=> UART1 RX Trigger -// <0x18=> UART2 TX Trigger -// <0x19=> UART2 RX Trigger -// <0x1A=> UART3 TX Trigger -// <0x1B=> UART3 RX Trigger -// <0x1C=> UART4 TX Trigger -// <0x1D=> UART4 RX Trigger -// <0x1E=> DACC TX Trigger -// <0x20=> SSC TX Trigger -// <0x21=> SSC RX Trigger -// <0x22=> PIOA RX Trigger -// <0x23=> AFEC0 RX Trigger -// <0x24=> AFEC1 RX Trigger -// <0x25=> AES TX Trigger -// <0x26=> AES RX Trigger -// <0x27=> PWM1 TX Trigger -// <0x28=> TC0 RX Trigger -// <0x29=> TC3 RX Trigger -// <0x2A=> TC6 RX Trigger -// <0x2B=> TC9 RX Trigger -// <0x2C=> I2SC0 TX Left Trigger -// <0x2D=> I2SC0 RX Left Trigger -// <0x2E=> I2SC1 TX Left Trigger -// <0x2F=> I2SC1 RX Left Trigger -// <0x30=> I2SC0 TX Right Trigger -// <0x31=> I2SC0 RX Right Trigger -// <0x32=> I2SC1 TX Right Trigger -// <0x33=> I2SC1 RX Right Trigger -// <i> Define the DMA trigger source -// <id> dmac_trifsrc_6 -#ifndef CONF_DMAC_TRIGSRC_6 -#define CONF_DMAC_TRIGSRC_6 0xff -#endif - -// </e> - -#if CONF_DMAC_TRANS_TYPE_6 == 0 -#define CONF_DMAC_TYPE_6 0 -#define CONF_DMAC_DSYNC_6 0 -#elif CONF_DMAC_TRANS_TYPE_6 == 1 -#define CONF_DMAC_TYPE_6 1 -#define CONF_DMAC_DSYNC_6 0 -#elif CONF_DMAC_TRANS_TYPE_6 == 2 -#define CONF_DMAC_TYPE_6 1 -#define CONF_DMAC_DSYNC_6 1 -#endif - -#if CONF_DMAC_TRIGSRC_6 == 0xFF -#define CONF_DMAC_SWREQ_6 1 -#else -#define CONF_DMAC_SWREQ_6 0 -#endif - -/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address - * or fixed destination address mode, source and destination addresses are incremented - * by 8-bit or 16-bit. - * Workaround: The user can fix the problem by setting the source addressing mode to - * use microblock and data striding with microblock stride set to 0 and data stride set to -1. - */ -#if (CONF_DMAC_CHANNEL_6_SETTINGS == 1 && CONF_DMAC_BEATSIZE_6 != 2 && ((!CONF_DMAC_SRCINC_6) || (!CONF_DMAC_DSTINC_6))) -#if (!CONF_DMAC_SRCINC_6) -#define CONF_DMAC_SRC_STRIDE_6 ((int16_t)(-1)) -#endif -#if (!CONF_DMAC_DSTINC_6) -#define CONF_DMAC_DES_STRIDE_6 ((int16_t)(-1)) -#endif -#endif - -#ifndef CONF_DMAC_SRC_STRIDE_6 -#define CONF_DMAC_SRC_STRIDE_6 0 -#endif - -#ifndef CONF_DMAC_DES_STRIDE_6 -#define CONF_DMAC_DES_STRIDE_6 0 -#endif - -// <e> Channel 7 settings -// <id> dmac_channel_7_settings -#ifndef CONF_DMAC_CHANNEL_7_SETTINGS -#define CONF_DMAC_CHANNEL_7_SETTINGS 0 -#endif - -// <o> Burst Size -// <0x0=> 1 burst size -// <0x1=> 4 burst size -// <0x2=> 8 burst size -// <0x3=> 16 burst size -// <i> Define the memory burst size -// <id> dmac_burstsize_7 -#ifndef CONF_DMAC_BURSTSIZE_7 -#define CONF_DMAC_BURSTSIZE_7 0x0 -#endif - -// <o> Chunk Size -// <0x0=> 1 data transferred -// <0x1=> 2 data transferred -// <0x2=> 4 data transferred -// <0x3=> 8 data transferred -// <0x4=> 16 data transferred -// <i> Define the peripheral chunk size -// <id> dmac_chunksize_7 -#ifndef CONF_DMAC_CHUNKSIZE_7 -#define CONF_DMAC_CHUNKSIZE_7 0x0 -#endif - -// <o> Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// <i> Defines the size of one beat -// <id> dmac_beatsize_7 -#ifndef CONF_DMAC_BEATSIZE_7 -#define CONF_DMAC_BEATSIZE_7 0x0 -#endif - -// <o> Source Interface Identifier -// <0x0=> AHB_IF0 -// <0x1=> AHB_IF1 -// <i> Define the data is read through the system bus interface 0 or 1 -// <id> dma_src_interface_7 -#ifndef CONF_DMAC_SRC_INTERFACE_7 -#define CONF_DMAC_SRC_INTERFACE_7 0x0 -#endif - -// <o> Destination Interface Identifier -// <0x0=> AHB_IF0 -// <0x1=> AHB_IF1 -// <i> Define the data is written through the system bus interface 0 or 1 -// <id> dma_des_interface_7 -#ifndef CONF_DMAC_DES_INTERFACE_7 -#define CONF_DMAC_DES_INTERFACE_7 0x0 -#endif - -// <q> Source Address Increment -// <i> Indicates whether the source address incremented as beat size or not -// <id> dmac_srcinc_7 -#ifndef CONF_DMAC_SRCINC_7 -#define CONF_DMAC_SRCINC_7 0 -#endif - -// <q> Destination Address Increment -// <i> Indicates whether the destination address incremented as beat size or not -// <id> dmac_dstinc_7 -#ifndef CONF_DMAC_DSTINC_7 -#define CONF_DMAC_DSTINC_7 0 -#endif - -// <o> Transfer Type -// <0x0=> Memory to Memory Transfer -// <0x1=> Peripheral to Memory Transfer -// <0x2=> Memory to Peripheral Transfer -// <i> Define the data transfer type -// <id> dma_trans_type_7 -#ifndef CONF_DMAC_TRANS_TYPE_7 -#define CONF_DMAC_TRANS_TYPE_7 0x0 -#endif - -// <o> Trigger source -// <0xFF=> Software Trigger -// <0x00=> HSMCI TX/RX Trigger -// <0x01=> SPI0 TX Trigger -// <0x02=> SPI0 RX Trigger -// <0x03=> SPI1 TX Trigger -// <0x04=> SPI1 RX Trigger -// <0x05=> QSPI TX Trigger -// <0x06=> QSPI RX Trigger -// <0x07=> USART0 TX Trigger -// <0x08=> USART0 RX Trigger -// <0x09=> USART1 TX Trigger -// <0x0A=> USART1 RX Trigger -// <0x0B=> USART2 TX Trigger -// <0x0C=> USART2 RX Trigger -// <0x0D=> PWM0 TX Trigger -// <0x0E=> TWIHS0 TX Trigger -// <0x0F=> TWIHS0 RX Trigger -// <0x10=> TWIHS1 TX Trigger -// <0x11=> TWIHS1 RX Trigger -// <0x12=> TWIHS2 TX Trigger -// <0x13=> TWIHS2 RX Trigger -// <0x14=> UART0 TX Trigger -// <0x15=> UART0 RX Trigger -// <0x16=> UART1 TX Trigger -// <0x17=> UART1 RX Trigger -// <0x18=> UART2 TX Trigger -// <0x19=> UART2 RX Trigger -// <0x1A=> UART3 TX Trigger -// <0x1B=> UART3 RX Trigger -// <0x1C=> UART4 TX Trigger -// <0x1D=> UART4 RX Trigger -// <0x1E=> DACC TX Trigger -// <0x20=> SSC TX Trigger -// <0x21=> SSC RX Trigger -// <0x22=> PIOA RX Trigger -// <0x23=> AFEC0 RX Trigger -// <0x24=> AFEC1 RX Trigger -// <0x25=> AES TX Trigger -// <0x26=> AES RX Trigger -// <0x27=> PWM1 TX Trigger -// <0x28=> TC0 RX Trigger -// <0x29=> TC3 RX Trigger -// <0x2A=> TC6 RX Trigger -// <0x2B=> TC9 RX Trigger -// <0x2C=> I2SC0 TX Left Trigger -// <0x2D=> I2SC0 RX Left Trigger -// <0x2E=> I2SC1 TX Left Trigger -// <0x2F=> I2SC1 RX Left Trigger -// <0x30=> I2SC0 TX Right Trigger -// <0x31=> I2SC0 RX Right Trigger -// <0x32=> I2SC1 TX Right Trigger -// <0x33=> I2SC1 RX Right Trigger -// <i> Define the DMA trigger source -// <id> dmac_trifsrc_7 -#ifndef CONF_DMAC_TRIGSRC_7 -#define CONF_DMAC_TRIGSRC_7 0xff -#endif - -// </e> - -#if CONF_DMAC_TRANS_TYPE_7 == 0 -#define CONF_DMAC_TYPE_7 0 -#define CONF_DMAC_DSYNC_7 0 -#elif CONF_DMAC_TRANS_TYPE_7 == 1 -#define CONF_DMAC_TYPE_7 1 -#define CONF_DMAC_DSYNC_7 0 -#elif CONF_DMAC_TRANS_TYPE_7 == 2 -#define CONF_DMAC_TYPE_7 1 -#define CONF_DMAC_DSYNC_7 1 -#endif - -#if CONF_DMAC_TRIGSRC_7 == 0xFF -#define CONF_DMAC_SWREQ_7 1 -#else -#define CONF_DMAC_SWREQ_7 0 -#endif - -/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address - * or fixed destination address mode, source and destination addresses are incremented - * by 8-bit or 16-bit. - * Workaround: The user can fix the problem by setting the source addressing mode to - * use microblock and data striding with microblock stride set to 0 and data stride set to -1. - */ -#if (CONF_DMAC_CHANNEL_7_SETTINGS == 1 && CONF_DMAC_BEATSIZE_7 != 2 && ((!CONF_DMAC_SRCINC_7) || (!CONF_DMAC_DSTINC_7))) -#if (!CONF_DMAC_SRCINC_7) -#define CONF_DMAC_SRC_STRIDE_7 ((int16_t)(-1)) -#endif -#if (!CONF_DMAC_DSTINC_7) -#define CONF_DMAC_DES_STRIDE_7 ((int16_t)(-1)) -#endif -#endif - -#ifndef CONF_DMAC_SRC_STRIDE_7 -#define CONF_DMAC_SRC_STRIDE_7 0 -#endif - -#ifndef CONF_DMAC_DES_STRIDE_7 -#define CONF_DMAC_DES_STRIDE_7 0 -#endif - -// <e> Channel 8 settings -// <id> dmac_channel_8_settings -#ifndef CONF_DMAC_CHANNEL_8_SETTINGS -#define CONF_DMAC_CHANNEL_8_SETTINGS 0 -#endif - -// <o> Burst Size -// <0x0=> 1 burst size -// <0x1=> 4 burst size -// <0x2=> 8 burst size -// <0x3=> 16 burst size -// <i> Define the memory burst size -// <id> dmac_burstsize_8 -#ifndef CONF_DMAC_BURSTSIZE_8 -#define CONF_DMAC_BURSTSIZE_8 0x0 -#endif - -// <o> Chunk Size -// <0x0=> 1 data transferred -// <0x1=> 2 data transferred -// <0x2=> 4 data transferred -// <0x3=> 8 data transferred -// <0x4=> 16 data transferred -// <i> Define the peripheral chunk size -// <id> dmac_chunksize_8 -#ifndef CONF_DMAC_CHUNKSIZE_8 -#define CONF_DMAC_CHUNKSIZE_8 0x0 -#endif - -// <o> Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// <i> Defines the size of one beat -// <id> dmac_beatsize_8 -#ifndef CONF_DMAC_BEATSIZE_8 -#define CONF_DMAC_BEATSIZE_8 0x0 -#endif - -// <o> Source Interface Identifier -// <0x0=> AHB_IF0 -// <0x1=> AHB_IF1 -// <i> Define the data is read through the system bus interface 0 or 1 -// <id> dma_src_interface_8 -#ifndef CONF_DMAC_SRC_INTERFACE_8 -#define CONF_DMAC_SRC_INTERFACE_8 0x0 -#endif - -// <o> Destination Interface Identifier -// <0x0=> AHB_IF0 -// <0x1=> AHB_IF1 -// <i> Define the data is written through the system bus interface 0 or 1 -// <id> dma_des_interface_8 -#ifndef CONF_DMAC_DES_INTERFACE_8 -#define CONF_DMAC_DES_INTERFACE_8 0x0 -#endif - -// <q> Source Address Increment -// <i> Indicates whether the source address incremented as beat size or not -// <id> dmac_srcinc_8 -#ifndef CONF_DMAC_SRCINC_8 -#define CONF_DMAC_SRCINC_8 0 -#endif - -// <q> Destination Address Increment -// <i> Indicates whether the destination address incremented as beat size or not -// <id> dmac_dstinc_8 -#ifndef CONF_DMAC_DSTINC_8 -#define CONF_DMAC_DSTINC_8 0 -#endif - -// <o> Transfer Type -// <0x0=> Memory to Memory Transfer -// <0x1=> Peripheral to Memory Transfer -// <0x2=> Memory to Peripheral Transfer -// <i> Define the data transfer type -// <id> dma_trans_type_8 -#ifndef CONF_DMAC_TRANS_TYPE_8 -#define CONF_DMAC_TRANS_TYPE_8 0x0 -#endif - -// <o> Trigger source -// <0xFF=> Software Trigger -// <0x00=> HSMCI TX/RX Trigger -// <0x01=> SPI0 TX Trigger -// <0x02=> SPI0 RX Trigger -// <0x03=> SPI1 TX Trigger -// <0x04=> SPI1 RX Trigger -// <0x05=> QSPI TX Trigger -// <0x06=> QSPI RX Trigger -// <0x07=> USART0 TX Trigger -// <0x08=> USART0 RX Trigger -// <0x09=> USART1 TX Trigger -// <0x0A=> USART1 RX Trigger -// <0x0B=> USART2 TX Trigger -// <0x0C=> USART2 RX Trigger -// <0x0D=> PWM0 TX Trigger -// <0x0E=> TWIHS0 TX Trigger -// <0x0F=> TWIHS0 RX Trigger -// <0x10=> TWIHS1 TX Trigger -// <0x11=> TWIHS1 RX Trigger -// <0x12=> TWIHS2 TX Trigger -// <0x13=> TWIHS2 RX Trigger -// <0x14=> UART0 TX Trigger -// <0x15=> UART0 RX Trigger -// <0x16=> UART1 TX Trigger -// <0x17=> UART1 RX Trigger -// <0x18=> UART2 TX Trigger -// <0x19=> UART2 RX Trigger -// <0x1A=> UART3 TX Trigger -// <0x1B=> UART3 RX Trigger -// <0x1C=> UART4 TX Trigger -// <0x1D=> UART4 RX Trigger -// <0x1E=> DACC TX Trigger -// <0x20=> SSC TX Trigger -// <0x21=> SSC RX Trigger -// <0x22=> PIOA RX Trigger -// <0x23=> AFEC0 RX Trigger -// <0x24=> AFEC1 RX Trigger -// <0x25=> AES TX Trigger -// <0x26=> AES RX Trigger -// <0x27=> PWM1 TX Trigger -// <0x28=> TC0 RX Trigger -// <0x29=> TC3 RX Trigger -// <0x2A=> TC6 RX Trigger -// <0x2B=> TC9 RX Trigger -// <0x2C=> I2SC0 TX Left Trigger -// <0x2D=> I2SC0 RX Left Trigger -// <0x2E=> I2SC1 TX Left Trigger -// <0x2F=> I2SC1 RX Left Trigger -// <0x30=> I2SC0 TX Right Trigger -// <0x31=> I2SC0 RX Right Trigger -// <0x32=> I2SC1 TX Right Trigger -// <0x33=> I2SC1 RX Right Trigger -// <i> Define the DMA trigger source -// <id> dmac_trifsrc_8 -#ifndef CONF_DMAC_TRIGSRC_8 -#define CONF_DMAC_TRIGSRC_8 0xff -#endif - -// </e> - -#if CONF_DMAC_TRANS_TYPE_8 == 0 -#define CONF_DMAC_TYPE_8 0 -#define CONF_DMAC_DSYNC_8 0 -#elif CONF_DMAC_TRANS_TYPE_8 == 1 -#define CONF_DMAC_TYPE_8 1 -#define CONF_DMAC_DSYNC_8 0 -#elif CONF_DMAC_TRANS_TYPE_8 == 2 -#define CONF_DMAC_TYPE_8 1 -#define CONF_DMAC_DSYNC_8 1 -#endif - -#if CONF_DMAC_TRIGSRC_8 == 0xFF -#define CONF_DMAC_SWREQ_8 1 -#else -#define CONF_DMAC_SWREQ_8 0 -#endif - -/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address - * or fixed destination address mode, source and destination addresses are incremented - * by 8-bit or 16-bit. - * Workaround: The user can fix the problem by setting the source addressing mode to - * use microblock and data striding with microblock stride set to 0 and data stride set to -1. - */ -#if (CONF_DMAC_CHANNEL_8_SETTINGS == 1 && CONF_DMAC_BEATSIZE_8 != 2 && ((!CONF_DMAC_SRCINC_8) || (!CONF_DMAC_DSTINC_8))) -#if (!CONF_DMAC_SRCINC_8) -#define CONF_DMAC_SRC_STRIDE_8 ((int16_t)(-1)) -#endif -#if (!CONF_DMAC_DSTINC_8) -#define CONF_DMAC_DES_STRIDE_8 ((int16_t)(-1)) -#endif -#endif - -#ifndef CONF_DMAC_SRC_STRIDE_8 -#define CONF_DMAC_SRC_STRIDE_8 0 -#endif - -#ifndef CONF_DMAC_DES_STRIDE_8 -#define CONF_DMAC_DES_STRIDE_8 0 -#endif - -// <e> Channel 9 settings -// <id> dmac_channel_9_settings -#ifndef CONF_DMAC_CHANNEL_9_SETTINGS -#define CONF_DMAC_CHANNEL_9_SETTINGS 0 -#endif - -// <o> Burst Size -// <0x0=> 1 burst size -// <0x1=> 4 burst size -// <0x2=> 8 burst size -// <0x3=> 16 burst size -// <i> Define the memory burst size -// <id> dmac_burstsize_9 -#ifndef CONF_DMAC_BURSTSIZE_9 -#define CONF_DMAC_BURSTSIZE_9 0x0 -#endif - -// <o> Chunk Size -// <0x0=> 1 data transferred -// <0x1=> 2 data transferred -// <0x2=> 4 data transferred -// <0x3=> 8 data transferred -// <0x4=> 16 data transferred -// <i> Define the peripheral chunk size -// <id> dmac_chunksize_9 -#ifndef CONF_DMAC_CHUNKSIZE_9 -#define CONF_DMAC_CHUNKSIZE_9 0x0 -#endif - -// <o> Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// <i> Defines the size of one beat -// <id> dmac_beatsize_9 -#ifndef CONF_DMAC_BEATSIZE_9 -#define CONF_DMAC_BEATSIZE_9 0x0 -#endif - -// <o> Source Interface Identifier -// <0x0=> AHB_IF0 -// <0x1=> AHB_IF1 -// <i> Define the data is read through the system bus interface 0 or 1 -// <id> dma_src_interface_9 -#ifndef CONF_DMAC_SRC_INTERFACE_9 -#define CONF_DMAC_SRC_INTERFACE_9 0x0 -#endif - -// <o> Destination Interface Identifier -// <0x0=> AHB_IF0 -// <0x1=> AHB_IF1 -// <i> Define the data is written through the system bus interface 0 or 1 -// <id> dma_des_interface_9 -#ifndef CONF_DMAC_DES_INTERFACE_9 -#define CONF_DMAC_DES_INTERFACE_9 0x0 -#endif - -// <q> Source Address Increment -// <i> Indicates whether the source address incremented as beat size or not -// <id> dmac_srcinc_9 -#ifndef CONF_DMAC_SRCINC_9 -#define CONF_DMAC_SRCINC_9 0 -#endif - -// <q> Destination Address Increment -// <i> Indicates whether the destination address incremented as beat size or not -// <id> dmac_dstinc_9 -#ifndef CONF_DMAC_DSTINC_9 -#define CONF_DMAC_DSTINC_9 0 -#endif - -// <o> Transfer Type -// <0x0=> Memory to Memory Transfer -// <0x1=> Peripheral to Memory Transfer -// <0x2=> Memory to Peripheral Transfer -// <i> Define the data transfer type -// <id> dma_trans_type_9 -#ifndef CONF_DMAC_TRANS_TYPE_9 -#define CONF_DMAC_TRANS_TYPE_9 0x0 -#endif - -// <o> Trigger source -// <0xFF=> Software Trigger -// <0x00=> HSMCI TX/RX Trigger -// <0x01=> SPI0 TX Trigger -// <0x02=> SPI0 RX Trigger -// <0x03=> SPI1 TX Trigger -// <0x04=> SPI1 RX Trigger -// <0x05=> QSPI TX Trigger -// <0x06=> QSPI RX Trigger -// <0x07=> USART0 TX Trigger -// <0x08=> USART0 RX Trigger -// <0x09=> USART1 TX Trigger -// <0x0A=> USART1 RX Trigger -// <0x0B=> USART2 TX Trigger -// <0x0C=> USART2 RX Trigger -// <0x0D=> PWM0 TX Trigger -// <0x0E=> TWIHS0 TX Trigger -// <0x0F=> TWIHS0 RX Trigger -// <0x10=> TWIHS1 TX Trigger -// <0x11=> TWIHS1 RX Trigger -// <0x12=> TWIHS2 TX Trigger -// <0x13=> TWIHS2 RX Trigger -// <0x14=> UART0 TX Trigger -// <0x15=> UART0 RX Trigger -// <0x16=> UART1 TX Trigger -// <0x17=> UART1 RX Trigger -// <0x18=> UART2 TX Trigger -// <0x19=> UART2 RX Trigger -// <0x1A=> UART3 TX Trigger -// <0x1B=> UART3 RX Trigger -// <0x1C=> UART4 TX Trigger -// <0x1D=> UART4 RX Trigger -// <0x1E=> DACC TX Trigger -// <0x20=> SSC TX Trigger -// <0x21=> SSC RX Trigger -// <0x22=> PIOA RX Trigger -// <0x23=> AFEC0 RX Trigger -// <0x24=> AFEC1 RX Trigger -// <0x25=> AES TX Trigger -// <0x26=> AES RX Trigger -// <0x27=> PWM1 TX Trigger -// <0x28=> TC0 RX Trigger -// <0x29=> TC3 RX Trigger -// <0x2A=> TC6 RX Trigger -// <0x2B=> TC9 RX Trigger -// <0x2C=> I2SC0 TX Left Trigger -// <0x2D=> I2SC0 RX Left Trigger -// <0x2E=> I2SC1 TX Left Trigger -// <0x2F=> I2SC1 RX Left Trigger -// <0x30=> I2SC0 TX Right Trigger -// <0x31=> I2SC0 RX Right Trigger -// <0x32=> I2SC1 TX Right Trigger -// <0x33=> I2SC1 RX Right Trigger -// <i> Define the DMA trigger source -// <id> dmac_trifsrc_9 -#ifndef CONF_DMAC_TRIGSRC_9 -#define CONF_DMAC_TRIGSRC_9 0xff -#endif - -// </e> - -#if CONF_DMAC_TRANS_TYPE_9 == 0 -#define CONF_DMAC_TYPE_9 0 -#define CONF_DMAC_DSYNC_9 0 -#elif CONF_DMAC_TRANS_TYPE_9 == 1 -#define CONF_DMAC_TYPE_9 1 -#define CONF_DMAC_DSYNC_9 0 -#elif CONF_DMAC_TRANS_TYPE_9 == 2 -#define CONF_DMAC_TYPE_9 1 -#define CONF_DMAC_DSYNC_9 1 -#endif - -#if CONF_DMAC_TRIGSRC_9 == 0xFF -#define CONF_DMAC_SWREQ_9 1 -#else -#define CONF_DMAC_SWREQ_9 0 -#endif - -/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address - * or fixed destination address mode, source and destination addresses are incremented - * by 8-bit or 16-bit. - * Workaround: The user can fix the problem by setting the source addressing mode to - * use microblock and data striding with microblock stride set to 0 and data stride set to -1. - */ -#if (CONF_DMAC_CHANNEL_9_SETTINGS == 1 && CONF_DMAC_BEATSIZE_9 != 2 && ((!CONF_DMAC_SRCINC_9) || (!CONF_DMAC_DSTINC_9))) -#if (!CONF_DMAC_SRCINC_9) -#define CONF_DMAC_SRC_STRIDE_9 ((int16_t)(-1)) -#endif -#if (!CONF_DMAC_DSTINC_9) -#define CONF_DMAC_DES_STRIDE_9 ((int16_t)(-1)) -#endif -#endif - -#ifndef CONF_DMAC_SRC_STRIDE_9 -#define CONF_DMAC_SRC_STRIDE_9 0 -#endif - -#ifndef CONF_DMAC_DES_STRIDE_9 -#define CONF_DMAC_DES_STRIDE_9 0 -#endif - -// <e> Channel 10 settings -// <id> dmac_channel_10_settings -#ifndef CONF_DMAC_CHANNEL_10_SETTINGS -#define CONF_DMAC_CHANNEL_10_SETTINGS 0 -#endif - -// <o> Burst Size -// <0x0=> 1 burst size -// <0x1=> 4 burst size -// <0x2=> 8 burst size -// <0x3=> 16 burst size -// <i> Define the memory burst size -// <id> dmac_burstsize_10 -#ifndef CONF_DMAC_BURSTSIZE_10 -#define CONF_DMAC_BURSTSIZE_10 0x0 -#endif - -// <o> Chunk Size -// <0x0=> 1 data transferred -// <0x1=> 2 data transferred -// <0x2=> 4 data transferred -// <0x3=> 8 data transferred -// <0x4=> 16 data transferred -// <i> Define the peripheral chunk size -// <id> dmac_chunksize_10 -#ifndef CONF_DMAC_CHUNKSIZE_10 -#define CONF_DMAC_CHUNKSIZE_10 0x0 -#endif - -// <o> Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// <i> Defines the size of one beat -// <id> dmac_beatsize_10 -#ifndef CONF_DMAC_BEATSIZE_10 -#define CONF_DMAC_BEATSIZE_10 0x0 -#endif - -// <o> Source Interface Identifier -// <0x0=> AHB_IF0 -// <0x1=> AHB_IF1 -// <i> Define the data is read through the system bus interface 0 or 1 -// <id> dma_src_interface_10 -#ifndef CONF_DMAC_SRC_INTERFACE_10 -#define CONF_DMAC_SRC_INTERFACE_10 0x0 -#endif - -// <o> Destination Interface Identifier -// <0x0=> AHB_IF0 -// <0x1=> AHB_IF1 -// <i> Define the data is written through the system bus interface 0 or 1 -// <id> dma_des_interface_10 -#ifndef CONF_DMAC_DES_INTERFACE_10 -#define CONF_DMAC_DES_INTERFACE_10 0x0 -#endif - -// <q> Source Address Increment -// <i> Indicates whether the source address incremented as beat size or not -// <id> dmac_srcinc_10 -#ifndef CONF_DMAC_SRCINC_10 -#define CONF_DMAC_SRCINC_10 0 -#endif - -// <q> Destination Address Increment -// <i> Indicates whether the destination address incremented as beat size or not -// <id> dmac_dstinc_10 -#ifndef CONF_DMAC_DSTINC_10 -#define CONF_DMAC_DSTINC_10 0 -#endif - -// <o> Transfer Type -// <0x0=> Memory to Memory Transfer -// <0x1=> Peripheral to Memory Transfer -// <0x2=> Memory to Peripheral Transfer -// <i> Define the data transfer type -// <id> dma_trans_type_10 -#ifndef CONF_DMAC_TRANS_TYPE_10 -#define CONF_DMAC_TRANS_TYPE_10 0x0 -#endif - -// <o> Trigger source -// <0xFF=> Software Trigger -// <0x00=> HSMCI TX/RX Trigger -// <0x01=> SPI0 TX Trigger -// <0x02=> SPI0 RX Trigger -// <0x03=> SPI1 TX Trigger -// <0x04=> SPI1 RX Trigger -// <0x05=> QSPI TX Trigger -// <0x06=> QSPI RX Trigger -// <0x07=> USART0 TX Trigger -// <0x08=> USART0 RX Trigger -// <0x09=> USART1 TX Trigger -// <0x0A=> USART1 RX Trigger -// <0x0B=> USART2 TX Trigger -// <0x0C=> USART2 RX Trigger -// <0x0D=> PWM0 TX Trigger -// <0x0E=> TWIHS0 TX Trigger -// <0x0F=> TWIHS0 RX Trigger -// <0x10=> TWIHS1 TX Trigger -// <0x11=> TWIHS1 RX Trigger -// <0x12=> TWIHS2 TX Trigger -// <0x13=> TWIHS2 RX Trigger -// <0x14=> UART0 TX Trigger -// <0x15=> UART0 RX Trigger -// <0x16=> UART1 TX Trigger -// <0x17=> UART1 RX Trigger -// <0x18=> UART2 TX Trigger -// <0x19=> UART2 RX Trigger -// <0x1A=> UART3 TX Trigger -// <0x1B=> UART3 RX Trigger -// <0x1C=> UART4 TX Trigger -// <0x1D=> UART4 RX Trigger -// <0x1E=> DACC TX Trigger -// <0x20=> SSC TX Trigger -// <0x21=> SSC RX Trigger -// <0x22=> PIOA RX Trigger -// <0x23=> AFEC0 RX Trigger -// <0x24=> AFEC1 RX Trigger -// <0x25=> AES TX Trigger -// <0x26=> AES RX Trigger -// <0x27=> PWM1 TX Trigger -// <0x28=> TC0 RX Trigger -// <0x29=> TC3 RX Trigger -// <0x2A=> TC6 RX Trigger -// <0x2B=> TC9 RX Trigger -// <0x2C=> I2SC0 TX Left Trigger -// <0x2D=> I2SC0 RX Left Trigger -// <0x2E=> I2SC1 TX Left Trigger -// <0x2F=> I2SC1 RX Left Trigger -// <0x30=> I2SC0 TX Right Trigger -// <0x31=> I2SC0 RX Right Trigger -// <0x32=> I2SC1 TX Right Trigger -// <0x33=> I2SC1 RX Right Trigger -// <i> Define the DMA trigger source -// <id> dmac_trifsrc_10 -#ifndef CONF_DMAC_TRIGSRC_10 -#define CONF_DMAC_TRIGSRC_10 0xff -#endif - -// </e> - -#if CONF_DMAC_TRANS_TYPE_10 == 0 -#define CONF_DMAC_TYPE_10 0 -#define CONF_DMAC_DSYNC_10 0 -#elif CONF_DMAC_TRANS_TYPE_10 == 1 -#define CONF_DMAC_TYPE_10 1 -#define CONF_DMAC_DSYNC_10 0 -#elif CONF_DMAC_TRANS_TYPE_10 == 2 -#define CONF_DMAC_TYPE_10 1 -#define CONF_DMAC_DSYNC_10 1 -#endif - -#if CONF_DMAC_TRIGSRC_10 == 0xFF -#define CONF_DMAC_SWREQ_10 1 -#else -#define CONF_DMAC_SWREQ_10 0 -#endif - -/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address - * or fixed destination address mode, source and destination addresses are incremented - * by 8-bit or 16-bit. - * Workaround: The user can fix the problem by setting the source addressing mode to - * use microblock and data striding with microblock stride set to 0 and data stride set to -1. - */ -#if (CONF_DMAC_CHANNEL_10_SETTINGS == 1 && CONF_DMAC_BEATSIZE_10 != 2 \ - && ((!CONF_DMAC_SRCINC_10) || (!CONF_DMAC_DSTINC_10))) -#if (!CONF_DMAC_SRCINC_10) -#define CONF_DMAC_SRC_STRIDE_10 ((int16_t)(-1)) -#endif -#if (!CONF_DMAC_DSTINC_10) -#define CONF_DMAC_DES_STRIDE_10 ((int16_t)(-1)) -#endif -#endif - -#ifndef CONF_DMAC_SRC_STRIDE_10 -#define CONF_DMAC_SRC_STRIDE_10 0 -#endif - -#ifndef CONF_DMAC_DES_STRIDE_10 -#define CONF_DMAC_DES_STRIDE_10 0 -#endif - -// <e> Channel 11 settings -// <id> dmac_channel_11_settings -#ifndef CONF_DMAC_CHANNEL_11_SETTINGS -#define CONF_DMAC_CHANNEL_11_SETTINGS 0 -#endif - -// <o> Burst Size -// <0x0=> 1 burst size -// <0x1=> 4 burst size -// <0x2=> 8 burst size -// <0x3=> 16 burst size -// <i> Define the memory burst size -// <id> dmac_burstsize_11 -#ifndef CONF_DMAC_BURSTSIZE_11 -#define CONF_DMAC_BURSTSIZE_11 0x0 -#endif - -// <o> Chunk Size -// <0x0=> 1 data transferred -// <0x1=> 2 data transferred -// <0x2=> 4 data transferred -// <0x3=> 8 data transferred -// <0x4=> 16 data transferred -// <i> Define the peripheral chunk size -// <id> dmac_chunksize_11 -#ifndef CONF_DMAC_CHUNKSIZE_11 -#define CONF_DMAC_CHUNKSIZE_11 0x0 -#endif - -// <o> Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// <i> Defines the size of one beat -// <id> dmac_beatsize_11 -#ifndef CONF_DMAC_BEATSIZE_11 -#define CONF_DMAC_BEATSIZE_11 0x0 -#endif - -// <o> Source Interface Identifier -// <0x0=> AHB_IF0 -// <0x1=> AHB_IF1 -// <i> Define the data is read through the system bus interface 0 or 1 -// <id> dma_src_interface_11 -#ifndef CONF_DMAC_SRC_INTERFACE_11 -#define CONF_DMAC_SRC_INTERFACE_11 0x0 -#endif - -// <o> Destination Interface Identifier -// <0x0=> AHB_IF0 -// <0x1=> AHB_IF1 -// <i> Define the data is written through the system bus interface 0 or 1 -// <id> dma_des_interface_11 -#ifndef CONF_DMAC_DES_INTERFACE_11 -#define CONF_DMAC_DES_INTERFACE_11 0x0 -#endif - -// <q> Source Address Increment -// <i> Indicates whether the source address incremented as beat size or not -// <id> dmac_srcinc_11 -#ifndef CONF_DMAC_SRCINC_11 -#define CONF_DMAC_SRCINC_11 0 -#endif - -// <q> Destination Address Increment -// <i> Indicates whether the destination address incremented as beat size or not -// <id> dmac_dstinc_11 -#ifndef CONF_DMAC_DSTINC_11 -#define CONF_DMAC_DSTINC_11 0 -#endif - -// <o> Transfer Type -// <0x0=> Memory to Memory Transfer -// <0x1=> Peripheral to Memory Transfer -// <0x2=> Memory to Peripheral Transfer -// <i> Define the data transfer type -// <id> dma_trans_type_11 -#ifndef CONF_DMAC_TRANS_TYPE_11 -#define CONF_DMAC_TRANS_TYPE_11 0x0 -#endif - -// <o> Trigger source -// <0xFF=> Software Trigger -// <0x00=> HSMCI TX/RX Trigger -// <0x01=> SPI0 TX Trigger -// <0x02=> SPI0 RX Trigger -// <0x03=> SPI1 TX Trigger -// <0x04=> SPI1 RX Trigger -// <0x05=> QSPI TX Trigger -// <0x06=> QSPI RX Trigger -// <0x07=> USART0 TX Trigger -// <0x08=> USART0 RX Trigger -// <0x09=> USART1 TX Trigger -// <0x0A=> USART1 RX Trigger -// <0x0B=> USART2 TX Trigger -// <0x0C=> USART2 RX Trigger -// <0x0D=> PWM0 TX Trigger -// <0x0E=> TWIHS0 TX Trigger -// <0x0F=> TWIHS0 RX Trigger -// <0x10=> TWIHS1 TX Trigger -// <0x11=> TWIHS1 RX Trigger -// <0x12=> TWIHS2 TX Trigger -// <0x13=> TWIHS2 RX Trigger -// <0x14=> UART0 TX Trigger -// <0x15=> UART0 RX Trigger -// <0x16=> UART1 TX Trigger -// <0x17=> UART1 RX Trigger -// <0x18=> UART2 TX Trigger -// <0x19=> UART2 RX Trigger -// <0x1A=> UART3 TX Trigger -// <0x1B=> UART3 RX Trigger -// <0x1C=> UART4 TX Trigger -// <0x1D=> UART4 RX Trigger -// <0x1E=> DACC TX Trigger -// <0x20=> SSC TX Trigger -// <0x21=> SSC RX Trigger -// <0x22=> PIOA RX Trigger -// <0x23=> AFEC0 RX Trigger -// <0x24=> AFEC1 RX Trigger -// <0x25=> AES TX Trigger -// <0x26=> AES RX Trigger -// <0x27=> PWM1 TX Trigger -// <0x28=> TC0 RX Trigger -// <0x29=> TC3 RX Trigger -// <0x2A=> TC6 RX Trigger -// <0x2B=> TC9 RX Trigger -// <0x2C=> I2SC0 TX Left Trigger -// <0x2D=> I2SC0 RX Left Trigger -// <0x2E=> I2SC1 TX Left Trigger -// <0x2F=> I2SC1 RX Left Trigger -// <0x30=> I2SC0 TX Right Trigger -// <0x31=> I2SC0 RX Right Trigger -// <0x32=> I2SC1 TX Right Trigger -// <0x33=> I2SC1 RX Right Trigger -// <i> Define the DMA trigger source -// <id> dmac_trifsrc_11 -#ifndef CONF_DMAC_TRIGSRC_11 -#define CONF_DMAC_TRIGSRC_11 0xff -#endif - -// </e> - -#if CONF_DMAC_TRANS_TYPE_11 == 0 -#define CONF_DMAC_TYPE_11 0 -#define CONF_DMAC_DSYNC_11 0 -#elif CONF_DMAC_TRANS_TYPE_11 == 1 -#define CONF_DMAC_TYPE_11 1 -#define CONF_DMAC_DSYNC_11 0 -#elif CONF_DMAC_TRANS_TYPE_11 == 2 -#define CONF_DMAC_TYPE_11 1 -#define CONF_DMAC_DSYNC_11 1 -#endif - -#if CONF_DMAC_TRIGSRC_11 == 0xFF -#define CONF_DMAC_SWREQ_11 1 -#else -#define CONF_DMAC_SWREQ_11 0 -#endif - -/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address - * or fixed destination address mode, source and destination addresses are incremented - * by 8-bit or 16-bit. - * Workaround: The user can fix the problem by setting the source addressing mode to - * use microblock and data striding with microblock stride set to 0 and data stride set to -1. - */ -#if (CONF_DMAC_CHANNEL_11_SETTINGS == 1 && CONF_DMAC_BEATSIZE_11 != 2 \ - && ((!CONF_DMAC_SRCINC_11) || (!CONF_DMAC_DSTINC_11))) -#if (!CONF_DMAC_SRCINC_11) -#define CONF_DMAC_SRC_STRIDE_11 ((int16_t)(-1)) -#endif -#if (!CONF_DMAC_DSTINC_11) -#define CONF_DMAC_DES_STRIDE_11 ((int16_t)(-1)) -#endif -#endif - -#ifndef CONF_DMAC_SRC_STRIDE_11 -#define CONF_DMAC_SRC_STRIDE_11 0 -#endif - -#ifndef CONF_DMAC_DES_STRIDE_11 -#define CONF_DMAC_DES_STRIDE_11 0 -#endif - -// <e> Channel 12 settings -// <id> dmac_channel_12_settings -#ifndef CONF_DMAC_CHANNEL_12_SETTINGS -#define CONF_DMAC_CHANNEL_12_SETTINGS 0 -#endif - -// <o> Burst Size -// <0x0=> 1 burst size -// <0x1=> 4 burst size -// <0x2=> 8 burst size -// <0x3=> 16 burst size -// <i> Define the memory burst size -// <id> dmac_burstsize_12 -#ifndef CONF_DMAC_BURSTSIZE_12 -#define CONF_DMAC_BURSTSIZE_12 0x0 -#endif - -// <o> Chunk Size -// <0x0=> 1 data transferred -// <0x1=> 2 data transferred -// <0x2=> 4 data transferred -// <0x3=> 8 data transferred -// <0x4=> 16 data transferred -// <i> Define the peripheral chunk size -// <id> dmac_chunksize_12 -#ifndef CONF_DMAC_CHUNKSIZE_12 -#define CONF_DMAC_CHUNKSIZE_12 0x0 -#endif - -// <o> Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// <i> Defines the size of one beat -// <id> dmac_beatsize_12 -#ifndef CONF_DMAC_BEATSIZE_12 -#define CONF_DMAC_BEATSIZE_12 0x0 -#endif - -// <o> Source Interface Identifier -// <0x0=> AHB_IF0 -// <0x1=> AHB_IF1 -// <i> Define the data is read through the system bus interface 0 or 1 -// <id> dma_src_interface_12 -#ifndef CONF_DMAC_SRC_INTERFACE_12 -#define CONF_DMAC_SRC_INTERFACE_12 0x0 -#endif - -// <o> Destination Interface Identifier -// <0x0=> AHB_IF0 -// <0x1=> AHB_IF1 -// <i> Define the data is written through the system bus interface 0 or 1 -// <id> dma_des_interface_12 -#ifndef CONF_DMAC_DES_INTERFACE_12 -#define CONF_DMAC_DES_INTERFACE_12 0x0 -#endif - -// <q> Source Address Increment -// <i> Indicates whether the source address incremented as beat size or not -// <id> dmac_srcinc_12 -#ifndef CONF_DMAC_SRCINC_12 -#define CONF_DMAC_SRCINC_12 0 -#endif - -// <q> Destination Address Increment -// <i> Indicates whether the destination address incremented as beat size or not -// <id> dmac_dstinc_12 -#ifndef CONF_DMAC_DSTINC_12 -#define CONF_DMAC_DSTINC_12 0 -#endif - -// <o> Transfer Type -// <0x0=> Memory to Memory Transfer -// <0x1=> Peripheral to Memory Transfer -// <0x2=> Memory to Peripheral Transfer -// <i> Define the data transfer type -// <id> dma_trans_type_12 -#ifndef CONF_DMAC_TRANS_TYPE_12 -#define CONF_DMAC_TRANS_TYPE_12 0x0 -#endif - -// <o> Trigger source -// <0xFF=> Software Trigger -// <0x00=> HSMCI TX/RX Trigger -// <0x01=> SPI0 TX Trigger -// <0x02=> SPI0 RX Trigger -// <0x03=> SPI1 TX Trigger -// <0x04=> SPI1 RX Trigger -// <0x05=> QSPI TX Trigger -// <0x06=> QSPI RX Trigger -// <0x07=> USART0 TX Trigger -// <0x08=> USART0 RX Trigger -// <0x09=> USART1 TX Trigger -// <0x0A=> USART1 RX Trigger -// <0x0B=> USART2 TX Trigger -// <0x0C=> USART2 RX Trigger -// <0x0D=> PWM0 TX Trigger -// <0x0E=> TWIHS0 TX Trigger -// <0x0F=> TWIHS0 RX Trigger -// <0x10=> TWIHS1 TX Trigger -// <0x11=> TWIHS1 RX Trigger -// <0x12=> TWIHS2 TX Trigger -// <0x13=> TWIHS2 RX Trigger -// <0x14=> UART0 TX Trigger -// <0x15=> UART0 RX Trigger -// <0x16=> UART1 TX Trigger -// <0x17=> UART1 RX Trigger -// <0x18=> UART2 TX Trigger -// <0x19=> UART2 RX Trigger -// <0x1A=> UART3 TX Trigger -// <0x1B=> UART3 RX Trigger -// <0x1C=> UART4 TX Trigger -// <0x1D=> UART4 RX Trigger -// <0x1E=> DACC TX Trigger -// <0x20=> SSC TX Trigger -// <0x21=> SSC RX Trigger -// <0x22=> PIOA RX Trigger -// <0x23=> AFEC0 RX Trigger -// <0x24=> AFEC1 RX Trigger -// <0x25=> AES TX Trigger -// <0x26=> AES RX Trigger -// <0x27=> PWM1 TX Trigger -// <0x28=> TC0 RX Trigger -// <0x29=> TC3 RX Trigger -// <0x2A=> TC6 RX Trigger -// <0x2B=> TC9 RX Trigger -// <0x2C=> I2SC0 TX Left Trigger -// <0x2D=> I2SC0 RX Left Trigger -// <0x2E=> I2SC1 TX Left Trigger -// <0x2F=> I2SC1 RX Left Trigger -// <0x30=> I2SC0 TX Right Trigger -// <0x31=> I2SC0 RX Right Trigger -// <0x32=> I2SC1 TX Right Trigger -// <0x33=> I2SC1 RX Right Trigger -// <i> Define the DMA trigger source -// <id> dmac_trifsrc_12 -#ifndef CONF_DMAC_TRIGSRC_12 -#define CONF_DMAC_TRIGSRC_12 0xff -#endif - -// </e> - -#if CONF_DMAC_TRANS_TYPE_12 == 0 -#define CONF_DMAC_TYPE_12 0 -#define CONF_DMAC_DSYNC_12 0 -#elif CONF_DMAC_TRANS_TYPE_12 == 1 -#define CONF_DMAC_TYPE_12 1 -#define CONF_DMAC_DSYNC_12 0 -#elif CONF_DMAC_TRANS_TYPE_12 == 2 -#define CONF_DMAC_TYPE_12 1 -#define CONF_DMAC_DSYNC_12 1 -#endif - -#if CONF_DMAC_TRIGSRC_12 == 0xFF -#define CONF_DMAC_SWREQ_12 1 -#else -#define CONF_DMAC_SWREQ_12 0 -#endif - -/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address - * or fixed destination address mode, source and destination addresses are incremented - * by 8-bit or 16-bit. - * Workaround: The user can fix the problem by setting the source addressing mode to - * use microblock and data striding with microblock stride set to 0 and data stride set to -1. - */ -#if (CONF_DMAC_CHANNEL_12_SETTINGS == 1 && CONF_DMAC_BEATSIZE_12 != 2 \ - && ((!CONF_DMAC_SRCINC_12) || (!CONF_DMAC_DSTINC_12))) -#if (!CONF_DMAC_SRCINC_12) -#define CONF_DMAC_SRC_STRIDE_12 ((int16_t)(-1)) -#endif -#if (!CONF_DMAC_DSTINC_12) -#define CONF_DMAC_DES_STRIDE_12 ((int16_t)(-1)) -#endif -#endif - -#ifndef CONF_DMAC_SRC_STRIDE_12 -#define CONF_DMAC_SRC_STRIDE_12 0 -#endif - -#ifndef CONF_DMAC_DES_STRIDE_12 -#define CONF_DMAC_DES_STRIDE_12 0 -#endif - -// <e> Channel 13 settings -// <id> dmac_channel_13_settings -#ifndef CONF_DMAC_CHANNEL_13_SETTINGS -#define CONF_DMAC_CHANNEL_13_SETTINGS 0 -#endif - -// <o> Burst Size -// <0x0=> 1 burst size -// <0x1=> 4 burst size -// <0x2=> 8 burst size -// <0x3=> 16 burst size -// <i> Define the memory burst size -// <id> dmac_burstsize_13 -#ifndef CONF_DMAC_BURSTSIZE_13 -#define CONF_DMAC_BURSTSIZE_13 0x0 -#endif - -// <o> Chunk Size -// <0x0=> 1 data transferred -// <0x1=> 2 data transferred -// <0x2=> 4 data transferred -// <0x3=> 8 data transferred -// <0x4=> 16 data transferred -// <i> Define the peripheral chunk size -// <id> dmac_chunksize_13 -#ifndef CONF_DMAC_CHUNKSIZE_13 -#define CONF_DMAC_CHUNKSIZE_13 0x0 -#endif - -// <o> Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// <i> Defines the size of one beat -// <id> dmac_beatsize_13 -#ifndef CONF_DMAC_BEATSIZE_13 -#define CONF_DMAC_BEATSIZE_13 0x0 -#endif - -// <o> Source Interface Identifier -// <0x0=> AHB_IF0 -// <0x1=> AHB_IF1 -// <i> Define the data is read through the system bus interface 0 or 1 -// <id> dma_src_interface_13 -#ifndef CONF_DMAC_SRC_INTERFACE_13 -#define CONF_DMAC_SRC_INTERFACE_13 0x0 -#endif - -// <o> Destination Interface Identifier -// <0x0=> AHB_IF0 -// <0x1=> AHB_IF1 -// <i> Define the data is written through the system bus interface 0 or 1 -// <id> dma_des_interface_13 -#ifndef CONF_DMAC_DES_INTERFACE_13 -#define CONF_DMAC_DES_INTERFACE_13 0x0 -#endif - -// <q> Source Address Increment -// <i> Indicates whether the source address incremented as beat size or not -// <id> dmac_srcinc_13 -#ifndef CONF_DMAC_SRCINC_13 -#define CONF_DMAC_SRCINC_13 0 -#endif - -// <q> Destination Address Increment -// <i> Indicates whether the destination address incremented as beat size or not -// <id> dmac_dstinc_13 -#ifndef CONF_DMAC_DSTINC_13 -#define CONF_DMAC_DSTINC_13 0 -#endif - -// <o> Transfer Type -// <0x0=> Memory to Memory Transfer -// <0x1=> Peripheral to Memory Transfer -// <0x2=> Memory to Peripheral Transfer -// <i> Define the data transfer type -// <id> dma_trans_type_13 -#ifndef CONF_DMAC_TRANS_TYPE_13 -#define CONF_DMAC_TRANS_TYPE_13 0x0 -#endif - -// <o> Trigger source -// <0xFF=> Software Trigger -// <0x00=> HSMCI TX/RX Trigger -// <0x01=> SPI0 TX Trigger -// <0x02=> SPI0 RX Trigger -// <0x03=> SPI1 TX Trigger -// <0x04=> SPI1 RX Trigger -// <0x05=> QSPI TX Trigger -// <0x06=> QSPI RX Trigger -// <0x07=> USART0 TX Trigger -// <0x08=> USART0 RX Trigger -// <0x09=> USART1 TX Trigger -// <0x0A=> USART1 RX Trigger -// <0x0B=> USART2 TX Trigger -// <0x0C=> USART2 RX Trigger -// <0x0D=> PWM0 TX Trigger -// <0x0E=> TWIHS0 TX Trigger -// <0x0F=> TWIHS0 RX Trigger -// <0x10=> TWIHS1 TX Trigger -// <0x11=> TWIHS1 RX Trigger -// <0x12=> TWIHS2 TX Trigger -// <0x13=> TWIHS2 RX Trigger -// <0x14=> UART0 TX Trigger -// <0x15=> UART0 RX Trigger -// <0x16=> UART1 TX Trigger -// <0x17=> UART1 RX Trigger -// <0x18=> UART2 TX Trigger -// <0x19=> UART2 RX Trigger -// <0x1A=> UART3 TX Trigger -// <0x1B=> UART3 RX Trigger -// <0x1C=> UART4 TX Trigger -// <0x1D=> UART4 RX Trigger -// <0x1E=> DACC TX Trigger -// <0x20=> SSC TX Trigger -// <0x21=> SSC RX Trigger -// <0x22=> PIOA RX Trigger -// <0x23=> AFEC0 RX Trigger -// <0x24=> AFEC1 RX Trigger -// <0x25=> AES TX Trigger -// <0x26=> AES RX Trigger -// <0x27=> PWM1 TX Trigger -// <0x28=> TC0 RX Trigger -// <0x29=> TC3 RX Trigger -// <0x2A=> TC6 RX Trigger -// <0x2B=> TC9 RX Trigger -// <0x2C=> I2SC0 TX Left Trigger -// <0x2D=> I2SC0 RX Left Trigger -// <0x2E=> I2SC1 TX Left Trigger -// <0x2F=> I2SC1 RX Left Trigger -// <0x30=> I2SC0 TX Right Trigger -// <0x31=> I2SC0 RX Right Trigger -// <0x32=> I2SC1 TX Right Trigger -// <0x33=> I2SC1 RX Right Trigger -// <i> Define the DMA trigger source -// <id> dmac_trifsrc_13 -#ifndef CONF_DMAC_TRIGSRC_13 -#define CONF_DMAC_TRIGSRC_13 0xff -#endif - -// </e> - -#if CONF_DMAC_TRANS_TYPE_13 == 0 -#define CONF_DMAC_TYPE_13 0 -#define CONF_DMAC_DSYNC_13 0 -#elif CONF_DMAC_TRANS_TYPE_13 == 1 -#define CONF_DMAC_TYPE_13 1 -#define CONF_DMAC_DSYNC_13 0 -#elif CONF_DMAC_TRANS_TYPE_13 == 2 -#define CONF_DMAC_TYPE_13 1 -#define CONF_DMAC_DSYNC_13 1 -#endif - -#if CONF_DMAC_TRIGSRC_13 == 0xFF -#define CONF_DMAC_SWREQ_13 1 -#else -#define CONF_DMAC_SWREQ_13 0 -#endif - -/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address - * or fixed destination address mode, source and destination addresses are incremented - * by 8-bit or 16-bit. - * Workaround: The user can fix the problem by setting the source addressing mode to - * use microblock and data striding with microblock stride set to 0 and data stride set to -1. - */ -#if (CONF_DMAC_CHANNEL_13_SETTINGS == 1 && CONF_DMAC_BEATSIZE_13 != 2 \ - && ((!CONF_DMAC_SRCINC_13) || (!CONF_DMAC_DSTINC_13))) -#if (!CONF_DMAC_SRCINC_13) -#define CONF_DMAC_SRC_STRIDE_13 ((int16_t)(-1)) -#endif -#if (!CONF_DMAC_DSTINC_13) -#define CONF_DMAC_DES_STRIDE_13 ((int16_t)(-1)) -#endif -#endif - -#ifndef CONF_DMAC_SRC_STRIDE_13 -#define CONF_DMAC_SRC_STRIDE_13 0 -#endif - -#ifndef CONF_DMAC_DES_STRIDE_13 -#define CONF_DMAC_DES_STRIDE_13 0 -#endif - -// <e> Channel 14 settings -// <id> dmac_channel_14_settings -#ifndef CONF_DMAC_CHANNEL_14_SETTINGS -#define CONF_DMAC_CHANNEL_14_SETTINGS 0 -#endif - -// <o> Burst Size -// <0x0=> 1 burst size -// <0x1=> 4 burst size -// <0x2=> 8 burst size -// <0x3=> 16 burst size -// <i> Define the memory burst size -// <id> dmac_burstsize_14 -#ifndef CONF_DMAC_BURSTSIZE_14 -#define CONF_DMAC_BURSTSIZE_14 0x0 -#endif - -// <o> Chunk Size -// <0x0=> 1 data transferred -// <0x1=> 2 data transferred -// <0x2=> 4 data transferred -// <0x3=> 8 data transferred -// <0x4=> 16 data transferred -// <i> Define the peripheral chunk size -// <id> dmac_chunksize_14 -#ifndef CONF_DMAC_CHUNKSIZE_14 -#define CONF_DMAC_CHUNKSIZE_14 0x0 -#endif - -// <o> Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// <i> Defines the size of one beat -// <id> dmac_beatsize_14 -#ifndef CONF_DMAC_BEATSIZE_14 -#define CONF_DMAC_BEATSIZE_14 0x0 -#endif - -// <o> Source Interface Identifier -// <0x0=> AHB_IF0 -// <0x1=> AHB_IF1 -// <i> Define the data is read through the system bus interface 0 or 1 -// <id> dma_src_interface_14 -#ifndef CONF_DMAC_SRC_INTERFACE_14 -#define CONF_DMAC_SRC_INTERFACE_14 0x0 -#endif - -// <o> Destination Interface Identifier -// <0x0=> AHB_IF0 -// <0x1=> AHB_IF1 -// <i> Define the data is written through the system bus interface 0 or 1 -// <id> dma_des_interface_14 -#ifndef CONF_DMAC_DES_INTERFACE_14 -#define CONF_DMAC_DES_INTERFACE_14 0x0 -#endif - -// <q> Source Address Increment -// <i> Indicates whether the source address incremented as beat size or not -// <id> dmac_srcinc_14 -#ifndef CONF_DMAC_SRCINC_14 -#define CONF_DMAC_SRCINC_14 0 -#endif - -// <q> Destination Address Increment -// <i> Indicates whether the destination address incremented as beat size or not -// <id> dmac_dstinc_14 -#ifndef CONF_DMAC_DSTINC_14 -#define CONF_DMAC_DSTINC_14 0 -#endif - -// <o> Transfer Type -// <0x0=> Memory to Memory Transfer -// <0x1=> Peripheral to Memory Transfer -// <0x2=> Memory to Peripheral Transfer -// <i> Define the data transfer type -// <id> dma_trans_type_14 -#ifndef CONF_DMAC_TRANS_TYPE_14 -#define CONF_DMAC_TRANS_TYPE_14 0x0 -#endif - -// <o> Trigger source -// <0xFF=> Software Trigger -// <0x00=> HSMCI TX/RX Trigger -// <0x01=> SPI0 TX Trigger -// <0x02=> SPI0 RX Trigger -// <0x03=> SPI1 TX Trigger -// <0x04=> SPI1 RX Trigger -// <0x05=> QSPI TX Trigger -// <0x06=> QSPI RX Trigger -// <0x07=> USART0 TX Trigger -// <0x08=> USART0 RX Trigger -// <0x09=> USART1 TX Trigger -// <0x0A=> USART1 RX Trigger -// <0x0B=> USART2 TX Trigger -// <0x0C=> USART2 RX Trigger -// <0x0D=> PWM0 TX Trigger -// <0x0E=> TWIHS0 TX Trigger -// <0x0F=> TWIHS0 RX Trigger -// <0x10=> TWIHS1 TX Trigger -// <0x11=> TWIHS1 RX Trigger -// <0x12=> TWIHS2 TX Trigger -// <0x13=> TWIHS2 RX Trigger -// <0x14=> UART0 TX Trigger -// <0x15=> UART0 RX Trigger -// <0x16=> UART1 TX Trigger -// <0x17=> UART1 RX Trigger -// <0x18=> UART2 TX Trigger -// <0x19=> UART2 RX Trigger -// <0x1A=> UART3 TX Trigger -// <0x1B=> UART3 RX Trigger -// <0x1C=> UART4 TX Trigger -// <0x1D=> UART4 RX Trigger -// <0x1E=> DACC TX Trigger -// <0x20=> SSC TX Trigger -// <0x21=> SSC RX Trigger -// <0x22=> PIOA RX Trigger -// <0x23=> AFEC0 RX Trigger -// <0x24=> AFEC1 RX Trigger -// <0x25=> AES TX Trigger -// <0x26=> AES RX Trigger -// <0x27=> PWM1 TX Trigger -// <0x28=> TC0 RX Trigger -// <0x29=> TC3 RX Trigger -// <0x2A=> TC6 RX Trigger -// <0x2B=> TC9 RX Trigger -// <0x2C=> I2SC0 TX Left Trigger -// <0x2D=> I2SC0 RX Left Trigger -// <0x2E=> I2SC1 TX Left Trigger -// <0x2F=> I2SC1 RX Left Trigger -// <0x30=> I2SC0 TX Right Trigger -// <0x31=> I2SC0 RX Right Trigger -// <0x32=> I2SC1 TX Right Trigger -// <0x33=> I2SC1 RX Right Trigger -// <i> Define the DMA trigger source -// <id> dmac_trifsrc_14 -#ifndef CONF_DMAC_TRIGSRC_14 -#define CONF_DMAC_TRIGSRC_14 0xff -#endif - -// </e> - -#if CONF_DMAC_TRANS_TYPE_14 == 0 -#define CONF_DMAC_TYPE_14 0 -#define CONF_DMAC_DSYNC_14 0 -#elif CONF_DMAC_TRANS_TYPE_14 == 1 -#define CONF_DMAC_TYPE_14 1 -#define CONF_DMAC_DSYNC_14 0 -#elif CONF_DMAC_TRANS_TYPE_14 == 2 -#define CONF_DMAC_TYPE_14 1 -#define CONF_DMAC_DSYNC_14 1 -#endif - -#if CONF_DMAC_TRIGSRC_14 == 0xFF -#define CONF_DMAC_SWREQ_14 1 -#else -#define CONF_DMAC_SWREQ_14 0 -#endif - -/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address - * or fixed destination address mode, source and destination addresses are incremented - * by 8-bit or 16-bit. - * Workaround: The user can fix the problem by setting the source addressing mode to - * use microblock and data striding with microblock stride set to 0 and data stride set to -1. - */ -#if (CONF_DMAC_CHANNEL_14_SETTINGS == 1 && CONF_DMAC_BEATSIZE_14 != 2 \ - && ((!CONF_DMAC_SRCINC_14) || (!CONF_DMAC_DSTINC_14))) -#if (!CONF_DMAC_SRCINC_14) -#define CONF_DMAC_SRC_STRIDE_14 ((int16_t)(-1)) -#endif -#if (!CONF_DMAC_DSTINC_14) -#define CONF_DMAC_DES_STRIDE_14 ((int16_t)(-1)) -#endif -#endif - -#ifndef CONF_DMAC_SRC_STRIDE_14 -#define CONF_DMAC_SRC_STRIDE_14 0 -#endif - -#ifndef CONF_DMAC_DES_STRIDE_14 -#define CONF_DMAC_DES_STRIDE_14 0 -#endif - -// <e> Channel 15 settings -// <id> dmac_channel_15_settings -#ifndef CONF_DMAC_CHANNEL_15_SETTINGS -#define CONF_DMAC_CHANNEL_15_SETTINGS 0 -#endif - -// <o> Burst Size -// <0x0=> 1 burst size -// <0x1=> 4 burst size -// <0x2=> 8 burst size -// <0x3=> 16 burst size -// <i> Define the memory burst size -// <id> dmac_burstsize_15 -#ifndef CONF_DMAC_BURSTSIZE_15 -#define CONF_DMAC_BURSTSIZE_15 0x0 -#endif - -// <o> Chunk Size -// <0x0=> 1 data transferred -// <0x1=> 2 data transferred -// <0x2=> 4 data transferred -// <0x3=> 8 data transferred -// <0x4=> 16 data transferred -// <i> Define the peripheral chunk size -// <id> dmac_chunksize_15 -#ifndef CONF_DMAC_CHUNKSIZE_15 -#define CONF_DMAC_CHUNKSIZE_15 0x0 -#endif - -// <o> Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// <i> Defines the size of one beat -// <id> dmac_beatsize_15 -#ifndef CONF_DMAC_BEATSIZE_15 -#define CONF_DMAC_BEATSIZE_15 0x0 -#endif - -// <o> Source Interface Identifier -// <0x0=> AHB_IF0 -// <0x1=> AHB_IF1 -// <i> Define the data is read through the system bus interface 0 or 1 -// <id> dma_src_interface_15 -#ifndef CONF_DMAC_SRC_INTERFACE_15 -#define CONF_DMAC_SRC_INTERFACE_15 0x0 -#endif - -// <o> Destination Interface Identifier -// <0x0=> AHB_IF0 -// <0x1=> AHB_IF1 -// <i> Define the data is written through the system bus interface 0 or 1 -// <id> dma_des_interface_15 -#ifndef CONF_DMAC_DES_INTERFACE_15 -#define CONF_DMAC_DES_INTERFACE_15 0x0 -#endif - -// <q> Source Address Increment -// <i> Indicates whether the source address incremented as beat size or not -// <id> dmac_srcinc_15 -#ifndef CONF_DMAC_SRCINC_15 -#define CONF_DMAC_SRCINC_15 0 -#endif - -// <q> Destination Address Increment -// <i> Indicates whether the destination address incremented as beat size or not -// <id> dmac_dstinc_15 -#ifndef CONF_DMAC_DSTINC_15 -#define CONF_DMAC_DSTINC_15 0 -#endif - -// <o> Transfer Type -// <0x0=> Memory to Memory Transfer -// <0x1=> Peripheral to Memory Transfer -// <0x2=> Memory to Peripheral Transfer -// <i> Define the data transfer type -// <id> dma_trans_type_15 -#ifndef CONF_DMAC_TRANS_TYPE_15 -#define CONF_DMAC_TRANS_TYPE_15 0x0 -#endif - -// <o> Trigger source -// <0xFF=> Software Trigger -// <0x00=> HSMCI TX/RX Trigger -// <0x01=> SPI0 TX Trigger -// <0x02=> SPI0 RX Trigger -// <0x03=> SPI1 TX Trigger -// <0x04=> SPI1 RX Trigger -// <0x05=> QSPI TX Trigger -// <0x06=> QSPI RX Trigger -// <0x07=> USART0 TX Trigger -// <0x08=> USART0 RX Trigger -// <0x09=> USART1 TX Trigger -// <0x0A=> USART1 RX Trigger -// <0x0B=> USART2 TX Trigger -// <0x0C=> USART2 RX Trigger -// <0x0D=> PWM0 TX Trigger -// <0x0E=> TWIHS0 TX Trigger -// <0x0F=> TWIHS0 RX Trigger -// <0x10=> TWIHS1 TX Trigger -// <0x11=> TWIHS1 RX Trigger -// <0x12=> TWIHS2 TX Trigger -// <0x13=> TWIHS2 RX Trigger -// <0x14=> UART0 TX Trigger -// <0x15=> UART0 RX Trigger -// <0x16=> UART1 TX Trigger -// <0x17=> UART1 RX Trigger -// <0x18=> UART2 TX Trigger -// <0x19=> UART2 RX Trigger -// <0x1A=> UART3 TX Trigger -// <0x1B=> UART3 RX Trigger -// <0x1C=> UART4 TX Trigger -// <0x1D=> UART4 RX Trigger -// <0x1E=> DACC TX Trigger -// <0x20=> SSC TX Trigger -// <0x21=> SSC RX Trigger -// <0x22=> PIOA RX Trigger -// <0x23=> AFEC0 RX Trigger -// <0x24=> AFEC1 RX Trigger -// <0x25=> AES TX Trigger -// <0x26=> AES RX Trigger -// <0x27=> PWM1 TX Trigger -// <0x28=> TC0 RX Trigger -// <0x29=> TC3 RX Trigger -// <0x2A=> TC6 RX Trigger -// <0x2B=> TC9 RX Trigger -// <0x2C=> I2SC0 TX Left Trigger -// <0x2D=> I2SC0 RX Left Trigger -// <0x2E=> I2SC1 TX Left Trigger -// <0x2F=> I2SC1 RX Left Trigger -// <0x30=> I2SC0 TX Right Trigger -// <0x31=> I2SC0 RX Right Trigger -// <0x32=> I2SC1 TX Right Trigger -// <0x33=> I2SC1 RX Right Trigger -// <i> Define the DMA trigger source -// <id> dmac_trifsrc_15 -#ifndef CONF_DMAC_TRIGSRC_15 -#define CONF_DMAC_TRIGSRC_15 0xff -#endif - -// </e> - -#if CONF_DMAC_TRANS_TYPE_15 == 0 -#define CONF_DMAC_TYPE_15 0 -#define CONF_DMAC_DSYNC_15 0 -#elif CONF_DMAC_TRANS_TYPE_15 == 1 -#define CONF_DMAC_TYPE_15 1 -#define CONF_DMAC_DSYNC_15 0 -#elif CONF_DMAC_TRANS_TYPE_15 == 2 -#define CONF_DMAC_TYPE_15 1 -#define CONF_DMAC_DSYNC_15 1 -#endif - -#if CONF_DMAC_TRIGSRC_15 == 0xFF -#define CONF_DMAC_SWREQ_15 1 -#else -#define CONF_DMAC_SWREQ_15 0 -#endif - -/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address - * or fixed destination address mode, source and destination addresses are incremented - * by 8-bit or 16-bit. - * Workaround: The user can fix the problem by setting the source addressing mode to - * use microblock and data striding with microblock stride set to 0 and data stride set to -1. - */ -#if (CONF_DMAC_CHANNEL_15_SETTINGS == 1 && CONF_DMAC_BEATSIZE_15 != 2 \ - && ((!CONF_DMAC_SRCINC_15) || (!CONF_DMAC_DSTINC_15))) -#if (!CONF_DMAC_SRCINC_15) -#define CONF_DMAC_SRC_STRIDE_15 ((int16_t)(-1)) -#endif -#if (!CONF_DMAC_DSTINC_15) -#define CONF_DMAC_DES_STRIDE_15 ((int16_t)(-1)) -#endif -#endif - -#ifndef CONF_DMAC_SRC_STRIDE_15 -#define CONF_DMAC_SRC_STRIDE_15 0 -#endif - -#ifndef CONF_DMAC_DES_STRIDE_15 -#define CONF_DMAC_DES_STRIDE_15 0 -#endif - -// <e> Channel 16 settings -// <id> dmac_channel_16_settings -#ifndef CONF_DMAC_CHANNEL_16_SETTINGS -#define CONF_DMAC_CHANNEL_16_SETTINGS 0 -#endif - -// <o> Burst Size -// <0x0=> 1 burst size -// <0x1=> 4 burst size -// <0x2=> 8 burst size -// <0x3=> 16 burst size -// <i> Define the memory burst size -// <id> dmac_burstsize_16 -#ifndef CONF_DMAC_BURSTSIZE_16 -#define CONF_DMAC_BURSTSIZE_16 0x0 -#endif - -// <o> Chunk Size -// <0x0=> 1 data transferred -// <0x1=> 2 data transferred -// <0x2=> 4 data transferred -// <0x3=> 8 data transferred -// <0x4=> 16 data transferred -// <i> Define the peripheral chunk size -// <id> dmac_chunksize_16 -#ifndef CONF_DMAC_CHUNKSIZE_16 -#define CONF_DMAC_CHUNKSIZE_16 0x0 -#endif - -// <o> Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// <i> Defines the size of one beat -// <id> dmac_beatsize_16 -#ifndef CONF_DMAC_BEATSIZE_16 -#define CONF_DMAC_BEATSIZE_16 0x0 -#endif - -// <o> Source Interface Identifier -// <0x0=> AHB_IF0 -// <0x1=> AHB_IF1 -// <i> Define the data is read through the system bus interface 0 or 1 -// <id> dma_src_interface_16 -#ifndef CONF_DMAC_SRC_INTERFACE_16 -#define CONF_DMAC_SRC_INTERFACE_16 0x0 -#endif - -// <o> Destination Interface Identifier -// <0x0=> AHB_IF0 -// <0x1=> AHB_IF1 -// <i> Define the data is written through the system bus interface 0 or 1 -// <id> dma_des_interface_16 -#ifndef CONF_DMAC_DES_INTERFACE_16 -#define CONF_DMAC_DES_INTERFACE_16 0x0 -#endif - -// <q> Source Address Increment -// <i> Indicates whether the source address incremented as beat size or not -// <id> dmac_srcinc_16 -#ifndef CONF_DMAC_SRCINC_16 -#define CONF_DMAC_SRCINC_16 0 -#endif - -// <q> Destination Address Increment -// <i> Indicates whether the destination address incremented as beat size or not -// <id> dmac_dstinc_16 -#ifndef CONF_DMAC_DSTINC_16 -#define CONF_DMAC_DSTINC_16 0 -#endif - -// <o> Transfer Type -// <0x0=> Memory to Memory Transfer -// <0x1=> Peripheral to Memory Transfer -// <0x2=> Memory to Peripheral Transfer -// <i> Define the data transfer type -// <id> dma_trans_type_16 -#ifndef CONF_DMAC_TRANS_TYPE_16 -#define CONF_DMAC_TRANS_TYPE_16 0x0 -#endif - -// <o> Trigger source -// <0xFF=> Software Trigger -// <0x00=> HSMCI TX/RX Trigger -// <0x01=> SPI0 TX Trigger -// <0x02=> SPI0 RX Trigger -// <0x03=> SPI1 TX Trigger -// <0x04=> SPI1 RX Trigger -// <0x05=> QSPI TX Trigger -// <0x06=> QSPI RX Trigger -// <0x07=> USART0 TX Trigger -// <0x08=> USART0 RX Trigger -// <0x09=> USART1 TX Trigger -// <0x0A=> USART1 RX Trigger -// <0x0B=> USART2 TX Trigger -// <0x0C=> USART2 RX Trigger -// <0x0D=> PWM0 TX Trigger -// <0x0E=> TWIHS0 TX Trigger -// <0x0F=> TWIHS0 RX Trigger -// <0x10=> TWIHS1 TX Trigger -// <0x11=> TWIHS1 RX Trigger -// <0x12=> TWIHS2 TX Trigger -// <0x13=> TWIHS2 RX Trigger -// <0x14=> UART0 TX Trigger -// <0x15=> UART0 RX Trigger -// <0x16=> UART1 TX Trigger -// <0x17=> UART1 RX Trigger -// <0x18=> UART2 TX Trigger -// <0x19=> UART2 RX Trigger -// <0x1A=> UART3 TX Trigger -// <0x1B=> UART3 RX Trigger -// <0x1C=> UART4 TX Trigger -// <0x1D=> UART4 RX Trigger -// <0x1E=> DACC TX Trigger -// <0x20=> SSC TX Trigger -// <0x21=> SSC RX Trigger -// <0x22=> PIOA RX Trigger -// <0x23=> AFEC0 RX Trigger -// <0x24=> AFEC1 RX Trigger -// <0x25=> AES TX Trigger -// <0x26=> AES RX Trigger -// <0x27=> PWM1 TX Trigger -// <0x28=> TC0 RX Trigger -// <0x29=> TC3 RX Trigger -// <0x2A=> TC6 RX Trigger -// <0x2B=> TC9 RX Trigger -// <0x2C=> I2SC0 TX Left Trigger -// <0x2D=> I2SC0 RX Left Trigger -// <0x2E=> I2SC1 TX Left Trigger -// <0x2F=> I2SC1 RX Left Trigger -// <0x30=> I2SC0 TX Right Trigger -// <0x31=> I2SC0 RX Right Trigger -// <0x32=> I2SC1 TX Right Trigger -// <0x33=> I2SC1 RX Right Trigger -// <i> Define the DMA trigger source -// <id> dmac_trifsrc_16 -#ifndef CONF_DMAC_TRIGSRC_16 -#define CONF_DMAC_TRIGSRC_16 0xff -#endif - -// </e> - -#if CONF_DMAC_TRANS_TYPE_16 == 0 -#define CONF_DMAC_TYPE_16 0 -#define CONF_DMAC_DSYNC_16 0 -#elif CONF_DMAC_TRANS_TYPE_16 == 1 -#define CONF_DMAC_TYPE_16 1 -#define CONF_DMAC_DSYNC_16 0 -#elif CONF_DMAC_TRANS_TYPE_16 == 2 -#define CONF_DMAC_TYPE_16 1 -#define CONF_DMAC_DSYNC_16 1 -#endif - -#if CONF_DMAC_TRIGSRC_16 == 0xFF -#define CONF_DMAC_SWREQ_16 1 -#else -#define CONF_DMAC_SWREQ_16 0 -#endif - -/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address - * or fixed destination address mode, source and destination addresses are incremented - * by 8-bit or 16-bit. - * Workaround: The user can fix the problem by setting the source addressing mode to - * use microblock and data striding with microblock stride set to 0 and data stride set to -1. - */ -#if (CONF_DMAC_CHANNEL_16_SETTINGS == 1 && CONF_DMAC_BEATSIZE_16 != 2 \ - && ((!CONF_DMAC_SRCINC_16) || (!CONF_DMAC_DSTINC_16))) -#if (!CONF_DMAC_SRCINC_16) -#define CONF_DMAC_SRC_STRIDE_16 ((int16_t)(-1)) -#endif -#if (!CONF_DMAC_DSTINC_16) -#define CONF_DMAC_DES_STRIDE_16 ((int16_t)(-1)) -#endif -#endif - -#ifndef CONF_DMAC_SRC_STRIDE_16 -#define CONF_DMAC_SRC_STRIDE_16 0 -#endif - -#ifndef CONF_DMAC_DES_STRIDE_16 -#define CONF_DMAC_DES_STRIDE_16 0 -#endif - -// <e> Channel 17 settings -// <id> dmac_channel_17_settings -#ifndef CONF_DMAC_CHANNEL_17_SETTINGS -#define CONF_DMAC_CHANNEL_17_SETTINGS 0 -#endif - -// <o> Burst Size -// <0x0=> 1 burst size -// <0x1=> 4 burst size -// <0x2=> 8 burst size -// <0x3=> 16 burst size -// <i> Define the memory burst size -// <id> dmac_burstsize_17 -#ifndef CONF_DMAC_BURSTSIZE_17 -#define CONF_DMAC_BURSTSIZE_17 0x0 -#endif - -// <o> Chunk Size -// <0x0=> 1 data transferred -// <0x1=> 2 data transferred -// <0x2=> 4 data transferred -// <0x3=> 8 data transferred -// <0x4=> 16 data transferred -// <i> Define the peripheral chunk size -// <id> dmac_chunksize_17 -#ifndef CONF_DMAC_CHUNKSIZE_17 -#define CONF_DMAC_CHUNKSIZE_17 0x0 -#endif - -// <o> Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// <i> Defines the size of one beat -// <id> dmac_beatsize_17 -#ifndef CONF_DMAC_BEATSIZE_17 -#define CONF_DMAC_BEATSIZE_17 0x0 -#endif - -// <o> Source Interface Identifier -// <0x0=> AHB_IF0 -// <0x1=> AHB_IF1 -// <i> Define the data is read through the system bus interface 0 or 1 -// <id> dma_src_interface_17 -#ifndef CONF_DMAC_SRC_INTERFACE_17 -#define CONF_DMAC_SRC_INTERFACE_17 0x0 -#endif - -// <o> Destination Interface Identifier -// <0x0=> AHB_IF0 -// <0x1=> AHB_IF1 -// <i> Define the data is written through the system bus interface 0 or 1 -// <id> dma_des_interface_17 -#ifndef CONF_DMAC_DES_INTERFACE_17 -#define CONF_DMAC_DES_INTERFACE_17 0x0 -#endif - -// <q> Source Address Increment -// <i> Indicates whether the source address incremented as beat size or not -// <id> dmac_srcinc_17 -#ifndef CONF_DMAC_SRCINC_17 -#define CONF_DMAC_SRCINC_17 0 -#endif - -// <q> Destination Address Increment -// <i> Indicates whether the destination address incremented as beat size or not -// <id> dmac_dstinc_17 -#ifndef CONF_DMAC_DSTINC_17 -#define CONF_DMAC_DSTINC_17 0 -#endif - -// <o> Transfer Type -// <0x0=> Memory to Memory Transfer -// <0x1=> Peripheral to Memory Transfer -// <0x2=> Memory to Peripheral Transfer -// <i> Define the data transfer type -// <id> dma_trans_type_17 -#ifndef CONF_DMAC_TRANS_TYPE_17 -#define CONF_DMAC_TRANS_TYPE_17 0x0 -#endif - -// <o> Trigger source -// <0xFF=> Software Trigger -// <0x00=> HSMCI TX/RX Trigger -// <0x01=> SPI0 TX Trigger -// <0x02=> SPI0 RX Trigger -// <0x03=> SPI1 TX Trigger -// <0x04=> SPI1 RX Trigger -// <0x05=> QSPI TX Trigger -// <0x06=> QSPI RX Trigger -// <0x07=> USART0 TX Trigger -// <0x08=> USART0 RX Trigger -// <0x09=> USART1 TX Trigger -// <0x0A=> USART1 RX Trigger -// <0x0B=> USART2 TX Trigger -// <0x0C=> USART2 RX Trigger -// <0x0D=> PWM0 TX Trigger -// <0x0E=> TWIHS0 TX Trigger -// <0x0F=> TWIHS0 RX Trigger -// <0x10=> TWIHS1 TX Trigger -// <0x11=> TWIHS1 RX Trigger -// <0x12=> TWIHS2 TX Trigger -// <0x13=> TWIHS2 RX Trigger -// <0x14=> UART0 TX Trigger -// <0x15=> UART0 RX Trigger -// <0x16=> UART1 TX Trigger -// <0x17=> UART1 RX Trigger -// <0x18=> UART2 TX Trigger -// <0x19=> UART2 RX Trigger -// <0x1A=> UART3 TX Trigger -// <0x1B=> UART3 RX Trigger -// <0x1C=> UART4 TX Trigger -// <0x1D=> UART4 RX Trigger -// <0x1E=> DACC TX Trigger -// <0x20=> SSC TX Trigger -// <0x21=> SSC RX Trigger -// <0x22=> PIOA RX Trigger -// <0x23=> AFEC0 RX Trigger -// <0x24=> AFEC1 RX Trigger -// <0x25=> AES TX Trigger -// <0x26=> AES RX Trigger -// <0x27=> PWM1 TX Trigger -// <0x28=> TC0 RX Trigger -// <0x29=> TC3 RX Trigger -// <0x2A=> TC6 RX Trigger -// <0x2B=> TC9 RX Trigger -// <0x2C=> I2SC0 TX Left Trigger -// <0x2D=> I2SC0 RX Left Trigger -// <0x2E=> I2SC1 TX Left Trigger -// <0x2F=> I2SC1 RX Left Trigger -// <0x30=> I2SC0 TX Right Trigger -// <0x31=> I2SC0 RX Right Trigger -// <0x32=> I2SC1 TX Right Trigger -// <0x33=> I2SC1 RX Right Trigger -// <i> Define the DMA trigger source -// <id> dmac_trifsrc_17 -#ifndef CONF_DMAC_TRIGSRC_17 -#define CONF_DMAC_TRIGSRC_17 0xff -#endif - -// </e> - -#if CONF_DMAC_TRANS_TYPE_17 == 0 -#define CONF_DMAC_TYPE_17 0 -#define CONF_DMAC_DSYNC_17 0 -#elif CONF_DMAC_TRANS_TYPE_17 == 1 -#define CONF_DMAC_TYPE_17 1 -#define CONF_DMAC_DSYNC_17 0 -#elif CONF_DMAC_TRANS_TYPE_17 == 2 -#define CONF_DMAC_TYPE_17 1 -#define CONF_DMAC_DSYNC_17 1 -#endif - -#if CONF_DMAC_TRIGSRC_17 == 0xFF -#define CONF_DMAC_SWREQ_17 1 -#else -#define CONF_DMAC_SWREQ_17 0 -#endif - -/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address - * or fixed destination address mode, source and destination addresses are incremented - * by 8-bit or 16-bit. - * Workaround: The user can fix the problem by setting the source addressing mode to - * use microblock and data striding with microblock stride set to 0 and data stride set to -1. - */ -#if (CONF_DMAC_CHANNEL_17_SETTINGS == 1 && CONF_DMAC_BEATSIZE_17 != 2 \ - && ((!CONF_DMAC_SRCINC_17) || (!CONF_DMAC_DSTINC_17))) -#if (!CONF_DMAC_SRCINC_17) -#define CONF_DMAC_SRC_STRIDE_17 ((int16_t)(-1)) -#endif -#if (!CONF_DMAC_DSTINC_17) -#define CONF_DMAC_DES_STRIDE_17 ((int16_t)(-1)) -#endif -#endif - -#ifndef CONF_DMAC_SRC_STRIDE_17 -#define CONF_DMAC_SRC_STRIDE_17 0 -#endif - -#ifndef CONF_DMAC_DES_STRIDE_17 -#define CONF_DMAC_DES_STRIDE_17 0 -#endif - -// <e> Channel 18 settings -// <id> dmac_channel_18_settings -#ifndef CONF_DMAC_CHANNEL_18_SETTINGS -#define CONF_DMAC_CHANNEL_18_SETTINGS 0 -#endif - -// <o> Burst Size -// <0x0=> 1 burst size -// <0x1=> 4 burst size -// <0x2=> 8 burst size -// <0x3=> 16 burst size -// <i> Define the memory burst size -// <id> dmac_burstsize_18 -#ifndef CONF_DMAC_BURSTSIZE_18 -#define CONF_DMAC_BURSTSIZE_18 0x0 -#endif - -// <o> Chunk Size -// <0x0=> 1 data transferred -// <0x1=> 2 data transferred -// <0x2=> 4 data transferred -// <0x3=> 8 data transferred -// <0x4=> 16 data transferred -// <i> Define the peripheral chunk size -// <id> dmac_chunksize_18 -#ifndef CONF_DMAC_CHUNKSIZE_18 -#define CONF_DMAC_CHUNKSIZE_18 0x0 -#endif - -// <o> Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// <i> Defines the size of one beat -// <id> dmac_beatsize_18 -#ifndef CONF_DMAC_BEATSIZE_18 -#define CONF_DMAC_BEATSIZE_18 0x0 -#endif - -// <o> Source Interface Identifier -// <0x0=> AHB_IF0 -// <0x1=> AHB_IF1 -// <i> Define the data is read through the system bus interface 0 or 1 -// <id> dma_src_interface_18 -#ifndef CONF_DMAC_SRC_INTERFACE_18 -#define CONF_DMAC_SRC_INTERFACE_18 0x0 -#endif - -// <o> Destination Interface Identifier -// <0x0=> AHB_IF0 -// <0x1=> AHB_IF1 -// <i> Define the data is written through the system bus interface 0 or 1 -// <id> dma_des_interface_18 -#ifndef CONF_DMAC_DES_INTERFACE_18 -#define CONF_DMAC_DES_INTERFACE_18 0x0 -#endif - -// <q> Source Address Increment -// <i> Indicates whether the source address incremented as beat size or not -// <id> dmac_srcinc_18 -#ifndef CONF_DMAC_SRCINC_18 -#define CONF_DMAC_SRCINC_18 0 -#endif - -// <q> Destination Address Increment -// <i> Indicates whether the destination address incremented as beat size or not -// <id> dmac_dstinc_18 -#ifndef CONF_DMAC_DSTINC_18 -#define CONF_DMAC_DSTINC_18 0 -#endif - -// <o> Transfer Type -// <0x0=> Memory to Memory Transfer -// <0x1=> Peripheral to Memory Transfer -// <0x2=> Memory to Peripheral Transfer -// <i> Define the data transfer type -// <id> dma_trans_type_18 -#ifndef CONF_DMAC_TRANS_TYPE_18 -#define CONF_DMAC_TRANS_TYPE_18 0x0 -#endif - -// <o> Trigger source -// <0xFF=> Software Trigger -// <0x00=> HSMCI TX/RX Trigger -// <0x01=> SPI0 TX Trigger -// <0x02=> SPI0 RX Trigger -// <0x03=> SPI1 TX Trigger -// <0x04=> SPI1 RX Trigger -// <0x05=> QSPI TX Trigger -// <0x06=> QSPI RX Trigger -// <0x07=> USART0 TX Trigger -// <0x08=> USART0 RX Trigger -// <0x09=> USART1 TX Trigger -// <0x0A=> USART1 RX Trigger -// <0x0B=> USART2 TX Trigger -// <0x0C=> USART2 RX Trigger -// <0x0D=> PWM0 TX Trigger -// <0x0E=> TWIHS0 TX Trigger -// <0x0F=> TWIHS0 RX Trigger -// <0x10=> TWIHS1 TX Trigger -// <0x11=> TWIHS1 RX Trigger -// <0x12=> TWIHS2 TX Trigger -// <0x13=> TWIHS2 RX Trigger -// <0x14=> UART0 TX Trigger -// <0x15=> UART0 RX Trigger -// <0x16=> UART1 TX Trigger -// <0x17=> UART1 RX Trigger -// <0x18=> UART2 TX Trigger -// <0x19=> UART2 RX Trigger -// <0x1A=> UART3 TX Trigger -// <0x1B=> UART3 RX Trigger -// <0x1C=> UART4 TX Trigger -// <0x1D=> UART4 RX Trigger -// <0x1E=> DACC TX Trigger -// <0x20=> SSC TX Trigger -// <0x21=> SSC RX Trigger -// <0x22=> PIOA RX Trigger -// <0x23=> AFEC0 RX Trigger -// <0x24=> AFEC1 RX Trigger -// <0x25=> AES TX Trigger -// <0x26=> AES RX Trigger -// <0x27=> PWM1 TX Trigger -// <0x28=> TC0 RX Trigger -// <0x29=> TC3 RX Trigger -// <0x2A=> TC6 RX Trigger -// <0x2B=> TC9 RX Trigger -// <0x2C=> I2SC0 TX Left Trigger -// <0x2D=> I2SC0 RX Left Trigger -// <0x2E=> I2SC1 TX Left Trigger -// <0x2F=> I2SC1 RX Left Trigger -// <0x30=> I2SC0 TX Right Trigger -// <0x31=> I2SC0 RX Right Trigger -// <0x32=> I2SC1 TX Right Trigger -// <0x33=> I2SC1 RX Right Trigger -// <i> Define the DMA trigger source -// <id> dmac_trifsrc_18 -#ifndef CONF_DMAC_TRIGSRC_18 -#define CONF_DMAC_TRIGSRC_18 0xff -#endif - -// </e> - -#if CONF_DMAC_TRANS_TYPE_18 == 0 -#define CONF_DMAC_TYPE_18 0 -#define CONF_DMAC_DSYNC_18 0 -#elif CONF_DMAC_TRANS_TYPE_18 == 1 -#define CONF_DMAC_TYPE_18 1 -#define CONF_DMAC_DSYNC_18 0 -#elif CONF_DMAC_TRANS_TYPE_18 == 2 -#define CONF_DMAC_TYPE_18 1 -#define CONF_DMAC_DSYNC_18 1 -#endif - -#if CONF_DMAC_TRIGSRC_18 == 0xFF -#define CONF_DMAC_SWREQ_18 1 -#else -#define CONF_DMAC_SWREQ_18 0 -#endif - -/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address - * or fixed destination address mode, source and destination addresses are incremented - * by 8-bit or 16-bit. - * Workaround: The user can fix the problem by setting the source addressing mode to - * use microblock and data striding with microblock stride set to 0 and data stride set to -1. - */ -#if (CONF_DMAC_CHANNEL_18_SETTINGS == 1 && CONF_DMAC_BEATSIZE_18 != 2 \ - && ((!CONF_DMAC_SRCINC_18) || (!CONF_DMAC_DSTINC_18))) -#if (!CONF_DMAC_SRCINC_18) -#define CONF_DMAC_SRC_STRIDE_18 ((int16_t)(-1)) -#endif -#if (!CONF_DMAC_DSTINC_18) -#define CONF_DMAC_DES_STRIDE_18 ((int16_t)(-1)) -#endif -#endif - -#ifndef CONF_DMAC_SRC_STRIDE_18 -#define CONF_DMAC_SRC_STRIDE_18 0 -#endif - -#ifndef CONF_DMAC_DES_STRIDE_18 -#define CONF_DMAC_DES_STRIDE_18 0 -#endif - -// <e> Channel 19 settings -// <id> dmac_channel_19_settings -#ifndef CONF_DMAC_CHANNEL_19_SETTINGS -#define CONF_DMAC_CHANNEL_19_SETTINGS 0 -#endif - -// <o> Burst Size -// <0x0=> 1 burst size -// <0x1=> 4 burst size -// <0x2=> 8 burst size -// <0x3=> 16 burst size -// <i> Define the memory burst size -// <id> dmac_burstsize_19 -#ifndef CONF_DMAC_BURSTSIZE_19 -#define CONF_DMAC_BURSTSIZE_19 0x0 -#endif - -// <o> Chunk Size -// <0x0=> 1 data transferred -// <0x1=> 2 data transferred -// <0x2=> 4 data transferred -// <0x3=> 8 data transferred -// <0x4=> 16 data transferred -// <i> Define the peripheral chunk size -// <id> dmac_chunksize_19 -#ifndef CONF_DMAC_CHUNKSIZE_19 -#define CONF_DMAC_CHUNKSIZE_19 0x0 -#endif - -// <o> Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// <i> Defines the size of one beat -// <id> dmac_beatsize_19 -#ifndef CONF_DMAC_BEATSIZE_19 -#define CONF_DMAC_BEATSIZE_19 0x0 -#endif - -// <o> Source Interface Identifier -// <0x0=> AHB_IF0 -// <0x1=> AHB_IF1 -// <i> Define the data is read through the system bus interface 0 or 1 -// <id> dma_src_interface_19 -#ifndef CONF_DMAC_SRC_INTERFACE_19 -#define CONF_DMAC_SRC_INTERFACE_19 0x0 -#endif - -// <o> Destination Interface Identifier -// <0x0=> AHB_IF0 -// <0x1=> AHB_IF1 -// <i> Define the data is written through the system bus interface 0 or 1 -// <id> dma_des_interface_19 -#ifndef CONF_DMAC_DES_INTERFACE_19 -#define CONF_DMAC_DES_INTERFACE_19 0x0 -#endif - -// <q> Source Address Increment -// <i> Indicates whether the source address incremented as beat size or not -// <id> dmac_srcinc_19 -#ifndef CONF_DMAC_SRCINC_19 -#define CONF_DMAC_SRCINC_19 0 -#endif - -// <q> Destination Address Increment -// <i> Indicates whether the destination address incremented as beat size or not -// <id> dmac_dstinc_19 -#ifndef CONF_DMAC_DSTINC_19 -#define CONF_DMAC_DSTINC_19 0 -#endif - -// <o> Transfer Type -// <0x0=> Memory to Memory Transfer -// <0x1=> Peripheral to Memory Transfer -// <0x2=> Memory to Peripheral Transfer -// <i> Define the data transfer type -// <id> dma_trans_type_19 -#ifndef CONF_DMAC_TRANS_TYPE_19 -#define CONF_DMAC_TRANS_TYPE_19 0x0 -#endif - -// <o> Trigger source -// <0xFF=> Software Trigger -// <0x00=> HSMCI TX/RX Trigger -// <0x01=> SPI0 TX Trigger -// <0x02=> SPI0 RX Trigger -// <0x03=> SPI1 TX Trigger -// <0x04=> SPI1 RX Trigger -// <0x05=> QSPI TX Trigger -// <0x06=> QSPI RX Trigger -// <0x07=> USART0 TX Trigger -// <0x08=> USART0 RX Trigger -// <0x09=> USART1 TX Trigger -// <0x0A=> USART1 RX Trigger -// <0x0B=> USART2 TX Trigger -// <0x0C=> USART2 RX Trigger -// <0x0D=> PWM0 TX Trigger -// <0x0E=> TWIHS0 TX Trigger -// <0x0F=> TWIHS0 RX Trigger -// <0x10=> TWIHS1 TX Trigger -// <0x11=> TWIHS1 RX Trigger -// <0x12=> TWIHS2 TX Trigger -// <0x13=> TWIHS2 RX Trigger -// <0x14=> UART0 TX Trigger -// <0x15=> UART0 RX Trigger -// <0x16=> UART1 TX Trigger -// <0x17=> UART1 RX Trigger -// <0x18=> UART2 TX Trigger -// <0x19=> UART2 RX Trigger -// <0x1A=> UART3 TX Trigger -// <0x1B=> UART3 RX Trigger -// <0x1C=> UART4 TX Trigger -// <0x1D=> UART4 RX Trigger -// <0x1E=> DACC TX Trigger -// <0x20=> SSC TX Trigger -// <0x21=> SSC RX Trigger -// <0x22=> PIOA RX Trigger -// <0x23=> AFEC0 RX Trigger -// <0x24=> AFEC1 RX Trigger -// <0x25=> AES TX Trigger -// <0x26=> AES RX Trigger -// <0x27=> PWM1 TX Trigger -// <0x28=> TC0 RX Trigger -// <0x29=> TC3 RX Trigger -// <0x2A=> TC6 RX Trigger -// <0x2B=> TC9 RX Trigger -// <0x2C=> I2SC0 TX Left Trigger -// <0x2D=> I2SC0 RX Left Trigger -// <0x2E=> I2SC1 TX Left Trigger -// <0x2F=> I2SC1 RX Left Trigger -// <0x30=> I2SC0 TX Right Trigger -// <0x31=> I2SC0 RX Right Trigger -// <0x32=> I2SC1 TX Right Trigger -// <0x33=> I2SC1 RX Right Trigger -// <i> Define the DMA trigger source -// <id> dmac_trifsrc_19 -#ifndef CONF_DMAC_TRIGSRC_19 -#define CONF_DMAC_TRIGSRC_19 0xff -#endif - -// </e> - -#if CONF_DMAC_TRANS_TYPE_19 == 0 -#define CONF_DMAC_TYPE_19 0 -#define CONF_DMAC_DSYNC_19 0 -#elif CONF_DMAC_TRANS_TYPE_19 == 1 -#define CONF_DMAC_TYPE_19 1 -#define CONF_DMAC_DSYNC_19 0 -#elif CONF_DMAC_TRANS_TYPE_19 == 2 -#define CONF_DMAC_TYPE_19 1 -#define CONF_DMAC_DSYNC_19 1 -#endif - -#if CONF_DMAC_TRIGSRC_19 == 0xFF -#define CONF_DMAC_SWREQ_19 1 -#else -#define CONF_DMAC_SWREQ_19 0 -#endif - -/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address - * or fixed destination address mode, source and destination addresses are incremented - * by 8-bit or 16-bit. - * Workaround: The user can fix the problem by setting the source addressing mode to - * use microblock and data striding with microblock stride set to 0 and data stride set to -1. - */ -#if (CONF_DMAC_CHANNEL_19_SETTINGS == 1 && CONF_DMAC_BEATSIZE_19 != 2 \ - && ((!CONF_DMAC_SRCINC_19) || (!CONF_DMAC_DSTINC_19))) -#if (!CONF_DMAC_SRCINC_19) -#define CONF_DMAC_SRC_STRIDE_19 ((int16_t)(-1)) -#endif -#if (!CONF_DMAC_DSTINC_19) -#define CONF_DMAC_DES_STRIDE_19 ((int16_t)(-1)) -#endif -#endif - -#ifndef CONF_DMAC_SRC_STRIDE_19 -#define CONF_DMAC_SRC_STRIDE_19 0 -#endif - -#ifndef CONF_DMAC_DES_STRIDE_19 -#define CONF_DMAC_DES_STRIDE_19 0 -#endif - -// <e> Channel 20 settings -// <id> dmac_channel_20_settings -#ifndef CONF_DMAC_CHANNEL_20_SETTINGS -#define CONF_DMAC_CHANNEL_20_SETTINGS 0 -#endif - -// <o> Burst Size -// <0x0=> 1 burst size -// <0x1=> 4 burst size -// <0x2=> 8 burst size -// <0x3=> 16 burst size -// <i> Define the memory burst size -// <id> dmac_burstsize_20 -#ifndef CONF_DMAC_BURSTSIZE_20 -#define CONF_DMAC_BURSTSIZE_20 0x0 -#endif - -// <o> Chunk Size -// <0x0=> 1 data transferred -// <0x1=> 2 data transferred -// <0x2=> 4 data transferred -// <0x3=> 8 data transferred -// <0x4=> 16 data transferred -// <i> Define the peripheral chunk size -// <id> dmac_chunksize_20 -#ifndef CONF_DMAC_CHUNKSIZE_20 -#define CONF_DMAC_CHUNKSIZE_20 0x0 -#endif - -// <o> Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// <i> Defines the size of one beat -// <id> dmac_beatsize_20 -#ifndef CONF_DMAC_BEATSIZE_20 -#define CONF_DMAC_BEATSIZE_20 0x0 -#endif - -// <o> Source Interface Identifier -// <0x0=> AHB_IF0 -// <0x1=> AHB_IF1 -// <i> Define the data is read through the system bus interface 0 or 1 -// <id> dma_src_interface_20 -#ifndef CONF_DMAC_SRC_INTERFACE_20 -#define CONF_DMAC_SRC_INTERFACE_20 0x0 -#endif - -// <o> Destination Interface Identifier -// <0x0=> AHB_IF0 -// <0x1=> AHB_IF1 -// <i> Define the data is written through the system bus interface 0 or 1 -// <id> dma_des_interface_20 -#ifndef CONF_DMAC_DES_INTERFACE_20 -#define CONF_DMAC_DES_INTERFACE_20 0x0 -#endif - -// <q> Source Address Increment -// <i> Indicates whether the source address incremented as beat size or not -// <id> dmac_srcinc_20 -#ifndef CONF_DMAC_SRCINC_20 -#define CONF_DMAC_SRCINC_20 0 -#endif - -// <q> Destination Address Increment -// <i> Indicates whether the destination address incremented as beat size or not -// <id> dmac_dstinc_20 -#ifndef CONF_DMAC_DSTINC_20 -#define CONF_DMAC_DSTINC_20 0 -#endif - -// <o> Transfer Type -// <0x0=> Memory to Memory Transfer -// <0x1=> Peripheral to Memory Transfer -// <0x2=> Memory to Peripheral Transfer -// <i> Define the data transfer type -// <id> dma_trans_type_20 -#ifndef CONF_DMAC_TRANS_TYPE_20 -#define CONF_DMAC_TRANS_TYPE_20 0x0 -#endif - -// <o> Trigger source -// <0xFF=> Software Trigger -// <0x00=> HSMCI TX/RX Trigger -// <0x01=> SPI0 TX Trigger -// <0x02=> SPI0 RX Trigger -// <0x03=> SPI1 TX Trigger -// <0x04=> SPI1 RX Trigger -// <0x05=> QSPI TX Trigger -// <0x06=> QSPI RX Trigger -// <0x07=> USART0 TX Trigger -// <0x08=> USART0 RX Trigger -// <0x09=> USART1 TX Trigger -// <0x0A=> USART1 RX Trigger -// <0x0B=> USART2 TX Trigger -// <0x0C=> USART2 RX Trigger -// <0x0D=> PWM0 TX Trigger -// <0x0E=> TWIHS0 TX Trigger -// <0x0F=> TWIHS0 RX Trigger -// <0x10=> TWIHS1 TX Trigger -// <0x11=> TWIHS1 RX Trigger -// <0x12=> TWIHS2 TX Trigger -// <0x13=> TWIHS2 RX Trigger -// <0x14=> UART0 TX Trigger -// <0x15=> UART0 RX Trigger -// <0x16=> UART1 TX Trigger -// <0x17=> UART1 RX Trigger -// <0x18=> UART2 TX Trigger -// <0x19=> UART2 RX Trigger -// <0x1A=> UART3 TX Trigger -// <0x1B=> UART3 RX Trigger -// <0x1C=> UART4 TX Trigger -// <0x1D=> UART4 RX Trigger -// <0x1E=> DACC TX Trigger -// <0x20=> SSC TX Trigger -// <0x21=> SSC RX Trigger -// <0x22=> PIOA RX Trigger -// <0x23=> AFEC0 RX Trigger -// <0x24=> AFEC1 RX Trigger -// <0x25=> AES TX Trigger -// <0x26=> AES RX Trigger -// <0x27=> PWM1 TX Trigger -// <0x28=> TC0 RX Trigger -// <0x29=> TC3 RX Trigger -// <0x2A=> TC6 RX Trigger -// <0x2B=> TC9 RX Trigger -// <0x2C=> I2SC0 TX Left Trigger -// <0x2D=> I2SC0 RX Left Trigger -// <0x2E=> I2SC1 TX Left Trigger -// <0x2F=> I2SC1 RX Left Trigger -// <0x30=> I2SC0 TX Right Trigger -// <0x31=> I2SC0 RX Right Trigger -// <0x32=> I2SC1 TX Right Trigger -// <0x33=> I2SC1 RX Right Trigger -// <i> Define the DMA trigger source -// <id> dmac_trifsrc_20 -#ifndef CONF_DMAC_TRIGSRC_20 -#define CONF_DMAC_TRIGSRC_20 0xff -#endif - -// </e> - -#if CONF_DMAC_TRANS_TYPE_20 == 0 -#define CONF_DMAC_TYPE_20 0 -#define CONF_DMAC_DSYNC_20 0 -#elif CONF_DMAC_TRANS_TYPE_20 == 1 -#define CONF_DMAC_TYPE_20 1 -#define CONF_DMAC_DSYNC_20 0 -#elif CONF_DMAC_TRANS_TYPE_20 == 2 -#define CONF_DMAC_TYPE_20 1 -#define CONF_DMAC_DSYNC_20 1 -#endif - -#if CONF_DMAC_TRIGSRC_20 == 0xFF -#define CONF_DMAC_SWREQ_20 1 -#else -#define CONF_DMAC_SWREQ_20 0 -#endif - -/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address - * or fixed destination address mode, source and destination addresses are incremented - * by 8-bit or 16-bit. - * Workaround: The user can fix the problem by setting the source addressing mode to - * use microblock and data striding with microblock stride set to 0 and data stride set to -1. - */ -#if (CONF_DMAC_CHANNEL_20_SETTINGS == 1 && CONF_DMAC_BEATSIZE_20 != 2 \ - && ((!CONF_DMAC_SRCINC_20) || (!CONF_DMAC_DSTINC_20))) -#if (!CONF_DMAC_SRCINC_20) -#define CONF_DMAC_SRC_STRIDE_20 ((int16_t)(-1)) -#endif -#if (!CONF_DMAC_DSTINC_20) -#define CONF_DMAC_DES_STRIDE_20 ((int16_t)(-1)) -#endif -#endif - -#ifndef CONF_DMAC_SRC_STRIDE_20 -#define CONF_DMAC_SRC_STRIDE_20 0 -#endif - -#ifndef CONF_DMAC_DES_STRIDE_20 -#define CONF_DMAC_DES_STRIDE_20 0 -#endif - -// <e> Channel 21 settings -// <id> dmac_channel_21_settings -#ifndef CONF_DMAC_CHANNEL_21_SETTINGS -#define CONF_DMAC_CHANNEL_21_SETTINGS 0 -#endif - -// <o> Burst Size -// <0x0=> 1 burst size -// <0x1=> 4 burst size -// <0x2=> 8 burst size -// <0x3=> 16 burst size -// <i> Define the memory burst size -// <id> dmac_burstsize_21 -#ifndef CONF_DMAC_BURSTSIZE_21 -#define CONF_DMAC_BURSTSIZE_21 0x0 -#endif - -// <o> Chunk Size -// <0x0=> 1 data transferred -// <0x1=> 2 data transferred -// <0x2=> 4 data transferred -// <0x3=> 8 data transferred -// <0x4=> 16 data transferred -// <i> Define the peripheral chunk size -// <id> dmac_chunksize_21 -#ifndef CONF_DMAC_CHUNKSIZE_21 -#define CONF_DMAC_CHUNKSIZE_21 0x0 -#endif - -// <o> Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// <i> Defines the size of one beat -// <id> dmac_beatsize_21 -#ifndef CONF_DMAC_BEATSIZE_21 -#define CONF_DMAC_BEATSIZE_21 0x0 -#endif - -// <o> Source Interface Identifier -// <0x0=> AHB_IF0 -// <0x1=> AHB_IF1 -// <i> Define the data is read through the system bus interface 0 or 1 -// <id> dma_src_interface_21 -#ifndef CONF_DMAC_SRC_INTERFACE_21 -#define CONF_DMAC_SRC_INTERFACE_21 0x0 -#endif - -// <o> Destination Interface Identifier -// <0x0=> AHB_IF0 -// <0x1=> AHB_IF1 -// <i> Define the data is written through the system bus interface 0 or 1 -// <id> dma_des_interface_21 -#ifndef CONF_DMAC_DES_INTERFACE_21 -#define CONF_DMAC_DES_INTERFACE_21 0x0 -#endif - -// <q> Source Address Increment -// <i> Indicates whether the source address incremented as beat size or not -// <id> dmac_srcinc_21 -#ifndef CONF_DMAC_SRCINC_21 -#define CONF_DMAC_SRCINC_21 0 -#endif - -// <q> Destination Address Increment -// <i> Indicates whether the destination address incremented as beat size or not -// <id> dmac_dstinc_21 -#ifndef CONF_DMAC_DSTINC_21 -#define CONF_DMAC_DSTINC_21 0 -#endif - -// <o> Transfer Type -// <0x0=> Memory to Memory Transfer -// <0x1=> Peripheral to Memory Transfer -// <0x2=> Memory to Peripheral Transfer -// <i> Define the data transfer type -// <id> dma_trans_type_21 -#ifndef CONF_DMAC_TRANS_TYPE_21 -#define CONF_DMAC_TRANS_TYPE_21 0x0 -#endif - -// <o> Trigger source -// <0xFF=> Software Trigger -// <0x00=> HSMCI TX/RX Trigger -// <0x01=> SPI0 TX Trigger -// <0x02=> SPI0 RX Trigger -// <0x03=> SPI1 TX Trigger -// <0x04=> SPI1 RX Trigger -// <0x05=> QSPI TX Trigger -// <0x06=> QSPI RX Trigger -// <0x07=> USART0 TX Trigger -// <0x08=> USART0 RX Trigger -// <0x09=> USART1 TX Trigger -// <0x0A=> USART1 RX Trigger -// <0x0B=> USART2 TX Trigger -// <0x0C=> USART2 RX Trigger -// <0x0D=> PWM0 TX Trigger -// <0x0E=> TWIHS0 TX Trigger -// <0x0F=> TWIHS0 RX Trigger -// <0x10=> TWIHS1 TX Trigger -// <0x11=> TWIHS1 RX Trigger -// <0x12=> TWIHS2 TX Trigger -// <0x13=> TWIHS2 RX Trigger -// <0x14=> UART0 TX Trigger -// <0x15=> UART0 RX Trigger -// <0x16=> UART1 TX Trigger -// <0x17=> UART1 RX Trigger -// <0x18=> UART2 TX Trigger -// <0x19=> UART2 RX Trigger -// <0x1A=> UART3 TX Trigger -// <0x1B=> UART3 RX Trigger -// <0x1C=> UART4 TX Trigger -// <0x1D=> UART4 RX Trigger -// <0x1E=> DACC TX Trigger -// <0x20=> SSC TX Trigger -// <0x21=> SSC RX Trigger -// <0x22=> PIOA RX Trigger -// <0x23=> AFEC0 RX Trigger -// <0x24=> AFEC1 RX Trigger -// <0x25=> AES TX Trigger -// <0x26=> AES RX Trigger -// <0x27=> PWM1 TX Trigger -// <0x28=> TC0 RX Trigger -// <0x29=> TC3 RX Trigger -// <0x2A=> TC6 RX Trigger -// <0x2B=> TC9 RX Trigger -// <0x2C=> I2SC0 TX Left Trigger -// <0x2D=> I2SC0 RX Left Trigger -// <0x2E=> I2SC1 TX Left Trigger -// <0x2F=> I2SC1 RX Left Trigger -// <0x30=> I2SC0 TX Right Trigger -// <0x31=> I2SC0 RX Right Trigger -// <0x32=> I2SC1 TX Right Trigger -// <0x33=> I2SC1 RX Right Trigger -// <i> Define the DMA trigger source -// <id> dmac_trifsrc_21 -#ifndef CONF_DMAC_TRIGSRC_21 -#define CONF_DMAC_TRIGSRC_21 0xff -#endif - -// </e> - -#if CONF_DMAC_TRANS_TYPE_21 == 0 -#define CONF_DMAC_TYPE_21 0 -#define CONF_DMAC_DSYNC_21 0 -#elif CONF_DMAC_TRANS_TYPE_21 == 1 -#define CONF_DMAC_TYPE_21 1 -#define CONF_DMAC_DSYNC_21 0 -#elif CONF_DMAC_TRANS_TYPE_21 == 2 -#define CONF_DMAC_TYPE_21 1 -#define CONF_DMAC_DSYNC_21 1 -#endif - -#if CONF_DMAC_TRIGSRC_21 == 0xFF -#define CONF_DMAC_SWREQ_21 1 -#else -#define CONF_DMAC_SWREQ_21 0 -#endif - -/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address - * or fixed destination address mode, source and destination addresses are incremented - * by 8-bit or 16-bit. - * Workaround: The user can fix the problem by setting the source addressing mode to - * use microblock and data striding with microblock stride set to 0 and data stride set to -1. - */ -#if (CONF_DMAC_CHANNEL_21_SETTINGS == 1 && CONF_DMAC_BEATSIZE_21 != 2 \ - && ((!CONF_DMAC_SRCINC_21) || (!CONF_DMAC_DSTINC_21))) -#if (!CONF_DMAC_SRCINC_21) -#define CONF_DMAC_SRC_STRIDE_21 ((int16_t)(-1)) -#endif -#if (!CONF_DMAC_DSTINC_21) -#define CONF_DMAC_DES_STRIDE_21 ((int16_t)(-1)) -#endif -#endif - -#ifndef CONF_DMAC_SRC_STRIDE_21 -#define CONF_DMAC_SRC_STRIDE_21 0 -#endif - -#ifndef CONF_DMAC_DES_STRIDE_21 -#define CONF_DMAC_DES_STRIDE_21 0 -#endif - -// <e> Channel 22 settings -// <id> dmac_channel_22_settings -#ifndef CONF_DMAC_CHANNEL_22_SETTINGS -#define CONF_DMAC_CHANNEL_22_SETTINGS 0 -#endif - -// <o> Burst Size -// <0x0=> 1 burst size -// <0x1=> 4 burst size -// <0x2=> 8 burst size -// <0x3=> 16 burst size -// <i> Define the memory burst size -// <id> dmac_burstsize_22 -#ifndef CONF_DMAC_BURSTSIZE_22 -#define CONF_DMAC_BURSTSIZE_22 0x0 -#endif - -// <o> Chunk Size -// <0x0=> 1 data transferred -// <0x1=> 2 data transferred -// <0x2=> 4 data transferred -// <0x3=> 8 data transferred -// <0x4=> 16 data transferred -// <i> Define the peripheral chunk size -// <id> dmac_chunksize_22 -#ifndef CONF_DMAC_CHUNKSIZE_22 -#define CONF_DMAC_CHUNKSIZE_22 0x0 -#endif - -// <o> Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// <i> Defines the size of one beat -// <id> dmac_beatsize_22 -#ifndef CONF_DMAC_BEATSIZE_22 -#define CONF_DMAC_BEATSIZE_22 0x0 -#endif - -// <o> Source Interface Identifier -// <0x0=> AHB_IF0 -// <0x1=> AHB_IF1 -// <i> Define the data is read through the system bus interface 0 or 1 -// <id> dma_src_interface_22 -#ifndef CONF_DMAC_SRC_INTERFACE_22 -#define CONF_DMAC_SRC_INTERFACE_22 0x0 -#endif - -// <o> Destination Interface Identifier -// <0x0=> AHB_IF0 -// <0x1=> AHB_IF1 -// <i> Define the data is written through the system bus interface 0 or 1 -// <id> dma_des_interface_22 -#ifndef CONF_DMAC_DES_INTERFACE_22 -#define CONF_DMAC_DES_INTERFACE_22 0x0 -#endif - -// <q> Source Address Increment -// <i> Indicates whether the source address incremented as beat size or not -// <id> dmac_srcinc_22 -#ifndef CONF_DMAC_SRCINC_22 -#define CONF_DMAC_SRCINC_22 0 -#endif - -// <q> Destination Address Increment -// <i> Indicates whether the destination address incremented as beat size or not -// <id> dmac_dstinc_22 -#ifndef CONF_DMAC_DSTINC_22 -#define CONF_DMAC_DSTINC_22 0 -#endif - -// <o> Transfer Type -// <0x0=> Memory to Memory Transfer -// <0x1=> Peripheral to Memory Transfer -// <0x2=> Memory to Peripheral Transfer -// <i> Define the data transfer type -// <id> dma_trans_type_22 -#ifndef CONF_DMAC_TRANS_TYPE_22 -#define CONF_DMAC_TRANS_TYPE_22 0x0 -#endif - -// <o> Trigger source -// <0xFF=> Software Trigger -// <0x00=> HSMCI TX/RX Trigger -// <0x01=> SPI0 TX Trigger -// <0x02=> SPI0 RX Trigger -// <0x03=> SPI1 TX Trigger -// <0x04=> SPI1 RX Trigger -// <0x05=> QSPI TX Trigger -// <0x06=> QSPI RX Trigger -// <0x07=> USART0 TX Trigger -// <0x08=> USART0 RX Trigger -// <0x09=> USART1 TX Trigger -// <0x0A=> USART1 RX Trigger -// <0x0B=> USART2 TX Trigger -// <0x0C=> USART2 RX Trigger -// <0x0D=> PWM0 TX Trigger -// <0x0E=> TWIHS0 TX Trigger -// <0x0F=> TWIHS0 RX Trigger -// <0x10=> TWIHS1 TX Trigger -// <0x11=> TWIHS1 RX Trigger -// <0x12=> TWIHS2 TX Trigger -// <0x13=> TWIHS2 RX Trigger -// <0x14=> UART0 TX Trigger -// <0x15=> UART0 RX Trigger -// <0x16=> UART1 TX Trigger -// <0x17=> UART1 RX Trigger -// <0x18=> UART2 TX Trigger -// <0x19=> UART2 RX Trigger -// <0x1A=> UART3 TX Trigger -// <0x1B=> UART3 RX Trigger -// <0x1C=> UART4 TX Trigger -// <0x1D=> UART4 RX Trigger -// <0x1E=> DACC TX Trigger -// <0x20=> SSC TX Trigger -// <0x21=> SSC RX Trigger -// <0x22=> PIOA RX Trigger -// <0x23=> AFEC0 RX Trigger -// <0x24=> AFEC1 RX Trigger -// <0x25=> AES TX Trigger -// <0x26=> AES RX Trigger -// <0x27=> PWM1 TX Trigger -// <0x28=> TC0 RX Trigger -// <0x29=> TC3 RX Trigger -// <0x2A=> TC6 RX Trigger -// <0x2B=> TC9 RX Trigger -// <0x2C=> I2SC0 TX Left Trigger -// <0x2D=> I2SC0 RX Left Trigger -// <0x2E=> I2SC1 TX Left Trigger -// <0x2F=> I2SC1 RX Left Trigger -// <0x30=> I2SC0 TX Right Trigger -// <0x31=> I2SC0 RX Right Trigger -// <0x32=> I2SC1 TX Right Trigger -// <0x33=> I2SC1 RX Right Trigger -// <i> Define the DMA trigger source -// <id> dmac_trifsrc_22 -#ifndef CONF_DMAC_TRIGSRC_22 -#define CONF_DMAC_TRIGSRC_22 0xff -#endif - -// </e> - -#if CONF_DMAC_TRANS_TYPE_22 == 0 -#define CONF_DMAC_TYPE_22 0 -#define CONF_DMAC_DSYNC_22 0 -#elif CONF_DMAC_TRANS_TYPE_22 == 1 -#define CONF_DMAC_TYPE_22 1 -#define CONF_DMAC_DSYNC_22 0 -#elif CONF_DMAC_TRANS_TYPE_22 == 2 -#define CONF_DMAC_TYPE_22 1 -#define CONF_DMAC_DSYNC_22 1 -#endif - -#if CONF_DMAC_TRIGSRC_22 == 0xFF -#define CONF_DMAC_SWREQ_22 1 -#else -#define CONF_DMAC_SWREQ_22 0 -#endif - -/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address - * or fixed destination address mode, source and destination addresses are incremented - * by 8-bit or 16-bit. - * Workaround: The user can fix the problem by setting the source addressing mode to - * use microblock and data striding with microblock stride set to 0 and data stride set to -1. - */ -#if (CONF_DMAC_CHANNEL_22_SETTINGS == 1 && CONF_DMAC_BEATSIZE_22 != 2 \ - && ((!CONF_DMAC_SRCINC_22) || (!CONF_DMAC_DSTINC_22))) -#if (!CONF_DMAC_SRCINC_22) -#define CONF_DMAC_SRC_STRIDE_22 ((int16_t)(-1)) -#endif -#if (!CONF_DMAC_DSTINC_22) -#define CONF_DMAC_DES_STRIDE_22 ((int16_t)(-1)) -#endif -#endif - -#ifndef CONF_DMAC_SRC_STRIDE_22 -#define CONF_DMAC_SRC_STRIDE_22 0 -#endif - -#ifndef CONF_DMAC_DES_STRIDE_22 -#define CONF_DMAC_DES_STRIDE_22 0 -#endif - -// <e> Channel 23 settings -// <id> dmac_channel_23_settings -#ifndef CONF_DMAC_CHANNEL_23_SETTINGS -#define CONF_DMAC_CHANNEL_23_SETTINGS 0 -#endif - -// <o> Burst Size -// <0x0=> 1 burst size -// <0x1=> 4 burst size -// <0x2=> 8 burst size -// <0x3=> 16 burst size -// <i> Define the memory burst size -// <id> dmac_burstsize_23 -#ifndef CONF_DMAC_BURSTSIZE_23 -#define CONF_DMAC_BURSTSIZE_23 0x0 -#endif - -// <o> Chunk Size -// <0x0=> 1 data transferred -// <0x1=> 2 data transferred -// <0x2=> 4 data transferred -// <0x3=> 8 data transferred -// <0x4=> 16 data transferred -// <i> Define the peripheral chunk size -// <id> dmac_chunksize_23 -#ifndef CONF_DMAC_CHUNKSIZE_23 -#define CONF_DMAC_CHUNKSIZE_23 0x0 -#endif - -// <o> Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// <i> Defines the size of one beat -// <id> dmac_beatsize_23 -#ifndef CONF_DMAC_BEATSIZE_23 -#define CONF_DMAC_BEATSIZE_23 0x0 -#endif - -// <o> Source Interface Identifier -// <0x0=> AHB_IF0 -// <0x1=> AHB_IF1 -// <i> Define the data is read through the system bus interface 0 or 1 -// <id> dma_src_interface_23 -#ifndef CONF_DMAC_SRC_INTERFACE_23 -#define CONF_DMAC_SRC_INTERFACE_23 0x0 -#endif - -// <o> Destination Interface Identifier -// <0x0=> AHB_IF0 -// <0x1=> AHB_IF1 -// <i> Define the data is written through the system bus interface 0 or 1 -// <id> dma_des_interface_23 -#ifndef CONF_DMAC_DES_INTERFACE_23 -#define CONF_DMAC_DES_INTERFACE_23 0x0 -#endif - -// <q> Source Address Increment -// <i> Indicates whether the source address incremented as beat size or not -// <id> dmac_srcinc_23 -#ifndef CONF_DMAC_SRCINC_23 -#define CONF_DMAC_SRCINC_23 0 -#endif - -// <q> Destination Address Increment -// <i> Indicates whether the destination address incremented as beat size or not -// <id> dmac_dstinc_23 -#ifndef CONF_DMAC_DSTINC_23 -#define CONF_DMAC_DSTINC_23 0 -#endif - -// <o> Transfer Type -// <0x0=> Memory to Memory Transfer -// <0x1=> Peripheral to Memory Transfer -// <0x2=> Memory to Peripheral Transfer -// <i> Define the data transfer type -// <id> dma_trans_type_23 -#ifndef CONF_DMAC_TRANS_TYPE_23 -#define CONF_DMAC_TRANS_TYPE_23 0x0 -#endif - -// <o> Trigger source -// <0xFF=> Software Trigger -// <0x00=> HSMCI TX/RX Trigger -// <0x01=> SPI0 TX Trigger -// <0x02=> SPI0 RX Trigger -// <0x03=> SPI1 TX Trigger -// <0x04=> SPI1 RX Trigger -// <0x05=> QSPI TX Trigger -// <0x06=> QSPI RX Trigger -// <0x07=> USART0 TX Trigger -// <0x08=> USART0 RX Trigger -// <0x09=> USART1 TX Trigger -// <0x0A=> USART1 RX Trigger -// <0x0B=> USART2 TX Trigger -// <0x0C=> USART2 RX Trigger -// <0x0D=> PWM0 TX Trigger -// <0x0E=> TWIHS0 TX Trigger -// <0x0F=> TWIHS0 RX Trigger -// <0x10=> TWIHS1 TX Trigger -// <0x11=> TWIHS1 RX Trigger -// <0x12=> TWIHS2 TX Trigger -// <0x13=> TWIHS2 RX Trigger -// <0x14=> UART0 TX Trigger -// <0x15=> UART0 RX Trigger -// <0x16=> UART1 TX Trigger -// <0x17=> UART1 RX Trigger -// <0x18=> UART2 TX Trigger -// <0x19=> UART2 RX Trigger -// <0x1A=> UART3 TX Trigger -// <0x1B=> UART3 RX Trigger -// <0x1C=> UART4 TX Trigger -// <0x1D=> UART4 RX Trigger -// <0x1E=> DACC TX Trigger -// <0x20=> SSC TX Trigger -// <0x21=> SSC RX Trigger -// <0x22=> PIOA RX Trigger -// <0x23=> AFEC0 RX Trigger -// <0x24=> AFEC1 RX Trigger -// <0x25=> AES TX Trigger -// <0x26=> AES RX Trigger -// <0x27=> PWM1 TX Trigger -// <0x28=> TC0 RX Trigger -// <0x29=> TC3 RX Trigger -// <0x2A=> TC6 RX Trigger -// <0x2B=> TC9 RX Trigger -// <0x2C=> I2SC0 TX Left Trigger -// <0x2D=> I2SC0 RX Left Trigger -// <0x2E=> I2SC1 TX Left Trigger -// <0x2F=> I2SC1 RX Left Trigger -// <0x30=> I2SC0 TX Right Trigger -// <0x31=> I2SC0 RX Right Trigger -// <0x32=> I2SC1 TX Right Trigger -// <0x33=> I2SC1 RX Right Trigger -// <i> Define the DMA trigger source -// <id> dmac_trifsrc_23 -#ifndef CONF_DMAC_TRIGSRC_23 -#define CONF_DMAC_TRIGSRC_23 0xff -#endif - -// </e> - -#if CONF_DMAC_TRANS_TYPE_23 == 0 -#define CONF_DMAC_TYPE_23 0 -#define CONF_DMAC_DSYNC_23 0 -#elif CONF_DMAC_TRANS_TYPE_23 == 1 -#define CONF_DMAC_TYPE_23 1 -#define CONF_DMAC_DSYNC_23 0 -#elif CONF_DMAC_TRANS_TYPE_23 == 2 -#define CONF_DMAC_TYPE_23 1 -#define CONF_DMAC_DSYNC_23 1 -#endif - -#if CONF_DMAC_TRIGSRC_23 == 0xFF -#define CONF_DMAC_SWREQ_23 1 -#else -#define CONF_DMAC_SWREQ_23 0 -#endif - -/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address - * or fixed destination address mode, source and destination addresses are incremented - * by 8-bit or 16-bit. - * Workaround: The user can fix the problem by setting the source addressing mode to - * use microblock and data striding with microblock stride set to 0 and data stride set to -1. - */ -#if (CONF_DMAC_CHANNEL_23_SETTINGS == 1 && CONF_DMAC_BEATSIZE_23 != 2 \ - && ((!CONF_DMAC_SRCINC_23) || (!CONF_DMAC_DSTINC_23))) -#if (!CONF_DMAC_SRCINC_23) -#define CONF_DMAC_SRC_STRIDE_23 ((int16_t)(-1)) -#endif -#if (!CONF_DMAC_DSTINC_23) -#define CONF_DMAC_DES_STRIDE_23 ((int16_t)(-1)) -#endif -#endif - -#ifndef CONF_DMAC_SRC_STRIDE_23 -#define CONF_DMAC_SRC_STRIDE_23 0 -#endif - -#ifndef CONF_DMAC_DES_STRIDE_23 -#define CONF_DMAC_DES_STRIDE_23 0 -#endif - -// </e> - -// <<< end of configuration section >>> - -#endif // HPL_XDMAC_CONFIG_H diff --git a/tinyusb/hw/bsp/same70_xplained/peripheral_clk_config.h b/tinyusb/hw/bsp/same70_xplained/peripheral_clk_config.h deleted file mode 100755 index 84756f5a..00000000 --- a/tinyusb/hw/bsp/same70_xplained/peripheral_clk_config.h +++ /dev/null @@ -1,126 +0,0 @@ -/* Auto-generated config file peripheral_clk_config.h */ -#ifndef PERIPHERAL_CLK_CONFIG_H -#define PERIPHERAL_CLK_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -/** - * \def CONF_HCLK_FREQUENCY - * \brief HCLK's Clock frequency - */ -#ifndef CONF_HCLK_FREQUENCY -#define CONF_HCLK_FREQUENCY 300000000 -#endif - -/** - * \def CONF_FCLK_FREQUENCY - * \brief FCLK's Clock frequency - */ -#ifndef CONF_FCLK_FREQUENCY -#define CONF_FCLK_FREQUENCY 300000000 -#endif - -/** - * \def CONF_CPU_FREQUENCY - * \brief CPU's Clock frequency - */ -#ifndef CONF_CPU_FREQUENCY -#define CONF_CPU_FREQUENCY 300000000 -#endif - -/** - * \def CONF_SLCK_FREQUENCY - * \brief Slow Clock frequency - */ -#define CONF_SLCK_FREQUENCY 0 - -/** - * \def CONF_MCK_FREQUENCY - * \brief Master Clock frequency - */ -#define CONF_MCK_FREQUENCY 150000000 - -/** - * \def CONF_PCK6_FREQUENCY - * \brief Programmable Clock Controller 6 frequency - */ -#define CONF_PCK6_FREQUENCY 1714285 - -// <h> USART Clock Settings -// <o> USART Clock source - -// <0=> Master Clock (MCK) -// <1=> MCK / 8 for USART -// <2=> Programmable Clock Controller 4 (PMC_PCK4) -// <3=> External Clock -// <i> This defines the clock source for the USART -// <id> usart_clock_source -#ifndef CONF_USART1_CK_SRC -#define CONF_USART1_CK_SRC 0 -#endif - -// <o> USART External Clock Input on SCK <1-4294967295> -// <i> Inputs the external clock frequency on SCK -// <id> usart_clock_freq -#ifndef CONF_USART1_SCK_FREQ -#define CONF_USART1_SCK_FREQ 10000000 -#endif - -// </h> - -/** - * \def USART FREQUENCY - * \brief USART's Clock frequency - */ -#ifndef CONF_USART1_FREQUENCY -#define CONF_USART1_FREQUENCY 150000000 -#endif - -#ifndef CONF_SRC_USB_480M -#define CONF_SRC_USB_480M 0 -#endif - -#ifndef CONF_SRC_USB_48M -#define CONF_SRC_USB_48M 1 -#endif - -// <y> USB Full/Low Speed Clock -// <CONF_SRC_USB_48M"> USB Clock Controller (USB_48M) -// <id> usb_fsls_clock_source -// <i> 48MHz clock source for low speed and full speed. -// <i> It must be available when low speed is supported by host driver. -// <i> It must be available when low power mode is selected. -#ifndef CONF_USBHS_FSLS_SRC -#define CONF_USBHS_FSLS_SRC CONF_SRC_USB_48M -#endif - -// <y> USB Clock Source(Normal/Low-power Mode Selection) -// <CONF_SRC_USB_480M"> USB High Speed Clock (USB_480M) -// <CONF_SRC_USB_48M"> USB Clock Controller (USB_48M) -// <id> usb_clock_source -// <i> Select the clock source for USB. -// <i> In normal mode, use "USB High Speed Clock (USB_480M)". -// <i> In low-power mode, use "USB Clock Controller (USB_48M)". -#ifndef CONF_USBHS_SRC -#define CONF_USBHS_SRC CONF_SRC_USB_480M -#endif - -/** - * \def CONF_USBHS_FSLS_FREQUENCY - * \brief USBHS's Full/Low Speed Clock Source frequency - */ -#ifndef CONF_USBHS_FSLS_FREQUENCY -#define CONF_USBHS_FSLS_FREQUENCY 48000000 -#endif - -/** - * \def CONF_USBHS_FREQUENCY - * \brief USBHS's Selected Clock Source frequency - */ -#ifndef CONF_USBHS_FREQUENCY -#define CONF_USBHS_FREQUENCY 480000000 -#endif - -// <<< end of configuration section >>> - -#endif // PERIPHERAL_CLK_CONFIG_H diff --git a/tinyusb/hw/bsp/same70_xplained/same70_xplained.c b/tinyusb/hw/bsp/same70_xplained/same70_xplained.c deleted file mode 100755 index e6e7db0f..00000000 --- a/tinyusb/hw/bsp/same70_xplained/same70_xplained.c +++ /dev/null @@ -1,156 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2019, hathach (tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - */ - -#include "sam.h" -#include "bsp/board.h" - -#include "peripheral_clk_config.h" -#include "hpl/usart/hpl_usart_base.h" -#include "hpl/pmc/hpl_pmc.h" -#include "hal/include/hal_init.h" -#include "hal/include/hal_usart_async.h" -#include "hal/include/hal_gpio.h" - - -//--------------------------------------------------------------------+ -// MACRO TYPEDEF CONSTANT ENUM DECLARATION -//--------------------------------------------------------------------+ - -#define LED_PIN GPIO(GPIO_PORTC, 8) - -#define BUTTON_PIN GPIO(GPIO_PORTA, 11) -#define BUTTON_STATE_ACTIVE 0 - -#define UART_TX_PIN GPIO(GPIO_PORTB, 4) -#define UART_RX_PIN GPIO(GPIO_PORTA, 21) - -static struct usart_async_descriptor edbg_com; -static uint8_t edbg_com_buffer[64]; -static volatile bool uart_busy = false; - -static void tx_cb_EDBG_COM(const struct usart_async_descriptor *const io_descr) -{ - (void) io_descr; - uart_busy = false; -} - -//------------- IMPLEMENTATION -------------// -void board_init(void) -{ - init_mcu(); - - /* Disable Watchdog */ - hri_wdt_set_MR_WDDIS_bit(WDT); - - // LED - _pmc_enable_periph_clock(ID_PIOC); - gpio_set_pin_level(LED_PIN, false); - gpio_set_pin_direction(LED_PIN, GPIO_DIRECTION_OUT); - gpio_set_pin_function(LED_PIN, GPIO_PIN_FUNCTION_OFF); - - // Button - _pmc_enable_periph_clock(ID_PIOA); - gpio_set_pin_direction(BUTTON_PIN, GPIO_DIRECTION_IN); - gpio_set_pin_pull_mode(BUTTON_PIN, GPIO_PULL_UP); - gpio_set_pin_function(BUTTON_PIN, GPIO_PIN_FUNCTION_OFF); - - // Uart via EDBG Com - _pmc_enable_periph_clock(ID_USART1); - gpio_set_pin_function(UART_RX_PIN, MUX_PA21A_USART1_RXD1); - gpio_set_pin_function(UART_TX_PIN, MUX_PB4D_USART1_TXD1); - - usart_async_init(&edbg_com, USART1, edbg_com_buffer, sizeof(edbg_com_buffer), _usart_get_usart_async()); - usart_async_set_baud_rate(&edbg_com, CFG_BOARD_UART_BAUDRATE); - usart_async_register_callback(&edbg_com, USART_ASYNC_TXC_CB, tx_cb_EDBG_COM); - usart_async_enable(&edbg_com); - -#if CFG_TUSB_OS == OPT_OS_NONE - // 1ms tick timer (samd SystemCoreClock may not correct) - SysTick_Config(CONF_CPU_FREQUENCY / 1000); -#endif - - // Enable USB clock - _pmc_enable_periph_clock(ID_USBHS); - -} - -//--------------------------------------------------------------------+ -// USB Interrupt Handler -//--------------------------------------------------------------------+ -void USBHS_Handler(void) -{ - tud_int_handler(0); -} - -//--------------------------------------------------------------------+ -// Board porting API -//--------------------------------------------------------------------+ - -void board_led_write(bool state) -{ - gpio_set_pin_level(LED_PIN, state); -} - -uint32_t board_button_read(void) -{ - return BUTTON_STATE_ACTIVE == gpio_get_pin_level(BUTTON_PIN); -} - -int board_uart_read(uint8_t* buf, int len) -{ - (void) buf; (void) len; - return 0; -} - -int board_uart_write(void const * buf, int len) -{ - // while until previous transfer is complete - while(uart_busy) {} - uart_busy = true; - - io_write(&edbg_com.io, buf, len); - return len; -} - -#if CFG_TUSB_OS == OPT_OS_NONE -volatile uint32_t system_ticks = 0; - -void SysTick_Handler (void) -{ - system_ticks++; -} - -uint32_t board_millis(void) -{ - return system_ticks; -} -#endif - -// Required by __libc_init_array in startup code if we are compiling using -// -nostdlib/-nostartfiles. -void _init(void) -{ - -} |