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Diffstat (limited to 'watch-library/include/instance/oscctrl.h')
| -rw-r--r-- | watch-library/include/instance/oscctrl.h | 86 |
1 files changed, 86 insertions, 0 deletions
diff --git a/watch-library/include/instance/oscctrl.h b/watch-library/include/instance/oscctrl.h new file mode 100644 index 00000000..bd390207 --- /dev/null +++ b/watch-library/include/instance/oscctrl.h @@ -0,0 +1,86 @@ +/** + * \file + * + * \brief Instance description for OSCCTRL + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML22_OSCCTRL_INSTANCE_ +#define _SAML22_OSCCTRL_INSTANCE_ + +/* ========== Register definition for OSCCTRL peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_OSCCTRL_INTENCLR (0x40001000) /**< \brief (OSCCTRL) Interrupt Enable Clear */ +#define REG_OSCCTRL_INTENSET (0x40001004) /**< \brief (OSCCTRL) Interrupt Enable Set */ +#define REG_OSCCTRL_INTFLAG (0x40001008) /**< \brief (OSCCTRL) Interrupt Flag Status and Clear */ +#define REG_OSCCTRL_STATUS (0x4000100C) /**< \brief (OSCCTRL) Power and Clocks Status */ +#define REG_OSCCTRL_XOSCCTRL (0x40001010) /**< \brief (OSCCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */ +#define REG_OSCCTRL_CFDPRESC (0x40001012) /**< \brief (OSCCTRL) Cloc Failure Detector Prescaler */ +#define REG_OSCCTRL_EVCTRL (0x40001013) /**< \brief (OSCCTRL) Event Control */ +#define REG_OSCCTRL_OSC16MCTRL (0x40001014) /**< \brief (OSCCTRL) 16MHz Internal Oscillator (OSC16M) Control */ +#define REG_OSCCTRL_DFLLCTRL (0x40001018) /**< \brief (OSCCTRL) DFLL48M Control */ +#define REG_OSCCTRL_DFLLVAL (0x4000101C) /**< \brief (OSCCTRL) DFLL48M Value */ +#define REG_OSCCTRL_DFLLMUL (0x40001020) /**< \brief (OSCCTRL) DFLL48M Multiplier */ +#define REG_OSCCTRL_DFLLSYNC (0x40001024) /**< \brief (OSCCTRL) DFLL48M Synchronization */ +#define REG_OSCCTRL_DPLLCTRLA (0x40001028) /**< \brief (OSCCTRL) DPLL Control */ +#define REG_OSCCTRL_DPLLRATIO (0x4000102C) /**< \brief (OSCCTRL) DPLL Ratio Control */ +#define REG_OSCCTRL_DPLLCTRLB (0x40001030) /**< \brief (OSCCTRL) Digital Core Configuration */ +#define REG_OSCCTRL_DPLLPRESC (0x40001034) /**< \brief (OSCCTRL) DPLL Prescaler */ +#define REG_OSCCTRL_DPLLSYNCBUSY (0x40001038) /**< \brief (OSCCTRL) DPLL Synchronization Busy */ +#define REG_OSCCTRL_DPLLSTATUS (0x4000103C) /**< \brief (OSCCTRL) DPLL Status */ +#else +#define REG_OSCCTRL_INTENCLR (*(RwReg *)0x40001000UL) /**< \brief (OSCCTRL) Interrupt Enable Clear */ +#define REG_OSCCTRL_INTENSET (*(RwReg *)0x40001004UL) /**< \brief (OSCCTRL) Interrupt Enable Set */ +#define REG_OSCCTRL_INTFLAG (*(RwReg *)0x40001008UL) /**< \brief (OSCCTRL) Interrupt Flag Status and Clear */ +#define REG_OSCCTRL_STATUS (*(RoReg *)0x4000100CUL) /**< \brief (OSCCTRL) Power and Clocks Status */ +#define REG_OSCCTRL_XOSCCTRL (*(RwReg16*)0x40001010UL) /**< \brief (OSCCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */ +#define REG_OSCCTRL_CFDPRESC (*(RwReg8 *)0x40001012UL) /**< \brief (OSCCTRL) Cloc Failure Detector Prescaler */ +#define REG_OSCCTRL_EVCTRL (*(RwReg8 *)0x40001013UL) /**< \brief (OSCCTRL) Event Control */ +#define REG_OSCCTRL_OSC16MCTRL (*(RwReg8 *)0x40001014UL) /**< \brief (OSCCTRL) 16MHz Internal Oscillator (OSC16M) Control */ +#define REG_OSCCTRL_DFLLCTRL (*(RwReg16*)0x40001018UL) /**< \brief (OSCCTRL) DFLL48M Control */ +#define REG_OSCCTRL_DFLLVAL (*(RwReg *)0x4000101CUL) /**< \brief (OSCCTRL) DFLL48M Value */ +#define REG_OSCCTRL_DFLLMUL (*(RwReg *)0x40001020UL) /**< \brief (OSCCTRL) DFLL48M Multiplier */ +#define REG_OSCCTRL_DFLLSYNC (*(RwReg8 *)0x40001024UL) /**< \brief (OSCCTRL) DFLL48M Synchronization */ +#define REG_OSCCTRL_DPLLCTRLA (*(RwReg8 *)0x40001028UL) /**< \brief (OSCCTRL) DPLL Control */ +#define REG_OSCCTRL_DPLLRATIO (*(RwReg *)0x4000102CUL) /**< \brief (OSCCTRL) DPLL Ratio Control */ +#define REG_OSCCTRL_DPLLCTRLB (*(RwReg *)0x40001030UL) /**< \brief (OSCCTRL) Digital Core Configuration */ +#define REG_OSCCTRL_DPLLPRESC (*(RwReg8 *)0x40001034UL) /**< \brief (OSCCTRL) DPLL Prescaler */ +#define REG_OSCCTRL_DPLLSYNCBUSY (*(RoReg8 *)0x40001038UL) /**< \brief (OSCCTRL) DPLL Synchronization Busy */ +#define REG_OSCCTRL_DPLLSTATUS (*(RoReg8 *)0x4000103CUL) /**< \brief (OSCCTRL) DPLL Status */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for OSCCTRL peripheral ========== */ +#define OSCCTRL_DFLL48M_COARSE_MSB 5 +#define OSCCTRL_DFLL48M_FINE_MSB 9 +#define OSCCTRL_GCLK_ID_DFLL48 0 // Index of Generic Clock for DFLL48 +#define OSCCTRL_GCLK_ID_FDPLL 1 // Index of Generic Clock for DPLL +#define OSCCTRL_GCLK_ID_FDPLL32K 2 // Index of Generic Clock for DPLL 32K +#define OSCCTRL_CFD_VERSION 0x100 +#define OSCCTRL_DFLL48M_VERSION 0x320 +#define OSCCTRL_FDPLL_VERSION 0x211 +#define OSCCTRL_OSC16M_VERSION 0x101 +#define OSCCTRL_XOSC_VERSION 0x201 + +#endif /* _SAML22_OSCCTRL_INSTANCE_ */ |