diff options
Diffstat (limited to 'watch-library/watch/watch_private.c')
| -rw-r--r-- | watch-library/watch/watch_private.c | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/watch-library/watch/watch_private.c b/watch-library/watch/watch_private.c index a4e2f72c..88d80be9 100644 --- a/watch-library/watch/watch_private.c +++ b/watch-library/watch/watch_private.c @@ -54,8 +54,14 @@ void _watch_enable_tcc() { hri_tcc_wait_for_sync(TCC0, TCC_SYNCBUSY_ENABLE); hri_tcc_write_CTRLA_reg(TCC0, TCC_CTRLA_SWRST); hri_tcc_wait_for_sync(TCC0, TCC_SYNCBUSY_SWRST); - // have prescaler divide our 8 MHz clock down to 1 MHz. - hri_tcc_write_CTRLA_reg(TCC0, TCC_CTRLA_PRESCALER_DIV8); + // divide the clock down to 1 MHz + if (hri_usbdevice_get_CTRLA_ENABLE_bit(USB)) { + // if USB is enabled, we are running an 8 MHz clock. + hri_tcc_write_CTRLA_reg(TCC0, TCC_CTRLA_PRESCALER_DIV8); + } else { + // otherwise it's 4 Mhz. + hri_tcc_write_CTRLA_reg(TCC0, TCC_CTRLA_PRESCALER_DIV4); + } // We're going to use normal PWM mode, which means period is controlled by PER, and duty cycle is controlled by // each compare channel's value: // * Buzzer tones are set by setting PER to the desired period for a given frequency, and CC[1] to half of that @@ -98,6 +104,9 @@ void _watch_enable_usb() { // disable USB, just in case. hri_usb_clear_CTRLA_ENABLE_bit(USB); + // bump clock up to 8 MHz + hri_oscctrl_write_OSC16MCTRL_FSEL_bf(OSCCTRL, OSCCTRL_OSC16MCTRL_FSEL_8_Val); + // reset flags and disable DFLL OSCCTRL->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRDY; OSCCTRL->DFLLCTRL.reg = 0; |