From 39a5c822a2a2e798e2e39ff8a98b7af84253026c Mon Sep 17 00:00:00 2001 From: Joey Castillo Date: Sat, 28 Aug 2021 12:50:18 -0400 Subject: add tinyusb --- tinyusb/hw/bsp/fomu/boards/fomu/board.h | 40 ++ tinyusb/hw/bsp/fomu/boards/fomu/board.mk | 1 + tinyusb/hw/bsp/fomu/crt0-vexriscv.S | 83 ++++ tinyusb/hw/bsp/fomu/dfu.py | 95 ++++ tinyusb/hw/bsp/fomu/family.mk | 30 ++ tinyusb/hw/bsp/fomu/fomu.c | 115 +++++ tinyusb/hw/bsp/fomu/fomu.ld | 104 +++++ tinyusb/hw/bsp/fomu/include/csr.h | 750 +++++++++++++++++++++++++++++++ tinyusb/hw/bsp/fomu/include/hw/common.h | 33 ++ tinyusb/hw/bsp/fomu/include/irq.h | 71 +++ tinyusb/hw/bsp/fomu/output_format.ld | 1 + tinyusb/hw/bsp/fomu/regions.ld | 6 + 12 files changed, 1329 insertions(+) create mode 100755 tinyusb/hw/bsp/fomu/boards/fomu/board.h create mode 100755 tinyusb/hw/bsp/fomu/boards/fomu/board.mk create mode 100755 tinyusb/hw/bsp/fomu/crt0-vexriscv.S create mode 100755 tinyusb/hw/bsp/fomu/dfu.py create mode 100755 tinyusb/hw/bsp/fomu/family.mk create mode 100755 tinyusb/hw/bsp/fomu/fomu.c create mode 100755 tinyusb/hw/bsp/fomu/fomu.ld create mode 100755 tinyusb/hw/bsp/fomu/include/csr.h create mode 100755 tinyusb/hw/bsp/fomu/include/hw/common.h create mode 100755 tinyusb/hw/bsp/fomu/include/irq.h create mode 100755 tinyusb/hw/bsp/fomu/output_format.ld create mode 100755 tinyusb/hw/bsp/fomu/regions.ld (limited to 'tinyusb/hw/bsp/fomu') diff --git a/tinyusb/hw/bsp/fomu/boards/fomu/board.h b/tinyusb/hw/bsp/fomu/boards/fomu/board.h new file mode 100755 index 00000000..666ba1d9 --- /dev/null +++ b/tinyusb/hw/bsp/fomu/boards/fomu/board.h @@ -0,0 +1,40 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +// Place holder only + +#ifdef __cplusplus + } +#endif + +#endif diff --git a/tinyusb/hw/bsp/fomu/boards/fomu/board.mk b/tinyusb/hw/bsp/fomu/boards/fomu/board.mk new file mode 100755 index 00000000..8ced1141 --- /dev/null +++ b/tinyusb/hw/bsp/fomu/boards/fomu/board.mk @@ -0,0 +1 @@ +# place holder \ No newline at end of file diff --git a/tinyusb/hw/bsp/fomu/crt0-vexriscv.S b/tinyusb/hw/bsp/fomu/crt0-vexriscv.S new file mode 100755 index 00000000..d80a29e0 --- /dev/null +++ b/tinyusb/hw/bsp/fomu/crt0-vexriscv.S @@ -0,0 +1,83 @@ +.global main +.global isr + +.section .text.start +.global _start + +_start: + j crt_init + +.section .text +.global trap_entry +trap_entry: + sw x1, - 1*4(sp) + sw x5, - 2*4(sp) + sw x6, - 3*4(sp) + sw x7, - 4*4(sp) + sw x10, - 5*4(sp) + sw x11, - 6*4(sp) + sw x12, - 7*4(sp) + sw x13, - 8*4(sp) + sw x14, - 9*4(sp) + sw x15, -10*4(sp) + sw x16, -11*4(sp) + sw x17, -12*4(sp) + sw x28, -13*4(sp) + sw x29, -14*4(sp) + sw x30, -15*4(sp) + sw x31, -16*4(sp) + addi sp,sp,-16*4 + call isr + lw x1 , 15*4(sp) + lw x5, 14*4(sp) + lw x6, 13*4(sp) + lw x7, 12*4(sp) + lw x10, 11*4(sp) + lw x11, 10*4(sp) + lw x12, 9*4(sp) + lw x13, 8*4(sp) + lw x14, 7*4(sp) + lw x15, 6*4(sp) + lw x16, 5*4(sp) + lw x17, 4*4(sp) + lw x28, 3*4(sp) + lw x29, 2*4(sp) + lw x30, 1*4(sp) + lw x31, 0*4(sp) + addi sp,sp,16*4 + mret + +.text +crt_init: + la sp, _estack - 4 + la a0, trap_entry + csrw mtvec, a0 + +bss_init: + la a0, _sbss + la a1, _ebss + 4 +bss_loop: + beq a0,a1,bss_done + sw zero,0(a0) + add a0,a0,4 + j bss_loop +bss_done: + + /* Load DATA */ + la t0, _etext + la t1, _srelocate + la t2, _erelocate + 4 +3: + lw t3, 0(t0) + sw t3, 0(t1) + /* _edata is aligned to 4 bytes. Use word-xfers. */ + addi t0, t0, 4 + addi t1, t1, 4 + bltu t1, t2, 3b + + li a0, 0x880 //880 enable timer + external interrupt sources (until mstatus.MIE is set, they will never trigger an interrupt) + csrw mie,a0 + + call main +infinite_loop: + j infinite_loop diff --git a/tinyusb/hw/bsp/fomu/dfu.py b/tinyusb/hw/bsp/fomu/dfu.py new file mode 100755 index 00000000..32479350 --- /dev/null +++ b/tinyusb/hw/bsp/fomu/dfu.py @@ -0,0 +1,95 @@ +#!/usr/bin/python + +# Written by Antonio Galea - 2010/11/18 +# Updated for DFU 1.1 by Sean Cross - 2020/03/31 +# Distributed under Gnu LGPL 3.0 +# see http://www.gnu.org/licenses/lgpl-3.0.txt + +import sys,struct,zlib,os +from optparse import OptionParser + +DEFAULT_DEVICE="0x1209:0x5bf0" + +def named(tuple,names): + return dict(zip(names.split(),tuple)) +def consume(fmt,data,names): + n = struct.calcsize(fmt) + return named(struct.unpack(fmt,data[:n]),names),data[n:] +def cstring(string): + return string.split('\0',1)[0] +def compute_crc(data): + return 0xFFFFFFFF & -zlib.crc32(data) -1 + +def parse(file,dump_images=False): + print ('File: "%s"' % file) + data = open(file,'rb').read() + crc = compute_crc(data[:-4]) + data = data[len(data)-16:] + suffix = named(struct.unpack('<4H3sBI',data[:16]),'device product vendor dfu ufd len crc') + print ('usb: %(vendor)04x:%(product)04x, device: 0x%(device)04x, dfu: 0x%(dfu)04x, %(ufd)s, %(len)d, 0x%(crc)08x' % suffix) + if crc != suffix['crc']: + print ("CRC ERROR: computed crc32 is 0x%08x" % crc) + data = data[16:] + if data: + print ("PARSE ERROR") + +def build(file,data,device=DEFAULT_DEVICE): + # Parse the VID and PID from the `device` argument + v,d=map(lambda x: int(x,0) & 0xFFFF, device.split(':',1)) + + # Generate the DFU suffix, consisting of these fields: + # Field name | Length | Description + # ================+=========+================================ + # bcdDevice | 2 | The release number of this firmware (0xffff - don't care) + # idProduct | 2 | PID of this device + # idVendor | 2 | VID of this device + # bcdDFU | 2 | Version of this DFU spec (0x01 0x00) + # ucDfuSignature | 3 | The characters 'DFU', printed in reverse order + # bLength | 1 | The length of this suffix (16 bytes) + # dwCRC | 4 | A CRC32 of the data, including this suffix + data += struct.pack('<4H3sB',0xffff,d,v,0x0100,b'UFD',16) + crc = compute_crc(data) + # Append the CRC32 of the entire block + data += struct.pack(' +#include +#include "../board.h" +#include "csr.h" +#include "irq.h" + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ + +void fomu_error(uint32_t line) +{ + (void)line; + TU_BREAKPOINT(); +} + +volatile uint32_t system_ticks = 0; +static void timer_init(void) +{ + int t; + + timer0_en_write(0); + t = CONFIG_CLOCK_FREQUENCY / 1000; // 1000 kHz tick + timer0_reload_write(t); + timer0_load_write(t); + timer0_en_write(1); + timer0_ev_enable_write(1); + timer0_ev_pending_write(1); + irq_setmask(irq_getmask() | (1 << TIMER0_INTERRUPT)); +} + +void isr(void) +{ + unsigned int irqs; + + irqs = irq_pending() & irq_getmask(); + +#if CFG_TUSB_RHPORT0_MODE == OPT_MODE_DEVICE + if (irqs & (1 << USB_INTERRUPT)) { + tud_int_handler(0); + } +#endif + if (irqs & (1 << TIMER0_INTERRUPT)) { + system_ticks++; + timer0_ev_pending_write(1); + } +} + +void board_init(void) +{ + irq_setmask(0); + irq_setie(1); + timer_init(); + return; +} + +void board_led_write(bool state) +{ + rgb_ctrl_write(0xff); + rgb_raw_write(state); +} + +uint32_t board_button_read(void) +{ + return 0; +} + +int board_uart_read(uint8_t* buf, int len) +{ + (void) buf; + (void) len; + return 0; +} + +int board_uart_write(void const * buf, int len) +{ + int32_t offset = 0; + for (offset = 0; offset < len; offset++) + if (! (messible_status_read() & CSR_MESSIBLE_STATUS_FULL_OFFSET)) + messible_in_write(((uint8_t *)buf)[offset]); + return len; +} + +#if CFG_TUSB_OS == OPT_OS_NONE +uint32_t board_millis(void) +{ + return system_ticks; +} +#endif diff --git a/tinyusb/hw/bsp/fomu/fomu.ld b/tinyusb/hw/bsp/fomu/fomu.ld new file mode 100755 index 00000000..13278d2a --- /dev/null +++ b/tinyusb/hw/bsp/fomu/fomu.ld @@ -0,0 +1,104 @@ +OUTPUT_FORMAT("elf32-littleriscv") +ENTRY(_start) + +__DYNAMIC = 0; + +MEMORY { + csr : ORIGIN = 0x60000000, LENGTH = 0x01000000 + vexriscv_debug : ORIGIN = 0xf00f0000, LENGTH = 0x00000100 + ram : ORIGIN = 0x10000000, LENGTH = 0x00020000 + rom : ORIGIN = 0x20040000, LENGTH = 0x00200000 - 0x40000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _ftext = .; + *(.text.start) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + } > rom + + . = ALIGN(4); + _etext = .; /* End of text section */ + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(.sbss .sbss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + end = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; +} diff --git a/tinyusb/hw/bsp/fomu/include/csr.h b/tinyusb/hw/bsp/fomu/include/csr.h new file mode 100755 index 00000000..a2f60ecf --- /dev/null +++ b/tinyusb/hw/bsp/fomu/include/csr.h @@ -0,0 +1,750 @@ +//-------------------------------------------------------------------------------- +// Auto-generated by Migen (f4fcd10) & LiteX (1425a68d) on 2019-11-12 19:41:49 +//-------------------------------------------------------------------------------- +#ifndef __GENERATED_CSR_H +#define __GENERATED_CSR_H +#include +#ifdef CSR_ACCESSORS_DEFINED +extern void csr_writeb(uint8_t value, unsigned long addr); +extern uint8_t csr_readb(unsigned long addr); +extern void csr_writew(uint16_t value, unsigned long addr); +extern uint16_t csr_readw(unsigned long addr); +extern void csr_writel(uint32_t value, unsigned long addr); +extern uint32_t csr_readl(unsigned long addr); +#else /* ! CSR_ACCESSORS_DEFINED */ +#include +#endif /* ! CSR_ACCESSORS_DEFINED */ + +/* ctrl */ +#define CSR_CTRL_BASE 0xe0000000L +#define CSR_CTRL_RESET_ADDR 0xe0000000L +#define CSR_CTRL_RESET_SIZE 1 +static inline unsigned char ctrl_reset_read(void) { + unsigned char r = csr_readl(0xe0000000L); + return r; +} +static inline void ctrl_reset_write(unsigned char value) { + csr_writel(value, 0xe0000000L); +} +#define CSR_CTRL_SCRATCH_ADDR 0xe0000004L +#define CSR_CTRL_SCRATCH_SIZE 4 +static inline unsigned int ctrl_scratch_read(void) { + unsigned int r = csr_readl(0xe0000004L); + r <<= 8; + r |= csr_readl(0xe0000008L); + r <<= 8; + r |= csr_readl(0xe000000cL); + r <<= 8; + r |= csr_readl(0xe0000010L); + return r; +} +static inline void ctrl_scratch_write(unsigned int value) { + csr_writel(value >> 24, 0xe0000004L); + csr_writel(value >> 16, 0xe0000008L); + csr_writel(value >> 8, 0xe000000cL); + csr_writel(value, 0xe0000010L); +} +#define CSR_CTRL_BUS_ERRORS_ADDR 0xe0000014L +#define CSR_CTRL_BUS_ERRORS_SIZE 4 +static inline unsigned int ctrl_bus_errors_read(void) { + unsigned int r = csr_readl(0xe0000014L); + r <<= 8; + r |= csr_readl(0xe0000018L); + r <<= 8; + r |= csr_readl(0xe000001cL); + r <<= 8; + r |= csr_readl(0xe0000020L); + return r; +} + +/* messible */ +#define CSR_MESSIBLE_BASE 0xe0008000L +#define CSR_MESSIBLE_IN_ADDR 0xe0008000L +#define CSR_MESSIBLE_IN_SIZE 1 +static inline unsigned char messible_in_read(void) { + unsigned char r = csr_readl(0xe0008000L); + return r; +} +static inline void messible_in_write(unsigned char value) { + csr_writel(value, 0xe0008000L); +} +#define CSR_MESSIBLE_OUT_ADDR 0xe0008004L +#define CSR_MESSIBLE_OUT_SIZE 1 +static inline unsigned char messible_out_read(void) { + unsigned char r = csr_readl(0xe0008004L); + return r; +} +#define CSR_MESSIBLE_STATUS_ADDR 0xe0008008L +#define CSR_MESSIBLE_STATUS_SIZE 1 +static inline unsigned char messible_status_read(void) { + unsigned char r = csr_readl(0xe0008008L); + return r; +} +#define CSR_MESSIBLE_STATUS_FULL_OFFSET 0 +#define CSR_MESSIBLE_STATUS_FULL_SIZE 1 +#define CSR_MESSIBLE_STATUS_HAVE_OFFSET 1 +#define CSR_MESSIBLE_STATUS_HAVE_SIZE 1 + +/* picorvspi */ +#define CSR_PICORVSPI_BASE 0xe0005000L +#define CSR_PICORVSPI_CFG1_ADDR 0xe0005000L +#define CSR_PICORVSPI_CFG1_SIZE 1 +static inline unsigned char picorvspi_cfg1_read(void) { + unsigned char r = csr_readl(0xe0005000L); + return r; +} +static inline void picorvspi_cfg1_write(unsigned char value) { + csr_writel(value, 0xe0005000L); +} +#define CSR_PICORVSPI_CFG1_BB_OUT_OFFSET 0 +#define CSR_PICORVSPI_CFG1_BB_OUT_SIZE 4 +#define CSR_PICORVSPI_CFG1_BB_CLK_OFFSET 4 +#define CSR_PICORVSPI_CFG1_BB_CLK_SIZE 1 +#define CSR_PICORVSPI_CFG1_BB_CS_OFFSET 5 +#define CSR_PICORVSPI_CFG1_BB_CS_SIZE 1 +#define CSR_PICORVSPI_CFG2_ADDR 0xe0005004L +#define CSR_PICORVSPI_CFG2_SIZE 1 +static inline unsigned char picorvspi_cfg2_read(void) { + unsigned char r = csr_readl(0xe0005004L); + return r; +} +static inline void picorvspi_cfg2_write(unsigned char value) { + csr_writel(value, 0xe0005004L); +} +#define CSR_PICORVSPI_CFG2_BB_OE_OFFSET 0 +#define CSR_PICORVSPI_CFG2_BB_OE_SIZE 4 +#define CSR_PICORVSPI_CFG3_ADDR 0xe0005008L +#define CSR_PICORVSPI_CFG3_SIZE 1 +static inline unsigned char picorvspi_cfg3_read(void) { + unsigned char r = csr_readl(0xe0005008L); + return r; +} +static inline void picorvspi_cfg3_write(unsigned char value) { + csr_writel(value, 0xe0005008L); +} +#define CSR_PICORVSPI_CFG3_RLAT_OFFSET 0 +#define CSR_PICORVSPI_CFG3_RLAT_SIZE 4 +#define CSR_PICORVSPI_CFG3_CRM_OFFSET 4 +#define CSR_PICORVSPI_CFG3_CRM_SIZE 1 +#define CSR_PICORVSPI_CFG3_QSPI_OFFSET 5 +#define CSR_PICORVSPI_CFG3_QSPI_SIZE 1 +#define CSR_PICORVSPI_CFG3_DDR_OFFSET 6 +#define CSR_PICORVSPI_CFG3_DDR_SIZE 1 +#define CSR_PICORVSPI_CFG4_ADDR 0xe000500cL +#define CSR_PICORVSPI_CFG4_SIZE 1 +static inline unsigned char picorvspi_cfg4_read(void) { + unsigned char r = csr_readl(0xe000500cL); + return r; +} +static inline void picorvspi_cfg4_write(unsigned char value) { + csr_writel(value, 0xe000500cL); +} +#define CSR_PICORVSPI_CFG4_MEMIO_OFFSET 7 +#define CSR_PICORVSPI_CFG4_MEMIO_SIZE 1 +#define CSR_PICORVSPI_STAT1_ADDR 0xe0005010L +#define CSR_PICORVSPI_STAT1_SIZE 1 +static inline unsigned char picorvspi_stat1_read(void) { + unsigned char r = csr_readl(0xe0005010L); + return r; +} +#define CSR_PICORVSPI_STAT1_BB_IN_OFFSET 0 +#define CSR_PICORVSPI_STAT1_BB_IN_SIZE 4 +#define CSR_PICORVSPI_STAT2_ADDR 0xe0005014L +#define CSR_PICORVSPI_STAT2_SIZE 1 +static inline unsigned char picorvspi_stat2_read(void) { + unsigned char r = csr_readl(0xe0005014L); + return r; +} +#define CSR_PICORVSPI_STAT3_ADDR 0xe0005018L +#define CSR_PICORVSPI_STAT3_SIZE 1 +static inline unsigned char picorvspi_stat3_read(void) { + unsigned char r = csr_readl(0xe0005018L); + return r; +} +#define CSR_PICORVSPI_STAT4_ADDR 0xe000501cL +#define CSR_PICORVSPI_STAT4_SIZE 1 +static inline unsigned char picorvspi_stat4_read(void) { + unsigned char r = csr_readl(0xe000501cL); + return r; +} + +/* reboot */ +#define CSR_REBOOT_BASE 0xe0006000L +#define CSR_REBOOT_CTRL_ADDR 0xe0006000L +#define CSR_REBOOT_CTRL_SIZE 1 +static inline unsigned char reboot_ctrl_read(void) { + unsigned char r = csr_readl(0xe0006000L); + return r; +} +static inline void reboot_ctrl_write(unsigned char value) { + csr_writel(value, 0xe0006000L); +} +#define CSR_REBOOT_CTRL_IMAGE_OFFSET 0 +#define CSR_REBOOT_CTRL_IMAGE_SIZE 2 +#define CSR_REBOOT_CTRL_KEY_OFFSET 2 +#define CSR_REBOOT_CTRL_KEY_SIZE 6 +#define CSR_REBOOT_ADDR_ADDR 0xe0006004L +#define CSR_REBOOT_ADDR_SIZE 4 +static inline unsigned int reboot_addr_read(void) { + unsigned int r = csr_readl(0xe0006004L); + r <<= 8; + r |= csr_readl(0xe0006008L); + r <<= 8; + r |= csr_readl(0xe000600cL); + r <<= 8; + r |= csr_readl(0xe0006010L); + return r; +} +static inline void reboot_addr_write(unsigned int value) { + csr_writel(value >> 24, 0xe0006004L); + csr_writel(value >> 16, 0xe0006008L); + csr_writel(value >> 8, 0xe000600cL); + csr_writel(value, 0xe0006010L); +} + +/* rgb */ +#define CSR_RGB_BASE 0xe0006800L +#define CSR_RGB_DAT_ADDR 0xe0006800L +#define CSR_RGB_DAT_SIZE 1 +static inline unsigned char rgb_dat_read(void) { + unsigned char r = csr_readl(0xe0006800L); + return r; +} +static inline void rgb_dat_write(unsigned char value) { + csr_writel(value, 0xe0006800L); +} +#define CSR_RGB_ADDR_ADDR 0xe0006804L +#define CSR_RGB_ADDR_SIZE 1 +static inline unsigned char rgb_addr_read(void) { + unsigned char r = csr_readl(0xe0006804L); + return r; +} +static inline void rgb_addr_write(unsigned char value) { + csr_writel(value, 0xe0006804L); +} +#define CSR_RGB_CTRL_ADDR 0xe0006808L +#define CSR_RGB_CTRL_SIZE 1 +static inline unsigned char rgb_ctrl_read(void) { + unsigned char r = csr_readl(0xe0006808L); + return r; +} +static inline void rgb_ctrl_write(unsigned char value) { + csr_writel(value, 0xe0006808L); +} +#define CSR_RGB_CTRL_EXE_OFFSET 0 +#define CSR_RGB_CTRL_EXE_SIZE 1 +#define CSR_RGB_CTRL_CURREN_OFFSET 1 +#define CSR_RGB_CTRL_CURREN_SIZE 1 +#define CSR_RGB_CTRL_RGBLEDEN_OFFSET 2 +#define CSR_RGB_CTRL_RGBLEDEN_SIZE 1 +#define CSR_RGB_CTRL_RRAW_OFFSET 3 +#define CSR_RGB_CTRL_RRAW_SIZE 1 +#define CSR_RGB_CTRL_GRAW_OFFSET 4 +#define CSR_RGB_CTRL_GRAW_SIZE 1 +#define CSR_RGB_CTRL_BRAW_OFFSET 5 +#define CSR_RGB_CTRL_BRAW_SIZE 1 +#define CSR_RGB_RAW_ADDR 0xe000680cL +#define CSR_RGB_RAW_SIZE 1 +static inline unsigned char rgb_raw_read(void) { + unsigned char r = csr_readl(0xe000680cL); + return r; +} +static inline void rgb_raw_write(unsigned char value) { + csr_writel(value, 0xe000680cL); +} +#define CSR_RGB_RAW_R_OFFSET 0 +#define CSR_RGB_RAW_R_SIZE 1 +#define CSR_RGB_RAW_G_OFFSET 1 +#define CSR_RGB_RAW_G_SIZE 1 +#define CSR_RGB_RAW_B_OFFSET 2 +#define CSR_RGB_RAW_B_SIZE 1 + +/* timer0 */ +#define CSR_TIMER0_BASE 0xe0002800L +#define CSR_TIMER0_LOAD_ADDR 0xe0002800L +#define CSR_TIMER0_LOAD_SIZE 4 +static inline unsigned int timer0_load_read(void) { + unsigned int r = csr_readl(0xe0002800L); + r <<= 8; + r |= csr_readl(0xe0002804L); + r <<= 8; + r |= csr_readl(0xe0002808L); + r <<= 8; + r |= csr_readl(0xe000280cL); + return r; +} +static inline void timer0_load_write(unsigned int value) { + csr_writel(value >> 24, 0xe0002800L); + csr_writel(value >> 16, 0xe0002804L); + csr_writel(value >> 8, 0xe0002808L); + csr_writel(value, 0xe000280cL); +} +#define CSR_TIMER0_RELOAD_ADDR 0xe0002810L +#define CSR_TIMER0_RELOAD_SIZE 4 +static inline unsigned int timer0_reload_read(void) { + unsigned int r = csr_readl(0xe0002810L); + r <<= 8; + r |= csr_readl(0xe0002814L); + r <<= 8; + r |= csr_readl(0xe0002818L); + r <<= 8; + r |= csr_readl(0xe000281cL); + return r; +} +static inline void timer0_reload_write(unsigned int value) { + csr_writel(value >> 24, 0xe0002810L); + csr_writel(value >> 16, 0xe0002814L); + csr_writel(value >> 8, 0xe0002818L); + csr_writel(value, 0xe000281cL); +} +#define CSR_TIMER0_EN_ADDR 0xe0002820L +#define CSR_TIMER0_EN_SIZE 1 +static inline unsigned char timer0_en_read(void) { + unsigned char r = csr_readl(0xe0002820L); + return r; +} +static inline void timer0_en_write(unsigned char value) { + csr_writel(value, 0xe0002820L); +} +#define CSR_TIMER0_UPDATE_VALUE_ADDR 0xe0002824L +#define CSR_TIMER0_UPDATE_VALUE_SIZE 1 +static inline unsigned char timer0_update_value_read(void) { + unsigned char r = csr_readl(0xe0002824L); + return r; +} +static inline void timer0_update_value_write(unsigned char value) { + csr_writel(value, 0xe0002824L); +} +#define CSR_TIMER0_VALUE_ADDR 0xe0002828L +#define CSR_TIMER0_VALUE_SIZE 4 +static inline unsigned int timer0_value_read(void) { + unsigned int r = csr_readl(0xe0002828L); + r <<= 8; + r |= csr_readl(0xe000282cL); + r <<= 8; + r |= csr_readl(0xe0002830L); + r <<= 8; + r |= csr_readl(0xe0002834L); + return r; +} +#define CSR_TIMER0_EV_STATUS_ADDR 0xe0002838L +#define CSR_TIMER0_EV_STATUS_SIZE 1 +static inline unsigned char timer0_ev_status_read(void) { + unsigned char r = csr_readl(0xe0002838L); + return r; +} +static inline void timer0_ev_status_write(unsigned char value) { + csr_writel(value, 0xe0002838L); +} +#define CSR_TIMER0_EV_PENDING_ADDR 0xe000283cL +#define CSR_TIMER0_EV_PENDING_SIZE 1 +static inline unsigned char timer0_ev_pending_read(void) { + unsigned char r = csr_readl(0xe000283cL); + return r; +} +static inline void timer0_ev_pending_write(unsigned char value) { + csr_writel(value, 0xe000283cL); +} +#define CSR_TIMER0_EV_ENABLE_ADDR 0xe0002840L +#define CSR_TIMER0_EV_ENABLE_SIZE 1 +static inline unsigned char timer0_ev_enable_read(void) { + unsigned char r = csr_readl(0xe0002840L); + return r; +} +static inline void timer0_ev_enable_write(unsigned char value) { + csr_writel(value, 0xe0002840L); +} + +/* touch */ +#define CSR_TOUCH_BASE 0xe0005800L +#define CSR_TOUCH_O_ADDR 0xe0005800L +#define CSR_TOUCH_O_SIZE 1 +static inline unsigned char touch_o_read(void) { + unsigned char r = csr_readl(0xe0005800L); + return r; +} +static inline void touch_o_write(unsigned char value) { + csr_writel(value, 0xe0005800L); +} +#define CSR_TOUCH_O_O_OFFSET 0 +#define CSR_TOUCH_O_O_SIZE 4 +#define CSR_TOUCH_OE_ADDR 0xe0005804L +#define CSR_TOUCH_OE_SIZE 1 +static inline unsigned char touch_oe_read(void) { + unsigned char r = csr_readl(0xe0005804L); + return r; +} +static inline void touch_oe_write(unsigned char value) { + csr_writel(value, 0xe0005804L); +} +#define CSR_TOUCH_OE_OE_OFFSET 0 +#define CSR_TOUCH_OE_OE_SIZE 4 +#define CSR_TOUCH_I_ADDR 0xe0005808L +#define CSR_TOUCH_I_SIZE 1 +static inline unsigned char touch_i_read(void) { + unsigned char r = csr_readl(0xe0005808L); + return r; +} +#define CSR_TOUCH_I_I_OFFSET 0 +#define CSR_TOUCH_I_I_SIZE 4 + +/* usb */ +#define CSR_USB_BASE 0xe0004800L +#define CSR_USB_PULLUP_OUT_ADDR 0xe0004800L +#define CSR_USB_PULLUP_OUT_SIZE 1 +static inline unsigned char usb_pullup_out_read(void) { + unsigned char r = csr_readl(0xe0004800L); + return r; +} +static inline void usb_pullup_out_write(unsigned char value) { + csr_writel(value, 0xe0004800L); +} +#define CSR_USB_ADDRESS_ADDR 0xe0004804L +#define CSR_USB_ADDRESS_SIZE 1 +static inline unsigned char usb_address_read(void) { + unsigned char r = csr_readl(0xe0004804L); + return r; +} +static inline void usb_address_write(unsigned char value) { + csr_writel(value, 0xe0004804L); +} +#define CSR_USB_ADDRESS_ADDR_OFFSET 0 +#define CSR_USB_ADDRESS_ADDR_SIZE 7 +#define CSR_USB_NEXT_EV_ADDR 0xe0004808L +#define CSR_USB_NEXT_EV_SIZE 1 +static inline unsigned char usb_next_ev_read(void) { + unsigned char r = csr_readl(0xe0004808L); + return r; +} +#define CSR_USB_NEXT_EV_IN_OFFSET 0 +#define CSR_USB_NEXT_EV_IN_SIZE 1 +#define CSR_USB_NEXT_EV_OUT_OFFSET 1 +#define CSR_USB_NEXT_EV_OUT_SIZE 1 +#define CSR_USB_NEXT_EV_SETUP_OFFSET 2 +#define CSR_USB_NEXT_EV_SETUP_SIZE 1 +#define CSR_USB_NEXT_EV_RESET_OFFSET 3 +#define CSR_USB_NEXT_EV_RESET_SIZE 1 +#define CSR_USB_SETUP_DATA_ADDR 0xe000480cL +#define CSR_USB_SETUP_DATA_SIZE 1 +static inline unsigned char usb_setup_data_read(void) { + unsigned char r = csr_readl(0xe000480cL); + return r; +} +#define CSR_USB_SETUP_DATA_DATA_OFFSET 0 +#define CSR_USB_SETUP_DATA_DATA_SIZE 8 +#define CSR_USB_SETUP_CTRL_ADDR 0xe0004810L +#define CSR_USB_SETUP_CTRL_SIZE 1 +static inline unsigned char usb_setup_ctrl_read(void) { + unsigned char r = csr_readl(0xe0004810L); + return r; +} +static inline void usb_setup_ctrl_write(unsigned char value) { + csr_writel(value, 0xe0004810L); +} +#define CSR_USB_SETUP_CTRL_RESET_OFFSET 5 +#define CSR_USB_SETUP_CTRL_RESET_SIZE 1 +#define CSR_USB_SETUP_STATUS_ADDR 0xe0004814L +#define CSR_USB_SETUP_STATUS_SIZE 1 +static inline unsigned char usb_setup_status_read(void) { + unsigned char r = csr_readl(0xe0004814L); + return r; +} +#define CSR_USB_SETUP_STATUS_EPNO_OFFSET 0 +#define CSR_USB_SETUP_STATUS_EPNO_SIZE 4 +#define CSR_USB_SETUP_STATUS_HAVE_OFFSET 4 +#define CSR_USB_SETUP_STATUS_HAVE_SIZE 1 +#define CSR_USB_SETUP_STATUS_PEND_OFFSET 5 +#define CSR_USB_SETUP_STATUS_PEND_SIZE 1 +#define CSR_USB_SETUP_STATUS_IS_IN_OFFSET 6 +#define CSR_USB_SETUP_STATUS_IS_IN_SIZE 1 +#define CSR_USB_SETUP_STATUS_DATA_OFFSET 7 +#define CSR_USB_SETUP_STATUS_DATA_SIZE 1 +#define CSR_USB_SETUP_EV_STATUS_ADDR 0xe0004818L +#define CSR_USB_SETUP_EV_STATUS_SIZE 1 +static inline unsigned char usb_setup_ev_status_read(void) { + unsigned char r = csr_readl(0xe0004818L); + return r; +} +static inline void usb_setup_ev_status_write(unsigned char value) { + csr_writel(value, 0xe0004818L); +} +#define CSR_USB_SETUP_EV_PENDING_ADDR 0xe000481cL +#define CSR_USB_SETUP_EV_PENDING_SIZE 1 +static inline unsigned char usb_setup_ev_pending_read(void) { + unsigned char r = csr_readl(0xe000481cL); + return r; +} +static inline void usb_setup_ev_pending_write(unsigned char value) { + csr_writel(value, 0xe000481cL); +} +#define CSR_USB_SETUP_EV_ENABLE_ADDR 0xe0004820L +#define CSR_USB_SETUP_EV_ENABLE_SIZE 1 +static inline unsigned char usb_setup_ev_enable_read(void) { + unsigned char r = csr_readl(0xe0004820L); + return r; +} +static inline void usb_setup_ev_enable_write(unsigned char value) { + csr_writel(value, 0xe0004820L); +} +#define CSR_USB_IN_DATA_ADDR 0xe0004824L +#define CSR_USB_IN_DATA_SIZE 1 +static inline unsigned char usb_in_data_read(void) { + unsigned char r = csr_readl(0xe0004824L); + return r; +} +static inline void usb_in_data_write(unsigned char value) { + csr_writel(value, 0xe0004824L); +} +#define CSR_USB_IN_DATA_DATA_OFFSET 0 +#define CSR_USB_IN_DATA_DATA_SIZE 8 +#define CSR_USB_IN_CTRL_ADDR 0xe0004828L +#define CSR_USB_IN_CTRL_SIZE 1 +static inline unsigned char usb_in_ctrl_read(void) { + unsigned char r = csr_readl(0xe0004828L); + return r; +} +static inline void usb_in_ctrl_write(unsigned char value) { + csr_writel(value, 0xe0004828L); +} +#define CSR_USB_IN_CTRL_EPNO_OFFSET 0 +#define CSR_USB_IN_CTRL_EPNO_SIZE 4 +#define CSR_USB_IN_CTRL_RESET_OFFSET 5 +#define CSR_USB_IN_CTRL_RESET_SIZE 1 +#define CSR_USB_IN_CTRL_STALL_OFFSET 6 +#define CSR_USB_IN_CTRL_STALL_SIZE 1 +#define CSR_USB_IN_STATUS_ADDR 0xe000482cL +#define CSR_USB_IN_STATUS_SIZE 1 +static inline unsigned char usb_in_status_read(void) { + unsigned char r = csr_readl(0xe000482cL); + return r; +} +#define CSR_USB_IN_STATUS_IDLE_OFFSET 0 +#define CSR_USB_IN_STATUS_IDLE_SIZE 1 +#define CSR_USB_IN_STATUS_HAVE_OFFSET 4 +#define CSR_USB_IN_STATUS_HAVE_SIZE 1 +#define CSR_USB_IN_STATUS_PEND_OFFSET 5 +#define CSR_USB_IN_STATUS_PEND_SIZE 1 +#define CSR_USB_IN_EV_STATUS_ADDR 0xe0004830L +#define CSR_USB_IN_EV_STATUS_SIZE 1 +static inline unsigned char usb_in_ev_status_read(void) { + unsigned char r = csr_readl(0xe0004830L); + return r; +} +static inline void usb_in_ev_status_write(unsigned char value) { + csr_writel(value, 0xe0004830L); +} +#define CSR_USB_IN_EV_PENDING_ADDR 0xe0004834L +#define CSR_USB_IN_EV_PENDING_SIZE 1 +static inline unsigned char usb_in_ev_pending_read(void) { + unsigned char r = csr_readl(0xe0004834L); + return r; +} +static inline void usb_in_ev_pending_write(unsigned char value) { + csr_writel(value, 0xe0004834L); +} +#define CSR_USB_IN_EV_ENABLE_ADDR 0xe0004838L +#define CSR_USB_IN_EV_ENABLE_SIZE 1 +static inline unsigned char usb_in_ev_enable_read(void) { + unsigned char r = csr_readl(0xe0004838L); + return r; +} +static inline void usb_in_ev_enable_write(unsigned char value) { + csr_writel(value, 0xe0004838L); +} +#define CSR_USB_OUT_DATA_ADDR 0xe000483cL +#define CSR_USB_OUT_DATA_SIZE 1 +static inline unsigned char usb_out_data_read(void) { + unsigned char r = csr_readl(0xe000483cL); + return r; +} +#define CSR_USB_OUT_DATA_DATA_OFFSET 0 +#define CSR_USB_OUT_DATA_DATA_SIZE 8 +#define CSR_USB_OUT_CTRL_ADDR 0xe0004840L +#define CSR_USB_OUT_CTRL_SIZE 1 +static inline unsigned char usb_out_ctrl_read(void) { + unsigned char r = csr_readl(0xe0004840L); + return r; +} +static inline void usb_out_ctrl_write(unsigned char value) { + csr_writel(value, 0xe0004840L); +} +#define CSR_USB_OUT_CTRL_EPNO_OFFSET 0 +#define CSR_USB_OUT_CTRL_EPNO_SIZE 4 +#define CSR_USB_OUT_CTRL_ENABLE_OFFSET 4 +#define CSR_USB_OUT_CTRL_ENABLE_SIZE 1 +#define CSR_USB_OUT_CTRL_RESET_OFFSET 5 +#define CSR_USB_OUT_CTRL_RESET_SIZE 1 +#define CSR_USB_OUT_CTRL_STALL_OFFSET 6 +#define CSR_USB_OUT_CTRL_STALL_SIZE 1 +#define CSR_USB_OUT_STATUS_ADDR 0xe0004844L +#define CSR_USB_OUT_STATUS_SIZE 1 +static inline unsigned char usb_out_status_read(void) { + unsigned char r = csr_readl(0xe0004844L); + return r; +} +#define CSR_USB_OUT_STATUS_EPNO_OFFSET 0 +#define CSR_USB_OUT_STATUS_EPNO_SIZE 4 +#define CSR_USB_OUT_STATUS_HAVE_OFFSET 4 +#define CSR_USB_OUT_STATUS_HAVE_SIZE 1 +#define CSR_USB_OUT_STATUS_PEND_OFFSET 5 +#define CSR_USB_OUT_STATUS_PEND_SIZE 1 +#define CSR_USB_OUT_EV_STATUS_ADDR 0xe0004848L +#define CSR_USB_OUT_EV_STATUS_SIZE 1 +static inline unsigned char usb_out_ev_status_read(void) { + unsigned char r = csr_readl(0xe0004848L); + return r; +} +static inline void usb_out_ev_status_write(unsigned char value) { + csr_writel(value, 0xe0004848L); +} +#define CSR_USB_OUT_EV_PENDING_ADDR 0xe000484cL +#define CSR_USB_OUT_EV_PENDING_SIZE 1 +static inline unsigned char usb_out_ev_pending_read(void) { + unsigned char r = csr_readl(0xe000484cL); + return r; +} +static inline void usb_out_ev_pending_write(unsigned char value) { + csr_writel(value, 0xe000484cL); +} +#define CSR_USB_OUT_EV_ENABLE_ADDR 0xe0004850L +#define CSR_USB_OUT_EV_ENABLE_SIZE 1 +static inline unsigned char usb_out_ev_enable_read(void) { + unsigned char r = csr_readl(0xe0004850L); + return r; +} +static inline void usb_out_ev_enable_write(unsigned char value) { + csr_writel(value, 0xe0004850L); +} +#define CSR_USB_OUT_ENABLE_STATUS_ADDR 0xe0004854L +#define CSR_USB_OUT_ENABLE_STATUS_SIZE 1 +static inline unsigned char usb_out_enable_status_read(void) { + unsigned char r = csr_readl(0xe0004854L); + return r; +} +#define CSR_USB_OUT_STALL_STATUS_ADDR 0xe0004858L +#define CSR_USB_OUT_STALL_STATUS_SIZE 1 +static inline unsigned char usb_out_stall_status_read(void) { + unsigned char r = csr_readl(0xe0004858L); + return r; +} + +/* version */ +#define CSR_VERSION_BASE 0xe0007000L +#define CSR_VERSION_MAJOR_ADDR 0xe0007000L +#define CSR_VERSION_MAJOR_SIZE 1 +static inline unsigned char version_major_read(void) { + unsigned char r = csr_readl(0xe0007000L); + return r; +} +#define CSR_VERSION_MINOR_ADDR 0xe0007004L +#define CSR_VERSION_MINOR_SIZE 1 +static inline unsigned char version_minor_read(void) { + unsigned char r = csr_readl(0xe0007004L); + return r; +} +#define CSR_VERSION_REVISION_ADDR 0xe0007008L +#define CSR_VERSION_REVISION_SIZE 1 +static inline unsigned char version_revision_read(void) { + unsigned char r = csr_readl(0xe0007008L); + return r; +} +#define CSR_VERSION_GITREV_ADDR 0xe000700cL +#define CSR_VERSION_GITREV_SIZE 4 +static inline unsigned int version_gitrev_read(void) { + unsigned int r = csr_readl(0xe000700cL); + r <<= 8; + r |= csr_readl(0xe0007010L); + r <<= 8; + r |= csr_readl(0xe0007014L); + r <<= 8; + r |= csr_readl(0xe0007018L); + return r; +} +#define CSR_VERSION_GITEXTRA_ADDR 0xe000701cL +#define CSR_VERSION_GITEXTRA_SIZE 2 +static inline unsigned short int version_gitextra_read(void) { + unsigned short int r = csr_readl(0xe000701cL); + r <<= 8; + r |= csr_readl(0xe0007020L); + return r; +} +#define CSR_VERSION_DIRTY_ADDR 0xe0007024L +#define CSR_VERSION_DIRTY_SIZE 1 +static inline unsigned char version_dirty_read(void) { + unsigned char r = csr_readl(0xe0007024L); + return r; +} +#define CSR_VERSION_DIRTY_DIRTY_OFFSET 0 +#define CSR_VERSION_DIRTY_DIRTY_SIZE 1 +#define CSR_VERSION_MODEL_ADDR 0xe0007028L +#define CSR_VERSION_MODEL_SIZE 1 +static inline unsigned char version_model_read(void) { + unsigned char r = csr_readl(0xe0007028L); + return r; +} +#define CSR_VERSION_MODEL_MODEL_OFFSET 0 +#define CSR_VERSION_MODEL_MODEL_SIZE 8 +#define CSR_VERSION_SEED_ADDR 0xe000702cL +#define CSR_VERSION_SEED_SIZE 4 +static inline unsigned int version_seed_read(void) { + unsigned int r = csr_readl(0xe000702cL); + r <<= 8; + r |= csr_readl(0xe0007030L); + r <<= 8; + r |= csr_readl(0xe0007034L); + r <<= 8; + r |= csr_readl(0xe0007038L); + return r; +} + +/* constants */ +#define TIMER0_INTERRUPT 2 +static inline int timer0_interrupt_read(void) { + return 2; +} +#define USB_INTERRUPT 3 +static inline int usb_interrupt_read(void) { + return 3; +} +#define CONFIG_BITSTREAM_SYNC_HEADER1 2123999870 +static inline int config_bitstream_sync_header1_read(void) { + return 2123999870; +} +#define CONFIG_BITSTREAM_SYNC_HEADER2 2125109630 +static inline int config_bitstream_sync_header2_read(void) { + return 2125109630; +} +#define CONFIG_CLOCK_FREQUENCY 12000000 +static inline int config_clock_frequency_read(void) { + return 12000000; +} +#define CONFIG_CPU_RESET_ADDR 0 +static inline int config_cpu_reset_addr_read(void) { + return 0; +} +#define CONFIG_CPU_TYPE "VEXRISCV" +static inline const char * config_cpu_type_read(void) { + return "VEXRISCV"; +} +#define CONFIG_CPU_TYPE_VEXRISCV 1 +static inline int config_cpu_type_vexriscv_read(void) { + return 1; +} +#define CONFIG_CPU_VARIANT "MIN" +static inline const char * config_cpu_variant_read(void) { + return "MIN"; +} +#define CONFIG_CPU_VARIANT_MIN 1 +static inline int config_cpu_variant_min_read(void) { + return 1; +} +#define CONFIG_CSR_ALIGNMENT 32 +static inline int config_csr_alignment_read(void) { + return 32; +} +#define CONFIG_CSR_DATA_WIDTH 8 +static inline int config_csr_data_width_read(void) { + return 8; +} + +#endif diff --git a/tinyusb/hw/bsp/fomu/include/hw/common.h b/tinyusb/hw/bsp/fomu/include/hw/common.h new file mode 100755 index 00000000..6a97ca2e --- /dev/null +++ b/tinyusb/hw/bsp/fomu/include/hw/common.h @@ -0,0 +1,33 @@ +#ifndef _HW_COMMON_H_ +#define _HW_COMMON_H_ +#include +static inline void csr_writeb(uint8_t value, uint32_t addr) +{ + *((volatile uint8_t *)addr) = value; +} + +static inline uint8_t csr_readb(uint32_t addr) +{ + return *(volatile uint8_t *)addr; +} + +static inline void csr_writew(uint16_t value, uint32_t addr) +{ + *((volatile uint16_t *)addr) = value; +} + +static inline uint16_t csr_readw(uint32_t addr) +{ + return *(volatile uint16_t *)addr; +} + +static inline void csr_writel(uint32_t value, uint32_t addr) +{ + *((volatile uint32_t *)addr) = value; +} + +static inline uint32_t csr_readl(uint32_t addr) +{ + return *(volatile uint32_t *)addr; +} +#endif /* _HW_COMMON_H_ */ \ No newline at end of file diff --git a/tinyusb/hw/bsp/fomu/include/irq.h b/tinyusb/hw/bsp/fomu/include/irq.h new file mode 100755 index 00000000..a8221890 --- /dev/null +++ b/tinyusb/hw/bsp/fomu/include/irq.h @@ -0,0 +1,71 @@ +#ifndef __IRQ_H +#define __IRQ_H + +#ifdef __cplusplus +extern "C" { +#endif + + +#define CSR_MSTATUS_MIE 0x8 + +#define CSR_IRQ_MASK 0xBC0 +#define CSR_IRQ_PENDING 0xFC0 + +#define CSR_DCACHE_INFO 0xCC0 + +#define csrr(reg) ({ unsigned long __tmp; \ + asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ + __tmp; }) + +#define csrw(reg, val) ({ \ + if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ + asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ + else \ + asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) + +#define csrs(reg, bit) ({ \ + if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ + asm volatile ("csrrs x0, " #reg ", %0" :: "i"(bit)); \ + else \ + asm volatile ("csrrs x0, " #reg ", %0" :: "r"(bit)); }) + +#define csrc(reg, bit) ({ \ + if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ + asm volatile ("csrrc x0, " #reg ", %0" :: "i"(bit)); \ + else \ + asm volatile ("csrrc x0, " #reg ", %0" :: "r"(bit)); }) + +static inline unsigned int irq_getie(void) +{ + return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0; +} + +static inline void irq_setie(unsigned int ie) +{ + if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE); +} + +static inline unsigned int irq_getmask(void) +{ + unsigned int mask; + asm volatile ("csrr %0, %1" : "=r"(mask) : "i"(CSR_IRQ_MASK)); + return mask; +} + +static inline void irq_setmask(unsigned int mask) +{ + asm volatile ("csrw %0, %1" :: "i"(CSR_IRQ_MASK), "r"(mask)); +} + +static inline unsigned int irq_pending(void) +{ + unsigned int pending; + asm volatile ("csrr %0, %1" : "=r"(pending) : "i"(CSR_IRQ_PENDING)); + return pending; +} + +#ifdef __cplusplus +} +#endif + +#endif /* __IRQ_H */ \ No newline at end of file diff --git a/tinyusb/hw/bsp/fomu/output_format.ld b/tinyusb/hw/bsp/fomu/output_format.ld new file mode 100755 index 00000000..5e76f5f4 --- /dev/null +++ b/tinyusb/hw/bsp/fomu/output_format.ld @@ -0,0 +1 @@ +OUTPUT_FORMAT("elf32-littleriscv") diff --git a/tinyusb/hw/bsp/fomu/regions.ld b/tinyusb/hw/bsp/fomu/regions.ld new file mode 100755 index 00000000..51811f66 --- /dev/null +++ b/tinyusb/hw/bsp/fomu/regions.ld @@ -0,0 +1,6 @@ +MEMORY { + csr : ORIGIN = 0x60000000, LENGTH = 0x01000000 + vexriscv_debug : ORIGIN = 0xf00f0000, LENGTH = 0x00000100 + sram : ORIGIN = 0x10000000, LENGTH = 0x00020000 + rom : ORIGIN = 0x00000000, LENGTH = 0x00002000 +} -- cgit v1.2.3