From 71c2eaa3f9e7a041168c67dad35e6a94e20cb2be Mon Sep 17 00:00:00 2001 From: Joey Castillo Date: Sun, 9 Jan 2022 12:05:21 -0500 Subject: shuffle uart pins for new accelerometer board --- watch-library/watch/watch_uart.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'watch-library') diff --git a/watch-library/watch/watch_uart.c b/watch-library/watch/watch_uart.c index d35533d0..64b63bee 100644 --- a/watch-library/watch/watch_uart.c +++ b/watch-library/watch/watch_uart.c @@ -56,8 +56,8 @@ void watch_enable_debug_uart(uint32_t baud) { uint64_t br = (uint64_t)65536 * ((CONF_CPU_FREQUENCY * 4) - 16 * baud) / (CONF_CPU_FREQUENCY * 4); - gpio_set_pin_direction(D1, GPIO_DIRECTION_IN); - gpio_set_pin_function(D1, PINMUX_PB00C_SERCOM3_PAD2); + gpio_set_pin_direction(A2, GPIO_DIRECTION_OUT); + gpio_set_pin_function(A2, PINMUX_PB02C_SERCOM3_PAD0); MCLK->APBCMASK.reg |= MCLK_APBCMASK_SERCOM3; @@ -66,7 +66,7 @@ void watch_enable_debug_uart(uint32_t baud) { SERCOM3->USART.CTRLA.reg = SERCOM_USART_CTRLA_DORD | SERCOM_USART_CTRLA_MODE(1/*USART_INT_CLK*/) | - SERCOM_USART_CTRLA_RXPO(0/*PAD0*/) | SERCOM_USART_CTRLA_TXPO(1/*PAD2*/); + SERCOM_USART_CTRLA_RXPO(1/*PAD1*/) | SERCOM_USART_CTRLA_TXPO(0/*PAD0*/); SERCOM3->USART.CTRLB.reg = SERCOM_USART_CTRLB_RXEN | SERCOM_USART_CTRLB_TXEN | SERCOM_USART_CTRLB_CHSIZE(0/*8 bits*/); -- cgit v1.2.3