From fbd9ae4b67b74a9a215f8231d33e3b2f5509abd0 Mon Sep 17 00:00:00 2001 From: Joey Castillo Date: Mon, 30 Aug 2021 17:35:47 -0400 Subject: run watch at 4 MHz unless USB is enabled --- watch-library/config/hpl_oscctrl_config.h | 2 +- watch-library/config/peripheral_clk_config.h | 2 +- watch-library/hpl/core/hpl_core_m0plus_base.c | 6 ++++-- watch-library/watch/watch_private.c | 13 +++++++++++-- 4 files changed, 17 insertions(+), 6 deletions(-) (limited to 'watch-library') diff --git a/watch-library/config/hpl_oscctrl_config.h b/watch-library/config/hpl_oscctrl_config.h index 405ff207..ba2d42e6 100644 --- a/watch-library/config/hpl_oscctrl_config.h +++ b/watch-library/config/hpl_oscctrl_config.h @@ -147,7 +147,7 @@ // This defines the oscillator frequency (Mhz) // osc16m_freq #ifndef CONF_OSC16M_FSEL -#define CONF_OSC16M_FSEL OSCCTRL_OSC16MCTRL_FSEL_8_Val +#define CONF_OSC16M_FSEL OSCCTRL_OSC16MCTRL_FSEL_4_Val #endif // Oscillator Calibration Control diff --git a/watch-library/config/peripheral_clk_config.h b/watch-library/config/peripheral_clk_config.h index 5cd1bb68..61619b6a 100644 --- a/watch-library/config/peripheral_clk_config.h +++ b/watch-library/config/peripheral_clk_config.h @@ -61,7 +61,7 @@ * \brief CPU's Clock frequency */ #ifndef CONF_CPU_FREQUENCY -#define CONF_CPU_FREQUENCY 8000000 +#define CONF_CPU_FREQUENCY 4000000 #endif // RTC Clock Source diff --git a/watch-library/hpl/core/hpl_core_m0plus_base.c b/watch-library/hpl/core/hpl_core_m0plus_base.c index 1d32300a..cad2a662 100644 --- a/watch-library/hpl/core/hpl_core_m0plus_base.c +++ b/watch-library/hpl/core/hpl_core_m0plus_base.c @@ -167,7 +167,8 @@ static inline uint32_t _get_cycles_for_us_internal(const uint16_t us, const uint */ uint32_t _get_cycles_for_us(const uint16_t us) { - return _get_cycles_for_us_internal(us, CONF_CPU_FREQUENCY, CPU_FREQ_POWER); + int32_t freq = hri_usbdevice_get_CTRLA_ENABLE_bit(USB) ? 8000000 : 4000000; + return _get_cycles_for_us_internal(us, freq, CPU_FREQ_POWER); } /** @@ -196,5 +197,6 @@ static inline uint32_t _get_cycles_for_ms_internal(const uint16_t ms, const uint */ uint32_t _get_cycles_for_ms(const uint16_t ms) { - return _get_cycles_for_ms_internal(ms, CONF_CPU_FREQUENCY, CPU_FREQ_POWER); + int32_t freq = hri_usbdevice_get_CTRLA_ENABLE_bit(USB) ? 8000000 : 4000000; + return _get_cycles_for_ms_internal(ms, freq, CPU_FREQ_POWER); } diff --git a/watch-library/watch/watch_private.c b/watch-library/watch/watch_private.c index a4e2f72c..88d80be9 100644 --- a/watch-library/watch/watch_private.c +++ b/watch-library/watch/watch_private.c @@ -54,8 +54,14 @@ void _watch_enable_tcc() { hri_tcc_wait_for_sync(TCC0, TCC_SYNCBUSY_ENABLE); hri_tcc_write_CTRLA_reg(TCC0, TCC_CTRLA_SWRST); hri_tcc_wait_for_sync(TCC0, TCC_SYNCBUSY_SWRST); - // have prescaler divide our 8 MHz clock down to 1 MHz. - hri_tcc_write_CTRLA_reg(TCC0, TCC_CTRLA_PRESCALER_DIV8); + // divide the clock down to 1 MHz + if (hri_usbdevice_get_CTRLA_ENABLE_bit(USB)) { + // if USB is enabled, we are running an 8 MHz clock. + hri_tcc_write_CTRLA_reg(TCC0, TCC_CTRLA_PRESCALER_DIV8); + } else { + // otherwise it's 4 Mhz. + hri_tcc_write_CTRLA_reg(TCC0, TCC_CTRLA_PRESCALER_DIV4); + } // We're going to use normal PWM mode, which means period is controlled by PER, and duty cycle is controlled by // each compare channel's value: // * Buzzer tones are set by setting PER to the desired period for a given frequency, and CC[1] to half of that @@ -98,6 +104,9 @@ void _watch_enable_usb() { // disable USB, just in case. hri_usb_clear_CTRLA_ENABLE_bit(USB); + // bump clock up to 8 MHz + hri_oscctrl_write_OSC16MCTRL_FSEL_bf(OSCCTRL, OSCCTRL_OSC16MCTRL_FSEL_8_Val); + // reset flags and disable DFLL OSCCTRL->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRDY; OSCCTRL->DFLLCTRL.reg = 0; -- cgit v1.2.3